Toshiba A30 Schematics

0 (0)

COMPAL CONFIDENTIAL

MODEL NAME : Sapporo XA

COMPAL P/N : DFL10

PCB NO : LA-2051

Revision : 1.0

Sapporo XA Schematics Document	2

uFCBGA/uFCPGA NorthWood MT

2003 11 07 v1.0

Compal Electronics, Inc.

Title

Cover Sheet

THISSHEETOFENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

Size

Document Number

R ev

ANDTRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

LA-2051

1.0

DEPARTMENTEXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAYBEUSEDBYORDISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Friday, November 14, 2003

Sheet

o f

Compal confidential

Block Diagram

Model : DFL10

LA-2051

Fan Control 1

NorthWood-MT -- 533

Prescott-MT -- 533

Thermal Sensor

+12VALW

page 37

Celeron-MT -- 400

Clock Generator

+5VALW

CPU Bypass

+1.2VP

uFCPGA CPU 478pin

ADM1032AR

ICS951402AGT

Fan Control 2

page 6

+CPU_CORE

page 4,5,6

+5VS

page 6

+3VS

page 16

+12VALW

page 37

System Bus

+5VALW

HA#(3..31)

HD#(0..63)

400/533 MHz

TV OUT Connector

Memory

DDR-DIMM X2

BUS(DDR)

+2.5V 333MHz

BANK 0, 1, 2, 3

+3VS

page 17

ATI RC300ML

+1.5VS

+2.5V

page 13,14,15

CRT Connector

CRT Signal

+2.5V

718 pin u-BGA

+1.25VS

+5VS

page 18

+3VS

+CPU_CORE

page 7,8,9,10,11,12

LVDS Connector

LVDS Signal

B+

page 18

USB2.0 CTRL.

A LINK

NEC uPD720101

+1.5VS

page 24

66MHz

PCI BUS

+3VS

USB 2.0/1.1

USB Ports X3

+3VS 33MHz

48MHz

( X1 reserve )

+3VALW

IDSEL:AD18

IDSEL:AD19

IDSEL:AD20

IDSEL:AD16

+1.5VS

ATI IXP150

+5V

page 27

PIRQC#

PIRQD#

PIRQB#

PIRQA#

+1.5VALW

24.576MHz

AC-LINK

CardBus

IEEE 1394

457 BGA

Minipci CONN

LAN

+CPU_CORE

ATA100

RTL8101L

CB1410

TSB43AB21

VCC5REF

MDC

WIRELESS & Dubug

VCC5REFSUS

page 26,27,28,29

+3V

+5VS

+3VS

page 25

+2.5VLAN page 22

+3VS

page 20

+3VS

page 19

+3VS

+5VS

LPC BUS

+3VS

+3V page 23

RJ45

PWR Controller & Slot

1394 Conn.

33MHz

IDE HDD

IDE ODD

AC97 Codec

Cable

+12VALW

+5VALW

page 19

ALC202A

RJ11

page 23

+3VALW

page 21

+5VS

+5VCD

Super I/O

Embedded Controller

+5VALW

-> +VDDA

page 30

+3VS

page32

Cable

SW Board Conn

LPC47N217

NS PC87591L

SIDE IRQ14

PIDE IRQ15

On/Off BTN &

+3VS

page 34

+3VS

page 31

AMP TPA0232

+5VALW

page 37

+3VALW

User Keys

RTC Batt.

+5VALW

page 33

MIC Phone

+3VALW

page 37

EC DEBUG & Int. KB

page 37

Parallel

+5VDDA

page 33

+3VALW

page 31

Power Circuit

DC/DC Interface

+5VS

page 34

LINE IN

BIOS & Ext. IO

DC/DC

Suspend

+3VALW

page 32

HeadPhone

+5VDDA

page 40

page 36

Debug COM Port

+5VALW

INT. Speaker

+AUD_VREF

+5V

page 34

LID SW & Kill SW

page 33

+3VALW

page 31

FIR

Touch Pad

+5VS

page 31

+3VS

page 34

LID Hibernation

Compal Electronics, Inc.

+5VALW

+RTC_VREF

Title

Block Diagram

page 39

Size

Document Number

R ev

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

LA-2051

1.0

THIS SHEET OF ENGINEERINGDRAWINGIS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALDate:

Friday, November 14, 2003

Sheet

o f

A	B	C	D	E
		DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
		MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Voltage Rails

Power Managment table

+3VALW

+5V

+2.5VS

Power Plane

Description

S0-S1

Signal

+1.8VS

+5VALW

+3V

VIN

Adapter power supply (19V)

N/A

+5VS

+12VALW

+2.5V

B+

AC or battery power rail for power circuit.

N/A

+3VS

+CPU_CORE

Core voltage for CPU

OFF

+1.5VS

+CPU_CORE

+1.2V

The voltage for Processor VID select

OFF

State

+1.25VS

1.25V switched power rail for DDR Vtt

OFF

+1.5VS

1.5V I/O power rail for ATI-RS300M/RC300M NB AGP.

OFF

+1.8VS

1.8V switched power rail for ATI-RS300M/RC300M NB.

OFF

+2.5VALW

2.5V always on power rail

ON*

+2.5V

2.5V system power rail for DDR

OFF

+2.5VS

2.5V switched power rail

OFF

+3VALW

3.3V always on power rail

ON*

OFF

+3V

3.3V system power rail for SB,LAN,CardReader and HUB.

OFF

+3VS

3.3V switched power rail

OFF

S5 S4/AC

OFF

+5VALW

5V always on power rail

ON*

+5V

5V system power rail .

OFF

S5 S4/AC don't exist

OFF

+5VS

5V switched power rail

OFF

+12VALW

12V always on power rail

ON*

RTCVCC

RTC power

Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.

SKU ID Table for AD channel

External PCI Devices

Vcc

3.3V +/- 5%

100K +/- 5%

SKU ID

VAD_BID min

VAD_BID typ

VAD_BID max

DEVICE

IDSEL #

REQ/GNT #

PIRQ

0 V

NB Internal VGA

N/A

8.2K +/- 5%

0.216 V

0.250 V

0.289 V

18K +/- 5%

0.436 V

0.503 V

0.538 V

AGP BUS

AGP_DEVSEL

N/A

SOUTHBRIDGE

AD31 (INT.)

N/A

33K +/- 5%

0.712 V

0.819 V

0.875 V

56K +/- 5%

1.036 V

1.185 V

1.264 V

USB

AD30 (INT.)

N/A

100K +/- 5%

1.453 V

1.650 V

1.759 V

AC97

AD31 (INT.)

N/A

200K +/- 5%

1.935 V

2.200 V

2.341 V

ATA 100

AD31 (INT.)

N/A

2.500 V

3.300 V

ETHERNET

AD24(INT.)

N/A

1394

AD16

L AN

AD19

CARD BUS

AD20

BOARD ID

Wireless LAN(MINI PCI) AD18

Sku ID

CD PLAY FUNCTION

Short cut key

Version

BID1

BID0

EXT USB

AD23(EXT.)

A,C,D

YES

EC SM Bus1 address

EC SM Bus2 address

YES

Device

Address

Device

Address

YES

Smart Battery

0001 011X b

ADM1032

1001 100X b

EEPROM(24C16)

1010 000X b

I2C / SMBUS ADDRESSING

DEVICE

HEX

ADDRESS

Compal Electronics, Inc.

DDR SO-DIMM 0

1 0 1 0 0 0 0 X

Title

Note & Revision

DDR SO-DIMM 1

1 0 1 0 0 0 1 X

THISSHEETOFENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

Size

Document Number

R ev

CLOCK GENERATOR (EXT.)

1 1 0 1 0 0 1 X

ANDTRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

LA-2051

1.0

DEPARTMENTEXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAYBEUSEDBYORDISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Tuesday, November 18, 2003

Sheet 3 o f

+CPU_CORE

A10

A12

A14

A16

A18

A20

AA10

AA12

AA14

AA16

AA18

AA8

AB11

AB13

AB15

AB17

AB19

AB7

AB9

AC10

AC12

AC14

AC16

AC18

AC8

AD11

AD13

AD15

AD17

AD19

AD7

AD9

AE10

AE12

AE14

AE16

AE18

AE20

AE6

AE8

AF11

AF13

AF15

AF17

AF19

AF2

AF21

AF5

AF7

AF9

B11

B13

B15

B17

B19

C10

C12

C14

C16

C18

C20

D11

D13

D15

D17

D19

E10

JCPU1A

HA#[3..31]

HA#3

VCC_0 VCC_1 VCC_2 VCC_3 VCC_4 VCC_5

VCC_6 VCC_7 VCC_8 VCC_9 _VCC10

_VCC11 _VCC12

_VCC13

_VCC14 _VCC15

_VCC16 _VCC17

_VCC18

_VCC19 _VCC20

_VCC21 _VCC22

_VCC23

_VCC24 _VCC25

_VCC26 _VCC27

_VCC28

_VCC29 _VCC30

_VCC31 _VCC32

_VCC33 _VCC34 _VCC35 _VCC36 _VCC37 _VCC38 _VCC39 _VCC40 _VCC41 _VCC42 _VCC43 _VCC44 _VCC45

_VCC46 _VCC47 _VCC48 _VCC49 _VCC50

_VCC51 _VCC52

_VCC53

_VCC54 _VCC55

_VCC56 _VCC57

_VCC58 _VCC59 _VCC61 _VCC62 _VCC63 _VCC64 _VCC65 _VCC66 _VCC67 _VCC68 _VCC69

_VCC70 _VCC71 _VCC72 _VCC73

B21

HD#0

HD#[0..63]

A#3

D#0

HA#4

B22

HD#1

HA#5

A#4

D#1

A23

HD#2

HA#8

A#5

POWER

D#2

D22

HD#5

A#7

D#4

HA#6

A#6

D#3

A25

HD#3

HA#7

C21

HD#4

A#8

D#5

HA#9

A#9

D#6

B24

HD#6

HA#10

C23

HD#7

HA#11

A#10

D#7

C24

HD#8

HA#12

A#11

D#8

B25

HD#9

HA#13

A#12

D#9

G22

HD#10

HA#14

A#13

D#10

H21

HD#11

HA#15

A#14

D#11

C26

HD#12

HA#16

A#15

D#12

D23

HD#13

HA#17

A#16

D#13

J21

HD#14

HA#18

A#17

D#14

D25

HD#15

HA#19

A#18

D#15

H22

HD#16

HA#20

A#19

HOST

D#16

E24

HD#17

HA#21

A#20

D#17

G23

HD#18

HA#22

A#21

D#18

F23

HD#19

HA#24

A#23

ADDR

D#20

E25

HD#21

HA#23

A#22

D#19

F24

HD#20

A#24

D#21

HA#25

F26

HD#22

HA#26

A#25

D#22

D26

HD#23

HA#27

A#26

D#23

L21

HD#24

HA#28

A#27

D#24

G26

HD#25

HA#29

A#28

D#25

H24

HD#26

HA#30

A#29

Northwood-MT

D#26

M21

HD#27

HA#31

A#30

D#27

L22

HD#28

A#34

D#31

H25

HD#31

A#31

D#28

J24

HD#29

AB1

A#32

HOST

D#29

M23

HD#32

A#33

Prescott-MT

D#30

K23

HD#30

H_REQ#0

ADDR

REQ#0

D#35

M24

HD#35

H_REQ#[0..4]

A#35

D#32

N22

HD#33

D#33

P21

HD#34

D#34

H_REQ#1

REQ#1

D#36

N23

HD#36

H_REQ#2

M26

HD#37

H_REQ#3

REQ#2

D#37

N26

HD#38

H_REQ#4

REQ#3

D#38

N25

HD#39

H_ADS#

REQ#4

D#39

R21

HD#40

ADS#

D#40

P24

HD#41

D#41

R25

HD#42

+CPU_CORE

AA3

AP#1

CONTROL

D#42

T25

HD#45

D#44

AC1

AP#0

D#43

R24

HD#43

T26

HD#44

BINIT#

D#45

56_0402_5%

AC3

IERR#

D#46

T22

HD#46

T23

HD#47

+CPU_CORE

R36 1

2 51_0402_5%

D#47

U26

HD#48

D#48

U24

HD#49

H_BREQ0#

BR0#

D#49

U23

HD#50

H_BPRI#

BPRI#

D#50

V25

HD#51

H_BNR#

BNR#

D#51

U21

HD#52

H_LOCK#

LOCK#

D#52

V22

HD#53

CLK

D#53

V24

HD#54

16 CLK_CPU_BCLK

CLK_CPU_BCLK

AF22

D#54

W26

HD#55

CLK_CPU_BCLK#

AF23

BCLK0

D#55

Y26

HD#56

16 CLK_CPU_BCLK#

BCLK1

D#56

W25

HD#57

CON

D#57

Y23

HD#58

D#58

Y24

HD#59

GND

POWER

D#59

TROL

D#61

AA22

HD#62

H_HIT#

HIT#

D#60

Y21

HD#60

H_HITM#

HITM#

BOOTSELECT

AA25

HD#61

_0VSS _1VSS _2VSS _3VSS

_4VSS _5VSS _6VSS _7VSS _8VSS

_9VSS _10VSS

_11VSS

_12VSS _13VSS

_14VSS _15VSS

_16VSS

_17VSS _18VSS

_19VSS _20VSS

_21VSS

_22VSS _23VSS

_24VSS _25VSS

_26VSS

_27VSS _28VSS

_29VSS _30VSS

_31VSS _32VSS _33VSS _34VSS _35VSS _36VSS _37VSS _38VSS _39VSS _40VSS _41VSS _42VSS _43VSS

_44VSS _45VSS _46VSS _47VSS _48VSS

_49VSS _50VSS

_51VSS

_52VSS _53VSS

_54VSS _55VSS

_81VCC _82VCC _83VCC _84VCC _85VCC _80VCC _79VCC _78VCC

_77VCC _76VCC _75VCC _74VCC

H_DEFER#

DEFER#

D#62

AA24

HD#63

D#63

FOX_PZ47803-274A-42_Prescott

H23

H26

A11

A13

A15

A17

A19

A21

A24

A26

AA1

AA11

AA13

AA15

AA17

AA19

AA23

AA26

AA4

AA7

AA9

AB10

AB12

AB14

AB16

AB18

AB20

AB21

AB24

AB3

AB6

AB8

AC11

AC13

AC15

AC17

AC19

AC2

AC22

AC25

AC5

AC7

AC9

AD10

AD12

AD14

AD16

AD18

AD21

AD23

AD4

AD8

AD1

F13

F15

F17

F19

F11

E20

E18

E16

E14

E12

+CPU_CORE

BOOTSELECT

0_0402_5%

Compal Electronics, Inc.

Title

Prescott / P4 uFCPGA (1/2)

THISSHEETOFENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

Size

Document Number

R ev

ANDTRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

LA-2051

1.0

DEPARTMENTEXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

Custom

Date:

Friday, November 14, 2003

Sheet

o f

GND

H_SKTOCC#

AE11 AE13 AE15 AE17 AE19 AE22 AE24 AE7 AE9 AF1 AF10 AF12 AF14 AF16 AF18 AF20 AF6 AF8 B10 B12 B14 B16 B18 B20 B23 B26 B4 B8 C11 C13 C15 C17 C19 C2 C22 C25 C5 C7 C9 D10 D12 D14 D16 D18 D20 D21 D24 D3 D6 D8 E1 E11 E13 E15 E17 E19 E23 E26 E4 E7 E9 F10 F12 F14 F16 F18 F2 F22 F25 F5

AF26

R403

H_GHI#

CPU_GHI# 27

@33_0402_5%

R42

JCPU1B

0_0402_5%

VSS57 VSS58

VSS59 VSS60 VSS61 VSS62 VSS63 VSS65

VSS66

VSS67

VSS68

VSS69

VSS70

VSS71

VSS72

VSS73

VSS75

VSS76

VSS77

VSS78

VSS79

VSS80

VSS81

VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90 VSS91 VSS92 VSS93 VSS94

VSS95 VSS96 VSS97 VSS98 VSS99 VSS100

VSS101

VSS102 VSS103

VSS104 VSS105 VSS106 VSS107

VSS108

VSS109

VSS110

VSS111 VSS112 VSS113

VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120

VSS121

VSS122 VSS123

VSS124

VSS125

VSS126 VSS127 VSS128

SKTOCC#

+CPU_CORE

H_RS#[0..2]

+H_GTLREF

H_RS#0

J26

RS#0

DP#0

C47

2ITP_BPM#0

H_RS#1

K25

RS#1

GROUND

DP#1

R59

51_0402_5%

H_TRDY#

K26

220P_0603_50V8J

RSP#

DP#3

R56

51_0402_5%

H_RS#2

RS#2

DP#2

2ITP_BPM#1

AB2

CON

L25

2ITP_BPM#2

H_TRDY#

TRDY#

GTLREF0

AA21

R47

51_0402_5%

H_A20M#

AA6

R46

51_0402_5%

TROL

GTLREF2

2ITP_BPM#3

REF

GTLREF1

F20

R55

51_0402_5%

H_FERR#

H_I GNNE#

FERR#

AE26

+CPU_CORE

2ITP_BPM#4

H_A20M#

H_FERR#

A20M#

GTLREF3

R404 R_G

0_0402_5%

2ITP_BPM#5

H_IGNNE#

H_SMI#

IGNNE#

OPTIMIZED/COMPAT#

R57

51_0402_5%

H_SMI#

H_PWRGD

AB23

SMI#

H_PWRGD

PWRGOOD

H_STPCLK#

AD24

H_STPCLK#

STPCLK#

TESTHI0

AA2

R408

56_0402_5%

LEGACY

TESTHI1

H_NMI

H_INIT#

LINT1

AC24

TESTHI3

H_INTR

LINT0

TESTHI2

AC21

H_NMI

AC20

R409

56_0402_5%

+CPU_CORE

H_INIT#

H_RESET#

AB25

INIT#

TESTHI4

AC23

7,26

H_RESET#

RESET#

TESTHI5

R58

56_0402_5%

AA20

ITP

TESTHI6

H_DBSY#

H_DRD Y#

DBSY#

R45

56_0402_5%

TESTHI8

H_D BSY#

TESTHI7

AB22

R60

56_0402_5%

MISC

R38

56_0402_5%

150_0402_5%

12,16

BSEL0

TESTHI10

H_GHI#

BSEL1

AD5

R35

300_0402_5%

1 ITP_TDI

H_DRDY#

BSEL0

AD6

DRDY#

TESTHI9

R39

56_0402_5%

12,16

BSEL1

TESTHI11

AD25 H_DPSLPR#

R405

56_0402_5%

1ITP_TMS

Northwood-MT

TESTHI12

THER

R51

39.2_0603_1%

H_THERMDA

H_DSTBN#[0..3]

H_DSTBN#[0..3] 7

2ITP_TDO

6 H_THERMDC

H_THERMDC

THERMDC

DSTBN#1

E22

H_DSTBN#0

H_THERMDA

H_THERMTRIP#

THERMTRIP#

K22

H_DSTBN#1

THERMDA

MAL

1ITP_TRST#

ITP_BPM#1

AB5

BPM#0

Prescott-MT

DSTBN#0

H_DSTBP#[0..3] 7

R586

75_0402_5%

H_THERMTRIP#

DSTBN#2

R22

H_DSTBN#2

W22

H_DSTBN#3

ITP_BPM#0

AC6

DATA

DSTBN#3

H_DSTBP#[0..3]

R43

680_0402_5%

ITP_BPM#2

AC4

BPM#1

MISC

DSTBP#1

F21

H_DSTBP#0

ITP_BPM#4

AA5

BPM#3

P23

H_DSTBP#2

ITP_BPM#3

BPM#2

DSTBP#0

J23

H_DSTBP#1

1ITP_TCK

ITP_BPM#5

AB4

BPM#4

DSTBP#2

W23

H_DSTBP#3

H_ADSTB#0 7

BPM#5

DSTBP#3

R52

27.4_0603_1%

ITP_TDO

TDI

ADDR

ADSTB#1

H_ADSTB#0

H_DBI#[0..3]

H_ADSTB#1 7

ITP_TCK

TCK

ITP

ADSTB#0

ITP_TDI

H_ADSTB#1

ITP_TMS

TDO

H_DBI#[0..3] 7

+CPU_CORE

ITP_TRST#

TMS

DBI#0

E21

H_DBI#0

L27

TRST#

G25

H_DBI#1

DATA

DBI#1

VCCIOPLL

AE23

VCCA

V21

H_DBI#2

DBI#3

AD20

VCCIOPLL

DBI#2

P26

LQG21F4R7N00_0805

VCCA

MISC

H_DBI#3

LQG21F4R7N00_0805

VCCSENSE

DBR#

AE25

R410

150_0402_5%

+3VALW

L26

VSSSENSE

+CPU_CORE

VSSSENSE 1

AF3

VSSSENSE

R10

100K_0402_1%

C423

C422

+1.2V

R587

0_0402_5%

VCCVIDLB

MISC

PROCHOT#

H_PROCHOT#

H_PROCHOT# 26,46

@33U_D2_8M_R35

33U_D2_8M_R35

AD22

VSSA

ITP

MCERR#

AB26

H_SLP#

SLP#

16 CLK_CPU_ITP

AC26

ITP_CLK0

GROUND

MISC

NC1

A22

L24

ITP_CLK1 CLK

NC3

AF24

16 CLK_CPU_ITP#

AD26

NC2

AF25

Comp0/1 need keep 25

COMP0

VIDPWRGD

NC4

AE21

R96

51.1_0603_1%

COMP1

129VSS 130VSS

131VSS 132VSS 133VSS 134VSS 135VSS 136VSS

137VSS

138VSS

139VSS

140VSS

141VSS

142VSS

143VSS

144VSS

145VSS

146VSS

147VSS

148VSS

149VSS

150VSS

151VSS

152VSS 153VSS 154VSS 155VSS 156VSS 157VSS 158VSS 159VSS 160VSS 161VSS 162VSS 163VSS 164VSS

165VSS 166VSS 167VSS 168VSS 169VSS 170VSS

171VSS

172VSS 173VSS

174VSS 175VSS 176VSS 177VSS

178VSS

179VSS

180VSS

181VSS

VID0 VID1 VID2 VID3 VID4 VID5

VCCVID

NC5

GTL Reference Voltage

mils trace width

R11

51.1_0603_1%

Layout note :

COMP1

If CPU is P4 , Change the

G21 G24 G3 G6 J2 J22 J25 J5 K21 K24 K3 K6 L1 L23 L26 L4 M2 M22 M25 M5 N21 N24 N3 N6 P2 P22 P25

P5 R1 R23 R26 R4 T21 T24 T3 T6 U2 U22 U25 U5 V1 V23 V26 V4 W21 W24 W3 W6 Y2 Y22 Y25 Y5

AE5 AE4 AE3 AE2 AE1 AD3

AD2

AF4

1. Place R_A and R_B near CPU (Within 1.5").

+CPU_CORE

+1.2V

resistor R53 9,R540 value to

5 1.1_0603_1%,or prescott

VID0 VID1 VID2 VID3 VID4 VID5

+CPU_CORE

Place near SB200

6 1 .9 _ 0603_1%

+3VS

_ _ _ _ _ _

R560

56_0402_5%

Reserve

CPU CPU CPU CPU CPU CPU

Pop: Prescott

H_FERR#

10K_1206_8P4R_5%

0.1U_0402_10V6K

R74

RP1

Depop: Northwood

49.9_0603_1%

FOX_PZ47803-274A-42_Prescott

for

EMI.

R12

Near

CPU.

@2.43K_0603_1%

Place near CPU

+1.2V

+H_GTLREF

+3VS

2 10K_0402_5%

56_0402_5%

10K_0402_5%

R67

C50

H_THERMTRIP#

H_VID_PWRGD 38

CPU_VID[0..5]

100_0603_1%

1U_0603_6.3V6M

R66

56_0402_5%

H_RESET#

4.7K_0402_5%

H_DPSLPR#

H_PWRGD

R64

300_0402_5%

MMBT3904_SOT23

Compal Electronics, Inc.

MMBT3904_SOT23

10,16,26,47 PM_STPCPU#

4.7K_0402_5%

Title

Prescott / P4 uFCPGA & Thermal sensor (2/2)

THISSHEETOFENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

Size

Document Number

R ev

ANDTRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

LA-2051

1.0

DEPARTMENTEXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

Custom

Date:

Friday, November 14, 2003

Sheet

o f

Layout note :

Place close to CPU, Use 2~3 vias per PAD.

Place 22uF caps x31 pcs, populated 14pcs.

+CPU_CORE

Place

CPU inside

C396

C388

C383

C379

C397

C389

22U_1206_6.3V6M

+CPU_CORE

C384

C380

C398

C390

C385

C381

22U_1206_6.3V6M

+CPU_CORE

Please place these cap on the socket north side

C409

C408

C418

C410

C411

22U_1206_6.3V6M

2 22U_1206_6.3V6M

22U_1206_6.3V6M

2 22U_1206_6.3V6M

+CPU_CORE

C412

C413

C414

C415

C416

C417

22U_1206_6.3V6M

+CPU_CORE

Please place these cap on the socket sourth side

C21

C22

C23

C19

C72

C73

22U_1206_6.3V6M

+CPU_CORE

C74

C75

C20

22U_1206_6.3V6M

+CPU_CORE

Layout note :

Place close to CPU power and

C382

C392

C401

C404

ground pin as possible

@470U_D2_2.5VM

470U_D4_2.5VM

(<1inch)

+CPU_CORE

For Desktop's CPU:

470uFx15/12mOhm H=1.8 each

Total 0.923m ohm

C407

C419

C30

C33

C36

470U_D4_2.5VM

+CPU_CORE

C40

C48

C58

C65

470U_D4_2.5VM

+CPU_CORE


	1	C82	1	C81	1	C80	1	C18	1	C17	1	C16

	@0.22U_0603_10V7K		@0.22U_0603_10V7K		@0.22U_0603_10V7K		@0.22U_0603_10V7K		@0.22U_0603_10V7K		@0.22U_0603_10V7K
	2		2		2		2		2		2

+CPU_CORE

1 300_0402_5%

C2 2

1 @1U_0603_10V6K

2SC2411K_SC59

H_THERMTRIP#

5 H_THERMTRIP#

MAINPWON 41,42,44

CPU Temperature Sensor

+3VS

R63

+3VS_VDD

5 H_THERMDA

H_THERMDA

200_0402_5%

C42

C39

2 0.1U_0402_10V6K

2200P_0402_50V7K

D+

VDD1

5 H_THERMDC

H_THERMDC

D-

ALERT#

EC_SMC2

SCLK

THERM#

EC_SMD2

SDATA

GND

ADM1032ARM_RM8

R54

10K_0402_5% 2

THIS SHEET OF ENGINEERINGDRAWINGIS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

	Compal Electronics, Inc.
Title	CPU Decoupling CAP.
	CPU Decoupling CAP.

Size	Document Number			R ev
Custom	LA-2051			1.0
Custom	LA-2051
Date:	Friday, November 14, 2003	Sheet 6 o f	51

HA#[3..31]

HA#[3..31] 4

H_REQ#[0..4]

HD#[0..63]

HD#[0..63] 4

HA#3

M28

U24A

L30

HD#0

CPU_A3#

CPU_D0#

HA#4

P25

K29

HD#1

CPU_A4#

CPU_D1#

HA#5

M25

J29

HD#2

CPU_A5#

CPU_D2#

HA#6

N29

H28

HD#3

HA#7

N30

CPU_A6#

CPU_D3#

K28

HD#4

CPU_A7#

CPU_D4#

HA#8

M26

K30

HD#5

HA#9

N28

CPU_A8#

PART1 OF

GROUP0

CPU_D5#

H29

HD#6

CPU_A9#

CPU_D6#

HA#10

P29

J28

HD#7

HA#12

R29

CPU_A12#

CPU_D9#

H30

HD#9

HA#11

P26

CPU_A10#

CPU_D7#

F28

HD#8

CPU_A11#

CPU_D8#

HA#13

P30

CPU_A13#

DATA

CPU_D10#

E30

HD#10

H_REQ#1

N25

CPU_REQ0#

GROUP0

CPU_D14#

F29

HD#15

HA#14

P28

CPU_A14#

CPU_D11#

D29

HD#11

HA#15

N26

CPU_A15#

CPU_D12#

G28

HD#12

HA#16

N27

E29

HD#13

CPU_A16#

CPU_D13#

H_REQ#0

M29

D30

HD#14

CPU_REQ1#

ADDR.

CPU_D15#

H_REQ#2

R26

E28

H_DBI#0

H_REQ#4

L29

CPU_REQ3#

CPU_DSTBN0#

G29

H_DSTBP#0

H_DSTBN#0 5

H_REQ#3

L28

CPU_REQ2#

CPU_DBI0#

G30

H_DSTBN#0

H_DBI#0

CPU_REQ4#

CPU_DSTBP0#

H_DSTBP#0 5

H_ADSTB#0

R27

CPU_ADSTB0#

B26

HD#16

CPU_D16#

HA#17

U30

C30

HD#17

CPU_A17#

CPU_D17#

HA#18

T30

A27

HD#18

CPU_A18#

CPU_D18#

HA#19

R28

B29

HD#19

CPU_A19#

CPU_D19#

HA#20

R25

C28

HD#20

CPU_A20#

CPU_D20#

HA#21

U25

C29

HD#21

CPU_A21#

CPU_D21#

HA#22

T28

GROUP

B28

HD#22

HA#24

T26

CPU_A24#

CPU_D24#

D26

HD#24

HA#23

V29

CPU_A22#

CPU_D22#

D28

HD#23

CPU_A23#

CPU_D23#

HA#25

U29

CPU_A25#

I/F

DATA

CPU_D25#

B27

HD#25

HA#30

U27

CPU_A29#

GROUP1

CPU_D29#

B25

HD#30

HA#26

U26

CPU_A26#

CPU_D26#

C26

HD#26

HA#27

V26

CPU_A27#

CPU_D27#

E25

HD#27

HA#28

T25

E26

HD#28

HA#29

V25

CPU_A28#

PENTIUMAGTL+

CPU_D28#

A26

HD#29

H_TRDY#

H_HIT#

J26

CPU_TRDY#

CONTROL

IV2GROUPDATA

CPU_D44#

C21

HD#45

HA#31

U28

CPU_A30#

CPU_D30#

C25

HD#31

H_ADSTB#1

CPU_ADSTB1# ADDR.

CPU_DBI1#

D27

H_DSTBN#1

H_DBI#1

H_ADSTB#1

T29

CPU_A31#

CPU_D31#

A28

H_DBI#1

H_ADS#

L27

CPU_DSTBN1#

E27

H_DSTBP#1

H_DSTBN#1 5

H_ADS#

H_BNR#

K25

CPU_ADS#

CPU_DSTBP1#

H_DSTBP#1 5

H_BNR#

H_BPRI#

H26

CPU_BNR#

F24

HD#32

H_BPRI#

H_DEFER#

J27

CPU_BPRI#

CPU_D32#

D24

HD#33

H_DEFER#

H_DRDY#

L26

CPU_DEFER#

CPU_D33#

E23

HD#34

H_DRDY#

H_DBSY#

G27

CPU_DRDY#

CPU_D34#

E24

HD#35

H_DBSY#

H_BREQ0#

F25

CPU_DBSY#

CPU_D35#

F23

HD#36

H_BREQ0#

CPU_BR0#

CPU_D36#

H_LOCK#

K26

C24

HD#37

H_LOCK#

CPU_LOCK#

CPU_D37#

B24

HD#38

5,26

H_RESET#

A17

CPU_D38#

A24

HD#39

CPU_CPURSET#

CPU_D39#

H_RS#2

G25

F21

HD#40

H_RS#2

H_RS#1

G26

CPU_RS2#

CPU_D40#

A23

HD#41

H_RS#1

CPU_RS1#

CPU_D41#

0.1U_0402_10V6K

H_RS#0

J25

B23

HD#42

C590

H_RS#0

CPU_RS0#

CPU_D42#

C22

HD#43

CPU_D43#

H_TRDY#

F26

B22

HD#44

H_HIT#

CPU_HIT#

CPU_D45#

--> 412_0402_1%

H_HITM#

H25

E21

HD#46

H_HITM#

CPU_HITM#

CPU_D46#

R485

D22

HD#47

CPU_D47#

D23

H_DBI#2

Note: PLACE CLOSE TO RC300M,

AH5

CPU_RSET

CPU_DBI2#

E22

H_DSTBN#2

_5%

SUS_STAT#

CPU_DSTBN2#

H_DSTBN#2 5

AG5

F22

H_DSTBP#2

USE 10/10 WIDTH/SPACE

330_040226,30,34,35 NB_RST#

SYSRESET#

CPU_DSTBP2#

H_DSTBP#2 5

NB_PW RGD

POWERGOOD

B21

HD#48

+CPU_CORE

24.9_0402_1% COMP_N

CPU_D48#

R437

V28

+CPU_CORE

F20

HD#49

PLACE CLOSE TO U27 Ball

CPU_COMP_N

CPU_D49#

A21

HD#50

CPU_D50#

W28, USE 20/20

R436

49.9_0402_1% COMP_P

W29

CPU_COMP_P

CPU_D51#

C20

HD#51

L31

E20

HD#52

R428

WIDTH/SPACE

CPVDD

H23

CPU_D52#

+1.8VS

D20

HD#53

CPVDD

CPU_D53#

HB-1M2012-121JT03_0805

1U_0603_10V6K

A20

HD#54

CPU_D54#

49.9_0603_1%

2CPVSS

J23

GROUP

D19

HD#55

NB_GTLREF

W28

CPU_VREF

CPU_D57#

B20

HD#57

C492

CPVSS

CPU_D55#

C18

HD#56

CPU_D56#

MISC.

DATA

CPU_D58#

E18

HD#58

Y28

B18

HD#61

R429

1 C433

1 C441

CPU_D59#

B19

HD#59

Y29

D18

HD#60

THERMALDIODE_N

CPU_D60#

THERMALDIODE_P

CPU_D61#

100_0603_1%

2 1U_0603_10V6K

2 220P_0402_50V8K

CPU_D62#

C17

HD#62

CPU_D63#

A18

HD#63

B17

TESTMODE

CPU_DBI3#

F19

H_DBI#3

C441 CLOSE

CPU_DSTBN3#

E19

H_DSTBN#3

H_DSTBN#3 5

TO Ball W28

R469

CPU_DSTBP3#

F18

H_DSTBP#3

H_DSTBP#3 5

4.7K_0402_5%

CHS-216IGP9050A21_BGA718

+CPU_CORE

0.1U_0402_10V6K

C486

C541

C525

C490

C466

C465

C464

C463

1 C507

22U_1206_16V4Z_V1

2 0.1U_0402_10V6K

0.1U_0402_10V6K

Compal Electronics, Inc.

Title

ATI RC300M-AGTL+

THIS SHEET OF ENGINEERINGDRAWINGIS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

Size

Document Number

R ev

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

LA-2051

1.0

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Friday, November 14, 2003

Sheet

o f

U24B

DDR_SMA0

AH19

MEM_A0 PART2 OF 6

MEM_DQ0

AG6

DDR_DQ0

DDR_SMA1

AJ17

MEM_A1

MEM_DQ1

AJ7

DDR_DQ1

DDR_SMA2

AK17

AJ9

DDR_DQ2

MEM_A2

MEM_DQ2

DDR_SMA3

AH16

AJ10

DDR_DQ3

MEM_A3

MEM_DQ3

DDR_SMA4

AK16

AJ6

DDR_DQ4

MEM_A4

MEM_DQ4

DDR_SMA5

AF17

AH6

DDR_DQ5

MEM_A5

MEM_DQ5

DDR_SMA6

AE18

AH8

DDR_DQ6

MEM_A6

MEM_DQ6

DDR_SMA7

AF16

AH9

DDR_DQ7

MEM_A7

MEM_DQ7

DDR_SMA8

AE17

AE7

DDR_DQ8

MEM_A8

MEM_DQ8

DDR_SMA9

AE16

AE8

DDR_DQ9

MEM_A9

MEM_DQ9

DDR_SMA10

AJ20

AE12

DDR_ DQ10

MEM_A10

MEM_DQ10

DDR_DM[0..7]

DDR_SMA11

AG15

AF12

DDR_ DQ11

DDR_DM[0..7]

13,14

DDR_SMA12

AF15

MEM_A11

MEM_DQ11

AF7

DDR_ DQ12

MEM_A12

MEM_DQ12

DDR_SBS0

AE23

AF8

DDR_ DQ13

MEM_A13

MEM_DQ13

DDR_DQ[0..63]

AH20

AE11

DDR_ DQ14

DDR_SBS1

DDR_DQ[0..63]

13,14

AE25

MEM_A14

MEM_DQ14

AF11

DDR_ DQ15

DDR_SMA15

MEM_A15

MEM_DQ15

AJ12

DDR_ DQ16

MEM_DQ16

DDR_DQS[0..7]

DDR_DM0

AH7

MEM_DM0

AH12

DDR_ DQ17

DDR_DQS[0..7]

13,14

DDR_DM1

AF10

MEM_DQ17

AH14

DDR_ DQ18

DDR_DM2

AJ14

MEM_DM1

MEM_DQ18

AH15

DDR_ DQ19

MEM_DM2

MEM_DQ19

DDR_SMA[0..12]

DDR_DM3

AF21

AH11

DDR_ DQ20

DDR_SMA[0..12]

DDR_DM4

AH23

MEM_DM3

MEM_DQ20

AJ13

DDR_ DQ21

DDR_DM5

AK28

MEM_DM4

MEM_DQ21

AJ15

DDR_ DQ22

MEM_DM5

MEM_DQ22

DDR_DM6

AD29

AJ16

DDR_ DQ23

DDR_DM7

AB26

MEM_DM6

MEM_DQ23

AF18

DDR_ DQ24

MEM_DM7

MEM_DQ24

AG20

DDR_ DQ25

MEM_DQ25

DDR_SRAS#

AF24

AG21

DDR_ DQ26

MEM_RAS#

MEM_DQ26

DDR_SCAS#

AF25

AF22

DDR_ DQ27

DDR_SCAS#

MEM_CAS#

MEM_DQ27

AF19

DDR_ DQ28

DDR_SW E#

AE24

MEM_DQ28

AF20

DDR_ DQ29

MEM_WE#

MEM_DQ29

AE22

DDR_ DQ30

MEM_DQ30

DDR_ DQS0

AJ8

AF23

DDR_ DQ31

MEM_DQS0

MEM_DQ31

DDR_ DQS1

AF9

I/F

AJ21

DDR_ DQ32

MEM_DQS1

MEM_DQ32

DDR_ DQS2

AH13

AJ22

DDR_ DQ33

MEM_DQS2

MEM_DQ33

DDR_ DQS3

AE21

AJ24

DDR_ DQ34

MEM_DQS3

MEM_DQ34

DDR_ DQS4

AJ23

MEM

AK25

DDR_ DQ35

MEM_DQS4

MEM_DQ35

DDR_ DQS5

AJ27

AH21

DDR_ DQ36

DDR_ DQS6

AC28

MEM_DQS5

MEM_DQ36

AH22

DDR_ DQ37

MEM_DQS6

MEM_DQ37

DDR_ DQS7

AA25

AH24

DDR_ DQ38

MEM_DQS7

MEM_DQ38

AJ25

DDR_ DQ39

MEM_DQ39

AK26

DDR_ DQ40

DDR_CLK0

AK10

MEM_DQ40

AK27

DDR_ DQ41

DDR_CLK0#

AH10

MEM_CK0

MEM_DQ41

AJ28

DDR_ DQ42

DDR_CLK0#

MEM_CK0#

MEM_DQ42

AH29

DDR_ DQ43

MEM_DQ43

DDR_CLK1

AH18

AH25

DDR_ DQ44

MEM_CK1

MEM_DQ44

DDR_CLK1#

AJ19

AJ26

DDR_ DQ45

DDR_CLK1#

MEM_CK1#

MEM_DQ45

AJ29

DDR_ DQ46

MEM_DQ46

AG30

AH30

DDR_ DQ47

MEM_CK2

MEM_DQ47

AG29

AF29

DDR_ DQ48

MEM_CK2#

MEM_DQ48

AE29

DDR_ DQ49

MEM_DQ49

DDR_CLK3

AK11

AB28

DDR_ DQ50

MEM_CK3

MEM_DQ50

DDR_CLK3#

AJ11

AA28

DDR_ DQ51

DDR_CLK3#

MEM_CK3#

MEM_DQ51

AE28

DDR_ DQ52

MEM_DQ52

DDR_CLK4

AH17

AD28

DDR_ DQ53

MEM_CK4

MEM_DQ53

DDR_CLK4#

AJ18

AC29

DDR_ DQ54

DDR_CLK4#

MEM_CK4#

MEM_DQ54

AB29

DDR_ DQ55

MEM_DQ55

AF28

AC26

DDR_ DQ56

MEM_CK5

MEM_DQ56

AG28

AB25

DDR_ DQ57

MEM_CK5#

MEM_DQ57

Y26

DDR_ DQ58

MEM_DQ58

13,14 DDR_SCKE0

DDR_SCKE0

AF13

W26

DDR_ DQ59

MEM_CKE0

MEM_DQ59

DDR_SCKE1

AE13

AE26

DDR_ DQ60

13,14 DDR_SCKE1

MEM_CKE1

MEM_DQ60

DDR_SCKE2

AG14

AD26

DDR_ DQ61

DDR_SCKE2

MEM_CKE2

MEM_DQ61

DDR_SCKE3

AF14

AA26

DDR_ DQ62

DDR_SCKE3

MEM_CKE3

MEM_DQ62

Y27

DDR_ DQ63

DDR_SCS#0

AH26

MEM_DQ63

13,14 DDR_SCS#0

MEM_CS#0

DDR_SCS#1

AH27

AF6

C645

0.47U_0603_16V7K

13,14 DDR_SCS#1

MEM_CS#1

MEM_CAP1

DDR_SCS#2

AF26

DDR_SCS#2

MEM_CS#2

DDR_SCS#3

AG27

AA29

C432

0.47U_0603_16V7K

DDR_SCS#3

MEM_CS#3

MEM_CAP2

+1.8VS

L34 1

MPVDD

AC18

MPVDD

MEM_COMP

AK19

MEN_COMP R468 1

49.9_0402_1%

HB-1M2012-121JT03_0805

C516

2MPVSS

AD18

MPVSS

MEM_DDRVREF

AK20

+SDREF

1U_0603_10V6K

CHS-216IGP9050A21_BGA718

C489 2

0.1U_0402_10V6K 1

C724

+SDREF

+2.5V

0.1U_0402_10V6K

Close to U24.AK20

+2.5V

0.1U_0402_10V6K

C547

C475

C572

C450

1 C600

0.1U_0402_10V6K

2 0.1U_0402_10V6K

0.1U_0402_10V6K

Compal Electronics, Inc.

Title

ATIRC300M-DDR I/F

Size

Document Number

R e v

LA-2051

1.0

Date:

Friday, November 14, 2003

Sheet

o f 51

12,26 A_AD[0..31] A_AD[0..31] 12,26 A_CBE#[0..3] A_CBE#[0..3]

A_AD0

U24C

R600

AK5

ALINK_AD0

AGP_AD0/TMD2_HSYNC

A_AD1

AJ5

PART 3 OF 6

EXT_LVDS_SSOUT

ALINK_AD1

AGP_AD1/TMD2_VSYNC

A_AD2

AJ4

ALINK_AD2

AGP_AD2/TMD2_D1

A_AD3

AH4

@0_0402_5%

ALINK_AD3

AGP_AD3/TMD2_D0

A_AD4

AJ3

ALINK_AD4

AGP_AD4/TMD2_D3

A_AD5

AJ2

ALINK_AD5

AGP_AD5/TMD2_D2

A_AD6

AH2

ALINK_AD6

AGP_AD6/TMD2_D5

A_AD7

AH1

@0.1U_0402_10V6K

+3VS_SSVDD

L42 1

+3VS

ALINK_AD7

AGP_AD7/TMD2_D4

R534

A_AD8

AG2

@BLM21P300S_0805

A_AD9

AG1

ALINK_AD8

ZVPort),

AGP_AD8/TMD2_D6

LVDS_SSOUT2

AGP_SBA6

ALINK_AD9

AGP_AD9/TMD2_D9

A_AD10

AG3

A_AD18

AE6

ALINK_AD17

AGP_AD17/TMD1_HSYNC

@0_0402_5%

21@0_0402_5%

VDD

2 1

LVDS_SSIN2

AGP_SBA7

A_AD11

AF3

ALINK_AD10

AGP_AD10/TMD2_D8

C653

C656

@0_0402_5%

C651

@0_0402_5%

A_AD12

AF1

ALINK_AD11

AGP_AD11/TMD2_D11

A_AD13

AF2

ALINK_AD12

AGP_AD12/TMD2_D10

R294

@10P_0402_25V8K

A_AD14

AF4

ALINK_AD13

AGP_AD13

U44

R275

A_AD15

AE3

ALINK_AD14

AGP_AD14

@10U_0805_6.3V6M

ALINK_AD15

AGP_AD15

A_AD16

AE4

R296

R295

@0_0402_5%

A_AD17

AE5

ALINK_AD16

AGP_AD16/TMD1_VSYNC

R535

A_AD19

AC2

ALINK_AD18

TMDS

AGP_AD18/TMD1_DE

Xin/CLK

SSCLK

ALINK_AD19

AGP_AD19/TMD1_D0

@0_0402_5%

A_AD26

AA4

I/F

R277

@SM561BS_SO8

R274

ALINK_AD25

AGP_AD25/TMD1_D6

A_AD20

AC4

ALINK_AD20

AGP_AD20/TMD1_D1

A_AD21

AB3

Xout

A_AD22

AB2

ALINK_AD21

AGP_AD21/TMD1_D2

C657

R601

A_AD23

AB5

ALINK_AD22

AGP_AD22/TMD1_D3

VSS

EXT_LVDS_SSIN 38

ALINK_AD23

AGP_AD23/TMD1_D4

SSCC

A_AD24

AB6

2 @10P_0402_25V8K

ALINK_AD24

AGP_AD24/TMD1_D7

@0_0402_5%

A_AD25

AA2

A/-Link

(GPIO,

A_AD27

AA5

ALINK_AD26

AGP_AD26/TMD1_D9

R276

ALINK_AD27

AGP_AD27/TMD1_D8

A_AD28

AA6

@0_0402_5%

ALINK_AD28

AGP2_SBSTB/AGP3_SBSTBF/NC/LVDS_BLON

A_AD29

ALINK_AD29

AGP_AD29/TMD1_D10

LVDS SPREAD SPECTRUM

A_AD30

ALINK_AD30

AGP_AD30/TMDS_HPD

R293

A_AD31

ALINK_AD31

AGP_AD31

@0_0402_5%

A_CBE#0

AG4

ALINK_CBE#0

PCI Bus 0

/ AGP Bus

AGP2_SBSTB#/AGP3_SBSTBS/NC/ENA_BL

Note: PLACE CLOSE TO U2 (NB RC300M)

A_CBE#1

AE2

ALINK_CBE#1

AGP2_ADSTB0/AGP3_ADSTBF0/TMD2_CLK#

A_CBE#2

AC3

ALINK_CBE#2

AGP2_ADSTB0#/AGP3_ADSTBS0/TMD2_CLK

A_CBE#3

AA3

ALINK_CBE#3

AGP2_ADSTB1/AGP3_ADSTBF1/TMD1_CLK#

A_PAR

AD5

AGP2_ADSTB1#/AGP3_ADSTBS1/TMD1_CLK

12,26

A_PAR

PCI_PAR/ALINK_NC

A_STROBE#

AC6

A_STROBE#

PCI_FRAME#/ALINK_STROBE#

A_ACAT#

AC5

A_ACAT#

PCI_IRDY#/ALINK_ACAT#

A_END#

AD2

A_END#

PCI_TRDY#/ALINK_END#

AGP2_CBE#0/AGP3_CBE0/TMD2_D7

R517

0_0402_5%

19,20,24,26

PCI_PIRQA#

INTA#

AGP2_CBE#1/AGP3_CBE1/TMD2_DE

A_DEVSEL#

AD3

A_DEVSEL#

ALINK_DEVSEL#

AGP2_CBE#2/AGP3_CBE2

A_OFF#

AD6

PCI_STOP#/ALINK_OFF#

AGP2_CBE#3/AGP3_CBE3/TMD1_D5

A_SBREQ#

ALINK_SBREQ#

BUS

AGP2_IRDY#/AGP3_IRDY/GPIO8/I2C_CLK

+3VS

A_SBGNT#

ALINK_SBGNT#

AGP2_TRDY#/AGP3_TRDY/TMDS_DVI_CLK

R500

AGP2_STOP#/AGP3_STOP/GPIO10/DDC_DATA

+3VS

PCI_REQ#0/ALINK_NC

AGP_PAR

8.2K_0402_5%

PCI_GNT#0/ALINK_NC

AGP2_FRAME#/AGP3_FRAME/TMDS_DVI_DATA

PCI

AGP2_DEVSEL#/AGP3_DEVSEL/GPIO9/I2C_DATA

R518

R519

AGP2_PIPE#/AGP3_DBI_HI

AGP2_NC/AGP3_DBI_LO

2.2K_0402_5%

AGP2_GNT#/AGP3_GNT

AGP2_RBF#/AGP3_RBF

AGP2_REQ#/AGP3_REQ

AGP2_WBF#/AGP3_WBF

AGP8X_DET#

DDC_CLK

AGP2_SBA0/AGP3_SBA#0/GPIO0/VDDC_CNTL0

AGPREF_8X

DDC_DAT

AGP_VREF/TMDS_VREF

AGP2_SBA1/AGP3_SBA#1/GPIO1/VDDC_CNTL1

AGP_SBA2

ENBKL#

C615

AGP2_SBA2/AGP3_SBA#2/GPIO2/LVDS_BLON#

AGP_SBA3

ENVDD

AGP2_SBA3/AGP3_SBA#3/GPIO3/LVDS_DIGON

AGP_SBA4

AGP_STP#

AGP2_SBA4/AGP3_SBA#4/GPIO4/STP_AGP#

AGP_SBA5

+1.5VS

AGP2_SBA5/AGP3_SBA#5/GPIO5/AGP_BUSY#

AGP_BUSY#

0.1U_0402_10V6K

AGP_SBA6

R523

AGP2_SBA6/AGP3_SBA#6/GPIO6/LVDS_SSOUT

AGP_SBA7

R628

AGP_COMP

AGP2_SBA7/AGP3_SBA#7/GPIO7/LVDS_SSIN

AGP_COMP

1.2K_0402_5%

AGP_ST0

@52.3_0603_1%

AGP_ST1

R529

AGP_ST2

1K_0402_1%

+3VS

CHS-216IGP9050A21_BGA718

AGPREF_8X

8X(M9+M10@)

4X(NAGP@)

1K_0402_1%

R504

169_0402_1%

52.1_0402_1%

R533

@47K_0402

324_0402_1%

1K_0402_1%

AGP8X_DET#

100_0402_1%

1K_0402_1%

+1.5VS

+3VS

+1.5VS

ATI request

0.1U_0402_10V6K

10U_0805_10V4Z

0.1U_0402_10V6K

@0.01U_0402_16V7Z

1 C515

1 C605

1 C498

1 C558

C557

C506

C540

C530

C524

C513

C555

C549

C529

C580

C633

C639

C638

C617

C618

C602

C601

C568

C569

C610

C585

C619

C609

C514

C595

47U_B_6.3VM

@0.01U_

0.1U_0402

_10V6K

0.1U_0402_10V6K

0402_16V7Z

@0.01U_0402_16V7Z

+1.5VS

PIR

LAYOUT 92.06.23

0.1U_0402_10V6K

1C548

C487

C523

C508

C565

C564

C539

C554

C640

C641

C628

C627

C629

C630

C631

C556

C571

C589

C620

C608

47U_B_6.3VM

0.1U_0402_10V6K

Note: PLACE CLOSE TO U27 (NB RC300M)

Compal Electronics, Inc.

Title

ATI RC300M-AGP, ALINK BUS

THIS SHEET OF ENGINEERINGDRAWINGIS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

Size

Document Number

R ev

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

LA-2051

1.0

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Friday, November 14, 2003

Sheet

o f 51

L39

+3VS

+2.5VS

+ 3VS_VDDR

1 C622

FBM-11-160808-121-T_0603

L35

2 0.1U_0402_10V6K

KC FBM-L11-201209-221LMAT_0805

+2.5VS_AVDD

U24D

VDDR3

PART 4 OF 6

D12

LCD_B0-

VDDR3

TXOUT_U0N

C551

TXOUT_U0P

E12

LCD_B0+

A14

AVDD_25

TXOUT_U1N

F11

LCD_B1-

0.1U_0402_10V6K

F12

KC FBM-L11-201209-221LMAT_0805

TXOUT_U1P

LCD_B1+

B13

D13

AVSSN

TXOUT_U2N

LCD_B2-

L37

D14

+1.8VS

TXOUT_U2P

LCD_B2+

C550

+1.8VS_AVDDDI

B14

TXCLK_UN

E13

LCD_BCLK-

AVDDDI_18

F13

TXCLK_UP

LCD_BCLK+

0.1U_0402_10V6K 2

C13

AVSSDI

TXOUT_L0N

E10

LCD_A0-

D10

+1.8VS

TXOUT_L0P

LCD_A0+

L33

10_0603_5%

+1.8VS_AVDDQ

A15

C537

C536

AVDDQ

TXOUT_L1N

LCD_A1-

B15

TXOUT_L1P

D11

LCD_A1+

0.1U_0402_10V6K 2

2 0.1U_0402_10V6K

AVSSQ

TXOUT_L2N

LCD_A2-

LVDS

TXOUT_L2P

E11

LCD_A2+

L38

TXCLK_LN

B10

LCD_ACLK-

0.1U_0402_10V6K

2 0.1U_0402_10V6K

H11

C10

L32

+1.8VS

KC FBM-L11-201209-221LMAT_0805

C578

C586

G11

PLLVDD_18

TXCLK_LP

LCD_ACLK+

+1.8VS

C577

PLLVSS

+1.8VS_LPVDD

KC FBM-L11-201209-221LMAT_0805

10U_0805_10V4Z

LPVDD_18

A12

0.1U_0402_10V6K

F14

LPVSS

A11

LPVSS

C591

C576

C518

INTCRT_R

RED

F15

INTCRT_G

GREEN

+1.8VS_LVDDR

INTCRT_B

E14

BLUE

CRT

LVDDR_18

B12

0.1U_0402_10V6K

10U_0805_10V4Z

18 INTCRT_ HSYNC

DACHSYNC

LVDDR_18

C12

18 INTCRT_VSYNC

DACVSYNC

R474

715 _0402_1% NB_RSET

C14

RSET

LVSSR

B11

LVSSR

+1.8VS

C11

LVSSR

KC FBM-L11-201209-221LMAT_0805

REFCLK1_NB

RC300M_X1

XTALIN

0.1U_0402_10V6K

R520

RC300M_X2

XTALOUT

E15

C566

C567

C587

L36

CLK_AGP_66M

CLK_NB_BCLK

C_R

TV_CRMA 17

2 1

CLK_NB_BCLK

HCLKIN

SVID

CLK_NB_BCLK#

C15

2 1

16 CLK_NB_BCLK#

HCLKIN#

DACSCL

TV_LUMA 17

INTDDCCK

R506

Y_G

R272

56_0402_5%

@10_0402_5%

SYS_FBCLKOUT

COMP_B

D15

TV_COMPS 17

0.1U_0402_10V6K

10U_0805_10V4Z

@10_0402_5%

1 C634

SYS_FBCLKOUT#

C282

2 @15P_0402_50V8J

ALINK_CLK

DACSDA

INTDDCDA 18

2 @15P_0402_50V8J

AGPCLKOUT

Q45

CLK_AGP_66M

AGPCLKIN

@2N7002_SOT23

CPUSTOP#

PM_STPCPU#

5,16,26,47

CLK_MEM_66M

EXT_MEM_CLK

CLK_MEM_66M

+3VS

SYSCLK

2 G

R271

27M_TV 2

127M_TV_R

USBCLK

CLK. GEN.

PCIRST#

19,20,21,22,24,25,26,34,35

VCC

OUT

REF27

SYSCLK#

R457

@0_0402_5%

@10_0402_5%

R497

@22_0402_5%

1 C592

GND

OSC

C271

@27MHZ_20P_6N

R505

CHS-216IGP9050A21_BGA718

+3VS

2 @0.1U_0402_16V7K

R588

R461

1K_0402_5%

2 @15P_0402_50V8J

@10_0402_5%

4.7K_0402_5%

+3VS

Note: PLACE CLOSE TO U27 (NB CHIP)

EXCLK_27M_TV

RC300M_X1

C650

@18P_0402_50V8K

R531

Y 5

@1M_0402_1%

@14.31818MHZ_20P_6X1430004201

C649

RC300M_X2

@18P_0402_50V8K

Compal Electronics, Inc.

Title

ATI RC300M-VIDEO I/F

THIS SHEETOFENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

Size

Document Number

R ev

ANDTRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

LA-2051

1.0

DEPARTMENTEXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USEDBY ORDISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Friday, November 14, 2003

Sheet

o f

+1.5VS

+2.5V

U24E

U24F

PART 6 OF 6

F10

VDD_CORE

VDDR_MEM

AA23

A29

VSS

R23

VDD_CORE

VDDR_MEM

AA27

AB23

VSS

G12

VDD_CORE

VDDR_MEM

AB30

AB24

VSS

H12

VDD_CORE

5OF

VDDR_MEM

AC10

AB27

VSS

T12

H13

AC12

AB4

T13

M12

VDD_CORE

PART

VDDR_MEM

AC13

AB8

VSS

T14

M13

VDD_CORE

VDDR_MEM

AC15

AC1

VSS

T15

VDD_CORE

VDDR_MEM

VSS

M14

VDD_CORE

VDDR_MEM

AC17

AC11

VSS

T16

M17

VDD_CORE

VDDR_MEM

AC19

AC14

VSS

T17

M18

AC21

AC16

T18

VDD_CORE

VDDR_MEM

VSS

M19

AC23

AC20

T19

VDD_CORE

VDDR_MEM

VSS

N12

AC24

AC30

T27

VDD_CORE

VDDR_MEM

VSS

N13

AC25

AD11

VDD_CORE

VDDR_MEM

VSS

N14

AC27

AD14

U15

VDD_CORE

VDDR_MEM

VSS

N17

AD10

AD16

U16

VDD_CORE

VDDR_MEM

VSS

N18

AD12

AD20

VDD_CORE

VDDR_MEM

VSS

N19

AD13

AD4

VDD_CORE

VDDR_MEM

VSS

P12

PWR

AD15

AE27

V15

VDD_CORE

VDDR_MEM

VSS

P13

AD17

AF30

V16

VDD_CORE

VDDR_MEM

VSS

P14

AD19

AF5

V27

VDD_CORE

VDDR_MEM

VSS

P17

AD21

AG10

VDD_CORE

VDDR_MEM

VSS

P18

VDD_CORE

CORE

PWR

VDDR_MEM

AD23

AG13

VSS

U14

VDD_CORE

VDDR_MEM

AE10

AG25

VSS

W27

P19

VDD_CORE

VDDR_MEM

AD24

AG16

VSS

U12

VDD_CORE

VDDR_MEM

AD25

AG19

VSS

W15

U13

VDD_CORE

VDDR_MEM

AD27

AG22

VSS

W16

U17

VDD_CORE

I/F

VDDR_MEM

AE14

AG7

VSS

U18

AE15

AH28

Y23

VDD_CORE

VDDR_MEM

VSS

GND

VSS

U19

MEM

AE19

AH3

Y24

VDD_CORE

VDDR_MEM

VSS

V12

AE20

AJ1

Y30

VDD_CORE

VDDR_MEM

VSS

V13

VDD_CORE

VDDR_MEM

AE30

AK13

VSS

V14

AE9

AK2

VDD_CORE

VDDR_MEM

VSS

V17

VDD_CORE

VDDR_MEM

AF27

AK22

VSS

V18

AG11

AK29

R19

VDD_CORE

VDDR_MEM

VSS

V19

AG12

AK4

R18

VDD_CORE

POWER

VDDR_MEM

VSS

W12

AG17

AK7

R17

VDD_CORE

VDDR_MEM

VSS

C16

AJ30

W13

VDD_CORE

VDDR_MEM

AG18

VSS

R16

W14

VDD_CORE

VDDR_MEM

AG23

B16

VSS

R15

W17

VDD_CORE

VDDR_MEM

AG24

B30

VSS

R14

+CPU_CORE

W18

VDD_CORE

VDDR_MEM

AG26

C19

VSS

R13

W19

AG8

C23

R12

VDD_CORE

VDDR_MEM

VSS

AG9

C27

D16

VDDR2_CPU

VDDR_MEM

AK14

D21

VSS

P27

VDDR2_CPU

VDDR_MEM

VSS

D17

AK23

D25

P16

VDDR2_CPU

VDDR_MEM

VSS

E16

AK8

P15

VDDR2_CPU

VDDR_MEM

VSS

E17

V23

VDDR2_CPU

VDDR_MEM

VSS

F16

W23

N24

VDDR2_CPU

VDDR_MEM

VSS

F17

W24

F27

N23

VDDR2_CPU

VDDR_MEM

VSS

G17

W25

N16

VDDR2_CPU

VDDR_MEM

VSS

G21

Y25

N15

VDDR2_CPU

VDDR_MEM

+1.5VS

VSS

G23

G14

VDDR2_CPU

VSS

G24

G15

M27

VDDR2_CPU

VDDP_AGP

VSS

H16

PWR

G18

M16

VDDR2_CPU

VDDP_AGP

VSS

H17

G20

M15

VDDR2_CPU

VDDP_AGP

VSS

H19

H14

VDDR2_CPU

VDDP_AGP

VSS

H21

H15

H24

VDDR2_CPU

I/F

VDDP_AGP

H18

VSS

L25

VDDR2_CPU

VDDP_AGP

VSS

K23

H20

L24

VDDR2_CPU

VDDP_AGP

VSS

K24

VDDR2_CPU

CPU

VDDP_AGP

H27

VSS

L23

M23

VDDR2_CPU

VDDP_AGP

VSS

P23

K27

VDDR2_CPU

PWR

VDDP_AGP

VSS

P24

VDDR2_CPU

VDDP_AGP

VSS

T23

VDDR2_CPU

VDDP_AGP

T24

VDDR2_CPU

VDDP_AGP

CHS-216IGP9050A21_BGA718

U23

VDDR2_CPU

VDDP_AGP

U24

AGP

VDDR2_CPU

VDDP_AGP

W30

+3VS

VDDR2_CPU

VDDP_AGP

AA1

VDDL_ALINK

AA7

PWR

VDDP_AGP

VDDL_ALINK

VDDP_AGP

AA8

VDDL_ALINK

VDDP_AGP/VDDP33

AC7

+3VS

VDDL_ALINK

VDDP_AGP/VDDP33

AC8

VDDL_ALINK

VDDP_AGP/VDDP33

AD1

VDDL_ALINK

ALINK

VDDL_ALINK

VDD_18

H22

+1.8VS

AD7

VDDL_ALINK

VDD_18

AC22

AD8

VDDL_ALINK

VDD_18

AC9

AK3

VDDL_ALINK

VDD_18

H10

CHS-216IGP9050A21_BGA718

+2.5V

0.1U_0402_10V6K

C445 1

C570 1 C462

C436 1

1 C538

1 C522

1 C446

1 C457

1 C437

1 C438

C429 + C505

C553

C461

+1.8VS

100U_D2_10VM 2

2 0.1U_0402_10V6K

0.1U_0402_10V6K

C581

C575

C482

C481

1 C588

10U_0805_10V4Z

2 0.1U_0402_10V6K

0.1U_0402_10V6K

Title

Compal Electronics, Inc.

ATI RC300M-POWER

THIS SHEET OF ENGINEERINGDRAWINGIS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

Size

Document Number

R ev

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

LA-2051

1.0

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Friday, November 14, 2003

Sheet

o f

9,26 A_AD[0..31]

A_AD[0..31]

9,26 A_CBE#[0..3]

A_CBE#[0..3]

R418 1

10K_0402_5%

+3VS

A_AD[31..30] : FSB CLK SPEED

R537

@4.7K_0402_5%

A_AD18 : ENABLE PHASE CALIBRATION

A_AD31

R4201

4.7K_0402_5% 2

DEFAULT: 01

+3VS

BSEL1

5,16

A_AD18

R2901

24.7K_0402_5%

DEFAULT: 0

D45

RB751V_

SOD323

00: 100 MHZ

0: DISABLE

R417

10K_0402_5%

+3VS

01: 133 MHZ

A_AD30

R4191

4.7K_0402_5% 2

BSEL0

5,16

10: 200MHZ

1:ENABLE

11:166 MHZ

D44

RB751V_

SOD323

R538

@4.7K_0402_5%

A_AD25/A_AD17 : CPU VOLTAGE[1..0]

R549

10K_0402_5%

A_AD29: STRAP CONFIGURATION

+3VS

A_AD17

A_AD29

R2781

2@4.7K_0402_5%

DEFAULT:1

R2891

24.7K_0402_5%

DEFAULT: 0

00: 1.05V

0:REDUCEDE SET

01: 1.35V

1: FULL SET(internal Pull high)

11: 1.75V

R544

@10K_0402_5%

A_AD28: SPREAD SPECTRUM ENABLE

10: 1.45V

+3VS

A_AD28

R2831

24.7K_0402_5%

DEFAULT:0

0: DISABLE

1: ENABLE

A_PAR

R288

@4.7K_0402_5%

PAR: EXTENDED DEBUG MODE

9,26

A_PAR

R548

10K_0402_5%

A_AD27: FrcShortReset#

R539

DEFAULT : 1

4.7K_0402_5%

+3VS

A_AD27

R2791

2@4.7K_0402_5%

DEFAULT: 1

0: DEBUG MODE

0: TEST MODE

1: NORMAL

1: NORMAL MODE

R547

10K_0402_5%

+3VS

A_AD26 : ENABLE IOQ

A_AD26

R2801

2@4.7K_0402_5%

DEFAULT: 1

0: IOQ=1

1: IOQ=12

R545

2 10K_0402_5%

+3VS

A_AD25/A_AD17 : CPU VOLTAGE[1..0]

A_AD25

R282

@4.7K_0402_5%

DEFAULT: 10

AD25=1 DESTOP CPU

00: 1.05V

AD25=0 MOBILE CPU

01: 1.35V

AD17--DON'T CARE

11: 1.75V

10: 1.45V

A_AD24

R543

10K_0402_5%

+3VS

A_AD24 : MOBILE CPU SELECT

DEFAULT: 1

0: BANIAS CPU

1: OTHER CPU

R541

10K_0402_5%

+3VS

A_AD23 : CLOCK BYPASS DISABLE

A_AD23

R2861

2@4.7K_0402_5%

DEFAULT: 1

0: TEST MODE

1: NORMAL(internal Pull high)

A_AD22

R284

@4.7K_0402_5%

A_AD22 : OSC PAD OUTPUT PCICLK

DEFAULT : 1

0:PCICLK OUT

1: OSC CLK OUT

R542

10K_0402_5%

+3VS

A_AD21 : AUTO_CAL ENABLE

A_AD21

R2851

2@4.7K_0402_5%

DEFAULT : 1

0: DISABLE

1: ENABLE

R540

@4.7K_0402_5%

A_AD20 : INTERNAL CLK GEN ENABLE

+3VS

A_AD20

R2871

24.7K_0402_5%

DEFAULT : 0

0: DISABLE

1: ENABLE

R546

@4.7K_0402_5%

A_CBE#3: NOT USED

+3VS

A_CBE#3

R2811

2@4.7K_0402_5%

R536

@4.7K_0402_5%

A_CBE#0 :NO USED

+3VS

A_CBE#0

R2911

2@4.7K_0402_5%

Compal Electronics, Inc.

Title

ATI RC300M-SYSTEM STRAP

THIS SHEET OF ENGINEERINGDRAWINGIS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

Size

Document Number

R ev

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

LA-2051

1.0

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Friday, November 14, 2003

Sheet

12 o f

A		B			C					D			E			F				G					H
											+2.5V										DDR_DQ[0..6 3]
															+2.5V						DDR_DQ[0..6 3]			DDR_DQ[0..63] 8,14
															+2.5V						DDR_DQS[0..7]			DDR_DQ[0..63] 8,14
							C725					JP17									DDR_DQS[0..7]			DDR_DQS[0..7] 8,14
											1	VREF	VREF	2				+ SDREF						DDR_DQS[0..7] 8,14
											1			2							DDR_DM[0..7]
					+ SDREF	2	1	+2.5V			3			4										DDR_DM[0..7] 8,14
						2	1			DD R_DQ7	3	VSS	VSS	4	DD R_DQ6
											5	VSS	VSS	6
											5	DQ0	DQ4	6							DDR_SMAA[0..12]
							0.1U_0402_10V6K			DD R_DQ5	7	DQ0	DQ4	8	DD R_DQ0	1					DDR_SMAA[0..12]			DDR_SMAA[0..12] 14
										DD R_DQ5	7	DQ1	DQ5	8	DD R_DQ0	1
											9	DQ1	DQ5	10
										D DR_DQS0	9	VDD	VDD	10	D DR_DM0
											11	VDD	VDD	12
											11	DQS0	DM0	12			C679
										DD R_DQ1	13	DQS0	DM0	14	DD R_DQ4		C679				DDR_SMAA15			DDR_SMAA15 14
											15	DQ2	DQ6	16		2	0.1U_0402_10V6K							DDR_SMAA15 14
										DD R_DQ3	15	VSS	VSS	16	DD R_DQ2		0.1U_0402_10V6K
											17	VSS	VSS	18
											17	DQ3	DQ7	18
										DD R_DQ8	19	DQ3	DQ7	20	DDR_DQ12
										DD R_DQ8	19	DQ8	DQ12	20	DDR_DQ12
											21	DQ8	DQ12	22
1										DD R_DQ9	21	VDD	VDD	22	DDR_DQ13
1											23	VDD	VDD	24
											23	DQ9	DQ13	24					10_1206_8P4R_5%
										D DR_DQS1	25	DQ9	DQ13	26	D DR_DM1				10_1206_8P4R_5%
										D DR_DQS1	25	DQS1	DM1	26	D DR_DM1				DDR_SMA15			DDR_SMAA15
											27	DQS1	DM1	28						5	4
											27	VSS	VSS	28						5	4
										DDR_DQ11	29	VSS	VSS	30	DDR_DQ15	8	D DR_SWE#		D DR_SWE#	6	3				DDR _WE# 14
										DDR_DQ11	29	DQ10	DQ14	30	DDR_DQ15				D DR_SWE#	6	3
										DDR_DQ10	31	DQ10	DQ14	32	DDR_DQ14				DDR_SBS0	7	2
										DDR_DQ10	31	DQ11	DQ15	32	DDR_DQ14	8	DDR_SBS0		DDR_SBS0	7	2				D DR_BS0 14
											33	DQ11	DQ15	34		8	DDR_SBS0		DDR_SMA10	8	1	DDR_SMAA10			D DR_BS0 14
											33	VDD	VDD	34					DDR_SMA10	8	1	DDR_SMAA10
							8	DDR_CLK0			35	VDD	VDD	36
											35	CK0	VDD	36
											37	CK0	VDD	38
							8	DDR_CLK0#			37	CK0#	VSS	38						RP19
							8	DDR_CLK0#			39	CK0#	VSS	40						RP19
											39	VSS	VSS	40
												VSS	VSS
																			10_1206_8P4R_5%
										DDR_DQ20	41	DQ16	DQ20	42	DDR_DQ16				DDR_SMA1	5	4	DDR_SMAA1
										DDR_DQ21	43	DQ16	DQ20	44	DDR_DQ17				DDR_SMA3	6	3	DDR_SMAA3
										DDR_DQ21	43	DQ17	DQ21	44	DDR_DQ17				DDR_SMA3	6	3	DDR_SMAA3
											45	DQ17	DQ21	46					DDR_SMA5	7	2	DDR_SMAA5
											45	VDD	VDD	46					DDR_SMA5	7	2	DDR_SMAA5
										D DR_DQS2	47	VDD	VDD	48	D DR_DM2				DDR_SMA7	8	1	DDR_SMAA7
										DDR_DQ23	49	DQS2	DM2	50	DDR_DQ22
										DDR_DQ23	49	DQ18	DQ22	50	DDR_DQ22
											51	DQ18	DQ22	52
										DDR_DQ18	51	VSS	VSS	52	DDR_DQ19					RP27
										DDR_DQ18	53	VSS	VSS	54	DDR_DQ19					RP27
										DDR_DQ28	55	DQ19	DQ23	56	DDR_DQ24
										DDR_DQ28	55	DQ24	DQ28	56	DDR_DQ24				DDR_SMA9			DDR_SMAA9
											57	DQ24	DQ28	58						2	1
											57	VDD	VDD	58						2	1
										DDR_DQ26	59	VDD	VDD	60	DDR_DQ25				R234		10_0402_5%
										D DR_DQS3	61	DQ25	DQ29	62	D DR_DM3
										D DR_DQS3	61	DQS3	DM3	62	D DR_DM3
											63	DQS3	DM3	64
										DDR_DQ27	63	VSS	VSS	64	DDR_DQ29
										DDR_DQ27	65	DQ26	DQ30	66	DDR_DQ29
										DDR_DQ31	67	DQ26	DQ30	68	DDR_DQ30
										DDR_DQ31	67	DQ27	DQ31	68	DDR_DQ30				DDR_SMA12			DDR_SMAA12
											69	DQ27	DQ31	70						2	1
											69	VDD	VDD	70						2	1
											71	VDD	VDD	72					R239		10_0402_5%
											71	CB0	CB4	72					R239		10_0402_5%
											73	CB0	CB4	74
											73	CB1	CB5	74
											75	CB1	CB5	76
											75	VSS	VSS	76
											77	VSS	VSS	78
											77	DQS8	DM8	78
											79	DQS8	DM8	80
											79	CB2	CB6	80					10_1206_8P4R_5%
											81	CB2	CB6	82					10_1206_8P4R_5%
2											81	VDD	VDD	82					DDR_SCAS#
2											83	VDD	VDD	84			8	DDR_SCAS#			5	4			D DR_CAS# 14
											83	CB3	CB7	84							5	4
											85	CB3	CB7	86					DDR_SRAS#		6	3
											85	DU	DU/RESET#	86			8	DDR_SRAS#	DDR_SRAS#		6	3			D DR_RAS# 14
											87	VSS	VSS	88			8	DDR_SBS1	DDR_SBS1		7	2			D DR_BS1 14
											89	VSS	VSS	90			8	DDR_SBS1	DDR_SMA0		8	1	DDR_SMAA0		D DR_BS1 14
	DDR_DQ[0..6 3]										89	CK2	VSS	90					DDR_SMA0		8	1	DDR_SMAA0
		DDR_DQ[0..63]	8,14								91	CK2	VSS	92
								R592			91	CK2#	VDD	92		R593
											93	CK2#	VDD	94
	DDR_DQS[0..7]										93	VDD	VDD	94							RP18
	DDR_DQS[0..7]	DDR_DQS[0..7] 8,14		8,14	DDR_SCKE1			1	2		95	VDD	VDD	96	1	2		D DR_SCKE0 8,14			RP18
		DDR_DQS[0..7] 8,14		8,14	DDR_SCKE1						97	CKE1	CKE0	98		10_0402_5%		D DR_SCKE0 8,14
								10_0402_5%		DDR_SMA12	97	DU/A13	DU/BA2	98	DDR_SMA11	10_0402_5%			10_1206_8P4R_5%
											99	DU/A13	DU/BA2	100					10_1206_8P4R_5%
	DDR_DM[0..7]										99	A12	A11	100
		DDR_DM[0..7]	8,14							DDR_SMA9	101	A12	A11	102	DDR_SMA8				DDR_SMA2		5	4	DDR_SMAA2
										DDR_SMA9	101	A9	A8	102	DDR_SMA8				DDR_SMA2		5	4	DDR_SMAA2
											103	A9	A8	104					DDR_SMA4		6	3	DDR_SMAA4
										DDR_SMA7	105	VSS	VSS	106	DDR_SMA6				DDR_SMA6		7	2	DDR_SMAA6
	DDR_SMA[0..12]									DDR_SMA7	105	A7	A6	106	DDR_SMA6				DDR_SMA6		7	2	DDR_SMAA6
		DDR_SMA[0..12]	8							DDR_SMA5	107	A7	A6	108	DDR_SMA4				DDR_SMA8		8	1	DDR_SMAA8
										DDR_SMA5	107	A5	A4	108	DDR_SMA4				DDR_SMA8		8	1	DDR_SMAA8
										DDR_SMA3	109	A5	A4	110	DDR_SMA2
										DDR_SMA1	111	A3	A2	112	DDR_SMA0
										DDR_SMA1	111	A1	A0	112	DDR_SMA0						RP28
											113	A1	A0	114							RP28
										DDR_SMA10	113	VDD	VDD	114	DDR_SBS1				DDR_SMA11				DDR_SMAA11
										DDR_SMA10	115	A10/AP	BA1	116	DDR_SBS1				DDR_SMA11		2	1	DDR_SMAA11
								10_0402_5%		DDR_SBS0	117	A10/AP	BA1	118	DDR_SRAS#					R238		10_0402_5%
								10_0402_5%		DDR_SBS0	117	BA0	RAS#	118	DDR_SRAS#					R238		10_0402_5%
								R594		D DR_SWE#	119	BA0	RAS#	120	DDR_SCAS#	R595
								R594		D DR_SWE#	119	WE#	CAS#	120	DDR_SCAS#	R595
				8,14	DDR_SCS#0			1	2		121	S0#	S1#	122	1	2			DDR_SCS#1 8,14
				8,14	DDR_SCS#0		8	DDR_SMA15		DDR_SMA15	123	S0#	S1#	124		10_0402_5%			DDR_SCS#1 8,14
										DDR_SMA15	123	DU	DU	124		10_0402_5%
											125	DU	DU	126
										DDR_DQ32	125	VSS	VSS	126	DDR_DQ33
											127	VSS	VSS	128
											127	DQ32	DQ36	128
										DDR_DQ34	129	DQ32	DQ36	130	DDR_DQ36
										DDR_DQ34	129	DQ33	DQ37	130	DDR_DQ36
											131	DQ33	DQ37	132
										D DR_DQS4	131	VDD	VDD	132	D DR_DM4
											133	VDD	VDD	134
											133	DQS4	DM4	134
										DDR_DQ39	135	DQS4	DM4	136	DDR_DQ35
										DDR_DQ39	135	DQ34	DQ38	136	DDR_DQ35
											137	DQ34	DQ38	138
										DDR_DQ37	137	VSS	VSS	138	DDR_DQ38
											139	VSS	VSS	140
											139	DQ35	DQ39	140
										DDR_DQ41	141	DQ35	DQ39	142	DDR_DQ40
										DDR_DQ41	141	DQ40	DQ44	142	DDR_DQ40
											143	DQ40	DQ44	144
										DDR_DQ44	143	VDD	VDD	144	DDR_DQ45
											145	VDD	VDD	146
3											145	DQ41	DQ45	146
3										D DR_DQS5	147	DQ41	DQ45	148	D DR_DM5
										D DR_DQS5	147	DQS5	DM5	148	D DR_DM5
											149	DQS5	DM5	150
										DDR_DQ47	149	VSS	VSS	150	DDR_DQ42
											151	VSS	VSS	152
											151	DQ42	DQ46	152
										DDR_DQ43	153	DQ42	DQ46	154	DDR_DQ46
										DDR_DQ43	153	DQ43	DQ47	154	DDR_DQ46
											155	DQ43	DQ47	156
											155	VDD	VDD	156
											157	VDD	VDD	158		DDR_CLK1# 8
											157	VDD	CK1#	158		DDR_CLK1# 8
											159	VSS	CK1	160		D DR_CLK1 8
											161	VSS	CK1	162		D DR_CLK1 8
										DDR_DQ48	161	VSS	VSS	162	DDR_DQ53
											163	VSS	VSS	164
											163	DQ48	DQ52	164
										DDR_DQ49	165	DQ48	DQ52	166	DDR_DQ52
										DDR_DQ49	165	DQ49	DQ53	166	DDR_DQ52
											167	DQ49	DQ53	168
										D DR_DQS6	167	VDD	VDD	168	D DR_DM6				Layout note
											169	VDD	VDD	170
											169	DQS6	DM6	170
										DDR_DQ54	171	DQ50	DQ54	172	DDR_DQ50
											173	DQ50	DQ54	174
										DDR_DQ55	173	VSS	VSS	174	DDR_DQ51				Place these resistor
											175	VSS	VSS	176
											175	DQ51	DQ55	176
										DDR_DQ61	177	DQ56	DQ60	178	DDR_DQ60				close by DIMM0,
											179	DQ56	DQ60	180					close by DIMM0,
										DDR_DQ63	181	VDD	VDD	182	DDR_DQ56				all trace length
										DDR_DQ63	181	DQ57	DQ61	182	DDR_DQ56				all trace length
										D DR_DQS7	183	DQS7	DM7	184	D DR_DM7				Max=1.4"
										DDR_DQ62	185	VSS	VSS	186	DDR_DQ59
											187	VSS	VSS	188
											187	DQ58	DQ62	188
										DDR_DQ57	189	DQ58	DQ62	190	DDR_DQ58
										DDR_DQ57	189	DQ59	DQ63	190	DDR_DQ58
											191	DQ59	DQ63	192
											191	VDD	VDD	192
								14,16,27	SMDATA		193	VDD	VDD	194
											193	SDA	SA0	194
											195	SDA	SA0	196
								14,16,27	SMCLK		195	SCL	SA1	196
								14,16,27	SMCLK	+3VS	197	SCL	SA1	198
											197	VDD_SPD	SA2	198
											199	VDD_SPD	SA2	200
											199	VDD_ID	DU	200
												VDD_ID	DU
												KLINK_5746-2-111

Layout note

Place these resistors close to DIMM0,

all trace length<500 mil

DDR TOPOLOGY 1 FOR SMAA[0, 3, 6:12], SBA[1, 0], SRAS#, SCAS#, SWE#

Compal Electronics, Inc.

Title

DDR-SODIMM SLOT0

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

Size

Document Number

R e v

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

LA-2051

1.0

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Friday, November 14, 2003

Sheet 13 o f

+1.25VS

C726

+2.5V

RP37

RP91

+SDREF

+2.5V

JP20

+SDREF

DDR_DQ7

DDR_DQ6

VREF

0.1U_0402_10V6K

VSS

DDR_DQ5

DDR_DQ0

DDR_DQ7

DDR_DQ6

DQ0

DQ4

DDR_DQS0

DDR_DM0

DDR_DQ5

DQ1

DQ5

DDR_DQ0

DDR_DQ1

DDR_DQ4

DDR_DQS0

VDD

DDR_DM0

DQS0

DM0

56_0804_8P4R_5%

DDR_DQ1

DQ2

DQ6

DDR_DQ4

C672

VSS

DDR_DQ3

DDR_DQ2

0.1U_0402_10V6K

DQ3

DQ7

DDR_DQ8

DQ8

DQ12

DDR_DQ12

RP35

RP84

DDR_DQ9

VDD

DDR_DQ13

DQ9

DQ13

DDR_DQ3

DDR_DQ2

DDR_DQS1

DQS1

DM1

DDR_DM1

VSS

DDR_DQ8

DDR_DQ12

DDR_DQ11

DDR_DQ15

DQ10

DQ14

DDR_DQ9

DDR_DQ13

DDR_DQ10

DDR_DQ14

DQ11

DQ15

DDR_DQS1

DDR_DM1

VDD

DDR_CLK3

CK0

VDD

56_0804_8P4R_5%

DDR_CLK3#

CK0#

VSS

DDR_DQ20

VSS

DDR_DQ16

DQ16

DQ20

RP33

RP73

DDR_DQ21

DQ17

DQ21

DDR_DQ17

DDR_DQ11

DDR_DQ15

DDR_DQS2

VDD

DDR_DM2

DQS2

DM2

DDR_DQ10

DDR_DQ14

DDR_DQ23

DDR_DQ22

DQ18

DQ22

DDR_DQ20

DDR_DQ16

VSS

DDR_DQ21

DDR_DQ17

DDR_DQ18

DQ19

DQ23

DDR_DQ19

DDR_DQ28

DQ24

DQ28

DDR_DQ24

+1.25VS

56_0804_8P4R_5%

DDR_DQ26

VDD

DDR_DQ25

RP24

DQ25

DQ29

RP62

DDR_DQS3

DQS3

DM3

DDR_DM3

DDR_SMAA9

DDR_SCKE2

VSS

DDR_DQ27

DQ26

DQ30

DDR_DQ29

DDR_SMAA7

DDR_SMAA11

RP32

RP71

DDR_DQ31

DQ27

DQ31

DDR_DQ30

DDR_SMAA5

DDR_SMAA8

DDR_DQS2

DDR_DM2

VDD

DDR_SMAA3

DDR_SMAA6

CB0

CB4

DDR_DQ23

DDR_DQ22

CB1

CB5

33_0804_8P4R_5%

_0804_8P4R_5%

DDR_DQ18

DDR_DQ19

VSS

DDR_DQ28

DDR_DQ24

DQS8

DM8

CB2

CB6

56_0804_8P4R_5%

VDD

RP23

RP61

CB3

CB7

DDR_SMAA1

DDR_SMAA4

DU/RESET#

VSS

DDR_SMAA10

DDR_SMAA2

CK2

VSS

DDR_BS0

DDR_SMAA0

RP30

RP68

R596

CK2#

VDD

R597

DDR_W E#

DDR_BS1

DDR_DQ26

DDR_DQ25

DDR_SCKE3

DDR_CKE3

VDD

DDR_CKE21

2DDR_SCKE2

8 DDR_SCKE3

DDR_SCKE2 8 33_0804_8P4R_5%

_0804_8P4R_5%

CKE1

CKE0

DDR_DQS3

DDR_DM3

DU/A13

DU/BA2

DDR_DQ27

DDR_DQ29

10_0402_5%

DDR_SMAA12

A12

A11

100

DDR_SMAA11

10_0402_5%

DDR_DQ31

DDR_DQ30

DDR_SMAA9

101

102

DDR_SMAA8

DDR_SMAA7

103

VSS

104

DDR_SMAA6

56_0804_8P4R_5%

105

106

RP20

RP60

DDR_SMAA5

107

108

DDR_SMAA4

DDR_SMAA3

109

110

DDR_SMAA2

8,13

DDR_SCS#1

DDR_RAS#

DDR_SMAA1

111

112

DDR_SMAA0

DDR_CAS#

8,13

DDR_SCS#0

113

114

DDR_SCS#2

DDR_SCS#3

VDD

RP15

RP58

DDR_SMAA10

115

116

DDR_BS1

DDR_SMAA15

A10/AP

BA1

DDR_BS0

117

118

DDR_RAS#

BA0

RAS#

DDR_RAS# 13

DDR_DQ32

DDR_DQ33

DDR_W E#

119

120

DDR_CAS#

33_0804_8P4R_5%

_0804_8P4R_5%

DDR_W E#

WE#

CAS#

DDR_CAS# 13

DDR_DQ34

DDR_DQ36

DDR_SCS#2

2R598 DDR_CS#2

121

S0#

S1#

122

DDR_CS#31

DDR_SCS#3

DDR_SCS#3 8

DDR_DQS4

DDR_DM4

DDR_SMAA15

10_0402_5%DDR_SMAA15

123

124

R599

10_0402_5%

DDR_DQ39

DDR_DQ35

125

DDR_DQ32

VSS

DDR_DQ33

127

128

DQ32

DQ36

56_0804_8P4R_5%

DDR_DQ34

129

130

DDR_DQ36

RP25

DQ33

DQ37

131

132

DDR_DQS4

VDD

DDR_DM4

133

DQS4

DM4

134

8,13

DDR_SCKE0

DDR_DQ39

135

DQ34

DQ38

136

DDR_DQ35

8,13

DDR_SCKE1

137

VSS

138

DDR_SCKE3

RP13

RP55

DDR_DQ37

139

DQ35

DQ39

140

DDR_DQ38

DDR_SMAA12

DDR_DQ37

DDR_DQ38

DDR_DQ41

141

DQ40

DQ44

142

DDR_DQ40

143

VDD

144

33_0804_8P4R_5%

DDR_DQ41

DDR_DQ40

DDR_DQ44

145

DQ41

DQ45

146

DDR_DQ45

DDR_DQ44

DDR_DQ45

DDR_DQS5

147

148

DDR_DM5

DQS5

DM5

DDR_DQS5

DDR_DM5

DDR_DQ47

149

VSS

150

DDR_DQ42

151

DQ42

DQ46

152

56_0804_8P4R_5%

DDR_DQ43

153

DQ43

DQ47

154

DDR_DQ46

155

VDD

156

157

VDD

CK1#

158

DDR_CLK4# 8

159

VSS

CK1

160

DDR_CLK4 8

RP11

RP52

DDR_DQ48

161

VSS

162

DDR_DQ53

Layout note

163

DQ48

DQ52

164

DDR_DQ49

165

166

DDR_DQ52

DDR_DQ47

DDR_DQ42

DQ49

DQ53

Place these resistor

167

VDD

168

DDR_DQ43

DDR_DQ46

DDR_DQS6

169

DQS6

DM6

170

DDR_DM6

DDR_DQS[0..7]

DDR_DQ48

DDR_DQ53

closely DIMM1,

DDR_DQ54

171

DQ50

DQ54

172

DDR_DQ50

DDR_DQS[0..7] 8,13

DDR_DQ49

DDR_DQ52

173

174

all trace

DDR_DQ55

DQ51

DQ55

DDR_DQ51

DDR_DQ[0..63]

8,13

175

176

length<=800mil

VSS

56_0804_8P4R_5%

DDR_DQ61

177

DQ56

DQ60

178

DDR_DQ60

DDR_DM[0..7]

179

180

DDR_DM[0..7]

8,13

DDR_DQ63

VDD

DDR_DQ56

181

182

DQ57

DQ61

DDR_DQS7

183

DQS7

DM7

184

DDR_DM7

DDR_SMAA[0..12]

185

186

DDR_SMAA[0..12]

DDR_DQ62

VSS

DDR_DQ59

187

188

DQ58

DQ62

RP7

RP42

DDR_DQ57

189

DQ59

DQ63

190

DDR_DQ58

191

192

DDR_DQS6

DDR_DM6

VDD

13,16,27

SMDATA

193

194

SDA

SA0

+3VS

DDR_DQ54

DDR_DQ50

195

196

13,16,27

SMCLK

SCL

SA1

DDR_DQ55

DDR_DQ51

197

198

+3VS

VDD_SPD

SA2

DDR_DQ61

DDR_DQ60

199

200

VDD_ID

Layout note

56_0804_8P4R_5%

DDR-SODIMM_200_STD_H4.0

Place these resistor

close by DIMM1,

RP6

RP41

all trace length

DDR_DQ63

DDR_DQ56

Max=0.8"

DDR_DQS7

DDR_DM7

DDR

TOPOLOGY

1 FOR SMAA[0, 3, 6:12], SBA[1, 0], SRAS#, SCAS#, SWE#

DDR_DQ62

DDR_DQ59

DDR_DQ57

DDR_DQ58

Compal Electronics, Inc.

56_0804_8P4R_5%

Title

DDR-SODIMM SLOT1

THIS SHEET OF ENGINEERINGDRAWINGIS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

Size

Document Number

R ev

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

LA-2051

1.0

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Friday, November 14, 2003

Sheet

o f

Layout note :

Distribute as close as possible

to DDR-SODIMM0.

to DDR-SODIMM1.

+2.5V

C92

C139

C151

C274

C111

C165

C245

C171

C292

C686

C289

C146

C291

C122

C246

C170

C191

C150

220U_D2_4VM

0.1U_0402_10V6K

220U_D2_4VM

0.1U_0402_10V6K

2 0.1U_0402_10V6K

0.1U_0402_10V6K

C227

C184

C136

C248

C174

C266

C106

C258

C265

C113

C277

C247

C137

C226

C185

C261

C290

C176

0.1U_0402_10V6K

2 0.1U_0402_10V6K

0.1U_0402_10V6K

2 0.1U_0402_10V6K

C322

Layout note :

C93

for EMI solution

220U_D2_4VM

+2.5V

1000P_0402_50V7K

Layout note :

Place one cap close to every 2 pull up resistors termination to

C714

C715

C716

C717

C718

C719

C720

C721

C722

+1.25VS

1000P_0402_50V7K

C283

C426

C228

C255

C263

C132

C156

C625

C281

C434

1000P_0402_50V7K

0.1U_0402_10V6K

2 0.1U_0402_10V6K

0.1U_0402_10V6K

+1.25VS

C425

C671

C606

C456

C287

C474

C483

C635

C449

C510

0.1U_0402_10V6K

2 0.1U_0402_10V6K

0.1U_0402_10V6K

+1.25VS

C197

C662

C276

C149

C209

C424

0.1U_0402_10V6K

+1.25VS

C208

C169

C177

C220

C249

C440

C616

C219

C664

C642

0.1U_0402_10V6K

2 0.1U_0402_10V6K

0.1U_0402_10V6K

+1.25VS

C294

C244

C183

C187

C126

C427

C120

C270

C115

C439

0.1U_0402_10V6K

2 0.1U_0402_10V6K

0.1U_0402_10V6K

+1.25VS

C428

C225

C535

C194

C497

C528

0.1U_0402_10V6K

Compal Electronics, Inc.

Title

DDR SODIMM Decoupling

THIS SHEET OF ENGINEERINGDRAWINGIS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

Size

Document Number

R ev

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

LA-2051

1.0

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Friday, November 14, 2003

Sheet

o f

A				B							C					D									E										F					G	H
																																		CLK_BCLK		R1581		2@0_0402_5%		CLK_CPU_ITP 5
																																								CLK_CPU_ITP 5
														+3VS			+3V_CLK																	CLK_BCLK#		R1521		2@0_0402_5%		CLK_CPU_ITP# 5
														+3VS																										CLK_CPU_ITP# 5
															L7								0.1U_0402_10V6K		0.1U_0402_10V6K
														1		2							0.1U_0402_10V6K		0.1U_0402_10V6K
														HB-1M2012-121JT03_0805					Width=40C145mils 1				C141 1	C118 1		C95	1	C105		1			C89	1
																						2	2		2		2			2				2
																				10U_0805_10V4Z				0.1U_0402_10V6K				0.1U_0402_10V6K					0.1U_0402_10V6K
																						+3VS_VDDA
										1	R146 @10_0402_5%					U16	42 48		30 29 19 13 1 9
			38 EXCLK_CLKGEN							1		2				U16					VDDPCI VDDREF VDDXTAL																L4
			38 EXCLK_CLKGEN								1			1		XIN	VDDCPU	VDDSD VDDAGP VDD48M		VDDPCI					C104	1	C99	1	C90		1		C138	1	1		L4
											1			1		XIN	VDDCPU	VDDSD VDDAGP VDD48M		VDDPCI					C104	1	C99	1	C90		1		C138	1	1	C110
								C116			10P_0402_50V8K												VDDA	36			+3VS_VDDA						0.1U_0402_10V6K			1	2	+3VS
								C116			10P_0402_50V8K																									CHB2012U121_0805
									1		2	XTALIN_CLK			6
												Y2		R150										0.1U_0402_10V6K					0.1U_0402_10V6K							0.1U_0402_10V6K
																								0.1U_0402_10V6K					0.1U_0402_10V6K							0.1U_0402_10V6K
														@1M_0402_5%											VSSA	2		2			2			2	2
											2	XTALOUT_CLK		2									VSSA	37	VSSA		10U_0805_10V4Z
									1		2	XTALOUT_CLK			7	XOUT							VSSA
								C112		14.31818MHZ_20P_6X1430004201						XOUT							CPUT0	40	CLK_BCLK			R148	1			2	33_0402_5%					CLK_CPU_BCLK 4
				+3VS							10P_0402_50V8K												CPUT0															CLK_CPU_BCLK 4
																																	R147		1	2 49.9_0402_1%
				1	1		13,14,27		SMCLK						35	SCLK																	R139		1	2	49.9_0402_1%
				R577		R578	13,14,27		SMDATA						34	SDATA							CPUC0	39	CLK_BCLK#			R142	1			2	33_0402_5%					CLK_CPU_BCLK#		4
		10K_0402_5%				10K_0402_5%																	CPUC0															CLK_CPU_BCLK#		4
		10K_0402_5%				10K_0402_5%																			CLK_NB			R164					33_0402_5%
								17,27	VTT_PWRGD														CPUT1	44	CLK_NB			R164	1			2	33_0402_5%					CLK_NB_BCLK	10
				2	2			17,27	VTT_PWRGD														CPUT1															CLK_NB_BCLK	10
		R579		2	2								VTT_PWRGD		10																		R163		1	2	49.9_0402_1%
		R579	@0_0402_5%										VTT_PWRGD		10	VTTPWRGD/PD#																	R163		1	2	49.9_0402_1%
5,10,26,47	PM_STPCPU#	1		2											45	VTTPWRGD/PD#
5,10,26,47	PM_STPCPU#	1		2											45	CPU_STP#
26	PCI_STP#	1		2											12	PCI_STOP#																	R155		1	2	49.9_0402_1%
		R580	@0_0402_5%										PCI33/66#		26	24/48#SEL																	R155		1	2	49.9_0402_1%
															11	24/48#SEL
															11	PCI33/66#SEL								43	CLK_NB#			R156	1			2	33_0402_5%
																PCI33/66#SEL							CPUC1															CLK_NB_BCLK#	10


							R109	1		2	33_0402_5%		CLK_48M		27								SDRAMOUT	47	MEM_66M			R168	1			2	33_0402_5%					CLK_MEM_66M 10
			27	CLK_SB_48M												48MHz_1							SDRAMOUT															CLK_MEM_66M 10
																									AGP_66M			R125					33_0402_5%
															28									32					1			2						CLK_AGP_66M	10
															28	48MHz_0							AGPCLK0	32					1			2
																48MHz_0							AGPCLK0	31
																							AGPCLK1	31
																							AGPCLK1
		32	CLK_AUDIO_14M				R159	1		2	@33_0402_5%										FS3/PCICLK_F0			14	FS3			R115	1			2	33_0402_5%					CLK_ALINK_SB	26
		32	CLK_AUDIO_14M				R161	1		2	68_0402_5%		FS2		4						FS3/PCICLK_F0			15	FS4													CLK_ALINK_SB	26
		10		REFCLK1_NB			R161	1		2	68_0402_5%		FS2		4	FS2/REF2					FS4/PCICLK_F1			15	FS4
		10		REFCLK1_NB			R165	1		2	33_0402_5%		FS1		3	FS2/REF2					FS4/PCICLK_F1
			34 CLK_SIO_14M				R165	1		2	33_0402_5%		FS1		3	FS1/REF1
			34 CLK_SIO_14M				R174	1		2	33_0402_5%		FS0		2	FS1/REF1
			27	CLK_SB_14M			R174	1		2	33_0402_5%		FS0		2	FS0/REF0								16
			27	CLK_SB_14M												FS0/REF0							PCICLK0	16
			26	CLK_14M_APIC			R173	1		2	@33_0402_5%												PCICLK0	17
							R173	1		2	@33_0402_5%		CLK_IREF										PCICLK1	17
															38								PCICLK1	20
															38	IREF							PCICLK2	20
																IREF							PCICLK2	21
																							PCICLK3	21
												2											PCICLK3	22
												2											PCICLK4	22
														R144									PCICLK5	23
														R144									PCICLK5
														475_0402_1%			GNDXTAL	GNDREF GNDPCI GNDPCI		GND48M	GNDAGP GNDSD GNDCPU
												1					GNDXTAL	GNDREF GNDPCI GNDPCI		GND48M	GNDAGP GNDSD GNDCPU
																	8 5		18 24 25 33 46 41			ICS951402AGT_TSSOP48
																	8 5		18 24 25 33 46 41

CLOCK FREQUENCY SELECT TABLE

FS4

FS3

FS2

FS1

FS0

CPU

MEM

With Spread Enabled…

+3V_CLK

200

133

133 *

Spreaf OFF OR

R160

R124

R120

R127

100

Center spread +/-0.3%

@10K_0402_

@10K_0402_5%

10K_0402_5%

FS1

FS0

+3V_CLK

FS2

+3VS

FS3

FS4

PCI33/66#

R172

R167

R169

R171

R166

R170

R153

R121

R123

R133

10K_0402_5%

4.7K_0402_5%

10K_0402_5%

@10K_0402_5%

Note:

0 = PULL LOW

5,12

BSEL1

D20

RB751V_SOD323

1 = PULL HIGH

5,12

BSEL0

D21

RB751V_SOD323

A-LINK FREQ

PCI33/66# = HIGH

66MHZ

PCI33/66# = LOW

33MHZ

Compal Electronics, Inc.

Title

Clock Generator

THIS SHEET OF ENGINEERINGDRAWINGIS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

Size

Document Number

R ev

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

LA-2051

1.0

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Friday, November 14, 2003

Sheet

16 o f 51

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