Motorola SN54LS48J, SN74LS48D, SN74LS48N Datasheet

5-59

FAST AND LS TTL DATA

BCD TO 7-SEGMENT
DECODER

The SN54/74LS48 is a BCD to 7-Segment Decoder consisting of NAND
gates, input buffers and seven AND-OR-INVERT gates. Seven NAND gates
and one driver are connected in pairs to make BCD data and its complement
available to the seven decoding AND-OR-INVERT gates. The remaining
NAND gate and three input buffers provide lamp test, blanking input/ripple­blanking input for the LS48.

The circuit accepts 4-bit binary-coded-decimal (BCD) and, depending on
the state of the auxiliary inputs, decodes this data to drive other components.
The relative positive logic output levels, as well as conditions required at the
auxiliary inputs, are shown in the truth tables.

The LS48 circuit incorporates automatic leading and/or trailing edge
zero-blanking control (RBI and RBO). Lamp Test (LT) may be activated any
time when the BI /RBO node is HIGH. Both devices contain an overriding
blanking input (BI) which can be used to control the lamp intensity by varying
the frequency and duty cycle of the BI input signal or to inhibit the outputs.

• Lamp Intensity Modulation Capability (BI/RBO)

• Internal Pull-Ups Eliminate Need for External Resistors

• Input Clamp Diodes Eliminate High-Speed Termination Effects

14 13 12 11 10 9

1 2 3 4 5 6

V

CC

7

16 15

8

f g a b c d e

B C LT

BI/RBO RBI D A GND

CONNECTION DIAGRAM DIP (TOP VIEW)

LOGIC DIAGRAM

INPUT

BLANKING INPUT OR
RIPPLE-BLANKING
OUTPUT

RIPPLE-BLANKING
INPUT

LAMP-TEST
INPUT

A

B

C
D

a

b

c

d

e

f

g

OUTPUT

SN54/74LS48

BCD TO 7-SEGMENT

DECODER

LOW POWER SCHOTTKY

J SUFFIX

CERAMIC

CASE 620-09

N SUFFIX

PLASTIC

CASE 648-08

16

1

16

1

ORDERING INFORMATION

SN54LSXXJ Ceramic
SN74LSXXN Plastic
SN74LSXXD SOIC

16

1

D SUFFIX

SOIC

CASE 751B-03

LOGIC SYMBOL

VCC = PIN 16
GND = PIN 8

7 1 2 6 3 5

13 12 11 10 9 15 14 4

A B C D LT RBI

a b c d e f g

BI/
RBO

SN54/74LS48

NUMERICAL DESIGNATIONS — RESULTANT DISPLAYS

0 1 2 3 4 5 6 7 8 9 10 11 12 13

NOTES:
(1) B

I/RBO is wired-AND logic serving as blanking input (BI) and/or

ripple-blanking output (RBO

). The blanking out (BI) must be open
or held at a HIGH level when output functions 0 through 15 are
desired, and ripple-blanking input (RB

I) must be open or at a HIGH
level if blanking of a decimal 0 is not desired. X=input may be HIGH
or LOW.

(2) When a LOW level is applied to the blanking input (forced condition)

all segment outputs go to a LOW level, regardless of the state of any
other input condition.

(3) When ripple-blanking input (RBI

) and inputs A, B, C, and D are at
LOW level, with the lamp test input at HIGH level, all segment
outputs go to a HIGH level and the ripple-blanking output (RBO

)

goes to a LOW level (response condition).

(4) When the blanking input/ripple-blanking output (BI

/RBO) is open or
held at a HIGH level, and a LOW level is applied to lamp-test input,
all segment outputs go to a LOW level.

TRUTH TABLE

SN54/74LS48

INPUTS OUTPUTS

5-60

FAST AND LS TTL DATA

SN54/74LS48

PIN NAMES LOADING (Note a)

HIGH

LOW

A, B, C, D
RBI
LT
BI/RBO

BI

BCD Inputs
Ripple-Blanking (Active Low) Input
Lamp-Test (Active Low) Input
Blanking Input or Ripple­Blanking Output (Active Low)
Blanking (Active Low) Input

0.5 U.L.

0.5 U.L.

0.5 U.L.

0.5 U.L.

1.2 U.L.

0.5 U.L.

Open-Collector

0.25 U.L.

0.25 U.L.

0.25 U.L.

0.75 U.L.
2(1) U.L.

0.25 U.L.

3.75 (1.25) U.L. (48)

NOTES:
a) Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW
b) Outut current measured at V

OUT

= 0.5 V

Output LOW drive factor is SN54LS/74LS48: 1.25 U.L. for Military (54), 3.75 U.L. for Commercial (74).

DECIMAL

OR

FUNCTION

LT RBI D C B A BI /RBO a b c d e f g NOTE

0 H H L L L L H H H H H H H L 1
1 H X L L L H H L H H L L L L 1
2 H X L L H L H H H L H H L H
3 H X L L H H H H H H H L L H
4 H X L H L L H L H H L L H H
5 H X L H L H H H L H H L H H
6 H X L H H L H L L H H H H H
7 H X L H H H H H H H L L L L
8 H X H L L L H H H H H H H H

9 H X H L L H H H H H L L H H
10 H X H L H L H L L L H H L H
11 H X H L H H H L L H H L L H
12 H X H H L L H L H L L L H H
13 H X H H L H H H L L H L H H
14 H X H H H L H L L L H H H H
15 H X H H H H H L L L L L L L
BI X X X X X X L L L L L L L L 2

RBI H L L L L L L L L L L L L L 3

LT L X X X X X H H H H H H H H 4

14 15