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9-BIT HOLD
REGISTER
SY10E143
SY100E143
FEATURES
■ 700MHz min. operating frequency
■ Extended 100E VEE range of –4.2V to –5.5V
■ 9 bits wide for byte-parity applications
■ Asynchronous Master Reset
■ Dual clocks
■ Fully compatible with industry standard 10KH,
100K ECL levels
■ Internal 75kΩ input pulldown resistors
■ Fully compatible with Motorola MC10E/100E143
■ Available in 28-pin PLCC package
BLOCK DIAGRAM
D
D1
D2
D3
D4
D5
0
MUX
MUX
MUX
MUX
MUX
MUX
D
R
D
R
D
R
D
R
D
R
D
R
Q0
Q1
Q2
Q3
Q4
Q5
DESCRIPTION
The SY10/100E143 are high-speed 9-bit hold registers
designed for use in new, high-performance ECL systems.
The E143 can hold current data or load new data. The nine
inputs, D0-D8, accept parallel input data.
The SEL (Select) control pin serves to determine the
mode of operation; either HOLD or LOAD. The input data
has to meet the set-up time before being clocked into the
nine input registers on the rising edge of CLK1 or CLK2.
The MR (Master Reset) control signal asynchronously
resets all nine registers to a logic LOW when a logic HIGH
is applied to MR.
The E143 is designed for applications requiring highspeed registers, pipeline registers, synchronous operation,
and is also suitable for byte-wide parity.
PIN CONFIGURATION
6
D
D7
D8
PLCC
TOP VIEW
J28-1
D3
D4
VCCO
VCCO
D5
Q8
18
Q7
17
Q6
16
VCC
Q5
15
14
VCCO
13
Q4
12
Q3
Q1
Q0
Q2
MR
CLK
CLK2
VEE
NC
D0
D1
SEL
25 24 23 22 21 20 19
26
1
27
28
1
2
3
4
567891011
D2
D6
D7
D8
SEL
CLK1
CLK2
MR
MUX
MUX
MUX
D
R
D
R
Q6
Q7
PIN NAMES
Pin Function
D0-D8 Parallel Data Inputs
SEL Mode Select Input
D
R
Q8
CLK1, CLK2 Clock Inputs
MR Master Reset
Q0-Q8 Data Outputs
NC No Connection
V
CCO VCC to Output
Rev.: D Amendment: /0
1
Issue Date: August, 1998
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SY10E143
Micrel
SY100E143
TRUTH TABLE
SEL MODE
L LOAD
H HOLD
DC ELECTRICAL CHARACTERISTICS
VEE = VEE (Min.) to VEE (Max.); VCC = VCCO = GND
TA = 0°CTA = +25°CTA = +85°C
Symbol Parameter Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit Condition
IIH Input HIGH Current — — 150 — — 150 — — 150 µA—
EE Power Supply Current mA —
I
10E — 120 145 — 120 145 — 120 145
100E — 120 145 — 120 145 — 138 165
AC ELECTRICAL CHARACTERISTICS
VEE = VEE (Min.) to VEE (Max.); VCC = VCCO = GND
TA = 0°CTA = +25°CTA = +85°C
Symbol Parameter Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit Condition
fMAX Max. Toggle Frequency 700 900 — 700 900 — 700 900 — MHz —
t
PLH Propagation Delay to Output ps —
tPHL CLK 600 800 1000 600 800 1000 600 800 1000
MR 600 800 1000 600 800 1000 600 800 1000
S Set-up Time ps —
t
D 50 –100 — 50 –100 — 50 –100 —
SEL 300 150 — 300 150 — 300 150 —
H Hold Time ps —
t
D 300 100 — 300 100 — 300 100 —
SEL 75 –150 — 75 –150 — 75 –150 —
tRR Reset Recovery Time 900 700 — 900 700 — 900 700 — ps —
PW Minimum Pulse Width 400 — — 400 — — 400 — — ps —
t
CLK, MR
tskew Within-Device Skew — 75 — — 75 — — 75 — ps 1
t
r Rise/Fall Time 300 525 800 300 525 800 300 525 800 ps —
tf 20% to 80%
NOTE:
1. Within-device skew is defined as identical transitions on similar paths through a device.
PRODUCT ORDERING CODE
Ordering Package Operating
Code Type Range
SY10E143JC J28-1 Commercial
SY10E143JCTR J28-1 Commercial
SY100E143JC J28-1 Commercial
SY100E143JCTR J28-1 Commercial
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Micrel
28 LEAD PLCC (J28-1)
SY10E143
SY100E143
Rev. 03
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Micrel
SY10E143
SY100E143
MICREL-SYNERGY 3250 SCOTT BOULEVARD SANTA CLARA CA 95054 USA
TEL + 1 (408) 980-9191 FAX + 1 (408) 914-7878 WEB http://www.micrel.com
This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or
other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc.
© 2000 Micrel Incorporated
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