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6-BIT D
REGISTER
SY10E151
SY100E151
FEATURES
■ 1100MHz toggle frequency
■ Extended 100E V
EE range of –4.2V to –5.46V
■ Differential outputs
■ Asynchronous Master Reset
■ Dual clocks
■ Fully compatible with industry standard 10KH,
100K ECL levels
■ Internal 75KΩ input pulldown resistors
■ Fully compatible with Motorola MC10E/100E151
■ Available in 28-pin PLCC package
BLOCK DIAGRAM
D
0
D
R
D
1
D
R
D
2
D
R
D
3
D
R
D
4
D
Q
0
Q
0
Q
1
Q
1
Q
2
Q
2
Q
3
Q
3
Q
4
DESCRIPTION
The SY10/100E151 offer 6 edge-triggered, high-speed,
master-slave D-type flip-flops with differential outputs,
designed for use in new, high-performance ECL systems.
The two external clock signals (CLK
1, CLK2) are gated
through a logical OR operation before use as clocking
control for the flip-flops. Data is clocked into the flip-flops
on the rising edge of either CLK1 or CLK2 (or both). When
both CLK1 and CLK2 are at a logic LOW, data enters the
master and is transferred to the slave when either CLK1 or
CLK2 (or both) go HIGH.
The MR (Master Reset) signal operates asynchronously
to make all Q outputs go to a logic LOW.
PIN CONFIGURATION
2
1
5
5
NC
CLK
PLCC
J28-1
0Q0
Q
CCO
V
1
Q
Q
Q
18
Q
4
17
Q
4
16
V
CC
15
Q
3
14
Q
3
13
Q
2
12
Q
2
1
Q
CCO
V
CLK
MR
24 23 22 21 20 19
25
26
D
5
27
D
4
28
D
3
V
EE
1
D
2
2
D
1
3
D
0
4
TOP VIEW
567891011
NC
CCO
V
CLK
CLK
Q
R
D
5
D
R
1
2
M
R
4
Q
5
Q
5
PIN NAMES
Pin Function
D0–D5 Data Inputs
CLK1, CLK2 Clock Inputs
MR Master Reset
Q0–Q5 True Outputs
Q0–Q5 Inverting Outputs
V
CCO VCC to Output
Rev.: D Amendment: /0
1
Issue Date: November, 1998
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SY10E151
SY100E151
TRUTH TABLES
Asynchronous Operation
Dn CLK1 CLK2 MR Qn(t + 1)
XXXH L
NOTE:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
t = Time before positive CLK transition
t+1 = Time after positive CLK transition
u = LOW-to-HIGH transition
(1)
Inputs Output
Synchronous Operation
Inputs Output
Dn CLK1 CLK2 MR Qn(t + 1)
LuLL L
HuLL H
LLuL L
HLuL H
XHuL Qn(t)
XuHL Qn(t)
XLLL Q
DC ELECTRICAL CHARACTERISTICS
VEE = VEE (Min.) to VEE (Max.); VCC = VCCO = GND
TA = 0°CTA = +25°CTA = +85°C
Symbol Parameter Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit Condition
IIH Input HIGH Current ——150 ——150 ——150 µA —
EE Power Supply Current mA —
I
10E — 65 78 — 65 78 — 65 78
100E — 65 78 — 65 78 — 75 90
n(t)
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SY100E151
AC ELECTRICAL CHARACTERISTICS
VEE = VEE (Min.) to VEE (Max.); VCC = VCCO = GND
TA = 0°CTA = +25°CTA = +85°C
Symbol Parameter Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit Condition
fMAX Max. Toggle Frequency 1100 1400 — 1100 1400 — 1100 1400 — MHz —
PLH Propagation Delay to Output ps —
t
tPHL CLK 475 650 800 475 650 800 475 650 800
MR 475 650 850 475 650 850 475 650 850
tS Set-up Time, D 0 –175 — 0 –175 — 0 –175 — ps —
tH Hold Time, D 350 175 — 350 175 — 350 175 — ps —
tRR Reset Recovery Time 750 550 — 750 550 — 750 550 — ps —
PW Minimum Pulse Width 400 ——400 ——400 ——ps —
t
CLK, MR
tskew Within-Device Skew — 65 ——65 ——65 — ps 1
r Rise/Fall Time 300 450 700 300 450 700 300 450 700 ps —
t
tf 20% to 80%
NOTE:
1. Within-device skew is defined as identical transitions on similar paths through a device.
SY10E151
PRODUCT ORDERING CODE
Ordering Package Operating
Code Type Range
SY10E151JC J28-1 Commercial
SY10E151JCTR J28-1 Commercial
SY100E151JC J28-1 Commercial
SY100E151JCTR J28-1 Commercial
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Micrel
28 LEAD PLCC (J28-1)
SY10E151
SY100E151
Rev. 03
MICREL-SYNERGY 3250 SCOTT BOULEVARD SANTA CLARA CA 95054 USA
TEL + 1 (408) 980-9191 FAX + 1 (408) 914-7878 WEB http://www.micrel.com
This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or
other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc.
© 2000 Micrel Incorporated
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