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9-BIT BUFFER
A
A
SY100S322
FEATURES
■ Max. propagation delay of 700ps
■ IEE min. of –55mA
■ Extended supply voltage option:
VEE = –4.2V to –5.5V
■ Voltage and temperature compensation for
improved noise immunity
■ Internal 75KΩ input pull-down resistors
■ 70% faster than Fairchild 300K at lower power
■ Function and pinout compatible with Fairchild F100K
■ Available in 24-pin CERPACK and 28-pin PLCC
packages
BLOCK DIAGRAM
D
1
D
2
O
1
O
2
DESCRIPTION
The SY100S322 is an ultra-fast buffer designed for use
in high-performance ECL systems. The device provides
nine non-inverting buffers with single-ended outputs. The
inputs on the device have 75KΩ pull-down resistors.
PIN CONFIGURATIONS
D5
D4
VCC
O4O5O6
VEES
5
6
D6
D7
VEE
VEES
VCCA
D8
12
13
14
15
16
17
Top View
PLCC
J28-1
1911201021922823724
D3
D2
D1
VEES
VCCA
25
O3
O7
4
3
O8
VCCA
2
1
VCC
VCC
28
27
O9
2618
O2
1D9
O
VCC
D9
D8
VEED7D6
D
3
D
4
D
5
D
6
D
7
D
8
D
9
O
3
1
D1
D2
O
4
O
5
O
6
O
7
O
8
O
9
VCCA
D3
O3
O2
2
3
Top View
Flatpack
4
5
6
F24-1
7248239221021112012
O9O8O1
VCC
VCCA
19
18
17
16
15
14
13
O7
D5
D4
VCCA
O4
O5
O6
PIN NAMES
Pin Function
D1 – D9 Data Inputs
O1 – O9 Data Outputs
VEES VEE Substrate
V
CCA VCCO for ECL Outputs
Rev.: G Amendment: /0
1
Issue Date: July, 1999
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Micrel
SY100S322
LOGIC EQUATION
On = Dn, n = 1 to 9
DC ELECTRICAL CHARACTERISTICS
VEE = –4.2V to –5.5V unless otherwise specified, VCC = VCCA = GND
Symbol Parameter Min. Typ. Max. Unit Condition
IIH Input HIGH Current — — 200 µAVIN = VIH (Max.)
EE Power Supply Current –55 –41 –25 mA Inputs Open
I
AC ELECTRICAL CHARACTERISTICS
CERPACK
VEE = –4.2V to –5.5V unless otherwise specified, VCC = VCCA = GND
TA = 0°CTA = +25°CTA = +85°C
Symbol Parameter Min. Max. Min. Max. Min. Max. Unit Condition
PLH Propagation Delay 300 800 300 800 300 800 ps
t
tPHL Data to Output
TLH Transition Time 300 900 300 900 300 900 ps
t
tTHL 20% to 80%, 80% to 20%
PLCC
VEE = –4.2V to –5.5V unless otherwise specified, VCC = VCCA = GND
TA = 0°CTA = +25°CTA = +85°C
Symbol Parameter Min. Max. Min. Max. Min. Max. Unit Condition
PLH Propagation Delay 300 700 300 700 300 700 ps
t
tPHL Data to Output
TLH Transition Time 300 900 300 900 300 900 ps
t
tTHL 20% to 80%, 80% to 20%
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Micrel
TIMING DIAGRAM
SY100S322
INPUT
t
PHL
OUTPUT
t
TLH
Propagation Delay and Transition Times
NOTE:
VEE = –4.2V to –5.5V unless otherwise specified, VCC = VCCA = GND
20%
50%
80%
0.7 ± 0.1 ns0.7 ± 0.1 ns
50%
20%
t
PLH
80%
t
THL
–0.95V
–1.69V
PRODUCT ORDERING CODE
Ordering Package Operating
Code Type Range
SY100S322FC F24-1 Commercial
SY100S322JC J28-1 Commercial
SY100S322JCTR J28-1 Commercial
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Micrel
24 LEAD CERPACK (F24-1)
SY100S322
Rev. 03
4
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Micrel
28 LEAD PLCC (J28-1)
SY100S322
Rev. 03
MICREL-SYNERGY 3250 SCOTT BOULEVARD SANTA CLARA CA 95054 USA
TEL + 1 (408) 980-9191 FAX + 1 (408) 914-7878 WEB http://www.micrel.com
This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or
other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc.
© 2000 Micrel Incorporated
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