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QUINT DIFFERENTIAL
B
LINE RECEIVER
SY100S314
FEATURES
■ Max. propagation delay of 900ps
■ Differential outputs
■ I
EE min. of –60mA
■ Extended supply voltage option:
VEE = –4.2V to –5.5V
■ Voltage and temperature compensation for improved
noise immunity
■ VBB output for single-ended use
■ More than twice as fast as Fairchild
■ Function and pinout compatible with Fairchild F100K
■ Available in 24-pin CERPACK and 28-pin PLCC
packages
BLOCK DIAGRAM
D
a
D
a
D
b
D
b
D
c
D
c
D
d
O
a
O
a
O
b
O
b
O
c
O
c
O
d
DESCRIPTION
The SY100S314 offers five differential line receivers
with emitter follower outputs, designed for use in highperformance ECL systems. For single-ended operation,
the VBB reference voltage is available. In the single-ended
mode, the apparent input threshold of the true inputs is
30mV higher than the threshold of the complementary
inputs.
Common mode rejection of +1.0V is achieved through
the use of active current sources. If both the true and
complement inputs are at the same potential between VEE
and VCC, then the complementary outputs will take on a
logic HIGH state. Unlike the other members of the Synergy
300K family, the inputs on this device do not have pulldown resistors.
PIN CONFIGURATIONS
Da
Da
Oa
OaObOb
VEES
5
6
Db
Db
VEE
VEES
VBB
Dc
12
13
14
Top View
15
16
17
PLCC
J28-1
1911201021922823724
De
Dd
Dd
VEES
25
De
Oe
Oc
4
3
Oc
VCCA
2
1
VCC
VCC
28
27
Od
2618
Oe
O
cDc
D
dDc
B
V
VEEDbD
b
D
d
D
e
D
e
O
d
O
e
O
e
V
BB
PIN NAMES
Pin Function
Da – De Data Inputs
Da – De Inverting Data Inputs
Oa – Oe Data Outputs
Oa – Oe Complementary Data Outputs
VEES VEE Substrate
CCA VCCO for ECL Outputs
V
19
CCA
V
18
D
a
17
D
a
16
O
a
15
O
a
14
O
b
13
O
b
c
c
O
O
1
D
d
D
d
2
3
D
e
D
e
O
e
O
e
1
Top View
Flatpack
4
5
6
F24-1
7248239221021112012
d
d
O
CC
O
V
Rev.: G Amendment: /0
Issue Date: July, 1999
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Micrel
LOGIC EQUATION
O = D
DC ELECTRICAL CHARACTERISTICS
VEE = –4.2V to –5.5V unless otherwise specified, VCC = VCCA = GND
Symbol Parameter Min. Typ. Max. Unit Condition
VDIFF Input Voltage Differential 150 — — mV Required for Full Output Swing
CM Common Mode Voltage — — 1.0 V Permissible ±VCM with
V
Respect to VBB
IIH Input HIGH Current — — 50 µAVIN = VIH (Max.), Da - De =
VBB, Da - De = VIL (Min.)
CBO Input Leakage Current –10 — — µAVIN = VEE, Da - De = VBB,
I
Da - De = VIL (Min.)
EE Power Supply Current –60 –45 –30 mA Da - De = VBB, Da - De = VIL (Min.)
I
AC ELECTRICAL CHARACTERISTICS
SY100S314
CERPACK
VEE = –4.2V to –5.5V unless otherwise specified, VCC = VCCA = GND
T
A = 0°CTA = +25°CTA = +85°C
Symbol Parameter Min. Max. Min. Max. Min. Max. Unit Condition
t
PLH Propagation Delay 300 1000 300 1000 300 1000 ps
tPHL Data to Output
TLH Transition Time300 900 300 900 300 900 ps
t
tTHL 20% to 80%, 80% to 20%
PLCC
VEE = –4.2V to –5.5V unless otherwise specified, VCC = VCCA = GND
TA = 0°CTA = +25°CTA = +85°C
Symbol Parameter Min. Max. Min. Max. Min. Max. Unit Condition
t
PLH Propagation Delay 300 900 300 900 300 900 ps
tPHL Data to Output
TLH Transition Time 300 900 300 900 300 900 ps
t
tTHL 20% to 80%, 80% to 20%
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Micrel
TIMING DIAGRAM
SY100S314
INPUT
t
TRUE
OUTPUT
COMPLEMENT
NOTE:
VEE = –4.2V to –5.5V unless otherwise specified, VCC = VCCA = GND
PHL
t
PLH
t
TLH
Propagation Delay and Transition Times
20%
50%
80%
0.7 ± 0.1 ns0.7 ± 0.1 ns
50%
80%
50%
t
PLH
t
PHL
20%
t
THL
–0.95V
–1.69V
PRODUCT ORDERING CODE
Ordering Package Operating
Code Type Range
SY100S314FC F24-1 Commercial
SY100S314JC J28-1 Commercial
SY100S314JCTR J28-1 Commercial
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Micrel
24 LEAD CERPACK (F24-1)
SY100S314
Rev. 03
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Micrel
28 LEAD PLCC (J28-1)
SY100S314
Rev. 03
MICREL-SYNERGY 3250 SCOTT BOULEVARD SANTA CLARA CA 95054 USA
TEL + 1 (408) 980-9191 FAX + 1 (408) 914-7878 WEB http://www.micrel.com
This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or
other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc.
© 2000 Micrel Incorporated
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