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QUINT EXCLUSIVE
D
2d
D2cD
1c
V
EE
D2bD
1b
D
1a
O
a
O
a
O
b
O
b
D
1e
O
d
O
e
17
16
15
14
13
1
2
3
4
5
6
7248239221021112012
19
Top View
Flatpack
F24-1
V
CC
V
CCA
F
O
c
O
d
O
c
OR/NOR GATE
SY100S307
FEATURES
■ Max. propagation delay of 1000ps
■ IEE min. of –58mA
■ Extended supply voltage option:
VEE = –4.2V to –5.5V
■ Voltage and temperature compensation for improved
noise immunity
■ Internal 75KΩ input pull-down resistors
■ 50% faster than Fairchild 300K at lower power
■ Function and pinout compatible with Fairchild F100K
■ Available in 24-pin CERPACK and 28-pin PLCC
packages
BLOCK DIAGRAM
F
DESCRIPTION
The SY100S307 is an ultra-fast quint exclusive-OR/
NOR gate designed for use in high-performance ECL
systems. A function output that is the wire-OR result of the
exclusive-OR outputs is also available. The inputs on the
device have 75KΩ pull-down resistors.
PIN CONFIGURATIONS
D2a
D1a
Oa
OaObOb
VEES
5
6
D1b
D2b
VEE
VEES
D1c
D2c
12
13
14
15
16
17
Top View
PLCC
J28-1
1911201021922823724
D2e
D1eOeD1d
VEES
25
Oe
Oc
4
3
Oc
VCCA
2
1
VCC
V
CC
28
27
F
2618
Od
dD2d
O
O
D
1a
D
2a
D
1b
D
2b
D
1c
D
2c
D
1d
D
2d
D
1e
D
2e
a
D
D
O
a
O
b
O
b
O
c
O
c
O
d
O
d
O
e
O
e
PIN NAMES
1d
D
2e
O
e
18
2a
Pin Function
Dna – Dne Data Inputs (n-1...5)
E Enable Input
Oa – Oe Data Outputs
Oa – Oe Complementary Data Outputs
VEES VEE Substrate
CCA VCCO for ECL Outputs
V
1
Rev.: G Amendment: /0
Issue Date: July, 1999
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Micrel
LOGIC EQUATION
F = (D1a ⊕ D2a) + (D1b ⊕ D2b) + (D1c ⊕ D2c) + (D1d ⊕ D2d)
+ (D1e ⊕ D2e).
DC ELECTRICAL CHARACTERISTICS
VEE = –4.2V to –5.5V unless otherwise specified, VCC = VCCA = GND
Symbol Parameter Min. Typ. Max. Unit Condition
I
IH Input HIGH Current µAVIN = VIH (Max.)
D2a — D2e ——200
D2a — D2e ——250
EE Power Supply Current –58 –40 –27 mA Inputs Open
I
AC ELECTRICAL CHARACTERISTICS
CERPACK
VEE = –4.2V to –5.5V unless otherwise specified, VCC = VCCA = GND
SY100S307
TA = 0°CTA = +25°CTA = +85°C
Symbol Parameter Min. Max. Min. Max. Min. Max. Unit Condition
PLH Propagation Delay 200 1100 200 1150 200 1100 ps
t
tPH2 D2a — D2e to O, O
PLH Propagation Delay 200 1000 200 950 200 1000 ps
t
tPHL D1a — D1e to O, O
PLH Propagation Delay 300 1525 300 1525 300 1525 ps
t
tPHL Data to F
TLH Transition Time 300 900 300 900 300 900 ps
t
tTHL 20% to 80%, 80% to 20%
PLCC
VEE = –4.2V to –5.5V unless otherwise specified, VCC = VCCA = GND
TA = 0°CTA = +25°CTA = +85°C
Symbol Parameter Min. Max. Min. Max. Min. Max. Unit Condition
PLH Propagation Delay 300 1000 300 1000 300 1000 ps
t
tPH2 D2a — D2e to O, O
PLH Propagation Delay 300 900 300 900 300 930 ps
t
tPHL D1a — D1e to O, O
t
PLH Propagation Delay 300 1425 300 1425 300 1425 ps
tPHL Data to F
TLH Transition Time 3 00 900 300 900 300 900 ps
t
tTHL 20% to 80%, 80% to 20%
2
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Micrel
TIMING DIAGRAM
SY100S307
INPUT
t
TRUE
OUTPUT
COMPLEMENT
NOTE:
VEE = –4.2V to –5.5V unless otherwise specified, VCC = VCCA = GND
PHL
t
PLH
t
TLH
Propagation Delay and Transition Times
20%
50%
80%
0.7 ± 0.1 ns0.7 ± 0.1 ns
50%
80%
50%
t
PLH
t
PHL
20%
t
THL
–0.95V
–1.69V
PRODUCT ORDERING CODE
Ordering Package Operating
Code Type Range
SY100S307FC F24-1 Commercial
SY100S307JC J28-1 Commercial
SY100S307JCTR J28-1 Commercial
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Micrel
24 LEAD CERPACK (F24-1)
SY100S307
Rev. 03
4
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Micrel
28 LEAD PLCC (J28-1)
SY100S307
Rev. 03
MICREL-SYNERGY 3250 SCOTT BOULEVARD SANTA CLARA CA 95054 USA
TEL + 1 (408) 980-9191 FAX + 1 (408) 914-7878 WEB http://www.micrel.com
This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or
other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc.
© 2000 Micrel Incorporated
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