Datasheet S6B0716X01-C0C8, S6B0716X11-C0C8 Datasheet (Samsung)

of this document may be reproduced or
transmitted in any form or by any means, electronic or mechanical, for any purpose, without the express written
permission of LCD Driver IC Team.

S6B0716

33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD

January.2000

Ver. 3.0

Prepared by: Jae-Su, Ko

[e-mail]

Contents in this document are subject to change without notice. No part

33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD S6B0716

S6B0716 Specification Revision History

Version Content Date

0.0 Original

1.0

2.0 Reference voltage is only fixed VREF = 2.1V Mar.1999

2.1 Reference voltage could be used both VREF = 1.9V and VREF = 2.1V May.1999

COM PAD NAME modify (reference PAD Center Coordinate)
Reference voltage [VREF1]: 2.0V -> 2.1V (reference DC Characteristics)

3.0 Change VDD Range : 2.4V to 5.5V → 2.4V to 3.6V Jan.2000

2

S6B0716 33COM/100SEG DRIVER & CONTROLLER FOR STN LCD

CO

NTENTS

INTRODUCTION.................................................................................................................................................. 1

FEATURES ......................................................................................................................................................... 1

BLOCK DIAGRAM.............................................................................................................................................. 3

PAD CONFIGURATION....................................................................................................................................... 4

PAD CENTER COORDINATES........................................................................................................................... 5

PIN DESCRIPTION.............................................................................................................................................. 7

POWER SUPPLY......................................................................................................................................... 7

LCD DRIVER SUPPLY................................................................................................................................. 7

SYSTEM CONTROL .................................................................................................................................... 8

MICROPROCESSOR INTERFACE .............................................................................................................. 9

LCD DRIVER OUTPUTS.............................................................................................................................11

TEST PINS ..................................................................................................................................................11

FUNCTIONAL DESCRIPTION............................................................................................................................12

MICROPROCESSOR INTERFACE .............................................................................................................12

DISPLAY DATA RAM (DDRAM)..................................................................................................................16

LCD DISPLAY CIRCUITS ............................................................................................................................19

LCD DRIVER CIRCUIT................................................................................................................................21

POWER SUPPLY CIRCUITS.......................................................................................................................22

REFERECE CIRCUIT EXAMPLES..............................................................................................................28

RESET CIRCUIT.........................................................................................................................................29

INSTRUCTION DESCRIPTION...........................................................................................................................30

SPECIFICATIONS..............................................................................................................................................43

ABSOLUTE MAXIMUM RATINGS...............................................................................................................43

DC CHARACTERISTICS.............................................................................................................................44

REFERENCE DATA....................................................................................................................................47

AC CHARACTERISTICS.............................................................................................................................49

REFERENCE APPLICATIONS...........................................................................................................................53

MICROPROCESSOR INTERFACE .............................................................................................................53

3

S6B0716 33COM/100SEG DRIVER & CONTROLLER FOR STN LCD

INTRODUCTION

The S6B0716 is a driver & controller LSI for graphic dot-matrix liquid crystal display systems. It contains 33 common
and 100 segment driver circuits. This chip is connected directly to a microprocessor, accepts serial or 8-bit parallel
display data and stores in an on-chip display data RAM of 65 x 132 bits. It provides a highly-flexible display section
due to 1-to-1 correspondence between on-chip display data RAM bits and LCD panel pixels. And it performs display
data RAM read/write operation with no external operating clock to minimize power consumption. In addition,
because it contains power supply circuits necessary to drive liquid crystal, it is possible to make a display system
with the fewest components.

FEATURES

Driver Output Circuits

− 33 common outputs / 100 segment outputs
On-chip Display Data RAM

− Capacity: 65 x 132 = 8,580 bits

− Bit data "1": a dot of display is illuminated

− Bit data "0": a dot of display is not illuminated

Multi-chip Operation (Master, Slave) Available
Applicable Duty-ratios

Duty ratio Applicable LCD bias Maximum display area

1/33 1/5 or 1/6

Microprocessor Interface

− 8-bit parallel bi-directional interface with 6800-series or 8080-series

− Serial interface (only write operation) available

Various Instruction Setting
On-chip Oscillator Circuit
On-chip Low Power Supply for LCD Driving Voltage Generation

− Voltage converter (x2, x3, x4)

− Voltage regulator (Temperature coefficient: -0.05%/°C, -0.2%/°C)

− Voltage follower (LCD Bias: 1/5 or 1/6)

On-chip Electronic Contrast Control Function (32 steps)
Operating Voltage Range

− Supply voltage (VDD): 2.4 to 3.6 V

− LCD driving voltage (VLCD = V0 - VSS): 4.0 to 15.0 V

Low Power Consumption

− 100 µΑ Typ. (VDD = 3V, x4 boosting, V0 = 8V, Internal power supply ON and display OFF)

− 10 µΑ Max. (standby mode)

Wide Operating Temperature Range

33 × 100

− Ta = -40°C to +85°C

CMOS Process
Package Type

− Bare die for COB

1

33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD S6B0716

Series Specifications

Product code TEMPS pin Temp. coefficient

S6B0716X01-C0C8

S6B0716X11-C0C8

(VSS connected)

(VDD connected)

0

1

-0.05%/°C 300 µm

-0.2%/°C

Package Chip thickness

COB

300 µm

2

S6B0716 33COM/100SEG DRIVER & CONTROLLER FOR STN LCD

V

DB0

DB1

COMS

COM31

BLOCK DIAGRAM

SEG99

SEG98

SEG66

SEG65

VDD

V0
V1
V2
V3
V4

SS

SEG64

SEG1

SEG0

:

100 SEGMENT

DRIVER CIRCUITS

:

COM1

COM0

DRIVER CIRCUITS

:

:

33 COMMON

V0

VR

TEMPS

VOUT

C1-

C1+

C2-

C2+

C3-

C3+

V / F

CIRCUIT

V / R

CIRCUIT

V / C

CIRCUIT

PAGE

ADDRESS

CIRCUIT

I/O

BUFFER

DISPLAY DATA

CONTROL CIRCUIT

DISPLAY DATA RAM

65 X 132 = 8,580 Bits

COLUMN ADDRESS

CIRCUIT

STATUS REGISTER INSTRUCTION REGISTER

COMMON OUTPUT
CONTROL CIRCUIT

LINE

ADDRESS

CIRCUIT

INSTRUCTION DECODERBUS HOLDER

DISPLAY

TIMING

GENERATOR

CIRCUIT

OSCILLATOR

MS
CL
M
FRS
DISP

TESTL2

TESTL1

MPU INTERFACE (PARALLEL & SERIAL)

DB2

DB3

DB4

DB5

DB6(SCLK)

DB7(SID)

MI

RESETB

PS

RW_WR

E_RD

RS

CS2

CS1B

Figure 1. Block Diagram

3

33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD S6B0716

88

138

87

139

52

17451 1

рррррррррррр

- - -

рррррррррррр

рррррррррррр

- - -

рррррррррррр

S6B0716

PAD CONFIGURATION

ррр ррррррррррррррррррр

рррррррррррррррррррррр

Figure 2. S6B0716 Chip Configuration

- - - - - - - - - -

(TOP VIEW)

Y

(0,0)

- - - - - - - - - -

ррррррррррррррррррр

X

ððð

ррррррррррррррррррррррр

Table 1. S6B0716 Pad Dimensions

Size

Item Pad No.

X Y

Chip size - 5950 4300
Pad pitch All pad 110

Pad center size All pad 90 x 90

Chip thickness - 300

Unit

µm

4

S6B0716 33COM/100SEG DRIVER & CONTROLLER FOR STN LCD

PAD CENTER COORDINATES

Table 2. Pad Center Coordinates

[Unit: µm]

No. Name X Y No. Name X Y No. Name X Y

1 COM28 -2750 -2046 51 COM11 2750 -2046 101 SEG38 1320 2046
2 COM29 -2640 -2046 52 COM10 2871 -1925 102 SEG39 1210 2046
3 COM30 -2530 -2046 53 COM9 2871 -1815 103 SEG40 1100 2046
4 COM31 -2420 -2046 54 COM8 2871 -1705 104 SEG41 990 2046
5 COMS -2310 -2046 55 COM7 2871 -1595 105 SEG42 880 2046
6 TESTL1 -2200 -2046 56 COM6 2871 -1485 106 SEG43 770 2046
7 FRS -2090 -2046 57 COM5 2871 -1375 107 SEG44 660 2046
8 M -1980 -2046 58 COM4 2871 -1265 108 SEG45 550 2046

9 CL -1870 -2046 59 COM3 2871 -1155 109 SEG46 440 2046
10 DISP -1760 -2046 60 COM2 2871 -1045 110 SEG47 330 2046
11 MS -1650 -2046 61 COM1 2871 -935 111 SEG48 220 2046
12 RESETB -1540 -2046 62 COM0 2871 -825 112 SEG49 110 2046
13 PS -1430 -2046 63 SEG0 2871 -715 113 SEG50 0 2046
14 CS1B -1320 -2046 64 SEG1 2871 -605 114 SEG51 -110 2046
15 CS2 -1210 -2046 65 SEG2 2871 -495 115 SEG52 -220 2046
16 MI -1100 -2046 66 SEG3 2871 -385 116 SEG53 -330 2046
17 RS -990 -2046 67 SEG4 2871 -275 117 SEG54 -440 2046
18 RW_WR -880 -2046 68 SEG5 2871 -165 118 SEG55 -550 2046
19 E_RD -770 -2046 69 SEG6 2871 -55 119 SEG56 -660 2046
20 VDD -660 -2046 70 SEG7 2871 55 120 SEG57 -770 2046
21 DB0 -550 -2046 71 SEG8 2871 165 121 SEG58 -880 2046
22 DB1 -440 -2046 72 SEG9 2871 275 122 SEG59 -990 2046
23 DB2 -330 -2046 73 SEG10 2871 385 123 SEG60 -1100 2046
24 DB3 -220 -2046 74 SEG11 2871 495 124 SEG61 -1210 2046
25 DB4 -110 -2046 75 SEG12 2871 605 125 SEG62 -1320 2046
26 DB5 0 -2046 76 SEG13 2871 715 126 SEG63 -1430 2046
27 DB6 110 -2046 77 SEG14 2871 825 127 SEG64 -1540 2046
28 DB7 220 -2046 78 SEG15 2871 935 128 SEG65 -1650 2046
29 VSS 330 -2046 79 SEG16 2871 1045 129 SEG66 -1760 2046
30 VOUT 440 -2046 80 SEG17 2871 1155 130 SEG67 -1870 2046
31 CAP3P 550 -2046 81 SEG18 2871 1565 131 SEG68 -1980 2046
32 CAP3M 660 -2046 82 SEG19 2871 1375 132 SEG69 -2090 2046
33 CAP1P 770 -2046 83 SEG20 2871 1485 133 SEG70 -2200 2046
34 CAP1M 880 -2046 84 SEG21 2871 1595 134 SEG71 -2310 2046
35 CAP2P 990 -2046 85 SEG22 2871 1705 135 SEG72 -2420 2046
36 CAP2M 1100 -2046 86 SEG23 2871 1815 136 SEG73 -2530 2046
37 V0 1210 -2046 87 SEG24 2871 1925 137 SEG74 -2640 2046
38 VR 1320 -2046 88 SEG25 2750 2046 138 SEG75 -2750 2046
39 VSS 1430 -2046 89 SEG26 2640 2046 139 SEG76 -2871 1925
40 V1 1540 -2046 90 SEG27 2530 2046 140 SEG77 -2871 1815
41 V2 1650 -2046 91 SEG28 2420 2046 141 SEG78 -2871 1705
42 V3 1760 -2046 92 SEG29 2310 2046 142 SEG79 -2871 1595
43 V4 1870 -2046 93 SEG30 2200 2046 143 SEG80 -2871 1485
44 V0 1980 -2046 94 SEG31 2090 2046 144 SEG81 -2871 1375
45 TEMPS 2090 -2046 95 SEG32 1980 2046 145 SEG82 -2871 1265
46 TESTL2 2200 -2046 96 SEG33 1870 2046 146 SEG83 -2871 1155
47 COM15 2310 -2046 97 SEG34 1760 2046 147 SEG84 -2871 1045
48 COM14 2420 -2046 98 SEG35 1650 2046 148 SEG85 -2871 935
49 COM13 2530 -2046 99 SEG36 1540 2046 149 SEG86 -2871 825
50 COM12 2640 -2046 100 SEG37 1430 2046 150 SEG87 -2871 715

5

33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD S6B0716

Table 2. Pad Center Coordinates (Continued)

[Unit: µm]

NO. Name X Y NO. Name X Y NO. Name X Y

151 SEG88 -2871 605
152 SEG89 -2871 495
153 SEG90 -2871 385
154 SEG91 -2871 275
155 SEG92 -2871 165
156 SEG93 -2871 55
157 SEG94 -2871 -55
158 SEG95 -2871 -165
159 SEG96 -2871 -275
160 SEG97 -2871 -385
161 SEG98 -2871 -495
162 SEG99 -2871 -605
163 COM16 -2871 -715
164 COM17 -2871 -825
165 COM18 -2871 -935
166 COM19 -2871 -1045
167 COM20 -2871 -1155
168 COM21 -2871 -1265
169 COM22 -2871 -1375
170 COM23 -2871 -1485
171 COM24 -2871 -1595
172 COM25 -2871 -1705
173 COM26 -2871 -1815
174 COM27 -2871 -1925

6

S6B0716 33COM/100SEG DRIVER & CONTROLLER FOR STN LCD

PIN DESCRIPTION

POWER SUPPLY

Table 3. Power Supply Pin Description

Name I/O Description

VDD Supply Power supply

VSS Supply Ground

LCD driver supply voltages
The voltage determined by LCD pixel is impedance-converted by an operational amplifier

for application.

V0
V1
V2
V3
V4

I/O

Voltages should have the following relationship;
V0 ≥ V1 ≥ V2 ≥ V3 ≥ V4 ≥ VSS
When the internal power circuit is active, these voltages are generated as following table
according to the state of LCD Bias.

LCD bias V1 V2 V3 V4

1/6 bias (5/6) x V0 (4/6) x V0 (2/6) x V0 (1/6) x V0
1/5 bias (4/5) x V0 (3/5) x V0 (2/5) x V0 (1/5) x V0

LCD DRIVER SUPPLY

Table 4. LCD Driver Supply Pin Description

Name I/O Description

C1- O Capacitor 1 negative connection pin for voltage converter

C1+ O Capacitor 1 positive connection pin for voltage converter

C2- O Capacitor 2 negative connection pin for voltage converter

C2+ O Capacitor 2 positive connection pin for voltage converter

C3- O Capacitor 3 negative connection pin for voltage converter

C3+ O Capacitor 3 positive connection pin for voltage converter

VOUT I/O Voltage converter input / output pin

VR I V0 voltage adjustment pin

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33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD S6B0716

SYSTEM CONTROL

Table 5. System Control Pin Description

Name I/O Description

Master / slave operation select pin

− MS = "H": master operation

− MS = "L": slave operation

The following table depends on the MS status.

MS I

CL I/O

M I/O

FRS O

DISP I/O

TEMPS I

MS

H Enabled Input Output Output Output Output

L Disabled Disabled Input Input Output Input

Display clock input / output pin
When the S6B0716 is used in master/slave mode (multi-chip), the CL pins must be
connected each other for sync.

LCD AC signal input / output pin
When the S6B0716 is used in master/slave mode (multi-chip), the M pins must be
connected each other.

− MS = “H” : output

− MS = “L” : input

Static driver segment output pin
This pin is used together with the M pin.

LCD display blanking control input / output
When S6B0716 is used in master/slave mode (multi-chip), the DISP pins must be
connected each other.

− MS = “H” : output

− MS = “L” : input

Selects temperature coefficient of the reference voltage

− TEMPS = "L": -0.05%/°C

− TEMPS = "H": -0.2%/°C

OSC

circuit

Power
supply

circuit

CL M FRS DISP

8

S6B0716 33COM/100SEG DRIVER & CONTROLLER FOR STN LCD

MICROPROCESSOR INTERFACE

Table 6. Microprocessor Interface Pin Description

Name I/O Description

RESETB

PS I

MI I

CS1B

CS2

RS I

RW_WR

Reset input pin

I

When RESETB is “L”, initialization is executed.
Parallel / Serial data input select input

PS

Interface

mode

H Parallel

L Serial

Chip

select

CS1B,

CS2

CS1B,

CS2

Data /

instruction

RS DB0 to DB7

Data Read / Write Serial clock

RW_WR

RS SID (DB7) Write only SCLK (DB6)

*NOTE: In serial mode, it is impossible to read data from the on-chip RAM.
And DB0 to DB5 are high impedance and E_RD and RW_WR must
be fixed to either “H” or “L”.

Microprocessor interface select input pin

− MI = "H": 6800-series MPU interface

− MI = "L": 8080-series MPU interface

Chip select input pins

I

Data / instruction I/O is enabled only when CS1B is “L” and CS2 is “H”.
When chip select is non-active, DB0 to DB7 may be high impedance.

Register select input pin

− RS = "H": DB0 to DB7 are display data

− RS = "L": DB0 to DB7 are control data

Read / Write execution control pin

MI MPU Type RW_WR Description

Read / Write control input pin

H 6800-series

I

RW

− RW = “H”: read

− RW = “L”: write

Write enable clock input pin

L 8080-series

/WR

The data on DB0 to DB7 are latched at the rising
edge of the /WR signal.

E_RD

-

9

33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD S6B0716

Table 6. Microprocessor Interface Pin Description (Continued)

Name I/O Description

Read / Write execution control pin

MI MPU Type E_RD Description

Read / Write control input pin

− RW = “H”: When E is “H”, DB0 to DB7 a re in an

E_RD I

H 6800-series

E

output status.

− RW = “L”: The data on DB0 to DB7 are latched at
the falling edge of the E signal.

DB0

to

DB7

I/O

L 8080-series

/RD

Read enable clock input pin
When /RD is “L”, DB0 to DB7 are in an output status.

8-bit bi-directional data bus that is connected to the standard 8-bit microprocessor data
bus. When the serial interface selected (PS = "L");

− DB0 to DB5: high impedance

− DB6: serial input clock (SCLK)

− DB7: serial input data (SID)

When chip select is not active, DB0 to DB7 may be high impedance.

10

S6B0716 33COM/100SEG DRIVER & CONTROLLER FOR STN LCD

LCD DRIVER OUTPUTS

Table 7. LCD Driver Outputs Pin Description

Name I/O Description

LCD segment driver outputs
The display data and the M signal control the output voltage of segment driver.

SEG0

to

SEG99

COM0

to

COM31

COMS O

O

O

Display data M

Segment driver output voltage

Normal display Reverse display
H H V0 V2
H L VSS V3

L H V2 V0
L L V3 VSS

Power save mode VSS VSS

LCD common driver outputs
The internal scanning data and M signal control the output voltage of common driver.

Scan data M Common driver output voltage

H H VSS
H L V0

L H V1
L L V4

Power save mode VSS

Common output for the icons. The output signals of two pins are same. When not used,
these pins should be left open. In multi-chip (master / slave) mode, all COMS pins on both
master and slave units are the same signal.

TEST PINS

Table 8. Test Pin Description

Name I/O Description

TESTL1
TESTL2

IC test pins with pull-up

I

These pins should be opened (floated).

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33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD S6B0716

FUNCTIONAL DESCRIPTION

MICROPROCESSOR INTERFACE

Chip Select Input

There are CS1B and CS2 pins for chip selection. The S6B0716 can interface with an MPU only when CS1B is “L”
and CS2 is “H”. When these pins are set to any othe r combination, RS, E_RD, and RW_WR inputs are disabled and
DB0 to DB7 are to be high impedance. And, in case of serial interface, the internal shift register and the counter are
reset.

Parallel / Serial Interface

S6B0716 has three types of interface with an MPU, which are one serial and two parallel interfaces. This parallel or
serial interface is determined by PS pin as shown in table 9.

Table 9. Parallel / Serial Interface Mode.

PS Type CS1B CS2 MI Interface mode

H Parallel CS1B CS2

L Serial CS1B CS2

Parallel Interface (PS = "H")

The 8-bit bi-directional data bus is used in parallel interface and the type of MPU is selected by MI as shown in table

10. The type of data transfer is determined by signals at RS, E_RD and RW_WR as shown in table 11.

Table 10. Microprocessor Selection for Parallel Interface

MI CS1B CS2 RS E_RD RW_WR

H CS1B CS2 RS E RW DB0 to DB7 6800-series

L CS1B CS2 RS /RD /WR DB0 to DB7 8080-series

Table 11. Parallel Data Transfer

Common

RS

H H H L H Display data read out
H H L H L Display data write

L H H L H Register status read
L H L H L Writes to internal register (instruction)

6800-series 8080-series

E_RD

(E)

RW_WR

(RW)

E_RD

(/RD)

RW_WR

(/WR)

H 6800-series MPU mode
L 8080-series MPU mode

*×

DB0 to DB7 MPU bus

Description

Serial-mode

*×: Don't care

12

S6B0716 33COM/100SEG DRIVER & CONTROLLER FOR STN LCD

Serial Interface (PS = "L")

When the S6B0716 is active, serial data (DB7) and serial clock (DB6) inputs are enabled. And not active, the internal
8-bit shift register and the 3-bit counter are reset. Serial data can be read on the rising edge of serial clock going into
DB6 and processed as 8-bit parallel data on the eighth serial clock. Serial data input is display data when RS is high
and control data when RS is low. Since the clock signal (DB6) is easy to be affected by the external noise caused by
the line length, the operation check on the actual machine is recommended.

CS1B

CS2

SID

SCLK

RS

DB6DB7DB0DB1DB2DB3DB4DB5DB6DB7

Figure 3. Serial Interface Timing

Busy Flag

The Busy Flag indicates whether the S6B0716 is operating or not. When DB7 is “H” in read status operation, this
device is in busy status and will accept only read status instruction. If the cycle time is correct, the microprocessor
needs not to check this flag before each instruction, which improves the MPU performance.

13

33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD S6B0716

Data Transfer

The S6B0716 uses bus holder and internal data bus for Data Transfer with the MPU. When writing data from the
MPU to on-chip RAM, data is automatically transferred from the bus holder to the RAM as shown in figure 4. And
when reading data from on-chip RAM to the MPU, the data for the initial read cycle is stored in the bus holder
(dummy read) and the MPU reads this stored data from bus holder for the next data read cycle as shown in figure 5.
This means that a dummy read cycle must be inserted between each pair of address sets when a sequence of
address sets is executed. Therefore, the data of the specified address cannot be output with the read display data
instruction right after the address sets, but can be output at the second read of data.

MPU signals

RS

/WR

DB0 to DB7

Internal signals

/WR

BUS HOLDER

COLUMN ADDRESS

N D(N) D(N+1) D(N+2) D(N+3)

N D(N) D(N+1) D(N+2) D(N+3)

N N+1 N+2 N+3

Figure 4. Write Timing

14

S6B0716 33COM/100SEG DRIVER & CONTROLLER FOR STN LCD

N

D(N)

D(N+1)

D(N+2)

N

N+1

N+2

N+3

MPU signals

RS

/WR

/RD

DB0 to DB7

Internal signals

/WR

/RD

BUS HOLDER

COLUMN ADDRESS

N

Dummy D(N) D(N+1)

Figure 5. Read Timing

15

33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD S6B0716

DISPLAY DATA RAM (DDRAM)

The Display Data RAM stores pixel data for the LCD. It is 65-row by 132-column addressable array. Each pixel can
be selected when the page and column addresses are specified. The 65 rows are divided into 8 pages of 8 lines and
the 9th page with a single line (DB0 only). Data is read from or written to the 8 lines of each page directly through
DB0 to DB7. The display data of DB0 to DB7 from the microprocessor correspond to the LCD common lines as
shown in figure 6. The microprocessor can read from and write to RAM through the I/O buffer. Since the LCD
controller operates independently, data can be written into RAM at the same time as data is being displayed without
causing the LCD flicker.

DB0 0 0 1 - - 0
DB1 1 0 0 - - 1
DB2 0 1 1 - - 0
DB3 1 0 1 - - 0
DB4 0 0 0 - - 1

COM0 - -

COM1 - ­COM2 - ­COM3 - ­COM4 - -

Display Data RAM LCD Display

Figure 6. RAM-to-LCD Data Transfer

Page Address Circuit

This circuit is for providing a Page Address to Display Data RAM shown in figure 8. It incorporates 4-bit Page
Address register changed by only the “Set Page” instruction. Page Address 8 (DB3 is “H”, but DB2, DB1 and DB0
are “L”) is a special RAM area for the icons and display data DB0 is only valid. When Page Address is above 8, it is
impossible to access to on-chip RAM.

Line Address Circuit

This circuit assigns DDRAM a Line Address corresponding to the first line (COM0) of the display. Therefore, by
setting Line Address repeatedly, it is possible to realize the screen scrolling and page switching without changing
the contents of on-chip RAM as shown in figure 8. It incorporates 6-bit Line Address register changed by only the
Initial display line instruction and 6-bit counter circuit. At the beginning of each LCD frame, the contents of register
are copied to the line counter which is increased by CL signal and generates the Line Address for transferring the
132-bit RAM data to the 100 display data latch circuit. However, display data of icons are not scrolled because the
MPU can not access Line Address of icons.

16

S6B0716 33COM/100SEG DRIVER & CONTROLLER FOR STN LCD

Column Address Circuit

Column Address circuit has a 8-bit preset counter that provides Column Address to the Display Data RAM as shown
in figure 8. When set Column Address MSB / LSB instruction is issued, 8-bit [Y7:Y0] is updated. And, since this
address is increased by 1 each a read or write data instruction, microprocessor can access the display data
continuously. However, the counter is not increased and locked if a non-existing address above 84H. It is unlocked
if a Column Address is set again by set Column Address MSB / LSB instruction. And the Column Address counter is
independent of page address register.

ADC Select instruction makes it possible to invert the relationship between the column address and the segment
outputs. It is necessary to rewrite the display data on built-in RAM after issuing ADC Select instruction. Refer to the
following figure 7.

SEG output -

Column address [Y7:Y0]

Display data

LCD panel display

( ADC = 0 )

00H~

0FH

×

Not

outputted

SEG 0 SEG 1 SEG

2

... ...

10H 01H 02H ... ... 71H 72H 73H

1 0 0 0 1 1 0

... ...

SEG

97

SEG

98

SEG

99

LCD panel display

( ADC = 1 )

Not

outputted

... ...

Figure 7. The Relationship between the Column Address and the Segment Outputs

Segment Control Circuit

This circuit controls the display data by the display ON / OFF, reverse display ON / OFF and entire display ON / OFF
instructions without changing the data in the display data RAM.

-

74H~

83H

Not

outputted

Not

outputted

17

33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD S6B0716

Page Address

DB3 DB0DB1DB2

0

0

0

0

0

0

0

0

0

0 0

0

0 1

0

1 0

0

1 1

1

0 0

1

0 1

1

1 0

1

1 1

1 0 0 0

Column

Address

LCD Output

ADC=0
ADC=1

Data

DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7

DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7

DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7

DB0

00 - 0F 1110 12
83

- 74 7273 71
SEG0

SEG1

-

SEG2

Page0

Page1

Page2

Page3

Page4

Page5

Page6

Page7

Page8

- - - - -

- - - - -

- - - - -

71 72 73 -74 83
12 11 10 -1F 00

SEG99

SEG98

SEG97

Line

Address

00H
01H
02H
03H
04H
05H
06H
07H
08H

09H
0AH
0BH
0CH
0DH
0EH
0FH

10H

11H

12H

13H

14H

15H

16H

17H

18H

19H

1AH

1BH
1CH
1DH

1EH

1FH

20H

21H

22H

23H

24H

25H

26H

27H

28H

29H
2AH
2BH
2CH
2DH
2EH
2FH

30H

31H

32H

33H

34H

35H

36H

37H

38H

39H

3AH

3BH
3CH
3DH

3EH

3FH

Start

COM

Output

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

­COM0
COM1
COM2
COM3
COM4

COM5
COM6
COM7
COM8
COM9

COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31

-

-

-

­COMS

Initial start line address = 1CH

---- -

Figure 8. Display Data RAM Map

18

S6B0716 33COM/100SEG DRIVER & CONTROLLER FOR STN LCD

LCD DISPLAY CIRCUITS

Oscillator

This is completely on-chip oscillator and its frequency is nearly independent of VDD. This oscillator signal is used in
the voltage converter and display timing generation circuit.

* Test Condition: Temperature (25°C & 85°C), TEMPS=”L” , No Load

VDD vs. fosc

4.00

3.50

3.00

fosc

[kHz]

2.50

2.00

1.50

1.00

0.50

0.00

2.4 2.7 3.0 3.3 3.6 4.0 4.5 5.0 5.5

1/33 Duty (25°C)
1/33 Duty (85°C)

VDD [V]

Figure 9. VDD vs. fOSC

Display Timing Generator Circuit

This circuit generates some signals to be used for displaying LCD. The display clock, CL, generated by oscillation
clock, generates the clock for the line counter and the signal for the display data latch. The line address of on-chip
RAM is generated in synchronization with the display clock (CL) and the 100-bit display data is latched by the
display data latch circuit in synchronization with the display clock. The display data, which is read to the LCD driver,
is completely independent of the access to the display data RAM from the microprocessor. The display clock
generates an LCD AC signal (M) which enables the LCD driver to make a AC drive waveform, and also generates an
internal common timing signal and start signal to the common driver. Driving 2-frame AC driver waveform and
internal timing signal are shown in figure 10.

In a multiple-chip configuration, the slave chip requires the M, CL and DISP signals from the master. The table 12
shows the M, CL, and DISP status.

Table 12. Master and Slave Timing Signal Status

Operation mode Oscillator

Master

ON (internal clock used) Output Output Output

M CL DISP

OFF (external clock used) Output Input Output

Slave - Input Input Input

19

33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD S6B0716

32 33 1 2 3 4 5 6 7 8 9 10 11 12 26 27 28 29 30 31 32 33 1 2 3 4 5 6

CL

M

V0
V1

COM0

COM1

SEGn

V2
V3
V4
VSS

V0
V1
V2
V3
V4
VSS

V0
V1
V2
V3
V4
VSS

Figure 10. 2-frame AC Driving Waveform

Common Output Control Circuit

This circuit controls the relationship between the number of common output and specified duty ratio. SHL Select
Instruction specifies the scanning direction of the common output pins.

Table 13. The Relationship between Duty Ratio and Common Output

Duty SHL

1/33

0
1

Common output pins

COM0 to COM31 COMS

COM0 to COM31

COMS

COM31 to COM0

20

S6B0716 33COM/100SEG DRIVER & CONTROLLER FOR STN LCD

V

V

V

V

V

V

LCD DRIVER CIRCUIT

This Driver circuit is configured by 34-channel (including 2 COMS channel) common driver and 100-channel
segment driver. This LCD panel driver voltage depends on the combination of display data and M signal.

COM0
COM1

COM2
COM3
COM4
COM5
COM6
COM7

COM8

COM9
COM10
COM11
COM12
COM13

COM14
COM15

VDD

M

VSS

V0
V1

COM0

COM1

COM2

SEG0

SEG1

S

S

S

S

S

E

E

E

G

0

G

G

2

1

E

E

G

G

4

3

SEG2

V2

V3
V4

SS

V0
V1
V2

V3
V4

SS

V0
V1
V2

V3
V4

SS

V0
V1
V2

V3
V4

SS

V0
V1
V2

V3
V4

SS

V0
V1
V2

V3
V4

SS

Figure 11. Segment and Common Timing

21

33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD S6B0716

POWER SUPPLY CIRCUITS

The Power Supply circuits generate the voltage levels necessary to drive liquid crystal driver circuits with low-power
consumption and the fewest components. There are voltage converter circuits, voltage regulator circuits, and
voltage follower circuits. They are valid only in master operation and controlled by power control instruction. For
details, refers to "Instruction Description". The table 14 shows the referenced combinations in using Power Supply
circuits.

Table 14. Recommended Power Supply Combinations

User setup

Only the internal power

supply circuits are used

Only the voltage

regulator circuits and

voltage follower circuits

are used

Only the voltage follower

circuits are used

Only the external power

supply circuits are used

Power

control

(VC VR VF)

1 1 1 ON ON ON Open Open Open

0 1 1 OFF ON ON

0 0 1 OFF OFF ON Open

0 0 0 OFF OFF ON Open

V/C

circuits

V/R

circuits

V/F

circuits

VOUT V0 V1 to V4

External

input

Open Open

External

input

External

input

External

Open

input

22

S6B0716 33COM/100SEG DRIVER & CONTROLLER FOR STN LCD

V

DD

C1C1 GND

V

SS

V

DD

V

-++--

+

C1

GND

V

-

+

+-+-+

V

V

Voltage Converter Circuits

These circuits boost up the electric potential between VDD and VSS to 2, 3 or 4 times toward positive side and
boosted voltage is outputted from VOUT pin.

[C1 = 1.0 to 4.7 µF]

DD

V

DD

V

VOUT

C3 -

SS

C3+

C2+
C2 ­C1+

C1 -

VOUT = 2 × V

DD

V

DD

V

VOUT

C3 -

SS

C3+

C2+
C2 ­C1+

C1 -

C1

C1

VOUT = 3 × V

DD

V

SS

V

Figure 12. Two times boosting circuit Figure 13. Three times boosting circuit

DD

DD

V

VOUT

C3+

C3 -

C2+
C2 ­C1+

C1 -

­C1

VOUT = 4 × V

DD

C1

C1

C1

DD

DD

V

SS

SS

GND

Figure 14. Four Times Boosting Circuit

23

33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD S6B0716

Voltage Regulator Circuits

The function of the internal Voltage Regulator circuits is to determine liquid crystal operating voltage, V0, by
adjusting resistors, Ra and Rb, within the range of |V0| < |VOUT|. Because VOUT is the operating voltage of
operational-amplifier circuits shown in figure 15, it is necessary to be applied internally or externally.

For the Eq. 1, we determine V0 by Ra, Rb and VEV. The Ra and Rb are connected internally or externally by INTRS
pin. And VEV called the voltage of electronic volume is determined by Eq. 2, where the parameter α is the value
selected by instruction, "Set Reference Voltage Register", within the range 0 to 31. VREF voltage at Ta = 25°C is
shown in table 15-1.

Rb
V0 = (1+  ) x VEV [V] ------ (Eq. 1)

Ra
(31 - α)

VEV = (1 -  ) x VREF [V] ------ (Eq. 2)
150

Table 15-1. VREF Voltage at Ta = 25°C

TEMPS Temp. Coefficient VREF [V]

L

H

-0.05%/ °C

-0.2% / °C

1.9

2.1

Table 15-2. Reference Voltage Parameter (α)

SV4 SV3 SV2 SV1 SV0

Reference voltage parameter (α)

0 0 0 0 0 0
0 0 0 0 1 1

:
:

:
:

:
:

:
:

:

:
1 1 1 1 0 30
1 1 1 1 1 31

:
:

24

S6B0716 33COM/100SEG DRIVER & CONTROLLER FOR STN LCD

GND

Ra

Rb

V

VR

V0

VOUT

-

+

V

EV

SS

Figure 15. Internal Voltage Regulator Circuit

25

33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD S6B0716

In Case of Using External Resistors, Ra and Rb

It is necessary to connect external regulator resistor Ra between VR and VSS, and Rb between V0 and VR.

Example: For the following requirements

1. LCD driver voltage, V0 = 8V

2. 5-bit reference voltage register = (1, 1, 1, 1, 1)

3. Maximum current flowing Ra, Rb = 1 uA

From Eq. 1
Rb

8 = (1 +  ) x VEV [V] ------ (Eq. 3)
Ra

From Eq. 2
(31 - 31)

VEV = (1 -  ) x 1.9 = 1.9 [V] ------ (Eq. 4)
150

From requirement 3.
8

 = 1 [uA] ------ (Eq. 5)
Ra + Rb

From equations Eq. 3, 4 and 5
Ra = 1.9 [MΩ]
Rb = 6.1 [MΩ]

The following table shows the range of V0 depending on the above requirements.

Table 16. V0 depending on Electronic Volume Level

Electronic volume level

0 ....... 16 ....... 31

V0 6.33 ....... 7.19 ....... 8

26

S6B0716 33COM/100SEG DRIVER & CONTROLLER FOR STN LCD

Voltage Follower Circuits

VLCD voltage (V0) is resistively divided into four voltage levels (V1, V2, V3 and V4) and those output impedance are
converted by the Voltage Follower for increasing drive capability. The table 17 shows the relationship between V1 to
V4 level and bias.

Table 17. The Relationship between V1 to V4 Level and Bias

Duty ratio

1/33

LCD bias V1 V2 V3 V4

1/6 (5/6) x V0 (4/6) x V0 (2/6) x V0 (1/6) x V0
1/5 (4/5) x V0 (3/5) x V0 (2/5) x V0 (1/5) x V0

27

33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD S6B0716

VDD

MS

VOUT

C1

VDD

VOUT

VOUT

V4

Item

Unit

0.47 to 1.0

F

REFERECE CIRCUIT EXAMPLES

MS

External
C1
C1

C1

Ra

C2 - +
C2 - +

C2 - +
C2 - +
C2 - +

C3+
C3­C2+
C2­C1+
C1-

VR

Rb

V0
V1
V2
V3
V4

Power

Supply

Ra

C2 - +
C2 - +

C2 - +
C2 - +
C2 - +

C3+
C3­C2+
C2­C1+
C1-

VR

Rb

V0
V1
V2
V3
V4

V

SS

V

SS

Figure 16. When Using all LCD Power Circuits Figure 17. When not Using V/C Circuit
(4-Time V/C: ON, V/R: ON, V/F: ON)

VDD

External

Power

Supply

C2 - +
C2 - +
C2 - +
C2 - +
C2 - +

C3+
C3­C2+
C2­C1+
C1-

VR
V0

V1
V2
V3

MS

Value of external Capacitance

C1 1.0 to 4.7
C2

VDD

Value

µ

External

Power

Supply

MS

VOUT
C3+
C3­C2+
C2­C1+
C1-

VR
V0

V1
V2
V3
V4

VSS

VSS

Figure 18. When Using some LCD Power Circuits Figure 19. When not Using Internal
(V/C: OFF, V/R: OFF, V/F: ON) LCD Power Supply Circuit

28

S6B0716 33COM/100SEG DRIVER & CONTROLLER FOR STN LCD

RESET CIRCUIT

Setting RESETB to “L” or Reset instruction can initialize internal function.
When RESETB becomes “L”, foll owing procedure is occurred.

Display ON / OFF: OFF
Entire display ON / OFF: OFF (normal)
ADC select: OFF (normal)
Reverse display ON / OFF: OFF (normal)
Power control register (VC, VR, VF) = (0, 0, 0)
LCD bias ratio: 1/6
Read-modify-write: OFF
SHL select: OFF (normal)
Static indicator mode: OFF
Display start line: 0 (first)
Column address: 0
Page address: 0
Reference voltage set: OFF
Reference voltage control register: (SV4, SV3, SV2, SV1, SV0) = (0, 0, 0, 0, 0)

When RESET instruction is issued, following procedure is occurred.

Read-modify-write: OFF
Static indicator mode: OFF
SHL select: 0
Display start line: 0 (first)
Column address: 0
Page address: 0
Reference voltage set: OFF
Reference voltage control register: (SV4, SV3, SV2, SV1, SV0) = (0, 0, 0, 0, 0)

While RESETB is “L” or Reset instruction is executed, no instruction except read status c ould be accepted. Reset
status appears at DB4. After DB4 becomes ”L”, any instruction can be accepted. RESETB must be connected to the
reset pin of the MPU, and initialize the MPU and this LSI at the same time. The initialization by RESETB is essential
before used.

29

33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD S6B0716

INSTRUCTION DESCRIPTION

Table 18. Instruction Table

× : Don’t care

Instruction

Read display data 1 1 Read data Read data from DDRAM
Write display data 1 0 Write data Write data into DDRAM

Read status 0 1

Display ON / OFF 0 0 1 0 1 0 1 1 1

Initial display line 0 0 0 1 ST5 ST4 ST3 ST2 ST1 ST0 Specify DDRAM line for COM1

Set Reference Voltage

mode

Set reference voltage

register

Set page address 0 0 1 0 1 1 P3 P2 P1 P0 Set page address

Set column address MSB

Set column address LSB 0 0 0 0 0 0 Y3 Y2 Y1 Y0 Set column address LSB

Reverse display ON / OFF 0 0 1 0 1 0 0 1 1 REV

Entire display ON / OFF 0 0 1 0 1 0 0 1 0 EON

LCD bias select 0 0 1 0 1 0 0 0 1
Set modify-read 0 0 1 1 1 0 0 0 0 0 Set modify-read mode

Reset modify-read 0 0 1 1 1 0 1 1 1 0 release modify-read mode

Set static indicator register 0 0 1 0 1 0 1 1 0 SI

ADC select 0 0 1 0 1 0 0 0 0 ADC

Reset 0 0 1 1 1 0 0 0 1 0 Initialize the internal functions

SHL select 0 0 1 1 0 0 SHL

Power control 0 0 0 0 1 0 1 VC VR VF Control power circuit operation

Power save - - - - - - - - - -

Test instruction 0 0 1 1 1 1

RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

BUSY ADC ON/OFF

0 0 1 0 0 0 0 0 0 1 Set reference voltage mode

0 0 1 0 0 SV4 SV3 SV2 SV1 SV0 Set reference voltage register

0 0 0 0 0 1 0 Y6 Y5 Y4 Set column address MSB

RESETB

0 0 0 0 Read the internal status

Turn ON / OFF LCD panel

DON

When DON = 0: display OFF
When DON = 1: display ON

Select SEG output direction
When ADC = 0: normal direction
(SEG0→SEG99)
When ADC = 1: reverse direction
(SEG99→SEG0)

Select normal / reverse display
When REV = 0: normal display
When REV = 1: reverse display

Select normal/ entire display ON
When EON = 0: normal display.
When EON = 1: entire display
ON

BIAS Select LCD bias

Select COM output direction
When SHL = 0: normal direction

× × ×

× × × ×

(COM0→COM31)
When SHL = 1: reverse direction
(COM31→COM0)

Set static indicator register
SI = 0 (OFF), SI = 1 (ON)

Compound instruction of display
OFF and entire display ON

Don't use this instruction.

Description

30

S6B0716 33COM/100SEG DRIVER & CONTROLLER FOR STN LCD

Read Display Data

8-bit data from display data RAM specified by the column address and page address could be read by this
instruction. As the column address is increased by 1 automatically after each this instruction, the
micro-processor can continuously read data from the addressed page. A dummy read is required after loading
an address into the column address register. Display data cannot be read through the serial interface.

RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

1 1 Read data

Write Display Data

8-bit data of display data from the microprocessor can be written to the RAM location specified by the column
address and page address. The column address is increased by 1 automatically so that the microprocessor can
continuously write data to the addressed page.

RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

1 0 Write data

Set Page Address

Set Column Address

Data Write

Column = Column +1

Data Write Continue ?

NO

YES

Set Page Address

Set Column Address

Dummy Data Read

Column = Column +1

Data Read

Column = Column +1

Optional Status

Data Read Continue ?

YES

NO

Optional Status

Figure 20. Sequence for Writing Display Data Figure 21. Sequence for Reading Display Data

31

33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD S6B0716

Read Status

Indicates the internal status of the S6B0716.

RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 1 BUSY ADC ON / OFF RESETB

Flag Description

BUSY

ADC

ON/OFF

RESETB

Display ON / OFF

Turns the Display ON or OFF

RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 1 0 1 0 1 1 1 DON

DON = 1: display ON
DON = 0: display OFF

0 0 0 0

The device is busy when internal operation or reset. Any instruction is rejected until
BUSY goes low.
0: chip is active, 1: chip is being busy

Indicates the relationship between RAM column address and segment driver.
0: reverse direction (SEG99 → SEG0), 1: normal direction (SEG0 → SEG99)

Indicates display ON / OFF status.
0: display ON, 1: display OFF

Indicates the initialization is in progress by RESETB signal.
0: chip is active, 1: chip is being reset

Initial Display Line

Sets the line address of display RAM to determine the Initial Display Line. The RAM display data is displayed at
the top row (COM0 when SHL = L, COM31 when SHL = H) of LCD panel.

RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 0 1 ST5 ST4 ST3 ST2 ST1 ST0

ST5 ST4 ST3 ST2 ST1 ST0 Line address

0 0 0 0 0 0 0
0 0 0 0 0 1 1

: : : : : : :
1 1 1 1 1 0 62
1 1 1 1 1 1 63

32

S6B0716 33COM/100SEG DRIVER & CONTROLLER FOR STN LCD

Reference Voltage Select

Consists of 2-byte instruction
The 1st instruction sets reference voltage mode, the 2nd one updates the contents of reference voltage register.
After second instruction, reference voltage mode is released.

The 1st Instruction: Set Reference Voltage Select Mode

RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 1 0 0 0 0 0 0 1

The 2nd Instruction: Set Reference Voltage Register

RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 1 0 0 SV4 SV3 SV2 SV1 SV0

SV4 SV3 SV2 SV1 SV0

Reference voltage parameter (α)

0 0 0 0 0 0
0 0 0 0 1 1

:
:

:
:

:
:

:
:

:

:
1 1 1 1 0 30
1 1 1 1 1 31

Setting Reference Voltage Start

1st Instruction for Mode Setting

2nd Instruction for Register Setting

Setting Reference Voltage End

Figure 22. Sequence for Setting the Reference Voltage

:
:

33

33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD S6B0716

Set Page Address

Sets the Page Address of display data RAM from the microprocessor into the Page Address register. Any RAM
data bit can be accessed when its Page Address and column address are specified. Along with the column
address, the Page Address defines the address of the display RAM to write or read display data. Changing the
Page Address doesn't effect to the display status.

RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

P3 P2 P1 P0 Page

0 0 0 0 0
0 0 0 1 1

: : : : :
0 1 1 1 7
1 0 0 0 8

Set Column Address

Sets the Column Address of display RAM from the microprocessor into the column address register. Along with
the Column Address, the Column Address defines the address of the display RAM to write or read display data.
When the microprocessor reads or writes display data to or from display RAM, Column Addresses are
automatically increased.

Set Column Address MSB

RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 0 0 0 1 0 Y6 Y5 Y4

Set Column Address LSB

RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 1 0 1 1 P3 P2 P1 P0

Y6 Y5 Y4 Y3 Y2 Y1 Y0 Column address

0 0 0 0 0 0 0 0
0 0 0 0 0 0 1 1

: : : : : : : :

1 1 0 0 0 1 0 98
1 1 0 0 0 1 1 99

34

0 0 0 0 0 0 Y3 Y2 Y1 Y0

S6B0716 33COM/100SEG DRIVER & CONTROLLER FOR STN LCD

ADC Select

Changes the relationship between RAM column address and segment driver. The direction of segment driver
output pins could be reversed by software. This makes IC layout flexible in LCD module assembly.

RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 1 0 1 0 0 0 0 ADC

ADC = 0: Normal Direction (SEG0 → SEG99)
ADC = 1: Reverse Direction (SEG99 → SEG0)

Reverse Display ON / OFF

Reverses the display status on LCD panel without rewriting the contents of the display data RAM.

RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

REV RAM bit data = “1” RAM bit data = “0”

0 (normal) LCD pixel is illuminated LCD pixel is not illuminated

1 (reverse) LCD pixel is not illuminated LCD pixel is illuminated

Entire Display ON / OFF

Forces the whole LCD points to be turned ON regardless of the contents of the display data RAM. At this time,
the contents of the display data RAM are held. This instruction has priority over the reverse display ON / OFF
instruction.

RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 1 0 1 0 0 1 0 EON

EON = 0: Normal Display
EON = 1: Entire Display ON

Select LCD Bias

Selects LCD Bias ratio of the voltage required for driving the LCD.

RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 1 0 1 0 0 0 1 Bias

0 0 1 0 1 0 0 1 1 REV

Duty

Ratio

Bias = 0 Bias = 1

LCD Bias

1/33 1/6 1/5

35

33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD S6B0716

Set Modify-Read

This instruction stops the automatic increment of the column address by the read display data instruction, but
the column address is still increased by the write display data instruction. And it reduces the load of
microprocessor when the data of a specific area is repeatedly changed during cursor blinking or others. This
mode is canceled by the reset Modify-read instruction.

RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 1 1 1 0 0 0 0 0

Reset Modify-Read

This instruction cancels the Modify-read mode, and makes the column address return to its initial value just
before the set Modify-read instruction is started.

RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 1 1 1 0 1 1 1 0

NO

Set Page Address

Set Column Address (N)

Set Modify-Read

Dummy Read

Data Read

Data Process

Data Write

Change Complete ?

YES

Reset Modify-Read

Return Column Address (N)

Figure 23. Sequence for Cursor Display

36

S6B0716 33COM/100SEG DRIVER & CONTROLLER FOR STN LCD

Reset

This instruction resets initial display line, column address, page address, and common output status select to
their initial status, but dose not affect the contents of display data RAM. This instruction cannot initialize the LCD
power supply, which is initialized by the RESETB pin.

RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 1 1 1 0 0 0 1 0

SHL Select

COM output scanning direction is selected by this instruction which determines the LCD driver output status.

RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 1 1 0 0 SHL

× × ×

× : Don’ t care
SHL = 0: normal direction (COM0 → COM31)
SHL = 1: reverse direction (COM31 → COM0)

Power Control

Selects one of eight power circuit functions by using 3-bit register. An external power supply and part of internal
power supply functions can be used simultaneously.

RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 0 0 1 0 1 VC VR VF

VC VR VF Status of internal power supply circuits

0
1

0
1

0
1

Internal voltage converter circuit is OFF

Internal voltage converter circuit is ON

Internal voltage regulator circuit is OFF

Internal voltage regulator circuit is ON

Internal voltage follower circuit is OFF

Internal voltage follower circuit is ON

Set Static Indicator State

This instruction sets the Static Indicator on/OFF. When it is ON, the static indicator operates and blinks at an
interval of approximately 1 second.

Set Static Indicator Register

RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 1 0 1 0 1 1 0 SI

SI Status of Static Indicator Output

0 OFF
1 ON (about 1 second blinking)

37

33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD S6B0716

Power Save (Compound Instruction)

If the entire display ON / OFF instruction is issued during the display OFF state, S6B0716 enters the Power
Save status to reduce the power consumption to the static power consumption value. According to the status of
static indicator mode, power save is entered to one of two modes (sleep and standby mode). When static
indicator mode is ON, standby mode is issued, when OFF, sleep mode is issued. Power Save mode is released
by the display ON & entire display OFF instruction.

Static Indicator OFF Static Indicator ON

Power Save (Compound Instruction)

[Display OFF]

[Entire Display ON]

Sleep Mode

[Oscillator Circuit: OFF]

[LCD Power Supply Circuit: OFF]

[All COM/SEG Outputs: VSS]

[Consumption Current: < 2µA]

Power Save OFF (Compound Instruction)

[Entire Display OFF]
[Static Indicator ON]

[Display ON]

Release Sleep Mode

Figure 24. Power Save Routine

Standby Mode

[Oscillator Circuit: ON]

[LCD Power Supply Circuit: OFF]

[All COM/SEG Outputs: VSS]

[Consumption Current: < 10µA]

Power Save OFF (Compound Instruction)

[Entire Display OFF]

[Display ON]

Release Standby Mode

38

S6B0716 33COM/100SEG DRIVER & CONTROLLER FOR STN LCD

Referential Instruction Setup Flow (1)

User System Setup by External Pins

Start of Initialization

Power On (VDD - VSS) Keeping the RESETB Pin = “L”

Waiting for Stabilizing the Power

RESETB Pin = “H”

User Application Setup by Internal Instructions

[ADC Select]

[SHL Select]

[LCD Bias Select]

User LCD Power Setup by Internal Instructions

[Reference Voltage Register Set]

User LCD Power Setup by Internal Instructions

[Voltage Converter ON]

Waiting for ≥ 1ms

User LCD Power Setup by Internal Instructions

[Voltage Regulator ON]

Waiting for ≥ 1ms

User LCD Power Setup by Internal Instructions

[Voltage Follower ON]

Waiting for Stabilizing the LCD Power Levels

End of Initialization

Figure 25. Initializing with the Built-in Power Supply Circuits

39

33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD S6B0716

End of Initialization

Referential Instruction Setup Flow (2)

User System Setup by External Pins

Start of Initialization

Power ON (VDD - VSS) Keeping the RESETB Pin = “L”

Waiting for Stabilizing the Power

RESETB Pin = “H”

Set Power Save

User Application Setup by Internal Instructions

[ADC Select]

[SHL Select]

[LCD Bias Select]

User LCD Power Setup by Internal Instructions

[Reference Voltage Register Set]

Release Power Save

Waiting for Stabilizing the LCD Power Levels

40

Figure 26. Initializing without the Built-in Power Supply Circuits

S6B0716 33COM/100SEG DRIVER & CONTROLLER FOR STN LCD

End of Data Display

Referential Instruction Setup Flow (3)

End of Initialization

Display Data RAM Addressing by Instruction

[Initial Display Line]

[Set Page Address]

[Set Column Address]

Write Display ON/OFF by Instruction

[Display ON/OFF]

Turn Display ON/OFF by Instruction

[Display ON/OFF]

Figure 27. Data Displaying

41

33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD S6B0716

Referential Instruction Setup Flow (4)

Optional Status

Turn Display ON/OFF by Instruction

[Display OFF]

User LCD Power Setup by Internal Instructions

[Voltage Regulator OFF]

Waiting for ≥ 50ms

User LCD Power Setup by Internal Instructions

[Voltage Follower OFF]

Waiting for ≥ 1ms

User LCD Power Setup by Internal Instructions

[Voltage Converter OFF]

Waiting for ≥ 1ms

Power OFF (VDD-VSS)

Figure 28. Power OFF

42

S6B0716 33COM/100SEG DRIVER & CONTROLLER FOR STN LCD

SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS

Table 19. Absolute Maximum Ratings

Parameter Symbol Rating Unit

Supply voltage range

Input voltage range VIN -0.3 to VDD +0.3 V

Operating temperature range TOPR -40 to +85

Storage temperature range TSTR -55 to +125

NOTES:

1. VDD and VLCD are based on VSS = 0V.

2. Voltages V0 ≥ V1 ≥ V2 ≥ V3 ≥ V4 ≥ VSS must always be satisfied. ( VLCD = V0 – VSS)

3. If supply voltage exceeds its absolute maximum range, this LSI may be damaged permanently.
It is desirable to use this LSI under electrical characteristic conditions during general operation.
Otherwise, this LSI may malfunction or reduced LSI reliability may result.

VDD -0.3 to +7.0 V

VLCD -0.3 to +17.0 V

°C
°C

43

33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD S6B0716

DC CHARACTERISTICS

Table 20. DC Characteristics

(VSS = 0V, VDD = 2.4 to 3.6V, Ta = -40 to 85°C)

Operating voltage (1)
Operating voltage (2)

Input voltage

Item Symbol

High VIH 0.8VDD

Output

voltage

Low VIL VSS - 0.2VDD

High VOH IOH = -0.5mA 0.8VDD

Low VOL IOL = 0.5mA VSS - 0.2VDD

VDD 2.4 - 3.6 V VDD *1

V0 4.0 - 15.0 V V0 *2

Input leakage current IIL VIN = VDD or VSS - 1.0 - + 1.0

Condition Min Typ Max Unit Pin used

- VDD
V *3

- VDD
V *4

µA

*5

Output leakage current

LCD driver ON

resistance

Oscillator

frequency(1)

Voltage converter

input voltage

Voltage converter

output voltage

Voltage regulator

operating voltage

Voltage follower

operating voltage

Reference voltage

Internal

fOSC 17 22.5 27

External fCL

VOUT

VOUT 4.0 - 15.0 V VOUT

VREF0
VREF1

IOZ VIN = VDD or VSS - 3.0 - + 3.0

µA

RON Ta = 25°C, V0 = 8V - 2.0 3.0 kΩ

*6

SEGn

COMn *7

Ta = 25°C

kHz

CL *8

2.13 2.81 3.37

2.4 - 3.6

2.4 - 3.6

2.4 - 3.6

V VDD

VDD

× 2
× 3
× 4

×2 / ×3 / ×4

voltage conversion

95 99 - % VOUT

(no-load )

V0 4.0 - 15.0 V V0 *9

Ta = 25°C -0.05%/°C
Ta = 25°C -0.2%/°C

1.84 1.9 1.96
V *10

2.04 2.1 2.16

44

S6B0716 33COM/100SEG DRIVER & CONTROLLER FOR STN LCD

Dynamic Current Consumption (1) when the Built-in Power Circuit is OFF (At Operate Mode)

(Ta = 25°C)

Item Symbol

Dynamic current

consumption (1)

IDD1

Condition Min. Typ. Max. Unit Pin used

VDD = 3.0V

V0 – VSS = 8.0V

- 5 20 µΑ *11

Display OFF

Dynamic Current Consumption (2) when the Built-in Power Circuit is ON (At Operate Mode)

(Ta = 25°C)

Item Symbol

Condition Min. Typ. Max. Unit Pin used

VDD = 3.0V,

Quad boosting,

V0 – VSS = 8.0V,

- 47 70

Display OFF

Dynamic current

consumption (2)

IDD2

Normal power mode

µΑ *12

VDD = 3.0V,

Quad boosting,

V0 – VSS = 8.0V,

- 75 100

Display ON, checker pattern

Normal power mode

Current Consumption during Power Save mode

Item Symbol

Condition Min. Typ. Max. Unit Pin used

Sleep mode IDDS1 During sleep - - 2.0 µA

Standby mode IDDS2 During standby - - 10.0 µA

(Ta = 25°C)

45

33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD S6B0716

Table 21. The Relationship between Oscillation Frequency and Frame Frequency

Duty Ratio Item fCL fM

1/33

On-chip oscillator circuit is

used

On-chip oscillator circuit is

not used

fOSC



8

External input (fCL)

fOSC



16 × 33

fOSC



2 × 33

(fOSC: oscillation frequency, fCL: display clock frequency, fM: LCD AC signal frequency)

[* Remark Solves]
*1. Though the wide range of operating voltages is guaranteed, a spike voltage change may affect the voltage
assurance during access from the MPU.
*2. In case of external power supply is applied.
*3. CS1B, CS2, RS, DB0 to DB7, E_RD, RW_WR, RESETB, MS, MI, PS, TEMPS, CL, M, DISP pins.
*4. DB0 to DB7, M, FRS, DISP, CL pins.
*5. CS1B, CS2, RS, DB[7:0], E_RD, RW_WR, RESETB, MS, MI, PS, TEMPS, CL, M, DISP pins.
*6. Applies when the DB[7:0], M, DISP, and CL pins are in high impedance.
*7. Resistance value when ± 0.1[mA] is applied during the ON status of the output pin SEGn or COMn.
RON= ∆V / 0.1 [kΩ] (∆V: voltage change when ± 0.1[mA] is applied in the ON status.)
*8. See table 21 for the relationship between oscillation frequency and frame frequency.
*9. The voltage regulator circuit adjusts V0 within the voltage follower operating voltage range
*10. On-chip reference voltage source of the voltage regulator circuit to adjust V0.
*11,12. Applies to the case where the on-chip oscillation circuit is used and no access is made from the MPU.
The current consumption, when the built-in power supply circuit is ON or OFF.
The current flowing through voltage regulation resistors (Ra and Rb) is not included.
It does not include the current of the LCD panel capacity, wiring capacity, etc

46

S6B0716 33COM/100SEG DRIVER & CONTROLLER FOR STN LCD

REFERENCE DATA

IDD1 vs. VDD

* Test Condition: Temperature (25°C & 85°C), V0 = 8V(External), TEMPS = 'L', 1/33 Duty, Ra = 1 [MΩ],
Rb = 3 [MΩ], Normal Power Mode

VDD vs. IDD1(Pattern OFF)

12.00

10.00

8.00

IDD1

[uA]

6.00

4.00

2.00

0.00

2.7 3.0 3.3 3.6 4.0 4.5 5.0 5.5

8.0V, 1/33 Duty (25°C)

8.0V, 1/33 Duty (85°C)

VDD [V]

Figure 29. Display Pattern is OFF

47

33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD S6B0716

1/33 Duty (85°C)

IDD2 vs. VDD

Test Condition: Temperature (25°C & 85°C), Quad Boosting, RR=6, EV=32, TEMPS = 'L', 1/33 Duty,
Ra = 1 [MΩ], Rb = 3 [MΩ], Normal Power Mode

VDD vs. IDD2 (Pattern OFF)

50.00

45.00

40.00

35.00

IDD2

[uA]

30.00

25.00

20.00

15.00

10.00

5.00

0.00

2.7 3.0 3.3 3.6 4.0 4.5 5.0 5.5
VDD [V]

1/33 Duty (25°C)
1/33 Duty (85°C)

DD2

I

[uA]

250.00

200.00

150.00

100.00

50.00

0.00

Figure 30. Display Pattern is OFF

VDD vs. I

DD2

(Checker Pattern)

2.7 3.0 3.3 3.6 4.0 4.5 5.0 5.5

DD

V

[V]

Figure 31. Display Pattern is Checker

1/33 Duty (25°C)

48

S6B0716 33COM/100SEG DRIVER & CONTROLLER FOR STN LCD

t

t

t

t

0.9V

0.1V

t

, t

t

t

t

AC CHARACTERISTICS

Read / Write Characteristics (8080-series MPU)

RS

AS80

AH80

CS1B
(CS2 = 1)

RD, WR

DD

PW80(R)

PW80(W)

DD

DS80

CY80

DH80

DB0 to DB7
(Write)

ACC80

OD80

DB6 to DB7
(Read)

Figure 32. Read / Write Characteristics (8080-series MPU)

(VDD = 2.4 to 3.6V, Ta = -40 to +85°C)

Item Signal Symbol

Address setup time

Address hold time

RS

tAS80
tAH80

Min. Typ. Max. Unit Remark

13
17

- - ns

System cycle time RS tCY80 400 - - ns

Pulse width(WR) RW_WR tPW80(W)

Pulse width(RD) E_RD tPW80(R)

Data setup time

Data hold time

Read access time

Output disable time

DB7

to

DB0

tDS80

tDH80

tACC80

tOD80

55 - - ns

125 - - ns

35
13

-

10

- - ns

-

125

90

ns CL = 100 pF

49

33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD S6B0716

t

t

t

t

t

Read / Write Characteristics (6800-series Microprocessor)

RS

AS68

AH68

CS1B

(CS2 = 1)

E

PW68(R), tPW68(W)

0.9VDD0.1VDD

DS68

tCY68

DH68

DB0 to DB7
(Write)

tACC68

tOD68

DB0 to DB7
(Read)

Figure 33. Read / Write Characteristics (6800-series Microprocessor)

(VDD = 2.4 to 3.6V, Ta = -40 to +85°C)

Item Signal Symbol

Address setup time

Address hold time

RS

tAS68
tAH68

Min. Typ. Max. Unit Remark

13
17

- - ns

System cycle time RS tCY68 400 - - ns

Data setup time

Data hold time

Access time

Output disable time

Enable pulse

width

Read

Write

DB7

to

DB0

E_RD

tDS68
tDH68

tACC68

tOD68

tPW68(R)

tPW68(W)

35
13

-

10

125

55

- - ns

-

125

90

ns CL = 100 pF

- - -

50

S6B0716 33COM/100SEG DRIVER & CONTROLLER FOR STN LCD

Serial Interface Characteristics

tCHStCSS

CS1B

(CS2 = 1)

tAHStASS

RS

tCYS

DB6

(SCLK)

0.9VDD

0.1VDD
tWLS

tWHS

DB7

(SID)

Item Signal Symbol Min. Typ. Max. Unit Remark

Serial clock cycle

SCLK high pulse width

SCLK low pulse width

Address setup time

Address hold time

Data setup time

Data hold time

CS1B setup time

CS1B hold time

t

DSS

t

DHS

Figure 34. Serial Interface Characteristics

( VDD = 2.4 to 3.6V, Ta = -40 to +85°C )

DB6

(SCLK)

RS

DB7

(SID)

CS1B

tCYS

tWHS

tWLS

tASS
tAHS

tDSS

tDHS

tCSS

tCHS

450
180
135

90

360

90
90

55

180

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

ns

ns

ns

ns

51

33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD S6B0716

t

Reset Input Timing

tRW

RESETB

Figure 35. Reset Input Timing

( VDD = 2.4 to 3.6V, Ta = -40 to +85°C )

Reset low pulse width RESETB

Item Signal Symbol

Display Control Output Timing

Min.

Typ.

Max. Unit

tRW 900 - - ns

DM

Remark

CL

M

Figure 36. Display Control Output Timing

( VDD = 2.4 to 3.6V, Ta = -40 to +85°C )

Item Signal Symbol

Min.

Typ.

Max. Unit

Remark

M delay time M tDM - 13 70 ns

52

S6B0716 33COM/100SEG DRIVER & CONTROLLER FOR STN LCD

DB0 to DB7

RESETB

VDDV

ERSCS2

CS1B

OPEN

VSSVDD or V

SID

CS1B

REFERENCE APPLICATIONS

MICROPROCESSOR INTERFACE

In Case of Interfacing with 6800-series (PS = “H”, MI = “H”)

CS1B

6800-series

MPU

RW

DD

Figure 37. Interfacing with 6800-series (PS = “H”, MI = “H”)

In Case of Interfacing with 8080-series (PS = “H”, MI = “L”)

CS2
RS

8080-series

MPU

/RD
/WR
DB0 to DB7
RESETB

V

SS

V

DD

CS1B
CS2
RS
E_RD
RW_WR
DB0 to DB7
RESETB
MI
PS

CS1B
CS2
RS
E_RD
RW_WR
DB0 to DB7
RESETB
MI
PS

S6B0716

S6B0716

Figure 38. Interfacing with 8080-series (PS = “H”, MI = “L”)

In Case of Serial Interface (PS = “L”, MI = “H/L”)

MPU

Figure 39. Serial Interface (PS = “L”, MI = “H/L”)

53

CS2
RS

SCLK
RESETB

SS

CS1B
CS2
RS
DB7(SID)
DB6(SCLK)
RESETB
DB0 to DB5
MI
PS

S6B0716