Apple J113 Schematic

8

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.

3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

7

3456

REV ECN

DESCRIPTION OF REVISION

12

CK APPD

DATE

J113 MLB SCHEMATIC

<ECO_DESCRIPTION>

10/03/14

D

C

B

TABLE_TABLEOFCONTENTS_HEAD

TABLE_TABLEOFCONTENTS_ITEM

Page

(.csa)

1

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 SMC 38 39 40 41 42 43 44 45 Fan

Table of Contents

2

BOM Configuration

3

BOM Variants

4

PD PARTS

5

CPU GFX/NCTF/RSVD

6

CPU Misc/JTAG/CFG/RSVD

7

CPU DDR3/LPDDR3 Interfaces

8

CPU/PCH POWER

9

CPU/PCH GROUNDS

10

CPU Decoupling

12

PCH Decoupling

13

PCH Audio/JTAG/SATA/CLK

14

PCH PM/PCI/GFX

15

PCH PCIe/USB/LPC/SPI/SMBus

16

PCH GPIO/MISC/LPIO

18

CPU/PCH Merged XDP

19

Chipset Support

20

Project Chipset Support

22

DDR3 VREF MARGINING

23

LPDDR3 DRAM Channel A (0-31)

24

LPDDR3 DRAM Channel A (32-63)

25

LPDDR3 DRAM Channel B (0-31)

26

LPDDR3 DRAM Channel B (32-63)

27

LPDDR3 DRAM Termination

28

Thunderbolt Host (1 of 2)

29

Thunderbolt Host (2 of 2)

30

TBT Power Support

32

Thunderbolt Connector A

35

Wireless Connector

37

SSD Connector

39

Camera 1 of 2

40

Camera 2 of 2

44

SD READER CONNECTOR

45

SD CONTROLLER (GL3219)

46

External A USB3 Connector

48

IPD Connector

50

51

SMC Shared Support

52

SMC Project Support

53

SMBus Connections

54

High Side Current Sensing

55

Voltage & Load Side Current Sensing

56

Debug Sensors 1

58

Thermal Sensors

60

Contents

MASTER

J41_MLB

K21_MLB

MASTER

J41_MLB

WILL_J43

J41_MLB

MASTER

J41_MLB

Sync

Date

MASTER

04/09/2013

11/16/2010

MASTER

02/06/2013

04/02/2013

02/06/2013

04/09/2013

02/06/2013

01/08/2013

02/07/2013

02/06/2013

04/02/2013

02/06/2013

02/15/2013

02/12/2013

02/06/2013

02/07/2013

02/06/2013

04/09/2013

04/02/2013

03/20/2013

07/01/2011

10/11/2010

02/07/2013

02/12/2013

02/06/2013

03/28/2013

02/06/2013

Page Sync

TABLE_TABLEOFCONTENTS_HEAD

TABLE_TABLEOFCONTENTS_ITEM

(.csa)

61

46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76

LPC+SPI Debug Connector

64

Audio: Speaker Amp

69

Battery Connector

70

DC-In & G3H Supply

71

PBus Supply & Battery Charger

72

CPU VR12.6 VCC Regulator IC

73

CPU VR12.5 VCC Power Stage

74

LPDDR3 Supply

75

5V S4RS3 / 3.3V S5 Power Supply

76

1.05V S0 Power Supply

77

LCD/KBD Backlight Driver

78

Misc Power Supplies

80

Power FETs

81

Power Control

83

Internal DisplayPort Connector

95

Left I/O (LIO) Connector

100

Power Aliases

102

Signal Aliases

104

Func Test / No Test

105

Project FCT/NC/Aliases

110

PCB Rule Definitions

111

CPU Constraints

112

PCH Constraints 1

113

PCH Constraints 2

114

Memory Constraints

115

Thunderbolt Constraints

116

Camera Constraints

117

SMC Constraints

118

Project Specific Constraints

119

Project Specific Constraints

121

Reference

Contents

J41_MLB

MASTER

J41_MLB

CLEAN_J43

J41_MLB

CONSTRAINTS

CLEAN_J43

J41_MLB

CONSTRAINTS

J41_MLB

CONSTRAINTS

J41_MLB

CONSTRAINTS

J41_MLB

Date

04/02/2013

04/26/2013

MASTER

02/06/2013

05/21/2013

04/09/2013

05/21/2013

09/17/2012

05/21/2013

02/06/2013

11/13/2012

01/30/2013

08/30/2012

02/01/2013

09/13/2012

10/24/2012

09/25/2012

11/13/2012

12/14/2012

09/25/2012

01/30/2013

09/25/2012

12/07/2012

09/25/2012

07/03/2012

D

C

B

A

ALIASES RESOLVED

Schematic / PCB #’s

PART NUMBER

051-00385

820-00165

DRAWING

TITLE=MLB

ABBREV=DRAWING

LAST_MODIFIED=Fri Oct 3 11:36:00 2014

DRAWING TITLE

PRODUCT SAFETY REQUIREMENTS: PCB, UL RECOGNIZED, MIN. 130-C TEMP. RATING AND V-0 FLAME RATING PER UL 796 & UL 94.

QTY

DESCRIPTION

1

SCHEM,MLB,J43A

PCBF,MLB,J43

REFERENCE DES

SCH

PCB

CRITICAL

BOM OPTION

8 7 6 5 4 2 1

PCB TO BE SILK-SCREENED WITH UL/CUL RECOGNITION MARK, MANUFACTURER’S UL FILE NUMBER, UL PCB MATERIAL DESIGNATION, 130-C TEMP. RATING AND V-0 FLAME RATING.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

3

<PART_DESCRIPTION>

Apple Inc.

R

DRAWING NUMBER

REVISION

BRANCH

PAGE

SHEET

<SCH_NUM>

<BRANCH> 1 OF 121

1 OF 76

SIZE

A

D

8 7 6 5 4 3

12

BOM Groups

BOM GROUP

MLB_COMMON

MLB_MISC

MLB_DEVEL:ENG

MLB_DEVEL:PVT

MLB_DEBUG:ENG

MLB_DEBUG:PVT

D

MLB_DEBUG:PROD

Current Sensor Configuration

BOM GROUP

ISNS:ENG

ISNS:PROD

CPU DRAM SPD Straps

BOM GROUP

DDR3:HYNIX_4GB

DDR3:HYNIX_8GB

DDR3:SAMSUNG_4GB

DDR3:SAMSUNG_8GB

DDR3:ELPIDA_4GB

DDR3:ELPIDA_8GB

DDR3:MICRON_4GB

DDR3:MICRON_8GB

C

DDR3:HYNIX_16GB

DDR3:SAMSUNG_16GB

DDR3:ELPIDA_16GB

DDR3:MICRON_16GB

Programmable Parts

PART NUMBER

335S0915

341S00159

338S1214

335S00006

335S00007

341S00153

QTY

1

Module Parts

PART NUMBER

337S00029

B

337S00073

338S00069

338S1264

607-6811

946-5477 CRITICALGLUE

825-7987

376S00036

376S00037

376S1194 CRITICAL

376S1193

900-0090

825-7670

QTY

1

2

1

PP5V5_DCIN:NO,TBTHV:P15V,EDP,CAM_XTAL:NO,CAM_WAKE:NO,APCLKRQ:ISOL,TPAD_INTWAKE:SHARED,USB_PWR:S3,SD_ON_MLB,VCORE_FETS,SSD_LPSR:S3

CPU_HS_ISNS:YES,CPUVR_ISNS:YES,DRAM_ISNS:YES,P1V05_ISNS:YES,AIRPORT_ISNS:YES,SSD_ISNS:YES,LCDBKLT_ISNS:YES,P3V3S5_ISNS:YES,3V3S0_ISNS:YES,OTHER_HS_ISNS:YES,CAM_ISNS:YES,CPUDDR_ISNS:YES,PANEL_ISNS:YES

CPU_HS_ISNS:YES,CPUVR_ISNS:YES,DRAM_ISNS:YES,P1V05_ISNS:NO,AIRPORT_ISNS:NO,SSD_ISNS:YES,LCDBKLT_ISNS:NO,P3V3S5_ISNS:NO,3V3S0_ISNS:NO,OTHER_HS_ISNS:NO,CAM_ISNS:NO,CPUDDR_ISNS:NO,PANEL_ISNS:NO

DESCRIPTION

EEPROM,4MBIT,SPI,50MHZ,1.8V,USON8

T29,EEPROM,FALCON RIDGE(V27.1), PROtO 0,J110/J113

IC,SMC12-B1,40MHZ/50DMIPS MCU,157BGA

IC,SERIAL FLASH,64 MBIT 3V,WSON,QE=1

IC,EFI ROM(V0108)), PROTO 0,J110/J113

DESCRIPTION

BDW,QGH9,D0,1.8,15W,2+2,0.7,4M,B1168

BDW,QGHB,D0,1.6,15W,2+2,0.6,4M,B1168

IC,TBT,FR-2C,288,12x12 ,FC-CSP,TRAY

IC,BCM15700A2KFEB4G,S2 CMRA,8X8,208FCBGA

ASSEMBLY,SUBASSY,PCBA,HALL EFFECT,K99

UV GLUE,MLB,J41_J43

LABEL,MLB,J41/J43

MOSFET,N-CH,30V,52A,5.9M,8P 3.3X3.3 DFN

MOSFET,N-CH,30V,64A,3.5M,8P 3.3X3.3 DFN

MOSFET,N-CH,30V,15.3A,12M,8P 3.3X3.3 DFN

MOSFET,N-CH,30V,22A,6.0M,8P 3.3X3.3 DFN

LABEL,TEXT,MLB,K21/K78

BOM OPTIONS

ALTERNATE,COMMON,MLB_MISC,MLB_DEBUG:PVT,MLB_PROGPARTS

ALTERNATE,BKLT:ENG,XDP_CONN,DDRVREF_DAC,S0PGOOD_ISL,DBGLED,ISNS:ENG

XDP_CONN

XDP,SAMCONN

BKLT:PROD,XDP,SAMCONN,ISNS:ENG,DBGLED,XDP_CONN

BKLT:PROD,SAMCONN,XDP,ISNS:PROD

BOM OPTIONS

RAMCFG0:L,RAMCFG1:L,RAMCFG2:L,RAMCFG3:L,DRAM_TYPE:HYNIX_4GB

RAMCFG0:L,RAMCFG1:L,RAMCFG2:H,RAMCFG3:L,DRAM_TYPE:HYNIX_8GB

RAMCFG0:L,RAMCFG1:H,RAMCFG2:L,RAMCFG3:L,DRAM_TYPE:SAMSUNG_4GB

RAMCFG0:L,RAMCFG1:H,RAMCFG2:H,RAMCFG3:L,DRAM_TYPE:SAMSUNG_8GB

RAMCFG0:H,RAMCFG1:H,RAMCFG2:L,RAMCFG3:L,DRAM_TYPE:ELPIDA_4GB

RAMCFG0:H,RAMCFG1:H,RAMCFG2:H,RAMCFG3:L,DRAM_TYPE:ELPIDA_8GB

RAMCFG0:H,RAMCFG1:L,RAMCFG2:L,RAMCFG3:L,DRAM_TYPE:MICRON_4GB

RAMCFG0:H,RAMCFG1:L,RAMCFG2:H,RAMCFG3:L,DRAM_TYPE:MICRON_8GB

RAMCFG0:L,RAMCFG1:L,RAMCFG2:L,RAMCFG3:H,DRAM_TYPE:HYNIX_16GB

RAMCFG0:L,RAMCFG1:H,RAMCFG2:L,RAMCFG3:H,DRAM_TYPE:SAMSUNG_16GB

RAMCFG0:H,RAMCFG1:H,RAMCFG2:L,RAMCFG3:H,DRAM_TYPE:ELPIDA_16GB

RAMCFG0:H,RAMCFG1:L,RAMCFG2:L,RAMCFG3:H,DRAM_TYPE:MICRON_16GB

REFERENCE DES

U2890

U5000

U6100

REFERENCE DES

U0500

U2800

U3900

J6955

NEW_LABEL

Q7310,Q7320

Q7311,Q7321

Q7310,Q7320

Q7311,Q7321

SOLDERPASTE

LABEL

CRITICAL

BOM OPTION

TBTROM:BLANK

TBTROM:PROG

SMC:BLANK

BOOTROM_MAC:BLANK

BOOTROM_NUM:BLANK

BOOTROM:PROG

BOM OPTION

CPU:2.1GHZ

CPU:1.6GHZ

J113_MLB

VCORE_FET:REN

VCORE_FET:VSHY

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

CPU DRAM CFG Chart

VENDOR

HYNIX

SAMSUNG

MICRON

ELPIDA

SIZE

4GB

8GB

16GB

RSVD

CFG 1

1 0

0 1

1

CFG 3

0

1

CFG 0

CFG 2

Alternate Parts

PART NUMBER

376S1032 376S0855

376S1129

376S1089

372S0186

00

152S1821

197S0480

1

197S0481 197S0343

107S0254 107S0241

353S3452

0

1

128S0386

128S0397 128S0325

0

1

376S00014

107S0255 107S0240

870-5074 870-1938

860-3428 860-1327

333S0787 333S0677

860-3690

333S0785 333S0681

311S00008

311S00007

311S00015

311S00013

311S00014

353S00133

ALTERNATE FOR PART NUMBER

376S0855

376S1128

138S0660138S0684

138S0648138S0703

152S1301152S0586

372S0185

197S0478197S0479

376S0604376S1053

371S0558371S0713

128S0376128S0371

152S1757

197S0343

353S1286

128S0284

377S0104377S0155

128S0220128S0398

197S0544197S0542

197S0544197S0545

138S0638138S0681

138S0638138S0841

376S0761

152S1804152S1876

107S0248107S0250

860-1328

353S3812353S3814

311S0271

311S0426

311S0450

311S0508

311S0515

353S2741

BOM OPTION

DRAM_TYPE:HYNIX_4GB

DRAM_TYPE:HYNIX_8GB

REF DES

ALL

COMMENTS:

Toshiba alt for Diodes dual

NXP alt for Diodes dual

NXP alt for Diodes single

Murata alt to Taiyo Yuden

Dale/Vishay alt to Cyntec

NXP alt to Diodes

200uW Epson alt to NDK

Diodes alt to Fairchild

Diodes alt to ST Micro

Kemet alt to Sanyo

Cyntec alt to NEC

NDK crystal alt to TXC

Epson crystal alt to TXC

Cyntec sense R alt to TFT

Maxim alt to Microchip

Kemet alt to Sanyo

OnSemi alt to Infineon

Kemet alt to Sanyo

NDK alt to TXC

Epson alt to TXC

Taiyo alt to Samsung

Murata alt to Samsung

Renesas alt to Vishay

TDK alt to Toko

Cyntec alt to TFT

ALT POGO PIN W_O CAP

ALT STANDOFF W_O MYLAR

ALT TBT PORT MUX

ALT AND GATE

ALT SNGL BUFFER

ALT 2-INPT AND

ALT SNGL BUFFER

ALT DUAL BUFFER

ALT PWR DIST SW

TABLE_ALT_HEAD

TABLE_ALT_ITEM

D

C

B

A

DRAM Parts

PART NUMBER

333S0677

333S0681

333S00001

333S00003

333S0793

333S0791

333S0793

333S0789

QTY

4

DESCRIPTION

IC,SDRAM,8Gb,LPDDR3-1600,178P FBGA

IC,SDRAM,16Gb,LPDDR3-1600,178P FBGA

IC,SDRAM,23NM,8GB,LPDDR3-1600,178P FBGA

IC,SDRAM,23NM,16GB,LPDDR3-1600,178P FBGA

IC,SDRAM,8Gb,LPDDR3-1600,178P FBGA

IC,SDRAM,16Gb,LPDDR3-1600,178P FBGA

IC,SDRAM,8Gb,LPDDR3-1600,178P FBGA

IC,SDRAM,16GB,LPDDR3-1600,178P FBGA

IC,SDRAM,25nm,32Gb,LPDDR3-1600,178P FBGA

REFERENCE DES

U2300,U2400,U2500,U2600

CRITICAL

CRITICAL333S0791

CRITICAL

BOM OPTION

DRAM_TYPE:HYNIX_4GB

DRAM_TYPE:HYNIX_8GB

DRAM_TYPE:SAMSUNG_4GB

DRAM_TYPE:SAMSUNG_8GB

DRAM_TYPE:ELPIDA_4GB

DRAM_TYPE:ELPIDA_8GB

DRAM_TYPE:MICRON_4GB

DRAM_TYPE:MICRON_8GB

DRAM_TYPE:ELPIDA_16GB

6 3

SYNC_MASTER=J43_MLB

PAGE TITLE

BOM Configuration

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=01/17/2013

DRAWING NUMBER

<SCH_NUM>

REVISION

BRANCH

PAGE

2 OF 121

SHEET

2 OF 76

124578

SIZE

A

D

8 7 6 5 4 3

12

D

C

BOM Variants

BOM NUMBER

639-00623

639-00624

639-00625

639-00626

639-00627

639-00628

639-00629

639-00630

639-00631

639-00632

639-00633

639-00634

639-00635

639-00636

639-00637

639-00638

639-00639

639-00640

639-00641

639-00642

685-00046

685-00047

685-00048

639-00697

BOM NAME

PCBA,MLB,BEST,HY-4GB,X430

PCBA,MLB,BEST,HY-8GB,X433

PCBA,MLB,BEST,HY-16GB,X433

PCBA,MLB,BEST,SM-4GB,X433

PCBA,MLB,BEST,SM-8GB,X433

PCBA,MLB,BEST,MI-4GB,X433

PCBA,MLB,BEST,MI-8GB,X433

PCBA,MLB,BEST,MI-16GB,X433

PCBA,MLB,BEST,EL-4GB,X433

PCBA,MLB,BEST,EL-8GB,X433

PCBA,MLB,BETTER,HY-4GB,X433

PCBA,MLB,BETTER,HY-8GB,X433

PCBA,MLB,BETTER,HY-16GB,X433

PCBA,MLB,BETTER,SM-4GB,X433

PCBA,MLB,BETTER,SM-8GB,X433

PCBA,MLB,BETTER,MI-4GB,X433

PCBA,MLB,BETTER,MI-8GB,X433

PCBA,MLB,BETTER,MI-16GB,X433

PCBA,MLB,BETTER,EL-4GB,X433

PCBA,MLB,BETTER,EL-8GB,X433

CMN PTS,PCBA,MLB,X433

VCORE FET,REN,X433

VCORE FET,VSHY,X433

PCBA,MLB,BETTER,EL-16GB,X433

BOM OPTIONS

MLB_CMNPTS,CPU:2.1GHZ,DDR3:HYNIX_4GB,ALTERNATE

MLB_CMNPTS,CPU:2.1GHZ,DDR3:HYNIX_8GB,ALTERNATE

MLB_CMNPTS,CPU:2.1GHZ,DDR3:HYNIX_16GB

MLB_CMNPTS,CPU:2.1GHZ,DDR3:SAMSUNG_4GB,ALTERNATE

MLB_CMNPTS,CPU:2.1GHZ,DDR3:SAMSUNG_8GB,ALTERNATE

MLB_CMNPTS,CPU:2.1GHZ,DDR3:MICRON_4GB

MLB_CMNPTS,CPU:2.1GHZ,DDR3:MICRON_8GB

MLB_CMNPTS,CPU:2.1GHZ,DDR3:MICRON_16GB

MLB_CMNPTS,CPU:2.1GHZ,DDR3:ELPIDA_4GB

MLB_CMNPTS,CPU:2.1GHZ,DDR3:ELPIDA_8GB

MLB_CMNPTS,CPU:1.6GHZ,DDR3:HYNIX_4GB,ALTERNATE

MLB_CMNPTS,CPU:1.6GHZ,DDR3:HYNIX_8GB,ALTERNATE

MLB_CMNPTS,CPU:1.6GHZ,DDR3:HYNIX_16GB

MLB_CMNPTS,CPU:1.6GHZ,DDR3:SAMSUNG_4GB,ALTERNATE

MLB_CMNPTS,CPU:1.6GHZ,DDR3:SAMSUNG_8GB,ALTERNATE

MLB_CMNPTS,CPU:1.6GHZ,DDR3:MICRON_4GB

MLB_CMNPTS,CPU:1.6GHZ,DDR3:MICRON_8GB

MLB_CMNPTS,CPU:1.6GHZ,DDR3:MICRON_16GB

MLB_CMNPTS,CPU:1.6GHZ,DDR3:ELPIDA_4GB

MLB_CMNPTS,CPU:1.6GHZ,DDR3:ELPIDA_8GB

MLB_COMMON,J113_MLB

VCORE_FET:REN

VCORE_FET:VSHY

MLB_CMNPTS,CPU:1.6GHZ,DDR3:ELPIDA_16GB

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

Alternate Parts

PART NUMBER

ALTERNATE FOR PART NUMBER

685-00048685-00047

333S0700333S0704

BOM OPTION

REF DES

ALL

COMMENTS:

Renesas alt to Vishay

Elpida CAM DRAM alt to Hynix

TABLE_ALT_HEAD

TABLE_ALT_ITEM

D

C

B

Module Parts

PART NUMBER

338S1246

BOM Groups

BOM GROUP

MLB_PROGPARTS

Programmable Parts

A

PART NUMBER

341S00148

Sub-BOMs

PART NUMBER

685-00046

685-00048

QTY

1

QTY

1

QTY

1

DESCRIPTION

IC,GL3219,USB3 SD CARD READER,46P,LQFN

DESCRIPTION

IC,SMC-B1,EXT(Vxxxx),PROTO 0,J113

DESCRIPTION

CMN PTS,PCBA,MLB,J113

VCORE FET,VSHY,J113

REFERENCE DES

U4500

BOM OPTIONS

BOOTROM:PROG,SMC:PROG,TBTROM:PROG

REFERENCE DES

U5000

REFERENCE DES

CMNPTS

VCOREFETS

CRITICAL

BOM OPTION

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

BOM OPTION

SMC:PROG

BOM OPTION

MLB_CMNPTS

VCORE_FETS

6 3

SYNC_MASTER=MASTER

PAGE TITLE

BOM Variants

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=MASTER

DRAWING NUMBER

<SCH_NUM>

REVISION

BRANCH

PAGE

3 OF 121

SHEET

3 OF 76

124578

SIZE

B

A

D

8 7 6 5 4 3

12

PD Module Parts

PART NUMBER

806-5107 CRITICAL

806-5108

806-3142

806-3215 TBTCOVER

D

806-3216 CRITICAL

806-3083 CRITICAL

QTY

1

DESCRIPTION

CAN,TOPSIDE,ALT,J41/J43

CAN,TOPSIDE,COVER,ALT,J41/J43

CAN,TBT,J11/J13

CAN,COVER,TBT,J11/J13

CAN,MDP,J11/J13

SHLD,USB,MLB,J11/J13

REFERENCE DES

TBTTOPSIDE_2P_FENCE

TBTTOPSIDE_2P_COVER

TBTFENCE CRITICAL

MDPCAN

USBCAN

CRITICAL

BOM OPTION

D

Plated Board Slot

SL0400

TH-NSP

1

SL-2.3X3.9-2.9X4.5

CPU Heat Sink Mounting Bosses

Z0413

STDOFF-4.5OD1.52H-SM

C

Fan Boss

Z0405

STDOFF-4.5OD1.8H-SM

1

860-1327

Z0411

1

4x 860-1327

X21 Boss

STDOFF-4.5OD1.9H-SM

1

860-1327

Z0414

Z0410

STDOFF-4.5OD1.52H-SM

1

Z0412

STDOFF-4.5OD1.52H-SM

1

SSD Boss

Z0415

STDOFF-4.5OD1.9H-SM

1

860-1327

SL-1.1X0.4-1.4X0.7

SL-1.1X0.45-1.4X0.75

SL-1.1X0.4-1.4X0.7

SL0401

TH-NSP

1

SL0403

TH-NSP

1

SL0405

TH-NSP

1

SL0404

TH-NSP

1

Can Slots

SL-1.1X0.4-1.4X0.7

SL-1.1X0.45-1.4X0.75

SL-1.1X0.4-1.4X0.7

SL0402

TH-NSP

1

SL0406

TH-NSP

1

SL0407

TH-NSP

1

SL0408

TH-NSP

1

2x TBT pin diodes

2x MDP Connector

2x TBT chip

2x USB Connector

C

EMI I/O Pogo Pins

DisplayPort Pogo

CRITICAL

ZS0405

POGO-2.0OD-3.6H-K86-K87

SM

1

870-1938

B

USB/SD Card Pogo

CRITICAL

ZS0406

POGO-2.0OD-3.6H-K86-K87

SM

1

870-1938

B

A

6 3

SYNC_MASTER=MASTER

PAGE TITLE

PD PARTS

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=MASTER

DRAWING NUMBER

<SCH_NUM>

REVISION

BRANCH

PAGE

4 OF 121

SHEET

4 OF 76

124578

SIZE

A

D

8 7 6 5 4 3

CRITICAL

OMIT_TABLE

U0500

BROADWELL-ULT

2C+GT2

BGA

DDI Port Assignments:

D

TBT Sink 0

TBT Sink 1 (MUXed with HDMI if necessary)

DP_TBTSNK0_ML_C_N<0>

25 67

OUT

DP_TBTSNK0_ML_C_P<0>

25 67

OUT

DP_TBTSNK0_ML_C_N<1>

25 67

OUT

DP_TBTSNK0_ML_C_P<1>

25 67

OUT

DP_TBTSNK0_ML_C_N<2>

25 67

OUT

DP_TBTSNK0_ML_C_P<2>

25 67

OUT

DP_TBTSNK0_ML_C_N<3>

25 67

OUT

DP_TBTSNK0_ML_C_P<3>

25 67

OUT

DP_TBTSNK1_ML_C_N<0>

18 25 67

OUT

DP_TBTSNK1_ML_C_P<0>

18 25 67

OUT

DP_TBTSNK1_ML_C_N<1>

18 25 67

OUT

DP_TBTSNK1_ML_C_P<1>

18 25 67

OUT

DP_TBTSNK1_ML_C_N<2>

18 25 67

OUT

DP_TBTSNK1_ML_C_P<2>

18 25 67

OUT

DP_TBTSNK1_ML_C_N<3>

18 25 67

OUT

DP_TBTSNK1_ML_C_P<3>

18 25 67

OUT

C54 C55 B58 C58 B55 A55 A57 B57

C51 C50 C53 B54 C49 B50 A53 B53

DDI1_TXN0 DDI1_TXP0 DDI1_TXN1 DDI1_TXP1 DDI1_TXN2 DDI1_TXP2 DDI1_TXN3 DDI1_TXP3

DDI2_TXN0 DDI2_TXP0 DDI2_TXN1 DDI2_TXP1 DDI2_TXN2 DDI2_TXP2 DDI2_TXN3 DDI2_TXP3

SYM 1 OF 19

DDI

EDP

EDP_TXN0 EDP_TXP0 EDP_TXN1 EDP_TXP1

EDP_TXN2 EDP_TXP2 EDP_TXN3 EDP_TXP3

EDP_AUXN EDP_AUXP

EDP_RCOMP

EDP_DISP_UTIL

C45 B46 A47 B47

C47 C46 A49 B49

A45 B45

D20 A43

DP_INT_ML_C_N<0> DP_INT_ML_C_P<0> NC_INT_ML_CN<1> NC_INT_ML_CP<1>

NC_INT_ML_CN<2> NC_INT_ML_CP<2> NC_INT_ML_CN<3> NC_INT_ML_CP<3>

DP_INT_AUXCH_C_N DP_INT_AUXCH_C_P

MCP_EDP_RCOMP TP_EDP_DISP_UTIL

60 67

OUT

60 67

OUT

64

OUT

64

OUT

64

OUT

64

OUT

64

OUT

64

OUT

60 67

BI

60 67

BI

eDP Port Assignment:

Internal panel

PPVCOMP_S0_CPU

1

R0530

24.9

1% 1/20W MF 201

2

8

12

D

CRITICAL

OMIT_TABLE

U0500

AT2 AU44 AV44

D15

F22

H22

J21

BROADWELL-ULT

2C+GT2

SYM 17 OF 19

CRITICAL

OMIT_TABLE

U0500

BROADWELL-ULT

2C+GT2

SYM 18 OF 19

SPARE

RSVD RSVD RSVD RSVD

RSVD RSVD RSVD

BGA

DAISY_CHAIN_NCTF DAISY_CHAIN_NCTF

DAISY_CHAIN_NCTF DAISY_CHAIN_NCTF DAISY_CHAIN_NCTF DAISY_CHAIN_NCTF DAISY_CHAIN_NCTF DAISY_CHAIN_NCTF DAISY_CHAIN_NCTF DAISY_CHAIN_NCTF DAISY_CHAIN_NCTF DAISY_CHAIN_NCTF

N23

RSVD

R23

RSVD

T23

RSVD

U10

RSVD

AL1

RSVD

AM11

RSVD

AP7

RSVD

AU10

RSVD

AU15

RSVD

AW14

RSVD

AY14

RSVD

C

TRUE

AY2

DAISY_CHAIN_NCTF

AY3

DAISY_CHAIN_NCTF

AY60

DAISY_CHAIN_NCTF

AY61

DAISY_CHAIN_NCTF

AY62

DAISY_CHAIN_NCTF

B2

DAISY_CHAIN_NCTF

B3

DAISY_CHAIN_NCTF

B61

DAISY_CHAIN_NCTF

B62

DAISY_CHAIN_NCTF

B63

DAISY_CHAIN_NCTF

C1

DAISY_CHAIN_NCTF

C2

DAISY_CHAIN_NCTF

TP0531

TP0501

TP-P6

MCP_DC_AW2_AY2

5

MCP_DC_AW3_AY3

5

MCP_DC_AY60

1

TP

1

MCP_DC_AW61_AY61

5

MCP_DC_AW62_AY62

5

MCP_DC_B2 MCP_DC_A3_B3

5

MCP_DC_A61_B61

5

MCP_DC_B62_B63

MCP_DC_C1_C2

B

NC NC

MCP Daisy-Chain Strategy:

Each corner of CPU has two testpoints. Other corner test signals connected in daisy-chain fashion. Continuity should exist between both TP’s on each corner.

NO_TESTNO_TEST

A3 A4

A60 A61 A62 AV1 AW1 AW2 AW3 AW61 AW62 AW63

NCNC NCNC NCNC

NCNC NCNC NCNC NC NC NC NC

TRUE

TRUE TRUE

TRUE

MCP_DC_A3_B3 MCP_DC_A4

MCP_DC_A60 MCP_DC_A61_B61 MCP_DC_A62 MCP_DC_AV1 MCP_DC_AW1 MCP_DC_AW2_AY2 MCP_DC_AW3_AY3 MCP_DC_AW61_AY61 MCP_DC_AW62_AY62 MCP_DC_AW63

C

5

1

TP

TP0500

TP-P6

1

TP

TP0510

TP-P6

5

1

TP

TP0511

TP-P6

1

TP

TP0520

TP-P6

1

TP

1

TP-P6

TP

TP0521

TP0530

5

B

A

PAGE TITLE

CPU GFX/NCTF/RSVD

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

6 3

SYNC_DATE=09/13/2012SYNC_MASTER=WILL_J43

DRAWING NUMBER

<SCH_NUM>

REVISION

BRANCH

PAGE

5 OF 121

SHEET

5 OF 76

124578

SIZE

A

D

8 7 6 5 4 3

CRITICAL

OMIT_TABLE

U0500

D

PP1V05_S0

8

11 15 16 17 38 42 51 55 58

59 62 64

R0650

PLACE_NEAR=U0500.AU60:12.7mm

PLACE_NEAR=U0500.AV60:12.7mm

1/20W

200

37 38 51 67

BI

1

1%

MF

201

2

R0610

CPU_PROCHOT_L

1

121

1%

1/20W

MF

201

2

PLACE_NEAR=U0500.C61:12.7mm

R0652

R0651

PLACE_NEAR=U0500.AU61:12.7mm

1/20W

100

1

62

5%

MF

201

2

R0611

56

2 1

5%

1/20W

MF

201

R0620

1/20W

10K

1

5%

MF

201

2

1

1%

MF

201

2

CPU_CATERR_L

37 67

OUT

CPU_PECI

38 67

BI

CPU_PROCHOT_R_L

CPU_PWRGD

67

CPU_SM_RCOMP<0>

67

CPU_SM_RCOMP<1>

67

CPU_SM_RCOMP<2>

67

TP_CPU_MEM_RESET_L

18

OUT

CPU_MEMVTT_PWR_EN_LSVDDQ

17

OUT

D61

K61

N62

K63

C61

AU60 AV60 AU61

AV15

AV61

PROC_DETECT*

CATERR*

PECI

PROCHOT*

PROCPWRGD

SM_RCOMP0 SM_RCOMP1 SM_RCOMP2

SM_DRAMRST*

SM_PG_CNTL1

NC

BROADWELL-ULT

2C+GT2

BGA

SYM 2 OF 19

MISC

PWR

(IPU)

JTAG

THERMAL

DDR3

(IPD)

(IPU)

PRDY*

(IPU)

PREQ*

(IPU)

PROC_TCK PROC_TMS

PROC_TRST*

PROC_TDI PROC_TDO

BPM0*

(IPU)

BPM1*

(IPU)

BPM2*

(IPU)

BPM3*

(IPU)

BPM4*

(IPU)

BPM5*

(IPU)

BPM6*

(IPU)

BPM7*

(IPU)

J62 K62

E60 E61 E59

F63 F62

J60 H60 H61 H62 K59 H63 K60 J61

XDP_CPU_PRDY_L XDP_CPU_PREQ_L

XDP_CPU_TCK XDP_CPU_TMS XDP_CPUPCH_TRST_L

XDP_CPU_TDI XDP_CPU_TDO

XDP_BPM_L<0> XDP_BPM_L<1> XDP_BPM_L<2> XDP_BPM_L<3> XDP_BPM_L<4> XDP_BPM_L<5> XDP_BPM_L<6> XDP_BPM_L<7>

OUT

IN

IN IN IN

IN

OUT

BI BI BI BI BI BI BI BI

16 64 67

12 16 64 67

16 64 67

16 67

12

D

C

B

CFG<10>:SAFE MODE BOOT 1 = NORMAL OPERATION 0 = POWER FEATURES NOT ACTIVE CFG<9> :NO SVID-CAPABLE VR 1 = VR SUPPORTS SVID 0 = VR DOES NOT SUPPORT SVID CFG<8> :ALLOW NOA ON LOCKED UNITS 1 = NORMAL OPERATION 0 = NOA ALWAYS UNLOCKED CFG<4> :eDP ENABLE/DISABLE 1 = DISABLED 0 = ENABLED CFG<1> :PCH-LESS MODE 1 = NORMAL OPERATION 0 = PCH-LESS MODE CFG<0> :RESET SEQUENCE STALL 1 = NORMAL OPERATION 0 = STALL AFTER PCU PLL LOCK

These can be placed close to J1800 and are only for debug access

NOSTUFF

R0640

A

HSW_PRE_ES2

1

R0639

1K

5%

1/20W

5% 1/20W

MF

201

2

NOTE: Pre-ES2 CPUs have issue with Sx cycling, must set CFG<9> low to avoid issue, but this locks CPU VR at 1.7V Vboot (CPU Sighting #4391569).

CPU_CFG<4>

EDP

1

R0634

1K

5% 1/20W MF 201

2

NOSTUFF

R0638

6

16 67

1/20W

NOSTUFF

1

R0631

1K

5%

5% 1/20W

MF

201

2

CPU_CFG<10> CPU_CFG<9> CPU_CFG<8> CPU_CFG<1> CPU_CFG<0>

NOSTUFF

1

R0630

1K

5% 1/20W MF 201

2

C

CRITICAL

OMIT_TABLE

U0500

BROADWELL-ULT

2C+GT2

BGA

CPU_CFG<0>

6

16 67

BI

CPU_CFG<1>

6

16 67

BI

CPU_CFG<2>

16 67

BI

CPU_CFG<3>

16 64 67

BI

CPU_CFG<4>

6

16 67

BI

CPU_CFG<5>

16 67

BI

CPU_CFG<6>

16 67

BI

CPU_CFG<7>

16 67

BI

CPU_CFG<8>

6

16 67

BI

CPU_CFG<9>

6

16 67

BI

CPU_CFG<10>

6

16 67

BI

CPU_CFG<11>

16 67

BI

CPU_CFG<12>

16 67

BI

CPU_CFG<13>

16 67

BI

CPU_CFG<14>

16 67

BI

CPU_CFG<15>

16 67

BI

CPU_CFG<16>

16

BI

CPU_CFG<18>

16

BI

CPU_CFG<17>

16

BI

CPU_CFG<19>

16

BI

CPU_CFG_RCOMP

6

16 67

6

16 67

6

16 67

6

16 67

6

16 67

R0680

49.9

1/20W

PCH_TD_IREF

1

R0685

8.25K

1%

1% 1/20W

MF

201

2

AC60

CFG0

AC62

CFG1

AC63

CFG2

AA63

CFG3

AA60

CFG4

Y62

CFG5

Y61

CFG6

Y60

CFG7

V62

CFG8

V61

CFG9

V60

CFG10

U60

CFG11

T63

CFG12

T62

CFG13

T61

CFG14

T60

CFG15

AA62

CFG16

U63

CFG18

AA61

CFG17

U62

CFG19

V63

CFG_RCOMP

A5

J20 H18 B12

E1 D1

RSVD

RSVD RSVD RSVD RSVD TD_IREF

NC NC

NC NC NC

(IPU)

(IPU) (IPU)

(IPU)

(IPU) (IPU)

(IPU)

(IPU) (IPU)

(IPU)

(IPU) (IPU)

SYM 19 OF 19

RESERVED

PROC_OPI_COMP

6 3

RSVD_TP RSVD_TP

RSVD_B43

RSVD_TP RSVD_TP

RSVD_TP

RSVD

RSVD RSVD

VSS VSS

AV63 AU63

C63 C62

B43

A51 B51

L60

N60

W23 Y22

AY15

AV62 D58

P22 N21

P20 R20

NC

NC NC

TP_MCP_RSVD_AV63 TP_MCP_RSVD_AU63

TP_MCP_RSVD_C63 TP_MCP_RSVD_C62

TP_MCP_RSVD_A51 TP_MCP_RSVD_B51

TP_MCP_RSVD_L60

CPU_OPI_RCOMP

1

R0690

49.9

1% 1/20W MF 201

2

PAGE TITLE

CPU Misc/JTAG/CFG/RSVD

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=09/13/2012SYNC_MASTER=WILL_J43

DRAWING NUMBER

<SCH_NUM>

REVISION

BRANCH

PAGE

6 OF 121

SHEET

6 OF 76

124578

SIZE

B

A

D

8 7 6 5 4 3

12

CRITICAL

MEM_A_DQ<0>

63 70

BI

MEM_A_DQ<1>

63 70

BI

MEM_A_DQ<2>

63 70

BI

MEM_A_DQ<3>

63 70

BI

MEM_A_DQ<4>

63 70

BI

MEM_A_DQ<5>

63 70

BI

MEM_A_DQ<6>

63 70

BI

MEM_A_DQ<7>

63 70

BI

MEM_A_DQ<8>

63 70

D

C

B

63 70

21 63 70

63 70

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

MEM_A_DQ<9> MEM_A_DQ<10> MEM_A_DQ<11> MEM_A_DQ<12> MEM_A_DQ<13> MEM_A_DQ<14> MEM_A_DQ<15> MEM_A_DQ<16> MEM_A_DQ<17> MEM_A_DQ<18> MEM_A_DQ<19> MEM_A_DQ<20> MEM_A_DQ<21> MEM_A_DQ<22> MEM_A_DQ<23> MEM_A_DQ<24> MEM_A_DQ<25> MEM_A_DQ<26> MEM_A_DQ<27> MEM_A_DQ<28> MEM_A_DQ<29> MEM_A_DQ<30> MEM_A_DQ<31> MEM_A_DQ<32> MEM_A_DQ<33> MEM_A_DQ<34> MEM_A_DQ<35> MEM_A_DQ<36> MEM_A_DQ<37> MEM_A_DQ<38> MEM_A_DQ<39> MEM_A_DQ<40> MEM_A_DQ<41> MEM_A_DQ<42> MEM_A_DQ<43> MEM_A_DQ<44> MEM_A_DQ<45> MEM_A_DQ<46> MEM_A_DQ<47> MEM_A_DQ<48> MEM_A_DQ<49> MEM_A_DQ<50> MEM_A_DQ<51> MEM_A_DQ<52> MEM_A_DQ<53> MEM_A_DQ<54> MEM_A_DQ<55> MEM_A_DQ<56> MEM_A_DQ<57> MEM_A_DQ<58> MEM_A_DQ<59> MEM_A_DQ<60> MEM_A_DQ<61> MEM_A_DQ<62> MEM_A_DQ<63>

AH63 AH62 AK63 AK62 AH61 AH60 AK61 AK60 AM63 AM62 AP63 AP62 AM61 AM60 AP61 AP60 AP58 AR58 AM57 AK57 AL58 AK58 AR57 AN57 AP55 AR55 AM54 AK54 AL55 AK55 AR54 AN54 AY58 AW58 AY56 AW56 AV58 AU58 AV56 AU56 AY54 AW54 AY52 AW52 AV54 AU54 AV52 AU52 AK40 AK42 AM43 AM45 AK45 AK43 AM40 AM42 AM46 AK46 AM49 AK49 AM48 AK48 AM51 AK51

SA_DQ0 SA_DQ1 SA_DQ2 SA_DQ3 SA_DQ4 SA_DQ5 SA_DQ6 SA_DQ7 SA_DQ8 SA_DQ9 SA_DQ10 SA_DQ11 SA_DQ12 SA_DQ13 SA_DQ14 SA_DQ15 SA_DQ16 SA_DQ17 SA_DQ18 SA_DQ19 SA_DQ20 SA_DQ21 SA_DQ22 SA_DQ23 SA_DQ24 SA_DQ25 SA_DQ26 SA_DQ27 SA_DQ28 SA_DQ29 SA_DQ30 SA_DQ31 SA_DQ32 SA_DQ33 SA_DQ34 SA_DQ35 SA_DQ36 SA_DQ37 SA_DQ38 SA_DQ39 SA_DQ40 SA_DQ41 SA_DQ42 SA_DQ43 SA_DQ44 SA_DQ45 SA_DQ46 SA_DQ47 SA_DQ48 SA_DQ49 SA_DQ50 SA_DQ51 SA_DQ52 SA_DQ53 SA_DQ54 SA_DQ55 SA_DQ56 SA_DQ57 SA_DQ58 SA_DQ59 SA_DQ60 SA_DQ61 SA_DQ62 SA_DQ63

OMIT_TABLE

U0500

BROADWELL-ULT

2C+GT2

BGA

SYM 3 OF 19

MEMORY CHANNEL A

LPDDR3

RSVD1

RSVD2

SA_CLK0*

SA_CLK0

SA_CLK1*

SA_CLK1

SA_CKE0 SA_CKE1 SA_CKE2 SA_CKE3

SA_CS0* SA_CS1*

SA_ODT0

SA_RAS*

CAB3

SA_WE*

CAB2

SA_CAS*

CAB1

SA_BA0

CAB4

SA_BA1

CAB6

SA_BA2

CAA5

SA_MA0

CAB9

SA_MA1

CAB8

SA_MA2

CAB5

SA_MA3 SA_MA4 SA_MA5

CAA0

SA_MA6

CAA2

SA_MA7

CAA4

SA_MA8

CAA3

SA_MA9

CAA1

SA_MA10

CAB7

SA_MA11

CAA7

SA_MA12

CAA6

SA_MA13

CAB0

SA_MA14

CAA9

SA_MA15

CAA8

SA_DQSN0 SA_DQSN1 SA_DQSN2 SA_DQSN3 SA_DQSN4 SA_DQSN5 SA_DQSN6 SA_DQSN7

SA_DQSP0 SA_DQSP1 SA_DQSP2 SA_DQSP3 SA_DQSP4 SA_DQSP5 SA_DQSP6 SA_DQSP7

SM_VREF_CA

SM_VREF_DQ0

SM_VREF_DQ1

AU37 AV37 AW36 AY36

AU43 AW43 AY42 AY43

AP33 AR32

AP32

AY34 AW34 AU34

AU35 AV35 AY41

AU36 AY37 AR38 AP36 AU39 AR36 AV40 AW39 AY39 AU40 AP35 AW41 AU41 AR35 AV42 AU42

AJ61 AN62 AM58 AM55 AV57 AV53 AL43 AL48

AJ62 AN61 AN58 AN55 AW57 AW53 AL42 AL49

AP49

AR51

AP51

MEM_A_CLK_N<0> MEM_A_CLK_P<0> MEM_A_CLK_N<1> MEM_A_CLK_P<1>

MEM_A_CKE<0> MEM_A_CKE<1> MEM_A_CKE<2> MEM_A_CKE<3>

MEM_A_CS_L<0> MEM_A_CS_L<1>

MEM_A_ODT<0>

=MEM_A_RAS_L =MEM_A_WE_L =MEM_A_CAS_L

=MEM_A_BA<0> MEM_A_CAB<6> =MEM_A_BA<2>

=MEM_A_A<0> =MEM_A_A<1> =MEM_A_A<2> TP_LPDDR3_RSVD1 TP_LPDDR3_RSVD2 =MEM_A_A<5> =MEM_A_A<6> =MEM_A_A<7> =MEM_A_A<8> =MEM_A_A<9> =MEM_A_A<10> =MEM_A_A<11> MEM_A_CAA<6> =MEM_A_A<13> =MEM_A_A<14> =MEM_A_A<15>

MEM_A_DQS_N<0> MEM_A_DQS_N<1> MEM_A_DQS_N<2> MEM_A_DQS_N<3> MEM_A_DQS_N<4> MEM_A_DQS_N<5> MEM_A_DQS_N<6> MEM_A_DQS_N<7>

MEM_A_DQS_P<0> MEM_A_DQS_P<1> MEM_A_DQS_P<2> MEM_A_DQS_P<3> MEM_A_DQS_P<4> MEM_A_DQS_P<5> MEM_A_DQS_P<6> MEM_A_DQS_P<7>

CPU_DIMM_VREFCA

CPU_DIMMA_VREFDQ

CPU_DIMMB_VREFDQ

OUT OUT OUT OUT

OUT OUT

OUT

OUT OUT OUT

OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT

BI BI BI BI BI BI BI BI

OUT

20 24 70

21 24 70

20 24 70

21 24 70

20 21 24 70

20 21 24 63 70

63

21 24 63 70

63

20 24 63 70

63

63 70

21 63 70

63 70

21 63 70

63 70

19

63 70

23 63 70

63 70

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

MEM_B_DQ<0> MEM_B_DQ<1> MEM_B_DQ<2> MEM_B_DQ<3> MEM_B_DQ<4> MEM_B_DQ<5> MEM_B_DQ<6> MEM_B_DQ<7> MEM_B_DQ<8> MEM_B_DQ<9> MEM_B_DQ<10> MEM_B_DQ<11> MEM_B_DQ<12>

MEM_B_DQ<14>

MEM_B_DQ<16>

MEM_B_DQ<18>

MEM_B_DQ<22> MEM_B_DQ<23> MEM_B_DQ<24> MEM_B_DQ<25> MEM_B_DQ<26> MEM_B_DQ<27> MEM_B_DQ<28> MEM_B_DQ<29> MEM_B_DQ<30> MEM_B_DQ<31> MEM_B_DQ<32>

MEM_B_DQ<36>

MEM_B_DQ<39> MEM_B_DQ<40> MEM_B_DQ<41> MEM_B_DQ<42> MEM_B_DQ<43> MEM_B_DQ<44> MEM_B_DQ<45> MEM_B_DQ<46> MEM_B_DQ<47> MEM_B_DQ<48> MEM_B_DQ<49> MEM_B_DQ<50> MEM_B_DQ<51> MEM_B_DQ<52> MEM_B_DQ<53> MEM_B_DQ<54> MEM_B_DQ<55> MEM_B_DQ<56> MEM_B_DQ<57> MEM_B_DQ<58> MEM_B_DQ<59> MEM_B_DQ<60> MEM_B_DQ<61> MEM_B_DQ<62> MEM_B_DQ<63>

AY31

SB_DQ0

AW31

SB_DQ1

AY29

SB_DQ2

AW29

SB_DQ3

AV31

SB_DQ4

AU31

SB_DQ5

AV29

SB_DQ6

AU29

SB_DQ7

AY27

SB_DQ8

AW27

SB_DQ9

AY25

SB_DQ10 SB_CS0*

AW25

SB_DQ11 SB_CS1*

AV27

SB_DQ12

AU27

SB_DQ13 SB_ODT0

AV25

SB_DQ14

AU25

SB_DQ15 SB_RAS*

AM29

SB_DQ16

AK29

SB_DQ17 SB_CAS*

AL28

SB_DQ18

AK28

SB_DQ19

AR29

SB_DQ20

AN29

SB_DQ21

AR28

SB_DQ22

AP28

SB_DQ23

AN26

SB_DQ24

AR26

SB_DQ25

AR25

SB_DQ26

AP25

SB_DQ27

AK26

SB_DQ28

AM26

SB_DQ29

AK25

SB_DQ30

AL25

SB_DQ31

AY23

SB_DQ32

AW23

SB_DQ33 SB_MA10

AY21

SB_DQ34 SB_MA11

AW21

SB_DQ35 SB_MA12

AV23

SB_DQ36

AU23

SB_DQ37 SB_MA14

AV21

SB_DQ38 SB_MA15

AU21

SB_DQ39

AY19

SB_DQ40

AW19

SB_DQ41

AY17

SB_DQ42

AW17

SB_DQ43

AV19

SB_DQ44

AU19

SB_DQ45

AV17

SB_DQ46

AU17

SB_DQ47

AR21

SB_DQ48

AR22

SB_DQ49

AL21

SB_DQ50

AM22

SB_DQ51

AN22

SB_DQ52

AP21

SB_DQ53

AK21

SB_DQ54

AK22

SB_DQ55

AN20

SB_DQ56

AR20

SB_DQ57

AK18

SB_DQ58

AL18

SB_DQ59

AK20

SB_DQ60

AM20

SB_DQ61

AR18

SB_DQ62

AP18

SB_DQ63

CRITICAL

OMIT_TABLE

U0500

BROADWELL-ULT

2C+GT2

BGA

SYM 4 OF 19

MEMORY CHANNEL B

LPDDR3

RSVD3

RSVD4

CAB3

CAB2 CAB1

CAB4 CAB6

CAA5

CAB9

CAB8 CAB5

CAA0

CAA2

CAA4 CAA3

CAA1

CAB7 CAA7

CAA6 CAB0

CAA9

CAA8

SB_CK0*

SB_CK0

SB_CK1*

SB_CK1

SB_CKE0 SB_CKE1 SB_CKE2 SB_CKE3

SB_WE*

SB_BA0 SB_BA1 SB_BA2

SB_MA0 SB_MA1 SB_MA2 SB_MA3 SB_MA4 SB_MA5 SB_MA6 SB_MA7 SB_MA8 SB_MA9

SB_MA13

SB_DQSN0 SB_DQSN1 SB_DQSN2 SB_DQSN3 SB_DQSN4 SB_DQSN5 SB_DQSN6 SB_DQSN7

SB_DQSP0 SB_DQSP1 SB_DQSP2 SB_DQSP3 SB_DQSP4 SB_DQSP5 SB_DQSP6 SB_DQSP7

AM38 AN38 AK38 AL38

AY49 AU50 AW49 AV50

AM32 AK32

AL32

AM35 AK35 AM33

AL35 AM36 AU49

AP40 AR40 AP42 AR42 AR45 AP45 AW46 AY46 AY47 AU46 AK36 AV47 AU47 AK33 AR46 AP46

AW30 AV26 AN28 AN25 AW22 AV18 AN21 AN18

AV30 AW26 AM28 AM25 AV22 AW18 AM21 AM18

MEM_B_CLK_N<0> MEM_B_CLK_P<0> MEM_B_CLK_N<1> MEM_B_CLK_P<1>

MEM_B_CKE<0> MEM_B_CKE<1> MEM_B_CKE<2> MEM_B_CKE<3>

MEM_B_CS_L<0> MEM_B_CS_L<1>

MEM_B_ODT<0>MEM_B_DQ<13>

=MEM_B_RAS_LMEM_B_DQ<15> =MEM_B_WE_L =MEM_B_CAS_LMEM_B_DQ<17>

=MEM_B_BA<0>MEM_B_DQ<19> MEM_B_CAB<6>MEM_B_DQ<20> =MEM_B_BA<2>MEM_B_DQ<21>

=MEM_B_A<0> =MEM_B_A<1> =MEM_B_A<2> TP_LPDDR3_RSVD3 TP_LPDDR3_RSVD4 =MEM_B_A<5> =MEM_B_A<6> =MEM_B_A<7> =MEM_B_A<8> =MEM_B_A<9> =MEM_B_A<10>MEM_B_DQ<33> =MEM_B_A<11>MEM_B_DQ<34> MEM_B_CAA<6>MEM_B_DQ<35> =MEM_B_A<13> =MEM_B_A<14>MEM_B_DQ<37> =MEM_B_A<15>MEM_B_DQ<38>

MEM_B_DQS_N<0> MEM_B_DQS_N<1> MEM_B_DQS_N<2> MEM_B_DQS_N<3> MEM_B_DQS_N<4> MEM_B_DQS_N<5> MEM_B_DQS_N<6> MEM_B_DQS_N<7>

MEM_B_DQS_P<0> MEM_B_DQS_P<1> MEM_B_DQS_P<2> MEM_B_DQS_P<3> MEM_B_DQS_P<4> MEM_B_DQS_P<5> MEM_B_DQS_P<6> MEM_B_DQS_P<7>

OUT OUT OUT OUT

OUT OUT

OUT

OUT OUT OUT

OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT

BI BI BI BI BI BI BI BI

22 24 70

23 24 70

22 24 70

23 24 70

22 23 24 70

22 23 24 63 70

63

23 24 63 70

63

22 24 63 70

63

63 70

23 63 70

63 70

23 63 70

63 70

D

C

B

A

6 3

SYNC_MASTER=WILL_J43 SYNC_DATE=09/13/2012

PAGE TITLE

CPU DDR3/LPDDR3 Interfaces

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

DRAWING NUMBER

<SCH_NUM>

REVISION

BRANCH

PAGE

7 OF 121

SHEET

7 OF 76

124578

SIZE

A

D

8 7 6 5 4 3

HSW-ULT current estimates from Haswell Mobile ULT Processor EDS vol 1, doc #502406, v0.9. LPT-LP current estimates from Lynx Point-LP PCH EDS, doc #503118, v1.0. Note [1] current numbers from clarification email, from Srini, dated 9/10/2012 2:11pm.

D

C

PP1V05_S0SW_PCH_HSIO

11 58 62

1838mA Max

PP1V05_S0

6 8

11 15 16 17 38 42 51

55 58 59 62 64

29mA Max[1]

PP1V05_S0SW_PCH_VCCUSB3PLL

11 14

41mA Max

PP1V05_S0SW_PCH_VCCSATA3PLL

B

A

11 12

42mA Max

WF: RSVD on Sawtooth Peak rev 1.0

PP1V05_S0_PCH_VCCAPLL_OPI

11

57mA Max

PP1V5_S0SW_AUDIO_HDA

11 17 58

11mA Max

PP3V3_SUS

8

11 14 18 46 57 58 59 62

64

59mA Max[1]

PP3V3_S5

11 13 15 16 17 18 28 29 34 42 57 58 59 60 62 64 74

114mA Max

56 59 61 62 64 65 74

PP3V3_S0

8

11 12 13 15 17 18 26 30

36 38 39 40 41 42 43 44 45

40mA Max[1]

PP1V05_S0_PCH_VCC_ICC

11

VCCCLK: 200mA Max

PP1V05_S0_PCH_VCCACLKPLL

11 12

31mA Max

PP1V05_S0

6 8

11 15 16 17 38 42 51

55 58 59 62 64

VCCCLK: 200mA Max

WF: RSVD on Sawtooth Peak rev 1.0

PP3V3_SUS

8

11 14 18 46 57 58 59 62

64

K9

L10

M9

N8 P9

B18

B11

Y20

NC

AA21

W21

J13

NC

AH14

AH13

NC

AC9 AA9

AH10

V8 W9

J18 K19

A20

J17 R21 T21 K18

NC

M20

NC

V21

NC

AE20 AE21

VCCHSIO VCCHSIO VCCHSIO

VCC1_05 VCC1_05

VCCUSB3PLL

VCCSATA3PLL

VCCAPLL VCCAPLL VCCAPLL

DCPSUS3

AZALIA/HDA

VCCHDA

VRM/USB2/AZALIA

DCPSUS2

VCCSUS3_3 VCCSUS3_3

VCCDSW3_3

VCC3_3 VCC3_3

VCCCLK VCCCLK

VCCACLKPLL

VCCCLK VCCCLK VCCCLK RSVD RSVD RSVD

VCCSUS3_3 VCCSUS3_3

CRITICAL

OMIT_TABLE

U0500

BROADWELL-ULT

2C+GT2

BGA

SYM 13 OF 19

SPI RTC

HSIO

OPI

USB3

CORE

GPIO/LCC

THERMAL SENSOR

SERIAL IO

SUS OSCILLATOR

ICC

USB2

LPT LP POWER

VCCSUS3_3

VCCRTC

DCPRTC

VCCSPI

VCCASW VCCASW

VCC1P05 VCC1P05 VCC1P05 VCC1P05 VCC1P05

DCPSUSBYP DCPSUSBYP

VCCASW VCCASW VCCASW

DCPSUS1 DCPSUS1

VCCTS1_5

VCC3_3 VCC3_3

VCCSDIO VCCSDIO

DCPSUS4

RSVD

VCC1_05 VCC1_05

PPVMEMIO_S0_CPU

10 42

1.4A Max (DDR3: 1.5-1.35V)

1.1A Max (LPDDR3: 1.2V)

PPVCC_S0_CPU

8

10 42 52 62 64

1

R0860

100

5%

1/20W

MF

201

2

CPU_VIDALERT_R_L CPU_VIDSCLK_R CPU_VIDSOUT_R CPU_VCCST_PWRGD

16 17

IN

CPU_VR_EN

17 51

OUT

CPU_VR_READY

17 51

IN

CPU_PWR_DEBUG

16

IN

TP_CPU_RSVD_P60 TP_CPU_RSVDP61

18

TP_CPU_RSVD_N59 TP_CPU_RSVDN61

18

PP1V05_S0

6 8

11 15 16 17 38 42 51 55

58 59 62 64

???mA Max

12 13 17 62 64

BYPASS=R0899:U0500:2.54mm

11 15 16 17 38 42 51 55

51 67

IN

51 67

OUT

51 67

BI

AH11

PP3V3_SUS

0.3mA Max[1]

AG10

AE7

PPVOUT_S0_PCH_DCPRTC

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V

Y8

PP3V3_SUS

18mA Max

AG14

PP1V05_S0

AG13

185mA Max[1]

J11

PP1V05_S0

H11

1499mA Max[1]

H15 AE8 AF22

AG19

PPVOUT_S5_PCH_DCPSUSBYP_R

MIN_LINE_WIDTH=0.2 mm

AG20

MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V

AE9

PP1V05_S0

AF9

473mA Max[1]

AG8

AD10

NC

AD8

NC

J15

PP1V5_S0

3mA Max

K14

PP3V3_S0

K16

1mA Max[1]

U8

PP3V3_S0

T9

17mA Max

AB8

NC

AC20

AG16 AG17

WF: RSVD on Sawtooth Peak rev 1.0

NC

PP1V05_S0

213mA Max[1]3.3mA Max[1]

PP1V05_S0

6 8 58 59 62 64

CPU_VIDALERT_L

CPU_VIDSCLK

CPU_VIDSOUT

R0800

75

1%

1/20W

MF

201

R0811

0

5%

1/20W

MF

0201

8

11 14 18 46 57 58 59 62 64

BYPASS=U0500.AE7:6.35mm

8

11 14 18 46 57 58 59

62 64

6 8 55 58 59 62 64

6 8 59 62 64

Powered in DeepSx

6 8 59 62 64

57 58 59 62 64

62 64 65 74 8

11 12 13 15 17 18 26 30 36 38

39 40 41 42 43 44 45 56 59 61

62 64 65 74 8

11 12 13 15 17 18 26 30 36 38

39 40 41 42 43 44 45 56 59 61

6 8 59 62 64

1

R0810

2

43

21

5%

1/20W

MF

201

21

R0812

0

21

5%

1/20W

MF

0201

11 15 16 17 38 42 51

11 15 16 17 38 42 51 55 58

PLACE_NEAR=U0500.AG19:2.54mm

R0899

5.11

1/20W

11 15 16 17 38 42 51 55 58

MF-LF

1

R0802

130

1% 1/20W MF 201

2

R0802.2:

R0810.2: R0800.2:

1

C0895

0.1UF

20% 10V

2

CERM 402

21

PPVOUT_S5_PCH_DCPSUSBYP

MIN_LINE_WIDTH=0.2 mm

1%

MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V

201

PLACE_NEAR=U0500.C50:50.8mm

Max load: 300mA

PLACE_NEAR=U0500.L63:2.54mm

PLACE_NEAR=U0500.L62:38.1mm PLACE_NEAR=R0810.1:2.54mm

1

C0892

0.1UF

20% 10V

2

CERM

402

C0891

BYPASS=U0500.AG10:6.35mm

CPU_VCCSENSE_P

51 67

OUT

TP_PPVCCIO_S0_CPU

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V

PPVCOMP_S0_CPU

5

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V

NOTE: Aliases not used on CPU supply outputs to avoid any extraneous connections.

PPVRTC_G3H

1

0.1UF

20% 10V

CERM

402

C0890

1UF

10%

6.3V

2

CERM 402

BYPASS=U0500.AG10:6.35mm

1

C0899

1UF

10%

6.3V

2

CERM 402

6 3

12

CRITICAL

L59 J58

AH26 AJ31 AJ33 AJ37 AN33 AP43 AR48 AY35 AY40 AY44 AY50

F59 N58

AC58

E63

AB23

A59

E20 AD23 AA23 AE59

L62

N63

L63

B59

F60

C59

D63

H59

P62

P60

P61

N59

N61

T59 AD60 AD59 AA59 AE60 AC59 AG58

U59

V59

AC22 AE22 AE23

AB57 AD57 AG57

C24

C28

C32

RSVD RSVD

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VCC RSVD RSVD

VCC_SENSE

RSVD VCCIO_OUT VCCIOA_OUT RSVD RSVD RSVD

VIDALERT* VIDSCLK VIDSOUT VCCST_PWRGD VR_EN VR_READY

VSS PWR_DEBUG* VSS RSVD_TP RSVD_TP RSVD_TP RSVD_TP RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD

VCCST VCCST VCCST

VCC VCC VCC VCC VCC VCC

NC NC

NC

NC NC NC

NC NC NC NC NC NC NC NC NC

U0500

BROADWELL-ULT

2C+GT2

BGA

SYM 12 OF 19

HSW ULT POWER

SYNC_MASTER=J43_MLB

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC

R

OMIT_TABLE

PPVCC_S0_CPU

C36 C40 C44 C48 C52 C56 E23 E25 E27 E29 E31 E33 E35 E37 E39 E41 E43 E45 E47 E49 E51 E53 E55 E57 F24 F28 F32 F36 F40 F44 F48 F52 F56 G23 G25 G27 G29 G31 G33 G35 G37 G39 G41 G43 G45 G47 G49 G51 G53 G55 G57 H23 J23 K23 K57 L22 M23 M57 P57 U57 W57

CPU/PCH POWER

Apple Inc.

32A Max

8

10 42 52 62 64

SYNC_DATE=10/02/2012

DRAWING NUMBER

<SCH_NUM>

REVISION

BRANCH

PAGE

8 OF 121

SHEET

8 OF 76

SIZE

D

C

B

A

D

124578

8 7 6 5 4 3

12

CRITICAL

OMIT_TABLE

U0500

BROADWELL-ULT

2C+GT2

BGA

SYM 14 OF 19

A11

VSS

A14

VSS

A18

VSS

A24

VSS

A28

VSS

AA58 AB10 AB20 AB22

AC61 AD21

AD63 AE10

AE58 AF11 AF12 AF14 AF15 AF17 AF18

AG11 AG21 AG23 AG60 AG61 AG62 AG63 AH17 AH19 AH20 AH22 AH24 AH28 AH30 AH32 AH34 AH36 AH38 AH40 AH42 AH44 AH49 AH51 AH53 AH55 AH57 AJ13 AJ14 AJ23 AJ25 AJ27 AJ29

A32 A36 A40 A44 A48 A52 A56 AA1

AB7

AD3

AE5

AG1

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

D

C

B

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

AJ35 AJ39 AJ41 AJ43 AJ45 AJ47 AJ50 AJ52 AJ54 AJ56 AJ58 AJ60 AJ63 AK23 AK3 AK52 AL10 AL13 AL17 AL20 AL22 AL23 AL26 AL29 AL31 AL33 AL36 AL39 AL40 AL45 AL46 AL51 AL52 AL54 AL57 AL60 AL61 AM1 AM17 AM23 AM31 AM52 AN17 AN23 AN31 AN32 AN35 AN36 AN39 AN40 AN42 AN43 AN45 AN46 AN48 AN49 AN51 AN52 AN60 AN63 AN7 AP10 AP17 AP20

AP22 AP23 AP26 AP29

AP3 AP31 AP38 AP39 AP48 AP52 AP54 AP57 AR11 AR15 AR17 AR23 AR31 AR33 AR39 AR43 AR49

AR5 AR52 AT13 AT35 AT37 AT40 AT42 AT43 AT46 AT49 AT61 AT62 AT63

AU1 AU16 AU18 AU20 AU22 AU24 AU26 AU28 AU30 AU33 AU51 AU53 AU55 AU57 AU59 AV14 AV16 AV20 AV24 AV28 AV33 AV34 AV36 AV39 AV41 AV43 AV46 AV49 AV51 AV55

CRITICAL

OMIT_TABLE

U0500

BROADWELL-ULT

2C+GT2

BGA

SYM 15 OF 19 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

AV59 AV8 AW16 AW24 AW33 AW35 AW37 AW4 AW40 AW42 AW44 AW47 AW50 AW51 AW59 AW60 AY11 AY16 AY18 AY22 AY24 AY26 AY30 AY33 AY4 AY51 AY53 AY57 AY59 AY6 B20 B24 B26 B28 B32 B36 B4 B40 B44 B48 B52 B56 B60 C11 C14 C18 C20 C25 C27 C38 C39 C57 D12 D14 D18 D2 D21 D23 D25 D26 D27 D29 D30 D31

D33 D34 D35 D37 D38 D39 D41 D42 D43 D45 D46 D47 D49

D50 D51 D53 D54 D55 D57 D59 D62

E11 E17 F20 F26 F30 F34 F38 F42 F46 F50 F54 F58 F61 G18 G22

H13

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

D5

VSS VSS VSS VSS VSS VSS VSS VSS VSS

D8

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

G3

VSS

G5

VSS

G6

VSS

G8

VSS VSS

CRITICAL

OMIT_TABLE

U0500

BROADWELL-ULT

2C+GT2

BGA

SYM 16 OF 19

VSS_SENSE

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS VSS VSS

VSS

H17 H57 J10 J22 J59 J63 K1 K12 L13 L15 L17 L18 L20 L58 L61 L7 M22 N10 N3 P59 P63 R10 R22 R8 T1 T58 U20 U22 U61 U9 V10 V3 V7 W20 W22 Y10 Y59 Y63

V58 AH46 V23 E62 AH16

CPU_VCCSENSE_N

1

R0960

100

5%

PLACE_NEAR=U0500.E62:50.8mm

1/20W MF 201

2

D

C

51 67

OUT

B

A

6 3

SYNC_MASTER=J43_MLB

PAGE TITLE

CPU/PCH GROUNDS

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=10/02/2012

DRAWING NUMBER

<SCH_NUM>

REVISION

BRANCH

PAGE

9 OF 121

SHEET

9 OF 76

124578

SIZE

A

D

8 7 6 5 4 3

All Intel recommendations from Intel doc #503160 Shark Bay Ultrabook Platform Power Delivery Design Guide Rev 1.0 unless stated otherwise

CPU VCC Decoupling

PPVCC_S0_CPU

8

42 52 62 64

D

Intel recommendation (Table 5-1): 23x 22uF 0805 stuff, 7x 22uF 0805 nostuff Apple implementation : 18x 10uF 0402 mirrored stuff, 1x 470uF stuff, 50x 10uF mirrored no stuff, 50x 10uF single sided no stuff

CRITICAL

1

C1000

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C1015

10UF

20% 4V

2

X6S 0402

CRITICAL

1

C1001

10UF

20% 4V

2

X6S 0402

CRITICAL

1

C1016

10UF

20% 4V

2

X6S 0402

CRITICAL

1

C1002

10UF

20% 4V

2

X6S 0402

CRITICAL

1

C1017

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C1003

10UF

20% 4V

2

X6S 0402

CRITICAL

1

C1018

10UF

20% 4V

2

X6S 0402

CRITICAL

1

C1004

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C1019

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C1005

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C1020

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C1006

10UF

20% 4V

2

X6S 0402

CRITICAL

1

C1021

10UF

20% 4V

2

X6S 0402

CRITICAL

1

C1007

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C1030

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C1008

10UF

20%

4V

2

X6S 0402

NO STUFF

1

C104A

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C1009

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C104B

10UF

20% 4V

2

X6S 0402

CRITICAL

1

C1010

10UF

20%

4V

2

X6S 0402

NO STUFF

1

C104C

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C1011

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C104D

10UF

20% 4V

2

X6S 0402

CRITICAL

1

C1012

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C104E

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C1013

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C104F

10UF

20% 4V

2

X6S 0402

CRITICAL

1

C1014

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C106A

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C105A

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C106B

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C105B

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C106C

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C105C

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C106D

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C105D

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C106E

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C105E

10UF

20% 4V

2

X6S 0402

12

NO STUFF

1

C105F

10UF

20% 4V

2

X6S 0402

D

NO STUFF

1

C1070

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C1085

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C

B

C1022

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C1039

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C1056

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C109B

10UF

20% 4V

2

X6S 0402

CRITICAL

1

C1031

470UF-0.0045OHM

20%

2.5V

3 2

POLY-TANT SM

NO STUFF

1

C1071

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C1086

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C1023

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C1044

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C1057

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C109C

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C1072

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C1087

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C1024

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C1045

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C1058

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C109D

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C1073

10UF

20% 4V

2

X6S 0402

CRITICAL

1

C1088

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C1025

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C1046

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C1059

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C109E

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C1074

10UF

20% 4V

2

X6S 0402

CRITICAL

1

C1089

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C1026

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C1047

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C1062

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C109F

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C1075

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C1090

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C1027

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C1048

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C1063

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C108A

10UF

20% 4V

2

X6S 0402

CRITICAL

1

C1076

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C1091

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C1028

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C1049

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C1064

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C108B

10UF

20% 4V

2

X6S 0402

CRITICAL

1

C1077

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C1092

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C1029

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C1065

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C108C

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C1078

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C1093

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C1032

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C1066

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C108D

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C1079

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C1094

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C1033

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C1067

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C108E

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C1080

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C1095

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C1034

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C1068

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C108F

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C1081

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C1096

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C1035

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C1069

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C107A

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C1082

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C1097

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C1036

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C1098

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C107B

10UF

20% 4V

2

X6S 0402

CRITICAL

1

C1083

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C1037

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C1099

10UF

20% 4V

2

X6S 0402

CRITICAL

1

C1084

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C1038

10UF

20% 4V

2

X6S 0402

NO STUFF

1

C109A

10UF

20% 4V

2

X6S 0402

C

B

CPU VDDQ DECOUPLING

PPVMEMIO_S0_CPU

8

42

A

Intel recommendation (Table 5-4): 4x 2.2uF 0402, 6x 10uF 0603 Apple implementation : 4x 2.2uF 0402, 6x 10uF 0402, 2x 270uF B2 no stuff

1

C1040

2

1

C1050

2

1

C1060

270UF

20% 2V

2

TANT CASE-B2-SM

2.2UF

20%

6.3V CERM 402-LF

10UF

20%

6.3V CERM-X5R 0402-1

1

C1041

2.2UF

20%

6.3V

2

CERM 402-LF

1

C1051

10UF

20%

6.3V

2

CERM-X5R 0402-1

NO STUFF

1

C1061

270UF

20% 2V

2

TANT CASE-B2-SM

1

2

1

2

C1042

2.2UF

20%

6.3V CERM 402-LF

C1052

10UF

20%

6.3V CERM-X5R 0402-1

1

2

1

C1053

2

C1043

2.2UF

20%

6.3V CERM 402-LF

10UF

20%

6.3V CERM-X5R 0402-1

1

C1054

2

10UF

20%

6.3V CERM-X5R 0402-1

2x Bulk nostuff per Harris Beach v1.0 schematic

1

C1055

2

6 3

10UF

20%

6.3V CERM-X5R 0402-1

PAGE TITLE

CPU Decoupling

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=01/08/2013SYNC_MASTER=WILL_J43

DRAWING NUMBER

<SCH_NUM>

REVISION

BRANCH

PAGE

10 OF 121

SHEET

10 OF 76

124578

SIZE

A

D

8 7 6 5 4 3

12

PCH VCCDSW3_3 BYPASS (PCH 3.3V DSW PWR)

PP3V3_S5

8

13 15 16 17 18 28 29 34 42

57 58 59 60 62 64 74

PCH VCCSPI BYPASS

D

(PCH 3.3V SPI PWR)

PP3V3_SUS

8

11 14 18 46 57 58 59 62 64

PCH VCCSUS3_3 BYPASS (PCH 3.3V SUSPEND PWR)

PP3V3_SUS

8

11 14 18 46 57 58 59 62 64

PCH VCCSUS3_3 BYPASS (PCH 3.3V SUSPEND RTC PWR)

PP3V3_SUS

8

11 14 18 46 57 58 59 62 64

C

PCH VCCSDIO BYPASS (PCH 3.3V/1.8V SDIO PWR)

61 62 64 65 74

PP3V3_S0

8

11 12 13 15 17 18 26 30 36

38 39 40 41 42 43 44 45 56 59

NO STUFF

C1200

BYPASS=U0500.AH10:6.35mm

NO STUFF

C1202

0.1UF

BYPASS=U0500.Y8:6.35mm

C1204

22UF

X5R-CERM-1

BYPASS=U0500.AC9:12.7mm

C1206

BYPASS=U0500.AH11:6.35mm

C1208

BYPASS=U0500.U8:6.35mm

6.3V CERM

CERM

6.3V

6.3V CERM

1UF

1

10%

2

402

1

20% 10V

2

402

1

20%

2

603

1

10%

2

402

1

10%

2

402

PCH VCC3_3 BYPASS (PCH 3.3V GPIO/LPC PWR)

61 62 64 65 74

PP3V3_S0

8

11 12 13 15 17 18 26 30 36

38 39 40 41 42 43 44 45 56 59

PCH VCC3_3 BYPASS (PCH 3.3V THERMAL PWR)

61 62 64 65 74

PP3V3_S0

8

11 12 13 15 17 18 26 30 36

38 39 40 41 42 43 44 45 56 59

11 15 16 17 38 42 51 55

PP1V05_S0

6 8 58 59 62 64

??mA Max

C1212

22UF

X5R-CERM-1

BYPASS=U0500.V8:12.7mm

C1214

0.1UF

BYPASS=U0500.K14:6.35mm

6.3V

CERM

1

20%

2

603

1

20% 10V

2

402

R1270

0

21

PP1V05_S0_PCH_VCCACLKPLL_R

MIN_LINE_WIDTH=0.2 MM

5%

MIN_NECK_WIDTH=0.2 MM

1/16W

VOLTAGE=1.05V

MF-LF

402

PCH VCCASW BYPASS (PCH 1.05V ME CORE PWR)

PP1V05_S0

6 8

11 15 16 17 38 42 51 55

58 59 62 64

PCH VCC BYPASS (PCH 1.05V CORE PWR)

PP1V05_S0

6 8

11 15 16 17 38 42 51 55

58 59 62 64

PCH VCCHSIO BYPASS (PCH 1.05V PCIe/SATA/USB3 PWR)

PP1V05_S0SW_PCH_HSIO

8

11 58 62

NO STUFF

C1250

22UF

20%

6.3V

X5R-CERM-1

BYPASS=U0500.AE9:12.7mm

BYPASS=U0500.J11:12.7mm

BYPASS=U0500.K9:6.35mm

2.2UH-240MA-0.221OHM

BYPASS=U0500.A20:12.7mm

603

BYPASS=U0500.AE9:6.35mm

C1255

10UF

20%

6.3V X5R 603

BYPASS=U0500.J11:6.35mm

C1260

1UF

10%

6.3V

CERM

402

CRITICAL

L1270

0603

C1270

47UF

CERM-X5R

0805-1

1

C1251

1UF

10%

6.3V

2

CERM 402

1

C1256

1UF

10%

6.3V

2

CERM

402

BYPASS=U0500.AE8:6.35mm

1

C1261

1UF

6.3V

2

CERM

BYPASS=U0500.L10:6.35mm

BYPASS=U0500.M9:6.35mm

21

1

C1271

20%

4V

BYPASS=U0500.A20:12.7mm

47UF

2

CERM-X5R

0805-1

BYPASS=U0500.A20:6.35mm

PCH VCCIO BYPASS (PCH 1.05V USB2 PWR)

PP1V05_S0

6 8

11 15 16 17 38 42 51 55

58 59 62 64

BYPASS=U0500.AG16:6.35mm

PCH VCCCLK BYPASS (PCH 1.05V CLK PWR)

PP1V05_S0

6 8

11 15 16 17 38 42 51 55

58 59 62 64

1

C1257

1UF

10%

6.3V

2

CERM 402

1

C1262

10%

402

10UF

20%

6.3V

2

CERM-X5R 0402-1

BYPASS=U0500.J17:6.35mm

1

C1266

1UF

10%

6.3V 2

CERM

402

BYPASS=U0500.R21:6.35mm

C1264

1UF

6.3V CERM

C1267

1UF

6.3V CERM

1

10%

2

402

D

1

10%

2

402

C

PCH VCCACLKPLL FILTER/BYPASS (PCH 1.05V ACLK PLL PWR)

PP1V05_S0_PCH_VCCACLKPLL

MIN_LINE_WIDTH=0.2 MM MIN_NECK_WIDTH=0.075 MM VOLTAGE=1.05V

1

C1272

20%

4V

1UF

10% 10V

2

X5R 402

31mA Max

8

12

PCH VCCSUSHDA BYPASS (PCH 3.3V/1.5V HDA PWR)

PP1V5_S0SW_AUDIO_HDA

8

17 58

B

A

LPT-LP current estimates from Lynx Point-LP PCH EDS, doc #503118, v1.0 as well as from clarification email, from Srini, dated 9/10/2012 2:11pm.

C1210

BYPASS=U0500.AH14:6.35mm

6.3V CERM

1UF

CRITICAL

L1275

R1275

0

21

PP1V05_S0_PCH_VCC_ICC_R

MIN_LINE_WIDTH=0.2 MM

5%

1

10%

2

402

PP1V05_S0SW_PCH_HSIO

8

11 58 62

R1280

BYPASS=U0500.B18:12.7mm

MIN_NECK_WIDTH=0.2 MM

1/16W

VOLTAGE=1.05V

MF-LF

402

0

21

5% 1/16W MF-LF

CRITICAL

402

NO STUFF

L1280

2.2UH-240MA-0.221OHM

0603

NO STUFF

C1280

CERM-X5R

BYPASS=U0500.AA21:12.7mm

CRITICAL

L1290

2.2UH-240MA-0.221OHM

0603

C1290

CERM-X5R

BYPASS=U0500.B11:12.7mm

CRITICAL

L1295

2.2UH-240MA-0.221OHM

0603

C1295

CERM-X5R

BYPASS=U0500.B18:12.7mm

21

NO STUFF

1

47UF

0805-1

47UF

0805-1

47UF

0805-1

C1281

20%

4V

2

BYPASS=U0500.AA21:12.7mm

BYPASS=U0500.AA21:6.35mm

21

NO STUFF

1

C1291

20%

4V

2

BYPASS=U0500.B11:12.7mm

BYPASS=U0500.B11:6.35mm

21

NO STUFF

1

C1296

20%

4V

2

BYPASS=U0500.B18:6.35mm

47UF

CERM-X5R

0805-1

47UF

CERM-X5R

0805-1

47UF

CERM-X5R

0805-1

1

20%

4V

2

1

20%

4V

2

1

20%

4V

2

2.2UH-240MA-0.221OHM

BYPASS=U0500.J18:12.7mm

PCH OPI VCCAPLL FILTER/BYPASS (PCH 1.05V OPI PLL PWR)

PP1V05_S0_PCH_VCCAPLL_OPI

MIN_LINE_WIDTH=0.2 MM MIN_NECK_WIDTH=0.075 MM VOLTAGE=1.05V

1

C1282

1UF

10% 10V

2

X5R 402

PCH VCCSATA3PLL FILTER/BYPASS (PCH 1.05V SATA3 PLL PWR)

PP1V05_S0SW_PCH_VCCSATA3PLL

MIN_LINE_WIDTH=0.2 MM MIN_NECK_WIDTH=0.075 MM VOLTAGE=1.05V

1

C1292

1UF

10% 10V

2

X5R 402

PCH VCCUSB3PLL FILTER/BYPASS (PCH 1.05V USB3 PLL PWR)

PP1V05_S0SW_PCH_VCCUSB3PLL

MIN_LINE_WIDTH=0.2 MM MIN_NECK_WIDTH=0.075 MM VOLTAGE=1.05V

1

C1297

1UF

10% 10V

2

X5R 402

0603

C1275

21

47UF

20%

4V

CERM-X5R

0805-1

BYPASS=U0500.J18:12.7mm

1

C1276

47UF

CERM-X5R

0805-1

20%

2

BYPASS=U0500.J18:6.35mm

57mA Max

42mA Max83mA Max

41mA Max

6 3

PCH VCCCLK FILTER/BYPASS (PCH 1.05V VCCCLK PWR)

PP1V05_S0_PCH_VCC_ICC

MIN_LINE_WIDTH=0.2 MM MIN_NECK_WIDTH=0.075 MM VOLTAGE=1.05V

1

C1277

4V

2

8

12

8

14

1UF

10% 10V X5R 402

??mA Max

8

SYNC_MASTER=J41_MLB

PAGE TITLE

PCH Decoupling

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=02/07/2013

DRAWING NUMBER

<SCH_NUM>

REVISION

BRANCH

PAGE

12 OF 121

SHEET

11 OF 76

124578

SIZE

B

A

D

8 7 6 5 4 3

PPVRTC_G3H

8

13 17 62 64

CRITICAL

BROADWELL-ULT

(IPD)

(IPU)

OMIT_TABLE

U0500

2C+GT2

BGA

SYM 5 OF 19

RTC

AUDIO

JTAG

SATA_RN0/PERN6_L3 SATA_RP0/PERP6_L3

SATA_TN0/PETN6_L3 SATA_TP0/PETP6_L3

SATA_RN1/PERN6_L2 SATA_RP1/PERP6_L2

SATA_TN1/PETN6_L2 SATA_TP1/PETP6_L2

SATA_RN2/PERN6_L1 SATA_RP2/PERP6_L1

SATA_TN2/PETN6_L1 SATA_TP2/PETP6_L1

SATA_RN3/PERN6_L0

SATA

SATA_RP3/PERP6_L0

SATA_TN3/PETN6_L0 SATA_TP3/PETP6_L0

SATA0GP/GPIO34 SATA1GP/GPIO35 SATA2GP/GPIO36 SATA3GP/GPIO37

(IPU)

SATA_IREF

SATA_RCOMP

RSVD

J5 H5

B15 A15

J8 H8

A17 B17

J6 H6

B14 C15

F5 E5

C17 D17

V1 U1 V6 AC1

A12

L11

K10

C12

U3

PCIE_SSD_D2R_N<3> PCIE_SSD_D2R_P<3>

PCIE_SSD_R2D_C_N<3> PCIE_SSD_R2D_C_P<3>

PCIE_SSD_D2R_N<2> PCIE_SSD_D2R_P<2>

PCIE_SSD_R2D_C_N<2> PCIE_SSD_R2D_C_P<2>

PCIE_SSD_D2R_N<1> PCIE_SSD_D2R_P<1>

PCIE_SSD_R2D_C_N<1> PCIE_SSD_R2D_C_P<1>

PCIE_SSD_D2R_N<0> PCIE_SSD_D2R_P<0>

PCIE_SSD_R2D_C_N<0> PCIE_SSD_R2D_C_P<0>

XDP_FW_PME_L XDP_PCH_GPIO35 XDP_PCH_UART_SSD_L_BT_H XDP_SSD_PCIE0_SEL_L

NC NC

PCH_SATA_RCOMP

PCH_SATALED_L

PCIe Port assignments:

30 64 67

IN

30 64 67

IN

OUT OUT

IN IN

OUT OUT

IN IN

OUT OUT

IN IN

OUT OUT

IN IN IN

30 67

30 64 67

30 67

30 64 67

30 67

30 64 67

30 67

15 16

12 16

16

SSD Lane 3

SSD Lane 2

SSD Lane 1

SSD Lane 0

PP1V05_S0SW_PCH_VCCSATA3PLL

1

R1370

3.01K

1% 1/20W MF 201

2

PLACE_NEAR=U0500.C12:2.54mm

12

SATA Port assignments:

Primary HDD/SSD

Reserved: ODD

Unused

Secondary HDD/SSD

8

11

1

R1300

1/20W

20K

1

R1303

20K

5%

5% 1/20W

MF

201

MF 201

2

R1302

D

1

C1300

1UF

10% 10V X5R 402

1

C1303

1UF

10% 10V

2

X5R 402

C

330K

1/20W

5%

MF

201

2

61 65 69

OUT

61 65 69

OUT

61 65 69

OUT

61 65 69

OUT

1

R1301

1M

5% 1/20W MF 201

2

PCH_INTRUDER_L

PCH_INTVRMEN

PCH_SRTCRST_L

RTC_RESET_L

HDA_BIT_CLK

HDA_SYNC

HDA_RST_L

HDA_SDOUT

R1310

R1311

R1312

R1313

PCH_CLK32K_RTCX1

17

IN

NC_RTC_CLK32K_RTCX2

17

OUT

33

21

HDA_BIT_CLK_R

69

1/20W

5%

PLACE_NEAR=U0500.AW8:1.27mm

21

HDA_SYNC_R

69

1/20W

PLACE_NEAR=U0500.AV11:1.27mm

21

HDA_RST_R_L

69

1/20W

5% MF33201

PLACE_NEAR=U0500.AU8:1.27mm

HDA_SDIN0

61 65 69

IN

NC_HDA_SDIN1

64

21

HDA_SDOUT_R

17 69

1/20W

5% MF

PLACE_NEAR=U0500.AU11:1.27mm

TP_PCH_I2S1_TXD TP_PCH_I2S1_SFRM

201

MF

201

MF5%

201

TP_PCH_I2S1_SCLK

XDP_CPUPCH_TRST_L

6

16 64 67

IN

XDP_PCH_TCK

16 64 69

IN IN

XDP_PCH_TDI

16 64 69

IN

XDP_PCH_TDO

16 64 69

OUT

XDP_PCH_TMS

16 64 69

IN

PCH_JTAGX

16

BI

AW5

RTCX1

AY5

RTCX2

AU6

INTRUDER*

AV7

INTVRMEN

AV6

SRTCRST*

AU7

RTCRST*

AW8

HDA_BCLK/I2S0_SCLK

AV11

HDA_SYNC/I2S0_SFRM

AU8

AY10 AU12

AU11

AW10 AV10

AY8

AU62

AE62

AD61

AE61

AD62

AL11

NC

AC4

NC

AE63

AV2

NC

(IPD-PLTRST#)

HDA_RST*/I2S_MCLK

HDA_SDI0/I2S0_RXD HDA_SDI1/I2S1_RXD

HDA_SDO/I2S0_TXD

(IPD-PLTRST#)

HDA_DOCK_EN*/I2S1_TXD HDA_DOCK_RST*/I2S1_SFRM

I2S1_SCLK

PCH_TRST*

PCH_TCK

PCH_TDI

PCH_TDO

PCH_TMS

RSVD

JTAGX

RSVD SATALED*

12

D

C

CRITICAL

OMIT_TABLE

U0500

BROADWELL-ULT

2C+GT2

BGA

TP_PCIE_CLK100M_ENETSDN TP_PCIE_CLK100M_ENETSDP

ENETSD_CLKREQ_L

12

PCIE_CLK100M_CAMERA_N

32 69

OUT

PCIE_CLK100M_CAMERA_P

32 69

OUT

CAMERA_CLKREQ_L

12 31

IN

PCIE_CLK100M_AP_N

29 64 69

B

A

PP3V3_S0

R1377 R1376 R1375

R1340 R1341 R1342 R1343 R1344 R1345

100K 100K 100K

100K 100K 100K 100K 100K 100K

64 65 74 8

11 13 15 17 18 26 30 36 38 39

40 41 42 43 44 45 56 59 61 62

21

1/20W

5% MF

21

5% MF

21

5%

21

5%

21

5% MF

21

5%

21

5%

21

5%

1/20W

1/20W 1/20W

1/20W

1/20W 1/20W

MF5%

MF

MF MF

XDP_PCH_UART_SSD_L_BT_H

201

XDP_PCH_GPIO35

201

PCH_SATALED_L

201

ENETSD_CLKREQ_L

201

CAMERA_CLKREQ_L

201

AP_CLKREQ_L

201

FW_CLKREQ_L

201

TBT_CLKREQ_L

201

SSD_CLKREQ_L

201

12 16

12

12 31

12 29

12

12 25

12 30

OUT

29 64 69

OUT

12 29

IN

64

12

25 69

OUT

25 69

OUT

12 25

IN

30 64 67

OUT

30 64 67

OUT

12 30

IN

PCIE_CLK100M_AP_P

AP_CLKREQ_L

NC_PCIE_CLK100M_FWN NC_PCIE_CLK100M_FWP

FW_CLKREQ_L

PCIE_CLK100M_TBT_N PCIE_CLK100M_TBT_P

TBT_CLKREQ_L

PCIE_CLK100M_SSD_N PCIE_CLK100M_SSD_P

SSD_CLKREQ_L

C43

CLKOUT_PCIE_N0

C42

CLKOUT_PCIE_P0

U2

PCIECLKRQ0*/GPIO18

B41

CLKOUT_PCIE_N1

A41

CLKOUT_PCIE_P1

Y5

PCIECLKRQ1*/GPIO19

C41

CLKOUT_PCIE_N2

B42

CLKOUT_PCIE_P2

AD1

PCIECLKRQ2*/GPIO20

B38

CLKOUT_PCIE_N3

C37

CLKOUT_PCIE_P3

N1

PCIECLKRQ3*/GPIO21

A39

CLKOUT_PCIE_N4

B39

CLKOUT_PCIE_P4

U5

PCIECLKRQ4*/GPIO22

B37

CLKOUT_PCIE_N5

A37

CLKOUT_PCIE_P5

T2

PCIECLKRQ5*/GPIO23

XTAL24_IN

XTAL24_OUT

CLOCK SIGNALS

DIFFCLK_BIASREF

CLKOUT_LPC_0

CLKOUT_LPC_1

(IPD-PWROK)

CLKOUT_ITPXDP_N CLKOUT_ITPXDP_P

6 3

SYM 6 OF 19

RSVD RSVD

TESTLOW TESTLOW TESTLOW TESTLOW

A25 B25

K21 M21

C26

C35 C34 AK8 AL8

AN15

AP15

B35 A35

PCH_CLK24M_XTALIN PCH_CLK24M_XTALOUT

NC NC

PCH_DIFFCLK_BIASREF

PCH_TESTLOW_C35 PCH_TESTLOW_C34 PCH_TESTLOW_AK8 PCH_TESTLOW_AL8

LPC_CLK24M_SMC_R

17

IN

17

OUT

PP1V05_S0_PCH_VCCACLKPLL

1

R1380

3.01K

1% 1/20W MF 201

2

PLACE_NEAR=U0500.C26:2.54mm

10K

R1390

10K

R1391

10K

R1392

10K

R1393

17 69

OUT

8

11

B

21

5%

21

5%

21

5%

21

5%

1/20W

1/20W 1/20W

MF

201

MF

201

MF MF

201

TP_LPC_CLK24M_LPCPLUS_R

TP_ITPXDP_CLK100MN TP_ITPXDP_CLK100MP

SIZE

A

D

PAGE TITLE

PCH Audio/JTAG/SATA/CLK

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=12/17/2012SYNC_MASTER=WILL_J43

DRAWING NUMBER

<SCH_NUM>

REVISION

BRANCH

PAGE

13 OF 121

SHEET

12 OF 76

124578

8 7 6 5 4 3

12

CRITICAL

OMIT_TABLE

U0500

BROADWELL-ULT

2C+GT2

BGA

D

61 62 64 65 74 8

11 12 13 15 17 18 26 30 36

38 39 40 41 42 43 44 45 56 59

13 18 37

OUT

SLP_S0# Isolation

PP3V3_S0

PM_SLP_S0_L

CRITICAL

74LVC1G08

SOT891

4

6

U1420

08

1

C1420

0.1UF

10% 10V

2

X5R-CERM 0201

2

1

NC

53

R1400 kept for debug purposes.

39

IN

NO STUFF

R1400

1/20W

39

OUT

1

0

5%

MF

0201

2

17 37 64

16 17 37

13 17

15 16 18

59 64

13 16 37

37 38

13 27 37

PCH_SUSACK_L

PM_SYSRST_L

IN

PM_PCH_SYS_PWROK

IN

PM_PCH_PWROK

IN

PM_PCH_PWROK

IN

PLT_RESET_L

OUT

PM_RSMRST_L

IN

PCH_SUSWARN_L

PM_PWRBTN_L

IN

SMC_ADAPTER_EN

IN

PM_BATLOW_L

IN

PCH_PM_SLP_S0_L

TP_PCH_SLP_WLAN_L

AK2

SUSACK*

AC3

SYS_RESET*

AG2

SYS_PWROK

AY7

PCH_PWROK

AB5

APWROK

AG7

PLTRST*

AW6

RSMRST*

AV4

SUSWARN*/SUSPWRDNACK/GPIO30

AL7

PWRBTN*

AJ8

ACPRESENT/GPIO31

AN4

BATLOW*/GPIO72

AF3 AJ7

SLP_S0*

AM5

SLP_WLAN*/GPIO29

SYM 8 OF 19

SYSTEM POWER MANAGEMENT

(IPU)

(IPD-DeepSx)

(IPU)

(IPD-DeepSx)

DSWVRMEN

DPWROK

WAKE*

CLKRUN*/GPIO32

SUS_STAT*/GPIO61

SUSCLK/GPIO62

SLP_S5*/GPIO63

SLP_S4*

SLP_S3*

SLP_A*

SLP_SUS*

SLP_LAN*

AW7

AV5

AJ5

V5

AG4

AE6

AP5

AJ6

AT4

AL5

AP4

PCH_DSWVRMEN

PM_DSW_PWRGD

PCIE_WAKE_L

PM_CLKRUN_L

LPC_PWRDWN_L

PM_CLK32K_SUSCLK_R

PM_SLP_S5_L

PM_SLP_S4_L

PM_SLP_S3_L

TP_PM_SLP_A_L

PM_SLP_SUS_L

TP_PCH_SLP_LAN_L

13 29 31 64

IN

13 37 64

BI

37 64

OUT

38 69

OUT

13 37 59

OUT

13 18 29 36 37 59

OUT

13 17 18 37 59

OUT

13 42 59

OUT

PPVRTC_G3H

1

R1450

330K

5% 1/20W MF 201

2

IN

1

R1451

100K

5% 1/20W MF 201

2

8

12 17 62 64

D

37

NC

SLP_S0# can be driven high outside of S0 U1420 ensures signal will only be high in S0.

C

AD4

B8

A9

C6

U6 P4 N4 N2

U7 L1 L3 R5 L4

EDP_BKLCTL

EDP_BKLEN

EDP_VDDEN

PIRQA*/GPIO77 PIRQB*/GPIO78 PIRQC*/GPIO79 PIRQD*/GPIO80

PME*

GPIO55 GPIO52 GPIO54 GPIO51 GPIO53

56

OUT

13 56

OUT

13 60

OUT

13 26

IN

13 37

IN

13 64

IN

13 30

OUT

64

13 64

OUT

13 64

OUT

13 64

OUT

13 59 61 65

OUT

13 64

OUT

EDP_BKLT_PWM

EDP_BKLT_EN

EDP_PANEL_PWR

TBT_PWR_REQ_L SMC_RUNTIME_SCI_L HDMITBTMUX_FLAG SSD_BOOT

NC_PCI_PME_L

ODD_PWR_EN_L HDMITBTMUX_LATCH ENET_LOW_PWR AUD_PWR_EN AP_PCIE_DEV_WAKE

OMIT_TABLE

BROADWELL-ULT

SYM 9 OF 19

(IPU)

CRITICAL

U0500

2C+GT2

BGA

eDP

SIDEBAND

PCI

DDPB_CTRLCLK

DDPB_CTRLDATA

(IPD-PLTRST#)

DDPC_CTRLCLK

DDPC_CTRLDATA

(IPD-PLTRST#)

DISPLAY

DDPB_AUXN DDPC_AUXN

DDPB_AUXP DDPC_AUXP

DDPB_HPD

DDPC_HPD

EDP_HPD

B9 C9

D9 D11

C5 B6

B5 A6

C8

A8

D6

DP_TBTSNK0_DDC_CLK DP_TBTSNK0_DDC_DATA

DP_TBTSNK1_DDC_CLK DP_TBTSNK1_DDC_DATA

DP_TBTSNK0_AUXCH_C_N DP_TBTSNK1_AUXCH_C_N

DP_TBTSNK0_AUXCH_C_P DP_TBTSNK1_AUXCH_C_P

DP_TBTSNK0_HPD

DP_TBTSNK1_HPD

DP_INT_HPD

C

18 28

OUT

18 28

BI

18

OUT

18

BI

25 67

BI

18 25 67

BI

25 67

BI

18 25 67

BI

25

IN

18 25

IN

60

IN

SIZE

B

A

D

B

PP3V3_S5 PP3V3_S0

R1405 R1410 R1452 R1455 R1460

R1461 R1462 R1463 R1464

R1430

A

R1431 R1440

R1441 R1442 R1443

R1445 R1446 R1447 R1448 R1449

1K

10K

100K 100K 100K 100K 100K

100K 100K

100K 100K 100K 100K

100K 100K 100K 100K 100K

8

11 15 16 17 18 28 29 34 42 57

58 59 60 62 64 74 62 64 65 74 8

11 12 13 15 17 18 26 30 36 38

39 40 41 42 43 44 45 56 59 61

21

5%

1/20W

1/20W 1/20W

1/20W

1/20W 1/20W

1/20W

MF

MF MF

MF

MF MF

MF

21

5%

21

5%

21

5%

21

5%

21

5%

21

5%

21

5%

21

5%

21

5%

21

5%

21

5%

21

5%

21

5%

21

5%

21

5%

21

5%

21

5%

21

5%

21

5%

PM_PWRBTN_L

201

PM_BATLOW_L

201

PCIE_WAKE_L

201

PM_CLKRUN_L

201

PM_SLP_S5_L

201

PM_SLP_S4_L

201

PM_SLP_S3_L

201

PM_SLP_S0_L

201

PM_SLP_SUS_L

201

EDP_BKLT_EN

201

EDP_PANEL_PWR

201

TBT_PWR_REQ_L

201

SMC_RUNTIME_SCI_L

201

HDMITBTMUX_FLAG

201

SSD_BOOT

201

ODD_PWR_EN_L

201

HDMITBTMUX_LATCH

201

ENET_LOW_PWR

201

AUD_PWR_EN

201

AP_PCIE_DEV_WAKE

201

13 16 37

13 27 37

13 29 31 64

13 37 64

13 37 59

13 18 29 36 37 59

13 17 18 37 59

13 18 37

13 42 59

13 56

13 60

13 26

13 37

13 64

13 30

13 64

13 59 61 65

13 64

6 3

SYNC_MASTER=J43_MLB

PAGE TITLE

PCH PM/PCI/GFX

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=02/20/2013

DRAWING NUMBER

<SCH_NUM>

REVISION

BRANCH

PAGE

14 OF 121

SHEET

13 OF 76

124578

8 7 6 5 4 3

12

PCIe Port Assignments:

PCIE_TBT_D2R_N<0>

25 69

IN

PCIE_TBT_D2R_P<0>

25 69

Thunderbolt lane 0

D

Thunderbolt lane 1

Thunderbolt lane 2

Thunderbolt lane 3

AirPort

Reserved: FireWire

C

SD Card Reader (& Ethernet if combo)

Camera

PP1V05_S0SW_PCH_VCCUSB3PLL

8

11

PLACE_NEAR=U0500.A27:2.54mm

LPC_AD<0>

37 64 69

BI

LPC_AD<1>

37 64 69

BI

LPC_AD<2>

37 64 69

BI

B

LPC_AD<3>

37 64 69

BI

LPC_FRAME_L

37 64 69

OUT

R1540 R1541 R1542 R1543

R1544

33 33 33 33

33

21

21 21

21

IN

25 69

OUT

25 69

OUT

25 69

IN

25 69

IN

25 69

OUT

25 69

OUT

25 69

IN

25 69

IN

25 69

OUT

25 69

OUT

25 69

IN

25 69

IN

25 69

OUT

25 69

OUT

29 64 69

IN

29 64 69

IN

29 69

OUT

29 69

OUT

34 65 68

IN

34 65 68

IN

34 65 68

OUT

34 65 68

OUT

32 69

IN

32 69

IN

32 69

OUT

32 69

OUT

1

R1500

3.01K

1%

1/20W

MF

201

2

1/20W

5% 5%

1/20W

5% MF

1/20W

5%

1/20W

5%

PCIE_TBT_R2D_C_N<0> PCIE_TBT_R2D_C_P<0>

PCIE_TBT_D2R_N<1> PCIE_TBT_D2R_P<1>

PCIE_TBT_R2D_C_N<1> PCIE_TBT_R2D_C_P<1>

PCIE_TBT_D2R_N<2> PCIE_TBT_D2R_P<2>

PCIE_TBT_R2D_C_N<2> PCIE_TBT_R2D_C_P<2>

PCIE_TBT_D2R_N<3> PCIE_TBT_D2R_P<3>

PCIE_TBT_R2D_C_N<3> PCIE_TBT_R2D_C_P<3>

PCIE_AP_D2R_N PCIE_AP_D2R_P

PCIE_AP_R2D_C_N PCIE_AP_R2D_C_P

NC_PCIE_FW_D2RN

64

NC_PCIE_FW_D2RP

64

NC_PCIE_FW_R2D_CN

64

NC_PCIE_FW_R2D_CP

64

USB3_SD_D2R_N USB3_SD_D2R_P

USB3_SD_R2D_C_N USB3_SD_R2D_C_P

PCIE_CAMERA_D2R_N PCIE_CAMERA_D2R_P

PCIE_CAMERA_R2D_C_N PCIE_CAMERA_R2D_C_P

PCH_PCIE_RCOMP

MF

201

MF

201

MF

201

MF

46 69

OUT

46 69

OUT

LPC_AD_R<0> LPC_AD_R<1> LPC_AD_R<2> LPC_AD_R<3>

LPC_FRAME_R_L

SPI_CLK_R

SPI_CS0_R_L

TP_SPI_CS1_L

TP_SPI_CS2_L

SPI_MOSI_R

46 69

BI

SPI_MISO

46 69

BI

SPI_IO<2>

14 46 69

BI

SPI_IO<3>

14 46 69

BI

F10

PERN5_L0

E10

PERP5_L0

C23

PETN5_L0

C22

PETP5_L0

F8

PERN5_L1

E8

PERP5_L1

B23

PETN5_L1

A23

PETP5_L1

H10

PERN5_L2

G10

PERP5_L2

B21

PETN5_L2

C21

PETP5_L2

E6

PERN5_L3

F6

PERP5_L3

B22

PETN5_L3

A21

PETP5_L3

G11

PERN3

F11

PERP3

C29

PETN3

B30

PETP3

F13

PERN4

G13

PERP4

B29

PETN4

A29

PETP4

G17

PERN1/USB3RN3

F17

PERP1/USB3RP3

C30

PETN1/USB3TN3

C31

PETP1/USB3TP3

F15

PERN2/USB3RN4

G15

PERP2/USB3RP4

B31

PETN2/USB3TN4

A31

PETP2/USB3TP4

E15

NC NC

RSVD

E13

RSVD

A27

PCIE_RCOMP

B27 AV3

PCIE_IREF

(IPU)

AU14

LAD0

AW12

LAD1

AY12

LAD2

AW11

LAD3

AV12

LFRAME*

AA3

SPI_CLK

(IPU)

Y7

SPI_CS0*

(IPU)

Y4

SPI_CS1*

(IPU)

AC2

SPI_CS2*

(IPU)

AA2

SPI_MOSI

(IPU/IPD)

AA4

SPI_MISO

(IPU)

Y6

SPI_IO2

(IPU)

AF1

SPI_IO3

(IPU)

CRITICAL

OMIT_TABLE

U0500

BROADWELL-ULT

2C+GT2

BGA

SYM 11 OF 19

USB

PCI-E

OC0*/GPIO40 OC1*/GPIO41 OC2*/GPIO42 OC3*/GPIO43

CRITICAL

OMIT_TABLE

U0500

BROADWELL-ULT

2C+GT2

BGA

SYM 7 OF 19

SMBALERT*/GPIO11

LPC

SML0ALERT*/GPIO60

SMBUS

SML1ALERT*/PCHHOT*/GPIO73

SML1CLK_GPIO75

SML1DATA/GPIO74

SPI

(IPU/IPD)

C-LINK

USB2N0 USB2P0

USB2N1 USB2P1

USB2N2 USB2P2

USB2N3 USB2P3

USB2N4 USB2P4

USB2N5 USB2P5

USB2N6 USB2P6

USB2N7 USB2P7

(IPD)

USB3RN1 USB3RP1

USB3TN1 USB3TP1

USB3RN2 USB3RP2

USB3TN2 USB3TP2

USBRBIAS*

USBRBIAS

RSVD RSVD

SMBCLK

SMBDATA

SML0CLK

SML0DATA

CL_CLK

CL_DATA

CL_RST*

AN8 AM8

AR7 AT7

AR8 AP8

AR10 AT10

AM15 AL15

AM13 AN13

AP11 AN11

AR13 AP13

G20 H20

C33 B34

E18 F18

B33 A33

AJ10 AJ11

AN10 AM10

AL3 AT1 AH2

AN2

AP2 AH1

AL2

AN1 AK1

AU4

AU3 AH3

AF2

AD2

AF4

USB_EXTA_N USB_EXTA_P

USB_EXTB_N USB_EXTB_P

USB_BT_N USB_BT_P

NC_USB_IRN NC_USB_IRP

USB_TPAD_N USB_TPAD_P

TP_USB_5N TP_USB_5P

NC_USB_CAMERAN NC_USB_CAMERAP

NC_USB_SDN NC_USB_SDP

USB3_EXTA_D2R_N USB3_EXTA_D2R_P

USB3_EXTA_R2D_C_N USB3_EXTA_R2D_C_P

USB3_EXTB_D2R_N USB3_EXTB_D2R_P

USB3_EXTB_R2D_C_N USB3_EXTB_R2D_C_P

PCH_USB_RBIAS

68

NC NC

XDP_USB_EXTA_OC_L XDP_USB_EXTB_OC_L XDP_USB_EXTC_OC_L XDP_USB_EXTD_OC_L

PCH_SMBALERT_L

SMBUS_PCH_CLK SMBUS_PCH_DATA

WOL_EN

SML_PCH_0_CLK SML_PCH_0_DATA

PCH_SML1ALERT_L

SMBUS_SMC_1_S0_SCL SMBUS_SMC_1_S0_SDA

NC_CLINK_CLK

NC_CLINK_DATA

NC_CLINK_RESET_L

35 68

BI

35 68

BI

61 65 68

BI

61 65 68

BI

29 68

BI

29 68

BI

64

BI

64

BI

36 64 68

BI

36 64 68

BI

64

35 68

IN

35 68

IN

35 68

OUT

35 68

OUT

61 65 68

IN

61 65 68

IN

61 65 68

OUT

61 65 68

OUT

14 16 35

IN

14 16 61 65

IN

14 16

IN

14 16

IN

14

16 19 40 56 69

OUT

16 19 40 56 69

BI

14 64

OUT

40 69

OUT

40 69

BI

18 39

OUT

32 37 40 43 44 64 69 73

OUT

32 37 40 43 44 64 69 73

BI

64

USB Port Assignments:

Ext A (LS/FS/HS)

Ext B (LS/FS/HS)

BT

IR

Trackpad

Unused

Reserved: Camera

Reserved: SD (HS)

USB3 Port Assignments:

Ext A (SS)

Ext B (SS)

PLACE_NEAR=U0500.AJ10:2.54mm

1

R1570

22.6

1% 1/20W MF 201

2

SML1ALERT# pull-up not provided on this page, may be wire-ORed into other signals. Otherwise, 100k pull-up to 3.3V SUS required.

D

C

B

PP3V3_SUS

A

PP3V3_SUS

R1580 R1581 R1582 R1583

R1548 R1549

R1590 R1591

100K 100K 100K 100K

1K 1K

100K 100K

8

11 14 18 46 57 58 59 62 64

8

11 14 18 46 57 58 59 62 64

21

1/20W

21

1/20W

5%

21

1/20W

5%

21

1/20W

5% MF

21

1/20W

21

1/20W

21

1/20W

5%

21

5% MF

1/20W

MF5%

MF MF

MF5% MF5%

MF

XDP_USB_EXTA_OC_L

201

XDP_USB_EXTB_OC_L

201

XDP_USB_EXTC_OC_L

201

XDP_USB_EXTD_OC_L

201

SPI_IO<2>

201

SPI_IO<3>

201

PCH_SMBALERT_L

201

WOL_EN

201

14 16 35

14 16 61 65

14 16

14 46 69

14

14 64

6 3

SYNC_MASTER=WILL_J43 SYNC_DATE=09/13/2012

PAGE TITLE

PCH PCIe/USB/LPC/SPI/SMBus

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

DRAWING NUMBER

<SCH_NUM>

REVISION

BRANCH

PAGE

15 OF 121

SHEET

14 OF 76

124578

SIZE

A

D

8 7 6 5 4 3

BOM GROUP

RAMCFG_SLOT

PP3V3_S0

RAMCFG3:H

R1631

100K

1/20W

RAMCFG2:H

1

R1636

100K

5%

5% 1/20W

MF

201

2

RAMCFG1:H

D

GPIO12:

CR: TBT_GO2SX_BIDIR, requires 100k pull-up to SUS RR/FR: DPHDMIMUX_SEL_TBT, requires 100k pull-up to TBTLC

C

B

A

TPAD_SPI_INT_L

15 36

IN

11 12 13 15 17 18 26 30 36

PP3V3_S5 PP3V3_S3 PP3V3_S0SW_SD PP3V3_S3 PP3V3_S3RS0_CAMERA PP3V3_S0 PP3V3_S0

TBTLC for CR, S0 for RR

R1610 R1614

R1615

R1616 R1617 R1618 R1619 R1620

R1622 R1623 R1624 R1625 R1626 R1627 R1628 R1629 R1630

R1632 R1633 R1634

R1637 R1638 R1640

R1652

R1691 R1693

R1694 R1695

61 62 64 65 74

PP3V3_S0

8 38 39 40 41 42 43 44 45 56 59

100K

100K 100K

100K 100K 100K 100K 100K

100K 100K 100K 100K 100K 100K 100K 100K 100K

100K 100K 100K

10K

100K

100K 100K 100K

SD_ON_MLB

SSD_LPSR:S0

62 64 65 74 8

11 12 13 15 17 18 26 30 36 38

39 40 41 42 43 44 45 56 59 61

1

100K

1/20W

1

5%

MF

201

2

R1635

TPAD_SPI_INT_GPIO28_L

1

R1681

0

5% 1/20W MF 0201

2

1

R1682

0

5% 1/20W MF 0201

2

TPAD_SPI_INT_GPIO46_L

8

11 13 16 17 18 28 29 34 42 57

58 59 60 62 64 74 15 18 19 33 36 40 41 58 62 64

34 37 39 65

15 18 19 33 36 40 41 58 62 64

31 41 45 56 59 61 62 64 65 74

8

11 12 13 15 17 18 26 30 36 38

62 64 65 74 8

11 12 13 15 17 18 26 30 36 38

39 40 41 42 43 44 45 56 59 61

21

1/20W

5% MF

21

5%

1/20W

21

1/20W

21

1/20W

5%

21

1/20W

21

5%

1/20W

21

5% MF

1/20W

21

1/20W

21

1/20W

5%

21

1/20W

5%

21

5%

1/20W

21

1/20W

5% MF

21

1/20W

5%

21

1/20W

5%

21

5% MF

1/20W

21

5%

1/20W

21

1/20W

5%

21

5%

1/20W

21

1/20W

5%

21

5%

NOSTUFF

1/20W

21

5%

1/20W

21

5%

1/20W

21

5%

1/20W

21

1/20W

5%

21

5%

1/20W

21

1/20W

5%

21

1/20W

5%

21

1/20W

5%

RAMCFG0:H

R1611

100K

5% 1/20W MF 201

XDP_MLB_RAMCFG0 XDP_MLB_RAMCFG1 XDP_MLB_RAMCFG2 XDP_MLB_RAMCFG3

13 15 16 18

39 40 41 42 43 44

MF

MF5%

MF

MF5%

MF

MF5%

MF

MF MF

MF

MF MF

MF

MF MF

MF

BOM OPTIONS

RAMCFG3:H,RAMCFG2:H,RAMCFG1:H,RAMCFG0:H

15 16 18

PLT_RESET_L

IN

1

R1621

100K

5%

1/20W

MF

201

2

18 25

OUT

15

1

R1639

100K

5%

1/20W

MF

201

30

18 31

2

OUT

R1641

XDP_PCH_GPIO76

201

XDP_LPCPLUS_GPIO

201

XDP_PCH_GPIO17

201

SD_RESET_L

201

SMC_WAKE_SCI_L

201

TPAD_SPI_INT_L

201

TPAD_USB_IF_EN

201

SSD_PWR_EN

201

HDD_PWR_EN

201

XDP_SDCONN_STATE_CHANGE_L

201

SD_PWR_EN

201

TBT_PWR_EN

201

XDP_JTAG_ISP_TCK

201

XDP_JTAG_ISP_TDI

201

JTAG_TBT_TMS_PCH

201

PCH_HSIO_PWR_EN

201

TPAD_SPI_IF_EN

201

SPIROM_USE_MLB

201

CAMERA_PWR_EN_PCH

201

TPAD_SPI_INT_GPIO46_L

201

SSD_SR_EN_L

201

AP_S0IX_WAKE_SEL

201

XDP_FW_PME_L

201

LPC_SERIRQ

201

BT_PWRRST_L

201

ENET_MEDIA_SENSE

201

LCD_IRQ_L

201

LCD_PSR_EN

201

R1680

100K

1/20W

1

5%

MF

201

2

21

5% MF1K201

1/20W

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

11 16 17 38 42 51 55 58

PP1V05_S0

6 8 59 62 64

R1650

PP3V3_S3

15 18 19 33 36 40 41 58 62 64

IN

XDP_PCH_GPIO76

15 16

BI

XDP_MLB_RAMCFG0

15 16 18

BI

HDMITBTMUX_SEL_TBT

18 25

BI

TP_MEM_VDD_SEL_1V5_L

18

OUT

XDP_LPCPLUS_GPIO

15 16 64

BI

XDP_PCH_GPIO17

15 16

IN

SD_RESET_L

15 34

OUT

SMC_WAKE_SCI_L

15 37

IN

TPAD_SPI_INT_GPIO28_L

15

IN

TPAD_USB_IF_EN

15 36

OUT

SSD_PWR_EN

15 30 58 59 64

OUT

PCH_TBT_PCIE_RESET_L

HDD_PWR_EN

15 64

OUT

XDP_SDCONN_STATE_CHANGE_L

15 16 33

BI

SD_PWR_EN

15 34

OUT

TBT_PWR_EN

15 25

OUT

XDP_JTAG_ISP_TCK

15 16 18 25

OUT

XDP_JTAG_ISP_TDI

15 16 18 25

OUT

JTAG_TBT_TMS_PCH

15 18

OUT

PCH_HSIO_PWR_EN

15 58

OUT

TPAD_SPI_IF_EN

15 36

OUT

XDP_MLB_RAMCFG3

15 16 18

BI

SPIROM_USE_MLB

15 46 64

BI

CAMERA_PWR_EN_PCH

15 18

OUT

TPAD_SPI_INT_GPIO46_L

15

IN

XDP_MLB_RAMCFG1

15 16 18

BI

XDP_MLB_RAMCFG2

15 16 18

BI

SSD_SR_EN_L

15 30 64

OUT

AP_S0IX_WAKE_SEL

15 29

OUT

SSD_RESET_L

CAM_PCIE_RESET_L

PCH_TCO_TIMER_DISABLE

15 16

15 16 64

15 16

R1616 should also be stuffed if

15 34

platform does not use SD card

15 37

15 36

SSD_LPSR:S0 BOM option is on R1620

15 30 58 59 64

15 64

15 16 33

15 34

15 25

15 16 18 25

15 18

15 58

15 36

15 46 64

15 18

15

15 30 64

15 29

12 16

15 37 64

15 64

Stuffed R1632

No-Stuffed R1634

SSD_LPSR:S3

R1696

100K

1/20W

1

5%

MF

201

2

P1

AU2

AM7

AD6

Y1

T3

AD5

AN5

AD7

AN3

AG6

AP1

AL4

AT5

AK4

AB6

U4

Y3

P3

Y2

AT3

AH4

AM4

AG5

AG3

AM3

AM2

P2

C4

L2

N5

V2

CRITICAL

OMIT_TABLE

U0500

BROADWELL-ULT

2C+GT2

BGA

SYM 10 OF 19

BMBUSY*/GPIO76

GPIO8

LAN_PHY_PWR_CTRL/GPIO12

GPIO15

(IPD-RSMRST#)

GPIO16

GPIO17

GPIO24

GPIO27

(IPD-DeepSx)

GPIO28

GPIO26

GPIO56

GPIO57

GPIO58

GPIO59

GPIO44

GPIO47

GPIO48

GPIO49

GPIO50

HSIOPC/GPIO71

GPIO13

GPIO14

GPIO25

GPIO45

GPIO46

GPIO9

GPIO10

DEVSLP0/GPIO33

SDIO_POWER_EN/GPIO70

DEVSLP1/GPIO38

DEVSLP2/GPIO39

SPKR/GPIO81

(IPD-PLTRST#)

THERMTRIP*

RCIN*/GPIO82

PCH_OPI_COMP

CPU/MISC

GSPI0_CS*/GPIO83

GSPI0_CLK/GPIO84

GSPI0_MISO/GPIO85

(IPD)

GSPI0_MOSI/GPIO86

(IPD-PLTRST#)

GSPI1_CS*/GPIO87

GSPI1_CLK/GPIO88

GSPI1_MISO/GPIO89

(IPD)

GSPI_MOSI/GPIO90

UART0_RXD/GPIO91

UART0_TXD/GPIO92

UART0_RTS*/GPIO93

UART0_CTS*/GPIO94

UART1_RXD/GPIO0

LPIO

GPIO

UART1_TXD/GPIO1

UART1_RST*/GPIO2

UART1_CTS*/GPIO3

I2C0_SDA/GPIO4

I2C0_SCL/GPIO5

I2C1_SDA/GPIO6

I2C1_SCL/GPIO7

SDIO_CLK/GPIO64

SDIO_CMD/GPIO65

SDIO_D0/GPIO66

(IPD-PLTRST#)

SDIO_D1/GPIO67

SDIO_D2/GPIO68

SDIO_D3/GPIO69

SERIRQ

RSVD RSVD

D60

V4

T4

AW15

AF20 AB21

R6

L6

N6

L8

R7

L5

N7

K2

J1

K3

J2

G1

K4

G2

J3

J4

F2

F3

G4

F1

E3

F4

D3

E4

C3

E2

PM_THRMTRIP_L

TBT_CIO_PLUG_EVENT_L

LPC_SERIRQ

PCH_OPI_COMP

NC NC

AUD_SPI_CS_L

AUD_SPI_CLK

AUD_SPI_MISO

AUD_SPI_MOSI

TPAD_SPI_CS_L

TPAD_SPI_CLK

TPAD_SPI_MISO

TPAD_SPI_MOSI

PCH_BT_UART_D2R

PCH_BT_UART_R2D

PCH_BT_UART_RTS_L

PCH_BT_UART_CTS_L

PCH_UART1_RXD

PCH_UART1_TXD

JTAG_ISP_TDO

PCH_UART1_CTS_L

AP_S0IX_WAKE_L

AP_RESET_L

PCH_I2C1_SDA

PCH_I2C1_SCL

TBT_POC_RESET_L

BT_PWRRST_L

PCH_STRP_TOPBLK_SWP_L

ENET_MEDIA_SENSE

LCD_IRQ_L

LCD_PSR_EN

1/20W

201

6 3

12

1

1K

5%

MF

2

38 67

OUT

15 64

OUT

15 64

15

OUT

IN

BI

18 25

15 37 64

15 36

15 36 68

15 18

15 29

26

15 64

39

15 64

Pull-up/down on chipset support page (depends on TBT controller) Cactus Ridge: Alias to TBT_CIO_PLUG_EVENT, requires pull-down. Redwood Ridge: Alias to TBT_CIO_PLUG_EVENT_L, requires pull-up (S0).

PLACE_NEAR=U0500.AW15:2.54mm

1

R1655

49.9

1% 1/20W MF 201

2

PLT_RESET_L

1

R1671

100K

5% 1/20W MF 201

2

OUT

29

IN

13 15 16 18

Pull-up on TBT page

Requires connection to SMC via 1K series R

AUD_SPI_CS_L

15 64

AUD_SPI_CLK

15 64

AUD_SPI_MISO

15 64

AUD_SPI_MOSI

15 64

TPAD_SPI_CS_L

15 36

TPAD_SPI_CLK

15 36 68

TPAD_SPI_MISO

15 36 68

TPAD_SPI_MOSI

15 36 68

PCH_BT_UART_D2R

15 64

PCH_BT_UART_R2D

15 64

PCH_UART1_RXD

15

PCH_UART1_TXD

15

JTAG_ISP_TDO

15 18

PCH_UART1_CTS_L

15

AP_S0IX_WAKE_L

15 29

PCH_I2C1_SDA

15

PCH_I2C1_SCL

15

PCH_BT_UART_RTS_L

15 64

PCH_BT_UART_CTS_L

15 64

R1660 R1661 R1662 R1663

R1664 R1665 R1666 R1667

R1668 R1669

R1672 R1673 R1674 R1675

R1676

R1678 R1679

R1670 R1677

SYNC_MASTER=WILL_J43 SYNC_DATE=01/14/2013

PAGE TITLE

100K 100K 100K 100K

47K 47K 47K 47K

47K 47K

100K

47K

100K

2.2K

47K 47K

PCH GPIO/MISC/LPIO

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

11 12 13 15 17 18 26 30 36

61 62 64 65 74

PP3V3_S0

8 38 39 40 41 42 43 44 45 56 59

21

21 21

21

21 21

21

21 21

21

21 21

5%

5% 5%

5%

5% 5%

5%

5% 5%

5%

5% 5%

5%

MF

1/20W

MF

1/20W 1/20W

MF

1/20W

MF

1/20W

MF

1/20W 1/20W

MF

1/20W

MF

1/20W 1/20W

MF

1/20W

MF

1/20W

MF

1/20W

MF

1/20W

MF

1/20W

MF

1/20W

MF

DRAWING NUMBER

<SCH_NUM>

REVISION

BRANCH

PAGE

16 OF 121

SHEET

15 OF 76

D

C

201

201 201

201

201 201

201

201 201

201

201 201

201

B

A

SIZE

D

124578

8 7 6 5 4 3

12

PP1V05_S0

6 8

11 15 16 17 38 42 51 55

0.1UF

6.3V 0201

XDP

58 59 62 64

1

R1830

150

5% 1/16W MF-LF 402

2

OBSFN_A0 OBSFN_A1

OBSDATA_A0 OBSDATA_A1

OBSDATA_A2 OBSDATA_A3

OBSFN_B0 OBSFN_B1

OBSDATA_B0 OBSDATA_B1

OBSDATA_B2 OBSDATA_B3

PWRGD/HOOK0

VCC_OBS_AB

XDP

1

R1831

10%

1K

5% 1/16W

2

MF-LF 402

2

C1800

0.1UF

CERM-X5R

Extra BPM Testpoints

XDP_BPM_L<2>

6

67

IN

XDP_BPM_L<3>

6

67

IN

XDP_BPM_L<4>

6

67

IN

XDP_BPM_L<5>

6

67

IN

XDP_BPM_L<6>

6

67

IN

XDP_BPM_L<7>

6

67

IN

D

CPU_VCCST_PWRGD

8

17

IN

PM_PWRBTN_L

13 37

OUT

PM_PCH_SYS_PWROK

13 17 37

OUT

XDP_CPU_TCK

6

16 64 67

C

OUT

PCH_JTAGX

12 16

OUT

1

TP

TP1802

TP-P6

1

TP

TP1803

TP-P6

1

TP

TP1804

TP-P6

1

TP

TP1805

TP-P6

1

TP

TP1806

TP-P6

1

TP

TP1807

TP-P6

PLACE_NEAR=U0500.C61:2.54mm

PLACE_NEAR=U5000.J3:2.54mm

R1800

R1802

R1804

R1835

XDP_CPU_PREQ_L

6

64 67

BI

XDP_CPU_PRDY_L

6

64 67

IN

CPU_CFG<0>

6

67

IN

CPU_CFG<1>

6

67

IN

CPU_CFG<2>

6

67

IN

CPU_CFG<3>

6

64 67

IN

XDP_BPM_L<0>

6

67

IN

XDP_BPM_L<1>

6

67

IN

CPU_CFG<4>

6

67

IN

CPU_CFG<5>

6

67

IN

CPU_CFG<6>

6

67

XDP

1K

0

XDP

21

5%

1/20W

MF

5%

1/20W

MF

5%

PLACE_NEAR=J1800.58:28mm

1/20W

MF-LF1/16W

MF

201

0201

402

0201

IN

6

67

IN

8

OUT

14 19 40 56 69

BI

14 19 40 56 69

IN

12 16 64 69

OUT

CPU_CFG<7>

XDP_CPU_VCCST_PWRGD

64

XDP_CPU_PWRBTN_L

CPU_PWR_DEBUG XDP_SYS_PWROK

64

SMBUS_PCH_DATA SMBUS_PCH_CLK XDP_PCH_TCK

C1804

CERM-X5R

XDP_CPU_PRESENT_L

PCH XDP Signals

These signals do not connect to XDP connector in this architecture, only accessible via Top-Side Probe. Nets are listed here to show XDP associations and to make clear what restrictions exist on PCH GPIOs when Top-Side Probe is used for PCH debug.

PCH/XDP Signals

XDP_MLB_RAMCFG0

15 18

B

A

BI

XDP_USB_EXTA_OC_L

14 16 35 14 16 35

OUT

XDP_USB_EXTB_OC_L

14 16 61 65

OUT

XDP_USB_EXTC_OC_L

14

OUT

XDP_USB_EXTD_OC_L

14

IN

XDP_SDCONN_STATE_CHANGE_L

15 16 33

OUT

XDP_MLB_RAMCFG1

15 18

BI

XDP_MLB_RAMCFG2

15 18

BI

XDP_MLB_RAMCFG3

15 18

BI

XDP_JTAG_ISP_TCK

15 16 18 25 15 16 18 25

IN

XDP_FW_PME_L

12 15

OUT

XDP_PCH_GPIO35

12

OUT

XDP_PCH_UART_SSD_L_BT_H

12

OUT

XDP_SSD_PCIE0_SEL_L

12

OUT

XDP_LPCPLUS_GPIO

15 16 64

BI

XDP_PCH_GPIO17

15

OUT

XDP_PCH_GPIO76

15

BI

XDP_JTAG_ISP_TDI

15 16 18 25 15 16 18 25

IN

MAKE_BASE=TRUE

R1884

MAKE_BASE=TRUE

Unused & MLB_RAMCFGx GPIOs have TPs.

USB Overcurrents are aliased, do not cause USB OC# events during PCH debug.

SDCONN_STATE_CHANGE_L is aliased, do not plug/unplug SD Cards during PCH debug.

JTAG_ISP (non-TMS) nets are aliased, do not attempt bit-banged JTAG during PCH debug.

NOTE: Should force PCH GPIO47 high to ensure TBT router powered to avoid leakage/clamping of signals.

SSD_PCIEx_SEL_L straps are connected via 1K to common net.

LPCPLUS_GPIO is aliased, do not attempt use during PCH debug.

1

TP

TP1870

TP-P6

1

TP

TP1873

TP-P6

1

TP

TP1874

TP-P6

1

TP

TP1876

TP-P6

1

TP

TP1877

TP-P6

1

TP

TP1878

TP-P6

1

TP

TP1879

TP-P6

1

TP

TP1880

TP-P6

1

TP

TP1881

TP-P6

1K

1

TP-P6

TP

21

TP1886 TP1887

5%

1/20W

MF

Non-XDP Signals

XDP_USB_EXTA_OC_L

XDP_USB_EXTB_OC_L

XDP_SDCONN_STATE_CHANGE_L

XDP_JTAG_ISP_TCK

NOTE: Must not short XDP pins together!

201

XDP_LPCPLUS_GPIO

XDP_JTAG_ISP_TDI

IN

OUT

BI

14 16 61 65

15 16 33

15 16 64

Merged (CPU/PCH) Micro2-XDP

CRITICAL XDP_CONN

J1800

DF40RC-60DP-0.4V

M-ST-SM1

62

61

1

8 7

9

10 12 11

14 13

16 15 18 17

20219

22 21 24 23

26 25

28 27 30329

32 31 34 33

36 35

38 37 40439

HOOK1

HOOK2 HOOK3

TCK1 TCK0

6.3V 0201

SDA SCL

XDP

1

10%

2

42 41

44 43 46 45

48 47

50549 52 51

54 53 56 55

58 57

60659

64 63

518S0847

CPU JTAG Isolation

PP5V_S0

17 32 45 51 52 56 58 59 61 62 64

PP3V3_S5

8

11 13 15 17 18 28 29 34 42

57 58 59 60 62 64 74

C1845

X5R-CERM

ALL_SYS_PWRGD

17 37 59

IN

0.1UF

0201

NOTE: This is not the standard XDP pinout. Use with 921-0133 Adapter Flex to support chipset debug.

OBSFN_C0 OBSFN_C1

OBSDATA_C0 OBSDATA_C1

OBSDATA_C2 OBSDATA_C3

OBSFN_D0 OBSFN_D1

OBSDATA_D0 OBSDATA_D1

OBSDATA_D2 OBSDATA_D3

ITPCLK/HOOK4 ITPCLK#/HOOK5 VCC_OBS_CD RESET#/HOOK6 DBR#/HOOK7

TDO TRSTn TDI TMS XDP_PRESENT# XDP

1

C1801

0.1UF

10%

6.3V

2

CERM-X5R 0201

1

10% 16V

2

NC

VCC

U1845

74LVC1G07GF

SOT891

2

A

1

NC NC

GND

6

Y

4

5

3

CPU_CFG<17> CPU_CFG<16>

CPU_CFG<8> CPU_CFG<9>

CPU_CFG<10> CPU_CFG<11>

CPU_CFG<19> CPU_CFG<18>

CPU_CFG<12> CPU_CFG<13>

CPU_CFG<14> CPU_CFG<15>

NC NC

XDP_CPURST_L

67

XDP_DBRESET_L

NOTE: XDP_DBRESET_L pulled-up to 3.3V on PCH Support Page

6

IN

6

IN

6

67

IN

6

67

IN

6

67

IN

6

67

IN

6

IN

6

IN

6

67

IN

6

67

IN

6

67

IN

6

67

IN

17 67

OUT

XDP_TRST_L

XDP

1

C1806

0.1UF

10%

6.3V

2

CERM-X5R 0201

PLACE_NEAR=J1800.51:28MM

CRITICAL

Q1840

DMN5L06VK-7

CRITICAL

Q1840

DMN5L06VK-7

CRITICAL

Q1842

DMN5L06VK-7

PLACE_NEAR=J1800.55:28mm

CRITICAL

Q1842

1

R1845

330K

5% 1/20W MF 201

2

XDP_JTAG_CPU_ISOL_L

DMN5L06VK-7

NC

R1805

XDP

SOT563

D

3

XDP

SOT563

D

6

XDP

SOT563

D

3

XDP

SOT563

D

6

VER 3

XDP_CPU_TDO

6

16 64 67

XDP_CPU_TCK

6

16 64 67

TDI and TMS are terminated in CPU.

XDP

1K

21

PLT_RESET_L

5%

1/20W

PLACE_NEAR=U0500.AG7:2.54mm

XDP_PCH_TDO

XDP_PCH_TDI XDP_PCH_TMS

5

S G

4

2

S G

1

5

S G

4

2

S G

1

MAKE_BASE=TRUE

PCH_JTAGX

12 16

XDP_PCH_TDO

12 16 64 69

XDP_PCH_TDI

12 16 64 69

XDP_PCH_TMS

12 16 64 69

XDP_PCH_TCK

12 16 64 69

XDP_CPUPCH_TRST_L

6

12 16 64 67

XDP_CPU_TDO

XDP_CPUPCH_TRST_L

XDP_CPUPCH_TRST_L XDP_CPUPCH_TRST_L

XDP_CPU_TDI

XDP_CPU_TMS

SYNC_MASTER=WILL_J43

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

R1810

PLACE_NEAR=U0500.F62:28mm

R1813

PLACE_NEAR=U0500.E60:28mm

201

MF

R1899

PLACE_NEAR=U0500.AE63:28mm

R1890

PLACE_NEAR=U0500.AE61:28mm

R1891

PLACE_NEAR=U0500.AD61:28mm

R1892

PLACE_NEAR=U0500.AD62:28mm

R1896

PLACE_NEAR=U0500.AE62:28mm

R1897

PLACE_NEAR=U0500.AU62:28mm

CPU/PCH Merged XDP

Apple Inc.

R

6 3

11 15 16 17 38 42 51 55

51

IN

OUT OUT

IN

6

12 16 64 67

OUT OUT

OUT

1K

51

PP1V05_S0

6 8 58 59 62 64

13 15 18

12 16 64 69

6

16 64 67

6

12 16 64 67

6

12 16 64 67

6

64 67

6

64 67

PP1V05_SUS

57 62

NO STUFF

XDP

21

5%

12

5%

12

5%

12

5%

12

5%

12

5%

12

5%

12

5%

1/20W

MF

1/20W

MF

1/20W

MF

1/20W

MF

1/20W

MF

1/20W

MF

1/20W

MF

1/20W

MF

SYNC_DATE=12/17/2012

DRAWING NUMBER

<SCH_NUM>

REVISION

BRANCH

PAGE

18 OF 121

SHEET

16 OF 76

124578

201

D

C

B

201

A

SIZE

D

8 7 6 5 4 3

This looks a little ugly to support new and old parts. With GreenCLK Rev C pin 5 must receive S5 power (Stuff R2042)

D

GreenCLK 25MHz Power Must be powered if any VDDIO is powered.

CAM XTAL Power TBT XTAL Power

C1905

12PF

2 1

5%

25V

CERM

NC

0201

NC

C1906

12PF

21

5%

25V CERM 0201

C

C1915

6.8PF

21

+/-0.1PF

25V C0G

NC

0201

NC

C1916

6.8PF

21

+/-0.1PF

25V C0G

0201

LPC_CLK24M_SMC_R

12 69

IN

B

System RTC Power Source & 32kHz / 25MHz Clock Generator

Chipset uses 24MHz crystal, GreenCLK kept to save 1x 25MHz crystal & 1x 32kHz crystal

PP3V42_G3H

17 30 35 36 37 38 40 46 49 50 59 61 62 64 65

Coin-Cell: VBAT (300-ohm & 10uF RC) No Coin-Cell: 3.42V G3Hot (no RC)

PP3V3_S5

8

11 13 15 16 17 18 28 29 34

42 57 58 59 60 62 64 74

Coin-Cell & G3Hot: 3.42V G3Hot Coin-Cell & No G3Hot: 3.3V S5

PP3V3_S5RS3RS0_SYSCLKGEN

18

PP1V2_CAM_XTALPCIEVDD

31

PP3V3_TBTLC

18 25 26 62 64

C1924

0.1UF

10% 16V

X5R-CERM

0201

R1905

0

1/20W

0201

21

5% MF

SYSCLK_CLK25M_X2

CRITICAL

Y1905

42

25.000MHZ-12PF-20PPM

31

SM-3.2X2.5MM

NOTE: 30 PPM or better required for RTC accuracy

No Coin-Cell: 3.3V S5

1

C1922

0.1UF

10%

2

16V

X5R-CERM

0201

CKPLUS_WAIVE=PwrTerm2Gnd

SYSCLK_CLK25M_X2_R

69 69

NO STUFF

1

R1906

1M

5% 1/20W MF 201

2

SYSCLK_CLK25M_X1

69

1

2

No bypass necessary

C1902

1UF

20%

6.3V X5R 0201

PCH 24MHz Crystal

R1915

0

1/20W

0201

21

5%

MF

PCH_CLK24M_XTALOUT

1

R1916

1M

5% 1/20W MF 201

2

PCH_CLK24M_XTALIN

PCH_CLK24M_XTALOUT_R

CRITICAL

Y1915

NC

24.000MHZ-20PPM-6PF

NC

4 2

3 1

3.20X2.50MM-SM1

PCH 24MHz Outputs

LPC_CLK24M_SMC

MAKE_BASE=TRUE

LPC_CLK24M_SMC

PLACE_NEAR=U0500.AN15:5.1mm

R1927

22

5%

1/20W

MF

201

21

OUT

17 37 69

OUT

IN

17 37 69

NC

U1900

SLG3NB148CV

CRITICAL

11

VIOE_25M_A

6

VIOE_25M_B

14

VIOE_25M_C

3

X2

4

X1

7

NC_RTC_CLK32K_RTCX2

12 17

MAKE_BASE=TRUE

12

GND

TQFN

10

12

PCH Reset Button

61 62 64 65 74

PP3V3_S0

8

11 12 13 15 17 18 26 30 36

38 39 40 41 42 43 44 45 56 59

XDP

XDP_DBRESET_L

13

5

VDD

THRM

PAD

VG3HOT

32.768K

25M_A 25M_B 25M_C

VOUT

17216

NO_TEST=TRUE

VBAT and +V3.3A are internally ORed to create VDD_RTC_OUT.

+V3.3A should be first available ~3.3V power to reduce VBAT draw.

12

9

8

15

1

PCH_CLK32K_RTCX1

NC

SYSCLK_CLK25M_CAMERA SYSCLK_CLK25M_TBT PPVRTC_G3H

For SB RTC Power

1

C1910

1UF

20%

6.3V

2

X5R 0201

NC_RTC_CLK32K_RTCX2

8

12 13 62 64

12

OUT

32 69

OUT

25 69

OUT

12 17

IN

R1996

1/20W

0201

1

R1995

10K

5% 1/20W MF 201

2

0

21

PM_SYSRST_L

NO STUFF

MF 5%

1

R1997

0

5% 1/16W MF-LF 402

2

SILK_PART=SYS RESET

13 37 64 16 67

BIIN

8

11 58

PP1V5_S0SW_AUDIO_HDA

PP1V2_S3

19 20 21 22 23 42 53 62 70

CPU_MEMVTT_PWR_EN_LSVDDQ

6

IN

SPI_DESCRIPTOR_OVERRIDE_L

37

IN

PCH uses HDA_SDO as a power-up strap. If low, ME functions normally. If high, ME is disabled. This allows for full re-flashing of SPI ROM. SMC controls strap enable to allow in-field control of strap setting. Q1920 & 5V pull-up allows circuit to work regardless of HDA voltage.

8

11 13 15 16 17 18 28 29 34

42 57 58 59 60 62 64 74

Memory VTT Enable Level-Shifter

CPU output is on VDDQ rail (1.2V), TPS51916 has 1.8V Vih(min).

C1970

0.1UF

X5R-CERM

0201

1

10% 16V

2

NC

6

VCC

U1970

74AUP1G07GF

SOT891

2

A Y

1

NC NC

GND

3

4

5

PCH ME Disable Strap

PP3V3_S5

13 18 37 59

ALL_SYS_PWRGD

16 17 37 59

PM_SLP_S3_L

IN

Q1920

DMN5L06VK-7

SOT563

3

DMN5L06VK-7

VCCST (1.05V S0) PWRGD

C1930

0.1UF

10% 16V

X5R-CERM

0201

D

Q1920

SOT563

VER 3

1

2

VER 3

2

NC

5

SPI_DESCRIPTOR_OVERRIDE_LS5V

S G

SPI_DESCRIPTOR_OVERRIDE

4

6

D

SG

1

CRITICAL

U1930

74AUP1G09

6

SOT891

VCC

GND

4

YA

3

2

1

B

5

NC

16 32 45 51 52 56 58 59 61 62 64

PP3V3_S0

1

R1970

330K

5% 1/20W MF 201

2

PP5V_S0

1

R1931

10K

2

TPS51916 I(leak) = +/- 1uA, Vih(min) = 1.8V 33uW when driven-low

MEMVTT_PWR_EN

MAKE_BASE=TRUE

MEMVTT_PWR_EN

1

R1921

1K

5% 1/20W MF 201

2

HDA_SDOUT_R

IPD = 9-50k

PP1V05_S0

5% 1/20W MF 201

CPU_VCCST_PWRGD

62 64 65 74 8

11 12 13 15 17 18 26 30 36 38

39 40 41 42 43 44 45 56 59 61

17 53

OUT

1

R1920

100K

5% 1/20W MF 201

2

6 8

11 15 16 38 42 51 55 58 59

62 64

8

16

OUT

D

12 69

OUT

C

B

PP3V42_G3H

17 30 35 36 37 38 40 46 49 50 59 61 62 64 65

61 62 64 65 74

PP3V3_S0

8

11 12 13 15 17 18 26 30 36

38 39 40 41 42 43 44 45 56 59

CPU_VR_EN

8

51

IN

1

R1955

10K

5%

A

CPU_VR_READY

8

17 51

OUT

MAKE_BASE=TRUE

CPU_VR_READY

8

17 51

IN

1/20W

NO STUFF

MF

201

R1951

2

1/20W

0

21

5%

MF

0201

16 17 37 59

IN

26 27 37 38

IN

ALL_SYS_PWRGD

CPUVR_PGOOD_R

SMC_DELAYED_PWRGD

R1950

1/20W

10K

1

5%

MF

201

2

1

A

U1950

2

08

B

PCH PWROK Generation

BYPASS=U1950:5MM

1

C1950

0.1UF

10% 16V

2

X5R-CERM 0201

74LVC2G08GT/S505

8

SOT833

7

Y

4

PM_S0_PGOOD

NO STUFF

R1963

R1961

100K

1/20W

5%

MF

201

1/20W

NO STUFF

2

R1960

0

5%

5% 1/20W

MF

0201

1

5

A

1

2

6

U1950

B

WF: Do we need this?

CKPLUS_WAIVE=UNCONNECTED_PINS

74LVC2G08GT/S505

8

SOT833

3

SYS_PWROK_R

Y

08

4

R1962

1K

5%

1/20W

MF

201

6 3

21

PM_PCH_SYS_PWROK

PM_PCH_PWROK PM_PCH_PWROK

MAKE_BASE=TRUE

13 17

OUT

13 17

OUT

SIZE

A

D

13 16 37

OUT

PAGE TITLE

Chipset Support

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=01/09/2013SYNC_MASTER=J43_MLB1

DRAWING NUMBER

<SCH_NUM>

REVISION

BRANCH

PAGE

19 OF 121

SHEET

17 OF 76

124578

8 7 6 5 4 3

12

R2016

1/20W

14 39

OUT

10K

1

5%

MF

201

2

DDC Pull-Ups

NO STUFF

1

2.2K

1/20W

1

R2021

2.2K

5%

5% 1/20W

MF

201

2

MAKE_BASE

TRUE

R2018

R2020

1

R2017

10K

5% 1/20W MF 201

2

TBT Aliases

MAKE_BASE

TRUE

MAKE_BASE

TRUE

TRUE TRUE

TRUE

PCH_SML1ALERT_L

NO STUFF

R2022

2.2K

1/20W

61 62 64 65 74

PP3V3_S0

8

11 12 13 15 17 18 26 30 36

38 39 40 41 42 43 44 45 56 59

HDMITBTMUX_SEL_TBT

TBT_CIO_PLUG_EVENT_L

1

R2019

10K

5%

1/20W

5% 1/20W

MF

201

2

DP_TBTSNK0_DDC_CLK DP_TBTSNK0_DDC_DATA

DP_TBTSNK1_HPD DP_TBTSNK1_ML_C_P<3..0> DP_TBTSNK1_ML_C_N<3..0> DP_TBTSNK1_AUXCH_C_P DP_TBTSNK1_AUXCH_C_N DP_TBTSNK1_DDC_CLK DP_TBTSNK1_DDC_DATA

XDP_JTAG_ISP_TCKXDP_JTAG_ISP_TCK

PP3V3_SUS

1

R2010

100K

5% 1/20W MF 201

2

1

R2023

2.2K

5%

5% 1/20W

MF

201

2

1

R2015

100K

5%

1/20W

MF

201

2

BIBI

IN

D

15 18 25 15 18 25

C

1

R2014

10K

5% 1/20W MF 201

2

13 18 28

OUT

13 18 28

BI

13 18 25

IN

5

25 67

OUT

5

25 67

OUT

13 18 25

BI

67 13 18 25

BI

67

13 18

OUT OUT

8

11 14 46 57 58 59 62 64

15 16 18 25

B

Platform Reset Connections

Unbuffered

PLT_RESET_L

13 15 16

IN

R2071

0

21

5%

1/20W

MF

D

61 62 64 65 74 38 39 40 41 42

PP3V3_S0

8

11 12 13 15

17 18 26 30 36 43 44 45 56 59

1

C2071

0.1UF

10% 16V

2

X5R-CERM 0201

PP3V3_S5

8

11 13 15 16 17 18 28 29 34

42 57 58 59 60 62 64 74

NOSTUFF

BYPASS=U2030:3mm

C2030

X5R-CERM

C

PM_SLP_S4_L

13 18 29 36 37 59

IN

CAMERA_PWR_EN_PCH

15

IN

1

2

0.1UF

U2071

10% 10V

0201

CRITICAL

5

MC74VHC1G08

SC70-HF

4

3

1

2

U2030

1

NC

5 3

PLT_RST_BUF_L

1

R2070

100K

5% 1/20W MF 201

2

PCH_TBT_PCIE_RESET_L

IN

MAKE_BASE=TRUE

NOSTUFF

CRITICAL

74LVC1G08

6

SOT891

4

08

Scrub for Layout Optimization

Buffered

CAMERA_PWR_EN

R2072

0

5%

1/20W

MF

0201

NOSTUFF

R2089

0

5%

1/20W

MF

0201

OUT

31

0201

21

R2088

0

21

5%

1/20W

MF

0201

21

PCA9557D_RESET_L

SMC_LRESET_L

BKLT_PLT_RST_L

CAM_PCIE_RESET_L

PCH_TBT_PCIE_RESET_L

OUT

19

37

56

15 31

15 18 25 15 18 25

From RR

From PCH

Redwood Ridge JTAG Isolation

25

IN

15

IN

S0 pull-up on PCH page

PP3V3_S3

15 19 33 36 40 41 58 62 64

61 62 64 65 74

PP3V3_S0

8

11 12 13 15 17 18 26 30 36

38 39 40 41 42 43 44 45 56 59

PP3V3_S5

8

11 13 15 16 17 18 28 29 34

42 57 58 59 60 62 64 74

TBTLC can be on when S0 is off, and vice-versa

PP3V3_TBTLC

17 25 26 62 64

JTAG_TBT_TDO JTAG_ISP_TDO

JTAG_TBT_TMS_PCH

GreenCLK 25MHz Power

NO STUFF

R2040

0

21

5%

1/20W

MF

0201

NO STUFF

R2041

0

21

5%

1/20W

MF

0201

R2042

0

21

5%

1/20W

MF

0201

Isolation ensures no leakage to RR or PCH

1

R2061

100K

1/20W

C2060

0.1UF

20%

5%

10V

2

CERM

MF

201

402

2

52

VCC

U2060

74LVC2G07

SOT891

1

1A 1Y

3

2A 2Y

6

4

GND

PP3V3_S5RS3RS0_SYSCLKGEN

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.3V MAKE_BASE=TRUE

R2041/2 should be stuffed for GreekCLK A or B depending on S2 rail

R2042 should be stuffed for GreenCLK C

1

R2062

100K

5% 1/20W MF 201

2

S0 pull-up on PCH page

JTAG_TBT_TMS

OUT

To PCH

15

To RR

25

17 18

2.2k pull-ups are required by PCH to indicate active display interface.

DP++ spec violation, should remove!

61 62 64 65 74

PP3V3_S0

8

11 12 13 15 17 18 26 30 36

17 18

38 39 40 41 42 43 44 45 56 59

DP_TBTSNK0_DDC_CLK

13 18 28

DP_TBTSNK0_DDC_DATA

13 18 28

DP_TBTSNK1_DDC_CLK

13 18

DP_TBTSNK1_DDC_DATA

13 18

TBTSNK1_DDC is pulled-up just to indicate that DP port is used. No DDC on this port, AUX-only.

NOTE: Only DDC_DATA is sensed by PCH, so DDC_CLK pull-ups are unstuffed.

Thunderbolt Pull-up/downs

CR: TBT_GO2SX_BIDIR, requires 100k pull-up to SUS RR/FR: DPHDMIMUX_SEL_TBT, requires 100k pull-up to TBTLC (on TBT page)

HDMITBTMUX_SEL_TBT

Falcon Ridge PLUG_EVENT is active-low, always driven (pull-up)

TBT_CIO_PLUG_EVENT_L

15 18 25 15 18 25

OUT

Required for unused second TBT port

TBT_B_CIO_SEL

25

IN

DP_TBTPB_HPD

25

OUT

TBT_B_CONFIG2_RC

25

OUT

TBT_B_CONFIG1_BUF

25

OUT

TBT_B_LSRX

25

NC

NOTE: Solution shown is for LPT-LP. Other PCH’s may require isolation on TCK

R2030

0

21

5%

1/20W

MF

PP3V3_S5_DBGLED

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.25 MM VOLTAGE=3.3V

1

5%

MF

2

S4_PWR_EN

IN

PM_SLP_S4_L

IN

PM_SLP_S3_L

IN

PM_SLP_S0_L

IN

0201

DBGLED

A

D2091

GREEN-56MCD-2MA-2.65V LTQH9G-SM

K

PLACE_SIDE=BOTTOM SILK_PART=STBY_ON

DBGLED_S4_D

DBGLED

Q2090

DMN5L06VK-7

SOT563

VER 3

58 59 60 18 28 29

PP3V3_S5

8

11 13

15 16 17 34 42 57 62 64 74

PLACE_SIDE=BOTTOM

B

A

K

DBGLED

R2094

2 1

DBGLED_S5

DBGLED

D2090

GREEN-56MCD-2MA-2.65V LTQH9G-SM

PLACE_SIDE=BOTTOM SILK_PART=S5_ON

0

5% 1/16W MF-LF

402

DBGLED

R2090

1/20W

20K

201

28 58 59

13 18 29 36 37 59

13 17 37 59

13 37

Power State Debug LEDs

(For development only)

DBGLED

1

R2091

20K

5%

1/20W

MF

201

2

D

2

SG

DBGLED_S3DBGLED_S4

DBGLED

A

D2092

GREEN-56MCD-2MA-2.65V LTQH9G-SM

K

PLACE_SIDE=BOTTOM SILK_PART=S3_ON

DBGLED_S3_D

6

1

Q2090

DMN5L06VK-7

DBGLED

R2092

DBGLED

SOT563

VER 3

5

1/20W

20K

DBGLED

Q2091

DMN5L06VK-7

SOT563

VER 3

DBGLED

R2093

1/20W

2

20K

1

5%

MF

201

2

DBGLED_S0

DBGLED

A

D2095

GREEN-56MCD-2MA-2.65V LTQH9G-SM

K

PLACE_SIDE=BOTTOM SILK_PART=S0_ON

DBGLED_S0_D

6

D

SG

1

DBGLED

Q2091

DMN5L06VK-7

SOT563

VER 3

1

5%

MF

201

2

DBGLED_S0I3

DBGLED

A

D2093

GREEN-56MCD-2MA-2.65V LTQH9G-SM

K

PLACE_SIDE=BOTTOM SILK_PART=S0I3_ON

DBGLED_S0I3_D

3

D

SG

4

and TDI as well for PCH glitch-prevention.

NOTE: This reference schematic assumes PCH JTAG GPIOs are only used for Thunderbolt. If other ASIC JTAG signals are wired into these GPIOs different isolation techniques will likely be necessary.

DBGLED

1

R2095

1/20W

5

20K

5%

MF

201

2

3

D

SG

Renaming the pins N61 and P61 to remove automatic diffpari property

4

Pin N61 needs a TP for Power to perform iFDIM test

TP_CPU_RSVDN61

8

18

8

18

XDP_MLB_RAMCFG0

15 16

OUT

XDP_MLB_RAMCFG1

15 16

OUT

XDP_MLB_RAMCFG2

15 16

OUT

XDP_MLB_RAMCFG3

15 16

OUT

TP_CPU_RSVDN61

MAKE_BASE=TRUE

TP_CPU_RSVDP61TP_CPU_RSVDP61

MAKE_BASE=TRUE

8

18

8

18

RAM Configuration Straps

Pull-downs for chip-down RAM systems

RAMCFG3:L

R2050

1/20W

10K

RAMCFG2:L

1

5% MF

201

2

R2051

1/20W

10K

5% MF

201

RAMCFG1:L

1

2

R2052

10K

1/20W

DP_TBTSNK0_DDC_CLK

13 18 28

IN

DP_TBTSNK0_DDC_DATA

13 18 28

BI

DP_TBTSNK1_HPD

13 18 25

OUT

=DP_TBTSNK1_ML_C_P<3..0>

IN

=DP_TBTSNK1_ML_C_N<3..0>

IN

DP_TBTSNK1_AUXCH_C_P

13 18 25 67

BI

DP_TBTSNK1_AUXCH_C_N

13 18 25 67

BI

DP_TBTSNK1_DDC_CLK

13 18

IN

DP_TBTSNK1_DDC_DATA

13 18

BI

Single-port TBT implementation does not require DDC Crossbar

15 16 18 25

IN

XDP_JTAG_ISP_TDI XDP_JTAG_ISP_TDI

15 16 18 25

IN

No MAKE_BASE on TCK/TDI as these are provided on XDP page.

RAMCFG0:L

1

5% MF

201

2

R2053

1/20W

10K

1

5% MF

201

2

A

LPDDR3 Alias Support

TP_CPU_MEM_RESET_L

6

18

IN

TP_MEM_VDD_SEL_1V5_L

15 18

IN

PP0V6_S3_MEM_VREFDQ_A

18 19 20 21 70 18 19 20 21 70

PP0V6_S3_MEM_VREFCA_A PP0V6_S3_MEM_VREFCA_A

18 19 20 21 70 18 19 20 21 70

PP0V6_S3_MEM_VREFDQ_B PP0V6_S3_MEM_VREFDQ_B

18 19 22 23 70 18 19 22 23 70

PP0V6_S3_MEM_VREFCA_B PP0V6_S3_MEM_VREFCA_B

18 19 22 23 70 18 19 22 23 70

TP_CPU_MEM_RESET_L

MAKE_BASE=TRUE

TP_MEM_VDD_SEL_1V5_L

MAKE_BASE=TRUE

PP0V6_S3_MEM_VREFDQ_A

MAKE_BASE=TRUE

VOLTAGE=0.6V

6

15 18

18

6 3

SYNC_MASTER=J43_MLB

PAGE TITLE

Project Chipset Support

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=01/17/2013

DRAWING NUMBER

<SCH_NUM>

REVISION

BRANCH

PAGE

20 OF 121

SHEET

18 OF 76

124578

SIZE

A

D

8 7 6 5 4 3

12

Page Notes

Power aliases required by this page:

- =PP3V3_S3_VREFMRGN

- =PPDDR_S3_MEMVREF

Signal aliases required by this page:

- =I2C_VREFDACS_SCL

- =I2C_VREFDACS_SDA

- =I2C_PCA9557D_SCL

- =I2C_PCA9557D_SDA

BOM options provided by this page:

- DDRVREF_DAC - Stuffs DAC margining circuit.

D

C

PP3V3_S3

15 18 19 33 36 40 41 58 62 64

B

A

DAC Channel:

PCA9557D Pin:

Nominal value

Margined target:

DAC range:

VRef current:

DAC step size:

MEM A VREF DQ

0.600V (DAC: 0x2E.5)

0.300V - 0.900V (+/- 300mV)

0.000V - 1.199V (0x00 - 0x5D)

+73uA - -73uA (- = sourced)

6.36mV / step @ output

DAC-Based Margining

DAC sets voltage level, PCA9557 & FETs enable outputs and disables margining after platform reset.

OMIT

R2218

SHORT

21

PP3V3_S3_VREFMRGN_DAC

MIN_LINE_WIDTH=0.3 mm

NONE

MIN_NECK_WIDTH=0.2 mm

NONE

VOLTAGE=3.3V

NONE 402

SMBUS_PCH_CLK

14 16 19 40 56

IN

69

SMBUS_PCH_DATA

14 16 19 40 56

BI

69

Addr=0x98(WR)/0x99(RD)

Addr=0x30(WR)/0x31(RD)

SMBUS_PCH_CLK

14 16 19 40 56 69

IN

SMBUS_PCH_DATA

14 16 19 40 56 69

BI

RST* on ’platform reset’ so that system watchdog will disable margining.

NOTE: Margining will be disabled across all soft-resets and sleep/wake cycles.

MEM B VREF DQ

A B

1

2

LPDDR3 (1.2V)

PCA9557D_RESET_L

18

IN

MEM A VREF CA

0.675V (DAC: 0x34)

0.337V - 1.013V (+/- 337.5mV)

+82uA - -82uA (- = sourced)

6.36mV / step @ output

CPU-Based Margining

FETs for CPU isolation during DAC margining

CPU_DIMMA_VREFDQ

7

IN

CPU_DIMMB_VREFDQ

7

IN

NOTE: CPU DAC output step sizes: DDR3 (1.5V) 7.70mV per step DDR3L (1.35V) 6.99mV per step LPDDR3 (1.2V) ?.??mV per step

CPU_DIMM_VREFCA

7

1

2

C2202

0.1UF

CERM-X5R

IN

DDRVREF_DAC

1

C2201

0.1UF

10%

6.3V

2

CERM-X5R 0201

1

10%

6.3V 2

0201

MEM B VREF CA

6

SCL

7

SDA

9

A0

10

A1

3

A0

4

A1

5

A2

1

SCL

2

SDA

C

4

NOTE: CPU has single output for VREFCA. Split into two signals for independent DAC margining support. When DAC margining VREFCA ensure VREFMRGN_CPU_EN is low to remove short due to CPU.

DDRVREF_DAC

C2200

2.2UF

20%

6.3V CERM

402-LF

DDRVREF_DAC

C

3

DDR3L (1.35V)

CPU_MEM_VREFDQ_A_ISOL

EN RC’s to avoid drain glitches May not be necessary due to C22x0

21

VREFMRGN_DQ_A_EN_RC

CPU_MEM_VREFDQ_B_ISOL

21

VREFMRGN_DQ_B_EN_RC

CPU_MEM_VREFCA_A_ISOL

21

VREFMRGN_CA_A_EN_RC

CPU_MEM_VREFCA_B_ISOL

21

VREFMRGN_CA_B_EN_RC

(All 4 R’s) DDRVREF_DAC

DDRVREF_DAC

21

VREFMRGN_DQ_A_RDIV

1%

1/20W

21

VREFMRGN_DQ_B_RDIV

1%

1/20W

21

VREFMRGN_CA_A_RDIV

1%

1/20W

21

VREFMRGN_CA_B_RDIV

1%

1/20W

DDRVREF_DAC

R2213

100K

1/20W

R2212

100K

1/20W

C2205

5%

MF

201

5%

MF

201

0.1UF

CERM-X5R

1

2

1

2

1

10%

6.3V 2

0201

DDRVREF_DAC

C2225

0.1UF

CERM-X5R

DDRVREF_DAC

C2245

0.1UF

CERM-X5R

DDRVREF_DAC

C2265

0.1UF

CERM-X5R

DDRVREF_DAC

C2285

0.1UF

CERM-X5R

MF

C2

C3

A2

A3

1

10%

6.3V 2

0201

1

10%

6.3V 2

0201

1

10%

6.3V 2

0201

1

10%

6.3V 2

0201

201

PP3V3_S3

CRITICAL DDRVREF_DAC

B1

U2204

MAX4253

V+

UCSP

C1

C4

V-

B4

CRITICAL DDRVREF_DAC

B1

U2204

MAX4253

V+

UCSP

A1

A4

V-

B4

Pins B1 & B4: CKPLUS_WAIVE=unconnected_pinsCKPLUS_WAIVE=unconnected_pins

THRM

PAD

CRITICAL DDRVREF_DAC

8

U2200

PCA9557

17

VDD

MSOP

GND

3

VCC

U2201

QFN

GND

1

VOUTA

2

VOUTB

4

VOUTC

DAC5574

5

VOUTD

NOTE: MEMVREG and SPARE share a DAC output, cannot enable both at the same time!

CRITICAL DDRVREF_DAC

16

6

P0

(OD)

7

P1

9

P2

10

P3

11

P4

12

P5

13

P6

14

P7

15

RESET*

8

2

S G

1

2

S G

1

5

S G

4

5

S G

4

VREFMRGN_DQ_A

VREFMRGN_DQ_B

VREFMRGN_CA_AB

VREFMRGN_MEMVREG

VREFMRGN_CPU_EN VREFMRGN_DQ_A_EN VREFMRGN_DQ_B_EN VREFMRGN_CA_A_EN VREFMRGN_CA_B_EN VREFMRGN_MEMVREG_EN VREFMRGN_SPARE_EN

NC

CRITICAL

Q2220

DMN5L06VK-7

VER 3

SOT563

D

6

CRITICAL

Q2260

DMN5L06VK-7

VER 3

SOT563

D

6

CRITICAL

Q2220

DMN5L06VK-7

VER 3

SOT563

D

3

CRITICAL

Q2260

DMN5L06VK-7

VER 3

SOT563

D

3

R2200

100K

1/20W

1

5%

MF

201

2

MEM VREG

DDRVREF_DAC

R2201

100K

1/20W

DDRVREF_DAC

R2202

100K

1/20W

DDRVREF_DAC

R2215

100K

1/20W

DDRVREF_DAC

R2207

100K

1/20W

R2226 R2246 R2266 R2286

1

5%

MF

201

2

1

5%

MF

201

2

1

5%

MF

201

2

1

5%

MF

201

2

DDRVREF_DAC

R2225

100K

5%

1/20W

MF

201

DDRVREF_DAC

R2245

100K

5%

1/20W

MF

201

DDRVREF_DAC

R2265

100K

5%

1/20W

MF

201

DDRVREF_DAC

R2285

100K

5%

1/20W

MF

201

4.02K

DDRVREF_DAC

D

LPDDR3 (1.2V)

1.200V (DAC: 0x5D)

0.800V - 1.600V (+/- 400mV)

0.000V - 2.397V (0x00 - 0xBA)

+21uA - -21uA (- = sourced)

4.28mV / step @ output

5

DDR3L (1.35V)

1.343V (DAC: 0x68)

0.972V - 1.714V (+/- 371mV)

0.000V - 2.694V (0x00 - 0xD1)0.000V - 1.354V (0x00 - 0x69)

+25uA - -25uA (- = sourced)

3.53mV / step @ output

NOTE: LPDDR3 assumes TPS51916 supply with 28.7k/57.6k divider DDR3L assumes TPS51916 supply with 19.6k/57.6k divider

6 3

CRITICAL

DDRVREF_DAC

Q2225

2

DMN5L06VK-7

VER 3

S G

1

Q2225 pin 6:

PLACE_NEAR=Q2220.6:2.54mm

2

1

Q2265 pin 6:

PLACE_NEAR=Q2260.6:2.54mm

5

4

5

4

R22x6 pin 2:

PLACE_NEAR=Q2225.1:2.54mm

PLACE_NEAR=Q2265.1:2.54mm

PLACE_NEAR=Q2225.4:2.54mm PLACE_NEAR=Q2265.4:2.54mm

6

CRITICAL

DDRVREF_DAC

Q2265

DMN5L06VK-7

VER 3

S G

6

CRITICAL

DDRVREF_DAC

Q2225

DMN5L06VK-7

VER 3

S G

3

CRITICAL

DDRVREF_DAC

Q2265

DMN5L06VK-7

VER 3

S G

3

15 18 19 33 36 40 41 58 62 64

VREFMRGN_MEMVREG_BUF

VREFMRGN_SPARE_BUF

SOT563

D

SOT563

D

SOT563

D

SOT563

D

VRef Dividers

Always used, regardless of margining option.

R2223

10

21

1%

1/20W

MF 201

PLACE_NEAR=Q2220.6:2mm

1

C2220

0.022UF

10%

6.3V

2

X5R-CERM 0201

MEM_VREFDQ_A_RC

R2243

10

1%

1/20W

MF 201

PLACE_NEAR=Q2260.6:2mm

1

C2240

0.022UF

10%

6.3V

2

X5R-CERM 0201

MEM_VREFDQ_B_RC

R2263

10

1%

1/20W

MF 201

PLACE_NEAR=Q2220.3:2mm

1

C2260

0.022UF

10%

6.3V

2

X5R-CERM 0201

MEM_VREFCA_A_RC

R2283

10

1%

1/20W

MF 201

PLACE_NEAR=Q2260.3:2mm

1

C2280

0.022UF

10%

6.3V

2

X5R-CERM 0201

MEM_VREFCA_B_RC

DDRVREF_DAC

R2214

38.3K

21

1%

1/20W

MF

201

DDRVREF_DAC

1

R2217

1M

5% 1/20W MF 201

2

PLACE_NEAR=R7415.2:1mm

21

DDRREG_FB

PLACE_NEAR=R2221.2:1mm

PLACE_NEAR=R2241.2:1mm

PLACE_NEAR=R2261.2:1mm

PLACE_NEAR=R2281.2:1mm

PP1V2_S3

1

R2221

8.2K

1% 1/20W MF 201

2

PLACE_NEAR=Q2220.6:3mm

PP0V6_S3_MEM_VREFDQ_A

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm

1

R2222

8.2K

1%

1/20W

MF

201

2

R2220

24.9

21

1%

1/20W

MF

201

R2242

8.2K

1/20W

201

R2240

24.9

21

1%

1/20W

MF

201

R2262

8.2K

1/20W

201

R2260

24.9

21

1%

1/20W

MF

201

R2282

8.2K

1/20W

201

R2280

24.9

21

1%

1/20W

MF

201

53

OUT

SYNC_MASTER=J41_MLB

PAGE TITLE

1%

MF

1%

MF

1%

MF

1

2

1

2

1

2

1

R2241

8.2K

1% 1/20W MF 201

2

PLACE_NEAR=Q2260.6:3mm

PP0V6_S3_MEM_VREFDQ_B

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm

1

R2261

8.2K

1% 1/20W MF 201

2

PLACE_NEAR=Q2220.3:3mm

PP0V6_S3_MEM_VREFCA_A

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm

1

R2281

8.2K

1% 1/20W MF 201

2

PLACE_NEAR=Q2260.3:3mm

PP0V6_S3_MEM_VREFCA_B

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm

DDR3 VREF MARGINING

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

17 20 21 22 23 42 53 62 70

SYNC_DATE=02/12/2013

DRAWING NUMBER

<SCH_NUM>

REVISION

BRANCH

PAGE

22 OF 121

SHEET

19 OF 76

124578

18 20 21 70

18 22 23 70

18 20 21 70

18 22 23 70

SIZE

D

C

B

A

D

8 7 6 5 4 3

12

D

LPDDR3 CHANNEL A (0-31)

U2300

LPDDR3-16GB

FBGA

NC NC NC NC NC NC NC NC NC NC NC NC

NC NC NC

1

C2300

0.1UF

10% 16V

2

X5R-CERM 0201

R2

P2 N2

N3

M3 F3

E3

E2 D2

C2

K3 K4

J3

J2

L3

L4

L8 G8

P8 D8

J8

B3

B4

H4

J11

A1

A2 A12

A13

B1 B13

T1

T13

U1

U2

U12 U13

C4

K9

R3

MEM_A_CAA<0>

24 63 70

IN

MEM_A_CAA<1>

24 63 70

IN

MEM_A_CAA<2>

24 63 70

IN

MEM_A_CAA<3>

24 63 70

IN

MEM_A_CAA<4>

24 63 70

IN

MEM_A_CAA<5>

24 63 70

IN

MEM_A_CAA<6>

7

24 63 70

IN

MEM_A_CAA<7>

24 63 70

IN

MEM_A_CAA<8>

24 63 70

IN

MEM_A_CAA<9>

24 63 70

IN

MEM_A_CKE<0>

7

24 70

IN

MEM_A_CKE<1>

7

24 70

IN

MEM_A_CLK_P<0>

7

24 70

IN

MEM_A_CLK_N<0>

7

24 70

IN

MEM_A_CS_L<0>

7

21 24 70

C

R2300

1/20W

243

1

1%

MF

201

2

R2301

1/20W

243

1

1%

MF

201

2

C2340

0.047UF

10%

6.3V X5R 201

1

C2341

0.047UF

10%

6.3V

2

X5R 201

IN

MEM_A_CS_L<1>

7

21 24 70

IN

MEM_A_ODT<0>

7

21 24 63 70

IN

MEM_A_ZQ<0> MEM_A_ZQ<1>

PP0V6_S3_MEM_VREFCA_A

18 19 21 70

PP0V6_S3_MEM_VREFDQ_A

18 19 21 70

B

PP1V2_S3

17 19 20 21 22 23 42 53 62 70

CA0 CA1 CA2 CA3 CA4 CA5 CA6 CA7 CA8 CA9

CKE0 CKE1

CK_T CK_C

CS0* CS1*

DM0 DM1 DM2 DM3

ODT

ZQ0 ZQ1

VREFCA VREFDQ

NU

NC

OMIT_TABLE

CRITICAL

1

C2301

0.1UF

10% 16V

2

X5R-CERM 0201

(1 OF 2)

EDFA232A1MA-GD-F

1

2

C2302

1UF

10% 10V X5R 402

DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31

DQS0_C DQS1_C DQS2_C DQS3_C

DQS0_T DQS1_T DQS2_T DQS3_T

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9

P9

N9 N10

N11

M8 M9

M10

M11 F11

F10 F9

F8

E11 E10

E9

D9 T8

T9

T10 T11

R8 R9

R10

R11 C11

C10

C9 C8

B11

B10 B9

B8

L11 G11

P11

D11

L10 G10

P10

D10

1

C2303

1UF

10% 10V

2

X5R 402

=MEM_A_DQ<0> =MEM_A_DQ<1> =MEM_A_DQ<2> =MEM_A_DQ<3> =MEM_A_DQ<4> =MEM_A_DQ<5> =MEM_A_DQ<6> =MEM_A_DQ<7> =MEM_A_DQ<8> =MEM_A_DQ<9> =MEM_A_DQ<10> =MEM_A_DQ<11> =MEM_A_DQ<12> =MEM_A_DQ<13> =MEM_A_DQ<14> =MEM_A_DQ<15> =MEM_A_DQ<16> =MEM_A_DQ<17> =MEM_A_DQ<18> =MEM_A_DQ<19> =MEM_A_DQ<20> =MEM_A_DQ<21> =MEM_A_DQ<22> =MEM_A_DQ<23> =MEM_A_DQ<24> =MEM_A_DQ<25> =MEM_A_DQ<26> =MEM_A_DQ<27> =MEM_A_DQ<28> =MEM_A_DQ<29> =MEM_A_DQ<30> =MEM_A_DQ<31>

=MEM_A_DQS_N<0> =MEM_A_DQS_N<1> =MEM_A_DQS_N<2> =MEM_A_DQS_N<3>

=MEM_A_DQS_P<0> =MEM_A_DQS_P<1> =MEM_A_DQS_P<2> =MEM_A_DQS_P<3>

1

C2304

1UF

10% 10V

2

X5R 402

1

C2305

1UF

2

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

1

C2306

10UF

10% 10V X5R 402

2

20% 25V X5R-CERM 0603

1

C2307

2

10UF

20% 25V X5R-CERM 0603

20 21 22 23 57 62

17 19 20 21 22 23 42 53 62 70

PP1V8_S3

PP1V2_S3

A3

A4 A5

A6

A10

U3

U4

U5 U6

U10

A8 A9

D4

D5 D6

G5

H5 H6

H12

J5

J6

K5 K6

K12

L5 P4

P5

P6 U8

U9

F2 G2

H3

L2 M2

A11

C12

E8 E12

G12

H8

H9

H11

J9

J10

K8 K11

L12

N8 N12

R12 U11

VDD1

VDD2

VDDCA

VDDQ

U2300

LPDDR3-16GB

FBGA

(2 OF 2)

OMIT_TABLE

CRITICAL

EDFA232A1MA-GD-F

VSS

VSSCA

VSSQ

B2

B5 C5

E4

E5 F5

J12

K2 L6

M5 N4

N5

R4 R5

T2

T3 T4

T5

H2

C3

D3

F4 G3

G4

P3 M4

J4

B6

B12 C6

D12 E6

F6

F12 G6

G9

H10 K10

L9

M6 M12

N6 P12

R6

T6 T12

D

C

B

PP1V2_S3

17 19 20 21 22 23 42 53 62 70

1

C2320

1UF

10% 10V

2

X5R 402

PP1V2_S3

17 19 20 21 22 23 42 53 62 70

1

C2310

1UF

A

PP1V8_S3

20 21 22 23 57 62

10% 10V

2

X5R 402

1

C2330

1UF

10% 10V

2

X5R 402

1

C2321

2

1

C2311

2

1

C2331

2

1UF

10% 10V X5R 402

1UF

10% 10V X5R 402

1UF

10% 10V X5R 402

1

2

1

2

1

2

C2322

1UF

10% 10V X5R 402

C2312

10UF

20% 25V X5R-CERM 0603

C2332

10UF

20% 25V X5R-CERM 0603

1

C2323

2

1

C2333

2

10UF

20% 25V X5R-CERM 0603

10UF

20% 25V X5R-CERM 0603

1

C2324

10UF

20% 25V

2

X5R-CERM 0603

PLACEMENT_NOTE:

10uF caps are shared between DRAM. Distribute evenly.

6 3

SYNC_MASTER=J41_MLB

PAGE TITLE

LPDDR3 DRAM Channel A (0-31)

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=02/06/2013

DRAWING NUMBER

<SCH_NUM>

REVISION

BRANCH

PAGE

23 OF 121

SHEET

20 OF 76

124578

SIZE

A

D

8 7 6 5 4 3

12

D

LPDDR3 CHANNEL A (32-63)

U2400

LPDDR3-16GB

FBGA

NC NC NC NC NC NC NC NC NC NC NC NC

NC NC NC

1

C2400

0.1UF

10% 16V

2

X5R-CERM 0201

R2

P2 N2

N3

M3 F3

E3

E2 D2

C2

K3 K4

J3

J2

L3

L4

L8 G8

P8 D8

J8

B3

B4

H4

J11

A1

A2 A12

A13

B1 B13

T1

T13

U1

U2

U12 U13

C4

K9

R3

MEM_A_CAB<0>

24 63 70

IN

MEM_A_CAB<1>

24 63 70

IN

MEM_A_CAB<2>

24 63 70

IN

MEM_A_CAB<3>

24 63 70

IN

MEM_A_CAB<4>

24 63 70

IN

MEM_A_CAB<5>

24 63 70

IN

MEM_A_CAB<6>

7

24 63 70

IN

MEM_A_CAB<7>

24 63 70

IN

MEM_A_CAB<8>

24 63 70

IN

MEM_A_CAB<9>

24 63 70

IN

MEM_A_CKE<2>

7

24 70

IN

MEM_A_CKE<3>

7

24 70

IN

MEM_A_CLK_P<1>

7

24 70

IN

MEM_A_CLK_N<1>

7

24 70

IN

MEM_A_CS_L<0>

7

20 24 70

C

R2400

1/20W

243

1

1%

MF

201

2

R2401

1/20W

243

1

1%

MF

201

2

C2440

0.047UF

1

C2441

10%

6.3V X5R 201

0.047UF

10%

6.3V

2

X5R 201

IN

MEM_A_CS_L<1>

7

20 24 70

IN

MEM_A_ODT<0>

7

20 24 63 70

IN

MEM_A_ZQ<2> MEM_A_ZQ<3>

PP0V6_S3_MEM_VREFCA_A

18 19 20 70

PP0V6_S3_MEM_VREFDQ_A

18 19 20 70

B

PP1V2_S3

17 19 20 21 22 23 42 53 62 70

CA0 CA1 CA2 CA3 CA4 CA5 CA6 CA7 CA8 CA9

CKE0 CKE1

CK_T CK_C

CS0* CS1*

DM0 DM1 DM2 DM3

ODT

ZQ0 ZQ1

VREFCA VREFDQ

NU

NC

OMIT_TABLE

CRITICAL

1

C2401

0.1UF

10% 16V

2

X5R-CERM 0201

(1 OF 2)

EDFA232A1MA-GD-F

1

2

C2402

1UF

10% 10V X5R 402

DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31

DQS0_C DQS1_C DQS2_C DQS3_C

DQS0_T DQS1_T DQS2_T DQS3_T

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9

P9

N9 N10

N11

M8 M9

M10

M11 F11

F10 F9

F8

E11 E10

E9

D9 T8

T9

T10 T11

R8 R9

R10

R11 C11

C10

C9 C8

B11

B10 B9

B8

L11 G11

P11

D11

L10 G10

P10

D10

1

C2403

1UF

10% 10V

2

X5R 402

=MEM_A_DQ<32> =MEM_A_DQ<33> =MEM_A_DQ<34> =MEM_A_DQ<35> =MEM_A_DQ<36> =MEM_A_DQ<37> =MEM_A_DQ<38> =MEM_A_DQ<39> =MEM_A_DQ<40> =MEM_A_DQ<41> =MEM_A_DQ<42> =MEM_A_DQ<43> =MEM_A_DQ<44> MEM_A_DQ<33> =MEM_A_DQ<46> =MEM_A_DQ<47> =MEM_A_DQ<48> =MEM_A_DQ<49> =MEM_A_DQ<50> =MEM_A_DQ<51> =MEM_A_DQ<52> =MEM_A_DQ<53> =MEM_A_DQ<54> =MEM_A_DQ<55> =MEM_A_DQ<56> =MEM_A_DQ<57> =MEM_A_DQ<58> =MEM_A_DQ<59> =MEM_A_DQ<60> =MEM_A_DQ<61> =MEM_A_DQ<62> =MEM_A_DQ<63>

=MEM_A_DQS_N<4> =MEM_A_DQS_N<5> MEM_A_DQS_N<6> =MEM_A_DQS_N<7>

=MEM_A_DQS_P<4> =MEM_A_DQS_P<5> MEM_A_DQS_P<6> =MEM_A_DQS_P<7>

1

C2404

1UF

10% 10V

2

X5R 402

1

C2405

1UF

2

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

7

63 70

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

7

63 70

BI

63

BI

63

BI

63

BI

7

63 70

BI

63

BI

1

C2406

10% 10V X5R 402

2

10UF

20% 25V X5R-CERM 0603

20 21 22 23 57 62

17 19 20 21 22 23 42 53 62 70

PP1V8_S3

PP1V2_S3

A3

A4 A5

A6

A10

U3

U4

U5 U6

U10

A8 A9

D4

D5 D6

G5

H5 H6

H12

J5

J6

K5 K6

K12

L5 P4

P5

P6 U8

U9

F2 G2

H3

L2 M2

A11

C12

E8 E12

G12

H8

H9

H11

J9

J10

K8 K11

L12

N8 N12

R12 U11

VDD1

VDD2

VDDCA

VDDQ

U2400

LPDDR3-16GB

FBGA

(2 OF 2)

OMIT_TABLE

CRITICAL

EDFA232A1MA-GD-F

VSS

VSSCA

VSSQ

B2

B5 C5

E4

E5 F5

J12

K2 L6

M5 N4

N5

R4 R5

T2

T3 T4

T5

H2

C3

D3

F4 G3

G4

P3 M4

J4

B6

B12 C6

D12 E6

F6

F12 G6

G9

H10 K10

L9

M6 M12

N6 P12

R6

T6 T12

D

C

B

PP1V2_S3

17 19 20 21 22 23 42 53 62 70

1

C2420

1UF

10% 10V

2

X5R 402

PP1V2_S3

17 19 20 21 22 23 42 53 62 70

1

C2410

1UF

A

PP1V8_S3

20 21 22 23 57 62

10% 10V

2

X5R 402

1

C2430

1UF

10% 10V

2

X5R 402

1

C2421

2

1

C2411

2

1

C2431

2

1UF

10% 10V X5R 402

1UF

10% 10V X5R 402

1UF

10% 10V X5R 402

1

2

1

2

1

2

C2422

1UF

10% 10V X5R 402

C2412

10UF

20% 25V X5R-CERM 0603

C2432

10UF

20% 25V X5R-CERM 0603

6 3

1

C2423

2

10UF

20% 25V X5R-CERM 0603

PLACEMENT_NOTE:

10uF caps are shared between DRAM. Distribute evenly.

SYNC_MASTER=J41_MLB

PAGE TITLE

LPDDR3 DRAM Channel A (32-63)

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=02/06/2013

DRAWING NUMBER

<SCH_NUM>

REVISION

BRANCH

PAGE

24 OF 121

SHEET

21 OF 76

124578

SIZE

A

D

8 7 6 5 4 3

12

D

LPDDR3 CHANNEL B (0-31)

U2500

LPDDR3-16GB

FBGA

NC NC NC NC NC NC NC NC NC NC NC NC

NC NC NC

1

C2500

0.1UF

10% 16V

2

X5R-CERM 0201

R2

P2 N2

N3

M3 F3

E3

E2 D2

C2

K3 K4

J3

J2

L3

L4

L8 G8

P8 D8

J8

B3

B4

H4

J11

A1

A2 A12

A13

B1 B13

T1

T13

U1

U2

U12 U13

C4

K9

R3

MEM_B_CAA<0>

24 63 70

IN

MEM_B_CAA<1>

24 63 70

IN

MEM_B_CAA<2>

24 63 70

IN

MEM_B_CAA<3>

24 63 70

IN

MEM_B_CAA<4>

24 63 70

IN

MEM_B_CAA<5>

24 63 70

IN

MEM_B_CAA<6>

7

24 63 70

IN

MEM_B_CAA<7>

24 63 70

IN

MEM_B_CAA<8>

24 63 70

IN

MEM_B_CAA<9>

24 63 70

IN

MEM_B_CKE<0>

7

24 70

IN

MEM_B_CKE<1>

7

24 70

IN

MEM_B_CLK_P<0>

7

24 70

IN

MEM_B_CLK_N<0>

7

24 70

IN

MEM_B_CS_L<0>

7

23 24 70

C

R2500

1/20W

243

1

1%

MF

201

2

R2501

1/20W

243

1

1%

MF

201

2

C2540

0.047UF

1

C2541

10%

6.3V X5R 201

0.047UF

10%

6.3V

2

X5R 201

IN

MEM_B_CS_L<1>

7

23 24 70

IN

MEM_B_ODT<0>

7

23 24 63 70

IN

MEM_B_ZQ<0> MEM_B_ZQ<1>

PP0V6_S3_MEM_VREFCA_B

18 19 23 70

PP0V6_S3_MEM_VREFDQ_B

18 19 23 70

B

PP1V2_S3

17 19 20 21 22 23 42 53 62 70

CA0 CA1 CA2 CA3 CA4 CA5 CA6 CA7 CA8 CA9

CKE0 CKE1

CK_T CK_C

CS0* CS1*

DM0 DM1 DM2 DM3

ODT

ZQ0 ZQ1

VREFCA VREFDQ

NU

NC

OMIT_TABLE

CRITICAL

1

C2501

0.1UF

10% 16V

2

X5R-CERM 0201

(1 OF 2)

EDFA232A1MA-GD-F

1

2

C2502

1UF

10% 10V X5R 402

DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31

DQS0_C DQS1_C DQS2_C DQS3_C

DQS0_T DQS1_T DQS2_T DQS3_T

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9

P9

N9 N10

N11

M8 M9

M10

M11 F11

F10 F9

F8

E11 E10

E9

D9 T8

T9

T10 T11

R8 R9

R10

R11 C11

C10

C9 C8

B11

B10 B9

B8

L11 G11

P11

D11

L10 G10

P10

D10

1

C2503

1UF

10% 10V

2

X5R 402

=MEM_B_DQ<0> =MEM_B_DQ<1> =MEM_B_DQ<2> =MEM_B_DQ<3> =MEM_B_DQ<4> =MEM_B_DQ<5> =MEM_B_DQ<6> =MEM_B_DQ<7> =MEM_B_DQ<8> =MEM_B_DQ<9> =MEM_B_DQ<10> =MEM_B_DQ<11> =MEM_B_DQ<12> =MEM_B_DQ<13> =MEM_B_DQ<14> =MEM_B_DQ<15> =MEM_B_DQ<16> =MEM_B_DQ<17> =MEM_B_DQ<18> =MEM_B_DQ<19> =MEM_B_DQ<20> =MEM_B_DQ<21> =MEM_B_DQ<22> =MEM_B_DQ<23> =MEM_B_DQ<24> =MEM_B_DQ<25> =MEM_B_DQ<26> =MEM_B_DQ<27> =MEM_B_DQ<28> =MEM_B_DQ<29> =MEM_B_DQ<30> =MEM_B_DQ<31>

=MEM_B_DQS_N<0> =MEM_B_DQS_N<1> =MEM_B_DQS_N<2> =MEM_B_DQS_N<3>

=MEM_B_DQS_P<0> =MEM_B_DQS_P<1> =MEM_B_DQS_P<2> =MEM_B_DQS_P<3>

1

C2504

1UF

10% 10V

2

X5R 402

1

C2505

1UF

2

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

1

C2506

10% 10V X5R 402

2

10UF

20% 25V X5R-CERM 0603

20 21 22 23 57 62

17 19 20 21 22 23 42 53 62 70

PP1V8_S3

PP1V2_S3

A3

A4 A5

A6

A10

U3

U4

U5 U6

U10

A8 A9

D4

D5 D6

G5

H5 H6

H12

J5

J6

K5 K6

K12

L5 P4

P5

P6 U8

U9

F2 G2

H3

L2 M2

A11

C12

E8 E12

G12

H8

H9

H11

J9

J10

K8 K11

L12

N8 N12

R12 U11

VDD1

VDD2

VDDCA

VDDQ

U2500

LPDDR3-16GB

FBGA

(2 OF 2)

OMIT_TABLE

CRITICAL

EDFA232A1MA-GD-F

VSS

VSSCA

VSSQ

B2

B5 C5

E4

E5 F5

J12

K2 L6

M5 N4

N5

R4 R5

T2

T3 T4

T5

H2

C3

D3

F4 G3

G4

P3 M4

J4

B6

B12 C6

D12 E6

F6

F12 G6

G9

H10 K10

L9

M6 M12

N6 P12

R6

T6 T12

D

C

B

PP1V2_S3

17 19 20 21 22 23 42 53 62 70

1

C2520

1UF

10% 10V

2

X5R 402

PP1V2_S3

17 19 20 21 22 23 42 53 62 70

1

C2510

1UF

A

PP1V8_S3

20 21 22 23 57 62

10% 10V

2

X5R 402

1

C2530

1UF

10% 10V

2

X5R 402

1

C2521

2

1

C2511

2

1

C2531

2

1UF

10% 10V X5R 402

1UF

10% 10V X5R 402

1UF

10% 10V X5R 402

1

2

1

2

1

2

C2522

1UF

10% 10V X5R 402

C2512

10UF

20% 25V X5R-CERM 0603

C2532

10UF

20% 25V X5R-CERM 0603

6 3

1

C2523

2

10UF

20% 25V X5R-CERM 0603

PLACEMENT_NOTE:

10uF caps are shared between DRAM. Distribute evenly.

SYNC_MASTER=J41_MLB

PAGE TITLE

LPDDR3 DRAM Channel B (0-31)

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=02/06/2013

DRAWING NUMBER

<SCH_NUM>

REVISION

BRANCH

PAGE

25 OF 121

SHEET

22 OF 76

124578

SIZE

A

D

8 7 6 5 4 3

12

D

LPDDR3 CHANNEL B (32-63)

U2600

LPDDR3-16GB

FBGA

NC NC NC NC NC NC NC NC NC NC NC NC

NC NC NC

1

C2600

0.1UF

10% 16V

2

X5R-CERM 0201

R2

P2 N2

N3

M3 F3

E3

E2 D2

C2

K3 K4

J3

J2

L3

L4

L8 G8

P8 D8

J8

B3

B4

H4

J11

A1

A2 A12

A13

B1 B13

T1

T13

U1

U2

U12 U13

C4

K9

R3

MEM_B_CAB<0>

24 63 70

IN

MEM_B_CAB<1>

24 63 70

IN

MEM_B_CAB<2>

24 63 70

IN

MEM_B_CAB<3>

24 63 70

IN

MEM_B_CAB<4>

24 63 70

IN

MEM_B_CAB<5>

24 63 70

IN

MEM_B_CAB<6>

7

24 63 70

IN

MEM_B_CAB<7>

24 63 70

IN

MEM_B_CAB<8>

24 63 70

IN

MEM_B_CAB<9>

24 63 70

IN

MEM_B_CKE<2>

7

24 70

IN

MEM_B_CKE<3>

7

24 70

IN

MEM_B_CLK_P<1>

7

24 70

IN

MEM_B_CLK_N<1>

7

24 70

IN

MEM_B_CS_L<0>

7

22 24 70

C

R2600

1/20W

243

1

1%

MF

201

2

R2601

1/20W

243

1

1%

MF

201

2

C2640

0.047UF

1

C2641

10%

6.3V X5R 201

0.047UF

10%

6.3V

2

X5R 201

IN

MEM_B_CS_L<1>

7

22 24 70

IN

MEM_B_ODT<0>

7

22 24 63 70

IN

MEM_B_ZQ<2> MEM_B_ZQ<3>

PP0V6_S3_MEM_VREFCA_B

18 19 22 70

PP0V6_S3_MEM_VREFDQ_B

18 19 22 70

B

PP1V2_S3

17 19 20 21 22 23 42 53 62 70

CA0 CA1 CA2 CA3 CA4 CA5 CA6 CA7 CA8 CA9

CKE0 CKE1

CK_T CK_C

CS0* CS1*

DM0 DM1 DM2 DM3

ODT

ZQ0 ZQ1

VREFCA VREFDQ

NU

NC

OMIT_TABLE

CRITICAL

1

C2601

0.1UF

10% 16V

2

X5R-CERM 0201

(1 OF 2)

EDFA232A1MA-GD-F

1

2

C2602

1UF

10% 10V X5R 402

DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31

DQS0_C DQS1_C DQS2_C DQS3_C

DQS0_T DQS1_T DQS2_T DQS3_T

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9

P9

N9 N10

N11

M8 M9

M10

M11 F11

F10 F9

F8

E11 E10

E9

D9 T8

T9

T10 T11

R8 R9

R10

R11 C11

C10

C9 C8

B11

B10 B9

B8

L11 G11

P11

D11

L10 G10

P10

D10

1

C2603

1UF

10% 10V

2

X5R 402

=MEM_B_DQ<32> =MEM_B_DQ<33> =MEM_B_DQ<34> =MEM_B_DQ<35> =MEM_B_DQ<36> =MEM_B_DQ<37> =MEM_B_DQ<38> =MEM_B_DQ<39> MEM_B_DQ<32> =MEM_B_DQ<41> =MEM_B_DQ<42> =MEM_B_DQ<43> =MEM_B_DQ<44> =MEM_B_DQ<45> =MEM_B_DQ<46> =MEM_B_DQ<47> =MEM_B_DQ<48> =MEM_B_DQ<49> =MEM_B_DQ<50> =MEM_B_DQ<51> =MEM_B_DQ<52> =MEM_B_DQ<53> =MEM_B_DQ<54> =MEM_B_DQ<55> =MEM_B_DQ<56> =MEM_B_DQ<57> =MEM_B_DQ<58> =MEM_B_DQ<59> =MEM_B_DQ<60> =MEM_B_DQ<61> =MEM_B_DQ<62> =MEM_B_DQ<63>

=MEM_B_DQS_N<4> =MEM_B_DQS_N<5> =MEM_B_DQS_N<6> MEM_B_DQS_N<6>

=MEM_B_DQS_P<4> =MEM_B_DQS_P<5> =MEM_B_DQS_P<6> MEM_B_DQS_P<6>

1

C2604

1UF

10% 10V

2

X5R 402

1

C2605

1UF

2

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

7

63 70

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

63

BI

7

63 70

BI

63

BI

63

BI

63

BI

7

63 70

BI

1

C2606

10% 10V X5R 402

2

10UF

20% 25V X5R-CERM 0603

20 21 22 23 57 62

17 19 20 21 22 23 42 53 62 70

PP1V8_S3

PP1V2_S3

A3

A4 A5

A6

A10

U3

U4

U5 U6

U10

A8 A9

D4

D5 D6

G5

H5 H6

H12

J5

J6

K5 K6

K12

L5 P4

P5

P6 U8

U9

F2 G2

H3

L2 M2

A11

C12

E8 E12

G12

H8

H9

H11

J9

J10

K8 K11

L12

N8 N12

R12 U11

VDD1

VDD2

VDDCA

VDDQ

U2600

LPDDR3-16GB

FBGA

(2 OF 2)

OMIT_TABLE

CRITICAL

EDFA232A1MA-GD-F

VSS

VSSCA

VSSQ

B2

B5 C5

E4

E5 F5

J12

K2 L6

M5 N4

N5

R4 R5

T2

T3 T4

T5

H2

C3

D3

F4 G3

G4

P3 M4

J4

B6

B12 C6

D12 E6

F6

F12 G6

G9

H10 K10

L9

M6 M12

N6 P12

R6

T6 T12

D

C

B

PP1V2_S3

17 19 20 21 22 23 42 53 62 70

1

C2620

1UF

10% 10V

2

X5R 402

PP1V2_S3

17 19 20 21 22 23 42 53 62 70

1

C2610

1UF

A

PP1V8_S3

20 21 22 23 57 62

10% 10V

2

X5R 402

1

C2630

1UF

10% 10V

2

X5R 402

1

C2621

2

1

C2611

2

1

C2631

2

1UF

10% 10V X5R 402

1UF

10% 10V X5R 402

1UF

10% 10V X5R 402

1

2

1

2

C2622

1UF

10% 10V X5R 402

C2632

10UF

20% 25V X5R-CERM 0603

6 3

1

C2623

2

10UF

20% 25V X5R-CERM 0603

PLACEMENT_NOTE:

10uF caps are shared between DRAM. Distribute evenly.

SYNC_MASTER=J41_MLB

PAGE TITLE

LPDDR3 DRAM Channel B (32-63)

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=02/06/2013

DRAWING NUMBER

<SCH_NUM>

REVISION

BRANCH

PAGE

26 OF 121

SHEET

23 OF 76

124578

SIZE

A

D