Apple Axtena Schematics
<XR_PAGE_TITLE>
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.
2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.
78
6
5
4
3
ECN
ZONE
01
REV
279015
DESCRIPTION OF CHANGE
ENGINEERING RELEASED
12
CK
APPD
DATE
06/06/03
ENG
APPD
?
DATE
Schematic,MLB,"Axtena"
D
PAGE
COVER PAGE
1
2,3
4,5
6,7
10-11
12
13
14-15
16
C
17
18
19
20-21
22-23
24-25
26-27
28
29
30
31
32
33
B
34
35
36
37
38
39
40-41
42-43
44
45-51
52-59
60-64
A
65-69
8
BLOCK DIAGRAM, SYSTEM, POWER & PCB INFO
MPC7450 MAXBUS
CPU SPEED & CONFIG OPTIONS
CPU LA CONNECTORS, ESP, CPU BYPASS
8
INTREPID MAX IF (SECTION 1)
9
INTREPID POWER & BYPASS (SECTION 8 & 9)
INTREPID DDR CONTROL
DDR MUXES
SO-DIMM, BIG DIMM
INTREPID AGP (SECTION 3)
NVIDIA AGP (SECTION 1)
NVIDIA FRAME BUFFER (SECTIONS 3 & 4)
NVIDIA FB SERIES TERMS, CLK DELAYS
GRAPHICS MEMORIES
NVIDIA DAC/DVI, CLOCKS & STRAPS (SECTIONS 2 & 5)
TMDS & EXTERNAL VGA CONNECTORS
NVIDIA POWER-ON RESET CONFIGURATION STRAPS
INTREPID GPIOS, INTERRUPTS & SERIAL PORTS (SECTION 6)
MODEM, BLUETOOTH, KITCHEN SINK & SERIAL DOWNLOAD
INTREPID PCI, ROM (SECTION 7)
WIRELESS PCI
USB2 CONTROLLER
USB POWER & CONNECTORS
INTREPID ETHERNET & FIREWIRE (SECTION 4)
ETHERNET PHY
FIREWIRE PHY
INTREPID UATA/IDE (SECTION 5)
ATA CD/HD CONNECTORS
AUDIO CODEC & VOLTAGE REGS
LINE IN/OUT BUFFERS
SPEAKER/MIC AMPS
POWER MANAGER UNIT
+5V/+12V, AUDIO, FW & TMDS POWER CONVERTERS
CONSTRAINT TABLES
NET TABLES
PART TABLES
TABLE OF CONTENTS
67
POWER RAIL DEFINITIONS
RUN
+2_5V_MAIN
+3V_MAIN
+5V_MAIN
+5V_SLEEP
+12V_MAIN
+12V_SLEEP
FW_PWR
+1.8V_SLEEP
+MAXBUS_SLEEP
PCB,UL RECOGNIZED, MIN.130 DEG. C TEMP. RATING AND V-0 FLAME RATING PER UL 796
& UL 94. PCB TO BE SILK-SCREENED WITH UL/CUL RECOGNITION MARK, MANUFACTURER’S UL
FILE NUMBER, UL PCB MATERIAL DESIGNATION, TEMPERATURE RATING AND FLAME RATING.
DIMENSIONS ARE IN MILLIMETERS
XX
X.XX
X.XXX
ANGLES
DO NOT SCALE DRAWING
THIRD ANGLE PROJECTION
5
4
3
ON
ON
ON
ON
ON
ON
ON
ON
ON
SLEEP
DRAFTER
ENG APPD
QA APPD
RELEASE
ON
ON
ON
OFF
ON
OFF
ON
OFF
OFF
MATERIAL/FINISH
NOTED AS
APPLICABLE
Sep 17 12:11:39 2003
SHUTDOWN
OFF
OFF
OFF
OFF
ON
OFF
OFF
OFF
OFF
METRIC
DESIGN CK
MFG APPD
DESIGNER
SCALE
NONE
SIZE
2
TITLE
DRAWING NUMBER
D
Apple Computer Inc.
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SCHEMATIC,MLB
051-6497
D
C
B
A
REV.
13
SHT
1
OF
1
69
DRAWING
<XR_PAGE_TITLE>
78
6
5
4
3
12
FW - B
Connector
Inverter
KITCHEN
D
LCD Panel
Connector
P.24P.29P.36
VGA/SVIDEO OUT
VGA
D
Connector
P.25
RGB
GRAPHICS
MEMORY
P.20
(EXTERNAL MEM)
FW - A
Connector
Connector
P.36 P.35
Ethernet
TMDS
EDID (I2C)
NVIDIA
NV18B
GRAPHICS
FireWire
PHY
Ethernet
PHY
64MB
P.17-27
P.35P.36
C
1394 OHCI
3.3V
8BIT TX/RX
AGP BUS
1.5V/3.3V
32BITS
66MHZ
USB
CONN(QTY3)
P.31
FIREWIRE
400 MB/S
P.34
ETHERNET
10/100
P.34
4X AGP
P.16
PCI
P.30
MEMORY
P.21
(EXTERNAL MEM)
PCI BUS
WIRELESS
P.31
32BITS
C
USB2
CONTROL
P.32
MODEM
B
BLUETOOTH
P.29
USB
P.28
INTREPID
DDR MEMORY
MEMORY BUS
2.5V
167MHZ
64BITS
I2C
P.34P.12
I2C
MAXBUS
P.9
MAXBUS
167MHZ
32BIT ADDRESS
64BIT DATA
BOOTROM
P.30
BOOT ROM
1M X 8
P.30
B
PMU
P.44
CPU PLL
DDR MUXES
APOLLO
Config
P.6
P.13
CPU
P.4-5
A
DDR SDRAM DIMM 0
P.15
DDR SDRAM DIMM 1
LAST_MODIFIED=Wed Sep 17 12:11:39 2003
SO-DIMM Connector
P.14
APPLE COMPUTER INC.
8
67
5
4
3
2
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SYSTEM BLOCK
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
SIZE
DRAWING NUMBER
D
051-6497
NONE
SHT
2
1
SCALE
A
REV.
13
OF
69
DRAWING
<XR_PAGE_TITLE>
78
6
5
4
3
12
LAYER
DUAL
+12V
D
DC/DC
(LTC3707)
FW
(SWITCH)
C
GRAPHIC
DC/DC
(SC2602)
5.1V
3.3V
12V
1.6V
TMDS
LDO
(EZ1582)
USB
(SWITCH)
EXTERNAL
VIDEO
(SWITCH)
HARD
DRIVE
(SWITCH)
3.65V
5.1V
5.1V
5.1V
----------------
1 - SIGNAL-TOP
PREPREG
2 - GROUND1
PREPREG
3 - SIGNAL
FILLER
4 - POWER
PREPREG
5 - POWER
FILLER
6 - SIGNAL
PREPREG
7 - GROUND2
PREPREG
8 - SIGNAL-BOTTOM
================
TOTAL
NOSTUFF
ZT39
HOLE-VIA-20R10
1
NOSTUFF
ZT46
HOLE-VIA-20R10
THICKNESS COPPER
(MILS)
------------
0.7
3
1.4
3
0.7
17.4
2.8
4
2.8
17.4
0.7
3
1.4
3
0.7
============
62.0
NOSTUFF
ZT53
1
HOLE-VIA-20R10
1
(OZ)
--------
0.5
--Â1
---
0.5
--Â2
---
2
---
0.5
--Â1
---
0.5
========
---
NOSTUFF
ZT59
HOLE-VIA-20R10
1
TRACE WIDTH
(MILS)
-------------Â4
---
4
---
---
4
---
4
=============
---
NOSTUFF
ZT64
HOLE-VIA-20R10
1
D
C
CPU
DC/DC
1.55V
(LTC3707)
B
BACKLIGHT
INVERTER
600V RMS
(OZ960)
DDR
DC/DC
2.5V
A
(SC2602)
POWER SYSTEM ARCHITECTURE
8
67
3.3V
OPTICAL
DRIVE
(SWITCH)
INTREPID
DC/DC
(SC2602)
MAXBUS I/O
LDO
(EZ1582)
AGP
LDO
(EZ1582)
5
5.1V
1.7V
1.8V
1.5V
NOSTUFF
ZT40
HOLE-VIA-20R10
1
NOSTUFF
ZT41
HOLE-VIA-20R10
1
NOSTUFF
ZT42
HOLE-VIA-20R10
1
NOSTUFF
ZT43
HOLE-VIA-20R10
1
NOSTUFF
ZT44
HOLE-VIA-20R10
1
NOSTUFF
ZT45
HOLE-VIA-20R10
1
4
NOSTUFF
ZT47
HOLE-VIA-20R10
1
NOSTUFF
ZT48
HOLE-VIA-20R10
1
NOSTUFF
ZT49
HOLE-VIA-20R10
1
NOSTUFF
ZT50
HOLE-VIA-20R10
1
NOSTUFF
ZT51
1
NOSTUFF
ZT52
HOLE-VIA-20R10
1
3
NOSTUFF
ZT54
HOLE-VIA-20R10
1
NOSTUFF
ZT55
HOLE-VIA-20R10
1
NOSTUFF
ZT56
HOLE-VIA-20R10
1
NOSTUFF
ZT57
HOLE-VIA-20R10
1
NOSTUFF
ZT58
HOLE-VIA-20R10HOLE-VIA-20R10
1
NOSTUFF
ZT60
HOLE-VIA-20R10
1
NOSTUFF
ZT61
HOLE-VIA-20R10
1
NOSTUFF
ZT62
HOLE-VIA-20R10
1
NOSTUFF
ZT63
HOLE-VIA-20R10
1
PWR BLOCK,PCB INFO
LAST_MODIFIED=Wed Sep 17 12:15:39 2003
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
APPLE COMPUTER INC.
2
NOSTUFF
ZT65
HOLE-VIA-20R10
1
NOSTUFF
ZT66
HOLE-VIA-20R10
1
NOSTUFF
ZT67
HOLE-VIA-20R10
1
NOSTUFF
ZT68
HOLE-VIA-20R10
1
NOTICE OF PROPRIETARY PROPERTY
SIZE
DRAWING NUMBER
D
051-6497
NONE
SHT
3
SCALE
1
B
A
REV.
13
OF
69
DRAWING
<XR_PAGE_TITLE>
78
6
5
4
3
12
CPU INTERNAL PLL FILTERING
C1036
0.1UF
20%
10V
CERM
402
7C4<
8B8<>
7A5<
8A3<>
7A5<
7D5<
7B5<
7B4<
7C4<
8C4<>
8B5<>
9A3<>
44C4<>
7A5<
7A3<
7C5<
7A4<
7A4<
7A5<
6C6<
6C6<
6C6<
6C6<
6C6<
56C3>
9A1<>
9A1<>
9A1<>
7C5<
8B7<>
9B3<>
7B5<
7A5<
4D7<>
1
2
8A8<>
8A8<>
8A8<>
8A8<>
8A8<>
9B1<>
8A3<>
59C8>
8A3<>
8A3<>
9A1<>
9A1<>
7B5<
8D7<>
8A3<>
7A5<
7C5<
1
2
56C3>
56C3>
56C3>
8A3<>
9B3<
56C3>
59C8>
8A3<>
7B3<
B4
C2
C12D5E18F2G18
+MAXBUS_SLEEP
K2L5M3N6P2
H3
J5
59D8>
59B6>
52C6>
45D2<>
8C1<
D
8B7<
4D3<
CPU_VCORE_SLEEP
R891
470
1/16W
1
5%
MF
402
2
K12
K14
L11
L13M8M10
H10
H12
J11
H8
J13K8K10
J7
J9
L7
L9
M12
VDD
9D3<
9D3<>
9D3<>
9C3<>
9C3<>
9C3<>
9C3<>
9C3<>
9C3<>
9C3<>
9C3<>
9C3<>
9C3<>
9C3<>
9C3<>
9C3<>
9C3<>
9C3<>
9C3<>
9C3<>
9C3<>
9C3<>
9C3<>
9C3<>
9C3<>
9B3<>
9B3<>
9B3<>
9B3<>
9B3<>
9B3<>
9B3<>
9C3<>
9B3<>
9B3<
7C5<
9D3<>
9D3<>
9D3<>
9D3<>
9D3<>
9D3<>
9D3<>
9D3<>
9D3<>
9C3<>
9B3<>
9B3<>
9B3<>
8B8<>
8B4<>
8B4<>
8B7<>
8B8<>
8C4<>
8B7<>
8B8<>
8B7<>
8B7<>
8B8<>
8B8<>
8C8<>
8B7<>
8B8<>
8C7<>
8C7<>
8C8<>
8B7<>
8B8<>
8C8<>
8C8<>
8C7<>
8C8<>
8C7<>
8C7<>
8B4<>
8B5<>
8B4<>
8B5<>
8B4<>
8B4<>
8B5<>
8C5<>
8B5<>
8B8<>
4A3<
8B4<>
8B5<>
8B4<>
8B8<>
8B5<>
8B7<>
8C4<>
8B7<>
8C5<>
8B8<>
8B5<>
8B5<>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56C3>
56C3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56C3>
56C3>
56C3>
56D3>
9B3<>
C
B
INT_V2
R311
0
9C3<>
CPU_INT_GBL_L
7B7<
56C3>
56C3>
8B5<>
CPU_GBL_L
1 2
5%
1/16W
MF
402
INT_V1
1
R312
100
2
1%
1/16W
MF
402
7C7<
7B7<
7C7<
CPU_PULLDOWN
CPU_ADDR<0>
CPU_ADDR<1>
CPU_ADDR<2>
CPU_ADDR<3>
CPU_ADDR<4>
CPU_ADDR<5>
CPU_ADDR<6>
CPU_ADDR<7>
CPU_ADDR<8>
CPU_ADDR<9>
CPU_ADDR<10>
CPU_ADDR<11>
CPU_ADDR<12>
CPU_ADDR<13>
CPU_ADDR<14>
CPU_ADDR<15>
CPU_ADDR<16>
CPU_ADDR<17>
CPU_ADDR<18>
CPU_ADDR<19>
CPU_ADDR<20>
CPU_ADDR<21>
CPU_ADDR<22>
CPU_ADDR<23>
CPU_ADDR<24>
CPU_ADDR<25>
CPU_ADDR<26>
CPU_ADDR<27>
CPU_ADDR<28>
CPU_ADDR<29>
CPU_ADDR<30>
CPU_ADDR<31>
NC_CPUAP<0>
NC_CPUAP<1>
NC_CPUAP<2>
NC_CPUAP<3>
NC_CPUAP<4>
CPU_TT<0>
7A7<
CPU_TT<1>
7A7<
CPU_TT<2>
7A7<
CPU_TT<3>
7A7<
CPU_TT<4>
7A7<
CPU_TBST_L
7B7<
CPU_TSIZ<0>
CPU_TSIZ<1>
CPU_TSIZ<2>
8B7<
7A7<
7A7<
CPU_AACK_L
7B7<
CPU_ARTRY_L
7C7<
CPU_SHD0_L
7B5<
CPU_SHD1_L
7B5<
CPU_HIT_L
7C7<
CPU_BR_L
CPU_BG_L
CPU_TS_L
CPU_WT_L
CPU_CI_L
D2 B7
BR*
M1
BG*
L4
TS*
E11
A0
H1
A1
C11
A2
G3
A3
F10
A4
L2
A5
D11
A6
D1
A7
C10
A8
G2
A9
D12
A10
L3
A11
G4
A12
T2
A13
F4
A14
V1
A15
J4
A16
R2
A17
K5
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST
A18
W2
A19
J2
A20
K4
A21
N4
A22
J3
A23
M5
A24
P5
A25
N3
A26
T1
A27
V2
A28
U1
A29
N5
A30
W1
A31
B12
A32
C4
A33
G10
A34
B11
A35
C1
AP0
E3
AP1
H6
AP2
F5
AP3
G7
AP4
E5
TT0
E6
TT1
F6
TT2
E9
TT3
C5
TT4
F11
TBST*
G6
TSIZ0
F7
TSIZ1
E7
TSIZ2
E2
GBL*
D3
WT*
J1
CI*
R1
AACK*
N2
ARTRY*
E4
SHD0*
H5
SHD1*
B2
HIT*
APOLLO_MPC7445_360
U34
800MHZ
BGA
(1 OF 3)
SEE_TABLE
6C5<
P8
OVDD
6D6<
9D8< 9B7<
7A3<
P11R4R13
R16
7B3<
T6T9U2
7C3<
U12
7C5<
44D2< 44D1< 44B7<
U16
45D2<>
V4
V7
7C7<
V10
8A3<>
V14
AVDD
BVSEL
SYSCLK
CLKOUT
PLLCFG0
PLLCFG1
PLLCFG2
PLLCFG3
PLL_EXT
DRDY*
TRST*
LSSDMODE*
L1TSTCLK
L2TSTCLK
QREQ*
QACK*
CKSTP_IN*
CKSTP_OUT*
SRESET*
HRESET*
PMON_IN*
PMON_OUT*
BMODE0*
BMODE1*
EXT_QUAL
TEST0
TEST1
TEST2
TEST3
TEST4
8D4< 8D1<
59C8> 52C6> 46D4<
CPU_AVDD
52C6>
1
A8
2
CPU_BUS_VSEL
A10
NO_TEST
H2
B8
C8
C7
D7
A7
M2
DBG*
R3
G1
DTI0
K1
DTI1
P1
DTI2
N1
DTI3
B9
TDI
A4
TDO
F1
TMS
C6
TCK
A5
E8
G8
B3
K6
TA*
L1
TEA*
E1
TBEN
P4
G5
A3
B1
D4
INT*
F9
SMI*
C9
MCP*
A2
D8
IBORG PULLS THIS UP, SPEC SAYS TO GROUND IT FOR SW CONTROL
D9
A9
G9
F8
A11
A12
B6
B10
E10
D10
NC_CPU_CLKOUT
CPU_PLL_CFG<0>
CPU_PLL_CFG<1>
CPU_PLL_CFG<2>
CPU_PLL_CFG<3>
CPU_PLL_CFGEXT
CPU_DBG_L
CPU_DRDY_L_UF
CPU_EDTI
CPU_DTI<0>
CPU_DTI<1>
CPU_DTI<2>
JTAG_CPU_TDI
JTAG_CPU_TDO
JTAG_CPU_TMS
JTAG_CPU_TCK
JTAG_CPU_TRST_L
CPU_LSSD_MODE
CPU_L1TSTCLK
CPU_L2TSTCLK
CPU_TA_L
CPU_TEA_L
CPU_TBEN
CPU_QREQ_L
CPU_QACK_L
CPU_CHKSTP_IN_L
CPU_CHKSTP_OUT_L
MPIC_CPU_INT_L
CPU_SMI_L
CPU_MCP_L
CPU_SRESET_L
CPU_HRESET_L
CPU_PMONIN_L
NO_TEST
NC_PMON_OUT_L
CPU_EMODE0_L
CPU_EMODE1_L
CPU_PULLUP
CPU_PULLDOWN
7B7<
7C5<
7C7<
7B7<
7C5<
7A5<
7B5<
8B7<>
8B4<>
8B4<>
7D5<
8B4<>
R901
10
1%
1/16W
MF
603
C1035
2.2UF
N20P80%
16V
CERM
805
56C3>
59C8>
59C8>
59C8>
56C3>
56C3>
59C6>
59C8>
56C3>
8D5<>
28B5>
8A3<>
CPU_VCORE_SLEEP
NOSTUFF
1
R895
47
5%
1/16W
MF
402
2
R850
0
1 2
5%
1/16W
MF
402
59C8>
59C8>
44D2<
44C2<
52C6>
45D2<>
8C1<
8B7<
4D7<
SYSCLK_CPU
RC GLITCH FILTER
PLACE CLOSE TO PIN
CPU_DRDY_L
NOSTUFF
1
C954
10PF
5%
50V
2
CERM
402
FILTERS A WAKE FROM SLEEP GLITCH
IF NECESSARY
ZH4
275R138
1
ZT9P1
ZH6
TH
SL-138X272-292
1
ZT10P1
59B6>
9A4<
7B7<
1
2
1
2
56C3>
8B5<>
C352
0.1UF
20%
10V
CERM
402
C369
0.1UF
20%
10V
CERM
402
59D8>
9B1<
56C3>
ZH5
TH
SL-138X272-292
ZH7
275R138
1
1
ZT11P1
ZT8P1
1
2
1
2
C345
0.1UF
20%
10V
CERM
402
C370
0.1UF
20%
10V
CERM
402
D
C
B
GND
INTREPID VERSION 1 PULLS GBL
ALL THE TIME. NEED TO
B5
C3
D13
E17F3G17
H9
J6
J8
H4
H7
H11
H13
K7K3K9
J10
J12
L6
L8
K11
K13
M4M7M9
L10
L12
M11D6M13
N7P3P9
P12R5R14
R17T7T10
U3
V5
V8
U13
U17
V11
V15
CUT THE TRACE AND YANK
A
FIXED IN INTREPID VERSION 2.
CPU MECHANICAL PARTS SUPPORT
DESCRIPTION REFERENCE DES BOM OPTIONQTYPART NUMBER CRITICAL
DOWN HARD FOR SNOOPING.
875-1475
870-1113
412-0042
835-0251
8
67
1
PAD,THERMAL,CPU,U34
1
HEAT SINK,CPU,Q26,U34
1
CLIP,HEAT SINK,CPU,Q26.U34
1
SCREW,MACH,3MM W,8MM L,U34
1
5
U341
U343870-1114
U344
?
?
?
?
?
DEVU342
DEV
DEV
DEVU345NUT,3MM,U34
4
3
APPLE COMPUTER INC.
2
MPC7450 MAXBUS
NOTICE OF PROPRIETARY PROPERTY
LAST_MODIFIED=Wed Sep 17 12:15:40 2003
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
051-6497
SCALE
NONE
SHT
OF
4
69
1
A
REV.
13
DRAWING
<XR_PAGE_TITLE>
78
6
5
4
3
12
APOLLO_MPC7445_360
NC_CPUCRUD<0>
NC_CPUCRUD<1>
NC_CPUCRUD<2>
NC_CPUCRUD<3>
NC_CPUCRUD<4>
NC_CPUCRUD<5>
NC_CPUCRUD<6>
D
C
B
A
NC_CPUCRUD<7>
NC_CPUCRUD<8>
NC_CPUCRUD<9>
NC_CPUCRUD<10>
NC_CPUCRUD<11>
NC_CPUCRUD<12>
NC_CPUCRUD<13>
NC_CPUCRUD<14>
NC_CPUCRUD<15>
NC_CPUCRUD<16>
NC_CPUCRUD<17>
NC_CPUCRUD<18>
NC_CPUCRUD<19>
NC_CPUCRUD<20>
NC_CPUCRUD<21>
NC_CPUCRUD<22>
NC_CPUCRUD<23>
NC_CPUCRUD<24>
NC_CPUCRUD<25>
NC_CPUCRUD<26>
NC_CPUCRUD<27>
NC_CPUCRUD<28>
NC_CPUCRUD<29>
NC_CPUCRUD<30>
NC_CPUCRUD<31>
NC_CPUCRUD<32>
NC_CPUCRUD<33>
NC_CPUCRUD<34>
NC_CPUCRUD<35>
NC_CPUCRUD<36>
NC_CPUCRUD<37>
NC_CPUCRUD<38>
NC_CPUCRUD<39>
NC_CPUCRUD<40>
NC_CPUCRUD<41>
NC_CPUCRUD<42>
NC_CPUCRUD<43>
NC_CPUCRUD<44>
NC_CPUCRUD<45>
NC_CPUCRUD<46>
NC_CPUCRUD<47>
NC_CPUCRUD<48>
NC_CPUCRUD<49>
NC_CPUCRUD<50>
NC_CPUCRUD<51>
NC_CPUCRUD<52>
NC_CPUCRUD<53>
NC_CPUCRUD<54>
NC_CPUCRUD<55>
NC_CPUCRUD<56>
NC_CPUCRUD<57>
NC_CPUCRUD<58>
NC_CPUCRUD<59>
NC_CPUCRUD<60>
NC_CPUCRUD<61>
NC_CPUCRUD<62>
NC_CPUCRUD<63>
NC_CPUCRUD<64>
NC_CPUCRUD<65>
NC_CPUCRUD<66>
NC_CPUCRUD<67>
NC_CPUCRUD<68>
NC_CPUCRUD<69>
NC_CPUCRUD<70>
NC_CPUCRUD<71>
NC_CPUCRUD<72>
NC_CPUCRUD<73>
NC_CPUCRUD<74>
NC_CPUCRUD<75>
NC_CPUCRUD<76>
NC_CPUCRUD<77>
NC_CPUCRUD<78>
NC_CPUCRUD<79>
NC_CPUCRUD<80>
NC_CPUCRUD<81>
NC_CPUCRUD<82>
NC_CPUCRUD<83>
NC_CPUCRUD<84>
NC_CPUCRUD<85>
NC_CPUCRUD<86>
NC_CPUCRUD<87>
NC_CPUCRUD<88>
NC_CPUCRUD<89>
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST
8
F18
F17
F19
H19
H18
H17
H16
E19
D18
F16
G16
D19
F15
G19
E16
D17
D16
P15
L15
N15
P18
N14
M14
M17
N13
N16
M19
M16
P19
N17
M15
L17
L14
K15
J14
J18
J19
J15
K19
J16
H15
L16
P16
M18
L19
L18
K18
J17
K16
C19
D15
G15
C18
A16
B19
A19
D14
E15
B15
B17
C17
C16
G13
E14
H14
G14
C15
A17
G12
F14
F13
E13
B16
A15
C14
A18
A13
F12
A14
G11
C13
N12
N18
K17
N19
B18
E12
B13
B14
A6
NC_F18
NC_F17
NC_F19
NC_H19
NC_H18
NC_H17
NC_H16
NC_E19
NC_D18
NC_F16
NC_G16
NC_D19
NC_F15
NC_G19
NC_E16
NC_D17
NC_D16
NC_P15
NC_L15
NC_N15
NC_P18
NC_N14
NC_M14
NC_M17
NC_N13
NC_N16
NC_M19
NC_M16
NC_P19
NC_N17
NC_M15
NC_L17
NC_L14
NC_K15
NC_J14
NC_J18
NC_J19
NC_J15
NC_K19
NC_J16
NC_H15
NC_L16
NC_P16
NC_M18
NC_L19
NC_L18
NC_K18
NC_J17
NC_K16
NC_C19
NC_D15
NC_G15
NC_C18
NC_A16
NC_B19
NC_A19
NC_D14
NC_E15
NC_B15
NC_B17
NC_C17
NC_C16
NC_G13
NC_E14
NC_H14
NC_G14
NC_C15
NC_A17
NC_G12
NC_F14
NC_F13
NC_E13
NC_B16
NC_A15
NC_C14
NC_A18
NC_A13
NC_F12
NC_A14
NC_G11
NC_C13
NC_N12
NC_N18
NC_K17
NC_N19
NC_B18
NC_E12
NC_B13
NC_B14
NC_A6
U34
800MHZ
BGA
(3 OF 3)
APOLLO_MPC7445_360
D
C
B
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
9C1<>
9C1<>
9C1<>
9C1<>
9C1<>
56D3>
56D3>
56D3>
9C1<>
9C1<>
9B1<>
9B1<>
9B1<>
9B1<>
9B1<>
9B1<>
9D8<
9D8<
9D8<
9D8<
9C8<
9C8<
9C8<
9C8<
56D3>
9D5<
9D5<
9D5<
9D5<
9C5<
9C5<
9C5<
9D1<>
9D1<>
9D1<>
9D1<>
9D1<>
9D1<>
9D1<>
9D1<>
9D1<>
9D1<>
9D1<>
9D1<>
9D1<>
9D1<>
9D1<>
9D1<>
9C1<>
9C1<>
9C1<>
9C1<>
9C1<>
9C1<>
9C1<>
9C1<>
9C1<>
9C1<>
9C1<>
9C1<>
9C1<>
9C1<>
9C1<>
9C1<>
9B7<
9B7<
9B7<
9B7<
9A7<
9C1<>
9C1<>
9C1<>
8D7<>
8C4<>
8C5<>
8C4<
8C8<>
8C7<>
8C4<>
8C7<
9B1<>
9B1<>
9B1<>
9B1<>
9B1<>
9B1<>
9B1<>
9B1<>
9B1<>
9B1<>
9B1<>
9B1<>
9B1<>
9B1<>
9B1<>
9B1<>
8C4<>
8C7<>
8C8<>
8C5<>
8C7<>
8C8<>
8C4<>
8C8<>
8C5<>
8C4<>
CPU_DATA<10>
8C7<>
CPU_DATA<11>
8C5<>
CPU_DATA<12>
8C5<>
CPU_DATA<13>
8C7<>
CPU_DATA<14>
8C8<>
CPU_DATA<15>
8C5<>
CPU_DATA<16>
8C4<>
CPU_DATA<17>
8C7<>
CPU_DATA<18>
8C4<>
CPU_DATA<19>
8C4<>
CPU_DATA<20>
8C4<>
CPU_DATA<21>
8C8<>
CPU_DATA<22>
8C7<>
CPU_DATA<23>
8C8<>
CPU_DATA<24>
8D4<>
CPU_DATA<25>
8D7<>
CPU_DATA<26>
8C5<>
CPU_DATA<27>
8C7<>
CPU_DATA<28>
8D8<>
CPU_DATA<29>
8C8<>
CPU_DATA<30>
8C5<>
CPU_DATA<31>
8D7<>
CPU_DATA<32>
8D7<>
CPU_DATA<33>
8D8<>
CPU_DATA<34>
8D8<>
CPU_DATA<35>
8D7<>
CPU_DATA<36>
8D4<>
CPU_DATA<37>
8D5<>
CPU_DATA<38>
8D5<>
CPU_DATA<39>
8D5<>
CPU_DATA<40>
6C4<
CPU_DATA<41>
6C4<
CPU_DATA<42>
6C4<
CPU_DATA<43>
6C4<
CPU_DATA<44>
6C4<
CPU_DATA<45>
6C4<
CPU_DATA<46>
6C4<
CPU_DATA<47>
6C4<
CPU_DATA<48>
8C5<>
CPU_DATA<49>
8C4<>
CPU_DATA<50>
8C8<>
CPU_DATA<51>
8C8<>
CPU_DATA<52>
8C5<>
CPU_DATA<53>
8C7<>
CPU_DATA<54>
8D7<>
CPU_DATA<55>
8C5<>
CPU_DATA<56>
8D8<>
CPU_DATA<57>
8D5<>
CPU_DATA<58>
8D4<>
CPU_DATA<59>
8D8<>
CPU_DATA<60>
8D8<>
CPU_DATA<61>
8D4<>
CPU_DATA<62>
8D4<>
CPU_DATA<63>
8D5<>
CPU_DATA<0>
CPU_DATA<1>
CPU_DATA<2>
CPU_DATA<3>
CPU_DATA<4>
CPU_DATA<5>
CPU_DATA<6>
CPU_DATA<7>
CPU_DATA<8>
CPU_DATA<9>
NC_CPUDP<0>
NC_CPUDP<1>
NC_CPUDP<2>
NC_CPUDP<3>
NC_CPUDP<4>
NC_CPUDP<5>
NC_CPUDP<6>
NC_CPUDP<7>
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST
R15
D0
W15
D1
T14
D2
V16
D3
W16
D4
T15
D5
U15
D6
P14
D7
V13
D8
W13
D9
T13
D10
P13
D11
U14
D12
W14
D13
R12
D14
T12
D15
W12
D16
V12
D17
N11
D18
N10
D19
R11
D20
U11
D21
W11
D22
T11
D23
R10
D24
N9
D25
P10
D26
U10
D27
R9
D28
W10
D29
U9
D30
V9
D31
W5
D32
U6
D33
T5
D34
U5
D35
W7
D36
R6
D37
P7
D38
V6
D39
P17
D40
R19
D41
V18
D42
R18
D43
V19
D44
T19
D45
U19
D46
W19
D47
U18
D48
W17
D49
W18
D50
T16
D51
T18
D52
T17
D53
W3
D54
V17
D55
U4
D56
U8
D57
U7
D58
R7
D59
P6
D60
R8
D61
W8
D62
T8
D63
T3
DP0
W4
DP1
T4
DP2
W9
DP3
M6
DP4
V3
DP5
N8
DP6
W6
DP7
U34
800MHZ
BGA
(2 OF 3)
MPC7450 - 2
NOTICE OF PROPRIETARY PROPERTY
LAST_MODIFIED=Wed Sep 17 12:15:41 2003
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
APPLE COMPUTER INC.
67
5
4
3
2
051-6497
SCALE
NONE
SHT
5
1
REV.
OF
69
A
13
DRAWING
<XR_PAGE_TITLE>
78
6
5
BOMOPTIONS FOR UPPER-SET OF RESISTORS
1200@133&1500@167&1333@133&1667@167&1467@133&1833@167&1600@133&2000@167&1733@133&2167@167&1867@133&2333@167&2000@133&2500@167&2133@133&2667@167
667@133&833@167&733@133&917@167&800@133&1000@167&1067@133&1333@167&1333@133&1667@167&1467@133&1833@167&1600@133&2000@167&1867@133&2333@167&2133@133&2667@167
800@133&1000@167&867@133&1083@167&1067@133&1333@167&1200@133&1500@167&1733@133&2167@167&1867@133&2333@167&2133@133&2667@167
4
3
12
D
SPECIAL CONFIG
1
R382
10K
1%
1/16W
MF
402
2
SPECIAL CONFIG
1
R379
10K
1%
1/16W
MF
402
2
SPECIAL CONFIG
1
R378
10K
1%
1/16W
MF
402
2
C
SPECIAL CONFIG
1
R383
1K
1%
1/16W
MF
402
2
CPU_PLL_STOP
44B8<
SPECIAL CONFIG
1
R381
1K
1%
1/16W
MF
402
2
SPECIAL CONFIG
1
R380
1K
1%
1/16W
MF
402
2
B
667@133&833@167&733@133&917@167&800@133&1000@167&867@133&1083@167&1000@133&1250@167&1200@133&1500@167&1467@133&1833@167&1600@133&2000@167&1733@133&2167@167&2000@133&2500@167&2133@133&2667@167
SPECIAL CONFIG
1
R376
10K
1%
1/16W
MF
402
2
SPECIAL CONFIG
1
R377
1K
1%
1/16W
MF
402
2
+MAXBUS_SLEEP
8D1<
8A3<>
46D4<
45D2<>
SPECIAL CONFIG
1
R374
10K
1%
1/16W
MF
402
2
CPU_PLL_CFGEXT
CPU_PLL_CFG<3>
CPU_PLL_CFG<2>
CPU_PLL_CFG<1>
CPU_PLL_CFG<0>
SPECIAL CONFIG
1
R375
1K
1%
1/16W
MF
402
2
7C7<
44D2<
7C5<
44D1<
4C3<
4C3<
4D3<
4D3<
4D3<
4D5<
44B7<
7C3<
8A8<>
8A8<>
8A8<>
8A8<>
8A8<>
6C5<
44D1<
7B3<
44B7<
7A3<
44D2<
59C8>
7A3<
9D8<
7B3<
52C6>
6D6<
9B7<
7C3<
45D2<>
4D5<
8D4<
7C5<
46D4<
52C6>
59C8>
8A3<>
7C7<
+MAXBUS_SLEEP
R879
10K
1/16W
R363
4.7K
1/16W
NOSTUFF
1
R878
1%
1/16W
MF
402
2
1
R364
4.7K
5%
1/16W
MF
402
2
NOSTUFF
SPARE
10K
402
402
8D1<
1%
MF
5%
MF
1
R889
2
1
R887
4.7K
2
SPARE
8D4<
9D8<
9B7<
NOSTUFF
667@133&733@133&800@133&867@133&933@133&1000@133&1067@133&1200@133&1333@133&1467@133&1600@133&1733@133&1867@133&2000@133&2133@133
1
1
R866
R874
10K
10K
1%
1/16W
MF
402
2
1
R357
4.7K
5%
1/16W
MF
402
2
PLL4MODESEL_NXT[2:0]
000: 166.4 MHZ
001: 149.76 MHZ
010: 133.12 MHZ
011: 99.84 MHZ
100: 83.20 MHZ
(STUFF FOR 133 AND 167)
10K
1%
1/16W
1/16W
402
402
1%
1/16W
MF
MF
402
2
1
R368
4.7K
5%
5%
1/16W
MF
MF
402
2
833@167&917@167&1000@167&1083@167&1167@167&1250@167&1333@167&1500@167&1667@167&1833@167&2000@167&2167@167&2333@167&2500@167&2667@167
NOSTUFF
NOSTUFF
NOSTUFF
NOSTUFF
1
R877
10K
1%
1/16W
MF
402
2
1
R365
4.7K
5%
1/16W
MF
402
2
1
1
2
1
2
1: ACTIVE
0: INACTIVE
R867
R875
R367
4.7K
INTERNALSPREADEN
10K
10K
1%
1/16W
1/16W
MF
402
2
1
R356
4.7K
5%
1/16W
1/16W
MF
402
2
PCI1 SOURCE CLOCK
1: PLL5 (NO SPREAD)
0: PLL4
402
402
(STUFF FOR 133 AND 167)
1
1%
MF
2
CPU_DATA<40>
CPU_DATA<41>
CPU_DATA<42>
CPU_DATA<43>
CPU_DATA<44>
CPU_DATA<45>
CPU_DATA<46>
CPU_DATA<47>
1
INTREPID BOOT STRAPS
5%
BITS 40 - 47
MF
2
PCI0 SOURCE CLOCK
1: PLL5 (NO SPREAD)
0: PLL4
5B4<>
5B4<>
5B4<>
5B4<>
5B4<>
5B4<>
5B4<>
5B4<>
8D7<>
8C4<>
8C5<>
8C4<
8C8<>
8C7<>
8C4<>
8C7<
9C1<>
9C1<>
9B1<>
9B1<>
9B1<>
9B1<>
9B1<>
9B1<>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
CPU FREQUENCY CONFIGURATION
MULTIPLIER
(BUS-TO-CORE)
5.0X
5.5X
6.0X
6.5X
7.0X
7.5X
8.0X
9.0X
10.0X
11.0X
12.0X
13.0X
14.0X
15.0X
16.0X
(SUPPORTED CPU & BUS SPEEDS)
CORE FREQUENCY
(AT BUS FREQUENCY)
167MHZ
833
917
1000
1083
1167
1250
1333
1500
1667
1833
2000
2167
2333
2500
2667
(MHZ)
133MHZ
667
733
800
867
933
1000
1067
1200
1333
1467
1600
1733
1867
2000
2133
CPU_PLL_CFG
E 0123 HEX
0 1011 0B
0 1001 09
0 1101 0D
0 0101 05
0 0010 02
0 0001 01
0 1100 0C
1 0111 17
1 1010 1A
1 1001 19
1 1011 1B
1 0101 15
1 1100 1C
1 0001 11
1 1101 1D
667@133&833@167&933@133&1167@167&1200@133&1500@167&1333@133&1667@167&1600@133&2000@167
D
C
B
933@133&1167@167&1067@133&1333@167&1333@133&1667@167&1867@133&2333@167
733@133&917@167&800@133&1000@167&867@133&1083@167&1000@133&1250@167&1067@133&1333@167&1467@133&1833@167&1733@133&2167@167&1867@133&2333@167&2000@133&2500@167&2133@133&2667@167
667@133&833@167&733@133&917@167&933@133&1167@167&1000@133&1250@167&1333@133&1667@167&1467@133&1833@167&1600@133&2000@167&2000@133&2500@167
867@133&1083@167&933@133&1167@167&1000@133&1250@167&1200@133&1500@167&1733@133&2167@167&2000@133&2500@167
667@133&833@167&733@133&917@167&800@133&1000@167&867@133&1083@167&933@133&1167@167&1000@133&1250@167&1067@133&1333@167
CPU SPEED & BUS RATIO SUPPORT
THE CONFIGURATION RESISTORS BELOW ARE SELF CONFIGURING
WHEN THE ENGINEER SELECTS THE APPROPRIATE CPU AND
A
BUS SPEED BOM OPTION, THE APPROPRIATE RESISTORS ARE
ARE AUTOMATICALLY SELECTED
DESCRIPTION REFERENCE DES BOM OPTIONQTYPART NUMBER CRITICAL
IC,APOLLO6,SICOH,1.0GHZ,1.5V+30/-130MV,28W,85C
1
1
IC,APOLLO6,SICOH,1.25GHZ,1.57V+70/-70MV,35W,85C
1000@167CRITICALU34337S2799
1250@167CRITICALU34337S2801
APPLE COMPUTER INC.
8
67
5
4
3
2
CPU BUS RATIO BITS
NOTICE OF PROPRIETARY PROPERTY
LAST_MODIFIED=Wed Sep 17 12:15:42 2003
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
051-6497
SCALE
NONE
SHT
OF
6
69
1
A
REV.
13
DRAWING
<XR_PAGE_TITLE>
D
C
B
A
8D1<
46D4<
56C3>
78
BMODE | MSSCR0 | Sys | Vger | Addr
<0> <1> | <16:17> | Bus | ID | Drve
=========+=========+=====+======+======
L L | 1 1 | ??? | 01 | yes unavail
L !hr | 1 0 | Max | 01 | yes unavail
L hr | 1 1 | ??? | 00 | yes unavail
L H | 1 0 | Max | 00 | yes unavail
---------+---------+-----+------+-----Â !hr L | 0 1 | MB+ | 01 | yes unavail
!hr !hr | 0 0 | 60x | 01 | yes unavail
!hr hr | 0 1 | MB+ | 00 | yes unavail
!hr H | 0 0 | 60x | 00 | yes unavail
---------+---------+-----+------+-----Â hr L | 1 1 | ??? | 01 | norm unavail
hr !hr | 1 0 | Max | 01 | norm
hr hr | 1 1 | ??? | 00 | norm unavail
HR H | 1 0 | MAX | 00 | NORM
---------+---------+-----+------+-----Â H L | 0 1 | MB+ | 01 | norm unavail
H !hr | 0 0 | 60x | 01 | norm
H hr | 0 1 | MB+ | 00 | norm unavail
H H | 0 0 | 60x | 00 | norm
MAXBUS PULL-UPS
59C8>
8A3<>
45D2<>
56D3>
56C3>
56C3>
56C3>
56C3>
56C3>
56D3>
56C3>
56D3>
56D3>
56D3>
56D3>
56D3>
56C3>
9B3<>
56D3>
56D3>
56C3>
56C3>
7C5<
9D3<>
9B3<
9B1<
9A1<>
9B3<>
9B1<>
9B3<>
9C3<>
9B3<>
9B3<>
9B3<>
9B3<>
9B3<>
44D2<
9A1<>
8B8<>
9D3<
8B5<>
9D3<>
9C3<>
9B3<>
7C3<
8B5<>
8B4<>
7B3<
44D1<
8B7<>
4D7<>
8C4<>
4A7<>
8B4<>
8B8<>
4A7>
4C2<
8B5<>
4C3<
4A7<
8B8<>
4C3<
8B4<>
4B7>
CPU_INT_GBL_L
4B8<
8C5<>
8B5<>
8B4<>
4B7<>
8B5<>
4B7<>
8B4<>
4B7<>
8B5<>
4B7<>
8B4<>
4B7<>
7A3<
6D6<
44B7<
9D8<
CPU_TS_L
CPU_TA_L
4C3<
CPU_ARTRY_L
CPU_BR_L
4D7>
CPU_HIT_L
CPU_DRDY_L
CPU_TEA_L
CPU_AACK_L
CPU_DBG_L
CPU_BG_L
4D7<
CPU_TBST_L
CPU_CI_L
4A7>
CPU_WT_L
4B7>
CPU_TT<0>
CPU_TT<1>
CPU_TT<2>
CPU_TT<3>
CPU_TT<4>
52C6>
6C5<
9B7<
+MAXBUS_SLEEP
4D5<
8D4<
R347
10K
1 2
1%
1/16W
MF
402
R346
10K
1 2
1%
1/16W
MF
402
R840
10K
1 2
1%
1/16W
MF
402
R845
10K
1 2
1%
1/16W
MF
402
R847
10K
1 2
1%
1/16W
MF
402
R349
10K
1 2
1%
1/16W
MF
402
R844
10K
1 2
1%
1/16W
MF
402
RP78
10K
1 8
5%
1/16W
SM1
R843
10K
1 2
1%
1/16W
MF
402
R350
10K
1 2
1%
1/16W
MF
402
R348
10K
1 2
1%
1/16W
MF
402
R841
10K
1 2
1%
1/16W
MF
402
R851
10K
1 2
1%
1/16W
MF
402
R849
10K
1 2
1%
1/16W
MF
402
R846
10K
1 2
1%
1/16W
MF
402
R842
10K
1 2
1%
1/16W
MF
402
RP78
10K
2 7
5%
1/16W
SM1
RP78
10K
3 6
5%
1/16W
SM1
RP78
10K
4 5
5%
1/16W
SM1
8
<- DEFAULT
59C8>
44D2<
8D4<
59C8>
44C2<
6
8D1<
52C6>
8D5<>
8A3<>
67
56C3>
59C8>
8A3<>
46D4<
28B5>
59C8>
8A3<>
59C8>
7B3<
59C6>
59C8>
59C8>
9B3<
8B7<>
8A3<>
8A3<>
4C3<
4D7<>
7C7<
7C3<
45D2<>
9A3<>
4C3<
CPU_CHKSTP_OUT_L
4B3>
4B3<
7A3<
8A3<>
8D7<>
4B3<
44C4<>
8A3<>
8A3<>
CPU_QREQ_L
4C3>
JTAG_CPU_TCK
4C3<
JTAG_CPU_TRST_L
CPU_PMONIN_L
4B3<
CPU_EDTI
4C3<
CPU_PULLDOWN
4A3<
7B3<
7A3<
44D1<
CPU_TBEN
4C3<
CPU_SHD0_L
CPU_SHD1_L
CPU_MCP_L
4B3<
6D6<
44B7<
44D2<
4A7<>
4A7<>
CPU_LSSD_MODE
CPU_CHKSTP_IN_L
CPU_PULLUP
4A3<
CPU_HRESET_L
4B3<
CPU_SRESET_L
4B3<
MPIC_CPU_INT_L
CPU_SMI_L
4B3<
JTAG_CPU_TDI
4C3<
JTAG_CPU_TMS
4C3<
5
R848
10K
1 2
1%
1/16W
MF
10K
402
470
402
1%
MF
10K
5%
1/16W
SM1
5%
MF
402
R925
200
1 2
5%
1/16W
MF
402
R858
10K
1 2
1%
1/16W
MF
402
R924
1 2
1/16W
RP79
4 5
R859
1 2
1/16W
MPC7450 PULL-UPS
59C8>
6C5<
9D8<
+MAXBUS_SLEEP
4D5<
9B7<
R857
10K
1 2
1%
1/16W
MF
402
R910
10K
1 2
1%
1/16W
MF
402
NOSTUFF
R921
1K
1 2
1%
1/16W
MF
402
R909
1K
1 2
1%
1/16W
MF
402
RP79
10K
2 7
5%
1/16W
SM1
R912
10K
1 2
1%
1/16W
MF
402
R923
10K
1 2
1%
1/16W
MF
402
R856
10K
1 2
1%
1/16W
MF
402
R860
10K
1 2
1%
1/16W
MF
402
R911
10K
1 2
1%
1/16W
MF
402
R882
1K
1 2
1%
1/16W
MF
402
R922
10K
1 2
1%
1/16W
MF
402
RP79
10K
3 6
5%
1/16W
SM1
RP79
10K
1 8
5%
1/16W
SM1
5
4
CPU_BUS_VSEL
4D3<
CPU_L2TSTCLK
4C3<
CPU_L1TSTCLK
4C3<
CPU_EMODE0_L
4B3<
CPU_EMODE1_L
4B3<
4
3
SIGNAL
CPU_EMODE0_L
CPU_BUS_VSEL
CPU_HRESET_L or L3_OVDD
CPU_L3_VSEL LOW
NOSTUFF
R915
0
1 2
5%
1/16W
NOSTUFF
MF
402
R913
10K
1 2
1/16W
402
R914
200
1 2
5%
1/16W
MF
402
BUS MODE
0V 1.8V BUS MODE
INV_HRESET 1.5V BUS MODE
OVDD 2.5V BUS MODE
R918
10K
1 2
1/16W
NOSTUFF
1 2
NOSTUFF
1 2
DO NOT USE UNLESS FIX INVERTER BUFFER
1 2
1 2
CPUBUS_MAX
1 2
NOSTUFF
R902
1 2
1/16W
R926
0
5%
1/16W
MF
402
R920
200
5%
1/16W
MF
402
NOSTUFF
R906
0
5%
1/16W
MF
402
R917
200
5%
1/16W
MF
402
R905
200
5%
1/16W
MF
402
200
5%
MF
402
402
NOSTUFF
R919
1 2
1/16W
402
NOSTUFF
R907
10K
1 2
1/16W
402
NOSTUFF
R916
1 2
1/16W
402
CPUBUS_60X
1 2
1 2
CPU_HRESET_L
CPU_HRESET_L
CPU_HRESET_H
CPU_HRESET_H
5%
MF
1%
MF
0
5%
MF
5%
MF
0
5%
MF
R904
1K
5%
1/16W
MF
402
R903
1K
1%
1/16W
MF
402
TIED
HIGH
LOW
VGER_INV_HRESET
+MAXBUS_SLEEP
+MAXBUS_SLEEP
CPU_HRESET_L
VGER_INV_HRESET
+MAXBUS_SLEEP
CPU_HRESET_L
VGER_INV_HRESET
+MAXBUS_SLEEP
CPU_HRESET_L
+MAXBUS_SLEEP
VGER_INV_HRESET
12
APPLICATION
60X BUS MODE
MAX BUS MODE
2.5V INTERFACE
1.8V INTERFACE
1.5V INTERFACE
2.5V INTERFACE
1.8V INTERFACE
1.5V INTERFACE
7B3<
7A3<
59C8>
6C5<
4D5<
9B7<
8D4<
6D6<
9D8<
44D1>
7A3<
44B7<
7B3<
44D1<
7C3<
44D2<
7C5<
7C7<
45D2<>
8A3<>
46D4<
8D1<
52C6>
D
C
59C8>
4D5<
8D4<
4B3<
4D5<
9B7<
4B3<
59C8>
4D5<
8D4<
4B3<
59C8>
7A3<
7A3<
7A3<
7A3<
6C5<
9B7<
7A5<
6C5<
9B7<
6C5<
9D8<
7A5<
7B3<
7A5<
7B3<
6D6<
9D8<
7B3<
6D6<
9D8<
6D6<
44B7<
7A3<
44B7<
7B3<
7C3<
7A3<
7B3<
7C3<
7A3<
44B7<
8A3<>
44D1>
44D1<
44D1>
7B3<
44D1<
8A3<>
7C3<
8A3<>
7B3<
44D1<
44C2<
44D2<
7C3<
7C3<
44D2<
44C2<
7C5<
44C2<
44D2<
44D2<
7C5<
7C7<
45D2<>
7C5<
45D2<>
44D2<
44D2<
45D2<>
7C7<
8A3<>
46D4<
7C7<
59C8>
59C8>
8A3<>
46D4<
8A3<>
46D4<
8D1<
52C6>
8D1<
52C6>
8D4<
59C8>
8D1<
52C6>
B
CPU CONFIG OPTIONS
9D8<
7C5<
4D5<
7A3<
44B7<
7B3<
6C5<
7B3<
44D1<
7C3<
6D6<
7C3<
8D1<
44D2<
44D1>
8A3<>
7C7<
3
9B7<
8D4<
46D4<
45D2<>
APPLE COMPUTER INC.
52C6>
2
NOTICE OF PROPRIETARY PROPERTY
LAST_MODIFIED=Wed Sep 17 12:15:43 2003
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
59C8>
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
051-6497
NONE
SHT
7
SCALE
1
REV.
OF
69
A
13
DRAWING
<XR_PAGE_TITLE>
1
C992
10UF
N20P80%
10V
2
Y5V
805
3
1
C988
0.1UF
20%
10V
2
CERM
402
1
C1026
0.1UF
20%
10V
2
CERM
402
1
C1043
0.1UF
20%
10V
2
CERM
402
1
C982
0.1UF
20%
10V
2
CERM
402
1
C1013
0.1UF
20%
10V
2
CERM
402
1
C999
0.1UF
20%
10V
2
CERM
402
78
6
8D1<
8A3<>
7C7<
46D4<
7C5<
45D2<>
52C6>
7C3<
44D2<
7B3<
5
7A3<
44D1<
6D6<
44B7<
59C8>
6C5<
9D8<
+MAXBUS_SLEEP
4D5<
9B7<
4
1
C350
10UF
N20P80%
10V
2
Y5V
805
1
C958
10UF
N20P80%
10V
2
Y5V
805
1
C983
10UF
N20P80%
10V
2
Y5V
805
1
C974
0.1UF
20%
10V
2
CERM
402
12
1
C1003
0.1UF
20%
10V
2
CERM
402
D
56B3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
9C1<>
56D3>
9D5<
9C1<>
9D5<
56D3>
56D3>
56D3>
56D3>
56D3>
9D8<
56D3>
56D3>
9D8<
56D3>
9B1<>
9B7<
9B1<>
9B1<>
9B7<
9B1<>
9C1<>
9C1<>
9C1<>
9C1<>
9D1<>
9B1<>
9D1<>
9D1<>
9B1<>
9D1<>
6C4<
5C4<>
5B4<>
5B4<>
5C4<>
5B4<>
5C4<>
5C4<>
5C4<>
5C4<>
5C4<>
5B4<>
5D4<>
5D4<>
5B4<>
5D4<>
5B4<>
8A2<
C
56D3>
9C3<>
9C3<>
9C3<>
9C3<>
9C3<>
9C3<>
9B1<>
9C3<>
9C3<>
9C3<>
7C7<
9C3<>
9C3<>
9B3<
9D3<>
9C3<>
4B7<>
4B7<>
4B7<>
4C7<>
4C7<>
4B7<>
7B7<
4C7<>
4C7<>
4C7<>
4A7<>
4C7<>
4C7<>
7C7<
4C7<>
4C7<>
4C3<
4A7>
56C3>
56D3>
56D3>
56D3>
56D3>
56D3>
56C3>
56D3>
56D3>
56D3>
9B3<>
56D3>
56D3>
56C3>
56D3>
56D3>
B
59D8>
59B6>
52C6>
45D2<>
8C1<
FMAX DEBUG CONNECTOR
NOSTUFF
J32
SM12B-SRSS-TB
F-RT-SM
14
1
2
3
4
5
A
6
7
8
9
10
11
12
13
CPU_PLL_CFG<0>
CPU_PLL_CFG<1>
CPU_PLL_CFG<2>
CPU_PLL_CFG<3>
CPU_PLL_CFGEXT
NO_TEST
NO_TEST
PWR_SWITCH*
PMU_RST*
NO_TEST
(518S0105)
8
SYSCLK_LA
CPU_DATA<34>
CPU_DATA<56>
CPU_DATA<59>
CPU_DATA<33>
CPU_DATA<60>
CPU_DATA<28>
CPU_DATA<29>
CPU_DATA<23>
CPU_DATA<21>
CPU_DATA<14>
CPU_DATA<50>
CPU_DATA<2>
CPU_DATA<5>
CPU_DATA<51>
CPU_DATA<7>
CPU_DATA<44>
CPU_ADDR<26>
CPU_ADDR<29>
CPU_ADDR<27>
CPU_ADDR<18>
CPU_ADDR<23>
CPU_ADDR<25>
CPU_DBG_L
CPU_ADDR<17>
CPU_ADDR<20>
CPU_ADDR<16>
CPU_ARTRY_L
CPU_ADDR<10>
CPU_ADDR<13>
CPU_HIT_L
CPU_ADDR<3>
CPU_ADDR<9>
CPU_VCORE_SLEEP
4D7<
4D3<
4D3<
4D3<
4D3<
4C3<
4C3<
NC_FMAX7
NC_FMAX8
29B3<>
NC_RESET_BUTTON_L
44B1<
44C5<>
44A5<>
CON_38SM_MICTOR
OMIT
10
11
12
13
14
15
16
17
18
19
CON_38SM_MICTOR
OMIT
10
11
12
13
14
15
16
17
18
19
6C6<
6C6<
6C6<
6C6<
6C6<
59D6>
59D6>
44B5<>
J20
SM
CPROBE
1
SYM_VER3
GND
2
GND
3
CLK3
4
C3_7
5
C3_6
6
C3_5
7
C3_4
8
C3_3
9
C3_2
C3_1
C3_0
C2_7
C2_6
C2_5
C2_4
C2_3
C2_2
C2_1
C2_0
GND
39404142434445
J31
SM
APROBE
1
SYM_VER2
GND
2
GND
3
CLK0
4
A3_7
5
A3_6
6
A3_5
7
A3_4
8
A3_3
9
A3_2
A3_1
A3_0
A2_7
A2_6
A2_5
A2_4
A2_3
A2_2
A2_1
A2_0
GND
39404142434445
SEE_TABLE
1
2
MAXBUS LOGIC ANALYZER SUPPORT
NOTE: INTREPID MAXBUS CONFIG STRAPS MUST DROP
TO 1K OR LOGIC ANALYZER MAY AFFECT STRAP VALUES
MPIC_CPU_INT_L
CPU_DATA<35>
CPU_DATA<54>
CPU_DATA<32>
CPU_DATA<40>
CPU_DATA<31>
CPU_DATA<25>
CPU_DATA<27>
CPU_DATA<22>
CPU_DATA<17>
CPU_DATA<10>
CPU_DATA<13>
CPU_DATA<1>
CPU_DATA<4>
CPU_DATA<53>
CPU_DATA<47>
CPU_DATA<45>
CPU_ADDR<30>
CPU_ADDR<31>
CPU_ADDR<28>
CPU_ADDR<22>
CPU_ADDR<21>
CPU_ADDR<24>
CPU_TS_L
CPU_ADDR<15>
CPU_ADDR<19>
CPU_ADDR<14>
CPU_DTI<0>
CPU_ADDR<7>
CPU_ADDR<12>
CPU_QREQ_L
CPU_TSIZ<2>
CPU_ADDR<5>
4D7<>
4C3<
4C3>
5C4<>
5B4<>
5C4<>
5B4<>
5C4<>
5C4<>
5C4<>
5C4<>
5C4<>
5D4<>
5C4<>
5D4<>
5D4<>
5B4<>
5B4<>
5B4<>
4B7<>
4B7<>
4B7<>
4C7<>
4C7<>
4B7<>
7C7<
4C7<>
4C7<>
4C7<>
4C7<>
4C7<>
4B7>
4C7<>
4B3<
9D1<>
9D1<>
9A1<>
9D3<>
7D5<
9B3<>
9D3<>
7A5<
9B7<
9B1<>
9B7<
6C4<
9C1<>
9C1<>
9C1<>
9C1<>
9C1<>
9D1<>
9D1<>
9B1<>
6C4<
6C4<
9C3<>
9C3<>
9C3<>
9C3<>
9C3<>
9C3<>
9D3<>
9C3<>
9C3<>
9C3<>
9C3<>
9B3<
56D3>
56D3>
56C3>
56D3>
56D3>
56D3>
28B5>
9C1<>
9C8<
9C1<>
9C1<>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
9C8<
9B1<>
9B1<>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56C3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
C1_7
C1_6
C1_5
C1_4
C1_3
C1_2
C1_1
C1_0
C0_7
C0_6
C0_5
C0_4
C0_3
C0_2
C0_1
C0_0
CLK1
A1_7
A1_6
A1_5
A1_4
A1_3
A1_2
A1_1
A1_0
A0_7
A0_6
A0_5
A0_4
A0_3
A0_2
A0_1
A0_0
GND
GND
GND
GND
38
37
36
Q1
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
CPU CORE DECOUPLING
SEE_TABLE
1
C1022
1UF
10%
6.3V
2
CERM
402
SEE_TABLE
1
C1009
1UF
10%
6.3V
2
CERM
402
SEE_TABLE
1
C996
1UF
10%
6.3V
2
CERM
402
C1096
1UF
10%
6.3V
CERM
402
1
2
1
2
1
2
SEE_TABLE
1
C1097
1UF
10%
6.3V
2
CERM
402
SEE_TABLE
C1027
1UF
10%
6.3V
CERM
402
SEE_TABLE
C1002
1UF
10%
6.3V
CERM
402
SEE_TABLE
C1012
1UF
10%
6.3V
CERM
402
1
C1901
0.1UF
10V
2
CERM
402
SEE_TABLE
1
C1011
1UF
10%
6.3V
2
CERM
402
SEE_TABLE
1
C1023
1UF
10%
6.3V
2
CERM
402
SEE_TABLE
1
C1024
1UF
10%
6.3V
2
CERM
402
1
C1902
0.1UF
20%20%
10V
2
CERM
SEE_TABLE
1
C1008
1UF
10%
6.3V
2
CERM
402
SEE_TABLE
1
C1017
1UF
10%
6.3V
2
CERM
402
SEE_TABLE
1
C1001
1UF
10%
6.3V
2
CERM
402
1
C1903
0.1UF
20%
10V
2
CERM
402402
67
1
2
1
2
1
2
8A3<>
59C8>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
(519-0698)
SEE_TABLE
C1010
1UF
10%
6.3V
CERM
402
SEE_TABLE
C1031
1UF
10%
6.3V
CERM
402
SEE_TABLE
C1028
1UF
10%
6.3V
CERM
402
1
C1904
0.1UF
20%
10V
2
CERM
402
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56C3>
SEE_TABLE
1
C1025
1UF
10%
6.3V
2
CERM
402
SEE_TABLE
1
C997
1UF
10%
6.3V
2
CERM
402
SEE_TABLE
1
C1018
1UF
10%
6.3V
2
CERM
402
1
C1910
2
7B5<
9C5<
9D5<
56D3>
9C8<
56D3>
9C8<
9B1<>
9D8<
56D3>
56C3>
56D3>
56D3>
56C3>
56D3>
56D3>
56C3>
56C3>
0.1UF
20%
10V
CERM
402
CPU_CHKSTP_OUT_L
4B3>
9C1<>
5B4<>
9C1<>
5B4<>
9C1<>
5B4<>
9B1<>
5A4<>
9B1<>
5B4<>
9C1<>
5C4<>
9C1<>
5C4<>
9D1<>
5D4<>
9D1<>
5C4<>
9B1<>
5B4<>
5C4<>
9D1<>
9D1<>
5D4<>
9D1<>
5C4<>
5B4<>
9B1<>
6C4<
5B4<>
9B1<>
5B4<>
9D3<>
4C7<>
9C3<>
7A7<
4B7>
9B3<>
9D3<>
4C7<>
9A1<>
7B7<
9B3<>
7A7<
9D3<>
4C7<>
9B3<>
4B7>
9B3<>
7A7<
9B3<>
7A7<
9B1<
7B7<
56C3>
9B3<>
7B7<
SEE_TABLE
1
C1098
1UF
10%
6.3V
2
CERM
402
59D8>
CPU_DATA<37>
CPU_DATA<39>
CPU_DATA<38>
CPU_DATA<63>
CPU_DATA<57>
CPU_DATA<30>
CPU_DATA<26>
CPU_DATA<8>
CPU_DATA<15>
CPU_DATA<55>
CPU_DATA<11>
CPU_DATA<3>
CPU_DATA<12>
CPU_DATA<52>
CPU_DATA<42>
CPU_DATA<48>
CPU_ADDR<8>
CPU_CI_L
4A7>
CPU_TSIZ<1>
CPU_ADDR<4>
CPU_TEA_L
4C3<
CPU_TT<1>
4B7<>
CPU_ADDR<1>
CPU_TSIZ<0>
CPU_WT_L
4B7>
CPU_TT<3>
4B7<>
CPU_DRDY_L
4C2<
CPU_GBL_L
4B8<>
CPU_AACK_L
4A7<
C1022,C1027,C1011,C1008,C1010,C1025,C1009,C1002,C1023,C1017,C1031,C997,C996,C1012,C1024,C1001,C1028,C1018,C1096,C1097,C1098
C1022,C1027,C1011,C1008,C1010,C1025,C1009,C1002,C1023,C1017,C1031,C997,C996,C1012,C1024,C1001,C1028,C1018,C1096,C1097,C1098
35A2<
35B4<>
59D8>
34B7<
59D8>
35C4<
59D8>
59C8>
5
J30
CON_38SM_MICTOR
OMIT
OMIT
SM
EPROBE
1
SYM_VER5
GND
J19
F-ST-SM
DPROBE
SYM_VER1
GND
E1_7
E1_6
E1_5
E1_4
E1_3
E1_2
E1_1
E1_0
E0_7
E0_6
E0_5
E0_4
E0_3
E0_2
E0_1
E0_0
CLK2
D1_7
D1_6
D1_5
D1_4
D1_3
D1_2
D1_1
D1_0
D0_7
D0_6
D0_5
D0_4
D0_3
D0_2
D0_1
D0_0
GND
GND
GND
GND
GND
2
GND
3
Q3
4
E3_7
5
E3_6
6
E3_5
7
E3_4
8
E3_3
9
E3_2
10
E3_1
11
E3_0
12
E2_7
13
E2_6
14
E2_5
15
E2_4
16
E2_3
17
E2_2
18
E2_1
19
E2_0
39404142434445
CON_37SM_MICTOR
2
GND
3
Q0
4
D3_7
5
D3_6
6
D3_5
7
D3_4
8
D3_3
9
D3_2
10
D3_1
11
D3_0
12
D2_7
13
D2_6
14
D2_5
15
D2_4
16
D2_3
17
D2_2
18
D2_1
19
D2_0
39 40 41 42 43 44 45
Q2
CPU CORE DECOUPLING
QTY
PART#
132S0013
138S0541 21
DESCRIPTION
CAP,CER,.22UF,20%,6.3V,0402,X5R
21
CAP,CER,1UF,10%,6.3V,0402,X5R
PULLDOWN ON TRST* STRONGER TO OVERCOME POSSIBLE LEAKAGE
+3V_MAIN
R937
10K
1% SM-1
1/16W
MF
402
JTAG_ASIC_TMS
34B7<
JTAG_ASIC_TDI
28C6<
JTAG_ASIC_TDO
35B4<>
JTAG_ASIC_TCK
34B7<
JTAG_ASIC_TRST_L
34B7<
NC_TESTMODE
NC_LCENABLE
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
1
2
NC_JTAG7
1
R939
10K
1%
1/16W
MF
402
2
4
1
C969
2.2UF
N20P80%
16V
2
CERM
805
CPU_DATA<58>
CPU_DATA<36>
CPU_DATA<62>
CPU_DATA<61>
CPU_DATA<24>
CPU_DATA<41>
CPU_DATA<9>
CPU_DATA<19>
CPU_DATA<20>
CPU_DATA<16>
CPU_DATA<18>
CPU_DATA<49>
CPU_DATA<6>
CPU_DATA<0>
CPU_DATA<43>
CPU_DATA<46>
REFERENCE DESIGNATOR(S)
1
C353
2.2UF
N20P80%
16V
2
CERM
805
CPU_ADDR<11>
CPU_ADDR<6>
CPU_TA_L
CPU_TT<0>
CPU_ADDR<2>
CPU_BR_L
CPU_TT<4>
CPU_ADDR<0>
CPU_TBST_L
CPU_DTI<1>
CPU_TT<2>
CPU_BG_L
CPU_QACK_L
CPU_DTI<2>
NO_TEST
NO_TEST
NO_TEST
1
R940
1K
1%
1/16W
MF
(511S0018)
402
2
5B4<>
5C4<>
5B4<>
5B4<>
5C4<>
5B4<>
5D4<>
5C4<>
5C4<>
5C4<>
5C4<>
5B4<>
5D4<>
5D4<>
5B4<>
5B4<>
4C7<>
4C7<>
7C7<
4C3<
4B7<>
4C7<>
7C7<
4D7>
4B7<>
4C7<>
4B7>
4C3<
4B7<>
4D7<
7B7<
4C3<
4C3<
NOSTUFF
J22
1
3 4
5 6
7 8
9
11 12
13 14
15 16
17 18
19
9B1<>
9A7<
9B1<>
9B1<>
9C1<>
6C4<
9D1<>
9C1<>
9C1<>
9C1<>
9C1<>
9B1<>
9D1<>
9D1<>
6C4<
6C4<
9C3<>
9D3<>
9A1<>
9B3<>
7A7<
9D3<>
9D3<
9B3<>
7A7<
9D3<>
9B3<>
7B7<
56C3>
9A1<>
9B3<>
7A7<
9D3<>
56C3>
9B3<>
56C3>
9A1<>
BOM OPTION
1GHZ_DECOUP
1_25GHZ_DECOUP
2
NO_TEST
10
20
9D5<
56D3>
56D3>
9C1<>
9C5<
56D3>
9C5<
56D3>
56D3>
9C1<>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
9D8<
56D3>
56D3>
56D3>
56D3>
9B1<>
9B1<>
56D3>
56D3>
56D3>
56C3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
TABLE_5_HEAD
TABLE_5_ITEM
TABLE_5_ITEM
59A8>
56B3>
+MAXBUS_SLEEP
CPU_CHKSTP_OUT_L
CPU_HRESET_L
CPU_SRESET_L
NC_JTAG10
JTAG_CPU_TMS
JTAG_CPU_TDI
JTAG_CPU_TDO
JTAG_CPU_TCK
JTAG_CPU_TRST_L
54A7<
3
52C6>
4D5<
8D4<
4B3<
4B3<
4C3<
4C3<
4C3>
4C3<
1
C1041
0.1UF
20%
10V
2
CERM
402
8D4<
8A3<>
52C6>
59D8>
INT_ANALYZER_CLK
9B4<
59C8>
6C5<
6D6<
9D8<
9B7<
7B5<
4B3>
7A3<
7A5<
59C6>
7A5<
59C8>
7A5<
59C8>
7A5<
59C8>
7D5<
59C8>
7C5<
4C3<
7C7<
46D4<
59B6>
1
C1014
0.1UF
20%
10V
2
CERM
402
7C5<
45D2<>
52C6>
7C3<
45D2<>
44D2<
1
2
1
2
1
2
1
2
7B3<
44D1<
C972
0.1UF
20%
10V
CERM
402
C994
0.1UF
20%
10V
CERM
402
C598
10UF
N20P80%
10V
Y5V
805
C987
0.1UF
20%
10V
CERM
402
8B7<
7A3<
6D6<
44B7<
4D7<
1
2
59C8>
6C5<
9D8<
1
C981
0.1UF
20%
10V
2
CERM
402
1
C1007
0.1UF
20%
10V
2
CERM
402
4D3<
1
C1054
10UF
N20P80%
10V
2
Y5V
805
C998
0.1UF
20%
10V
CERM
402
CPU_VCORE_SLEEP
INTREPID CLOCK OUTPUT
NOSTUFF
R314
0
1 2
5%
1/16W
MF
402
PLACE BOTH RESISTORS
CLOSE TO INTREPID
NOSTUFF
R313
22
2 1
5%
1/16W
MF
402
8D1<
7C7<
7C5<
7C3<
7B3<
7A3<
44B7<
8D5<>
7B3<
59C8>
44D1<
59C8>
44C2<
44D2<
44D2<
45D2<>
59C8>
46D4<
APPLE COMPUTER INC.
2
1
2
1
2
1
2
1
2
1
2
1
2
NOSTUFF
R308
1/16W
1
C991
0.1UF
20%
10V
2
CERM
402
C973
0.1UF
20%
10V
CERM
402
C1020
0.1UF
20%
10V
CERM
402
C976
10UF
N20P80%
10V
Y5V
805
C1042
10UF
N20P80%
10V
Y5V
805
C1912
10UF
N20P80%
10V
Y5V
805
C1056
10UF
N20P80%
10V
Y5V
805
1
47
5%
MF
402
2
8D8<>
1
2
1
C993
0.1UF
20%
10V
2
CERM
402
1
C1021
0.1UF
20%
10V
2
CERM
402
1
C1037
10UF
N20P80%
10V
2
Y5V
805
1
C1016
10UF
N20P80%
10V
2
Y5V
805
1
C1913
10UF
N20P80%
10V
2
Y5V
805
1
C1057
10UF
N20P80%
10V
2
Y5V
805
NOSTUFF
J27
U.FL-R_SMT
F-ST-SM
3
1
2
(518S0104)
56B3> 16C7<
C977
0.1UF
20%
10V
CERM
402
1
C990
0.1UF
20%
10V
2
CERM
402
1
C967
0.1UF
20%
10V
2
CERM
402
1
2
1
2
1
2
1
2
C1033
10UF
N20P80%
10V
Y5V
805
C364
10UF
N20P80%
10V
Y5V
805
C1914
10UF
N20P80%
10V
Y5V
805
1
2
+MAXBUS_SLEEP
4D5<
9B7<
1
C980
0.1UF
20%
10V
2
CERM
402
1
C961
0.1UF
20%
10V
2
CERM
402
1
C1040
10UF
N20P80%
10V
2
Y5V
805
1
C1032
10UF
N20P80%
10V
2
Y5V
805
1
C1911
10UF
N20P80%
10V
2
Y5V
805
1
C1055
10UF
N20P80%
10V
2
Y5V
805
56B3>
INT_CLOCK_OUT
SYSCLK_LA
C995
0.1UF
20%
10V
CERM
402
LA CONS & ESP
NOTICE OF PROPRIETARY PROPERTY
LAST_MODIFIED=Wed Sep 17 12:15:45 2003
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
051-6497
SCALE
NONE
SHT
OF
8 69
1
C1058
10UF
N20P80%
10V
Y5V
805
REV.
D
C
B
A
13
DRAWING
<XR_PAGE_TITLE>
52C6>
44D2<
D
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
C
45D2<>
7C3<
9D8<
B
A
8D4<
7A3<
7C7<
7B3<
8D4<
56D3>
56D3>
56D3>
56D3>
56D3>
46D4<
8D1<
6D6<
7C5<
44D1<
9B1<>
9B1<>
9B1<>
9B1<>
9B1<>
9B1<>
9B1<>
9B1<>
44D2<
9C1<>
9C1<>
9C1<>
9C1<>
9C1<>
7A3<
8D1<
45D2<>
8A3<>
6C5<
7C3<
44B7<
8C5<>
8C4<>
8C8<>
8C8<>
8C5<>
8C7<>
8D7<>
8C5<>
44D1<
8A3<>
59C8>
8D7<>
8D8<>
8D8<>
8D7<>
8D4<>
6D6<
4D5<
7B3<
9B7<
59C8>
8
5B4<>
5B4<>
5B4<>
5B4<>
5B4<>
5B4<>
5B4<>
5B4<>
52C6>
+MAXBUS_SLEEP
CPU_DATA<48>
CPU_DATA<49>
CPU_DATA<50>
CPU_DATA<51>
CPU_DATA<52>
CPU_DATA<53>
CPU_DATA<54>
CPU_DATA<55>
44B7<
6C5<
4D5<
7C7<
7C5<
46D4<
CPU_DATA<32>
5C4<>
CPU_DATA<33>
5C4<>
CPU_DATA<34>
5C4<>
CPU_DATA<35>
5C4<>
CPU_DATA<36>
5C4<>
INTREPID BOOT STRAPS
NOSTUFF
1
R890
10K
1%
1/16W
MF
402
2
NOSTUFF
R864
10K
1%
1/16W
MF
402
1
R894
4.7K
5%
1/16W
MF
402
2
R359
4.7K
5%
1/16W
MF
402
1: EXTERNAL SOURCE
1: ACTIVE
+MAXBUS_SLEEP
0: INACTIVE
0: PLL5
BUF_REF_CLK_OUTENABLE_H
BITS 32 - 39
NOSTUFF
1
R833
10K
1%
1/16W
MF
402
2
1
R342
4.7K
5%
1/16W
MF
402
2
0: TDI INPUT (JTAG)
DDR_TPDMODEENABLE_H
1: TDI OUTPUT
78
NOSTUFF
1
R868
10K
1%
1/16W
MF
402
2
1
2
1
2
NOSTUFF
R876
1/16W
NOSTUFF
1
R355
4.7K
5%
1/16W
MF
402
2
R366
4.7K
1/16W
1: BOOTROM ON PCI1
0: BOOTROM ON IDE/CARDSLOT
EN_PCI_ROM_P
SELPLL4EXTSRC
1
2
INT_V1
1
R854
10K
1%
1/16W
MF
402
2
1
INT_V2
R353
4.7K
1/16W
2
1
5%
MF
402
2
1: ACTIVE
0: INACTIVE
1: ACTIVE LOW
ANALYZERCLK_EN_H
1
R892
10K
1%
1/16W
MF
402
2
1
10K
1%
MF
402
2
1
R893
4.7K
5%
1/16W
MF
402
2
1
5%
MF
402
2
TI 1394B WORKAROUND
0: NORMAL 1394B
1: TI PHY WORKAROUND
MAXBUS OUTPUT
IMPEDANCE
111: 28.6 OHM
011: 33.3 OHM
101: 40 OHM
001: 50 OHM
110: 66.6 OHM
010: 100 OHM
100: 200 OHM
000: 200 OHM
NOSTUFF
R852
10K
1%
1/16W
MF
402
NOSTUFF
1
R853
10K
1%
1/16W
MF
402
2
R345
4.7K
5%
1/16W
MF
402
1
R344
4.7K
5%
1/16W
MF
402
2
0: ACTIVE HIGH
0: ACTIVE HIGH
DDR_TPDEN_POL
1: ACTIVE LOW
BITS 48 - 63
1
R832
10K
1%
1/16W
MF
402
10K
1%
MF
402
5%
MF
402
NOSTUFF
R862
10K
1%
1/16W
MF
402
R861
4.7K
5%
1/16W
MF
402
2
1
2
NOSTUFF
1
R343
4.7K
5%
1/16W
MF
402
2
1
2
NOSTUFF
R865
1/16W
R358
4.7K
1/16W
1
2
1
2
EXTPLL_SDWN_POL
SPARE
NOSTUFF
R885
10K
1/16W
R886
4.7K
1/16W
4C3<
5D4<>
5D4<>
5D4<>
5D4<>
5D4<>
5D4<>
5D4<>
5D4<>
5D4<>
5D4<>
4C3<
4C2<
4C3<
4C3<
4C3<
4C3<
SHT
5D4<>
5C4<>
5C4<>
5C4<>
5C4<>
5C4<>
5C4<>
5C4<>
5C4<>
5C4<>
5C4<>
5C4<>
5C4<>
5C4<>
5C4<>
5C4<>
5C4<>
5C4<>
5C4<>
5C4<>
5C4<>
5C4<>
5C4<>
5C4<>
5C4<>
5C4<>
5C4<>
5B4<>
5B4<>
5B4<>
5B4<>
5B4<>
5B4<>
5B4<>
5B4<>
5B4<>
5B4<>
5B4<>
5B4<>
5B4<>
5B4<>
5B4<>
5B4<>
5B4<>
5B4<>
5B4<>
5B4<>
5B4<>
5B4<>
5B4<>
5B4<>
5B4<>
5B4<>
5A4<>
7C7<
9
12
7B7<
7B7<
8B7<>
8B4<>
8B4<>
7B7<
1
8C4<>
8C7<>
8C8<>
8C5<>
8C7<>
8C8<>
8C4<>
8C8<>
8C5<>
8C4<>
8C7<>
8C5<>
8C5<>
8C7<>
8C8<>
8C5<>
8C4<>
8C7<>
8C4<>
8C4<>
8C4<>
8C8<>
8C7<>
8C8<>
8D4<>
8D7<>
8C5<>
8C7<>
8D8<>
8C8<>
8C5<>
8D7<>
8D7<>
8D8<>
8D8<>
8D7<>
8D4<>
8D5<>
8D5<>
8D5<>
6C4<
6C4<
6C4<
6C4<
6C4<
6C4<
6C4<
6C4<
8C5<>
8C4<>
8C8<>
8C8<>
8C5<>
8C7<>
8D7<>
8C5<>
8D8<>
8D5<>
8D4<>
8D8<>
8D8<>
8D4<>
8D4<>
8D5<>
8B8<>
8C4<>
8B5<>
8B5<>
56C3>
56C3>
56C3>
OF
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
9B7<
9B7<
9B7<
9B7<
9A7<
56D3>
56D3>
56D3>
8D7<>
8C4<>
8C5<>
8C4<
8C8<>
8C7<>
8C4<>
8C7<
9D8<
9D8<
9D8<
9D8<
9C8<
9C8<
9C8<
9C8<
56D3>
9D5<
9D5<
9D5<
9D5<
9C5<
9C5<
9C5<
56C3>
56C3>
56C3>
69
56C3>
REV.
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
13
D
C
B
A
DRAWING
6
NOSTUFF
1
R863
10K
1%
1/16W
MF
402
2
1
1%
MF
402
2
1
R360
4.7K
5%
1/16W
MF
402
2
1
5%
MF
402
2
SPARE
SPARE
1
R855
10K
1%
1/16W
MF
402
2
1
R352
4.7K
5%
1/16W
MF
402
NOSTUFF
R354
4.7K
1/16W
2
1
5%
MF
402
2
0: 0 IDE / 1 PCI1
ROM_Ovrly_Rng
1: 0-1 IDE / 2-3 PCI1
R351
4.7K
1/16W
0: REQ/GNT
1: GPIOs
PCI1_REQ2_L / PCI1_GNT2_L
NOSTUFF
1
R339
10K
1%
1/16W
MF
402
2
1
R338
4.7K
5%
1/16W
MF
402
2
1
5%
MF
402
2
1: GPIOS
0: REQ/GNT
0: REQ/GNT
1: GPIOs
PCI1_REQ1_L / PCI1_GNT1_L
59A8>
67
5
NOSTUFF
1
R340
10K
1%
1/16W
MF
402
NOSTUFF
R869
1/16W
R870
4.7K
1/16W
PCI1_REQ0_L / PCI1_GNT0_L
56B3>
2
1
10K
1%
MF
402
2
1
5%
MF
402
2
0: LEGACY INTERFACE
1: B-MODE INTERFACE
FIREWIRE PHY INTERFACE
54A7<
(0.35 NS)
56C3>
56C3>
56C3>
CPU_DATA<57>
CPU_DATA<58>
CPU_DATA<59>
CPU_DATA<60>
CPU_DATA<61>
CPU_DATA<62>
CPU_DATA<63>
1
R341
4.7K
5%
1/16W
MF
402
2
PROCESSOR BUS MODE
0: MAX BUS (G4)
1: 60X BUS (G3)
16C7<
CPU_FBI_PLUS1
CPU_FB_PLUS2
INT_ANALYZER_CLK
8A2<
56C3>
NOSTUFF
R321
0
1 2
5%
1/16W
MF
402
NOSTUFF
R319
0
1 2
5%
1/16W
MF
402
CPU_FBO_PLUS1
4D2<
(0.17 NS)
56C3>
5
52D3>
30D5<
SYSCLK_CPU
ADDS 1"ADDS 2"
1 2
CPU_FB_MINUS3
1
R776
0
5%
1/16W
MF
402
2
1 2
5B4<>
56D3>
5B4<>
56D3>
5B4<>
56D3>
5B4<>
56D3>
5B4<>
56D3>
5B4<>
56D3>
5A4<>
56D3>
56B3>
R777
0
5%
1/16W
MF
402
R765
0
5%
1/16W
MF
402
28D6<>
8D5<>
8D4<>
8D8<>
8D8<>
8D4<>
8D4<>
8D5<>
4
R720
4.7
+1_5V_INTREPID_PLL
16D6<
C854
0.1UF
20%
10V
CERM
402
9A2<>
INT_PLL6_GND
56D3>
8B4<>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
9B1<>
56D3>
9B1<>
56D3>
56D3>
9B1<>
56D3>
9B1<>
56D3>
9B1<>
56D3>
9B1<>
9B1<>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56C3>
56C3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56D3>
56C3>
56C3>
56C3>
8B8<>
56C3>
56C3>
R764
1 2
CPU_FB_PLUS3
ADDS 3"
NOSTUFF
(0.5 NS)
1
R772
0
5%
1/16W
MF
R310
402
2
1 2
1/16W
402
NOSTUFF
1
R757
0
5%
1/16W
MF
402
2
ALLOWS ADJUSTING FB CLOCK FROM -3" (0.5 NS)
TO +2" (0.35 NS) IN 1" (0.17 NS) INCREMENTS
PLACE ALL SERPENTINES ON INTERNAL LAYER
7C7<
8B4<>
7B7<
8B7<>
7C7<
8B4<>
4C7<>
8B5<>
4C7<>
8B4<>
4C7<>
8B8<>
4C7<>
8B5<>
4C7<>
8B7<>
4C7<>
8C4<>
4C7<>
8B7<>
4C7<>
8C5<>
4C7<>
8B8<>
4C7<>
8B8<>
4C7<>
8C4<>
4C7<>
8B7<>
4C7<>
8B8<>
4C7<>
8B7<>
4C7<>
8B7<>
4C7<>
8B8<>
4C7<>
8B8<>
4C7<>
8C8<>
4C7<>
8B7<>
4C7<>
8B8<>
4C7<>
8C7<>
4C7<>
8C7<>
4C7<>
8C8<>
4C7<>
8B7<>
4B7<>
8B8<>
4B7<>
8C8<>
4B7<>
8C8<>
4B7<>
8C7<>
4B7<>
8C8<>
4B7<>
8C7<>
4B7<>
8C7<>
4B7<>
8C5<>
7A7<
4B8<
7B7<
8B4<>
7B7<
8B5<>
8B5<>
8B7<
8B4<>
7A7<
8B5<>
7A7<
8B4<>
7A7<
8B5<>
7A7<
8B4<>
7A7<
8B5<>
7A7<
8B5<>
7B7<
7C7<
4A7<>
8B8<>
7C7<
8B7<>
7D5<
56C3>
8B4<>
INT_SUSPEND_REQ_L
44B8<>
INT_SUSPEND_ACK_L
44B5<>
INT_V1
10
5%
1/16W
MF
402
1 2
NOSTUFF
1
R766
0
2
0
5%
MF
MAIN LOOP IS 3" (0.5 NS)
SHORTER THAN MAXBUS CLOCK
CPU_BR_L
4D7>
CPU_BG_L
4D7<
CPU_TS_L
4D7<>
CPU_ADDR<0>
CPU_ADDR<1>
CPU_ADDR<2>
CPU_ADDR<3>
CPU_ADDR<4>
CPU_ADDR<5>
CPU_ADDR<6>
CPU_ADDR<7>
CPU_ADDR<8>
CPU_ADDR<9>
CPU_ADDR<10>
CPU_ADDR<11>
CPU_ADDR<12>
CPU_ADDR<13>
CPU_ADDR<14>
CPU_ADDR<15>
CPU_ADDR<16>
CPU_ADDR<17>
CPU_ADDR<18>
CPU_ADDR<19>
CPU_ADDR<20>
CPU_ADDR<21>
CPU_ADDR<22>
CPU_ADDR<23>
CPU_ADDR<24>
CPU_ADDR<25>
CPU_ADDR<26>
CPU_ADDR<27>
CPU_ADDR<28>
CPU_ADDR<29>
CPU_ADDR<30>
CPU_ADDR<31>
CPU_CI_L
4A7>
CPU_INT_GBL_L
CPU_TBST_L
4B7>
CPU_TSIZ<0>
4B7>
CPU_TSIZ<1>
4B7>
CPU_TSIZ<2>
4B7>
CPU_TT<0>
4B7<>
CPU_TT<1>
4B7<>
CPU_TT<2>
4B7<>
CPU_TT<3>
4B7<>
CPU_TT<4>
4B7<>
CPU_WT_L
4B7>
CPU_AACK_L
4A7<
CPU_ARTRY_L
CPU_HIT_L
4A7>
CPU_QREQ_L
4C3>
CPU_QACK_L
4C3<
56C3>
56C3>
INT_ANALYZER_CLKA
44C4<>
INTREPID_ACS_REF
R713
0
56C3>
5%
1/16W
MF
402
7C5<
5%
1/16W
MF
402
1
R752
470
5%
1/16W
MF
402
2
INT_CPU_FB_OUT
1 2
1
1/16W
2
INT_CPU_FB_IN
CPU_CLK_EN
SYSCLK_CPU_UF
CPU_TBEN
4C3<
4
3
5%
C1101
MF
0.1UF
402
+1_5V_INTREPID_PLL7
1
20%
10V
2
CERM
402
E29
BR
E26
BG
B27
TS
D24
A_0
D25
A_1
A27
A_2
E24
A_3
G23
A_4
B26
A_5
A26
A_6
D23
A_7
A25
A_8
E23
A_9
J22
A_10
B25
A_11
H22
A_12
G22
A_13
D22
A_14
B24
A_15
B23
A_16
E22
A_17
J21
A_18
G21
A_19
E21
A_20
A24
A_21
D21
A_22
A23
A_23
H20
A_24
B22
A_25
H21
A_26
A22
A_27
E20
A_28
B21
A_29
D20
A_30
A21
A_31
G26
CI
A29
GBL
A28
TBST
G24
TSIZ_0
H24
TSIZ_1
D26
TSIZ_2
E25
TT_0
G25
TT_1
B28
TT_2
D27
TT_3
J25
TT_4
D28
WT
B29
AACK
H23
ARTRY
B31
HIT
A32
QREQ
G27
QACK
AK9
SUSPENDREQ
AM8
SUSPENDACK
J24
CPU_FB_IN
H16 A30
CPU_FB_OUT
G8
ANALYZER_CLK
AH9
STOPCPUCLK
H13
ACS_REF
J15
CPU_CLK
A31
TBEN
1
R712
1K
9D3<
INT_PLL6_GND
2
1%
1/16W
MF
402
3
52D3>
H26
VDD15A_7
(PLL6)
U25
INTREPID
BGA
SEE_TABLE
(ON PAGE 12)
(1 OF 9)
MAXBUS
INTERFACE
VSSA_7
(PLL6)
H25
NO_TEST
XW47
SM
INTREPID V1.1 IS 133MHZ ONLY
2
1
APPLE COMPUTER INC.
2
D10
D_0
G12
D_1
E11
D_2
H11
D_3
B9
D_4
B8
D_5
A9
D_6
A8
D_7
E12
D_8
D11
D_9
B10
D_10
J13
D_11
A10
D_12
D12
D_13
E13
D_14
G13
D_15
B11
D_16
D13
D_17
A11
D_18
G14
D_19
H14
D_20
E14
D_21
B12
D_22
G15
D_23
B13
D_24
H15
D_25
D14
D_26
B14
D_27
A12
D_28
G16
D_29
E15
D_30
J16
D_31
D15
D_32
A14
D_33
A13
D_34
D16
D_35
E16
D_36
G17
D_37
B15
D_38
H17
D_39
A15
D_40
B16
D_41
E17
D_42
A16
D_43
J18
D_44
H18
D_45
D17
D_46
G18
D_47
A17
D_48
B17
D_49
E18
D_50
B18
D_51
D18
D_52
A18
D_53
A19
D_54
H19
D_55
B19
D_56
J19
D_57
A20
D_58
D19
D_59
E19
D_60
G19
D_61
B20
D_62
G20
D_63
DBG
G28
DRDY
K25
DTI_0
D29
DTI_1
B30
DTI_2
E27
TA
E28
TEA
VIN = INTREPID VCORE (1.7V)
VOUT = MAXBUS RAIL (1.8V)
CPU_DATA<0>
CPU_DATA<1>
CPU_DATA<2>
CPU_DATA<3>
CPU_DATA<4>
CPU_DATA<5>
CPU_DATA<6>
CPU_DATA<7>
CPU_DATA<8>
CPU_DATA<9>
CPU_DATA<10>
CPU_DATA<11>
CPU_DATA<12>
CPU_DATA<13>
CPU_DATA<14>
CPU_DATA<15>
CPU_DATA<16>
CPU_DATA<17>
CPU_DATA<18>
CPU_DATA<19>
CPU_DATA<20>
CPU_DATA<21>
CPU_DATA<22>
CPU_DATA<23>
CPU_DATA<24>
CPU_DATA<25>
CPU_DATA<26>
CPU_DATA<27>
CPU_DATA<28>
CPU_DATA<29>
CPU_DATA<30>
CPU_DATA<31>
CPU_DATA<32>
CPU_DATA<33>
CPU_DATA<34>
CPU_DATA<35>
CPU_DATA<36>
CPU_DATA<37>
CPU_DATA<38>
CPU_DATA<39>
CPU_DATA<40>
CPU_DATA<41>
CPU_DATA<42>
CPU_DATA<43>
CPU_DATA<44>
CPU_DATA<45>
CPU_DATA<46>
CPU_DATA<47>
CPU_DATA<48>
CPU_DATA<49>
CPU_DATA<50>
CPU_DATA<51>
CPU_DATA<52>
CPU_DATA<53>
CPU_DATA<54>
CPU_DATA<55>
CPU_DATA<56>
CPU_DATA<57>
CPU_DATA<58>
CPU_DATA<59>
CPU_DATA<60>
CPU_DATA<61>
CPU_DATA<62>
CPU_DATA<63>
CPU_DBG_L
CPU_DRDY_L
CPU_DTI<0>
CPU_DTI<1>
CPU_DTI<2>
CPU_TA_L
CPU_TEA_L
INTREPID MAX
NOTICE OF PROPRIETARY PROPERTY
LAST_MODIFIED=Wed Sep 17 12:15:46 2003
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
051-6497
SCALE
NONE
<XR_PAGE_TITLE>
D
C
B
A
INTREPID 1.1 SHOULD ALLOW MAXBUS
RAIL TO TURN OFF IN SLEEP
C12
C15
C18
C21
C24
C27
C30
C9
F12
F15
F18
F21
F24
F27
VDD1.8/CPUVIO
M15
M16
M19
M22
M23
N18
N21
N23
P16
P19
INTREPID
POWER/GROUND
L24
M14
M17
M18
M20
M21
M24
M28
M3
M31
M32
M34
M6
M9
N15
N25
P12
P17
P22
P29
P4
R14
VSS
R16
R18
R19
R21
R23
R24
R26
R29
R3
R31
R34
R6
T11
T14
T23
T24
T27
U10
U16
J6
F6G7J3
F34
J31
J34
8
U25
BGA
(8 OF 9)
SEE_TABLE
F3
F31
SHT
12
1
EMI-SPRING
INT_V1
1
SP4
CLIP-SM
SEE_TABLE
OF
6910
D
C
B
A
REV.
13
DRAWING
3
SP3
1
CLIP-SM
EMI-SPRING
SEE_TABLE
?
DESCRIPTION REFERENCE DES BOM OPTIONQTYPART NUMBER CRITICAL
4
INTREPID EMI CLIP
DESCRIPTION REFERENCE DES BOM OPTIONQTYPART NUMBER CRITICAL
IC,ASIC,INTREPID,V1.X
1
IC,ASIC,INTREPID,V2.1
1
SP1
1
CLIP-SM
EMI-SPRING
SEE_TABLE
1
CLIP-SM
EMI-SPRING
SEE_TABLE
CLIPS TO ATTACH INTREPID
HEATSINK TO GND AT THE
FOUR CORNERS
INTREPID EMI CLIP SUPPORT
SP1,SP2,SP3,SP4
INTREPID VERSION SUPPORT
U25
U25 INT_V2CRITICAL
SP2
INTREPID POWER
NOTICE OF PROPRIETARY PROPERTY
LAST_MODIFIED=Wed Sep 17 12:15:48 2003
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
APPLE COMPUTER INC.
3
2
051-6497
SCALE
NONE
52C3>
59C8>
78
46B4<>
17D5< 17A4< 17A3<
47B2<>
46B3<
16D7<
+INTREPID_CORE_MAIN
11D3<
16C2<
16A8<
11A6<
59C8>
6
+1_5V_AGP
5
+3V_MAIN
4
+2_5V_MAIN+1_8V_MAIN
AE3
AE6
AH3
AB3
AB6
AC11
AC12
AC15A3AC16
AC13
AC18
F30
AC20
F7F9G3
AC22
G6
VDD3.3
AC26
AD12
AD23
AC14
AD25
AD21
AE15
AE17
AD20
AE20
AE23
AF22
AH19
AA25
AA29
AB25
AB27
AB31
AB34
AC25
AC27
AC28
AE31
AE34
AF28
AH30
AH34
AK34
AP35
C35
G31
G34
K31
K34
N28
VDD2.5
N31
N34
N36
P25
P28
R25
R27
T25
T28
T29
T31
T34
U25
U28
V25
V29
W25
W31
W34
Y27
Y29
E33
AN33
AN4
AP1
AP12
AP15
AP18
AP21
AP24
AP27
AP3
AP30
AP33
AP34
AP36
AP6
AP9
VSS
AR2
AR35
AT3
AT34
B2
B35
C1
C10
C13
C16
C19
C22
C25
C28
C3
C31
C34
C7
D4
C36
D33
F10
F13
F16
F19
F22
F25
F28
AA21
AA24
AB13
AB15
AB17
AB19
AC17
AC19
AC23
AD13
AD15
AD22
AD28
AD31
AD34
AE14
AE16
AE18
AE19
AE21
AE22
AE28
AG21
AG23
AG24
AG30
AG34
AH20
AH21
AH23
AH27
AL12
AL15
AL18
AL21
AL27
AL31
AL34
P15
P18
P20
P21
R17
R20
T13
U17
U18
U24
V16
V19
V20
V22
W16
W24
Y13
Y18
AD3
AD6
AG3
AG6
AK3
AK7
AL6
AL9
VDD1.5
VSS
AH22
67
AH28
AJ21
AJ23
AL19
AGP_IO_VDD
AL22
A34
AL28
AA20
AL30
AA27
AN32
AA3
AP19
AA31
AP22
AA34
AP25
AA6
AP28
AB11
5
AP31
AR33
AR34
U25
INTREPID
BGA
(9 OF 9)
SEE_TABLE
POWER
GROUND
AGP_IO_VSS
AB12
AB14
AB16
AB18
AB24
AA11
AB28
AA12
AB29
AH6
AK6
AF25
AL10
AL13
AL16
AL3
AL7
AM4
VDD3.3
VSS
AN5
AP10
AP13
AP16
K3
K6
N24
N3
N6
P13
P14
R22
T12
T18
T3
T6
U12
W12
W13
W3
W6
AP2
AP7
AR3
B3
C2
C6
D32
D5
B34
E4
U19
U22
U27
U29
V10
V12
V17
V18
V21
V24
V3
V31
V34
V6
W11
W14
W23
W26
Y11
Y12
Y14
Y16
Y19
Y23
Y24
Y25
870-1125
343S0198
343S0211
4
<XR_PAGE_TITLE>
+1_8V_MAIN
78
INTREPID MAXBUS DECOUPLING
6
24 Balls
4 X 10UF (0805)
36 X 0.1UF (0402)
5
4
INTREPID CORE DECOUPLING
59C8>
47B2<>
46B3<
+INTREPID_CORE_MAIN
10D6<
3
30 Balls
4 X 10UF (0805)
29 X 0.1UF (0402)
12
C291
10UF
N20P80%
C290
10UF
N20P80%
1
10V
2
Y5V
805
1
10V
2
Y5V
805
1
C289
10UF
N20P80%
10V
2
Y5V
805
D
C288
10UF
N20P80%
1
10V
2
Y5V
805
1
2
1
2
1
2
1
2
C890
0.1UF
20%
10V
CERM
402
C901
0.1UF
20%
10V
CERM
402
C846
0.1UF
20%
10V
CERM
402
C902
0.1UF
20%
10V
CERM
402
+2_5V_MAIN
INTREPID DDR DECOUPLING
C
C277
10UF
N20P80%
C240
10UF
N20P80%
1
10V
2
Y5V
805
1
10V
2
Y5V
805
C271
10UF
N20P80%
C641
10UF
N20P80%
1
10V
2
Y5V
805
1
10V
2
Y5V
805
1
2
1
2
C700
0.1UF
20%
10V
CERM
402
C837
0.1UF
20%
10V
CERM
402
1
2
1
2
1
2
1
C878
0.1UF
2
1
C877
0.1UF
2
C832
0.1UF
20%
10V
CERM
402
C885
0.1UF
20%
10V
CERM
402
C843
0.1UF
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
1
2
1
2
1
2
1
2
1
2
C900
0.1UF
20%
10V
CERM
402
C823
0.1UF
20%
10V
CERM
402
C887
0.1UF
20%
10V
CERM
402
C725
0.1UF
20%
10V
CERM
402
C688
0.1UF
20%
10V
CERM
402
1
2
1
2
1
2
1
2
1
2
1
2
C888
0.1UF
20%
10V
CERM
402
C845
0.1UF
20%
10V
CERM
402
C870
0.1UF
20%
10V
CERM
402
C278
0.1UF
20%
10V
CERM
402
C836
0.1UF
20%
10V
CERM
402
C767
0.1UF
20%
10V
CERM
402
1
2
1
2
1
2
1
2
1
2
1
2
C891
0.1UF
20%
10V
CERM
402
C871
0.1UF
20%
10V
CERM
402
C897
0.1UF
20%
10V
CERM
402
C849
0.1UF
20%
10V
CERM
402
C817
0.1UF
20%
10V
CERM
402
C793
0.1UF
20%
10V
CERM
402
1
C844
0.1UF
20%
10V
2
CERM
402
1
C834
0.1UF
20%
10V
2
CERM
402
1
C889
0.1UF
20%
10V
2
CERM
402
1
C281
0.1UF
20%
10V
2
CERM
402
44 Balls
4 X 10UF (0805)
51 X 0.1UF (0402)
1
C839
0.1UF
20%
10V
2
CERM
402
1
C815
0.1UF
20%
10V
2
CERM
402
1
2
1
2
1
2
1
2
1
2
1
2
C824
0.1UF
20%
10V
CERM
402
C884
0.1UF
20%
10V
CERM
402
C842
0.1UF
20%
10V
CERM
402
C280
0.1UF
20%
10V
CERM
402
C857
0.1UF
20%
10V
CERM
402
C904
0.1UF
20%
10V
CERM
402
1
2
1
2
1
2
1
2
1
2
1
2
C872
0.1UF
20%
10V
CERM
402
C896
0.1UF
20%
10V
CERM
402
C895
0.1UF
20%
10V
CERM
402
C279
0.1UF
20%
10V
CERM
402
C794
0.1UF
20%
10V
CERM
402
C827
0.1UF
20%
10V
CERM
402
1
2
1
2
1
2
1
2
1
2
C874
0.1UF
20%
10V
CERM
402
C898
0.1UF
20%
10V
CERM
402
C869
0.1UF
20%
10V
CERM
402
C855
0.1UF
20%
10V
CERM
402
C876
0.1UF
20%
10V
CERM
402
1
2
1
2
1
2
1
2
1
2
C899
0.1UF
20%
10V
CERM
402
C886
0.1UF
20%
10V
CERM
402
C873
0.1UF
20%
10V
CERM
402
C880
0.1UF
20%
10V
CERM
402
C698
0.1UF
20%
10V
CERM
402
C702
10UF
N20P80%
C292
10UF
N20P80%
+3V_MAIN
C655
10UF
N20P80%
C892
10UF
N20P80%
C727
10UF
N20P80%
C841
10UF
N20P80%
1
10V
2
Y5V
805
1
10V
2
Y5V
805
1
10V
2
Y5V
805
1
10V
2
Y5V
805
1
2
1
2
1
2
C787
0.1UF
20%
10V
CERM
402
C764
0.1UF
20%
10V
CERM
402
C746
0.1UF
20%
10V
CERM
402
INTREPID 3.3V DECOUPLING
C264
10UF
N20P80%
C637
10UF
N20P80%
1
10V
2
Y5V
805
1
10V
2
Y5V
805
1
10V
2
Y5V
805
1
10V
2
Y5V
805
1
2
1
2
1
2
C745
0.1UF
20%
10V
CERM
402
C796
0.1UF
20%
10V
CERM
402
C720
0.1UF
20%
10V
CERM
402
1
2
1
2
1
2
1
2
1
2
1
2
C789
0.1UF
20%
10V
CERM
402
C831
0.1UF
20%
10V
CERM
402
C730
0.1UF
20%
10V
CERM
402
C830
0.1UF
20%
10V
CERM
402
C867
0.1UF
20%
10V
CERM
402
C728
0.1UF
20%
10V
CERM
402
1
2
1
2
1
2
1
2
1
2
1
2
C749
0.1UF
20%
10V
CERM
402
C833
0.1UF
20%
10V
CERM
402
C721
0.1UF
20%
10V
CERM
402
C775
0.1UF
20%
10V
CERM
402
C866
0.1UF
20%
10V
CERM
402
C809
0.1UF
20%
10V
CERM
402
1
2
1
2
1
2
1
2
C797
C765
C788
C717
C680
0.1UF
20%
10V
CERM
402
0.1UF
20%
10V
CERM
402
0.1UF
20%
10V
CERM
402
0.1UF
20%
10V
CERM
402
0.1UF
20%
10V
CERM
402
1
2
1
2
1
2
1
2
1
2
1
2
1
C719
0.1UF
20%
10V
CERM
402
C808
0.1UF
20%
10V
CERM
402
C734
0.1UF
20%
10V
CERM
402
C829
0.1UF
20%
10V
CERM
402
C863
0.1UF
20%
10V
CERM
402
C894
0.1UF
20%
10V
CERM
402
C800
0.1UF
20%
10V
2
CERM
402
1
C763
0.1UF
20%
10V
2
CERM
402
1
C748
0.1UF
20%
10V
2
CERM
402
57 Balls
4 X 10UF (0805)
66 X 0.1UF (0402)
1
C806
0.1UF
20%
10V
2
CERM
402
1
C868
0.1UF
20%
10V
2
CERM
402
1
C643
0.1UF
20%
10V
2
CERM
402
1
2
1
2
1
2
1
2
1
2
1
2
C810
0.1UF
20%
10V
CERM
402
C780
0.1UF
20%
10V
CERM
402
C811
0.1UF
20%
10V
CERM
402
C691
0.1UF
20%
10V
CERM
402
C812
0.1UF
20%
10V
CERM
402
C656
0.1UF
20%
10V
CERM
402
1
2
1
2
1
2
1
2
1
2
C766
0.1UF
20%
10V
CERM
402
C798
0.1UF
20%
10V
CERM
402
C747
0.1UF
20%
10V
CERM
402
C821
0.1UF
20%
10V
CERM
402
C689
0.1UF
20%
10V
CERM
402
1
2
1
2
1
2
1
2
1
2
1
2
C731
C779
C799
C762
C822
C774
0.1UF
20%
10V
CERM
402
0.1UF
20%
10V
CERM
402
0.1UF
20%
10V
CERM
402
0.1UF
20%
10V
CERM
402
0.1UF
20%
10V
CERM
402
0.1UF
20%
10V
CERM
402
1
2
1
2
1
2
1
2
1
2
C732
0.1UF
20%
10V
CERM
402
C790
0.1UF
20%
10V
CERM
402
C777
0.1UF
20%
10V
CERM
402
C893
0.1UF
20%
10V
CERM
402
C828
0.1UF
20%
10V
CERM
402
D
C
1
C850
C697
0.1UF
20%
10V
CERM
402
1
2
1
2
1
2
C792
0.1UF
20%
10V
CERM
402
C755
0.1UF
20%
10V
CERM
402
C814
0.1UF
20%
10V
CERM
402
1
2
1
2
1
2
1
2
C687
0.1UF
20%
10V
CERM
402
C791
0.1UF
20%
10V
CERM
402
C816
0.1UF
20%
10V
CERM
402
1
2
C231
10UF
N20P80%
1
C750
0.1UF
20%
10V
2
CERM
402
1
C723
0.1UF
20%
10V
2
CERM
402
1
C752
0.1UF
20%
10V
2
CERM
402
INTREPID AGP I/O DECOUPLING
1
10V
2
Y5V
805
16C2<
1
C735
0.1UF
2
1
C825
0.1UF
2
1
C751
0.1UF
2
16A8<
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
1
C856
0.1UF
20%
10V
2
CERM
402
1
C801
0.1UF
20%
10V
2
CERM
402
B
52C3>
46B4<>
17D5< 17A4< 17A3<
1
2
1
2
C699
0.1UF
20%
10V
CERM
402
C782
0.1UF
20%
10V
CERM
402
16D7<
10D6<
59C8>
1
C722
0.1UF
20%
10V
2
CERM
402
1
C838
0.1UF
20%
10V
2
CERM
402
1
C826
0.1UF
20%
10V
2
CERM
402
+1_5V_AGP
C232
10UF
N20P80%
1
C753
0.1UF
20%
10V
2
CERM
402
1
C803
0.1UF
20%
10V
2
CERM
402
1
C768
0.1UF
20%
10V
2
CERM
402
1
10V
2
Y5V
805
C693
0.1UF
20%
10V
CERM
402
1
2
1
2
1
2
C668
0.1UF
20%
10V
CERM
402
C818
0.1UF
20%
10V
CERM
402
C754
0.1UF
20%
10V
CERM
402
1
C684
0.1UF
20%
10V
2
CERM
402
1
2
1
2
1
2
C714
0.1UF
20%
10V
CERM
402
C802
0.1UF
20%
10V
CERM
402
C724
0.1UF
20%
10V
CERM
402
1
C686
0.1UF
20%
10V
2
CERM
402
1
2
1
2
1
2
C736
0.1UF
20%
10V
CERM
402
C813
0.1UF
20%
10V
CERM
402
C781
0.1UF
20%
10V
CERM
402
1
C709
0.1UF
20%
10V
2
CERM
402
21 Balls
4 X 10UF (0805)
24 X 0.1UF (0402)
1
2
C649
0.1UF
20%
10V
CERM
402
1
2
C667
0.1UF
20%
10V
CERM
402
1
2
C694
0.1UF
20%
10V
CERM
402
1
C695
0.1UF
20%
10V
2
CERM
402
2
1
2
1
2
1
2
0.1UF
20%
10V
CERM
402
C835
0.1UF
20%
10V
CERM
402
C708
0.1UF
20%
10V
CERM
402
C657
0.1UF
20%
10V
CERM
402
1
2
1
2
1
2
1
2
C664
0.1UF
20%
10V
CERM
402
C743
0.1UF
20%
10V
CERM
402
C729
0.1UF
20%
10V
CERM
402
C681
0.1UF
20%
10V
CERM
402
C851
0.1UF
20%
10V
CERM
402
1
2
1
2
1
2
1
2
C761
0.1UF
20%
10V
CERM
402
C881
0.1UF
20%
10V
CERM
402
C678
0.1UF
20%
10V
CERM
402
C875
0.1UF
20%
10V
CERM
402
1
2
1
2
1
2
1
2
C707
C676
C682
C659
0.1UF
20%
10V
CERM
402
0.1UF
20%
10V
CERM
402
0.1UF
20%
10V
CERM
402
0.1UF
20%
10V
CERM
402
1
2
1
2
1
2
1
2
C883
0.1UF
20%
10V
CERM
402
C716
0.1UF
20%
10V
CERM
402
C879
0.1UF
20%
10V
CERM
402
C690
0.1UF
20%
10V
CERM
402
1
2
1
2
1
2
1
2
C807
0.1UF
20%
10V
CERM
402
C805
0.1UF
20%
10V
CERM
402
C903
0.1UF
20%
10V
CERM
402
C658
0.1UF
20%
10V
CERM
402
1
2
1
2
1
2
1
2
C776
0.1UF
20%
10V
CERM
402
C644
0.1UF
20%
10V
CERM
402
C673
0.1UF
20%
10V
CERM
402
C852
0.1UF
20%
10V
CERM
402
1
2
1
2
1
2
1
2
C744
0.1UF
20%
10V
CERM
402
C645
0.1UF
20%
10V
CERM
402
C679
0.1UF
20%
10V
CERM
402
C646
0.1UF
20%
10V
CERM
402
C718
0.1UF
20%
10V
CERM
402 402
1
C865
0.1UF
20%
10V
2
CERM
402
1
C677
0.1UF
20%
10V
2
CERM
402
1
2
1
2
1
2
C712
0.1UF
20%
10V
CERM
C882
0.1UF
20%
10V
CERM
402
C660
0.1UF
20%
10V
CERM
402
B
INTREPID BYPASS
1
2
1
2
C685
0.1UF
20%
10V
CERM
402
C711
0.1UF
20%
10V
CERM
402
5
1
C710
0.1UF
2
1
C674
0.1UF
2
20%
10V
CERM
402
20%
10V
CERM
402
A
C638
10UF
N20P80%
1
10V
2
Y5V
805
C628
10UF
N20P80%
1
10V
2
Y5V
805
8
1
C733
0.1UF
20%
10V
2
CERM
402
1
C662
0.1UF
20%
10V
2
CERM
402
67
1
2
1
2
C650
C661
0.1UF
20%
10V
CERM
402
0.1UF
20%
10V
CERM
402
1
2
1
2
C647
0.1UF
20%
10V
CERM
402
C648
0.1UF
20%
10V
CERM
402
1
2
1
2
C683
0.1UF
20%
10V
CERM
402
C663
0.1UF
20%
10V
CERM
402
1
2
C665
0.1UF
20%
10V
CERM
402
1
2
C696
0.1UF
20%
10V
CERM
402
1
C666
0.1UF
20%
10V
2
CERM
402
4
1
2
C651
0.1UF
20%
10V
CERM
402
NOTICE OF PROPRIETARY PROPERTY
LAST_MODIFIED=Wed Sep 17 12:15:51 2003
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
APPLE COMPUTER INC.
3
2
051-6497
SCALE
NONE
SHT
11
1
REV.
OF
69
A
13
DRAWING
<XR_PAGE_TITLE>
78
6
5
DDR MUX CONNECTIONS
0-ohm resistors to allow
rewiring if necessary
4
SERIES RESISTORS FOR CONTROL SIGNALS
3
12
MUX_SEL_H
H35
13C8<>
13C8<>
13C8<>
13C8<>
13C8<>
13C8<>
13C8<>
13C8<>
13C8<>
13C8<>
13C8<>
13C8<>
13C8<>
13C8<>
13C8<>
13C8<>
13B6<>
13B6<>
13B6<>
13B6<>
13B6<>
13B6<>
13B6<>
13B6<>
13A6<>
13A6<>
13A6<>
13A6<>
13A6<>
13A6<>
13A6<>
13A6<>
13C4<>
13C4<>
13C4<>
13C4<>
13C4<>
13C4<>
13C4<>
13C4<>
13C4<>
13C4<>
13C4<>
13C4<>
13C4<>
13C4<>
13C4<>
13C4<>
13B3<>
13B3<>
13B3<>
13B3<>
13B3<>
13B3<>
13B3<>
13B3<>
13B3<>
13B3<>
13B3<>
13B3<>
13B3<>
13B3<>
13B3<>
13B3<>
MEM_DATA<0>
MEM_DATA<1>
MEM_DATA<2>
MEM_DATA<3>
MEM_DATA<4>
MEM_DATA<5>
MEM_DATA<6>
MEM_DATA<7>
MEM_DATA<8>
MEM_DATA<9>
MEM_DATA<10>
MEM_DATA<11>
MEM_DATA<12>
MEM_DATA<13>
MEM_DATA<14>
MEM_DATA<15>
MEM_DATA<16>
MEM_DATA<17>
MEM_DATA<18>
MEM_DATA<19>
MEM_DATA<20>
MEM_DATA<21>
MEM_DATA<22>
MEM_DATA<23>
MEM_DATA<24>
MEM_DATA<25>
MEM_DATA<26>
MEM_DATA<27>
MEM_DATA<28>
MEM_DATA<29>
MEM_DATA<30>
MEM_DATA<31>
MEM_DATA<32>
MEM_DATA<33>
MEM_DATA<34>
MEM_DATA<35>
MEM_DATA<36>
MEM_DATA<37>
MEM_DATA<38>
MEM_DATA<39>
MEM_DATA<40>
MEM_DATA<41>
MEM_DATA<42>
MEM_DATA<43>
MEM_DATA<44>
MEM_DATA<45>
MEM_DATA<46>
MEM_DATA<47>
MEM_DATA<48>
MEM_DATA<49>
MEM_DATA<50>
MEM_DATA<51>
MEM_DATA<52>
MEM_DATA<53>
MEM_DATA<54>
MEM_DATA<55>
MEM_DATA<56>
MEM_DATA<57>
MEM_DATA<58>
MEM_DATA<59>
MEM_DATA<60>
MEM_DATA<61>
MEM_DATA<62>
MEM_DATA<63>
INT_MEM_VREF
14A1<
53D6<
53D6<
53D6<
53D6<
D
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
C
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
B
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
AK32
AK33
AK31
AK35
AK36
AJ32
AJ35
AJ36
AG33
AG35
AH35
AG36
AH36
AH32
AG32
AG31
AE32
AF35
AF36
AE36
AE35
AE33
AD36
AD35
AA36
AA35
AA33
AB36
AB35
AC36
AA32
AB33
V36
U33
U32
V35
T30
U36
U35
T36
P33
R30
P35
P36
R36
R35
R33
R32
N35
M36
L35
M35
M33
L36
N33
M30
J32
J33
J35
K32
K33
J36
K36
K35
DDR_DATA_0
DDR_DATA_1
DDR_DATA_2
DDR_DATA_3
DDR_DATA_4
DDR_DATA_5
DDR_DATA_6
DDR_DATA_7
DDR_DATA_8
DDR_DATA_9
DDR_DATA_10
DDR_DATA_11
DDR_DATA_12
DDR_DATA_13
DDR_DATA_14
DDR_DATA_15
DDR_DATA_16
DDR_DATA_17
DDR_DATA_18
DDR_DATA_19
DDR_DATA_20
DDR_DATA_21
DDR_DATA_22
DDR_DATA_23
DDR_DATA_24
DDR_DATA_25
DDR_DATA_26
DDR_DATA_27
DDR_DATA_28
DDR_DATA_29
DDR_DATA_30
DDR_DATA_31
DDR_DATA_32
DDR_DATA_33
DDR_DATA_34
DDR_DATA_35
DDR_DATA_36
DDR_DATA_37
DDR_DATA_38
DDR_DATA_39
DDR_DATA_40
DDR_DATA_41
DDR_DATA_42
DDR_DATA_43
DDR_DATA_44
DDR_DATA_45
DDR_DATA_46
DDR_DATA_47
DDR_DATA_48
DDR_DATA_49
DDR_DATA_50
DDR_DATA_51
DDR_DATA_52
DDR_DATA_53
DDR_DATA_54
DDR_DATA_55
DDR_DATA_56
DDR_DATA_57
DDR_DATA_58
DDR_DATA_59
DDR_DATA_60
DDR_DATA_61
DDR_DATA_62
DDR_DATA_63
U25
INTREPID
BGA
(2 OF 9)
SEE_TABLE
(ON PAGE 12)
DDR
MEMORY
INTERFACE
MIN_LINE_WIDTH=25
+2_5V_MAIN
1
R82
100
A
1%
1/16W
MF
402
2
1
R93
2
MIN_LINE_WIDTH=20
LOCATE THESE RESISTORS NEAR INTREPID
100
1%
1/16W
MF
402
DDR_VREF
14D2<>
DDR_A_0
DDR_A_1
DDR_A_2
DDR_A_3
DDR_A_4
DDR_A_5
DDR_A_6
DDR_A_7
DDR_A_8
DDR_A_9
DDR_A_10
DDR_A_11
DDR_A_12
DDR_BA_0
DDR_BA_1
DDRCS_0
DDRCS_1
DDRCS_2
DDRCS_3
DDR_DQS_0
DDR_DQS_1
DDR_DQS_2
DDR_DQS_3
DDR_DQS_4
DDR_DQS_5
DDR_DQS_6
DDR_DQS_7
DDR_DM_0
DDR_DM_1
DDR_DM_2
DDR_DM_3
DDR_DM_4
DDR_DM_5
DDR_DM_6
DDR_DM_7
DDRRAS
DDRCAS
DDRCKE0
DDRCKE1
DDRCKE2
DDRCKE3
DDR_SELHI_0
DDR_SELHI_1
DDR_SELLO_0
DDR_SELLO_1
DDR_MCLK_0_P
DDR_MCLK_0_N
DDR_MCLK_1_P
DDR_MCLK_1_N
DDR_MCLK_2_P
DDR_MCLK_2_N
DDR_MCLK_3_P
DDR_MCLK_3_N
DDR_MCLK_4_P
DDR_MCLK_4_N
DDR_MCLK_5_P
DDR_MCLK_5_N
DDR_REF
DDR_VREF_0
DDR_VREF_1
15D8<
14D8<>
DDRWE
1
C14
0.1UF
20%
10V
2
CERM
402
LOCATE 2 DECOUPLING CAPS
DIRECTLY AT DDR_VREF_X BALLS
(U25-Y22 & T22)
52A6>
MEM_ADDR<0>
G35
MEM_ADDR<1>
G36
MEM_ADDR<2>
F36
MEM_ADDR<3>
F35
MEM_ADDR<4>
E35
MEM_ADDR<5>
E36
MEM_ADDR<6>
G32
MEM_ADDR<7>
D36
MEM_ADDR<8>
H36
MEM_ADDR<9>
G33
MEM_ADDR<10>
H33
MEM_ADDR<11>
D35
MEM_ADDR<12>
L30
MEM_BA<0>
M29
MEM_BA<1>
AN34
MEM_CS_L<0>
AN36
MEM_CS_L<1>
AL35
MEM_CS_L<2>
AL33
MEM_CS_L<3>
AJ31
MEM_DQS<0>
AH31
MEM_DQS<1>
AD32
MEM_DQS<2>
AB30
MEM_DQS<3>
V30
MEM_DQS<4>
P32
MEM_DQS<5>
N29
MEM_DQS<6>
L32
MEM_DQS<7>
AJ33
MEM_DQM<0>
AH33
MEM_DQM<1>
AD33
MEM_DQM<2>
AC35
MEM_DQM<3>
T35
MEM_DQM<4>
T33
MEM_DQM<5>
N32
MEM_DQM<6>
L33
MEM_DQM<7>
L29
MEM_RAS_L
H32
MEM_CAS_L
K30
MEM_WE_L
AN35
MEM_CKE<0>
AM35
MEM_CKE<1>
AM36
MEM_CKE<2>
AL36
MEM_CKE<3>
AB32
NC_MEM_MUXSEL_H<0>
AE29
N30
NC_MEM_MUXSEL_L<0>
T32
Y32
Y33
Y35
Y36
Y30
W30
W32
W33
V33
V32
W35
W36
AA22
Y22
T22
53C6<
53C6<
NO_TEST
1
R625
1K
2
1%
1/16W
MF
402
8
12C3<
53D6<
12C3<
53D6<
12C3<
53D6<
12D3<
53D6<
12D3<
53D6<
12C2<
53D6<
12D2<
53D6<
12D3<
53D6<
12D2<
53D6<
12C3<
53D6<
12C3<
53D6<
12B3<
53D6<
12D2<
12C2<
12C2<
12B2<
12B2<
13C8<>
13C8<>
13A6<>
13A6<>
13C4<>
13C4<>
13B3<>
13B3<>
13C8<>
13C8<>
13A6<>
13A6<>
13C4<>
13C4<>
13B3<>
13B3<>
53C6<
12C2<
12B2<
12C2<
12B2<
53D6<
53D6<
53C6<
53C6<
53C6<
53C6<
53C6<
53C6<
53D6<
53C6<
53C6<
53C6<
53C6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
12B3<
12B3<
12A3<
12A3<
12B3<
MEM_MUXSEL_H<1>
MEM_MUXSEL_L<1>
SYSCLK_DDRCLK_A0_UF
53C6<
SYSCLK_DDRCLK_A0_L_UF
53C6<
SYSCLK_DDRCLK_A1_UF
53C6<
SYSCLK_DDRCLK_A1_L_UF
53C6<
53C6<
SYSCLK_DDRCLK_A2_UF
SYSCLK_DDRCLK_A2_L_UF
53B6<
SYSCLK_DDRCLK_B0_UF
53B6<
SYSCLK_DDRCLK_B0_L_UF
53B6<
SYSCLK_DDRCLK_B1_UF
53B6<
SYSCLK_DDRCLK_B1_L_UF
53B6<
53B6<
SYSCLK_DDRCLK_B2_UF
53B6<
SYSCLK_DDRCLK_B2_L_UF
INT_MEM_REF
+2_5V_MAIN
1
C30
0.1UF
20%
10V
2
CERM
402
67
MEM_MUXSEL_H<1>
MEM_MUXSEL_L<1>
SYSCLK_DDRCLK_A0_UF
SYSCLK_DDRCLK_A0_L_UF
SYSCLK_DDRCLK_A1_UF
SYSCLK_DDRCLK_A1_L_UF
SYSCLK_DDRCLK_B1_UF
SYSCLK_DDRCLK_B1_L_UF
SYSCLK_DDRCLK_B2_UF
SYSCLK_DDRCLK_B2_L_UF
R288
47
1 2
5%
1/16W
MF
402
MUX_SEL_L
R261
47
1 2
5%
1/16W
MF
402
’0’S ARE SAME POLARITY (ACTIVE LO)
SEL = 0; HOST=B PORT, A PORT = 100 OHMGND
SEL = 1; HOST=A PORT, B PORT = 100 OHMGND
SYSCLK_DDRCLK_A2_UF
SYSCLK_DDRCLK_A2_L_UF
SYSCLK_DDRCLK_B0_UF
SYSCLK_DDRCLK_B0_L_UF
’1’S ARE SAME POLARITY (ACTIVE HI)
RP102
22
1 8
5%
1/16W
SM1
RP102
22
2 7
5%
1/16W
SM1
RP102
22
3 6
5%
1/16W
SM1
RP102
22
4 5
5%
1/16W
SM1
RP105
22
1 8
5%
1/16W
SM1
RP105
22
2 7
5%
1/16W
SM1
RP105
22
3 6
5%
1/16W
SM1
RP105
22
4 5
5%
1/16W
SM1
RP109
22
4 5
5%
1/16W
SM1
RP109
22
3 6
5%
1/16W
SM1
RP109
22
1 8
5%
1/16W
SM1
RP109
22
2 7
5%
1/16W
SM1
5
13A3<>
13A6<>
SYSCLK_DDRCLK_A0
SYSCLK_DDRCLK_A0_L
SYSCLK_DDRCLK_A1
SYSCLK_DDRCLK_A1_L
NO_TEST
NC_SYSCLK_DDRCLK_A2
NO_TEST
NC_SYSCLK_DDRCLK_A2_L
SYSCLK_DDRCLK_B0
SYSCLK_DDRCLK_B0_L
SYSCLK_DDRCLK_B1
SYSCLK_DDRCLK_B1_L
SYSCLK_DDRCLK_B2
SYSCLK_DDRCLK_B2_L
13C4<>
13C8<>
4
53C6<
53C6<
14D6<>
14A4<>
15B4>
15D6<
15A6<
MEM_ADDR<2>
53C6<
53C6<
14D6<>
MEM_ADDR<0>
53C6<
MEM_ADDR<9>
53C6<
14A4<>
MEM_BA<0>
53B6<
MEM_ADDR<11>
15B3>
53B6<
53B6<
53B6<
15C6<
53B6<
15A6<
53B6<
RP68
22
1 8
5%
1/16W
SM1
RP68
22
2 7
5%
1/16W
SM1
RP68
22
3 6
5%
1/16W
SM1
RP68
22
4 5
5%
1/16W
SM1
RP62
22
1 8
5%
1/16W
SM1
RP62
22
2 7
5%
1/16W
SM1
RP62
22
3 6
5%
1/16W
SM1
RP62
22
4 5
5%
1/16W
SM1
RP116
22
1 8
5%
1/16W
SM1
RP116
22
2 7
5%
1/16W
SM1
RP116
22
3 6
5%
1/16W
SM1
RP116
22
4 5
5%
1/16W
SM1
53C6< 15B4>
12C6<> 14B4<>
53C6< 15B6<
12C6<> 14B4<>
RAM_BA<1>MEM_BA<1>
RAM_BA<0>
RAM_WE_LMEM_WE_L
RAM_ADDR<11>
MEM_RAS_L RAM_RAS_L
MEM_CAS_L RAM_CAS_L
RAM_ADDR<4>MEM_ADDR<4>
RAM_ADDR<3>MEM_ADDR<3>
RAM_ADDR<7>MEM_ADDR<7>
RAM_ADDR<10>MEM_ADDR<10>
RAM_ADDR<2>
RAM_ADDR<1>MEM_ADDR<1>
RAM_ADDR<0>
RAM_ADDR<9>
14B4<> 12D6<>
14B6<> 12D6<>
14B6<> 12C6<>
14B4<> 12D6<>
53C6<
R697
22
1 2
5%
1/16W
MF
402
R286
22
1 2
5%
1/16W
MF
402
15C6< 53D6<
14B4<> 12D6<>
12D6<> 14B6<>
53D6< 15C4>
14B6<> 12D6<>
53D6< 15C4>
14B6<> 12D6<>
53D6< 15C4>
14B6<> 12D6<>
53D6< 15C6<
14B4<> 12D6<>
53C6<
12B6<>
14B6<> 12D6<>
53C6<
12C6<>
14B4<> 12D6<>
53C6<
12C6<>
14B6<> 12D6<>
53C6<
12C6<> 14B4<>
15B6< 53D6<
53D6<
53C6<
12C6<>
15B6< 53D6<
53D6<
53C6<
12B6<>
15B6< 53C6<
53C6<
12C6<>
15C4> 53D6<
12B6<>
53D6<
MEM_ADDR<12>
15C4> 53D6<
53D6<
MEM_ADDR<8>
12D6<> 14B4<>
15C6< 53D6<
53D6<
MEM_ADDR<6>
12D6<> 14B4<>
15B4> 53D6<
53D6<
MEM_ADDR<5>
12D6<> 14B6<>
15C6< 53D6<
53D6<
MEM_CKE<2>
15B6< 53D6<
53D6<
MEM_CS_L<0>
15B6< 53D6<
53D6<
MEM_CKE<0>
15C6< 53D6<
53D6<
MEM_CS_L<1> RAM_CS_L<1>
MEM_CS_L<3>
MEM_CKE<3>
53D6<
MEM_CKE<1>
INTREPID DDR CNTRL
LAST_MODIFIED=Wed Sep 17 12:15:52 2003
APPLE COMPUTER INC.
3
2
RP71
22
1 8
2 7
3 6
4 5
RP51
1 8
RP51
2 7
RP51
3 6
RP51
22
4 5
5%
1/16W
SM1
RP52
1 8
RP52
2 7
RP52
3 6
RP52
4 5
53C6<
53C6<
1/16W
RP71
1/16W
RP71
1/16W
RP71
1/16W
22
5%
1/16W
SM1
22
5%
1/16W
SM1
22
5%
1/16W
SM1
22
5%
1/16W
SM1
22
5%
1/16W
SM1
22
5%
1/16W
SM1
22
5%
1/16W
SM1
5%
SM1
22
5%
SM1
22
5%
SM1
22
5%
SM1
R137
1/16W
NOSTUFF
R172
10K
1/16W
NOSTUFF
RAM_ADDR<12>
RAM_ADDR<8>
RAM_ADDR<6>
RAM_ADDR<5>
1
10K
1%
MF
402
2
1
1%
MF
402
2
RAM_CKE<2>
RAM_CS_L<0>
RAM_CKE<0>
1
R214
10K
1%
1/16W
MF
402
2
NOSTUFF
RAM_CS_L<3>
RAM_CKE<3>
RAM_CS_L<2>MEM_CS_L<2>
RAM_CKE<1>
1
R235
10K
1%
1/16W
MF
402
2
NOSTUFF
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
051-6497
NONE
SHT
12 69
SCALE
1
OF
15B1<
53C6<
14B6<>
53C6<
14B4<>
53C6<
53C6<
15B4>
15A1<
53C6<
15B4>
14B6<>
53C6<
REV.
53D6<
53D6<
53D6<
53D6<
15C6<
15C1<
53C6<
15C4>
53C6< 53C6<
15C1<
13
D
C
B
A
DRAWING
<XR_PAGE_TITLE>
+2_5V_MAIN
78
6
5
4
3
12
+2_5V_MAIN
NOSTUFF
1
C230
10UF
N20P80%
10V
2
Y5V
805
CBTV4020
F2
DH0
H2
DH1
J2
DH2
J3
DH3
J5
DH4
J6
DH5
J8
DH6
J9
DH7
H9
DH8
F9
DH9
E9
DH10
C9
DH11
B9
DH12
B8
DH13
B6
DH14
B5
DH15
B3
DH16
B2
DH17
C2
DH18
E2
E3
SEL
C5C6D2D9G2G9H5
E8F3F8
VDD
U18
BGA
SYM_VER-3
GND
DA10
DA11
DA12
DA13
DA14
DA15
DA16
DA17
DA18
DA19
DB0*
DB1*
DB2*
DB3*
DB4*
DB5*
DB6*
DB7*
DB8*
DB9*DH19
DB10*
DB11*
DB12*
DB13*
DB14*
DB15*
DB16*
DB17*
DB18*
DB19*
DA0
DA1
DA2
DA3
DA4
DA5
DA6
DA7
DA8
DA9
F1
H1
K1
K3
K4
K6
J7
K9
J10
G10
E10
C10
A10
A8
A7
A5
B4
A2
B1
D1
G1
J1
K2
J4
K5
K7
K8
K10
H10
F10
D10
B10
A9
B7
A6
A4
A3
A1
C1
E1
H6
D
12D8<>
12D8<>
12D8<>
12D8<>
12D8<>
12D8<>
12D8<>
12D8<>
12C6<>
12C6<>
12D8<>
12D8<>
12D8<>
12D8<>
12D8<>
12D8<>
12C8<>
12C8<>
12C6<>
12C6<>
MEM_DATA<0>
MEM_DATA<1>
MEM_DATA<2>
MEM_DATA<3>
MEM_DATA<4>
MEM_DATA<5>
MEM_DATA<6>
MEM_DATA<7>
MEM_DQS<0>
MEM_DQM<0>
MEM_DATA<8>
MEM_DATA<9>
MEM_DATA<10>
MEM_DATA<11>
MEM_DATA<12>
MEM_DATA<13>
MEM_DATA<14>
MEM_DATA<15>
MEM_DQS<1>
MEM_DQM<1>
MUX_SEL_L
12D4<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
C
53D6<
53D6<
53D6<
53D6<
53C6<
53D6<
53D6<
13A6<>
1
C611
0.1UF
20%
10V
2
CERM
402
RAM_DATA_A<0>
RAM_DATA_A<1>
RAM_DATA_A<2>
RAM_DATA_A<3>
RAM_DATA_A<4>
RAM_DATA_A<5>
RAM_DATA_A<6>
RAM_DATA_A<7>
RAM_DQS_A<0>
RAM_DQM_A<0>
RAM_DATA_A<8>
RAM_DATA_A<9>
RAM_DATA_A<10>
RAM_DATA_A<11>
RAM_DATA_A<12>
RAM_DATA_A<13>
RAM_DATA_A<14>
RAM_DATA_A<15>
RAM_DQS_A<1>
RAM_DQM_A<1>
RAM_DATA_B<0>
RAM_DATA_B<1>
RAM_DATA_B<2>
RAM_DATA_B<3>
RAM_DATA_B<4>
RAM_DATA_B<5>
RAM_DATA_B<6>
RAM_DATA_B<7>
RAM_DQS_B<0>
RAM_DQM_B<0>
RAM_DATA_B<8>
RAM_DATA_B<9>
RAM_DATA_B<10>
RAM_DATA_B<11>
RAM_DATA_B<12>
RAM_DATA_B<13>
RAM_DATA_B<14>
RAM_DATA_B<15>
RAM_DQS_B<1>
RAM_DQM_B<1>
B
53C6<
A
8
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
13C8<>
1
2
14D6<>
14D6<>
14D6<>
14D6<>
14D4<>
14D4<>
14D4<>
14D4<>
14C8<
14D4<>
14D6<>
14D6<>
14C8<
14D4<>
15D6<
15D6<
15D6<
15D6<
15D4>
15D4>
15D4>
15D4>
15C8<
15D4>
15D6<
15D6<
15C8<
15D4>
12C8<>
12C8<>
12C8<>
12C8<>
12C8<>
12C8<>
12C8<>
12C8<>
12C6<>
12C6<>
12C8<>
12C8<>
12C8<>
12C8<>
12C8<>
12C8<>
12C8<>
12C8<>
12C6<>
12C6<>
C612
0.1UF
20%
10V
CERM
402
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
14D6<>
53D6<
53D6<
53D6<
53D6<
14D6<>
53D6<
14D6<>
53D6<
14D4<>
53D6<
14D4<>
53D6<
14D4<>
53D6<
14D4<>
14D6<>
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
15D6<
53D6<
53D6<
53D6<
53D6<
53D6<
15C6<
53D6<
15C6<
53D6<
15D4>
53D6<
15D4>
53D6<
15C4>
53D6<
15C4>
15D6<
53D6<
53D6<
MEM_DATA<16>
MEM_DATA<17>
MEM_DATA<18>
MEM_DATA<19>
MEM_DATA<20>
MEM_DATA<21>
MEM_DATA<22>
MEM_DATA<23>
MEM_DQS<2>
MEM_DQM<2>
MEM_DATA<24>
MEM_DATA<25>
MEM_DATA<26>
MEM_DATA<27>
MEM_DATA<28>
MEM_DATA<29>
MEM_DATA<30>
MEM_DATA<31>
MEM_DQS<3>
MEM_DQM<3>
MUX_SEL_L
12D4<
1
2
53D6<
53D6<
C613
0.1UF
20%
10V
CERM
402
F2
H2
J2
J3
J5
J6
J8
J9
H9
F9
E9
C9
B9
B8
B6
B5
B3
B2
C2
E2
E3
67
+2_5V_MAIN
E8F3F8
VDD
DA0
DA1
DA2
U22
CBTV4020
DH0
DH1
DH2
DH3
DH4
DH5
DH6
DH7
DH8
DH9
DH10
DH11
DH12
DH13
DH14
DH15
DH16
DH17
DH18
SEL
C5C6D2D9G2G9H5
BGA
SYM_VER-3
GND
DA10
DA11
DA12
DA13
DA14
DA15
DA16
DA17
DA18
DA19
DB0*
DB1*
DB2*
DB3*
DB4*
DB5*
DB6*
DB7*
DB8*
DB9*DH19
DB10*
DB11*
DB12*
DB13*
DB14*
DB15*
DB16*
DB17*
DB18*
DB19*
DA3
DA4
DA5
DA6
DA7
DA8
DA9
1
C858
0.1UF
20%
10V
2
CERM
402
E8F3F8
VDD
U27
CBTV4020
BGA
SYM_VER-3
12C8<>
12C8<>
12C8<>
12C8<>
12C8<>
12C8<>
12C8<>
12C8<>
12B8<>
12B8<>
12B8<>
12B8<>
12B8<>
12B8<>
12B8<>
12B8<>
13A3<>
1
C669
0.1UF
20%
10V
2
CERM
402
MEM_DATA<32>
MEM_DATA<33>
MEM_DATA<34>
MEM_DATA<35>
MEM_DATA<36>
MEM_DATA<37>
MEM_DATA<38>
MEM_DATA<39>
MEM_DQS<4>
12C6<>
MEM_DQM<4>
12C6<>
MEM_DATA<40>
MEM_DATA<41>
MEM_DATA<42>
MEM_DATA<43>
MEM_DATA<44>
MEM_DATA<45>
MEM_DATA<46>
MEM_DATA<47>
MEM_DQS<5>
12C6<>
MEM_DQM<5>
12C6<>
MUX_SEL_H
12D4<
14D6<>
14C6<>
14C6<>
14C6<>
14D4<>
14C4<>
14C4<>
14C4<>
14C6<>
14C4<>
14C6<>
14C6<>
14C6<>
14C6<>
14C4<>
14C4<>
14C4<>
14C4<>
14C6<>
14C4<>
15C6<
15C6<
15C6<
15C6<
15C4>
15C4>
15C4>
15C4>
15C6<
15C4>
15C6<
15C6<
15C6<
15C6<
15C4>
15C4>
15C4>
15C4>
15B8<
15C4>
NOSTUFF
1
C671
0.1UF
20%
10V
2
CERM
402
14C8<
53D6<
14C8<
53D6<
15C8<
53D6<
15C6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53C6<
1
C670
0.1UF
20%
10V
2
CERM
402
F1
RAM_DATA_A<16>
H1
RAM_DATA_A<17>
K1
RAM_DATA_A<18>
K3
RAM_DATA_A<19>
K4
RAM_DATA_A<20>
K6
RAM_DATA_A<21>
J7
RAM_DATA_A<22>
K9
RAM_DATA_A<23>
J10
RAM_DQS_A<2>
G10
RAM_DQM_A<2>
E10
RAM_DATA_A<24>
C10
RAM_DATA_A<25>
A10
RAM_DATA_A<26>
A8
RAM_DATA_A<27>
A7
RAM_DATA_A<28>
A5
RAM_DATA_A<29>
B4
RAM_DATA_A<30>
A2
RAM_DATA_A<31>
B1
RAM_DQS_A<3>
D1
RAM_DQM_A<3>
G1
RAM_DATA_B<16>
J1
RAM_DATA_B<17>
K2
RAM_DATA_B<18>
J4
RAM_DATA_B<19>
K5
RAM_DATA_B<20>
K7
RAM_DATA_B<21>
K8
RAM_DATA_B<22>
K10
RAM_DATA_B<23>
H10
RAM_DQS_B<2>
F10
RAM_DQM_B<2>
D10
RAM_DATA_B<24>
B10
RAM_DATA_B<25>
A9
RAM_DATA_B<26>
B7
RAM_DATA_B<27>
A6
RAM_DATA_B<28>
A4
RAM_DATA_B<29>
A3
RAM_DATA_B<30>
A1
RAM_DATA_B<31>
C1
RAM_DQS_B<3>
E1
RAM_DQM_B<3>
H6
F2
DH0
H2
DH1
J2
DH2
J3
DH3
J5
DH4
J6
DH5
J8
DH6
J9
DH7
H9
DH8
F9
DH9
E9
DH10
C9
DH11
B9
DH12
B8
DH13
B6
DH14
B5
DH15
B3
DH16
B2
DH17
C2
DH18
E2
E3
SEL
C5C6D2D9G2G9H5
GND
5
DA10
DA11
DA12
DA13
DA14
DA15
DA16
DA17
DA18
DA19
DB0*
DB1*
DB2*
DB3*
DB4*
DB5*
DB6*
DB7*
DB8*
DB9*DH19
DB10*
DB11*
DB12*
DB13*
DB14*
DB15*
DB16*
DB17*
DB18*
DB19*
4
DA0
DA1
DA2
DA3
DA4
DA5
DA6
DA7
DA8
DA9
F1
H1
K1
K3
K4
K6
J7
K9
J10
G10
E10
C10
A10
A8
A7
A5
B4
A2
B1
D1
G1
J1
K2
J4
K5
K7
K8
K10
H10
F10
D10
B10
A9
B7
A6
A4
A3
A1
C1
E1
H6
NOSTUFF
1
C860
0.1UF
20%
10V
2
CERM
402
RAM_DATA_A<32>
RAM_DATA_A<33>
RAM_DATA_A<34>
RAM_DATA_A<35>
RAM_DATA_A<36>
RAM_DATA_A<37>
RAM_DATA_A<38>
RAM_DATA_A<39>
RAM_DQS_A<4>
RAM_DQM_A<4>
RAM_DATA_A<40>
RAM_DATA_A<41>
RAM_DATA_A<42>
RAM_DATA_A<43>
RAM_DATA_A<44>
RAM_DATA_A<45>
RAM_DATA_A<46>
RAM_DATA_A<47>
RAM_DQS_A<5>
RAM_DQM_A<5>
RAM_DATA_B<32>
RAM_DATA_B<33>
RAM_DATA_B<34>
RAM_DATA_B<35>
RAM_DATA_B<36>
RAM_DATA_B<37>
RAM_DATA_B<38>
RAM_DATA_B<39>
RAM_DQS_B<4>
RAM_DQM_B<4>
RAM_DATA_B<40>
RAM_DATA_B<41>
RAM_DATA_B<42>
RAM_DATA_B<43>
RAM_DATA_B<44>
RAM_DATA_B<45>
RAM_DATA_B<46>
RAM_DATA_B<47>
RAM_DQS_B<5>
RAM_DQM_B<5>
1
2
C859
0.1UF
20%
10V
CERM
402
14B6<>
14B6<>
14B6<>
14B6<>
14B4<>
14B4<>
14B4<>
14B4<>
14B6<>
14B4<>
14B6<>
14B6<>
14A6<>
14A6<>
14B4<>
14B4<>
14A4<>
14A4<>
14A6<>
14A4<>
15B6<
15B6<
15B6<
15B6<
15B4>
15B4>
15B4>
15B4>
15B6<
15B4>
15B6<
15B6<
15A6<
15A6<
15B4>
15B4>
15A4>
15A4>
15B6<
15B4>
14B8<
53D6<
14B8<
53D6<
15B8<
53D6<
15B8<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53C6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
12B8<>
12B8<>
12B8<>
12B8<>
12B8<>
12B8<>
12B8<>
12B8<>
12B8<>
12B8<>
12B8<>
12B8<>
12B8<>
12B8<>
12B8<>
12B8<>
13C4<>
MEM_DATA<48>
MEM_DATA<49>
MEM_DATA<50>
MEM_DATA<51>
MEM_DATA<52>
MEM_DATA<53>
MEM_DATA<54>
MEM_DATA<55>
12C6<>
12C6<>
MEM_DATA<56>
MEM_DATA<57>
MEM_DATA<58>
MEM_DATA<59>
MEM_DATA<60>
MEM_DATA<61>
MEM_DATA<62>
MEM_DATA<63>
12C6<>
12C6<>
12D4<
3
MEM_DQS<6>
MEM_DQM<6>
MEM_DQS<7>
MEM_DQM<7>
MUX_SEL_H
+2_5V_MAIN
E8F3F8
VDD
U29
CBTV4020
BGA
SYM_VER-3
F2
DH0
H2
DH1
J2
DH2
J3
DH3
J5
DH4
J6
DH5
J8
DH6
J9
DH7
H9
DH8
F9
DH9
E9
DH10
C9
DH11
B9
DH12
B8
DH13
B6
DH14
B5
DH15
B3
DH16
B2
DH17
C2
DH18
E2
E3
SEL
GND
C5C6D2D9G2G9H5
APPLE COMPUTER INC.
DA10
DA11
DA12
DA13
DA14
DA15
DA16
DA17
DA18
DA19
DB0*
DB1*
DB2*
DB3*
DB4*
DB5*
DB6*
DB7*
DB8*
DB9*DH19
DB10*
DB11*
DB12*
DB13*
DB14*
DB15*
DB16*
DB17*
DB18*
DB19*
NOSTUFF
1
C910
0.1UF
20%
10V
2
CERM
402
14A6<>
14A6<>
14A6<>
14A6<>
14A4<>
14A4<>
14A4<>
14A4<>
14A6<>
14A4<>
14A6<>
14A6<>
14A6<>
14A6<>
14A4<>
14A4<>
14A4<>
14A4<>
14A6<>
14A4<>
15A6<
15A6<
15A6<
15A6<
15A4>
15A4>
15A4>
15A4>
15A6<
15A4>
15A6<
15A6<
15A6<
15A6<
15A4>
15A4>
15A4>
15A4>
15A6<
15A4>
14B8<
53D6<
14A8<
53D6<
15B8<
53D6<
15A8<
53D6<
DA0
DA1
DA2
DA3
DA4
DA5
DA6
DA7
DA8
DA9
1
C908
0.1UF
20%
10V
2
CERM
402
F1
H1
K1
K3
K4
K6
J7
K9
J10
G10
E10
C10
A10
A8
A7
A5
B4
A2
B1
D1
G1
J1
K2
J4
K5
K7
K8
K10
H10
F10
D10
B10
A9
B7
A6
A4
A3
A1
C1
E1
H6
1
C909
0.1UF
20%
10V
2
CERM
402
RAM_DATA_A<48>
RAM_DATA_A<49>
RAM_DATA_A<50>
RAM_DATA_A<51>
RAM_DATA_A<52>
RAM_DATA_A<53>
RAM_DATA_A<54>
RAM_DATA_A<55>
RAM_DQS_A<6>
RAM_DQM_A<6>
RAM_DATA_A<56>
RAM_DATA_A<57>
RAM_DATA_A<58>
RAM_DATA_A<59>
RAM_DATA_A<60>
RAM_DATA_A<61>
RAM_DATA_A<62>
RAM_DATA_A<63>
RAM_DQS_A<7>
RAM_DQM_A<7>
RAM_DATA_B<48>
RAM_DATA_B<49>
RAM_DATA_B<50>
RAM_DATA_B<51>
RAM_DATA_B<52>
RAM_DATA_B<53>
RAM_DATA_B<54>
RAM_DATA_B<55>
RAM_DQS_B<6>
RAM_DQM_B<6>
RAM_DATA_B<56>
RAM_DATA_B<57>
RAM_DATA_B<58>
RAM_DATA_B<59>
RAM_DATA_B<60>
RAM_DATA_B<61>
RAM_DATA_B<62>
RAM_DATA_B<63>
RAM_DQS_B<7>
RAM_DQM_B<7>
DDR MUXES
NOTICE OF PROPRIETARY PROPERTY
LAST_MODIFIED=Wed Sep 17 12:15:54 2003
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
051-6497
SCALE
NONE
2
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
SHT
13 69
1
D
C
B
A
REV.
13
OF
DRAWING
<XR_PAGE_TITLE>
D
C
B
A
78
+2_5V_MAIN
1
C1401
0.1UF
20%
10V
2
CERM
1
C1601
0.1UF
2
20%
10V
CERM
402
402
DISTRIBUTE THESE TWO CAPS
ALONG VREF TRACE
15D8<
DDR_VREF
12A7<
14D2<>
52A6>
1
C46
0.1UF
20%
10V
2
CERM
402
NOSTUFF
LOCATE C1601 AND C1401
DIRECTLY ON PIN AT J26-1
1
C47
0.1UF
20%
10V
2
CERM
402
NOSTUFF
+2_5V_MAIN
NOSTUFF
R1403
470
1 2
5%
1/16W
RAM_DQS_A<0>
13D7<>
14D6<>
53D6<
13C7<>
13B5<>
13B5<>
13D4<>
13C4<>
13B2<>
13B2<>
RAM_DQS_A<1>
RAM_DQS_A<2>
RAM_DQS_A<3>
RAM_DQS_A<4>
RAM_DQS_A<5>
RAM_DQS_A<6>
RAM_DQS_A<7>
14D6<>
53D6< 53D6<
14C6<>
53D6<
14C6<>
53D6<
14B6<>
53D6<
14A6<>
53D6<
14A6<>
53D6<
14A6<>
53D6<
MF
402
NOSTUFF
R1405
470
1 2
5%
1/16W
MF
402
NOSTUFF
R1407
470
1 2
5%
1/16W
MF
402
NOSTUFF
R1409
470
1 2
5%
1/16W
MF
402
NOSTUFF
R1411
470
1 2
5%
1/16W
MF
402
NOSTUFF
R1413
470
1 2
5%
1/16W
MF
402
NOSTUFF
R1415
470
1 2
5%
1/16W
MF
402
NOSTUFF
R1417
470
1 2
5%
1/16W
MF
402
NOSTUFF
R1404
470
1 2
5%
1/16W
MF
402
NOSTUFF
R1406
470
1 2
5%
1/16W
MF
402
NOSTUFF
R1408
470
1 2
5%
1/16W
MF
402
NOSTUFF
R1410
470
1 2
5%
1/16W
MF
402
NOSTUFF
R1412
470
1 2
5%
1/16W
MF
402
NOSTUFF
R1414
470
1 2
5%
1/16W
MF
402
NOSTUFF
R1416
470
1 2
5%
1/16W
MF
402
NOSTUFF
R1418
470
1 2
5%
1/16W
MF
402
+3V_MAIN
1
C319
10UF
N20P80%
10V
2
Y5V
805
1
C929
0.1UF
20%
10V
2
CERM
402
8
53D6<
53D6<
53C6<
53C6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
13D7<>
53D6<
13D7<>
14C8<
13D7<>
53D6<
13D7<>
53D6<
13D7<>
53D6<
13C7<>
53D6<
13C7<>
14C8<
13C7<>
53D6<
13C7<>
53D6<
13C7<>
12C4<
SYSCLK_DDRCLK_A0_L
53D6<
13B5<>
13B5<>
53D6<
13B5<>
14C8<
13B5<>
53D6<
53D6<
13B5<>
53D6<
13B5<>
53D6<
13B5<>
14C8<
13B5<>
13B5<>
53D6<
13B5<>
53D6<
53C6<
15C1<
15C4>
53D6<
15C6<
53D6<
15C6<
53D6<
15C6<
53D6<
15C4>
53D6<
15B6<
15B4>
53D6<
15B6<
53C6<
15B6<
53C6<
13D4<>
53D6<
13D4<>
53D6<
13D4<>
14B8<
13D4<>
53D6<
13D4<>
53D6<
13D4<>
53D6<
13C4<>
53D6<
13C4<>
14B8<
13C4<>
53D6<
13C4<>
53D6<
13C2<>
53D6<
13C2<>
53D6<
13B2<>
14B8<
13C2<>
53D6<
13C2<>
53D6<
13B2<>
53D6<
13B2<>
53D6<
13B2<>
14A8<
13B2<>
53D6<
13B2<>
53D6<
15A6<
34B3<
34B3<
6
MIN_LINE_WIDTH=20
RAM_DATA_A<0>
RAM_DATA_A<1>
RAM_DQS_A<0>
RAM_DATA_A<2>
RAM_DATA_A<3>
RAM_DATA_A<8>
RAM_DATA_A<9>
RAM_DQS_A<1>
RAM_DATA_A<10>
RAM_DATA_A<11>
SYSCLK_DDRCLK_A0
RAM_DATA_A<16>
RAM_DATA_A<17>
RAM_DQS_A<2>
RAM_DATA_A<18>
RAM_DATA_A<19>
RAM_DATA_A<24>
RAM_DATA_A<25>
RAM_DQS_A<3>
RAM_DATA_A<26>
RAM_DATA_A<27>
RAM_CKE<1>
12B1<
RAM_ADDR<12>
12D1<
RAM_ADDR<9>
12C3<
RAM_ADDR<7>
12D3<
RAM_ADDR<5>
12C1<
RAM_ADDR<3>
12D3<
RAM_ADDR<1>
12C3<
RAM_ADDR<10>
12C3<
RAM_BA<0>
12B3<
RAM_WE_L
12B3<
RAM_CS_L<0>
12C1<
RAM_DATA_A<32>
RAM_DATA_A<33>
RAM_DQS_A<4>
RAM_DATA_A<34>
RAM_DATA_A<35>
RAM_DATA_A<40>
RAM_DATA_A<41>
RAM_DQS_A<5>
RAM_DATA_A<42>
RAM_DATA_A<43>
RAM_DATA_A<48>
RAM_DATA_A<49>
RAM_DQS_A<6>
RAM_DATA_A<50>
RAM_DATA_A<51>
RAM_DATA_A<56>
RAM_DATA_A<57>
RAM_DQS_A<7>
RAM_DATA_A<58>
RAM_DATA_A<59>
INT_I2C_DATA0
INT_I2C_CLK0
15A6<
NC_SODIMM202
67
+2_5V_MAIN
NC_SODIMM71
NC_SODIMM73
NC_SODIMM77
NC_SODIMM79
NC_SODIMM83
NC_SODIMM85
NC_SODIMM89
NC_SODIMM91
NC_SODIMM97
NC_SODIMM123
NC_SODIMM199
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST
5
NC_SODIMM201
1 2
3 4
5
7
9
11
13
15
17
19
21
23
25
27 28
29
31
33 34
35
37
39 40
41
43
45 46
47
49
51
53
55
57
59
61
63 64
65
67
69 70
71 72
73 74
75 76
77 78
79 80
81 82
83 84
85 86
87 88
89
91
93 94
97 98
99
103 104
113 114
115
117
119
121 122
123 124
125 126
127
129
131 132
133
135
137 138
139
141
143 144
145
147
149 150
151
153
155 156
157
159
161 162
163
165
167 168
169
171
173
175
177
179
181
183
185 186
187
189
191 192
193
195
197
199 200
201
NO_TEST
VREF0
VSS0
DQ0
AS0A42-D2R
DQ1
F-RT-SM
VDD0
DQS0
DQ2
VSS2
DQ3
DQ8
VDD2
DQ9
DQS1
VSS4
DQ10
DQ11
VDD4
CK0
CK0*
VSS7
DQ16
DQ17
VDD7
DQS2
DQ18
VSS9
DQ19
DQ24
VDD9
DQ25
DQS3
VSS11
DQ26
DQ27
VDD11
RFU0
RFU2
VSS13
RFU4
RFU6
VDD13
RFU8
RFU10
VSS15
RFU12
RFU13
VDD16
CKE1
RFU14
A12
A9
VSS18
A7
A5
A3
A1
VDD18
A10_AP
BA0
WE*
S0*
RFU16
VSS20
DQ32
DQ33
VDD20
DQS4
DQ34
VSS22
DQ35
DQ40
VDD22
DQ41
DQS5
VSS24
DQ42
DQ43
VDD24
VDD26
VSS26
VSS27
DQ48
DQ49
VDD27
DQS6
DQ50
VSS29
DQ51
DQ56
VDD29
DQ57
DQS7
VSS31
DQ58
DQ59
VDD31
SDA
SCL
VDDSPD
RFU18
202
J26
KEY
5
+2_5V_MAIN
VREF1
VSS1
6
DQ4
8
DQ5
10
VDD1
12
DM0
14
DQ6
16
VSS3
18
DQ7
20
DQ12
22
VDD3
24
DQ13
26
DM1
VSS5
30
DQ14
32
DQ15
VDD5
36
VDD6
38
VSS6
VSS8
42
DQ20
44
DQ21
VDD8
48
DM2
50
DQ22
52
VSS10
54
DQ23
56
DQ28
58
VDD10
60
DQ29
62
DM3
VSS12
66
DQ30
68
DQ31
VDD12
RFU1
RFU3
VSS14
RFU5
RFU7
VDD14
RFU9
RFU11
VSS16
90
VSS17
92
VDD15
VDD17
9695
CKE0
RFU15
100
A11
102101
A8
VSS19
106105
A6
108107
A4
110109
A2
112111
A0
VDD19
116
BA1
118
RAS*
120
CAS*
S1*
RFU17
VSS21
128
DQ36
130
DQ37
VDD21
134
DM4
136
DQ38
VSS23
140
DQ39
142
DQ44
VDD23
146
DQ45
148
DM5
VSS25
152
DQ46
154
DQ47
VDD25
158
CK1*
160
CK1
VSS28
164
DQ52
166
DQ53
VDD28
170
DM6
172
DQ54
174
VSS30
176
DQ55
178
DQ60
180
VDD30
182
DQ61
184
DM7
VSS32
188
DQ62
190
DQ63
VDD32
194
SA0
196
SA1
198
SA2
RFU19
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST
4
4
NC_SODIMM72
NC_SODIMM74
NC_SODIMM78
NC_SODIMM80
NC_SODIMM84
NC_SODIMM86
NC_SODIMM98
NC_SODIMM124
ADDR=0 (0xA0)
NC_SODIMM200
MIN_LINE_WIDTH=20
RAM_DATA_A<4>
RAM_DATA_A<5>
RAM_DQM_A<0>
RAM_DATA_A<6>
RAM_DATA_A<7>
RAM_DATA_A<12>
RAM_DATA_A<13>
RAM_DQM_A<1>
RAM_DATA_A<14>
RAM_DATA_A<15>
RAM_DATA_A<20>
RAM_DATA_A<21>
RAM_DQM_A<2>
RAM_DATA_A<22>
RAM_DATA_A<23>
RAM_DATA_A<28>
RAM_DATA_A<29>
RAM_DQM_A<3>
RAM_DATA_A<30>
RAM_DATA_A<31>
RAM_CKE<0>
RAM_ADDR<11>
RAM_ADDR<8>
RAM_ADDR<6>
RAM_ADDR<4>
RAM_ADDR<2>
RAM_ADDR<0>
RAM_BA<1>
RAM_RAS_L
RAM_CAS_L
RAM_CS_L<1>
RAM_DATA_A<36>
RAM_DATA_A<37>
RAM_DQM_A<4>
RAM_DATA_A<38>
RAM_DATA_A<39>
RAM_DATA_A<44>
RAM_DATA_A<45>
RAM_DQM_A<5>
RAM_DATA_A<46>
RAM_DATA_A<47>
SYSCLK_DDRCLK_A1_L
SYSCLK_DDRCLK_A1
RAM_DATA_A<52>
RAM_DATA_A<53>
RAM_DQM_A<6>
RAM_DATA_A<54>
RAM_DATA_A<55>
RAM_DATA_A<60>
RAM_DATA_A<61>
RAM_DQM_A<7>
RAM_DATA_A<62>
RAM_DATA_A<63>
12C1<
12B3<
12A2<
12A2<
13D7<>
13C7<>
13B5<>
13A5<>
12B3<
12D1<
12D1<
12D3<
12C3<
12C3<
12C1<
13D4<>
13C4<>
13B2<>
13B2<>
13D7<>
13D7<>
13D7<>
13D7<>
15B6<
15B4>
15B6<
(516S0029)
13C7<>
13C7<>
13C7<>
13C7<>
13B5<>
13B5<>
13B5<>
13B5<>
13B5<>
13B5<>
13B5<>
13B5<>
15C1<
15C4>
15C4>
15C6<
15C6<
15B6<
53C6<
13D4<>
13D4<>
13D4<>
13D4<>
13C4<>
13C4<>
13C4<>
13C4<>
12C4<
13C2<>
13C2<>
13B2<>
13B2<>
13B2<>
13B2<>
13B2<>
13B2<>
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
15C4>
53D6<
53C6<
53C6<
53D6<
53D6<
12B4<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53C6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53C6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
3
C1602
0.1UF
20%
10V
CERM
402
+2_5V_MAIN
53D6<
53C6<
3
+2_5V_MAIN
1
1
2
LOCATE C1602 AND C1402
DIRECTLY ON PIN AT J26-2
1
C244
0.1UF
20%
10V
2
CERM
402
1
C313
0.1UF
20%
10V
2
CERM
402
1
C1406
0.1UF
20%
10V
2
CERM
402
1
C1415
0.1UF
20%
10V
2
CERM
402
C1402
0.1UF
20%
10V
2
CERM
402
DDR DECOUPLING
SLOT "A"
1
C263
0.1UF
20%
10V
2
CERM
402
1
C242
0.1UF
20%
10V
2
CERM
402
1
C1407
0.1UF
20%
10V
2
CERM
402
1
C1416
0.1UF
20%
10V
2
CERM
402
1
C320
0.1UF
2
1
C275
0.1UF
2
1
C1408
0.1UF
2
1
C1417
0.1UF
2
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
1
C243
2
1
C276
2
1
C1409
2
1
C1418
2
0.1UF
20%
10V
CERM
402
0.1UF
20%
10V
CERM
402
0.1UF
20%
10V
CERM
402
0.1UF
20%
10V
CERM
402
+2_5V_MAIN
1
R1401
100
1%
1/16W
MF
402
2
1
R1402
100
1%
1/16W
MF
402
2
LAST_MODIFIED=Wed Sep 17 12:15:56 2003
APPLE COMPUTER INC.
2
12
DDR_VREF
1 - 10UF
24 - 0.1UF
1
C255
0.1UF
2
1
C304
0.1UF
2
1
C1410
0.1UF
2
1
C1419
0.1UF
2
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
1
2
1
C261
2
1
C1411
2
1
C1420
2
C256
0.1UF
20%20%
10V
CERM
0.1UF
20%
10V
CERM
402
0.1UF
20%
10V
CERM
402
0.1UF
20%
10V
CERM
402402
MIN_LINE_WIDTH=25
LOCATE THESE RESISTORS BETWEEN DIMMS
14D8<>
12A7<
402
1
2
1
C311
0.1UF
2
1
C1412
0.1UF
2
1
2
C1403
0.1UF
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
C1421
0.1UF
20%
10V
CERM
402
15D8<
+2_5V_MAIN
INT_MEM_VREF
SO-DIMM SLOT A
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
051-6497
SCALE
NONE
SHT
OF
1
52A6>
1
2
1
2
1
2
1
2
6914
C1404
0.1UF
20%
10V
CERM
402
C1405
0.1UF
20%
10V
CERM
402
C1413
0.1UF
20%
10V
CERM
402
C1414
10UF
N20P80%
10V
Y5V
805
REV.
D
C
B
12A8<>
A
13
DRAWING
<XR_PAGE_TITLE>
D
53D6<
53D6<
C
53D6<
53D6<
53D6<
53D6<
B
53D6<
53D6<
A
DISTRIBUTE THESE THREE CAPS
ALONG VREF TRACE
DDR_VREF
52A6>
1
C48
0.1UF
20%
10V
2
CERM
402
NOSTUFF
13C7<>
13B7<>
13A5<>
13A5<>
13C4<>
13B4<>
13B2<>
13A2<>
RAM_DQS_B<0>
RAM_DQS_B<1>
RAM_DQS_B<2>
RAM_DQS_B<3>
RAM_DQS_B<4>
RAM_DQS_B<5>
RAM_DQS_B<6>
RAM_DQS_B<7>
15D6<
15D6<
15C6<
15C6<
15B6<
15B6<
15A6<
15A6<
8
LOCATE C1702 AND C1501
DIRECTLY ON PIN J11-1
1
C49
0.1UF
20%
10V
2
CERM
402
NOSTUFF
+2_5V_MAIN
+2_5V_MAIN
1
R809
1K
1%
1/16W
MF
402
2
1
R796
1K
1%
1/16W
MF
402
2
1
C50
0.1UF
20%
10V
2
CERM
402
NOSTUFF
NOSTUFF
R1503
470
1 2
5%
1/16W
MF
402
NOSTUFF
R1505
470
1 2
5%
1/16W
MF
402
NOSTUFF
R1507
470
1 2
5%
1/16W
MF
402
NOSTUFF
R1509
470
1 2
5%
1/16W
MF
402
NOSTUFF
R1511
470
1 2
5%
1/16W
MF
402
NOSTUFF
R1513
470
1 2
5%
1/16W
MF
402
NOSTUFF
R1515
470
1 2
5%
1/16W
MF
402
NOSTUFF
R1517
470
1 2
5%
1/16W
MF
402
M_VDDID
M_SPD_WP
78
+2_5V_MAIN
NOSTUFF
R1504
470
1 2
5%
1/16W
MF
402
NOSTUFF
R1506
470
1 2
5%
1/16W
MF
402
NOSTUFF
R1508
470
1 2
5%
1/16W
MF
402
NOSTUFF
R1510
470
1 2
5%
1/16W
MF
402
NOSTUFF
R1512
470
1 2
5%
1/16W
MF
402
NOSTUFF
R1514
470
1 2
5%
1/16W
MF
402
NOSTUFF
R1516
470
1 2
5%
1/16W
MF
402
NOSTUFF
R1518
470
1 2
5%
1/16W
MF
402
1
2
1
C1702
0.1UF
20%
10V
2
CERM
402
C1501
0.1UF
20%
10V
CERM
402
MIN_LINE_WIDTH=20
13C7<>
53D6<
53D6<
13C7<>
15C8<
53D6<
53D6<
13C7<>
53D6<
13C7<>
53D6<
13C7<>
53D6<
13C7<>
15C8<
53D6<
53B6<
12A4<
53B6<
53D6<
53D6<
53D6<
53D6<
53B6<
53D6<
53D6<
SYSCLK_DDRCLK_B1_L
53D6<
13C7<>
53D6<
13C7<>
15B1<
53C6<
53D6<
13A5<>
53D6<
13A5<>
15C8<
14B6<>
53D6<
53D6<
13A5<>
14B6<>
53D6<
53D6<
13A5<>
14B6<>
53D6<
53D6<
13A5<>
53D6<
13A5<>
15B8<
14B4<>
53D6<
53D6<
13A5<>
53D6<
13A5<>
53D6<
14B4<>
53D6<
14B6<>
53D6<
14B4<>
53D6<
14B4<>
53D6<
13C4<>
53D6<
13C4<>
15B8<
53D6<
13C4<>
53D6<
14B6<>
53D6<
13C4<>
53D6<
13C4<>
53C6<
14B6<>
53D6<
13C4<>
53C6<
14B4<>
15B8<
53D6<
13C4<>
53D6<
13C4<>
53D6<
13B2<>
53D6<
13B2<>
SYSCLK_DDRCLK_B2_L
53B6<
12A4<
15B8<
53D6<
13B2<>
53D6<
13B2<>
53D6<
13B2<>
53D6<
13A2<>
15A8<
53D6<
13A2<>
53D6<
13A2<>
34B3<
14A6<>
34B3<
6
RAM_DATA_B<0>
RAM_DATA_B<1>
RAM_DQS_B<0>
13C7<>
RAM_DATA_B<2>
RAM_DATA_B<3>
RAM_DATA_B<8>
RAM_DATA_B<9>
RAM_DQS_B<1>
13B7<>
SYSCLK_DDRCLK_B1
RAM_DATA_B<10>
RAM_DATA_B<11>
RAM_CKE<2>
12C1<
RAM_DATA_B<16>
RAM_DATA_B<17>
RAM_DQS_B<2>
13A5<>
RAM_ADDR<9>
12C3<
RAM_DATA_B<18>
RAM_ADDR<7>
12D3<
RAM_DATA_B<19>
RAM_ADDR<5>
12C1<
RAM_DATA_B<24>
RAM_DATA_B<25>
RAM_DQS_B<3>
13A5<>
RAM_ADDR<4>
12D3<
RAM_DATA_B<26>
RAM_DATA_B<27>
RAM_ADDR<2>
12C3<
RAM_ADDR<1>
12C3<
RAM_ADDR<0>
12C3<
RAM_BA<1>
12B3<
RAM_DATA_B<32>
RAM_DATA_B<33>
RAM_DQS_B<4>
13C4<>
RAM_DATA_B<34>
RAM_BA<0>
12B3<
RAM_DATA_B<35>
RAM_DATA_B<40>
RAM_WE_L
12B3<
RAM_DATA_B<41>
RAM_CAS_L
12A2<
RAM_DQS_B<5>
13B4<>
RAM_DATA_B<42>
RAM_DATA_B<43>
RAM_DATA_B<48>
RAM_DATA_B<49>
SYSCLK_DDRCLK_B2
RAM_DQS_B<6>
13B2<>
RAM_DATA_B<50>
RAM_DATA_B<51>
RAM_DATA_B<56>
RAM_DATA_B<57>
RAM_DQS_B<7>
13A2<>
RAM_DATA_B<58>
RAM_DATA_B<59>
INT_I2C_DATA0
INT_I2C_CLK0
14A6<>
67
NC_BIGDIMM9
NC_BIGDIMM10
NC_BIGDIMM44
NC_BIGDIMM45
NC_BIGDIMM47
NC_BIGDIMM49
NC_BIGDIMM51
NC_BIGDIMM71
+2_5V_MAIN
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST
5
J11
TH-DDR-DIMM-71243
FRONT SIDE
SYM_VER3
SX64 DIMM
DM1/DQS10
DM2/DQS11
DM3/DQS12
DM4/DQS13
DM5/DQS14
DM6/DQS15
DM7/DQS16
REAR SIDE
VDDQ
DM0/DQS9
VDDQ
DQ12
DQ13
DQ14
DQ15
CKE1
VDDQ
DQ20
DQ21
DQ22
DQ23
DQ28
DQ29
VDDQ
DQ30
DQ31
VDDQ
CKO*
VDDQ
DQ36
DQ37
DQ38
DQ39
DQ44
RAS*
DQ45
VDDQ
DQ46
DQ47
NC,S3*
VDDQ
DQ52
DQ53
NC,FETEN
DQ54
DQ55
VDDQ
DQ60
DQ61
DQ62
DQ63
VDDQ
VVDDSPD
VSS
DQ4
DQ5
DQ6
DQ7
VSS
A13
VDD
BA2
A12
VSS
A11
VDD
VSS
VSS
CK0
VSS
A10
VSS
VDD
VSS
S0*
S1*
VSS
VDD
VSS
SA0
SA1
SA2
NC
NC
A8
A6
A3
NC
NC
NC
NC
NC
NC
1
VREF
2
DQ0
3
VSS
4
DQ1
5
DQS0
6
DQ2
7
VDD
8
DQ3
9
NC
10
NC
11
VSS
12
DQ8
13
DQ9
14
DQS1
15
VDDQ
16
CK1
17
CK1*
18
VSS
19
DQ10
20
DQ11
21
CKE0
22
VDDQ
23
DQ16
24
DQ17
25
DQS2
26
VSS
27
A9
28
DQ18
29
A7
30
VDDQ
31
DQ19
32
A5
33
DQ24
34
VSS
35
DQ25
36
DQS3
37
A4
38
VDD
39
DQ26
40
DQ27
41
A2
42
VSS
43
A1
44
NC
45
NC
46
VDD
47
NC
48
A0
49
NC
50
VSS
51
NC
52
BA1
53
DQ32
54
VDDQ
55
DQ33
56
DQS4
57
DQ34
58
VSS
59
BA0
60
DQ35
61
DQ40
62
VDDQ
63
WE*
64
DQ41
65
CAS*
66
VSS
67
DQS5
68
DQ42
69
DQ43
70
VDD
71
NC,S2*
72
DQ48
73
DQ49
74
VSS
75
CK2*
76
CK2
77
VDDQ
78
DQS6
79
DQ50
80
DQ51
81
VSS
82
VDDID
83
DQ56
84
DQ57
85
VDD
86
DQS7
87
DQ58
88
DQ59
89
VSS
90
WP
91
SDA
92
SCL
(516-1001)
DDR SDRAM SLOT B
5
+2_5V_MAIN
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST
4
RAM_DATA_B<4>
RAM_DATA_B<5>
RAM_DQM_B<0>
RAM_DATA_B<6>
RAM_DATA_B<7>
NC_BIGDIMM101
NC_BIGDIMM102
NC_BIGDIMM103
RAM_DATA_B<12>
RAM_DATA_B<13>
RAM_DQM_B<1>
RAM_DATA_B<14>
RAM_DATA_B<15>
NC_BIGDIMM113
NC_BIGDIMM134
NC_BIGDIMM135
NC_BIGDIMM140
RAM_ADDR<10>
NC_BIGDIMM142
RAM_DATA_B<20>
RAM_ADDR<12>
RAM_DATA_B<21>
RAM_ADDR<11>
RAM_DQM_B<2>
RAM_DATA_B<22>
RAM_ADDR<8>
RAM_DATA_B<23>
RAM_ADDR<6>
RAM_DATA_B<28>
RAM_DATA_B<29>
RAM_DQM_B<3>
RAM_ADDR<3>
RAM_DATA_B<30>
RAM_DATA_B<31>
SYSCLK_DDRCLK_B0
SYSCLK_DDRCLK_B0_L
NC_BIGDIMM144
RAM_DATA_B<36>
RAM_DATA_B<37>
RAM_DQM_B<4>
RAM_DATA_B<38>
RAM_DATA_B<39>
RAM_DATA_B<44>
RAM_RAS_L
RAM_DATA_B<45>
RAM_CS_L<2>
RAM_CS_L<3>
RAM_DQM_B<5>
RAM_DATA_B<46>
RAM_DATA_B<47>
NC_BIGDIMM163
RAM_DATA_B<52>
RAM_DATA_B<53>
NC_BIGDIMM167
RAM_DQM_B<6>
RAM_DATA_B<54>
RAM_DATA_B<55>
NC_BIGDIMM173
RAM_DATA_B<60>
RAM_DATA_B<61>
RAM_DQM_B<7>
RAM_DATA_B<62>
RAM_DATA_B<63>
RAM_SA0
ADDR = 1 (0XA2)
4
RAM_CKE<3>
12C3<
14B6<>
12A2<
13C7<>
13B7<>
12B1<
12D1<
12B3<
13A5<>
12D1<
12D1<
13A5<>
12D3<
53D6<
44C2<>
13C4<>
12B1<
12B1<
13B4<>
13B2<>
13A2<>
13C7<>
13C7<>
13C7<>
13C7<>
13C7<>
13B7<>
13B7<>
13B7<>
15A1<
13A5<>
13A5<>
13A5<>
14B4<>
13A5<>
14B4<>
13A5<>
13A5<>
14B6<>
13A5<>
13A5<>
34C3<
13C4<>
13C4<>
13C4<>
13C4<>
13C4<>
14B4<>
13C4<>
53C6<
53C6<
13B4<>
13B4<>
13B2<>
13B2<>
13B2<>
13B2<>
53D6<
13A2<>
13A2<>
13A2<>
13A2<>
14B6<>
14B4<>
12B4<
+2_5V_MAIN
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53C6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53B6<
53B6<
12B4<
INT_PU_RESET_L
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53C6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
53D6<
1
53D6<
53D6<
R825
2
53D6<
+3V_MAIN
1K
1%
1/16W
MF
402
3
DDR DECOUPLING
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
1
C726
0.1UF
20%
10V
2
CERM
402
1
C925
0.1UF
20%
10V
2
CERM
402
1
C1505
20%
10V
2
CERM
402
1
C1515
0.1UF
20%
10V
2
CERM
402
1
2
1
2
1
2
1
2
C562
0.1UF
C819
0.1UF
C1504
0.1UF
C1514
0.1UF
+2_5V_MAIN
NOSTUFF
1
R512
1K
1%
1/16W
MF
402
2
R508
0
1 2
5%
1/16W
MF
402
CKE_HYNIX
1
C943
0.1UF
20%
10V
2
CERM
402
3
15_I286
SLOT "B"
1
C936
0.1UF
20%
10V
2
CERM
402
1
C741
0.1UF
20%
10V
2
CERM
402
1
C1506
0.1UF0.1UF
20%
10V
2
CERM
402
CKE_HYNIX
1
C51
0.1UF
20%
10V
2
CERM
402
1
1
C945
10UF
N20P80%
10V
2
Y5V
805
G
1
C864
0.1UF
20%
10V
2
CERM
402
1
C914
0.1UF
20%
10V
2
CERM
402
1
C1507
0.1UF
20%
10V
2
CERM
402
CKE_HYNIX
1
R405
4.7K
5%
1/16W
MF
402
2
3
CKE_HYNIX
D
Q41
2N7002
SM
S
2
APPLE COMPUTER INC.
1
2
1
2
1
2
1 - 10UF
24 - 0.1UF
C922
0.1UF
20%
10V
CERM
402
C593
0.1UF
20%
10V
CERM
402
C1508
0.1UF
20%
10V
CERM
402
1
2
1
2
1
2
C602
C1509
C624
0.1UF
20%
10V
CERM
402
0.1UF
20%
10V
CERM
402
20%
10V
CERM
402
1
2
1
2
1
2
C1502
0.1UF
20%
10V
CERM
402
C672
0.1UF
20%
10V
CERM
402
C1510
0.1UF0.1UF
10V
CERM
402
1
2
1
2
1
2
C1513
0.1UF
C1503
0.1UF
C1511
0.1UF
+2_5V_MAIN
NOSTUFF
1
R497
10K
1%
1/16W
MF
402
2
3
D
S
2
NOSTUFF
1
R471
10K
1%
1/16W
MF
402
2
CKE_HYNIX
Q54
2N7002
SM
3
CKE_HYNIX
D
Q42
2N7002
1
SM
G
S
2
1
G
+2_5V_MAIN
NOSTUFF
1
R507
10K
1%
1/16W
MF
15_I282
1
G
D
S
1
G
3
CKE_HYNIX
Q52
2N7002
SM
2
3
CKE_HYNIX
D
S
2
Q53
2N7002
SM
2
NOSTUFF
1
R495
10K
1%
1/16W
MF
402
2
402
BIG DIMM SLOT B
NOTICE OF PROPRIETARY PROPERTY
LAST_MODIFIED=Wed Sep 17 12:15:58 2003
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
051-6497
SCALE
NONE
2
12
+2_5V_MAIN
20%
10V
CERM
402
20%
10V
CERM
402
20%20%
10V
CERM
402
NOSTUFF
1
C55
0.1UF
20%
10V
2
CERM
402
RAM_CKE<0>
TO SO-DIMM
RAM_CKE<1>
NOSTUFF
1
C58
0.1UF
20%
10V
2
CERM
402
RAM_CKE<2>
TO BIG DIMM
RAM_CKE<3>
SHT
15
1
OF
1
C1512
10UF
N20P80%
10V
2
Y5V
805
12C1<
53C6<
12B1<
53C6<
12C1<
53C6<
12B1<
53C6<
69
D
C
14B4<>
14B6<>
B
15C6<
15C4>
A
REV.
13
DRAWING
<XR_PAGE_TITLE>
D
54A7<
C
B
59C8>
52C3>
16D7<
16C2<
17D5<
A
INTREPID AGP CLK IS 1.5V OUT
NEED 3.3V SWING FOR VIDEO CHIPS
VERSION 1 WORKAROUND IS LA CLOCK
VERSION 2 WORKAROUND IS UNUSED PIN
52C3>
46B4<>
17D5<
17A4<
54A7<
CLK66M_GPU_AGP
17C7<
SHARE THE SAME PAD
30C5<>
THESE RESISTORS
INT_ROM_OVERLAY_PU
30A7<
2" LONGER
(0.5NS SLOWER)
1 2
NOSTUFF
AGP_FB_PLUS2
54A7<
1 2
NOSTUFF
R203
5%
1/16W
MF
402
R204
5%
1/16W
MF
402
0
0
PLACE ALL SERPENTINES ON INTERNAL LAYER
GPU AGP I/O REFERENCE
46B4<>
11A6<
17A4<
10D6<
17A3<
(PLACE CLOSE TO GPU AGP BALLS)
1/16W
402
1/16W
C603
470PF
1 2
10%
1
50V
CERM
1%
402
MF
2
1
1%
C222
MF
2
470PF
402
1 2
10%
50V
CERM
402
+1_5V_AGP
4.99K
4.99K
R549
R205
8
17A3<
16C2<
INT_V2
R225
22
1 2
5%
1/16W
MF
402
R224
22
1 2
5%
1/16W
MF
402
NOSTUFF
(ZERO DELAY)
NOSTUFF
1
R211
0
5%
1/16W
MF
402
2
GPU_AGP_VREF_H
R545
1
82.5
1%
1/16W
MF
2
402
1
R197
82.5
1%
1/16W
MF
402
2
GPU_AGP_VREF_L
78
52D3>
30D5<
10D6<
11A6<
16A8<
INT_V1
R226
1 2
1/16W
AGP
AGP_FBI_EQUAL
AGP_FBO_EQUAL
59C8>
0
5%
MF
54B7<
402
NOSTUFF
R215
1 2
1/16W
NOSTUFF
R216
1 2
5%
1/16W
MF
402
28D6<>
9D4<
+1_5V_AGP
54B7<
17A8<
52C3>
INT_ANALYZER_CLK
17A8>
16D3<
54A7<
CLK66M_GPU_UF
54A7<
54A7<
2" SHORTER
(0.5NS FASTER)
54A7<
0
5%
MF
402
1
R220
0
5%
1/16W
MF
402
2
0
54A7<
54B7<
17B8<
INT_AGP_VREF
1
C1802
0.1UF
20%
10V
2
CERM
402
+1_5V_INTREPID_PLL
1
R619
60.4
1%
1/16W
MF
402
2
STOP_AGP_L
16D3<
INT_AGPPVT
INT_AGP_VREF
16A7<
9B4<
8A2<
59A8>
AGP_BUSY_L
16D1<
INT_AGP_FB_IN
INT_AGP_FB_OUT
NOSTUFF
1
R622
0
5%
1/16W
MF
402
2
AGP_WBF_L
16B1<
16C6<>
54A7<
52C3>
6
67
AN19
56B3>
AT19
AK30
1 2
1
C760
0.1UF
20%
10V
2
CERM
402
STP_AGP
AJ24
AGPPVT
AB20
AGPVREF0
AB21
AGPVREF1
AGP_BUSY
AK28
AGP_CLK
AK27
AGP_FB_IN
AK25
AGP_FB_OUT
VOUT = AGPIO (1.5V)
VIN = VCORE (1.5V)
AGP_WBF
R667
4.7
5%
1/16W
MF
402
V14
VDD15A_5
(PLL5)
U25
INTREPID
(3 OF 9)
SEE_TABLE
(ON PAGE 12)
INTERFACES
VSSA_5
(PLL5)
V13
BGA
AGP
OMIT
2
XW48
SM
1
C1801
0.1UF
20%
10V
CERM
402
AGPDEVSEL
AGP_SB_STB_P
AGP_SB_STB_N
AGP_AD_STB0_P
AGP_AD_STB0_N
AGP_AD_STB1_P
AGP_AD_STB1_N
NO_TEST
5
1
2
AGPREQ
AGPGNT
AGPAD0
AGPAD1
AGPAD2
AGPAD3
AGPAD4
AGPAD5
AGPAD6
AGPAD7
AGPAD8
AGPAD9
AGPAD10
AGPAD11
AGPAD12
AGPAD13
AGPAD14
AGPAD15
AGPAD16
AGPAD17
AGPAD18
AGPAD19
AGPAD20
AGPAD21
AGPAD22
AGPAD23
AGPAD24
AGPAD25
AGPAD26
AGPAD27
AGPAD28
AGPAD29
AGPAD30
AGPAD31
AGPCBE_0
AGPCBE_1
AGPCBE_2
AGPCBE_3
AGPPAR
AGPFRAME
AGPTRDY
AGPIRDY
AGPSTOP
AGP_SBA0
AGP_SBA1
AGP_SBA2
AGP_SBA3
AGP_SBA4
AGP_SBA5
AGP_SBA6
AGP_SBA7
AGP_ST0
AGP_ST1
AGP_ST2
AGPPIPE
AGPRBF
INT_PLL5_GND
5
+1_5V_INTREPID_PLL5
INT_PLL5_GND
AT33
AM29
AR19
AM19
AT20
AR20
AT21
AN20
AR21
AN21
AM21
AT22
AR22
AN22
AM22
AN23
AR23
AT24
AM23
AR24
AT25
AR25
AM24
AN25
AL24
AR26
AT26
AM25
AN26
AM26
AR27
AT27
AR28
AN27
AM20
AT23
AN24
AL25
AT29
AN28
AR29
AT28
AM28
AM27
AT32
AR32
AM31
AN31
AR31
AT31
AM30
AN30
AH25
AG25
AN29
AT30
AR30
AK20
AK19
AK21
AK22
AJ29
AK24
16D5<
52D3>
16A5<>
AGP_REQ_L
AGP_GNT_L
AGP_AD<0>
AGP_AD<1>
AGP_AD<2>
AGP_AD<3>
AGP_AD<4>
AGP_AD<5>
AGP_AD<6>
AGP_AD<7>
AGP_AD<8>
AGP_AD<9>
AGP_AD<10>
AGP_AD<11>
AGP_AD<12>
AGP_AD<13>
AGP_AD<14>
AGP_AD<15>
AGP_AD<16>
AGP_AD<17>
AGP_AD<18>
AGP_AD<19>
AGP_AD<20>
AGP_AD<21>
AGP_AD<22>
AGP_AD<23>
AGP_AD<24>
AGP_AD<25>
AGP_AD<26>
AGP_AD<27>
AGP_AD<28>
AGP_AD<29>
AGP_AD<30>
AGP_AD<31>
AGP_CBE<0>
AGP_CBE<1>
AGP_CBE<2>
AGP_CBE<3>
AGP_PAR
AGP_FRAME_L
AGP_TRDY_L
AGP_IRDY_L
AGP_STOP_L
AGP_DEVSEL_L
AGP_SBA<0>
AGP_SBA<1>
AGP_SBA<2>
AGP_SBA<3>
AGP_SBA<4>
AGP_SBA<5>
AGP_SBA<6>
AGP_SBA<7>
AGP_SB_STB
AGP_SB_STB_L
AGP_ST<0>
AGP_ST<1>
AGP_ST<2>
AGP_AD_STB<0>
AGP_AD_STB_L<0>
AGP_AD_STB<1>
AGP_AD_STB_L<1>
AGP_PIPE_L
AGP_RBF_L
17B8<
16C3<
16C3<
17D8<
17D8<
17D8<
17D8<
17D8<
17D8<
17D8<
17D8<
17D8<
17D8<
17D8<
17D8<
17D8<
17D8<
17D8<
17C8<
17C8<
17C8<
17C8<
17C8<
17C8<
17C8<
17C8<
17C8<
17C8<
17C8<
17C8<
17C8<
17C8<
17C8<
17C8<
17C8<
17C8<
17C8<
17C8<
17C8<
16C3<
16B3<
16C3<
16B3<
16C1<
16C1<
16B1<
16C1<
16C1<
16C1<
16B1<
16B1<
16B3<
16B1<
16B1<
16B1<
16B3<
16B3<
54B7<
16C3<
16D1<
16B3<
16B3<
4
17B7<>
17B7<
54C7<
54C7<
54C7<
54C7<
54C7<
54C7<
54C7<
54C7<
54C7<
54C7<
54C7<
54C7<
54C7<
54C7<
54C7<
54C7<
54C7<
54C7<
54C7<
54C7<
54C7<
54C7<
54C7<
54C7<
54C7<
54C7<
54C7<
54C7<
54C7<
54C7<
54C7<
54C7<
54C7<
54C7<
54C7<
54C7<
17B8<
17B8<
17B8<
17B8<
17A8<
17A8<
17A8<
17A8<
17A8<
17A8<
17A8<
17A8<
17B8<
17B6<
17B6<
17B6<
16D1<
16D1<
17B8<
17B8<
4
54B7<
17B8<
17A8<
54B7<
54B7<
54B7<
17B8<
17B8<
54B7<
54B7<
54C7<
54C7<
54C7<
54C7<
54B7<
54B7<
54B7<
54B7<
54B7<
54B7<
54B7<
54B7<
54B7<
17B8<
17B8<
54B7<
54B7<
52C3>
54C7<
54B7<
54C7<
54C7<
54C7<
54C7<
54C7<
54C7<
54C7<
17A8>
54B7<
46B4<>
54B7<
54B7<
54C7<
54C7<
54C7<
54C7<
54B7<
54B7<
17B8<
17B8<
54B7<
16D1<
17A8<
17D5<
17B8<
17B8<
17B8<
17B8<
17B8<
17B8<
17B8<
17B7<>
17B7<
16B4<>
16B4<>
17B8<
16A4<>
16A4<>
AGP_BUSY_L
16C6<>
STOP_AGP_L
16C6<>
17A4<
17A3<
AGP_REQ_L
16C4<>
AGP_GNT_L
16C4<>
AGP_FRAME_L
AGP_DEVSEL_L
AGP_IRDY_L
16B4<>
AGP_TRDY_L
16B4<>
AGP_STOP_L
16B4<>
AGP_RBF_L
16A4<>
NC_RP1PIN4
AGP_PIPE_L
16A4<>
AGP_AD_STB<0>
AGP_AD_STB<1>
AGP_SB_STB
16A4<>
3
AGP PULL-UPS/PULL DOWNS
R222
1 2
R217
10K
1 2
1%
1/16W
MF
402
16D7<
16A8<
11A6<
NO_TEST
10D6<
59C8>
RP37
10K
4 5
5%
1/16W
SM1
RP37
10K
3 6
1/16W
SM1
RP98
10K
3 6
5%
1/16W
SM1
RP98
10K
1 8
5%
1/16W
SM1
RP48
10K
1 8
5%
1/16W
SM1
R580
10K
1 2
1%
1/16W
MF
402
R233
10K
1 2
1%
1/16W
MF
402
+1_5V_AGP
RP37
10K
2 7
1/16W
5%
RP98
2 7
RP98
10K
4 5
1/16W
RP37
1 8
RP48
2 7
1 2
3
+3V_MAIN
10K
1%
1/16W
MF
402
5%
SM1
10K
5%
1/16W
SM1
5%
SM1
10K
5%
1/16W
SM1
10K
5%
1/16W
SM1
R587
10K
1%
1/16W
MF
402
17B8<
54B7<
54B7<
54B7<
54B7<
54B7<
54B7<
17B8<
17A8>
17A8<
17A8<
17A8<
17A8<
17A8<
17A8<
17A8<
17A8<
16A4<>
16A4<>
17A8<
16D3<
17B6<
17B6<
17B8<
17B6<
16B4<>
16B4<>
16B4<>
16B4<
16B4<>
16A4<>
16A4<>
16A4<>
16B4<>
16A4<>
16A6<>
16A4<>
54C7<
54C7<
54B7<
54B7<
54B7<
54B7<
54B7<
54B7<
54B7<
54B7<
APPLE COMPUTER INC.
2
12
R223
10K
AGP_AD_STB_L<0>
AGP_AD_STB_L<1>
AGP_SB_STB_L
16A4<>
AGP_BUSY_L
16C6<>
AGP_SBA<5>
AGP_SBA<1>
AGP_SBA<4>
AGP_SBA<0>
AGP_SBA<3>
AGP_SBA<7>
AGP_ST<1>
AGP_ST<2>
AGP_SBA<2>
AGP_SBA<6>
AGP_WBF_L
AGP_ST<0>
1 2
1/16W
R221
1 2
1/16W
RP99
10K
1 8
5%
1/16W
SM1
RP99
10K
3 6
5%
1/16W
SM1
RP49
10K
1 8
5%
1/16W
SM1
RP49
10K
3 6
5%
1/16W
SM1
RP50
10K
1 8
5%
1/16W
SM1
RP50
10K
3 6
5%
1/16W
SM1
402
10K
402
1%
MF
1%
MF
1 2
NOSTUFF
1 2
RP99
10K
2 7
1/16W
RP99
10K
4 5
1/16W
RP49
10K
2 7
5%
1/16W
SM1
RP49
10K
4 5
1/16W
RP50
10K
2 7
1/16W
RP50
10K
4 5
5%
1/16W
SM1
INTREPID AGP
NOTICE OF PROPRIETARY PROPERTY
LAST_MODIFIED=Wed Sep 17 12:16:00 2003
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
051-6497
NONE
SHT
16
1
SCALE
R234
10K
1%
1/16W
MF
402
R161
10K
1%
1/16W
MF
402
5%
SM1
5%
SM1
5%
SM1
5%
SM1
OF
D
C
B
A
REV.
13
69
DRAWING
TRST*
TDO
TDI
TMS
TCLK
AGPCALPU
AGP 2X,4X : AGP 8X
PCIC0/BE0* : C0*/BE0
PCIC1/BE1* : C1*/BE1
PCIC2/BE2* : C2*/BE2
PCIC3/BE3* : C3*/BE3
PCIRST* : RST*
PCICLK : CLK
AGPVDDQ
VD50CLAMP0
VD50CLAMP1
50 OHM
TO VDDQ
50 OHM
10K OHM
TO GND
TESTMODE
AGPVREF : AGPVREF
AGPSTOP* : STOP*
AGPBUSY* : BUSY*
AGPST2 : ST2
AGPST1 : ST1
AGPST0 : ST0
PCIINTA* : INTA
PCITRDY* : TRDY
PCIPAR : PAR
PCISTOP* : STOP
PCIDEVSEL* : DEVSEL
PCIIRDY* : IRDY
PCIFRAME* : FRAME
PCIGNT* : GNT
PCIREQ* : REQ
PCIAD1
PCIAD2
PCIAD3
PCIAD4
PCIAD5
PCIAD0
PCIAD6
PCIAD7
PCIAD8
PCIAD12
PCIAD11
PCIAD10
PCIAD9
PCIAD16
PCIAD17
PCIAD18
PCIAD13
PCIAD14
PCIAD15
PCIAD23
PCIAD22
PCIAD21
PCIAD20
PCIAD19
PCIAD28
PCIAD27
PCIAD24
PCIAD25
PCIAD26
PCIAD31
PCIAD30
PCIAD29
(1 OF 5)
AGPRBF* : RBF
AGPWBF* : WBF
<RESRVD> : DBI_LO
AGPSBA7 : SBA7*
AGPSBA6 : SBA6*
AGPSBA5 : SBA5*
AGPSBA0 : SBA0*
AGPSBA1 : SBA1*
AGPSBA2 : SBA2*
AGPSBA3 : SBA3*
AGPSBA4 : SBA4*
<RESRVD> : MBDET*
TO GND
AGPPIPE* : DBI_HI
NC_PCIINTB*: INTB
AGPADSTBF1 : ADSTBF1
AGPSBSTBF : SBSTBF
AGPSBSTBS* : SBSTBS
AGPADSTBF0 : ADSTBF0
AGPADSTBS0* : ADSTBS0
AGPADSTBS1* : ADSTBS1
NC
VDD
VDD33
AGPCALPD
AGP_PLLVDD
DRAWING
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
CORE BYPASS
(LOW = AGP V3.X)
AGP VERSION SELECT
ALL ARE NO_TEST
OUTPUT DRIVER BYPASS
NVIDIA AGP
I/O BYPASS
GPU AGP I/O REFERENCE
(PLACE CLOSE TO INTREPID AGP BALLS)
(HIGH = AGP V2.X)
MF
49.9
1%
402
1/16W
+3V_MAIN
+5V_MAIN
SM1
1/16W
5%
22
49.9
1/16W
402
MF
1%
22
5%
SM1
1/16W
22
5%
1/16W
SM1
22
SM1
1/16W
5%
22
5%
1/16W
SM1
22
SM1
1/16W
5%
22
SM1
1/16W
5%
22
SM1
1/16W
5%
22
1/16W
5%
SM1
22
SM1
1/16W
5%
22
SM1
1/16W
5%
22
SM1
1/16W
5%
22
SM1
1/16W
5%
22
SM1
1/16W
5%
22
5%
1/16W
SM1
22
GPU_AGP_SB_STB_L
22
10K
402
MF
1/16W
1%
10UF
Y5V
10V
N20P80%
805
10UF
Y5V
10V
N20P80%
805
10UF
Y5V
10V
N20P80%
805
10UF
Y5V
10V
N20P80%
805
0.1UF
402
CERM
10V
20%
0.1UF
402
CERM
10V
20%
CERM
0.1UF
402
10V
20%
0.1UF
402
CERM
10V
20%
0.1UF
402
CERM
10V
20%
0.1UF
402
CERM
10V
20%
0.1UF
402
CERM
10V
20%
0.01UF
10%
402
CERM
16V
0.01UF
10%
402
CERM
16V
0.1UF
402
CERM
10V
20%
16V
CERM
402
10%
0.01UF
16V
CERM
402
10%
0.01UF
20%
10V
CERM
402
0.1UF
20%
10V
CERM
402
0.1UF
20%
10V
CERM
402
0.1UF
20%
10V
CERM
402
0.1UF
20%
10V
CERM
402
0.1UF
20%
10V
CERM
402
0.1UF
20%
CERM
402
10V
0.1UF
20%
10V
CERM
402
0.1UF
20%
10V
CERM
402
0.1UF
0.01UF
10%
402
CERM
16V 16V
0.01UF
10%
402
CERM
0.1UF
402
CERM
10V
20%
0.1UF
402
CERM
10V
20%
0.1UF
402
CERM
10V
20%
0.1UF
402
CERM
10V
20%
0.1UF
402
CERM
10V
20%
0.1UF
402
CERM
10V
20%
0.1UF
402
CERM
10V
20%
0.1UF
402
CERM
10V
20%
0.1UF
402
CERM
10V
20%
16V
CERM
402
10%
0.01UF
20%
10V
CERM
402
0.1UF
20%
10V
CERM
402
0.1UF
20%
10V
CERM
402
0.1UF
20%
10V
CERM
402
0.1UF
20%
10V
CERM
402
0.1UF
16V
CERM
402
10%
0.01UF
Y5V
805
N20P80%
10V
10UF
16V
CERM
402
10%
0.01UF
16V
CERM
402
10%
0.01UF
20%
10V
CERM
402
0.1UF
20%
10V
CERM
402
0.1UF
20%
10V
CERM
402
0.1UF
20%
10V
CERM
402
0.1UF
20%
10V
CERM
402
0.1UF
20%
10V
CERM
402
0.1UF
20%
10V
CERM
402
0.1UF
0.1UF
402
20%
10V
CERM
0.1UF
402
10V
20%
CERM
1%
10
402
MF
1/16W
+3V_MAIN
CERM
50V
10%
402
0.001UF
20%
10V
CERM
402
0.1UF4.7UF
805
CERM
10V
N20P80%
10K
402
10K
402
NV18B
BGA
82.5
1%
1/16W
MF
402
10%
50V
CERM
402
470PF
4.99K
1%
1/16W
MF
402
82.5
402
MF
1/16W
1%
4.99K
MF
1/16W
1%
402
470PF
10%
50V
CERM
402
+3V_MAIN
402
0
5%
0
5%
402
TMDS_XMIT_SI_P
MF
1/16W
1%
10K
402
NV34
10K
1%
1/16W
MF
402
NV34
+3V_MAIN
1%
MF
1/16W
10K
402
17 69
051-6497
13
GRAPH_CORE
MIN_LINE_WIDTH=20
MIN_LINE_WIDTH=20
MIN_LINE_WIDTH=20
GPU_AGP_VREF
STOP_AGP_L
AGP_BUSY_L
AGP_SB_STB_L
AGP_AD_STB<0>
AGP_AD_STB_L<1>
AGP_AD_STB<1>
AGP_AD_STB_L<0>
AGP_RESET_L
MAIN_RESET_L
NV_PCI_RST_L
CLK66M_GPU_AGP
GPU_AGP_CBE<2>
NO_TEST
GPU_AGP_CBE<1>
GPU_AGP_CBE<0>
NO_TEST
GPU_AGP_AD<31>
AGP_REQ_L
AGP_GNT_L
AGP_AD<30>
NO_TEST
GPU_AGP_AD<25>
AGP_FRAME_L
NO_TEST
AGP_AD_STB_L_GPUUF<0>
NO_TEST
AGP_AD_STB_GPUUF<1>
GPU_AGP_SB_STB
GPU_AGP_DEVSEL_L
NO_TEST
GPU_AGP_TRDY_L
NC_GPU<2>
NC_GPU<0>
AGP_ST<2>
AGP_ST<1>
AGP_ST<0>
AGP_INT_L
GPU_AGP_STOP_L
NO_TEST
NO_TEST
GPU_AGP_IRDY_L
GPU_AGP_FRAME_L
NO_TEST
GPU_AGP_PAR
NO_TEST
GPU_AGP_AD<4>
AGP_AD<5>
AGP_AD<7>
GPU_AGP_AD<1>
NO_TEST
NO_TEST
GPU_AGP_AD<2>
NO_TEST
GPU_AGP_AD<3>
GPU_AGP_AD<8>
NO_TEST
GPU_AGP_AD<11>
NO_TEST
GPU_AGP_AD<9>
NO_TEST
GPU_AGP_AD<10>
GPU_AGP_AD<13>
NO_TEST
GPU_AGP_AD<7>
GPU_AGP_CBE<3>
NO_TEST
AGP_AD<2>
GPU_AGP_AD<5>
NO_TEST
AGP_SBA<5>
AGP_SBA<4>
AGP_SBA<6>
AGP_SBA<7>
AGP_SBA<0>
AGP_SBA<1>
AGP_SBA<2>
AGP_SBA<3>
AGP_SB_STB
AGP_AD_STB_GPUUF<0>
GPU_AGP_PIPE_L
NO_TEST
GPU_AGP_WBF_L
AGP_RBF_L
AGP_PIPE_L
AGP_WBF_L
AGP_DEVSEL_L
AGP_STOP_L
AGP_PAR
AGP_IRDY_L
AGP_TRDY_L
AGP_CBE<2>
AGP_AD<31>
AGP_AD<29>
AGP_AD<28>
AGP_AD<27>
AGP_AD<24>
AGP_AD<23>
AGP_AD<22>
AGP_AD<21>
AGP_AD<20>
AGP_AD<19>
AGP_AD<17>
AGP_AD<18>
NC_GPU_DBI_LO
NC_GPU<1>
NC_GPU<3>
NC_GPU<4>
NC_GPU_INTB_L
NVAGP_TCLK
NVAGP_TRST_L
GPU_50PULLDWN
AGP_AD<15>
AGP_AD<14>
AGP_AD<13>
AGP_AD<12>
AGP_AD<11>
AGP_AD<10>
AGP_AD<9>
AGP_AD<8>
AGP_AD<4>
AGP_AD<6>
AGP_AD<3>
AGP_AD<1>
AGP_AD<0>
NO_TEST
AGP_AD_STB_L_GPUUF<1>
GPU_AGP_RBF_L
NO_TEST
NC_NVAGP_TDO
GPU_50PULLUP
+1_5V_AGP
GPU_AGP_SBA<0>
NO_TEST
GPU_AGP_SBA<1>
NO_TEST
GPU_AGP_SBA<2>
NO_TEST
GPU_AGP_SBA<3>
GPU_AGP_SBA<4>
NO_TEST
GPU_AGP_SBA<5>
NO_TEST
GPU_AGP_SBA<6>
NO_TEST
GPU_AGP_SBA<7>
GPU_AGP_AD<6>
NO_TEST
GPU_AGP_AD<12>
GPU_AGP_AD<17>
NO_TEST
NO_TEST
GPU_AGP_AD<19>
GPU_AGP_AD<20>
GPU_AGP_AD<21>
GPU_AGP_AD<22>
NO_TEST
NO_TEST
GPU_AGP_AD<23>
GPU_AGP_AD<24>
GPU_AGP_AD<28>
NO_TEST
GPU_AGP_AD<29>
AGP_AD<26>
NO_TEST
GPU_AGP_AD<27>
GPU_AGP_AD<30>
NO_TEST
AGP_CBE<3>
NVAGP_TDI
NVAGP_TMS
NO_TEST
GPU_AGP_AD<26>
NO_TEST
GPU_AGP_AD<15>
NO_TEST
GPU_AGP_AD<14>
GPU_AGP_AD<18>
NO_TEST
GPU_AGP_AD<16>
AGP_PLLVDD
GPU_AGP_VREF_X
GPU_AGP_VREF_Y
+1_5V_AGP
GPU_AGP_VREF
GPU_AGP_AD<0>
AGP_CBE<1>
AGP_CBE<0>
+1_5V_AGP
MIN_LINE_WIDTH=20
AGP_AD<16>
AGP_AD<25>
GPU_MBDET_L
GPU_TMODE
<XR_PAGE_TITLE>
R160
1
2
RP33
1
2
3
4
8
7
6
5
R169
1
2
RP40
1
2
3
4
8
7
6
5
RP30
1
2
3
4
8
7
6
5
RP32
1
2
3
4
8
7
6
5
RP42
1
2
3
4
8
7
6
5
RP31
1
2
3
4
8
7
6
5
RP41
1
2
3
4
8
7
6
5
RP44
1
2
3
4
8
7
6
5
RP34
1
2
3
4
8
7
6
5
RP43
1
2
3
4
8
7
6
5
RP45
1
2
3
4
8
7
6
5
RP35
1
2
3
4
8
7
6
5
RP46
1
2
3
4
8
7
6
5
RP47
1
2
3
4
8
7
6
5
RP36
1
2
3
4
8
7
6
5
R558
1 2
R210
1 2
R168
1
2
C93
1
2
C94
1
2
C161
1
2
C168
1
2
C178
1
2
C201
1
2
C202
1
2
C185
1
2
C203
1
2
C183
1
2
C176
1
2
C200
1
2
C192
1
2
C180
1
2
C104
1
2
C134
1
2
C117
1
2
C109
1
2
C100
1
2
C101
1
2
C103
1
2
C110
1
2
C139
1
2
C99
1
2
C146
1
2
C148
1
2
C149
1
2
C150
1
2
C147
1
2
C118
1
2
C135
1
2
C169
1
2
C140
1
2
C120
1
2
C102
1
2
C151
1
2
C177
1
2
C184
1
2
C129
1
2
C136
1
2
C116
1
2
C87
1
2
C111
1
2
C137
1
2
C91
1
2
C97
1
2
C187
1
2
C179
1
2
C105
1
2
C112
1
2
C181
1
2
C182
1
2
C188
1
2
C193
1
2
C186
1
2
R198
1 2
C217
1
2
C219
1
2
C223
R80
1 2
R72
1 2
U39
AK24
AG21
AJ25
AF21
AF12
AA13
AA14
AJ19
AF16
AJ18
AG14
AJ11
AH11
AJ12
AH12
AJ14
AH14
AJ15
AH15
AK13
AJ13
AG13
AE16
AE13
AG11
AE14
AD17
AE11
AE17
AE20
AE23
AD11
AD14
AD23
AD20
AK29
AG17
AE12
A1
AK30
G6R7T7
AE10
AJ28
AK28
AH22
AJ22
AJ21
AK21
AH20
AJ20
AG26
AE24
AG25
AG24
AH27
AF24
AG23
AE22
AF22
AE21
AG20
AG19
AF19
AE19
AF18
AK27
AG18
AE18
AJ27
AH26
AJ26
AH25
AH23
AJ23
AJ24
AH19
AF25
AG22
AG12
AJ16
AK16
AE15
AG15
AG16
AK18
AF13
AF15
AH17
AJ17
C2D1E2
AE5
C1
D2
N4
AE9
AA17
AA18
L11
N11
P11
U11
V11
Y11
L14
Y14
L17
Y17
L20
L18
Y18
Y20
H6
AC6
AC7
AD12
P24
U7
G14
U6
AD15
H7
AD16
AD19
AD22
L13
Y13
N20
P20
U20
V20
R192
1
2
C214
1 2
R195
1
2
R193
1
2
R196
1
2
C215
1 2
R1026
1 2
R1027
1 2
R1024
1
2
R1025
1
2
R177
1
2
LAST_MODIFIED=Wed Sep 17 12:16:02 2003
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NC_FBADQS7*
NC_FBADQS6*
NC_FBADQS5*
NC_FBADQS0*
NC_FBADQS1*
NC_FBADQS2*
NC_FBADQS3*
NC_FBADQS4*
FBVDDQ
FBAA12
FBABA0
FBABA1
FBAA11
FBADQM7
FBADQM6
FBADQM5
FBADQM4
FBADQM3
FBADQM2
FBADQM1
FBADQM0
FBAD63
FBAD62
FBAD61
FBAD60
FBAD59
FBAD58
FBAD57
FBAD56
FBAD55
FBAD54
FBAD53
FBAD52
FBAD51
FBAD50
FBAD49
FBAD48
FBAD47
FBAD46
FBAD45
FBAD44
FBAD43
FBAD42
FBAD41
FBAD40
FBAD39
FBAD38
FBAD37
FBAD36
FBAD35
FBAD34
FBAD33
FBAD32
FBAD31
FBAD30
FBAD29
FBAD28
FBAD27
FBAD26
FBAD25
FBAD24
FBAD23
FBAD22
FBAD21
FBAD20
FBAD19
FBAD18
FBAD17
FBAD16
FBAD15
FBAD14
FBAD13
FBAD12
FBAD11
FBAD10
FBAD9
FBAD8
FBAD7
FBAD6
FBAD5
FBAD4
FBAD3
FBAD2
FBAD1
FBAD0
ROMCS*
ROMA15
(3 OF 5)
FBAA6
FBAA0
FBAA2
FBAA4
FBAA1
FBAA5
FBAA3
FBAA7
FBAA10
FBAA8
FBAA9
FBARAS*
FBVREF
FBACS1*
FBACS0*
FBAWE*
FBACAS*
ROMA14
NC_VTT
GND
FB_DLLVDD
FBCAL_CLK_GND
FBCAL_TERM_GND
FBCAL_PU_GND
FBCAL_PD_VDDQ
FBACKE
FBACLK1*
FBACLK0
FBACLK0*
FBACLK1
FBADQS4
FBADQS3
FBADQS2
FBADQS1
FBADQS0
FBADQS5
FBADQS6
FBADQS7
FBCDQM7
FBCDQM6
FBCDQM5
FBCDQM4
FBCDQM3
FBCDQM2
FBCDQM1
FBCDQM0
THERMAL GND
(4 OF 5)
FBCD0
FBCD1
FBCD2
FBCD3
FBCD4
FBCD5
FBCD6
FBCD7
FBCD8
FBCD9
FBCD10
FBCD11
FBCD12
FBCD13
FBCD14
FBCD15
FBCD16
FBCD17
FBCD18
FBCD19
FBCD20
FBCD21
FBCD22
FBCD23
FBCD25
FBCD26
FBCD27
FBCD28
FBCD29
FBCD30
FBCD31
FBCD32
FBCD33
FBCD34
FBCD35
FBCD36
FBCD37
FBCD38
FBCD39
FBCD40
FBCD41
FBCD42
FBCD43
FBCD44
FBCD45
FBCD46
FBCD47
FBCD48
FBCD49
FBCD50
FBCD51
FBCD52
FBCD53
FBCD54
FBCD55
FBCD56
FBCD57
FBCD58
FBCD59
FBCD60
FBCD63
FBCD61
FBCD24
FBCD62
FBCA0
FBCA1
FBCA2
FBCA3
FBCA4
FBCA5
FBCA6
FBCA7
FBCA8
FBCA9
FBCA10
FBCA11
FBBCLK1*
FBBCLK0*
FBBCLK0
FBBCLK1
FBCBA0
FBCBA1
FBCA12
FBCDQS0
FBCDQS1
FBCDQS2
FBCDQS3
FBCDQS4
FBCDQS5
FBCDQS6
FBCDQS7
NC_FBCDQS4*
NC_FBCDQS3*
NC_FBCDQS2*
NC_FBCDQS1*
NC_FBCDQS0*
NC_FBCDQS5*
NC_FBCDQS7*
NC_FBCDQS6*
FBCCKE
FBCRAS*
FBCCAS*
FBCWE*
FBCCS0*
FBCCS1*
DRAWING
REV.
DRAWING NUMBER
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
NOTICE OF PROPRIETARY PROPERTY
OFSHT
NONE
SCALE
E
SIZE
APPLE COMPUTER INC.
H
G
1
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E
234
D
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B
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14 3 2
567
H
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7 6 5
D
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8
RECOMMENDED BY NVIDIA
OTHER R’S BETWEEN GPU & MEMORY
DQM R’S CLOSE TO GPU
WEAK PULL-DOWN
WEAK PULL-DOWN
RECOMMENDED BY NVIDIA
EVENLY DISTRIBUTE 0.01UF & 0.1 UF CAPS
AMONGST FBVDDQ PINS ON NV ASIC
NVIDIA FRAME BUFFER
NVIDIA VREF
0.1UF
402
10V
CERM
20%
22
SM1
5%
1/16W
NV34
22
SM1
5%
1/16W
NV34
22
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1/16W
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22
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1/16W
NV34
22
1/16W
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22
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1/16W
NV34
10K
1/16W
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402
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NV34
22
1/16W
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0
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1/16W5%402
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6.3V
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22
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0
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1/16W
5%
0
402
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1/16W
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1/16W
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22
1/16W
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402
1/16W
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402
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20%
49.9
402
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49.9
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402
549
1%
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402
0
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1/16W
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402
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0
5%
1/16W
MF
402
+2_5V_MAIN
5%
1/16W
MF
402
0
0.1UF
20%
10V
CERM
402
0.1UF
20%
CERM
10V
402
402
MF
1/16W
1%
1K
1K
1%
1/16W
MF
402
100PF
5%
CERM
50V
402
NOSTUFF
TLV431A
SOT
NOSTUFF
+3V_MAIN
0.001UF
CERM
50V
10%
402
0.1UF
20%
10V
CERM
402
4.7UF
CERM
10V
N20P80%
805
0
402
5%
1/16W
MF
0
402
5%
1/16W
MF
0
402
5%
1/16W
MF
0
402
5%
1/16W
MF
0
402
5%
1/16W
MF
0
MF
1/16W5%402
NV34
0
MF5%
402
1/16W
NV34
0
MF5%
402
1/16W
NV34
0
402
5%
1/16W
MF
NV34
0
402
5%
1/16W
MF
NV34
0
5%
1/16W
MF
402
22
1/16W
5%
SM1
NV34
22
SM1
5%
1/16W
NV34
22
1/16W
5%
SM1
NV34
22
SM1
5%
1/16W
NV34
22
1/16W
5%
SM1
NV34
22
SM1
5%
1/16W
NV34
22
SM1
5%
1/16W
NV34
22
1/16W
5%
SM1
NV34
22
1/16W
5%
SM1
NV34
22
1/16W
5%
SM1
22
1/16W
5%
SM1
22
1/16W
5%
SM1
22
1/16W
5%
SM1
NV18B
BGA
NV18B
BGA
10
402
1/16W
1%
MF
0.1UF
402
CERM
10V
20%
0.1UF
20%
10V
CERM
402
0.1UF
20%
CERM
10V
402
0.1UF
20%
10V
CERM
402
0.1UF
20%
CERM
10V
402
0.1UF
402
CERM
10V
20%
0.01UF
16V
CERM
402
10%
0.1UF
20%
CERM
10V
402
0.1UF
20%
CERM
10V
402
0.1UF
20%
CERM
10V
402
0.1UF
20%
CERM
10V
402
0.01UF
CERM
16V
402
10%
0.01UF
16V
CERM
402
10%
0.1UF
402
CERM
10V
20%
0.01UF
10%
402
CERM
16V
0.1UF
402
CERM
10V
20%
0.1UF
402
10V
CERM
20%
0.01UF
10%
402
CERM
16V
0.1UF
402
10V
CERM
20%
0.1UF
402
10V
CERM
20%
0.01UF
10%
402
CERM
16V
69
051-6497
13
18
FBDQM<10>
FBDQM<11>
FBDQM<12>
RFBDQM<11>
RFBDQM<12>
RFBDQM<10>
FBDQM<9>
RFBACAS_L
NO_TEST
RFBARAS_L
NO_TEST
RFBDQM<8>
RFBDQM<9>
RFBBCS0_L
FBD<77>
FBD<89>
FBD<88>
FBD<86>
NC_FBDQS_L<12>
NO_TEST
NO_TEST
NC_RFBA<12>
NO_TEST
NC_RFBBA<12>
NC_VTT<0>
NO_TEST
NC_VTT<1>
NO_TEST
NC_VTT<2>
NO_TEST
NC_VTT<3>
NO_TEST
NC_VTT<4>
NO_TEST
NC_VTT<5>
NO_TEST
NC_VTT<6>
NO_TEST
NC_VTT<7>
NO_TEST
NC_VTT<8>
NO_TEST
NC_VTT<9>
NO_TEST
NC_VTT<10>
NO_TEST
NC_VTT<11>
NO_TEST
FBDQS<0>
FBDQS<1>
FBDQS<2>
FBDQS<6>
FBDQS<5>
FBDQS<7>
FBDQS<4>
FBDQS<3>
FBACLK0
FBACLK0_L
FBACLK1_L
FBACLK1
FBACKE
FBCAL_CLK_GND
FB_DLLVDD
FB_DLLVDD
FBCAL_TERM_GND
FBCAL_PU_GND
FBCAL_PD_VDDQ
ROMA15
TESTPOINT
ROMA14
TESTPOINT
NC_ROMCS_L
TESTPOINT
GPU_FB_VREF
NC_FBACS1_L
TESTPOINT
FBACS0_L
FBAWE_L
FBACAS_L
FBARAS_L
FBD<0>
FBD<1>
FBD<2>
FBD<3>
FBD<4>
FBD<5>
FBD<6>
FBD<7>
FBD<8>
FBD<9>
FBD<10>
FBD<11>
FBD<12>
FBD<13>
FBD<14>
FBD<15>
FBD<16>
FBD<17>
FBD<18>
FBD<19>
FBD<20>
FBD<21>
FBD<22>
FBD<23>
FBD<24>
FBD<25>
FBD<26>
FBD<27>
FBD<28>
FBD<29>
FBD<30>
FBD<31>
FBD<32>
FBD<33>
FBD<34>
FBD<35>
FBD<36>
FBD<37>
FBD<38>
FBD<39>
FBD<40>
FBD<41>
FBD<43>
FBD<44>
FBD<45>
FBD<46>
FBD<47>
FBD<48>
FBD<49>
FBD<50>
FBD<51>
FBD<52>
FBD<53>
FBD<54>
FBD<55>
FBD<56>
FBD<57>
FBD<58>
FBD<59>
FBD<60>
FBD<61>
FBD<62>
FBD<63>
FBD<42>
FBDQM<0>
FBDQM<1>
FBDQM<2>
FBDQM<3>
FBDQM<4>
FBDQM<5>
FBDQM<6>
FBDQM<7>
FBABA<1>
FBABA<0>
NC_FBDQS_L<2>
NC_FBDQS_L<1>
NC_FBDQS_L<0>
NC_FBDQS_L<4>
NC_FBDQS_L<3>
NC_FBDQS_L<5>
NC_FBDQS_L<6>
NC_FBDQS_L<7>
FBDQM<15>
FBDQM<14>
FBDQM<13>
FBDQM<12>
FBDQM<11>
FBDQM<10>
FBDQM<9>
FBDQM<8>
FBD<72>
FBD<73>
FBD<74>
FBD<75>
FBD<76>
FBD<78>
FBD<79>
FBD<80>
FBD<81>
FBD<82>
FBD<83>
FBD<84>
FBD<85>
FBD<87>
FBD<90>
FBD<91>
FBD<92>
FBD<93>
FBD<94>
FBD<95>
FBD<96>
FBD<97>
FBD<98>
FBD<99>
FBD<100>
FBD<101>
FBD<102>
FBD<103>
FBD<104>
FBD<105>
FBD<106>
FBD<107>
FBD<108>
FBD<109>
FBD<110>
FBD<111>
FBD<112>
FBD<113>
FBD<114>
FBD<115>
FBD<116>
FBD<117>
FBD<118>
FBD<119>
FBD<120>
FBD<121>
FBD<122>
FBD<123>
FBD<125>
FBD<126>
FBD<127>
FBD<71>
FBD<70>
FBD<69>
FBD<68>
FBD<67>
FBD<66>
FBD<65>
FBD<64>
FBBBA<0>
FBBBA<1>
FBBCLK0
FBBCLK0_L
FBBCLK1_L
FBBCLK1
FBDQS<8>
FBDQS<9>
FBDQS<10>
FBDQS<11>
FBDQS<12>
FBDQS<13>
FBDQS<14>
FBDQS<15>
NC_FBDQS_L<9>
NC_FBDQS_L<10>
NC_FBDQS_L<8>
NC_FBDQS_L<11>
NC_FBDQS_L<15>
NC_FBDQS_L<14>
NC_FBDQS_L<13>
FBBCAS_L
FBBRAS_L
TESTPOINT
NC_FBBCS1_L
FBBWE_L
FBBCS0_L
FBBCKE
FBACKE
RFBACKE
RFBABA<1>
FBABA<1>
RFBA<10>
RFBA<8>
RFBA<6>
RFBABA<0>
FBABA<0>
RFBA<11>
RFBA<9>
RFBA<7>
RFBA<5>
RFBA<2>
RFBA<4>
RFBA<0>
RFBACS0_L
NO_TEST
FBACS0_L
RFBA<3>
RFBA<1>
RFBAWE_L
FBAWE_L
FBARAS_L
FBACAS_L
FBDQM<6>
RFBDQM<6>
FBDQM<2>
RFBDQM<2>
FBDQM<4>
RFBDQM<4>
FBDQM<0>
RFBDQM<0>
FBDQM<7>
RFBDQM<7>
FBDQM<5>
RFBDQM<5>
FBDQM<3>
RFBDQM<3>
FBDQM<1>
RFBDQM<1>
RFBBBA<1>
FBBBA<1>
RFBBA<10>
RFBBA<6>
RFBBA<8>
FBBCKE
RFBBCKE
RFBBBA<0>
FBBBA<0>
RFBBA<11>
RFBBA<9>
RFBBA<7>
RFBBA<5>
RFBBA<4>
RFBBA<0>
RFBBA<2>
RFBBCAS_L
FBBCAS_L
FBDQM<14>
RFBDQM<14>
FBBCS0_L
FBDQM<8>
RFBBA<3>
RFBBA<1>
RFBBRAS_L
NO_TEST
FBBRAS_L
RFBBWE_L
FBBWE_L
FBDQM<15>
RFBDQM<15>
FBDQM<13>
RFBDQM<13>
FBCAL_TERM_GND
FBCAL_PU_GND
FBCAL_CLK_GND
MEMREFN1
NO_TEST
FBBA<0>
FBBA<0>
FBBA<1>
FBBA<1>
FBBA<2>
FBBA<2>
FBBA<3>
FBBA<3>
FBBA<4>
FBBA<4>
FBBA<5>
FBBA<5>
NO_TEST
FBBA<6>
FBBA<6>
FBBA<7>
FBBA<7>
FBBA<8>
FBBA<8>
FBBA<9>
FBBA<9>
FBBA<10>
FBBA<10>
FBBA<11>
FBBA<11>
FBBA<12>
FBBA<12>
FBA<0>
FBA<0>
FBA<1>
NO_TEST
FBA<1>
FBA<2>
FBA<2>
NO_TEST
FBA<3>
FBA<3>
FBA<4>
FBA<4>
FBA<5>
FBA<5>
NO_TEST
FBA<6>
FBA<6>
FBA<7>
FBA<7>
FBA<8>
FBA<8>
FBA<9>
FBA<9>
FBA<10>
FBA<10>
NO_TEST
FBA<11>
FBA<11>
FBA<12>
FBA<12>
FBD<124>
MEMREFN2
<XR_PAGE_TITLE>
C145
1
2
C96
1
2
C89
1
2
C80
1
2
C159
1
2
C167
1
2
C133
1
2
C98
1
2
C86
1
2
C84
1
2
C73
1
2
C81
1
2
C72
1
2
C78
1
2
C90
1
2
C75
1
2
C82
1
2
C79
1
2
C115
1
2
C175
1
2
C199
1
2
C83
1
2
RP84
1 8
RP85
3 6
RP8
1 8
RP8
3 6
RP8
2 7
RP8
4 5
R61
1
2
R62
12
R54
1
2
R58
1
2
R70
1
2
RP9
1 8
RP9
2 7
RP9
3 6
RP9
4 5
C95
1
2
C124
1
2
RP22
2 7
R90
1 2
R164
1 2
R154
1 2
RP22
1 8
RP22
3 6
RP94
3 6
RP22
4 5
RP95
1 8
RP95
3 6
RP94
2 7
RP94
4 5
RP95
2 7
RP95
4 5
RP23
1 8
RP23
3 6
R130
12
RP23
2 7
RP23
4 5
R131
1
2
C62
1
2
R71
1
2
R95
1
2
R88
1
2
R49
1 2
R50
1 2
R36
1
2
C54
1
2
C509
1
2
R41
1
2
R463
1
2
C510
1
2
U7
5
3
4
C69
1
2
C70
1
2
C61
1
2
R117
1 2
R111
1 2
R84
1 2
R155
1 2
R143
1 2
R64
1 2
R66
1 2
R67
1 2
R56
1 2
R59
1 2
ZT22
1
ZT23
1
ZT34
1
ZT24
1
ZT25
1
ZT37
1
ZT26
1
ZT27
1
ZT38
1
ZT36
1
ZT33
1
ZT35
1
ZT21
1
ZT32
1
ZT29
1
ZT20
1
ZT31
1
ZT30
1
ZT28
1
ZT6
1
ZT8
1
ZT11
1
ZT10
1
ZT12
1
ZT17
1
ZT14
1
ZT16
1
ZT18
1
ZT15
1
ZT9
1
ZT13
1
ZT4
1
ZT7
1
ZT3
1
ZT2
1
ZT19
1
R83
1
2
ZT1
1
ZT5
1
RP85
4 5
RP85
2 7
RP84
2 7
RP84
3 6
RP84
4 5
RP83
1 8
RP83
4 5
RP83
2 7
RP83
3 6
RP93
1 8
RP93
2 7
RP93
3 6
RP93
4 5
U39
V30
U28
R25
R30
U24
U29
T28
T29
T27
T30
T26
T25
R27
R26
R29
P29
N30
U21
V21
N21
P21
U27
P27
N25
N27
M28
L29
J29
J28
H29
G30
K25
J26
J25
G26
N26
F28
F26
E27
D27
H28
G29
F29
E29
C30
C29
M25
B30
A30
AJ29
AJ30
AH29
AH30
AF29
AE29
AD29
AC28
K26
AG28
AF27
AE26
AE28
AD25
AB25
AB26
AA25
AD30
AC29
K27
AB28
AB29
Y29
W28
W29
V29
AC27
AB27
AA27
AA26
J27
W25
V26
V27
V25
H27
N29
M29
L27
K29
G25
E28
AF28
AD27
AA30
Y27
M27
K30
G27
D30
AG30
AD26
AA29
W27
P28
R28
E3
F5
E4
D3
F17
G11
Y24
L24
G20
G23
H24
AC24
H25
P25
U25
AC25
G8
F8
L25
Y25
F11
F14
F20
F23
C28
C27
A25
AD28
AH18
F25
C18
E14
AF8
Y8
K3
G3
F6
AK25
AF17
AF23
AH24
AH28
AG27
AF26
AF14
AH13
L8
P26
AA5
G28
K28
N28
V28
AA28
F30
J30
M30
W30
AB30
AF20
AE30
H26
L26
Y26
AC26
E17
D28
C7
E8
A9
AH16
C10
E11
C13
E20
C21
E23
C24
A6
A12
AH10
AK15
AK12
C3
D4
E5
AG4
AH3
AK6
AH7
AF5
AE6
AF11
AK9
N3
H11
AC11
H20
AC20
L23
Y23
F1
J1
AH21
M1
T1
W1
AB1
AE1
A19
AK19
A22
AK22
K5
U26
J7
AE25
M26
L28
F27
D29
AG29
AE27
Y28
W26
G9
G12
W24
AB24
G15
G16
G19
G22
J24
M24
R24
T24
R2
R1
AF2
U39
K18
K17
K13
K14
A18
C17
F15
A15
G17
B17
C16
B16
D16
A16
E16
F16
D15
E15
B15
B14
A13
D17
D14
F13
D13
C12
B11
B9
C9
B8
A7
F10
E9
F9
F7
E13
C6
E6
D5
C4
C8
B7
B6
B5
A3
B3
F12
A2
B2
B29
A29
B28
A28
B26
B25
B24
C23
E10
E26
D26
E25
C25
E24
F22
E22
F21
A24
B23
D10
C22
B22
B20
C19
B19
B18
D23
D22
D21
E21
D9
F19
E18
D18
F18
D8
B13
B12
D11
B10
D7
C5
C26
F24
B21
D20
D12
A10
E7
A4
A27
D24
A21
D19
C14
C15
E12
C11
D6
B4
B27
D25
C20
E19
N13
U14
V14
W14
M15
N15
P15
R15
T15
U15
V15
P13
W15
M16
N16
P16
R16
T16
U16
V16
W16
M17
U13
N17
P17
R17
T17
U17
V17
W17
M18
N18
P18
V13
R18
T18
U18
V18
W18
M19
N19
P19
R19
T19
M14
U19
V19
W19
P12
N12
V12
U12
M12
R12
T12
N14
W12
M13
R13
T13
W13
P14
R14
T14
R52
1 2
LAST_MODIFIED=Wed Sep 17 12:16:07 2003
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DRAWING
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
PLACE 100OHM TERM AT RAM
PLACE 100OHM TERM AT RAM
PLACE R’S CLOSE TO GPU
PLACE 100OHM TERM AT RAM
PLACE 100OHM TERM AT RAM
PLACE THESE R CLOSE TO SGRAM PLACE THESE R CLOSE TO SGRAM
FB TERMINATION
PLACE THESE R CLOSE TO GPU PLACE THESE R CLOSE TO GPU
PLACE R’S BETWEEN GPU & MEMORY
15
15
15
15
15
15
15
15
15
15
402
1%
1/16W
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15
MF
1/16W
1%
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15
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1%
1/16W
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15
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1/16W
1%
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0
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402
0
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15
402
1%
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15
402
1%
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15
402
1%
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15
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15
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15
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402
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15
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0
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15
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15
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15
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15
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15
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15
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15
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0
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402
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15
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100
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100
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15
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15
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15
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15
6919
13
051-6497
FBBCLK1_L
RFBBCLK1
FBACLK0_L
FBBCLK1FBD<98>
NO_TEST
RFBD<117>
RFBD<108>
RFBD<111>
FBD<113>
NO_TEST
FBD<115>
NO_TEST
FBD<114>
NO_TEST
FBD<116>
FBD<117>
NO_TEST
FBD<118>
NO_TEST
FBD<119>
NO_TEST
FBD<120>
FBD<121>
NO_TEST
FBD<101>
FBD<102>
NO_TEST
FBD<105>
NO_TEST
FBD<23>
NO_TEST
FBD<19>
NO_TEST
FBD<17>
NO_TEST
FBD<18>
NO_TEST
RFBD<18>
RFBD<4>
RFBD<3>
RFBD<2>
FBD<1>
NO_TEST
RFBD<127>
RFBD<126>
RFBD<125>
RFBD<123>
RFBD<124>
RFBD<122>
RFBD<121>
RFBD<120>
RFBD<119>
RFBD<118>
RFBD<115>
RFBD<116>
RFBD<114>
RFBD<113>
RFBD<112>
RFBD<110>
RFBD<107>
RFBD<109>
RFBD<106>
RFBD<105>
RFBD<104>
RFBD<103>
RFBD<102>
RFBD<100>
RFBD<101>
RFBD<99>
RFBD<97>
RFBD<98>
RFBD<96>
RFBD<63>
RFBD<62>
RFBD<60>
RFBD<61>
RFBD<59>
RFBD<58>
RFBD<57>
RFBD<56>
RFBD<55>
RFBD<53>
RFBD<52>
RFBD<54>
RFBD<51>
NO_TEST
RFBD<50>
RFBD<47>
RFBD<49>
RFBD<48>
RFBD<46>
RFBD<45>
RFBD<43>
RFBD<42>
RFBD<44>
RFBD<41>
RFBD<40>
RFBD<39>
RFBD<37>
RFBD<38>
RFBD<36>
RFBD<35>
RFBD<34>
RFBD<33>
RFBD<32>
RFBBCLK0_L
FBBCLK0_L
RFBBCLK0
FBBCLK0
RFBBCLK1_L
RFBACLK0_L
RFBACLK0
FBACLK0
RFBACLK1_L
FBACLK1_L
RFBACLK1
FBACLK1
RFBDQS<9>
RFBDQS<10>
RFBDQS<11>
RFBDQS<13>
RFBDQS<14>
RFBDQS<15>
RFBDQS<12>
RFBDQS<8>
FBDQS<15>
FBDQS<14>
FBDQS<9>
FBDQS<11>
FBDQS<13>
FBDQS<12>
FBDQS<10>
FBDQS<8>
RFBDQS<7>
RFBDQS<5>
RFBDQS<6>
RFBDQS<3>
RFBDQS<4>
RFBDQS<2>
RFBDQS<1>
RFBDQS<0>
FBDQS<5>
FBDQS<7>
FBDQS<6>
FBDQS<3>
FBDQS<1>
FBDQS<4>
FBDQS<2>
FBDQS<0>
FBDQSTERM<15>
NO_TEST
FBDQSTERM<14>
NO_TEST
FBDQSTERM<13>
NO_TEST
FBDQSTERM<11>
NO_TEST
FBDQSTERM<12>
NO_TEST
FBDQSTERM<10>
NO_TEST
FBDQSTERM<9>
NO_TEST
FBDQSTERM<8>
NO_TEST
FBDQSTERM<7>
NO_TEST
FBDQSTERM<6>
NO_TEST
FBDQSTERM<1>
NO_TEST
FBDQSTERM<4>
NO_TEST
FBDQSTERM<2>
NO_TEST
FBDQSTERM<0>
NO_TEST
RFBD<94>
RFBD<95>
RFBD<93>
RFBD<91>
RFBD<92>
RFBD<89>
RFBD<90>
RFBD<88>
RFBD<87>
RFBD<86>
RFBD<84>
RFBD<85>
RFBD<83>
RFBD<82>
RFBD<81>
RFBD<79>
RFBD<80>
RFBD<78>
RFBD<76>
RFBD<77>
RFBD<73>
RFBD<74>
RFBD<75>
RFBD<71>
RFBD<72>
RFBD<70>
RFBD<69>
RFBD<68>
RFBD<66>
RFBD<67>
RFBD<65>
RFBD<64>
RFBD<30>
RFBD<29>
RFBD<27>
RFBD<28>
RFBD<26>
RFBD<10>
RFBD<9>
RFBD<12>
RFBD<11>
RFBD<13>
RFBD<15>
RFBD<14>
RFBD<17>
RFBD<16>
RFBD<19>
RFBD<20>
RFBD<22>
RFBD<21>
RFBD<23>
RFBD<25>
RFBD<24>
RFBD<8>
RFBD<6>
RFBD<7>
RFBD<5>
RFBD<1>
FBD<0>
FBD<2>
NO_TEST
FBD<3>
NO_TEST
FBD<4>
NO_TEST
FBD<5>
FBD<6>
NO_TEST
FBD<7>
NO_TEST
FBD<8>
NO_TEST
FBD<9>
FBD<10>
NO_TEST
FBD<11>
NO_TEST
FBD<12>
NO_TEST
FBD<13>
FBD<15>
NO_TEST
FBD<16>
FBD<20>
FBD<21>
NO_TEST
FBD<22>
NO_TEST
FBD<26>
NO_TEST
FBD<27>
NO_TEST
FBD<28>
FBD<29>
NO_TEST
FBD<30>
FBD<31>
NO_TEST
FBD<32>
FBD<33>
NO_TEST
FBD<34>
NO_TEST
NO_TEST
FBD<35>
FBD<36>
FBD<37>
NO_TEST
FBD<38>
FBD<39>
NO_TEST
FBD<40>
NO_TEST
FBD<41>
FBD<42>
NO_TEST
FBD<43>
NO_TEST
FBD<44>
NO_TEST
FBD<45>
FBD<46>
NO_TEST
FBD<47>
NO_TEST
FBD<48>
NO_TEST
FBD<49>
NO_TEST
FBD<51>
FBD<53>
FBD<54>
NO_TEST
FBD<55>
NO_TEST
FBD<56>
FBD<57>
NO_TEST
FBD<58>
NO_TEST
FBD<59>
NO_TEST
FBD<60>
FBD<61>
NO_TEST
FBD<62>
NO_TEST
FBD<63>
NO_TEST
FBD<64>
FBD<65>
NO_TEST
FBD<66>
NO_TEST
FBD<67>
FBD<68>
FBD<69>
NO_TEST
FBD<70>
NO_TEST
FBD<71>
NO_TEST
FBD<72>
NO_TEST
FBD<73>
NO_TEST
FBD<74>
NO_TEST
FBD<75>
FBD<76>
FBD<77>
NO_TEST
FBD<78>
NO_TEST
FBD<79>
NO_TEST
FBD<80>
FBD<81>
NO_TEST
FBD<82>
NO_TEST
FBD<83>
NO_TEST
FBD<84>
FBD<85>
NO_TEST
FBD<86>
NO_TEST
FBD<87>
NO_TEST
FBD<88>
NO_TEST
FBD<89>
FBD<90>
NO_TEST
FBD<91>
NO_TEST
FBD<92>
NO_TEST
FBD<93>
NO_TEST
FBD<94>
NO_TEST
FBD<95>
FBD<96>
FBD<97>
NO_TEST
NO_TEST
FBD<99>
NO_TEST
FBD<100>
FBD<103>
NO_TEST
FBD<104>
NO_TEST
FBD<106>
NO_TEST
FBD<107>
FBD<108>
FBD<109>
NO_TEST
FBD<110>
NO_TEST
FBD<111>
NO_TEST
FBD<112>
FBD<122>
NO_TEST
FBD<123>
NO_TEST
FBD<124>
FBD<125>
NO_TEST
FBD<126>
NO_TEST
FBD<127>
FBDQSTERM<3>
NO_TEST
FBDQSTERM<5>
NO_TEST
RFBD<0>
RFBD<31>
NO_TEST
FBD<14>
FBD<24>
FBD<25>
NO_TEST
FBD<52>
NO_TEST
FBD<50>
NO_TEST
<XR_PAGE_TITLE>
RP20
1 8
RP20
2 7
RP20
3 6
RP20
4 5
RP19
1 8
RP19
2 7
RP19
3 6
RP19
4 5
RP21
4 5
RP21
3 6
RP21
2 7
RP21
1 8
RP18
1 8
RP18
4 5
RP18
3 6
RP18
2 7
RP91
4 5
RP91
3 6
RP91
2 7
RP91
1 8
RP90
1 8
RP90
4 5
RP90
3 6
RP90
2 7
RP92
4 5
RP92
3 6
RP92
2 7
RP92
1 8
RP17
1 8
RP17
4 5
RP17
3 6
RP17
2 7
RP29
4 5
RP29
3 6
RP29
2 7
RP29
1 8
RP28
4 5
RP28
3 6
RP28
2 7
RP28
1 8
RP97
1 8
RP97
4 5
RP97
3 6
RP97
2 7
RP25
4 5
RP25
3 6
RP25
2 7
RP25
1 8
RP96
1 8
RP96
4 5
RP96
3 6
RP96
2 7
RP26
4 5
RP26
3 6
RP26
2 7
RP26
1 8
RP24
1 8
RP24
4 5
RP24
3 6
RP24
2 7
R148
12
R156
12
R123
12
R132
12
R122
12
R97
12
R479
1 2
R483
1 2
R104
12
R103
12
R105
12
R106
12
R509
1 2
R101
12
R506
1 2
R81
12
RP13
4 5
RP13
3 6
RP13
2 7
RP13
1 8
RP7
4 5
RP87
1 8
RP87
4 5
RP87
3 6
RP87
2 7
RP7
3 6
RP7
2 7
RP7
1 8
RP6
4 5
RP6
3 6
RP6
2 7
RP11
4 5
RP11
3 6
RP11
2 7
RP11
1 8
RP12
4 5
RP12
3 6
RP12
1 8
RP12
2 7
RP14
3 6
RP14
4 5
RP14
1 8
RP14
2 7
RP10
2 7
RP10
3 6
RP10
4 5
RP10
1 8
RP5
4 5
RP5
3 6
RP5
2 7
RP5
1 8
RP6
1 8
RP4
4 5
RP86
1 8
RP86
4 5
RP86
3 6
RP86
2 7
RP89
4 5
RP89
3 6
RP4
3 6
RP4
2 7
RP4
1 8
RP89
1 8
RP89
2 7
RP88
2 7
RP88
3 6
RP88
4 5
RP88
1 8
R140
12
R159
12
R147
12
R167
12
R153
1 2
R146
1 2
R186
1 2
R187
1 2
R428
1 2
R416
1 2
R31
1 2
R24
1 2
R32
1 2
R25
1 2
R415
1 2
R429
1 2
R63
12
R69
12
R53
12
R57
12
R65
12
R68
12
R55
12
R60
12
R158
1
2
R500
1
2
R20
1
2
R403
1
2
RP27
1 8
RP27
4 5
RP27
3 6
RP27
2 7
RP80
1 8
RP80
4 5
RP80
2 7
RP80
3 6
RP81
2 7
RP81
1 8
RP81
4 5
RP81
3 6
RP82
3 6
RP82
2 7
RP82
1 8
RP82
4 5
LAST_MODIFIED=Wed Sep 17 12:16:10 2003
55B3>
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55C3>
55D3>
55D3>
55D3>
55D3>
55D3>
55D3>
55D3>
18C5<>
21C2<
18D7>
18C5<> 18F5<>
21C1<>
21C1<>
21C1<>
18E5<>
18E5<>
18E5<>
18E5<>
18E5<>
18E5<>
18E5<>
18E5<>
18E5<>
18F5<>
18F5<>
18F5<>
18G8<>
18G8<>
18G8<>
18G8<> 20C5<>
20C5<>
20C5<>
20C5<>
18G8<>
21B1<>
21B1<>
21B1<>
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21C1<>
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20C1<>
20C1<>
20C1<>
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20C1<>
20C1<>
20C1<>
20C1<>
20C1<>
21C6<
18C5<>
21C6<
18C5<>
21C2<
20C6<
20C6< 18D7>
20C2< 18D7>
20C2< 18D7>
21C6<>
21C6<>
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21C2<>
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21C2<>
21C6<>
18D4<>
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18D4<>
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18D4<>
18D4<>
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20C2<>
20C2<>
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20C6<>
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20C6<>
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18C7<>
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18G5<>
18G5<>
18G5<>
18G5<>
18G5<>
18G5<>
18G5<>
18G5<>
18G5<>
18G5<>
18G5<>
18G5<>
18G5<>
18G5<>
18G5<>
18G5<>
18G5<>
18G5<>
18G5<>
18G5<>
18F5<>
18F5<>
18F5<>
18F5<>
18F5<>
18F5<>
18F5<>
18F5<>
18F5<>
18F5<>
18F5<>
18F5<>
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18F5<>
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18F5<>
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55C3>
55C3>
20C5<>
20B5<>
18G8<>
18G8<>
18F8<>
18E8<>
18E8<>
(1 OF 2)
CK
CK
CKE
RFU2
RFU1
MCL
DQ31
NC
BA1
DQ26
DQ27
DQ28
DQ29
DQ30
DQ25
DQ24
DQ21
DQ22
DQ23
DQ19
DQ20
DQ14
DQ16
DQ17
DQ18
DQ15
DQ13
DQ12
DQ11
DQ9
DQ10
DQ8
DQ4
DQ6
DQ5
DQ7
DQ3
DQ2
DQ1
DQ0
CS
RAS
CAS
WE
BA0
DM3
DQS3
DM2
DM1
DM0
DQS2
DQS0
DQS1
A0
A1
A2
A3
A6
A5
A4
A9
A8
A7
A10
A11
VSSQ
VSS_THERM
VSS
VDDQ
VREF
VDD
(2 OF 2)
(1 OF 2)
CK
CK
CKE
RFU2
RFU1
MCL
DQ31
NC
BA1
DQ26
DQ27
DQ28
DQ29
DQ30
DQ25
DQ24
DQ21
DQ22
DQ23
DQ19
DQ20
DQ14
DQ16
DQ17
DQ18
DQ15
DQ13
DQ12
DQ11
DQ9
DQ10
DQ8
DQ4
DQ6
DQ5
DQ7
DQ3
DQ2
DQ1
DQ0
CS
RAS
CAS
WE
BA0
DM3
DQS3
DM2
DM1
DM0
DQS2
DQS0
DQS1
A0
A1
A2
A3
A6
A5
A4
A9
A8
A7
A10
A11
VSSQ
VSS_THERM
VSS
VDDQ
VREF
VDD
(2 OF 2)
DESCRIPTION REFERENCE DES BOM OPTIONQTYPART NUMBER CRITICAL
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
DESCRIPTION REFERENCE DES BOM OPTIONQTYPART NUMBER CRITICAL
DRAWING
PLACE NEAR VDD PINS
SGRAM0 & SGRAM1 DDR MEMORY REFERENCE SUPPORT
PLACE NEAR VDD PINS
SGRAM0 & SGRAM1
SGRAM0 & SGRAM1 VREF
SGRAM0 & SGRAM1 MEMORY SUPPORT
10UF
Y5V
10V
N20P80%
805
10UF
Y5V
10V
N20P80%
805
0.1UF
CERM
402
10V
20%
0.1UF
402
20%
CERM
10V
0.1UF
402
CERM
10V
20%
0.1UF
CERM
20%
402
10V
0.1UF
CERM
402
10V
20%
0.1UF
402
CERM
10V
20%
0.1UF
20%
10V
CERM
402 402
10V
20%
CERM
0.1UF 0.1UF
20%
10V
402
CERM
0.1UF
10V
CERM
20%
402
0.1UF
20%
10V
CERM
402 402
0.1UF
10V
20%
CERM
10UF
Y5V
10V
N20P80%
805
10UF
Y5V
10V
N20P80%
805
SDRAM_DDR_4MX32
BGA
SEE_TABLE
SDRAM_DDR_4MX32
BGA
SEE_TABLE
SDRAM_DDR_4MX32
BGA
SEE_TABLE
SEE_TABLE
BGA
SDRAM_DDR_4MX32
+2_5V_MAIN
+2_5V_MAIN
+2_5V_MAIN +2_5V_MAIN
+2_5V_MAIN
+2_5V_MAIN+2_5V_MAIN
0
5%
1/16W
MF
402
MEMREFG_ACT
0
5%
1/16W
MF
402
MEMREFG_PAS
+2_5V_MAIN
SEE_TABLE
1K
MF
1/16W
5%
402
0.1UF
20%
10V
CERM
402
MEMREFG_PAS
0.1UF
CERM
10V
20%
402
MEMREFG_PAS
1K
MF
1/16W
1%
402
1K
1%
1/16W
MF
402
100PF
5%
50V
CERM
402
MEMREFG_ACT
TLV431A
SOT
MEMREFG_ACT
0.001UF
10%
50V
CERM
402
0.001UF
50V
10%
402
CERM
0.001UF
10%
50V
CERM
402
0.001UF
CERM
50V
10%
402
0.001UF
402
10%
50V
CERM
402
10%
50V
CERM
0.001UF
0.1UF
10V
20%
CERM
402
0.1UF
CERM
20%
10V
402
0.1UF
CERM
20%
10V
402 402
10V
20%
CERM
0.1UF
402
10V
20%
CERM
0.1UF
402
10V
20%
CERM
0.1UF
0.001UF
402
CERM
50V
10%
0.001UF
CERM
50V
10%
402
0.001UF
402
10%
50V
CERMCERM
0.001UF
402
10%
50V
0.1UF
10V
20%
CERM
402
402
20%
CERM
10V
0.1UF
R152 MEMREFG_ACT116S1103
1
RES,1K-OHM,5%,1/16W,0402
SAMSUNG_275_32M
CRITICAL
U12,U41
2
SDRAM,4MX32,DDR,275MHZ
333S0249
HYNIX_300_32M
CRITICAL
2
U12,U41
SDRAM,4MX32,DDR,300MHZ
333S0252
SAMSUNG_300_32M
2
U12,U41
CRITICAL
SDRAM,4MX32,DDR,300MHZ
333S0251
13
051-6497
6920
HYNIX_275_32M
CRITICAL
U12,U41
2
SDRAM,4MX32,DDR,275MHZ
333S0250
R152 MEMREFG_PAS
1
116S1000
RES,0-OHM,5%,1/16W,0402
SGRAVREF
RFBD<50>
NC_FB1<0>
NO_TEST
NC_FB1<1>
NO_TEST
NC_FB1<2>
NO_TEST
NC_FB1<3>
NO_TEST
NC_FB1<4>
NO_TEST
NC_FB1<5>
NO_TEST
NC_FB1<6>
NO_TEST
NC_FB1<7>
NO_TEST
NC_FB1<8>
NO_TEST
NC_FB1<9>
NO_TEST
NC_FB1<10>
NO_TEST
NC_FB2<0>
NO_TEST
NC_FB2<1>
NO_TEST
NC_FB2<2>
NO_TEST
NC_FB2<3>
NO_TEST
NC_FB2<4>
NO_TEST
NC_FB2<5>
NO_TEST
NC_FB2<6>
NO_TEST
NC_FB2<7>
NO_TEST
NC_FB2<8>
NO_TEST
NC_FB2<9>
NO_TEST
NC_FB2<10>
NO_TEST
SGRAVREF
RFBDQS<3>
RFBDQS<2>
RFBDQS<1>
RFBDQS<0>
RFBDQS<4>
RFBDQS<5>
RFBDQS<6>
RFBD<0>
RFBD<1>
RFBACKE
RFBACAS_L
RFBACS0_L
RFBARAS_L
RFBAWE_L
RFBACLK0_L
RFBACLK0
RFBABA<0>
RFBDQM<3>
RFBDQM<2>
RFBDQM<0>
RFBDQM<1>
RFBD<13>
RFBD<11>
RFBD<12>
RFBD<10>
RFBD<9>
RFBD<8>
RFBD<6>
RFBD<7>
RFBD<4>
RFBD<3>
RFBD<5>
RFBD<2>
RFBD<31>
RFBD<30>
RFBD<29>
RFBD<26>
RFBD<28>
RFBD<27>
RFBD<24>
RFBD<21>
RFBD<15>
RFBD<14>
RFBD<17>
RFBD<16>
RFBD<18>
RFBD<19>
RFBD<20>
RFBD<22>
RFBD<23>
RFBDQM<5>
RFBDQM<4>
RFBDQM<6>
RFBDQM<7>
RFBABA<0>
RFBACAS_L
RFBACS0_L
RFBARAS_L
RFBAWE_L
RFBD<32>
RFBD<34>
RFBD<33>
RFBD<37>
RFBD<35>
RFBD<36>
RFBD<39>
RFBD<38>
RFBD<40>
RFBD<41>
RFBD<42>
RFBD<44>
RFBD<43>
RFBD<47>
RFBD<45>
RFBD<46>
RFBD<49>
RFBD<48>
RFBD<51>
RFBD<52>
RFBD<54>
RFBD<55>
RFBD<53>
RFBD<56>
RFBD<57>
RFBD<59>
RFBD<60>
RFBD<58>
RFBD<61>
RFBD<62>
RFBD<63>
RFBACLK1
RFBACLK1_L
RFBACKE
RFBA<0>
RFBA<0>
RFBA<1>
RFBA<1>
RFBA<3>
RFBA<3>
RFBA<2>
RFBA<2>
RFBA<6>
RFBA<6>
RFBA<5>
RFBA<4>
RFBA<4>
RFBA<7>
RFBA<7>
RFBA<8>
RFBA<8>
RFBA<9>
RFBA<9>
RFBA<10>
RFBA<10>
RFBA<11>
RFBA<11>
RFBABA<1>
RFBABA<1>
SGRAVREFMEMREFG1
MEMREFG2
RFBA<5>
RFBDQS<7>
RFBD<25>
<XR_PAGE_TITLE>
C205
1
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1
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1
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1
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F5
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H10
J5
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K5
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D5
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D9
D10
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F6
F7
H8
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F8
F9
G6
G7
G8
G9
H6
H7
U41
N5
N6
L6
M7
M6
N7
N8
M9
N9
N10
N11
M8
N4
M5
L2
M11
M12
N12
N2
B3
H12
H3
B12
B7
C6
J13
J12
G13
G12
F13
F12
F3
F2
G3
G2
B6
J3
J2
K2
K3
E13
D13
D12
C13
B10
B9
B5
C9
B8
C2
D3
D2
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K13
K12
B2
H13
H2
B13
M13
C4
C11
H4
H11
L12
L13
M3
M4
N3
M2
L9
M10
L3
U41
D7
D8
E4
E11
L4
L7
L8
L11
C3
C5
G4
G11
J4
J11
K4
K11
C7
C8
C10
C12
E3
E12
F4
F11
N13
E5
E7
E8
E10
K6
K7
K8
K9
L5
L10
B4
B11
F5
F10
G5
G10
H5
H10
J5
J10
K5
K10
D4
D5
D6
D9
D10
D11
E6
E9
F6
F7
H8
H9
J6
J7
J8
J9
F8
F9
G6
G7
G8
G9
H6
H7
R151
1 2
R166
1 2
R152
1
2
C157
1
2
C172
1
2
R163
1
2
R176
1
2
C191
1
2
U16
5
3
4
C569
1
2
C566
1
2
C535
1
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C565
1
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C533
1
2
C143
1
2
C540
1
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C544
1
2
C532
1
2
C158
1
2
C142
1
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C144
1
2
C166
1
2
C173
1
2
C195
1
2
C194
1
2
C2201
1
2
C2202
1
2
LAST_MODIFIED=Wed Sep 17 12:16:13 2003
52A6>
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(1 OF 2)
CK
CK
CKE
RFU2
RFU1
MCL
DQ31
NC
BA1
DQ26
DQ27
DQ28
DQ29
DQ30
DQ25
DQ24
DQ21
DQ22
DQ23
DQ19
DQ20
DQ14
DQ16
DQ17
DQ18
DQ15
DQ13
DQ12
DQ11
DQ9
DQ10
DQ8
DQ4
DQ6
DQ5
DQ7
DQ3
DQ2
DQ1
DQ0
CS
RAS
CAS
WE
BA0
DM3
DQS3
DM2
DM1
DM0
DQS2
DQS0
DQS1
A0
A1
A2
A3
A6
A5
A4
A9
A8
A7
A10
A11
VSSQ
VSS_THERM
VSS
VDDQ
VREF
VDD
(2 OF 2)
(1 OF 2)
CK
CK
CKE
RFU2
RFU1
MCL
DQ31
NC
BA1
DQ26
DQ27
DQ28
DQ29
DQ30
DQ25
DQ24
DQ21
DQ22
DQ23
DQ19
DQ20
DQ14
DQ16
DQ17
DQ18
DQ15
DQ13
DQ12
DQ11
DQ9
DQ10
DQ8
DQ4
DQ6
DQ5
DQ7
DQ3
DQ2
DQ1
DQ0
CS
RAS
CAS
WE
BA0
DM3
DQS3
DM2
DM1
DM0
DQS2
DQS0
DQS1
A0
A1
A2
A3
A6
A5
A4
A9
A8
A7
A10
A11
VSSQ
VSS_THERM
VSS
VDDQ
VREF
VDD
(2 OF 2)
DRAWING
DESCRIPTION REFERENCE DES BOM OPTIONQTYPART NUMBER CRITICAL
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
DESCRIPTION REFERENCE DES BOM OPTIONQTYPART NUMBER CRITICAL
PLACE NEAR VDD PINS
SGRAM2 & SGRAM3
PLACE NEAR VDD PINS
SGRAM2 & SGRAM3 DDR MEMORY REFERENCE SUPPORT
SGRAM0 & SGRAM1 MEMORY SUPPORT
SGRAM2 & SGRAM3 VREF
64M_GRAM_DECOUP
Y5V
10V
N20P80%
805
10UF
Y5V
10V
N20P80%
805
10UF
64M_GRAM_DECOUP
64M_GRAM_DECOUP
0.1UF
CERM
402
10V
20%
64M_GRAM_DECOUP
0.1UF
402
20%
CERM
10V
64M_GRAM_DECOUP
0.1UF
402
CERM
10V
20%
64M_GRAM_DECOUP
0.1UF
CERM
20%
402
10V
64M_GRAM_DECOUP
0.1UF
CERM
402
10V
20%
64M_GRAM_DECOUP
0.1UF
402
CERM
10V
20%
64M_GRAM_DECOUP
0.1UF
20%
10V
CERM
402
64M_GRAM_DECOUP
0.1UF
10V
402
20%
CERM
64M_GRAM_DECOUP
0.1UF
402
20%
10V
CERM
64M_GRAM_DECOUP
0.1UF
10V
CERM
20%
402
64M_GRAM_DECOUP
0.1UF
20%
10V
CERM
402
64M_GRAM_DECOUP
0.1UF
10V
402
20%
CERM
64M_GRAM_DECOUP
Y5V
10V
N20P80%
805
10UF10UF
805
N20P80%
10V
Y5V
64M_GRAM_DECOUP
SEE_TABLE
SDRAM_DDR_4MX32
BGA
SEE_TABLE
SDRAM_DDR_4MX32
BGA
SEE_TABLE
SDRAM_DDR_4MX32
BGA
BGA
SDRAM_DDR_4MX32
SEE_TABLE
+2_5V_MAIN
+2_5V_MAIN
+2_5V_MAIN +2_5V_MAIN
+2_5V_MAIN
+2_5V_MAIN+2_5V_MAIN
MEMREFG_ACT_64M
5%
1/16W
MF
402
0
MEMREFG_PAS_64M
5%
1/16W
MF
402
0
+2_5V_MAIN
402
MF
1/16W
5%
1K
SEE_TABLE
MEMREFG_PAS_64M
402
CERM
10V
20%
0.1UF
MEMREFG_PAS_64M
0.1UF
10V
402
20%
CERM
1K
MF
1/16W
1%
402
64M_GRAM_DECOUP
64M_GRAM_DECOUP
1K
402
MF
1/16W
1%
MEMREFG_ACT_64M
CERM
50V
5%
402
100PF
MEMREFG_ACT_64M
TLV431A
SOT
64M_GRAM_DECOUP
0.1UF
CERM
20%
10V
402
64M_GRAM_DECOUP
20%
0.1UF
10V
CERM
402
64M_GRAM_DECOUP
0.1UF
CERM
20%
10V
402
64M_GRAM_DECOUP
0.001UF
CERM
50V
10%
402
64M_GRAM_DECOUP
0.1UF
10V
20%
CERM
402
64M_GRAM_DECOUP
0.1UF
CERM
20%
10V
402
64M_GRAM_DECOUP
0.1UF
10V
20%
CERM
402
64M_GRAM_DECOUP
0.001UF
10%
50V
CERM
402
0.001UF
CERM
50V
10%
402
64M_GRAM_DECOUP 64M_GRAM_DECOUP
0.001UF
402
CERM
50V
10%
64M_GRAM_DECOUP
0.001UF
402
10%
50V
CERM
64M_GRAM_DECOUP
0.001UF
402
CERM
50V
10%
0.001UF
402
10%
50V
CERM
64M_GRAM_DECOUP 64M_GRAM_DECOUP
0.001UF
402
CERM
50V
10%
64M_GRAM_DECOUP
0.001UF
402
10%
50V
CERM
64M_GRAM_DECOUP
0.001UF
402
CERM
50V
10%
0.1UF
10V
402
20%
CERM
64M_GRAM_DECOUP
64M_GRAM_DECOUP
20%
CERM
402
10V
0.1UF
MEMREFG_PAS_64M
R18
RES,0-OHM,5%,1/16W,0402
116S1000
1
MEMREFG_ACT_64M
RES,1K-OHM,5%,1/16W,0402
R18
1
116S1103
HYNIX_275_64M
CRITICAL
SDRAM,4MX32,DDR,275MHZ
U5,U36333S0250
2
21 69
051-6497
13
HYNIX_300_64MU5,U36333S0252
SDRAM,4MX32,DDR,300MHZ
CRITICAL
2
SAMSUNG_300_64M
U5,U36
SDRAM,4MX32,DDR,300MHZ
333S0251
CRITICAL
2
SAMSUNG_275_64M
U5,U36
SDRAM,4MX32,DDR,275MHZ
CRITICAL
333S0249
2
SGRBVREF
SGRBVREF
RFBD<68>
SGRBVREF
RFBBCAS_L
RFBBCAS_L
RFBD<64>
RFBD<65>
RFBBCKE
RFBBCS0_L
RFBBRAS_L
RFBBWE_L
RFBBCLK0_L
RFBBCLK0
RFBBBA<1>
RFBBBA<0>
RFBDQM<11>
RFBDQM<10>
RFBDQM<8>
RFBDQM<9>
RFBDQS<11>
RFBBA<11>
RFBBA<10>
RFBBA<9>
RFBBA<8>
RFBBA<7>
RFBBA<5>
RFBBA<6>
RFBDQS<10>
RFBDQS<9>
RFBDQS<8>
RFBBA<3>
RFBBA<2>
RFBBA<4>
RFBD<77>
RFBD<75>
RFBD<76>
RFBD<74>
RFBD<73>
RFBD<72>
RFBD<70>
RFBD<71>
RFBD<67>
RFBD<69>
RFBD<66>
RFBD<95>
RFBD<94>
RFBD<93>
RFBD<90>
RFBD<91>
RFBD<89>
RFBD<88>
RFBD<85>
RFBD<79>
RFBD<78>
RFBD<81>
RFBD<80>
RFBD<82>
RFBD<83>
RFBD<84>
RFBD<86>
RFBD<87>
RFBBA<11>
RFBBA<10>
RFBBA<9>
RFBBA<8>
RFBBA<7>
RFBBA<4>
RFBBA<5>
RFBBA<6>
RFBBA<2>
RFBBA<3>
RFBBA<1>
RFBBA<0>
RFBDQS<12>
RFBDQS<13>
RFBDQS<15>
RFBDQS<14>
RFBDQM<13>
RFBDQM<12>
RFBDQM<14>
RFBDQM<15>
RFBBBA<0>
RFBBCS0_L
RFBBRAS_L
RFBBWE_L
RFBD<96>
RFBD<98>
RFBD<97>
RFBD<101>
RFBD<99>
RFBD<100>
RFBD<103>
RFBD<102>
RFBD<104>
RFBD<105>
RFBD<106>
RFBD<108>
RFBD<107>
RFBD<111>
RFBD<109>
RFBD<110>
RFBD<113>
RFBD<112>
RFBD<114>
RFBD<115>
RFBD<116>
RFBD<118>
RFBD<119>
RFBD<117>
RFBD<120>
RFBD<121>
RFBD<123>
RFBD<124>
RFBD<122>
RFBD<125>
RFBD<126>
RFBBBA<1>
RFBD<127>
RFBBCLK1
RFBBCLK1_L
RFBBCKE
RFBBA<0>
NC_FB4<10>
NO_TEST
NC_FB4<9>
NO_TEST
NC_FB4<8>
NO_TEST
NC_FB4<7>
NO_TEST
NC_FB4<6>
NO_TEST
NC_FB4<5>
NO_TEST
NC_FB4<4>
NO_TEST
NC_FB4<3>
NO_TEST
NC_FB4<2>
NO_TEST
NC_FB4<1>
NO_TEST
NC_FB4<0>
NO_TEST
NC_FB3<10>
NO_TEST
NC_FB3<9>
NO_TEST
NC_FB3<8>
NO_TEST
NC_FB3<7>
NO_TEST
NC_FB3<6>
NO_TEST
NC_FB3<5>
NO_TEST
NC_FB3<4>
NO_TEST
NC_FB3<3>
NO_TEST
NC_FB3<2>
NO_TEST
NC_FB3<1>
NO_TEST
NC_FB3<0>
NO_TEST
RFBD<92>
RFBBA<1>
MEMREFG3
MEMREFG4
<XR_PAGE_TITLE>
C492
1
2
C15
1
2
C22
1
2
C23
1
2
C29
1
2
C34
1
2
C20
1
2
C31
1
2
C462
1
2
C488
1
2
C461
1
2
C469
1
2
C486
1
2
C476
1
2
C38
1
2
C460
1
2
U5
N5
N6
L6
M7
M6
N7
N8
M9
N9
N10
N11
M8
N4
M5
L2
M11
M12
N12
N2
B3
H12
H3
B12
B7
C6
J13
J12
G13
G12
F13
F12
F3
F2
G3
G2
B6
J3
J2
K2
K3
E13
D13
D12
C13
B10
B9
B5
C9
B8
C2
D3
D2
E2
K13
K12
B2
H13
H2
B13
M13
C4
C11
H4
H11
L12
L13
M3
M4
N3
M2
L9
M10
L3
U5
D7
D8
E4
E11
L4
L7
L8
L11
C3
C5
G4
G11
J4
J11
K4
K11
C7
C8
C10
C12
E3
E12
F4
F11
N13
E5
E7
E8
E10
K6
K7
K8
K9
L5
L10
B4
B11
F5
F10
G5
G10
H5
H10
J5
J10
K5
K10
D4
D5
D6
D9
D10
D11
E6
E9
F6
F7
H8
H9
J6
J7
J8
J9
F8
F9
G6
G7
G8
G9
H6
H7
U36
N5
N6
L6
M7
M6
N7
N8
M9
N9
N10
N11
M8
N4
M5
L2
M11
M12
N12
N2
B3
H12
H3
B12
B7
C6
J13
J12
G13
G12
F13
F12
F3
F2
G3
G2
B6
J3
J2
K2
K3
E13
D13
D12
C13
B10
B9
B5
C9
B8
C2
D3
D2
E2
K13
K12
B2
H13
H2
B13
M13
C4
C11
H4
H11
L12
L13
M3
M4
N3
M2
L9
M10
L3
U36
D7
D8
E4
E11
L4
L7
L8
L11
C3
C5
G4
G11
J4
J11
K4
K11
C7
C8
C10
C12
E3
E12
F4
F11
N13
E5
E7
E8
E10
K6
K7
K8
K9
L5
L10
B4
B11
F5
F10
G5
G10
H5
H10
J5
J10
K5
K10
D4
D5
D6
D9
D10
D11
E6
E9
F6
F7
H8
H9
J6
J7
J8
J9
F8
F9
G6
G7
G8
G9
H6
H7
R17
1 2
R5
1 2
R18
1
2
C8
1
2
C9
1
2
R6
1
2
R4
1
2
C11
1
2
U2
5
3
4
C467
1
2
C487
1
2
C493
1
2
C494
1
2
C17
1
2
C39
1
2
C21
1
2
C32
1
2
C470
1
2
C466
1
2
C475
1
2
C489
1
2
C16
1
2
C40
1
2
C33
1
2
C28
1
2
C2301
1
2
C2302
1
2
LAST_MODIFIED=Wed Sep 17 12:16:15 2003
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