Apple A1212 Schematic Rev06004

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_HEAD

TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

DRAWING

TABLE_TABLEOFCONTENTS_HEAD

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

ANGLES

3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

DATE

APPD

ENG

DATE

APPD

CK

ECN

ZONE

REV

DO NOT SCALE DRAWING

X.XXX

X.XX

XX

DIMENSIONS ARE IN MILLIMETERS

THIRD ANGLE PROJECTION

D

SIZE

APPLICABLE

NOTED AS

MATERIAL/FINISH

NONE

SCALE

DESIGNER

MFG APPD

DESIGN CK

RELEASE

QA APPD

ENG APPD

DRAFTER

METRIC

OF

SHT

DRAWING NUMBER

TITLE

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

Apple Computer Inc.

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

DESCRIPTION OF CHANGE

Schematic / PCB #’s

SCHEMATIC,MACBOOK PRO 17"

9/26/2006

ALIASES RESOLVED

SCHEMATIC,MACBOOK PRO 17

?

? ??

?

871

051-7164 06004

(.CSA)

SYNC

DATE

CONTENTS

PAGE

LAST_MODIFIED=Tue Sep 26 13:17:56 2006

TITLE=TRUCKEE ABBREV=DRAWING

44

M59_MLB

FireWire Ports

06/27/2006

46

SCHEM,TRUCKEE,M57

051-7164 CRITICAL

SCH1

PCBF,TRUCKEE,M57

CRITICAL

PCB1

820-2059

N/A

1

Table of Contents

PAGE

(.CSA)

SYNC

DATE

CONTENTS

45

M59_MLB

Camera Connector

09/15/2006

49

46

(MASTER)

Internal USB Hub

(MASTER)

50

47

M59_MLB

External USB Connector

09/15/2006

52

48

(MASTER)

Left I/O Board Connector

(MASTER)

55

49

(MASTER)

Current & Thermal Sensors

(MASTER)

56

50

(MASTER)

PCI-E Connections

(MASTER)

57

51

M59_MLB

SMC

09/15/2006

58

52

M59_MLB

SMC Support

09/15/2006

59

53

(MASTER)

LPC+ Debug Connector

(MASTER)

60

54

M59_MLB

Thermal Sensors

09/15/2006

61

55

M59_MLB

Current & Voltage Sensing

09/15/2006

62

56

M59_MLB

SPI BOOTROM

09/15/2006

63

57

(MASTER)

ALS Support

(MASTER)

64

58

(MASTER)

Fan Connectors

(MASTER)

65

59

M59_MLB

Sudden Motion Sensor (SMS)

09/15/2006

66

60

M59_MLB

TPM

09/15/2006

67

61

M59_MLB

IMVP6 CPU VCore Regulator

09/15/2006

75

62

M59_MLB

5V / 1.5V Power Supply

09/15/2006

76

63

M59_MLB

2.5V & 1.2V Regulators

09/15/2006

77

64

(MASTER)

1.8V Supply

(MASTER)

78

65

(MASTER)

3.3V / 1.05V Power Supplies

(MASTER)

79

66

M59_MLB

3.3V G3Hot Supply & Power Control

09/15/2006

80

67

(MASTER)

Power Aliases

(MASTER)

81

68

(MASTER)

DC-In & Battery Connectors

(MASTER)

82

69

M59_LIO

PBus Supply & Batt. Charger

09/15/2006

83

70

(MASTER)

ATI M56 PCI-E

(MASTER)

84

71

(MASTER)

GPU (M56) Core Supplies

(MASTER)

85

72

(MASTER)

ATI M56 Core Power

(MASTER)

86

73

(MASTER)

ATI M56 Frame Buffer I/F

(MASTER)

87

74

M57_MLB_MG

GPU Straps

08/08/2006

88

75

(MASTER)

GDDR3 Frame Buffer A

(MASTER)

89

76

(MASTER)

GDDR3 Frame Buffer B

(MASTER)

90

77

(MASTER)

ATI M56 GPIO/DVO/Misc

(MASTER)

91

78

(MASTER)

ATI M56 Video Interfaces

(MASTER)

93

79

M57_MLB_MG

Internal Display Connectors

08/08/2006

94

80

M59_MLB

External Display Connector

09/15/2006

97

81

(MASTER)

M57 SPECIFIC CONNECTORS

(MASTER)

98

82

M59_MLB

LVDS Interface Pull-downs

09/15/2006

99

83

(MASTER)

Revision History

(MASTER)

100

84

(MASTER)

Napa Platform Constraints

(MASTER)

101

85

(MASTER)

More System Constraints

(MASTER)

102

86

(MASTER)

M9 Spacing & Physical Constraints

(MASTER)

103

87

(MASTER)

M57 NET PROPERTIES

(MASTER)

104

(MASTER)

2

System Block Diagram

(MASTER)

3

Power Block Diagram

(MASTER)

4

BOM CONFIGURATION

(MASTER)

5

Functional / ICT Test

(MASTER)

6

Signal Aliases

M59_MLB

09/15/2006

7

CPU 1 OF 2-FSB

M59_MLB

09/15/2006

8

CPU 2 OF 2-PWR/GND

M59_MLB

09/15/2006

9

CPU Decoupling & VID

M59_MLB

09/15/2006

10

CPU MISC1-TEMP SENSOR

(MASTER)

11

CPU ITP700FLEX DEBUG

M59_MLB

09/15/2006

12

NB CPU Interface

M59_MLB

09/15/2006

13

NB PEG / Video Interfaces

M59_MLB

09/15/2006

14

NB Misc Interfaces

M59_MLB

09/15/2006

15

NB DDR2 Interfaces

M59_MLB

09/15/2006

16

NB Power 1

M59_MLB

09/15/2006

17

NB Power 2

M59_MLB

09/15/2006

18

NB Grounds

M57_MLB_MG

08/08/2006

19

NB (GM) Decoupling

M59_MLB

09/15/2006

20

NB Config Straps

M59_MLB

09/15/2006

21

SB: 1 OF 4

M59_MLB

09/15/2006

22

SB: 2 of 4

M57_MLB_MG

08/08/2006

23

SB: 3 OF 4

M59_MLB

09/15/2006

24

SB: 4 OF 4

M59_MLB

09/15/2006

25

SB Decoupling

(MASTER)

26

SB Misc

(MASTER)

27

M57 SMBUS CONNECTIONS

M59_MLB

09/15/2006

28

DDR2 SO-DIMM Connector A

M59_MLB

09/15/2006

29

DDR2 SO-DIMM Connector B

(MASTER)

30

Memory Active Termination

M59_MLB

09/15/2006

31

Memory Vtt Supply

M59_MLB

09/15/2006

32

DDR2 VRef

M59_MLB

09/15/2006

33

CLOCKS

M59_MLB

09/15/2006

34

Clock Termination

M59_MLB

09/15/2006

35

37

Mobile Clocking

(MASTER)

36

38

PATA Connector

M59_MLB

09/15/2006

37

39

FireWire Link (TSB83AA22)

M59_MLB

09/15/2006

38

40

FireWire PHY (TSB83AA22)

M59_MLB

09/15/2006

39

41

ETHERNET CONTROLLER

M59_MLB

09/15/2006

40

42

Ethernet Connector

M59_MLB

09/15/2006

41

43

Yukon Power Control

M59_MLB

09/15/2006

42

44

FW PHY Power Supply

(MASTER)

43

45

FireWire Port Power

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

P.61-68,71

P.69

P.48

P.55

P.59

P.57

P.53

P. 60

P.51-52

P.58

P.56

P.48,54

P.45

Camera

P.81

P.70-74,77-78

P.75-76

P.80

P.79

Dual-Channel LVDS

PWM

MUX

S-Video/Composite

Dual-Channel TMDS

LVDS Graphics

P.43

Port Power

PCIe x16

DMI x4

PCIe x1

Batt Chgr/

PBUS Supply

ICH7-M

SB

LPC 33MHZ

PHY Power

P.42

1394a/b (FireWire)

Supplies

RJ45 (Ethernet)

Connector

P.40

Power

Connectors

P.27

P.36

P.45

P.32

P.28

P.29

P.30-31

P.12-20

P.11

P.7-9

P.10

DVI-I/DL Connector

ENET

Frame Buffer 128MB/256MB

GPU

H8S/2116

SMBus x5

Analog

Battery SMBus

DDR2 SO-DIMM B

SMC SMBus

PWM/Tach

Connectors

Fan

SMS

FW

PCI

Yukon Power

INVERTER

CONNECTOR

Connector

ODD

Connector

Geyser KB /

TP Connector

16BITS

66MHZ

PATA

SB SMBus

USB

SMBus

BootROM

SPI

SMC

Sensors

609 BGA

USB

GDDR3

THERMAL

CPU Core Duo

945GM

1466UFCBGA

NB

FSB

CH.B

CH.A

479 BGA

CPU Debug

ITP700FLEX

Connector

PCIe x1

Azalia (HD-Audio)

BUFFER

DDR2 VREF

Left I/O &

Audio Board

Connector

J2900

J2800

DDR2 SO-DIMM A

DDR2 VTT

& REGULATOR

SENSOR

w/TV-Out Support

USB x2

Connectors

P.44

TSB83AA22 FireWire

Controller

P.37-38

P.41

P.39

Yukon Gig-E

ATI M56P

(Merom)

Factory/Upper Connector

Expansion/Lower Connector

RT ALS

P.21-26

Debug

LPC

Connector

TPM

P.79,82

LCD Panel

Connector

Sensors

Temperature

P.33-34

Controller

CK410 Clock

P.68

HDD/BT

USB

SATA

Right USB 2.0

Connector

P.47

PCIe x1

Controller

P.78

USB

Connector

USB 2.0 Hub/Sleep LED IR

P.46,81

051-7164

872

06004

System Block Diagram

SYNC_MASTER=(MASTER)

SYNC_DATE=(MASTER)

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

ACIN_ENABLE_DIV_L

J8290

Connector

LIO Power

J8290

MLB DC in Connector

Q8250

PP18V5_G3H_CHGR

Q7615

ENABLE

(ISL6255AHRZ)

PM_SLP_S3_LS5V_L

5.0V

PP1V8_S3

1.8V

3.3V

PPVCORE_S0_GPU

PGOOD

IMVP_PWRGD_IN

U7530

PP3V3_S5

PP1V05_S0

1.05V

PM_SLP_S3_L

Q7845

ENABLES

PPVCORE_S0_CPU

U7750

Q7770

"IMVP6"

PGOOD

RSMRST_PWRGD

Inverter

Connector

PPBUS_S5_FWPORT

12.6V - 9V

FWPWR_EN

5V/1.5V

U8500

PP3V3_S0

NC

1.5V

PGOOD

S5

3.3V

ENABLE

PGOOD

1.05V

U7950

S0

GPU VCore

ENABLE

3.3V

NC

(LTC3412)

S3

PGOOD

1.2V

ENABLE

1.2V

PP1V2_S3

2.5V

PGOOD

PP1V5_S0

5.0V

PP5V_S5

NC

PGOOD

ENABLES

U7600

5V

1.5V

SMC_PM_G2_ENABLE

VR_PWRGOOD_DELAY

S0

CPU VCore

IMVP_VR_ON

S0

ENABLE

NC

1.8V

U7800

S3

ENABLE

PGOOD

PM_SLP_S3_L

U3100

0.9V (Vtt) S0

PP0V9_S0

0.9V

Q4565

1.2V

PM_SLP_S3_LS5V_L

1.8V

PM_SLP_S4_L

PM_SLP_S3_L

Q7947

(ISL9504)

(TPS5117RGY)

(TPS51100)

(ISL6269B)

S3

S5S0

2.5V

ENABLE

(TPS62510)

PP1V2_D3C

P1V2R2V5D3C_EN_LS5V

PP2V5_S3

NC

Q7721

2.5V

P1V2R2V5DC3_EN_LS5V

PP2V5_D3C

2.5V

Q7720

PP2V5_S0

PM_SLP_S3_LS5V

Q7945

3.3V

PP3V3_S3

3.3V

Q4300

PP3V3_S3AC

PM_SLP_S3BATT

5.0V

PP5V_S0

5.0V

Q3820

PP5V_S0_IDE_ODD

ODD_PWR_EN_L (SB GPIO14)

PM_SLP_S3BATT

PM_SLP_S4_LS5V

PM_SLP_S3_LS5V

U7700

IMVP_PWRGD_IN/ALL_SYS_PWRGD

U7900

SMC_PM_G2_ENABLE

1.1V - 0.95V

=GPUVCORE_EN_L

PP1V8_D3C

J9450

1.25V - 0.8V

(LTC3728)

12.6V - 9V

G3Hot

U8000

PP3V42_G3H

3.425V

ENABLE

(LT3470)

3.425

PPBUS_G3H

12.6 - 9V

PBUS

SUPPLY

U8300

PPBUS_G3H

5.0V

Q7610

PM_SLP_S4_LS5V

PP5V_S3

18.5V - 9V

PPDCIN_G3H

3 87

06004051-7164

Power Block Diagram

SYNC_MASTER=(MASTER)

SYNC_DATE=(MASTER)

TABLE_BOMGROUP_ITEM

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

BOM OPTIONS

BOM NAME

BOM NUMBER

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

TABLE_ALT_ITEM

PART NUMBER

ALTERNATE FOR

PART NUMBER

BOM OPTION

REF DES

COMMENTS:

TABLE_ALT_HEAD

TABLE_ALT_ITEM

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

BOM OPTIONS

BOM GROUP

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM GROUP

TABLE_BOMGROUP_HEAD

BAR CODE LABELS / EEE #’S

ALTERNATE PARTS

MODULE PARTS

IS

Extra TPM options: SMC_TPM_GPIO2 SMC_TPM_GPIO1 SMC_TPM_PP

VRAM_128_SAMSUNG

VRAM_128SAM

VRAM_256SAM

GPU_MEM_256M,VRAM_256_SAMSUNG

U3301

359S0109

1

IC,LOW POWER CLOCK SYNTHESIZER,68PIN

CRITICAL

IC, BOOTROM, FINAL, LOCKED, M57

341S1925

1

CRITICAL

U6301

BOOTROM_FINAL

1

341S1924 CRITICAL

IC, BOOTROM, DEVELOPMENT, UNLOCKED ,M57

U6301

BOOTROM_DEVEL

SYNC_MASTER=(MASTER)

4

051-7164

SYNC_DATE=(MASTER)

87

06004

BOM CONFIGURATION

353S1461353S1465

Screened ISL6262 for ISL9504

ALL

152S0287 152S0435

ALL

Alternates for Coilcraft MSS5131

IC,SGRAM,GDDR3,8MX32,700MHZ,136 FBGA

U8900,U8950,U9000,U9050

VRAM_128_HYNIX

4

333S0358 CRITICAL

353S1461

U7530

1

CRITICAL

IC,ISL9504,SYNC REG CTL,QFN 48

1

IC,88E8053,GIGABIT ENET XCVR,64P QFN, NO

338S0270

U4101

CRITICAL

IC,SGRAM,GDDR3,8MX32,700MHZ,136 FBGA

U8900,U8950,U9000,U9050

VRAM_128_INFINEON

CRITICAL333S0376

4

333S0351

IC,SGRAM,GDDR3,16MX32,700MHZ,136 FBGA

U8900,U8950,U9000,U9050

VRAM_256_HYNIX

4

CRITICAL

376S0445

ALL

Si7806ADN for FDM6296

376S0448

128S0093

KEMET IS ALT TO SANYO

128S0092

ALL

128S0083

1.86 MAX ALT TO 1.9 MAX

128S0073

C2516

333S0377

IC,SGRAM,GDDR3,16MX32,600MHZ,136 FBGA

U8900,U8950,U9000,U9050

VRAM_256_INFINEON

CRITICAL

4

333S0350

U8900,U8950,U9000,U9050

IC,SGRAM,GDDR3,16MX32,700MHZ,136 FBGA

VRAM_256_SAMSUNG

CRITICAL

333S0354

U8900,U8950,U9000,U9050

4

CRITICAL

VRAM_128_SAMSUNG

IC,SGRAM,GDDR3,8MX32,700MHZ,136 FBGA

338S0368

IC,ATI,M56P,GRPHSCTRL,880BGA,LF

U8400

1

CRITICAL

ITP,LPCPLUS

M57_DEBUG

M57_COMMON4

BOOTROM_DEVEL,SMC_PRGRM

M57_COMMON3

LVDS_PD,FW_PORT_FAULT_PU

M57_COMMON2

KBDLED_HAS,MEMVREF_S3,MEMVTT_EN_PU,RTUSB_ESD,USB_C_OC_PU,USB_D_OC_PU,USB_E_OC_PU

ENET_LOWPWR_EN,ENETPWR_S3AC,GPU_BB_CTL,D3CPGOOD_3V3,ISL6255A,NO_3G

M57_COMMON1

ALTERNATE,COMMON,M57_COMMON1,M57_COMMON2,M57_COMMON3,M57_COMMON4,M57_DEBUG

M57_COMMON

[EEE:WJK]

LBL,P/N LABEL,PCB,28MM X 6 MM

826-4393

1

CRITICAL

EEE_WJK

M57_TPM

TPM

IC,PRGRM,SMC(NEW),M57

1

U5800

CRITICAL341S1931

SMC_PRGRM

IC,SMC,HS8/2116

1

338S0274

U5800

SMC_BLANK

CRITICAL

1

IC,EEPROM,SERIAL IIC,8KBIT,SO8

341S1797

U4102

CRITICAL

IC, TPM, 28-PIN TSSOP

TPM1

341S1789

U6700

CRITICAL

335S0384

IC,16MBIT 8-PIN SPI SERIAL FLASH,SOIC8

1

CRITICAL

BOOTROM_BLANK

U6301

TRUCKEE,2.33GHZ,B2,256VRAM,SAM,M57

VRAM_256SAM,M57_COMMON,CPU_2_33GHZ_B2,EEE_WJK

630-7814

337S3393

1

U0700

CRITICAL

CPU_2_33GHZ_B2

IC,MDC,B2,PRQ,2.33GHZ,34W,667M,4M,479 BGA

1

343S0385 CRITICAL

U2100

IC,ICH7M,BGA

1

338S0269 CRITICAL

U1200

IC,945GM,NORTHBRIDGE

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

FUNC_TEST

SMC TPs

Thermal Sensors

Left I/O Data Connector

FUNC_TEST

LPC+ Debug Connector

FUNC_TEST

(=PP2V5_S3_ENET)

(=PP3V3_S3_ENET)

(=PP1V2_S3_ENET)

FUNC_TEST

MAC-1 TPs

FUNC_TEST

Fan Connectors

FUNC_TEST

Battery Connector

Functional Test Points

FUNC_TEST

(=PP3V3_S0_CK410)

Power Nets

FUNC_TEST

Characterization TPs

Request for at least 10 GND TPs

Request for at least 10 GND test points

FUNC_TEST

Resistor Calibration

Left I/O Power Connector

FUNC_TEST

Request for at least 2 GND TPs per resistor

Camera Connector

Inverter Connector

Misc EXPOSED_VIA Nets

CPU FSB NO_TESTs

Misc NO_TESTs

EXPOSED_VIA

NO_TEST

EXPOSED_VIA

NO_TEST

EXPOSED_VIA

NO_TEST

Power Supply NO_TESTs

EXPOSED_VIA property indicates that the net should have a via with 10-mil soldermask opening for use as engineering probe point.

EXPOSED_VIA

I134

I135

I138

I139

I140

I141

I142

I143

I164

I165

I166

I167

I168

I169

I172

I173

I174

I175

I176

I177

I178

I179

I182

I183

I184

I185

I186

I187

I188

I189

I190

I191

I192

I193

I194

I195

I197

I198

I199

I200

I201

I202

I203

I204

I205

I206

I207

I208

I209

I210

I211

I212

I213

I214

I215

I216

I217

I218

I219

I220

I221

I222

I223

I224

I225

I227

I228

I229

I230

I231

I232

I233

I234

I235

I236

I237

I238

I239

I240

I241

I242

I243

I244

I245

I246

I247

I248

I249

I250

I251

I252

I253

I254

I255

I256

I257

I258

I259

I260

I261

I262

I263

I264

I267

I269

I273 I275

I276

I277

I278

I279

I280

I281 I282

I283

I285

I286

SYNC_DATE=(MASTER)

SYNC_MASTER=(MASTER)

051-7164 06004

875

Functional / ICT Test

TRUE

USB2_CAMERA_P_F

TRUE

USB2_CAMERA_N_F

TRUE

TP_FW_CTL<0>

TRUE

USB_BT_N

GPUBBP_ADJ

TRUE

P3V42G3H_FB

TRUE

P1V05S0_FSET

TRUE

P3V3S5_FSET

TRUE

P3V3S5_COMP

TRUE

P5VS5_RUNSS

IMVP6_RBIAS

TRUE

GPUVCORE_COMP

TRUE

P2V5S3_SHDNRT

TRUE

P1V2S3_RT P1V2S3_RUNSS

TRUE

P1V8S3_COMP

TRUE

P2V5S3_MODE

P1V05S0_COMP

TRUE

GPUVCORE_FSET

P1V8S3_FSET

TRUE

P1V5S0_RUNSS

TRUE

USB_BT_P

TRUE

SB_CLK100M_SATA_P

TRUE

SB_CLK100M_SATA_N

DMI_N2S_N<1..0>

TRUE

DMI_N2S_P<1..0>

TRUE

FSB_REQ_L<4..0>

FSB_LOCK_L

TRUE

FSB_HITM_L

FSB_HIT_L

TRUE

TRUE TRUE

FSB_DSTBP_L<3..0>

FSB_DSTBN_L<3..0>

TRUE TRUE

FSB_DRDY_L

TRUE

TRUE TRUE

FSB_DINV_L<3..0>

FSB_DBSY_L

TRUE

FSB_D_L<63..0>

TRUE

FSB_BNR_L

TRUE

FSB_BREQ0_L

TRUE

FSB_ADSTB_L<1..0>

TRUE

FSB_ADS_L

TRUE

FSB_A_L<31..3>

TRUE

PP5V_S0_ISENSECAL

TRUE

PPVCORE_D3C_GPU

TRUE

GND

PP5V_S3_CAMERA_F

TRUE

GND_CHASSIS_INVERTER

TRUE TRUE

PPBUS_S0_INVERTER PP5V_INVERTER_SW

TRUE

INVERTER_PWM

TRUE

GND_CHASSIS_INVERTER

TRUE

PPVCORE_S0_CPU

PP1V05_S0

TRUE

PP1V8_S3

TRUE

PP5V_S3

TRUE

USB2_CAMERA_N

TRUE

USB2_CAMERA_P

PM_SUS_STAT_L

TRUE

SMC_TDI

TRUE

SMC_TCK

TRUE

SMC_RST_L

TRUE TRUE

SMC_NMI

TRUE

SMC_RX_L

TRUE

SV_SET_UP

TRUE

ISENSE_CAL_EN

TRUE

PCIE_WAKE_L

TRUE

SMC_BC_ACOK

SMBUS_SMC_A_S3_SDA

TRUE

ACZ_SDATAIN<0> ACZ_SDATAOUT

TRUE

LT2USB_OC_L

TRUE

PM_SLP_S3_LS5V

TRUE

PM_SLP_S4_L

TRUE

SYS_ONEWIRE

TRUE

MINI_CLKREQ_L

TRUE

SMC_EXCARD_CP

TRUE TRUE

EXCARD_CLKREQ_L

LIO_PLT_RESET_L

TRUE

ACZ_SYNC

TRUE

USB2_LT_N

TRUE

USB2_LT_P

TRUE TRUE

USB2_EXCARD_N USB2_EXCARD_P

TRUE TRUE

PCIE_EXCARD_R2D_C_N

TRUE

PCIE_EXCARD_D2R_N

PCIE_CLK100M_EXCARD_P

TRUE

PCIE_CLK100M_EXCARD_N

TRUE

PCIE_MINI_R2D_C_N

TRUE

USB2_LT2_P

TRUE

ACZ_RST_L

TRUE

EXCARD_OC_L

TRUE

LTUSB_OC_L

TRUE

SMC_EXCARD_PWR_EN

TRUE

PM_DPRSLPVR

TRUE

GND

TRUE

IMVP_VR_ON

TRUE

PM_SLP_S3BATT

PM_SLP_S5_L

TRUE

P1V5P1V05S0_PGOOD

TRUE

FSB_CLK_CPU_P

TRUE

CPU_STPCLK_L

TRUE

FSB_CLK_NB_P

TRUE

PLT_RST_L

TRUE

PP1V8_S3

TRUE

PP1V8_D3C

TRUE

PP3V3_S5

TRUE

PP5V_S0

TRUE

PP5V_S3

TRUE

PP5V_S5

TRUE

PPBUS_G3H

TRUE

PP3V3_S3

PP1V05_S0

TRUE

PP1V2_S3

TRUE

PP1V5_S0_NB

TRUE

PP1V5_S0

TRUE

PP1V2_D3C

TRUE

PP0V9_S0

TRUE

FSB_SLPCPU_L

PP2V5_S0

TRUE

FAN_LT_PWM FAN_LT_TACH

TRUE

FAN_RT_PWM

TRUE

PM_CLKRUN_L

TRUE

SMC_TMS

TRUE

DEBUG_RST_L

TRUE

SMC_TRST_L

TRUE

SMC_TDO SMC_MD1

TRUE TRUE

SMC_TX_L

PCI_CLK_PORT80_LPC

TRUE

PP3V3_FWPHY

TRUE

PP3V3_FWPHY_AVDD

TRUE TRUE

PP3V3_FWPHY_PLLVDD PP1V95_FWPHY

TRUE

PP1V95_FWPHY_PLLVDD

TRUE

PP1V2_S3

TRUE

PP3V3_S3AC

TRUE

BATT_POS

TRUE

SMBUS_SMC_BSA_SCL

PP5V_S0

TRUE

SMC_BS_ALRT_L

TRUE

SMBUS_SMC_BSA_SDA

PP2V5_D3C

TRUE

PP3V3_S0

TRUE

INT_SERIRQ

TRUE

FWH_INIT_L

TRUE

LPC_AD<3>

TRUE

LPC_AD<2>

IMVP_DPRSLPVR

TRUE

PM_SLP_S4_L

TRUE

CPU_DPRSTP_L

TRUE

FSB_CLK_CPU_N

TRUE

TPM_LRESET_L

FSB_CLK_NB_N

TRUE TRUE

CLK_NB_OE_L

TRUE

NB_CLK100M_GCLKIN_P

TRUE

NB_CLK100M_GCLKIN_N

TRUE

NB_CLK_DREFCLKIN_P

TRUE

NB_CLK_DREFCLKIN_N

TRUE

NB_CLK_DREFSSCLKIN_N

TRUE

NB_CLK_DREFSSCLKIN_P

TRUE

CPU_THERMTRIP_R

TRUE

TP_SB_SUS_CLK

TRUE

TP_CPU_CPUSLP_L

TRUE

CPU_DPSLP_L

TRUE

PM_LAN_ENABLE

TRUE

PCI_RST_L

TRUE

PM_SB_PWROK

TRUE

PM_RSMRST_L

TRUE

SB_RTC_RST_L

TRUE

PM_STPCPU_L

TRUE

PM_STPPCI_L

TRUE

VR_PWRGD_CK410

TRUE

VR_PWRGOOD_DELAY

TRUE

FSB_CPURST_L

TRUE

FSB_DPWR_L

TRUE

NB_SB_SYNC_L

TRUE

CPU_PWRGD

TRUE

PP2V5_S0_GPU_TPVDD

TRUE

PP2V5_S0_GPU_TXVDDR

TRUE

PP2V5_S0_GPU_AVDD

TRUE

PP2V5_S0_GPU_A2VDD

TRUE

PP2V5_S0_GPU_LPVDD

TRUE

PP2V5_S0_GPU_LVDDR PP3V3_S0

TRUE

PP3V3_S0_CK410_VDD_REF

TRUE

PP3V3_S0_CK410_VDD48

TRUE

PP3V3_S0_CK410_VDD_PCI

TRUE

PP3V3_S0_CK410_VDD_CPU_SRC

PM_SLP_S3_L

TRUE

PP3V3_S0_CK410_VDDA

PP2V5_S3_ENET_AVDD

TRUE

PP2V5_S3

TRUE

PEG_RESET_L

TRUE

PLT_RST_L

TRUE

IMVP6_VID<6..0>

SMC_LRESET_L

TRUE

GND

TRUE

BATT_NEG

FAN_RT_TACH

TRUE

ALS_GAIN

PCIE_EXCARD_D2R_P

TRUE

USB2_LT2_N

PCIE_MINI_D2R_P

TRUE

PP18V5_DCIN

TRUE

PPBUS_G3H

TRUE

PP1V5_S0

RSFSTHMSNS_D_P

TRUE

HSTHMSNS_DX_P

TRUE

HSTHMSNS_DX_N

RSFSTHMSNS_D_N

TRUE

SMC_ONOFF_L

TRUE

PM_SYSRST_L

PP5V_S0

TRUE

PP3V42_G3H

TRUE

LPC_AD<0>

TRUE

LPC_AD<1>

TRUE

LPC_FRAME_L

TRUE

BOOT_LPC_SPI_L

TRUE

SMBUS_SMC_A_S3_SCL

SMBUS_SB_SDA

TRUE

SMBUS_SB_SCL

TRUE

PCIE_EXCARD_R2D_C_P

TRUE

LTALS_OUT

ACZ_BITCLK

TRUE

PCIE_MINI_R2D_C_P

TRUE

PCIE_CLK100M_MINI_P

TRUE

PCIE_CLK100M_MINI_N

TRUE

PCIE_MINI_D2R_N

TRUE

82D5 82C6 82B3 82A4

79D3 79A8 71D2 67C5 67C3 67B3 67A3 66B6

66B5 66B1 65D6 65B3 62A6

61D8 61A5 60D4 60C7 58C7 58C4 57B6 54D4

54B5 52D3 49C7 49C4 49B5

40B6 36D6 34A8 33D8 33D3 33C7

29A6 29A3

67D8

28A6

67D6

27D8

65A2

27D5

55A4

27D3

34C8

27C3

34C6

26D1

34B8

26B8

25D3

26B6

25C4

79D5

25C4

26B4

24D3

67D5

24D3

25D8

24C3

67D3

24C3

25D3

21C1

67C3

21C1

25C6

19D7

66C5

19D7

25C4

81D4

19D6

65D8

19D6

81B3

25B8

81B3

69C8

19D5

65D2

19D5

67C8

80B5

25B4

80B5

69B8

19D2

65D1

19D2

67C6

80A1

25A4

67C8

80A1

69A8

19D1

65C8

79B7

19D1

67B6

79B8

24D3

79B7

67C6

79B8

68B8

19C8

67B8

63D8

71D7

19C8

62A7

71A6

24C3

71D7

66C5

71A6

67D5

17D6

67B6

56D4

71D7

69C1

17D6

19D7

67B3

24B5

69C1

62C1

67B3

67D3

17D3

64C1

26C5

67C3

68D5

17D3

19D6

67B1

24B3

68D5

62A8

67B1

66D2

16D3

64A6

25D2

67C1

67C3

16D3

19D5

82D3

67A1

23D5

67C3

48B6

67A1

66C8

16C8

37B2

82D7

25C8

67B1

67C1

16C8

19D2

82C5

66B5

23B3

67C1

25D6

66B5

66A8

13B5

32C6

76D8

25B6

66D8

65D6

13B5

19D1

67B6

62B1

22B5

65D6

25C8

62B1

53C4

81C3

12C2

66B8

82A4

31C5

76D5

24C3

66B8

65B7

12C2

19C5

67A8

61D7

66B8

21D3

66C8

82A4

65B7

25C6

61D7

52D7

48B3

12B7

66A6

79A8

29D6

75D8

24B3

65D6

64D7

12B7

19C4

67A6

58C7

66A6

21C3

66C6

79A8

64D7

25C2

58C7

52B7

46B6

12A7

64C8

26C3

29D3

75D5

24A5

65B7

64A6

12A7

19C1

66B5

44B8

67D3

58C4

64C8

20B4

66B6

26C3

64A6

25B6

58C4

52B5

33B6

87D6

77A7

67D3

11C5

81C6

51C5

26C1

29B2

73B8

23D8

81C6

64C8

62D7

11C5

19B8

63D1

44A8

67D1

57B5

51C5

20A4

65B8

26C1

62D7

25B2

57B5

52B1

29A6

12D6

72D8

79A6

67D1

11B3

81C4

81C3

48C3

26B1

28D6

73B5

23D4

81C4

62C8

61D7

11B3

19B5

19D7

43B8

41C4

55A8

82D7

48C3

19C7

55C3

26B1

61D7

25A8

55A8

51D4

28A6

87D6

12C6

71C1

79A5

61D1

9B7

67B3

51B5

66C7

47C7

52B3

26A4

28D3

73A8

23D1

67B3

62B6

61D4

9B7

67D8

19A5

19C5

42C4

42C1

67D8

39D8

53C4

78C8

47C7

19C6

51C5

67B8

26A4

61D4

24B5

53C4

51D3

81C3

27D8

81A4

12B4

12B6

87D6

71B7

45C5

55D7

8C7

67B1

45C3

45B3

60C6

53B5

69A6

48B6

48C3

66C6

41B6

48C6

50B6

48C6

48C3

66B5

22A6

28B2

73A5

23B7

67B1

62B2

55D3

8C7

67D6

17C6

19A8

53B4

38D7

38D5

67D6

39D6

68B2

36D6

68B2

77C6

53C5

41B6

17C6

43C8

67B6

22A6

50C6

48C6

50C6

55D3

24A5

36D6

51C2

51B5

27D7

50C6

22C2

34C5

87D6

7C4

87C6

12D4

67A8

45B5

55A6

7D5

62A2

22C2

53B5

52B3

68A6

27C6

22D8

62B3

23C3

48C3

22C2

50B5

48B6

22C2

22D8

87C6

66B3

34D5

14B7

19D7

72B8

23A7

62A2

62A4

43D8

7D5

63B3

17B6

19A6

60C6

52B3

38B5

38B2

63B3

39B8

51B5

31C5

51B5

77A8

60C6

52D5

60C6

60C6 23C3

34D5

34C5

34B5

87D6

14D6

42A8

63D4

14B7

50C5

22C2

50C5

43D8

24A3

81C4

31C5

47B5

60C6

48B6

27D6

48C6

50C5

6C3

34C3

12B4

87D6

7C3

87D6

7C3

87D6

7C3

87D6

12C4

87D6

12C4

67A6

6A8

9D7

7B6

52B8

6D3

52A2

53B5

52B2

53B5

48C3

52A2

27C5

87B4

22C4

48C3

6A2

52B2

34A4

52A2

34A4

87B4

6D3

6C3

50C6

50B3

34C5

34B5

50C6

6C3

87B4

22C4

61C8

52A2

66B2

34D3

87C6

34D3

6C7

16B6

67B8

22D8

52B8

52B5

42B8

7B6

39D7

16D1

19A4

53C4

53B4

52B2

6C6

39D7

39B5

69B1

27C3

25D8

68B2

27C3

67A8

53C5

52D3

53C5

6A2

61C7

34D3

34C4

34B4

23C3

87C6

61C7

12C4

87D6

87C6

14C7

39C8

63D3

6C7

51B5

50C3

6C3

50C3

42B8

9B7

52C6

51B7

25D8

35B7

53C4

53B4

27C6

50C6

87B4

50C6

34D5

50C3

6C2

66A6

63B7

66C6

6C2

33B4

22D2

12A4

12B4

7B4

12B4

7B4

12B4

7B4

12C4

7D8

12C4

7D8

55C7

6A6

8D7

7B5

45C3

6D2

51C5

52B2

52D6

53B5

51C7

23C3

55A8

39C6

51C5

27C3

48B3

6C3

6A2

6A1

51B7

34A3

51B7

34A3

48C3

48B3

6D2

6C2

50C5

48B6

34C3

34B3

50C5

6C2

48B3

6C3

6D3

51B7

23C3

61C7

51C5

65B8

33C4

21C4

33C4

6C6

14C2

67B6

22C6

45C3

47C7

41C6

7B5

39A8

13D2

12A4

17D6

51C5

52B2

53B4

52B2

53B4

51C7

53C5

6C5

39A8

39B4

68A2

27C2

5D4

52B2

27C2

67A6

51C7

51D5

51C7

87C6

6A1

21C4

33C4

60B7

33C4

33B4

34B2

33B4

6C7

21C4

51D7

37C2

26A6

51D7

26D4

33C4

26B8

26B5

11B5

12B4

22A6

21C4

10C5

32B3

40D5

63C3

70A5

6C6

61C7

51C7

68B2

48C4

48B6

6C2

48C6

68C5

41C6

8B7

52B2

26C5

5D4

27C3

51D7

51C7

27C5

27B6

50C5

57C7

48B3

50C5

34D4

48C6

45B5

37C3

6C1

71B7

66C3

65B7

65D6

65C6

62C5

61C7

71C7

63B6

41C4

65A7

71C7

62C4

6C1

21B6

14B4

7D8

7D6

7B3

7D6

7B3

7D6

7B3

7D6

7C8

7D6

7C8

55A5

45C5

5B2

79B5

79A5

5B2

8B5

5D4

6D1

23C5

51B5

51C5

51C3

51C1

47B5

23B6

51B7

23C8

48C3

27B3

21C7

6C1

6A1

5C4

48C3

33B4

48C3

33B4

26C1

21C7

6D1

6C1

48B6

22D4

33B4

48C6

6C1

21C7

6C1

6D1

48C3

14B7

51D7

41B5

23C3

61C7

7C6

7C8

12A6

5C4

5B2

64A4

11B5

5B2

25C8

5A1

5B2

5A4

13C5

7A3

17C6

58B6

58B3

23C8

51B5

26B1

51C1

51B5

51C1

47B5

34D6

6C3

38D5

38C6

6C3

38D3

5D4

39A5

68A1

27C1

5D2

51C5

27C1

63C1

23C8

21C4

21D4

61C7

5C1

7B3

7C6

26B1

12A6

14B6

14C4

14B4

21C2

6C6

21C4

7B3

23C3

22A6

23C3

23C1

21D6

23C8

23C5

14B6

7D6

7B3

14B6

7B3

78C7

78B7

5D4

33C5

23C3

39D5

39D3

26B1

5C4

9C1

26B1

68B1

58B3

6D5

22D4

6C1

22D4

68B8

5C4

5D4

54D5

54C5

51C5

23C5

5D2

26D6

21D4

21C5

22B3

27C3

23D5

48B6

48C3

21C7

48C6

33B4

22D4

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

Chassis connection to be made at the fan cutout near the right ALS. Not stuffed at Proto.

Chassis connection to be made on FW shell

Chassis connection to be made at the mounting hole east of the LVDS connector

Chassis connection to be made at the mounting hole southwest of the USB connector. Plated hole.

USB Port "G" = Bluetooth (M13P)

USB Port "H" = 2nd Left USB 2.0 Port

LVDS Pull Down Aliases

LEFT CLUTCH BARREL CABLING

Inverter PWM Reset Alias

NOTE: NB_CFG<13..12> require test access

FireWire Aliases

Add one through via per hole to GND or 2 blind vias per side per hole to GND

Top CPU TM Hole

Top GPU Right TM Hole

Right CPU TM Hole

NOTE: BOM options "USB_G_OC_PU" and "ENET_LOWPWR_EN" are mutually-exclusive.

USB Port "E" = ExpressCard

USB Port "F" = USB 1.1 Hub

USB Port "D" = Camera

USB Port "B" = Trackpad (Geyser)

USB Port "A" (Debug Port) = Right USB 2.0 Port

USB Port "C" = Left USB 2.0 Port

Ethernet Powr Management Support

Lower Left GPU TM Hole

Thermal Module Holes

Frame holes

Left CPU TM Hole

Base net is PM_SLP_S4_L

Base net is PM_SLP_S3_LS5V

Chassis connection to be made at the mounting hole northwest of the DVI connector. Plated hole.

195R106

ZT0600

HOLE-VIA-P5RP25

ZT0603

1

HOLE-VIA-P5RP25

ZT0602

1

0

5% 1/16W MF-LF

402

R0600

1 2

402

5%

1/16W

0

MF-LF

ENET_LOWPWR_EN

R0690

1 2

5%

1/16W

0

402

MF-LF

NO STUFF

R0601

1 2

0G-502620R

EMI-SPRING

NO STUFF

SH0601

1

402

X7R

50V

10%

0.01UF

C0613

1

2

402

X7R

50V

10%

0.01UF

C0619

1

2

10% 50V X7R 402

0.01UF

C0615

1

2

HOLE-VIA-P5RP25

ZT0612

1

HOLE-VIA-P5RP25

ZT0611

1

HOLE-VIA-P5RP25

ZT0610

1

50V

10%

0.01UF

X7R 402

C0600

1

2

50V

0.01UF

10% X7R

402

C0602

1

2

195R106

ZT0601

402

X7R

50V

10%

0.01UF

C0612

1

2

10% 50V X7R 402

0.01UF

C0614

1

2

0.01UF

10% 50V X7R 402

C0616

1

2

0.01UF

10% 50V X7R 402

C0611

1

2

0.01UF

10% 50V X7R 402

C0610

1

2

HOLE-VIA-P5RP25

ZT0613

1

0.01UF

10% 50V X7R 402

C0618

1

2

0.01UF

10% 50V X7R 402

C0617

1

2

HOLE-VIA-P5RP25

ZT0614

1

SHLD-SM-LF

OG-503040

SH0600

1

2

3

HOLE-VIA-P5RP25

ZT0604

1

MF-LF

402

0

1/16W

5%

NO STUFF

R0602

1 2

Signal Aliases

SYNC_DATE=(MASTER)

SYNC_MASTER=(MASTER)

051-7164 06004

876

VOLTAGE=0V

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

GND_CHASSIS_FANFRAME

VOLTAGE=0V

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

GND_CHASSIS_DVI_TOP

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

MAKE_BASE=TRUE

VOLTAGE=0V

GND_CHASSIS_DVI_BOT

NC_CPU_A34_L

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_CPU_A36_L

MAKE_BASE=TRUE NO_TEST=TRUE

NC_CPU_A37_L

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_CPU_APM1_L

NO_TEST=TRUE

MAKE_BASE=TRUE

USB_HUB_P

USB_HUB_N

LT2USB_OC_L

USB2_LT2_N

=LVDS_PD_U_CLK_N

=LVDS_PD_U_CLK_P

LVDS_U_DATA_N<0>

=LVDS_PD_U_DATA_N<1>

LVDS_U_CLK_N

MIN_NECK_WIDTH=0.25 mm VOLTAGE=0V

MIN_LINE_WIDTH=0.5 mm

GND_CHASSIS_LNDACARD_HOLE

GND_CHASSIS_LEFT_DIMM_HOLE

MIN_NECK_WIDTH=0.25 mm VOLTAGE=0V

MIN_LINE_WIDTH=0.5 mm

GND_CHASSIS_ODD_HOLE

MIN_NECK_WIDTH=0.25 mm VOLTAGE=0V

MIN_LINE_WIDTH=0.5 mm

GND_CHASSIS_BATTCONN_HOLE

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=0V MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.5 mm

VOLTAGE=0V

GND_CHASSIS_LIOFLEX_HOLE

MIN_NECK_WIDTH=0.25 mm

GND_CHASSIS_BATTCONN_HOLE

PCI_GNT3_L

MAKE_BASE=TRUE

PCI_REQ3_L

LVDS_L_DATA_N<1>

MAKE_BASE=TRUE

NC_CPU_A33_L

MAKE_BASE=TRUE NO_TEST=TRUE

USB_BT_N

USB2_LT2_P

USB2_LT2_N

MAKE_BASE=TRUE

LT2USB_OC_L

MIN_NECK_WIDTH=0.20 mm

PP3V3_FWPHY

MIN_LINE_WIDTH=0.38 mm MAKE_BASE=TRUE

VOLTAGE=3.3V

VOLTAGE=1.95V MIN_LINE_WIDTH=0.38 mm

MAKE_BASE=TRUE

PP1V95_FWPHY

MIN_NECK_WIDTH=0.25 mm

NC_CPU_SPARE4

MAKE_BASE=TRUE NO_TEST=TRUE

MAKE_BASE=TRUE

PPFW_PORTB_VP_UF

PP1V95_FWPHY

SMC_RSTGATE_L

=FW_PCI_IDSEL

PCI_GNT3_L

PCI_REQ3_L

NC_CPU_EXTBREF

NB_CFG<6>

NB_CFG<4..3>

ALS_GAIN

NC_CPU_APM0_L

MAKE_BASE=TRUE NO_TEST=TRUE

NC_CPU_A39_L

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_CPU_A38_L

NC_CPU_A35_L

NC_CPU_A34_L

PP3V3_FWPHY

MAKE_BASE=TRUE

SMC_RSTGATE_L

PP1V95_FWPHY

PP3V3_FWPHY

PPFW_PORTB_VP_UF

ENET_LOWPWR_EN

MAKE_BASE=TRUE NO_TEST=TRUE

NC_ENET_CTRL12 NC_ENET_CTRL12

MAKE_BASE=TRUE NO_TEST=TRUE

NC_ENET_CTRL25

RTALS_GAIN

MAKE_BASE=TRUE

RTALS_GAIN

NC_CPU_SPARE0NC_CPU_SPARE0

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_CPU_HFPLL

MAKE_BASE=TRUE NO_TEST=TRUE

NC_CPU_SPARE2

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_CPU_SPARE2

NC_CPU_SPARE1

NC_CPU_EXTBREF

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_CPU_A38_L

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_CPU_SPARE1

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_CPU_SPARE4

MEM_B_A<15..14>

NB_CFG<15..14>

NB_CFG<8>

MEM_A_A<15..14>

NC_CPU_A32_L

MAKE_BASE=TRUE NO_TEST=TRUE

PP1V95_FWPHY

NB_CFG<13..12>

MAKE_BASE=TRUE

PCI_AD<19>

NB_CFG<17>

NC_CPU_HFPLL

NC_CPU_A32_L

MAKE_BASE=TRUE NO_TEST=TRUE

NC_MEM_B_A<15..14>

MAKE_BASE=TRUE

TP_NB_CFG<4..3>

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_MEM_A_A<15..14>

SB_GPIO30

USB2_RT_PUSB2_RT_P

MAKE_BASE=TRUE

USB2_RT_P

USB2_RT_N

RTUSB_OC_L

USB_TRACKPAD_N

USB_TRACKPAD_P

UNUSED_USB_B_OC_L

MAKE_BASE=TRUE

UNUSED_USB_B_OC_L

USB2_LT_P

USB2_LT_N

LTUSB_OC_L

MAKE_BASE=TRUE

LTUSB_OC_L

USB2_CAMERA_P

MAKE_BASE=TRUE

USB2_RT_NUSB2_RT_N

RTUSB_OC_L

MAKE_BASE=TRUE

RTUSB_OC_L

MAKE_BASE=TRUE

USB_TRACKPAD_PUSB_TRACKPAD_P

MAKE_BASE=TRUE

USB_TRACKPAD_NUSB_TRACKPAD_N

USB2_LT_P

MAKE_BASE=TRUE

USB2_LT_P

MAKE_BASE=TRUE

USB2_LT_NUSB2_LT_N

USB2_CAMERA_P

MAKE_BASE=TRUE

USB2_CAMERA_P

UNUSED_USB_D_OC_LUNUSED_USB_D_OC_L

MAKE_BASE=TRUE

USB2_CAMERA_N

USB2_EXCARD_N

USB2_EXCARD_P

EXCARD_OC_LEXCARD_OC_L

MAKE_BASE=TRUE

USB_BT_P

USB_BT_N

USB2_CAMERA_N

MAKE_BASE=TRUE

USB2_CAMERA_N

MAKE_BASE=TRUE

USB2_EXCARD_PUSB2_EXCARD_P

MAKE_BASE=TRUE

USB2_EXCARD_N

USB_BT_P

USB_BT_N

MAKE_BASE=TRUE

USB2_LT2_P

MAKE_BASE=TRUE

USB2_LT2_P

LVDS_L_DATA_P<1>

MAKE_BASE=TRUE

=LVDS_PD_L_CLK_N

=LVDS_PD_L_CLK_P

MAKE_BASE=TRUE

LVDS_L_DATA_P<0>LVDS_L_DATA_P<0>

LVDS_L_DATA_N<0>

MAKE_BASE=TRUE

LVDS_L_DATA_N<0>

MAKE_BASE=TRUE

LVDS_L_CLK_NLVDS_L_CLK_N

MAKE_BASE=TRUE

LVDS_L_CLK_PLVDS_L_CLK_P

LVDS_L_DATA_N<2>

MAKE_BASE=TRUE

=LVDS_PD_L_DATA_P<2>

LVDS_L_DATA_P<2>

MAKE_BASE=TRUE

=LVDS_PD_L_DATA_N<2>

MAKE_BASE=TRUE

LVDS_U_DATA_N<1>

MAKE_BASE=TRUE

LVDS_U_DATA_P<1>

MAKE_BASE=TRUE

LVDS_U_DATA_N<0>

LVDS_U_DATA_P<0>

MAKE_BASE=TRUE

LVDS_U_DATA_P<0>

MAKE_BASE=TRUE

LVDS_U_DATA_P<2>

=LVDS_PD_U_DATA_P<1>

LVDS_U_DATA_N<2>

MAKE_BASE=TRUE

LVDS_U_CLK_N

LVDS_U_CLK_P

MAKE_BASE=TRUE

LVDS_U_CLK_P

PM_SLP_S4_LPM_SLP_S4_L

PM_SLP_S3_LS5VPM_SLP_S3_LS5V

USB_HUB_P USB_HUB_P

MAKE_BASE=TRUE

TP_USB2_3G_N

USB_HUB_N

USB2_EXCARD_N

TP_USB2_3G_P

NC_ENET_CTRL25

PPFW_PORTA_VP_UF

MAKE_BASE=TRUE

PPFW_PORTA_VP_UF

NC_CPU_A36_L

NC_CPU_A33_L

GND_CHASSIS_INVERTER

NC_CPU_A39_L

TP_SB_SUS_CLK

MAKE_BASE=TRUE

TP_NB_CFG<13..12>

NB_CFG<11..10>

MAKE_BASE=TRUE

TP_SB_SUS_CLK

MAKE_BASE=TRUE

TP_NB_CFG<17>

MAKE_BASE=TRUE

TP_NB_CFG<15..14>

MAKE_BASE=TRUE

TP_NB_CFG<11..10>

MAKE_BASE=TRUE

TP_NB_CFG<8>

MAKE_BASE=TRUE

TP_NB_CFG<6>

PLT_RST_LPLT_RST_L

NC_CPU_APM1_L

NC_CPU_APM0_L

NC_CPU_A35_L

NO_TEST=TRUE

MAKE_BASE=TRUE

TP_USB2_3G_N

MAKE_BASE=TRUE

TP_USB2_3G_P

MAKE_BASE=TRUE

USB2_LT2_N

MAKE_BASE=TRUE

USB_BT_P

USB_HUB_N

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.5 mm

MAKE_BASE=TRUE

VOLTAGE=0V

MIN_NECK_WIDTH=0.25 mm

GND_CHASSIS_INVERTER

GND_CHASSIS_INVERTER GND_CHASSIS_INVERTER

NC_CPU_A37_L

GND_CHASSIS_INVERTER

GND

MIN_LINE_WIDTH=0.5 mm

GND_CHASSIS_USB

MAKE_BASE=TRUE

VOLTAGE=0V

MIN_NECK_WIDTH=0.25 mm

MAKE_BASE=TRUE

GND_CHASSIS_LVDS

MIN_NECK_WIDTH=0.25 mm VOLTAGE=0V

MIN_LINE_WIDTH=0.5 mm

GND_CHASSIS_USB GND_CHASSIS_USB GND_CHASSIS_USB

GND_CHASSIS_LVDS GND_CHASSIS_LVDS

GND_CHASSIS_LVDS

GND_CHASSIS_ENET GND_CHASSIS_ENET GND_CHASSIS_ENET

GND_CHASSIS_DVI_BOT GND_CHASSIS_DVI_BOT

GND_CHASSIS_DVI_TOP

GND_CHASSIS_ENET

VOLTAGE=0V MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm

66B8 66B8

44B8

66A6

82A4 82A4

44A8

44B8

44A8

64C8

79A8 79A8

43B8

44A8

43B8

51C5

26C3 26C3

42C4

42C1

43B8

42C1

42C4

48C3 48C3

79A6

26C1 26C1

79A6

38D7

38D5

42C4

38D5

38D7

42C1

47C5

48C6

45B3

52B3

45C3

48C6

81A4

48C6

47C7 47C7

66C7

46B7

79A5

26B1 26B1

48C6

81A4

46B3

79A6

79A5

79D3

46B7

46B3

48C3

48C6

82C8

82C3

81A4

48C6

48C3

38B5

38B2

38D7

38B2

38B5

38D5

47B5

47C5

48C6

48C3

45B3

47B5

22D8

47C5

81C4

22C2

48C6

22C2

48C6

22C2

45B3

45C3

48C6

48C3

81A4

22C2

45C3

22C2

48C6

22C2

81A4

22C2

48C6

22C2

82D8 82D8

82C8 82C8

82C8

82C8 82C8

82C3

82C3 82C3

41B6 41B6

66C6 66C6

46B3

48C6

45C5

26A4 26A4

22C2

46A7

79A5

45C5

79D3

47B2

79D2

44C1

80B5

46B3

46A7

22D8

22C2

82C3

82B8

37D3

22C2

22D8

6C6

37D3

38B5

6C6

38B2

47B5

22C2

47B5

22D8

81C4

22C2

22D8 22D8

22C2

47B5

22C4

22D8

22C2

81C4

22C2

81C4

6D3

22C2

6D3

22C2

6D3

22C2

22D8 22D8

22C2

6D3

22C2

6C3

22C2

6C3

22C2

6C3

22C2

6C3

82C3 82C3

82C3

82C3 82C3

82B8

82B8 82B8

23C3 23C3

62B3 62B3

22C2

45B5

22A6 22A6

6C3

22C2

45C5

45B5

47B2

79D2

44A3

79C3

44A1

80B5

80A5

44C1

80A5

80A2

22C2

22C4

6C3

79D7

37D3

26D2

82C3

6C2

22C4

6C3

44B3

6C5

51D7

37D3

26D2

51B5

6C5

51D7

6C5

44B3

6C5

22C2

6D3

22C2

22C4

22C2

22D8 22D8

6D3

22C4 22C4

6D3

22C2

6D3

22C4

6D3

22C2

6D3

22C2

6D1

6D2

6D1

6D2

6D1

6D2

22D8 22D8

6D3

6C3

22C4 22C4

6C3

6D1

6D2

6C1

6C2

6C1

6C2

6C1

6C3

6C1

82C3

79D7 79D7

82C3

79D7

79D7 79D7

82B3

82C3

79D7

79D7 79D7

6A2 6A1

48C3 48C3

6C3

6C2

44D3

6A8

23C3 23C3

14B7 14B7

6C1

6C3

45B5

6A8

44A3

79C3

44A1

79B2

40B2

80A2

80A3

44A1

80A3

6B6

7B8

6C3

6C2

78B3

69A1 69A1

22B6

79D7

7B8

6C1

5A4

7B6

43A2

6C3

37A8

22B6

7B6

48C4

7B8

6C3

37A8

6C3

43A2

39C8 39C8

39C8

57C4

7B6

7B8

7B6

7B8

7B6

7C8

6C3

37C6

7B8

7C8

22D8

6D3

6D1

6D2

6D3

22C4 22C4

6D2

6D3 6D1

6D2

6D1

6D2

6D1

6D2

6D1

6D2

6D1

6D2

5C1

6D1

5C1

6D1

5B2

6D1

22C4 22C4

6D2

6C2

6C3 6C1

6C2

5B2

6D1

5C1

6C1

5C1

6C1

5A7

6C2

5B1

79D7

78A3 78A3

79D7

78B3

78B3 78B3

79D7

78B3

78B3 78B3

5C4 5C4

6A2 6A1

6C1

46C3

6C1

46C3

39C8

43B2

7B8

6A6

7B8

6C7 6C6

7B8

46C3

5B1

5A7

6C1

6A6

7B8

6A6

44A1

79B2

6A8

6B8

40B2

6B6

6A6

6D7

6C7

6C2

5C1

5B1

82B8

6B1

82B8

6A1

6A4 6A6

6B3

78A3

6D7

5A7

5B1

5C1

6C7

6C3

5A4

6C5

37B7

6B5

6C8

14C6

5C1

6D7

6D8

5A4

6C3

5A4

6C5

39B8

6D4 6D5

6D4

6C8 6C7

6C7

6C7 6C8

6C8

6C7

6D7

6C7

6C8

14C6

6D7

5A4

14C6

22A7

14C6

6C8

6D8

29C3

28C3

22C4

6D2 6D1

6D2

6D3 6D1

5C1

5C1 5C1

5B2

6D1

5C1

5B2

6C3 6C1

5B2

5C1

5C1 5C1

5A7

5B2

5C1

5A7

5B1

78A3 82C8

82C8

6B2 6B1

78A3 82C8

78B3

6B2

6B2 6B1

78B3 82B8

78B3

6A2

6A2 6A1

5C1 5C1

6B2

5C1

6B2

6D5

6C5

6C3

6D8

5B2

6D8

5B4

14C6

5B4

14C6

5C4 5C4

6C8

6D8

6D7

6B3

5B2

6D8

5B2

6A6

6B6

6A6

IO IO

IO

IO IO

IO

IO IO

IO

IO IO

IO

IO IO

IO

IO IO

IO

IO IO

IO

IO IO

IO

IO IO

IO

IO IO

IN

IN IN

IN

IO IO

IO

IO IO

IO

IO IO

IO

IO IO

IO

IO IO

IO

IO IO

IO

IO IO

IO

IO IO

IO

IO IO

IO

IO IO

OUT

IO IO

IO

IO IO

IO

IO IO

IO

IO IO

IO

IO IO

IO

IO IO

IO

IO IO

IO

IO IO

IO

IO IO

IO

IO IO

IO

IO IO

IO

IO IO

IO

IO IO

IO

OUT

IN

IN IN

IN

IN IN

OUT

IN IN

IN

IN IN

IN

OUT

A7*

RSVD14 RSVD15

BCLK1

BCLK0

RSVD20

RSVD17 RSVD18 RSVD19

RSVD16

RSVD13

RSVD12

THERMTRIP*

THERMDC

THERMDA

PROCHOT*

DBR*

TRST*

TMS

TDO

TDI

TCK

PREQ*

PRDY*

BPM3*

BPM1* BPM2*

BPM0*

HITM*

HIT*

TRDY*

RS2*

RS1*

RS0*

RESET*

LOCK*

INIT*

IERR*

BR0*

DBSY*

DRDY*

DEFER*

BPRI*

BNR*

ADS*

RSVD11

RSVD6 RSVD7 RSVD8

RSVD1 RSVD2 RSVD3 RSVD4 RSVD5

RSVD9 RSVD10

SMI*

LINT0 LINT1

STPCLK*

IGNNE*

FERR*

A20M*

ADSTB1*

A30* A31*

A27* A28* A29*

A26*

A25*

A24*

A22* A23*

A21*

A20*

A19*

A18*

A17*

REQ4*

REQ3*

REQ1*

REQ0*

REQ2*

ADSTB0*

A14* A15* A16*

A13*

A12*

A11*

A10*

A9*

A8*

A6*

A5*

A4*

A3*

(1 OF 4)

THERM

HCLK

RESERVED

ADDR GROUP1 ADDR GROUP0

CONTROL

XDP/ITP SIGNALS

PSI*

SLP*

PWRGOOD

DPRSTP*

DPSLP*

DPWR*

COMP2 COMP3

COMP1

COMP0

DSTBP3*

DSTBN3*

DINV3*

D63*

D62*

D61*

D60*

D59*

D58*

D57*

D56*

D55*

D54*

D52* D53*

D51*

D50*

D49*

D48*

DINV2*

DSTBN2*

D47*

DSTBP2*

D45* D46*

D44*

D43*

D42*

D41*

D40*

D39*

D38*

D37*

D36*

D35*

D34*

D33*

D32*

BSEL2

DSTBN1*

BSEL0 BSEL1

TEST2

TEST1

DINV1*

DSTBP1*

D31*

D30*

D29*

D26* D27* D28*

D24* D25*

D23*

D21* D22*

D20*

D19*

D18*

D16* D17*

DINV0*

DSTBP0*

DSTBN0*

D15*

D14*

D13*

D12*

D11*

D10*

D9*

D8*

D7*

D6*

D5*

D4*

D3*

D2*

D1*

D0*

GTLREF NC

(2 OF 4)

MISC

DATA GRP0

DATA GRP2

DATA GRP1

DATA GRP3

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

0.1" AWAY

ROUTE TO TP VIA AND

SPARE[7-0],HFPLL:

STUB)

PM_THRMTRIP# SHOULD CONNECT TO

CPU_PROCHOT_L TO SMC

COMP1,3 CONNECT WITH ZO=55OHM, MAKE

LAYOUT NOTE: COMP0,2 CONNECT WITH ZO=27.4OHM, MAKE TRACE LENGTH SHORTER THAN 0.5".

TRACE LENGTH SHORTER THAN 0.5".

ICH7-M AND GMCH

LAYOUT NOTE: 0.5" MAX LENGTH

PLACE TESTPOINT ON FSB_IERR_L WITH A GND

PLACE GND VIA W/IN 1000 MILS

TCK PULL DOWN THROUGH 54.9 OHM(FOLLOW UP XDP DESIGN REFERENCE)

SO THE TDI PULL UP THROUGH 54.9 OHM,TMS PULL UP THROUGH 54.9 OHM

WE THROUGH THE ITP700FLEX CONNECTOR CONNECT TO PDB XDP BUFFER BOARD--ECM*50

CHANGE THE PULLS RESISTOR VALUE PER NAPA PLATFORM DG REV 0.9

WITHOUT T-ING (NO

AND CPU VR TO INFORM CPU IS HOT

1/16W 402

MF-LF

54.9

1%

R0702

1

2

MF-LF 402

5% 1/16W

68

R0704

1

2

1/16W

1%

402

MF-LF

1K

R0705

1

2

1/16W

1%

402

MF-LF

2.0K

R0706

1

2

54.9

402

1%

R0719

1 2

27.4

R0718

1 2

54.9

4021%

R0717

1 2

402

27.4

R0716

1 2

0

402

NOSTUFF

R0730

1 2

NOSTUFF

1K

MF-LF 402

5% 1/16W

R0707

1

2

MF-LF 402

5% 1/16W

51

R0712

1

2

54.9

1% 1/16W MF-LF 402

R0703

1

2

54.9

402

1%

R0720

1 2

1%

402

54.9

R0721

1 2

54.9

402

1%

R0722

1 2

BGA

YONAH

CPU

OMIT

U0700

N3 P5 P2 L1 P4 P1 R1

Y2 U5 R3 W6

A6

U4 Y5 U2 R4 T5 T3 W3 W5 Y4

J4

W2 Y1

L4 M3 K5 M1 N2 J1

H1

L2

V4

A22 A21

E2

AD4 AD3 AD1 AC4

G5

F1

C20

E1

H5 F21

A5

G6 E4

D20

C4

B3

C6 B4

H4

AC2 AC1

D21

K3 H2 K2 J3 L5

B1 F3 F4 G3

AA1

C3

B25

T22

D2 F6 D3 C1 AF1 D22 C23

AA4

C24

AB2 AA3

M4 N5 T2 V3 B2

A3

D5

AC5 AA6 AB3

A24 A25

C7

AB5

G2

AB6

CPU

YONAH

BGA

OMIT

U0700

B22 B23 C21

R26 U26 U1 V1

E22 F24

J24 J23 H26 F26 K22 H25

N22 K25 P26 R23

E26

L25 L22 L23 M23 P25 P22 P23 T24 R24 L26

H22

T25 N24

AA23 AB24 V24 V26 W25 U23 U25 U22

F23

AB25 W22 Y23 AA26 Y26 Y22 AC26 AA24

AC22 AC23

G25

AB22 AA21 AB21 AC25 AD20 AE22 AF23 AD24 AE21 AD21

E25

AE25 AF25 AF22 AF26

E23 K24 G24

J26

M26

V23

AC20

E5 B5 D24

H23

M24

W24

AD23

G22

N25

Y25

AE24

AD26

A2

AE6

D6 D7

C26

D25

SYNC_DATE=09/15/2006

SYNC_MASTER=M59_MLB

87

051-7164 06004

7

CPU 1 OF 2-FSB

FSB_RS_L<0> FSB_RS_L<1>

XDP_BPM_L<5>

FSB_HITM_L

FSB_HIT_L

FSB_RS_L<2> FSB_TRDY_L

PP1V05_S0

XDP_BPM_L<1>

FSB_DBSY_L

PP1V05_S0

XDP_TMS

XDP_TDI

XDP_TCK

FSB_A_L<3> FSB_A_L<4> FSB_A_L<5> FSB_A_L<6>

FSB_A_L<8> FSB_A_L<9> FSB_A_L<10> FSB_A_L<11> FSB_A_L<12> FSB_A_L<13>

FSB_A_L<16>

FSB_A_L<15>

FSB_A_L<14>

FSB_ADSTB_L<0>

FSB_REQ_L<2>

FSB_REQ_L<0> FSB_REQ_L<1>

FSB_REQ_L<3> FSB_REQ_L<4>

FSB_A_L<17> FSB_A_L<18> FSB_A_L<19> FSB_A_L<20> FSB_A_L<21>

FSB_A_L<23>

FSB_A_L<22>

FSB_A_L<24> FSB_A_L<25> FSB_A_L<26>

FSB_A_L<29>

FSB_A_L<28>

FSB_A_L<27>

FSB_A_L<31>

FSB_A_L<30>

FSB_ADSTB_L<1> CPU_A20M_L

CPU_FERR_L CPU_IGNNE_L

CPU_STPCLK_L

CPU_NMI

CPU_INTR

CPU_SMI_L

NC_CPU_APM1_L

NC_CPU_APM0_L

NC_CPU_A36_L

NC_CPU_A35_L

NC_CPU_A34_L

NC_CPU_A33_L

NC_CPU_A32_L

NC_CPU_A39_L

NC_CPU_A38_L

NC_CPU_A37_L

NC_CPU_HFPLL

FSB_DEFER_L FSB_DRDY_L

FSB_BREQ0_L FSB_IERR_L

CPU_INIT_L FSB_LOCK_L FSB_CPURST_L

XDP_BPM_L<0>

XDP_BPM_L<2> XDP_BPM_L<3> XDP_BPM_L<4>

XDP_TCK XDP_TDI XDP_TDO XDP_TMS XDP_TRST_L XDP_DBRESET_L

CPU_PROCHOT_L CPU_THERMD_P CPU_THERMD_N

PM_THRMTRIP_L

NC_CPU_EXTBREF

NC_CPU_SPARE0

TP_CPU_SPARE3

TP_CPU_SPARE6

TP_CPU_SPARE5

NC_CPU_SPARE4

TP_CPU_SPARE7

FSB_CLK_CPU_P FSB_CLK_CPU_N

NC_CPU_SPARE2

NC_CPU_SPARE1

FSB_A_L<7>

CPU_GTLREF

FSB_D_L<0> FSB_D_L<1> FSB_D_L<2> FSB_D_L<3> FSB_D_L<4> FSB_D_L<5> FSB_D_L<6> FSB_D_L<7> FSB_D_L<8> FSB_D_L<9> FSB_D_L<10> FSB_D_L<11> FSB_D_L<12> FSB_D_L<13> FSB_D_L<14> FSB_D_L<15> FSB_DSTBN_L<0> FSB_DSTBP_L<0> FSB_DINV_L<0>

FSB_D_L<17>

FSB_D_L<16>

FSB_D_L<18> FSB_D_L<19> FSB_D_L<20>

FSB_D_L<22>

FSB_D_L<21>

FSB_D_L<23>

FSB_D_L<25>

FSB_D_L<24>

FSB_D_L<28>

FSB_D_L<27>

FSB_D_L<26>

FSB_D_L<29> FSB_D_L<30> FSB_D_L<31>

FSB_DSTBP_L<1> FSB_DINV_L<1>

CPU_TEST1 CPU_TEST2

CPU_BSEL<1>

CPU_BSEL<0>

FSB_DSTBN_L<1>

CPU_BSEL<2>

FSB_D_L<32> FSB_D_L<33> FSB_D_L<34> FSB_D_L<35> FSB_D_L<36> FSB_D_L<37> FSB_D_L<38> FSB_D_L<39> FSB_D_L<40> FSB_D_L<41> FSB_D_L<42> FSB_D_L<43> FSB_D_L<44>

FSB_D_L<46>

FSB_D_L<45>

FSB_DSTBP_L<2>

FSB_D_L<47> FSB_DSTBN_L<2>

FSB_DINV_L<2> FSB_D_L<48>

FSB_D_L<49> FSB_D_L<50> FSB_D_L<51>

FSB_D_L<53>

FSB_D_L<52>

FSB_D_L<54> FSB_D_L<55> FSB_D_L<56> FSB_D_L<57> FSB_D_L<58> FSB_D_L<59> FSB_D_L<60> FSB_D_L<61> FSB_D_L<62> FSB_D_L<63>

FSB_DINV_L<3>

FSB_DSTBN_L<3> FSB_DSTBP_L<3>

CPU_COMP<0> CPU_COMP<1>

CPU_COMP<3>

CPU_COMP<2>

FSB_DPWR_L

CPU_DPSLP_L

CPU_DPRSTP_L

CPU_PWRGD FSB_SLPCPU_L CPU_PSI_L

FSB_ADS_L FSB_BNR_L FSB_BPRI_L

67D8

67D6

67D8

67D6

65A2

67D6

65A2

55A4

65A2

55A4

34C8

55A4

34C8

34C6

34C8

34C6

34B8

34C6

34B8

25D3

34B8

25D3

25C4

25D3

25C4

24D3

25C4

24D3

24C3

24D3

24C3

21C1

24C3

21C1

19D7

21C1

19D7

19D6

19D7

19D6

19D5

19D6

19D5

19D2

19D5

19D2

19D1

19D2

19D1

19C8

19D1

19C8

17D6

19C8

17D6

17D3

17D6

17D3

16D3

17D3

16D3

16C8

16D3

16C8

13B5

16C8

13B5

12C2

13B5

12C2

12B7

12C2

12B7

12A7

12B7

12A7

11C5

12A7

11C5

11B3

11C5

11B3

9B7

11B3

9B7

8C7

9B7

8C7

7D5

8C7

7D5

7B6

7D5

7B6

87D6

34D5

87D6

7B5

87D6

7B5

7B6

7B5

87D6

87C6

87D6

87C6

87D6

12C4

52C1

34D3

87D6

87C6

61C7

87C6

87D6

87C6

12B4

87D6

5D4

87C6

12B4

5D4

11B3

12D4

12C4

12D4

12C4

12A4

12B4

12A4

12C4

87C6

21C4

87C6

6C8

6D8

6C8

87D6

12B4

12C4

87C6

12B4

11B5

87C6

11B3

26C6

52D3

21C2

6C8

33C4

6C8

12D4

12D6

12C6

12B4

12C6

12B4

12C6

12B6

12B4

12B6

12B4

12B6

12B4

21C4

12A4

12C4

87D6

12A4

11B3

5B7

12A4

5B2

11B3

5B7

5B2

7C6

5B7

5A7

5B7

21C4

21C2

21C4

5C4

21C4

6C7

6D7

6C7

12B4

5B7

87C6

21C4

5A7

5A4

11B3

7A8

7B8

11B5

7B8

11B3

11B4

52C1

10B6

14B6

6C7

5C4

6C7

5B7

87C6

5B7

34B6

34C6

5B7

34B6

5B7

87C6

5A4

5B4

5C4

5B4

5A4

61C7

5B7

12C4

OUT OUT OUT OUT OUT OUT OUT

OUT

VSS_82 VSS_83 VSS_84 VSS_85

VSS_87

VSS_86

VSS_88 VSS_89 VSS_90

VSS_92

VSS_91

VSS_93 VSS_94 VSS_95

VSS_97

VSS_96

VSS_100

VSS_98 VSS_99

VSS_102

VSS_101

VSS_105

VSS_103 VSS_104

VSS_106 VSS_107

VSS_110

VSS_109

VSS_108

VSS_111 VSS_112

VSS_115

VSS_114

VSS_113

VSS_116 VSS_117 VSS_118

VSS_120

VSS_119

VSS_123

VSS_121 VSS_122

VSS_124 VSS_125

VSS_128

VSS_126 VSS_127

VSS_129 VSS_130

VSS_133

VSS_131 VSS_132

VSS_134 VSS_135

VSS_138

VSS_136 VSS_137

VSS_139 VSS_140 VSS_141

VSS_143

VSS_142

VSS_146

VSS_144 VSS_145

VSS_147 VSS_148

VSS_151

VSS_150

VSS_149

VSS_152 VSS_153

VSS_156

VSS_155

VSS_154

VSS_157 VSS_158 VSS_159

VSS_161

VSS_160

VSS_162

VSS_1 VSS_2 VSS_3

VSS_5

VSS_4

VSS_6 VSS_7 VSS_8

VSS_10

VSS_9

VSS_11 VSS_12

VSS_15

VSS_13 VSS_14

VSS_16 VSS_17 VSS_18 VSS_19 VSS_20

VSS_23

VSS_22

VSS_21

VSS_24 VSS_25

VSS_28

VSS_27

VSS_26

VSS_29 VSS_30

VSS_33

VSS_32

VSS_31

VSS_34 VSS_35

VSS_38

VSS_37

VSS_36

VSS_39 VSS_40 VSS_41 VSS_42 VSS_43

VSS_46

VSS_44 VSS_45

VSS_47 VSS_48

VSS_51

VSS_49 VSS_50

VSS_52 VSS_53

VSS_56

VSS_54 VSS_55

VSS_57 VSS_58 VSS_59 VSS_60 VSS_61

VSS_63

VSS_62

VSS_64 VSS_65 VSS_66

VSS_69

VSS_68

VSS_67

VSS_70 VSS_71

VSS_74

VSS_73

VSS_72

VSS_75 VSS_76

VSS_79

VSS_78

VSS_77

VSS_80 VSS_81

(4 OF 4)

VCC_67

VCC_64

VCC_66

VCC_65

VCC_63

VCC_62

VCC_61

VCC_59 VCC_60

VCC_58

VCC_57

VCC_56

VCC_54 VCC_55

VCC_53

VCC_51 VCC_52

VCC_49 VCC_50

VCC_48

VCC_47

VCC_46

VCC_44 VCC_45

VCC_43

VCC_41 VCC_42

VCC_40

VCC_39

VCC_38

VCC_36 VCC_37

VCC_33

VCC_35

VCC_34

VCC_31 VCC_32

VCC_29 VCC_30

VCC_28

VCC_26 VCC_27

VCC_23

VCC_25

VCC_24

VCC_22

VCC_21

VCC_20

VCC_18 VCC_19

VCC_17

VCC_16

VCC_15

VCC_13 VCC_14

VCC_12

VCC_10 VCC_11

VCC_8 VCC_9

VCC_7

VCC_6

VCC_5

VCC_3 VCC_4

VCC_2

VCC_1 VCC_68

VCC_69

VCC_71

VCC_70

VCC_72

VCC_74

VCC_76

VCC_75

VCC_78

VCC_77

VCC_79

VCC_81

VCC_80

VCC_84

VCC_82 VCC_83

VCC_86

VCC_85

VCC_87

VCC_89

VCC_88

VCC_90 VCC_91 VCC_92

VCC_94

VCC_93

VCC_95 VCC_96 VCC_97

VCC_99

VCC_98

VCC_100

VCCP_1 VCCP_2 VCCP_3 VCCP_4 VCCP_5 VCCP_6 VCCP_7

VCCP_9

VCCP_8

VCCP_11

VCCP_10

VCCP_12 VCCP_13 VCCP_14

VCCP_16

VCCP_15

VCCA

VID0 VID1 VID2 VID3 VID4 VID5 VID6

VSSSENSE

VCCSENSE

VCC_73

(3 OF 4)

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

VCCA=1.5 ONLY

LAYOUT NOTE: CONNECT R0803

PULL-DOWN

IF NO USE, NEED PULL-UP OR

VID FOR CPU POWER SUPPLY

TRANSMISSION LINE

RESISTORS TERMINATE THE 55 OHM

LAYOUT NOTE:

(CPU CORE POWER)

(CPU IO POWER 1.05V)

STUB.

LAYOUT NOTE:

VCCSENSE AND VSSSENSE LINES

SHOULD BE OF EQUAL LENGTH

LOCATION WHERE THE TWO 54.9 OHM

BETWEEN VCCSENSE AND VSSSENSE AT THE

TO CONNECT A DIFFERENCTIAL PROBE

PROVIDE A TEST POINT (WITH NO STUB)

LAYOUT NOTE:

TO TP_VSSSENSE WITH NO

(CPU INTERNAL PLL POWER 1.5V)

ZO=27.4 OHM DIFFERNTIAL TRACE ROUTING.

CPU_VCCSENSE_P/CPU_VCCSENSE_N USE

9C2

87B6

9C2

87B6

9C2

87B6

9C2

87B6

9C2

87B6

9C2

87B6

1/16W

1%

402

MF-LF

100

R0803

1

2

9C2

87B6

61A1 87B6

61B1 87B6

100

MF-LF 402

1% 1/16W

R0802

1

2

OMIT

BGA

YONAH

CPU

U0700

A4

B8

V25 W1 W4 W23 W26 Y3 Y6 Y21 Y24 AA2

B11

AA5 AA8 AA11 AA14 AA16 AA19 AA22 AA25 AB1 AB4

B13

AB8 AB11 AB13 AB16 AB19 AB23 AB26 AC3 AC6 AC8

B16

AC11 AC14 AC16 AC19 AC21 AC24 AD2 AD5 AD8 AD11

B19

AD13 AD16 AD19 AD22 AD25 AE1 AE4 AE8 AE11 AE14

B21

AE16 AE19 AE23 AE26 AF3 AF6 AF8 AF11 AF13 AF16

B24

AF19 AF21 AF24

C5 C8

C11

A8

C14 C16 C19

C2 C22 C25

D1

D4

D8 D11

A11

D13 D16 D19 D23 D26

E3

E6

E8 E11 E14

A14

E16 E19 E21 E24

F5

F8 F11 F13 F16 F19

A16

F2 F22 F25

G4

G1 G23 G26

H3

H6 H21

A19

H24

J2

J5 J22 J25

K1

K4 K23 K26

L3

A23

L6 L21 L24

M2

M5 M22 M25

N1

N4 N23

A26

N26

P3

P6 P21 P24 R2 R5 R22 R25 T1

B6 T4

T23 T26 U3 U6 U21 U24 V2 V5 V22

OMIT

BGA

YONAH

CPU

U0700

A7

B7

AF20

B9 B10 B12 B14 B15 B17 B18 B20

C9

A9

C10 C12 C13 C15 C17 C18

D9 D10 D12 D14

A10

D15 D17 D18

E7

E9 E10 E12 E13 E15 E17

A12

E18 E20

F7

F9 F10 F12 F14 F15 F17 F18

A13

F20 AA7 AA9

AA10 AA12 AA13 AA15 AA17 AA18 AA20

A15

AB9

AC10 AB10 AB12 AB14 AB15 AB17 AB18

AB20 AB7

A17

AC7 AC9 AC12 AC13 AC15 AC17 AC18 AD7 AD9 AD10

A18

AD12 AD14 AD15 AD17 AD18 AE9 AE10 AE12 AE13 AE15

A20

AE17 AE18 AE20 AF9 AF10 AF12 AF14 AF15 AF17 AF18

B26

V6

N6 R21 R6 T21 T6 V21 W21

G21 J6 K6 M6 J21 K21 M21 N21

AF7

AD6 AF5 AE5 AF4 AE3 AF2 AE2

AE7

CPU 2 OF 2-PWR/GND

051-7164 06004

8 87

SYNC_MASTER=M59_MLB

SYNC_DATE=09/15/2006

PPVCORE_S0_CPU

CPU_VCCSENSE_P

CPU_VCCSENSE_N

CPU_VID<6>

CPU_VID<5>

CPU_VID<4>

CPU_VID<3>

CPU_VID<2>

CPU_VID<1>

CPU_VID<0>

PP1V5_S0

PP1V05_S0

PPVCORE_S0_CPU

67D8 67D6

65A2 55A4 34C8 34C6 34B8 25D3 25C4 24D3 24C3 21C1 19D7 19D6 19D5

67C8

19D2

67C6

19D1

66C5

19C8

62C1

17D6

62A8

17D3

48B6

16D3

25D6

16C8

25C8

13B5

25C6

12C2

25C2

12B7

25B6

12A7

67D3

25B2

11C5

67D3

67D1

25A8

11B3

67D1

61D1

24B5

9B7

61D1

55D7

24A5

7D5

55D7

55A6

24A3

7B6

55A6

9D7

9B7

7B5

9D7

8D7

5D4

8B5

5B2

5D1

5B2

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

CPU VCORE VID Connections

NC NC

NOTE: This cap is shared

CPU VCORE HF AND BULK DECOUPLING

VCCP (CPU I/O) Decoupling

Will probably be removed before production

Resistors to allow for override of CPU VID

1x 10uF, 1x 0.01uF

between CPU and NB

1x 470uF, 6x 0.1uF 0402

VCCA (CPU AVdd) Decoupling

4x 330uF. 20x 22uF 0805

6.3V

20% CERM

805

22UF

C0906

1

2

6.3V

20% CERM

22UF

805

C0904

1

2

6.3V

20% CERM

22UF

805

C0916

1

2

6.3V

20% CERM

22UF

805

C0914

1

2

6.3V

20% CERM

22UF

805

C0908

1

2

6.3V

20% CERM

22UF

805

C0903

1

2

6.3V

20% CERM

22UF

805

C0907

1

2

6.3V

20% CERM

22UF

805

C0902

1

2

6.3V

20% CERM

805

22UF

C0901

1

2

6.3V

20% CERM

805

22UF

C0913

1

2

6.3V

20% CERM

22UF

805

C0912

1

2

6.3V

20% CERM

22UF

805

C0911

1

2

6.3V

20% CERM

22UF

805

C0919

1

2

6.3V

20% CERM

22UF

805

C0900

1

2

6.3V

20% CERM

22UF

805

C0910

1

2

0.1UF

CERM 402

20% 10V

C0936

1

2

470uF

CRITICAL

D2T

TANT

2.5V

20%

C0935

1

2 3

6.3V

20% CERM

22UF

805

C0905

1

2

6.3V

20% CERM

22UF

805

C0909

1

2

20% CERM

22UF

6.3V

805

C0915

1

2

6.3V

20% CERM

22UF

805

C0917

1

2

0.1UF

CERM 402

20% 10V

C0937

1

2

0.1UF

CERM 402

20% 10V

C0938

1

2

0.1UF

CERM 402

20% 10V

C0939

1

2

0.1UF

CERM 402

20% 10V

C0940

1

2

0.1UF

CERM 402

20% 10V

C0941

1

2

22UF

CERM

20%

6.3V

805

C0918

1

2

16V

0.01UF

CERM 402

20%

C0981

1

2

X5R

10uF

20%

6.3V

603

C0980

1

2

SM-LF

1/16W

5%

0

RP0990

1 2 3 4

8 7 6 5

SM-LF

1/16W

5%

0

RP0991

1 2 3 4

8 7 6 5

330UF

20%

2.5V POLY D2T

CRITICAL

C0950

1

23

CRITICAL

D2T

POLY

2.5V

20%

330UF

C0952

1

23

330UF

20%

2.5V POLY D2T

CRITICAL

C0953

1

23

CRITICAL

D2T

POLY

2.5V

20%

330UF

C0954

1

23

CPU Decoupling & VID

051-7164

SYNC_DATE=09/15/2006

SYNC_MASTER=M59_MLB

06004

9 87

PPVCORE_S0_CPU

PP1V5_S0

PP1V05_S0

CPU_VID<0> CPU_VID<1> CPU_VID<2> CPU_VID<3>

IMVP6_VID<0> IMVP6_VID<1> IMVP6_VID<2> IMVP6_VID<3>

CPU_VID<4> CPU_VID<5> CPU_VID<6>

IMVP6_VID<4> IMVP6_VID<5> IMVP6_VID<6>

67D8 67D6 65A2 55A4

34C8 34C6 34B8 25D3 25C4 24D3 24C3 21C1 19D7

19D6 19D5

67C8

19D2

67C6

19D1

66C5

19C8

62C1

17D6

62A8

17D3

48B6

16D3

25D6

16C8

25C8

13B5

25C6

12C2

25C2

12B7

25B6

12A7

67D3

25B2

11C5

67D1

25A8

11B3

61D1

24B5

8C7

55D7

24A5

7D5

55A6

24A3

7B6

8D7

8B7

7B5

8B5

5D4

87B6

61C7

87B6

61C7

5B2

5D1

5B2

8B7

5C4

8B7

5C4

IO

IN

OUT

GND

VDD

SDATA

SCLK

THM*

ALERT*/

D+ D-

THM2*

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

(TC0D)

(TO CPU INTERNAL THERMAL DIODE)

ROUTE CPU_THERMD_P AND

CPU_THERMD_N ON SAME LAYER.

10 MIL TRACE

LAYOUT NOTE:

10 MIL SPACING

LAYOUT NOTE:

CPU_THERMD_N

FOR CPU_THERMD_P AND

ADD GND GUARD TRACE

CPU ZONE THERMAL SENSOR

PLACE U1001 NEAR THE U1200

0.001UF

10%

402

CERM

50V

C1001

1

2

0.1UF

X5R

16V

10%

402

C1002

1

2

CRITICAL

TMP401

MSOP

U1001

6

3

2

5

8 7

4

1

MF-LF 402

1/16W

5%

10K

R1005

1

2

1/16W

5%

402

10K

MF-LF

R1006

1

2

499

1% 1/16W MF-LF

402

R1001

1 2

499

402

MF-LF

1/16W

1%

R1002

1 2

SYNC_DATE=09/15/2006

SYNC_MASTER=M59_MLB

051-7164 06004

10 87

CPU MISC1-TEMP SENSOR

PP3V3_S0

CPU_THERMD_P

THRM_CPU_DX_P

CPU_THERMD_N

THRM_CPU_DX_N

SMBUS_SMC_B_S0_SDA

SMBUS_SMC_B_S0_SCL

THRM_ALERT

THRM_ALERT_L

82D5 82C6 82B3 82A4 79D3 79A8 71D2 67C5

67C3 67B3 67A3 66B6 66B5 66B1 65D6 65B3

62A6 61D8 61A5 60D4 60C7 58C7 58C4 57B6 54D4

54B5 52D3 49C7 49C4 49B5 40B6 36D6 34A8 33D8

33D3 33C7 29A6 29A3 28A6 27D8 27D5 27D3 27C3

26D1 26B8 26B6 26B4 25D8 25D3 25C6 25C4 25B8

25B4 25A4 24D3 24C3 24B5 24B3 23D5 23B3 22B5 21D3

21C3 20B4 20A4 19C7 19C6 17C6

51B5

14D6

49B5

14C7

27D3

5D4

27D2

5A4

7C6

27D1

OUT OUT

OUT

IN

IN IN

IO

OUT

IN

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

ROUTE THE TCK SIGNAL FROM ITP700FLEX CONNECTOR’S TCK PIN TO CPU’S TCK PIN AND THEN FORK BACK FROM CPU TCK PIN AND ROUTE BACK TO ITP700FLEX

INDICATE THAT ITP IS USING TAP I/F, NC IN 945GM CHIPSET SYSTEM.

(FROM CK410M HOST 133/167MHZ)

(DEBUG PORT RESET)

(AND WITH RESET BUTTON)

TO ICH7M SYS_RST*, AND WITH SYSTEM RESET LOGIC

NC

(DBA#)

(DBR#)

(DEBUG PORT ACTIVE)

CPU ITP700FLEX DEBUG SUPPORT

(FBO)

(TCK)

518S0320

CONNECTOR’S FBO PIN.

ITP TCK SIGNAL LAYOUT NOTE:

MF-LF

22.6

1%

1/16W

402

ITP

R1100

1 2

ITP

402

1%

22.6

1/16W MF-LF

R1102

1 2

54.9

1/16W

1%

402

MF-LF

ITP

R1103

1

2

402

X5R

16V

10%

0.1UF

C1100

1

2

1/16W

240

402

MF-LF

5%

R1104

1

2

F-RT-SM

52435-2872

CRITICAL

ITPCONN

J1101

1

10 11 12 13 14 15 16 17 18 19

2

20 21 22 23 24 25 26 27 28

29

3

30

4 5 6 7 8 9

1/16W 402

54.9

1% MF-LF

R1101

1

2

680

402

5% 1/16W MF-LF

R1106

1

2

CPU ITP700FLEX DEBUG

051-7164 06004

11 87

SYNC_MASTER=(MASTER)

SYNC_DATE=(MASTER)

PP1V05_S0

FSB_CPURST_L

XDP_BPM_L<0>

XDP_TCK

XDP_TDI

XDP_TDO

PP3V3_S5

PP1V05_S0

XDP_TMS

CPU_XDP_CLK_N

XDP_TRST_L

XDP_BPM_L<1>

XDP_BPM_L<2>

XDP_BPM_L<3>

XDP_BPM_L<4>

XDP_BPM_L<5>

XDP_TCK

CPU_XDP_CLK_P

ITP_TDO

XDP_DBRESET_L

ITPRESET_L

67D8

67D6

65A2

55A4

34C8

34C6

34B8

25D3

25C4

79D5

25C4

24D3

67D5

24D3

24C3

67D3

24C3

21C1

67C3

21C1

19D7

66C5

19D7

19D6

65D8

19D6

19D5

65D2

19D5

19D2

65D1

19D2

19D1

65C8

19D1

19C8

63D8

19C8

17D6

56D4

17D6

17D3

26C5

17D3

16D3

25D2

16D3

16C8

25C8

16C8

13B5

25B6

13B5

12C2

24C3

12C2

12B7

24B3

12B7

12A7

24A5

12A7

11C5

23D8

11B3

9B7

23D4

9B7

8C7

23D1

8C7

7D5

23B7

7D5

7B6

87D6

23A7

7B6

87C6

7B5

12C4

11B3

22D8

7B5

34D5

11B3

34D5

5D4

7D6

87C6

7C6

22C6

5D4

7C6

34D3

87C6

7C6

34D3

26C6

5B2

5A4

7C6

7A8

7B8

7C6

5D4

5B2

7B8

33C4

7C6

7A8

33C4

7C6

87C6

IO

IO IO

OUT

IO

IO IO

IO

IO IO

IO

IO IO

IO

OUT

IO

OUT

IO IO

IO

IN

IO

IN

IO

HD4*

HD6*

HD16*

HTRDY*

HSLPCPU*

HRS1*

HRS0*

HHITM* HLOCK*

HHIT*

HDSTBP2* HDTSBP3*

HDSTBP1*

HDSTBP0*

HDSTBN3*

HDSTBN1* HDSTBN2*

HDSTBN0*

HDINV2* HDINV3*

HDINV1*

HDINV0*

HDVREF

HDRDY*

HDPWR*

HDEFER*

HDBSY*

HCPURST*

HBREQ0*

HBPRI*

HBNR*

HAVREF

HCLKIN*

HCLKIN

HYSWING

HYRCOMP HYSCOMP

HXSWING

HXSCOMP

HXRCOMP

HA13*

HADS*

HADSTB0*

HD3*

HD2*

HD1*

HD0*

HD63*

HD62*

HD61*

HD60*

HD59*

HD58*

HD57*

HD56*

HD55*

HD54*

HD53*

HD52*

HD51*

HD50*

HD49*

HD48*

HD47*

HD46*

HD45*

HD44*

HD43*

HD42*

HD41*

HD40*

HD39*

HD38*

HD37*

HD36*

HD35*

HD34*

HD33*

HD32*

HD31*

HD29*

HD28*

HD27*

HD26*

HD25*

HD24*

HD23*

HD22*

HD21*

HD20*

HD19*

HD18*

HD17*

HD15*

HD10* HD11* HD12* HD13* HD14*

HD5*

HD7* HD8* HD9*

HA30*

HA29*

HA28*

HA27*

HA26*

HA25*

HA24*

HA23*

HA31*

HA20*

HA19*

HA18*

HA16*

HA15*

HA14*

HA21* HA22*

HA17*

HA9*

HA8*

HA7*

HA6*

HA5*

HA4*

HA3*

HA10* HA11* HA12*

HADSTB1*

HREQ0* HREQ1* HREQ2* HREQ3*

HD30*

HREQ4*

HRS2*

(1 OF 10)

HOST

IO IO

IO

IO IO

IO

IO IO

IO

IO IO

IO

IO IO

IO

IO IO

IO

IO IO

IO

IO IO

IO

IO IO

IO

IO IO

IO

IO IO

IO

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

402

X5R

16V

10%

0.1uF

C1211

1

2

200

1% 1/16W MF-LF 402

R1211

1

2

100

1% 1/16W MF-LF 402

R1210

1

2

54.9

1% 1/16W MF-LF

402

R1220

1

2

402

MF-LF

1/16W

1%

24.9

R1221

1

2

221

1% 1/16W MF-LF 402

R1225

1

2

1% 1/16W MF-LF 402

100

R1226

1

2

0.1uF

402

X5R

16V

10%

C1226

1

2

402

X5R

16V

10%

0.1uF

C1236

1

2

221

1% 1/16W MF-LF 402

R1235

1

2

54.9

1% 1/16W MF-LF

402

R1230

1

2

1% 1/16W MF-LF 402

100

R1236

1

2

402

MF-LF

1/16W

1%

24.9

R1231

1

2

BGA

NB

945GM

OMIT

U1200

H11 J12

G14

D9 J14

H13

J15 F14

D12 A11

C11

A12 A13

E13

G13 F12

B12

B14 C12

A14

H9

C14

D14

C9

E11 G11

F11 G12

F9

E8 B9

C13

J13 C6

F6

C7

AG2

AG1

B7

F1

J1

K7 J8

H4

J3

K11

G4 T10

W11

T3

U7

H1

U9

U11 T11

W9

T1

T8

T4

W7

U5

T9

J6

W6

T5

AB7 AA9

W4

W3

Y3

Y7

W5

Y10

H3

AB8

W2

AA4

AA7 AA2

AA6

AA10

Y8

AA1 AB4

K2

AC9

AB11 AC11

AB3

AC2 AD1

AD9

AC1 AD7

AC6

G1

AB5

AD10

AD4 AC8

G2

K9

K1

A7 C3

J7 W8

U3

AB10

J9

H8

K4

T7

Y5 AC4

K3

T6

AA5 AC5

K13

D3 D4

B3

D8

G8 B8

F8

A8

B4

E6 D6

E3

E7

E1

E2

E4

Y1

U1

W1

SYNC_MASTER=M59_MLB

SYNC_DATE=09/15/2006

NB CPU Interface

06004

12 87

051-7164

NB_FSB_XRCOMP

PP1V05_S0

FSB_RS_L<2>

FSB_REQ_L<4>

FSB_D_L<30>

FSB_REQ_L<3>

FSB_REQ_L<2>

FSB_REQ_L<1>

FSB_REQ_L<0>

FSB_ADSTB_L<1>

FSB_A_L<12>

FSB_A_L<11>

FSB_A_L<10>

FSB_A_L<3> FSB_A_L<4> FSB_A_L<5> FSB_A_L<6> FSB_A_L<7> FSB_A_L<8> FSB_A_L<9>

FSB_A_L<17>

FSB_A_L<22>

FSB_A_L<21>

FSB_A_L<14> FSB_A_L<15> FSB_A_L<16>

FSB_A_L<18> FSB_A_L<19> FSB_A_L<20>

FSB_A_L<31>

FSB_A_L<23> FSB_A_L<24> FSB_A_L<25> FSB_A_L<26> FSB_A_L<27> FSB_A_L<28> FSB_A_L<29> FSB_A_L<30>

FSB_D_L<14>

FSB_D_L<13>

FSB_D_L<12>

FSB_D_L<11>

FSB_D_L<15>

FSB_D_L<18> FSB_D_L<19> FSB_D_L<20> FSB_D_L<21> FSB_D_L<22> FSB_D_L<23> FSB_D_L<24> FSB_D_L<25> FSB_D_L<26> FSB_D_L<27> FSB_D_L<28> FSB_D_L<29>

FSB_D_L<31> FSB_D_L<32> FSB_D_L<33> FSB_D_L<34> FSB_D_L<35> FSB_D_L<36> FSB_D_L<37> FSB_D_L<38> FSB_D_L<39> FSB_D_L<40> FSB_D_L<41> FSB_D_L<42> FSB_D_L<43> FSB_D_L<44> FSB_D_L<45> FSB_D_L<46> FSB_D_L<47> FSB_D_L<48> FSB_D_L<49> FSB_D_L<50> FSB_D_L<51> FSB_D_L<52> FSB_D_L<53> FSB_D_L<54> FSB_D_L<55> FSB_D_L<56> FSB_D_L<57> FSB_D_L<58> FSB_D_L<59> FSB_D_L<60> FSB_D_L<61> FSB_D_L<62> FSB_D_L<63>

FSB_ADSTB_L<0>

FSB_ADS_L

FSB_A_L<13>

NB_FSB_XSCOMP NB_FSB_XSWING

NB_FSB_YSCOMP

NB_FSB_YRCOMP

NB_FSB_YSWING

FSB_CLK_NB_P FSB_CLK_NB_N

FSB_BNR_L FSB_BPRI_L FSB_BREQ0_L FSB_CPURST_L FSB_DBSY_L FSB_DEFER_L FSB_DPWR_L FSB_DRDY_L

FSB_DINV_L<3>

FSB_DSTBN_L<1>

FSB_DSTBP_L<0>

FSB_HIT_L

FSB_LOCK_L

FSB_HITM_L

FSB_RS_L<0> FSB_RS_L<1>

FSB_SLPCPU_L FSB_TRDY_L

FSB_D_L<16>

FSB_D_L<0>

FSB_D_L<3>

FSB_D_L<7> FSB_D_L<8> FSB_D_L<9> FSB_D_L<10>

FSB_D_L<6>

FSB_D_L<5>

FSB_D_L<4>

FSB_D_L<2>

FSB_D_L<1>

NB_FSB_VREF

FSB_DINV_L<2>

FSB_DINV_L<1>

FSB_DSTBN_L<0>

FSB_DINV_L<0>

FSB_DSTBP_L<3>

FSB_DSTBP_L<2>

FSB_DSTBP_L<1>

FSB_DSTBN_L<3>

FSB_DSTBN_L<2>

FSB_D_L<17>

67D8

67D6

65A2

55A4

34C8

34C6

34B8

25D3

25C4

24D3

24C3

21C1

19D7

19D6

19D5

19D2

19D1

19C8

17D6

17D3

16D3

16C8

13B5

12B7

12C2

12A7

12B7

12A7

11C5

11B3

9B7

8C7

7D5

7B6

34D5

7B5

87D6

87C6

87D6

87C6

87D6

34D3

87D6

5D4

7D8

7B4

7D8

7C8

7D8

7C8

7D8

7C8

7C4

7B4

7C3

7B3

7D8

7D6

7D8

33C4

7B3

7B4

7C4

7D6

7A3

7C4

7C3

7B4

7C4

7B3

7C3

7B4

7B3

7C3

7C4

5B2

5A7

5B7

5A7

5B7

5C4

5B4

5B7

5A7

5B7

5A4

5B7

CRT_BLUE*

CRT_BLUE

CRT_GREEN*

CRT_GREEN

CRT_RED

CRT_DDC_CLK

CRT_RED*

HSYNC

CRT_DDC_DATA

CRT_VSYNC

CRT_IREF

TV_IRTNC

TV_IRTNB

TV_IREF TV_IRTNA

TV_DACB_OUT TV_DACC_OUT

TV_DACA_OUT

LB_DATA2

LB_DATA1

LB_DATA0

LB_DATA2*

LB_DATA1*

LB_DATA0*

LA_DATA2

LA_DATA1

LA_DATA0

LA_DATA2*

LA_DATA1*

LA_DATA0*

LB_CLK

LB_CLK*

LA_CLK

LA_CLK*

L_VDDEN

L_VREFL

L_VREFH

L_VBG

L_IBG

L_DDC_CLK L_DDC_DATA

EXP_A_COMPI EXP_A_COMPO

EXP_A_RXN0 EXP_A_RXN1 EXP_A_RXN2 EXP_A_RXN3 EXP_A_RXN4 EXP_A_RXN5 EXP_A_RXN6 EXP_A_RXN7 EXP_A_RXN8

EXP_A_RXN9 EXP_A_RXN10 EXP_A_RXN11 EXP_A_RXN12 EXP_A_RXN13

EXP_A_RXN15

EXP_A_RXN14

EXP_A_RXP0

EXP_A_RXP1

EXP_A_RXP2

EXP_A_RXP4

EXP_A_RXP3

EXP_A_RXP5

EXP_A_RXP6

EXP_A_RXP7

EXP_A_RXP10

EXP_A_RXP9

EXP_A_RXP8

EXP_A_RXP11 EXP_A_RXP12

EXP_A_RXP14

EXP_A_RXP13

EXP_A_RXP15

EXP_A_TXN1

EXP_A_TXN0

EXP_A_TXN3

EXP_A_TXN2

EXP_A_TXN6

EXP_A_TXN5

EXP_A_TXN4

EXP_A_TXN7

EXP_A_TXN8

EXP_A_TXN9 EXP_A_TXN10 EXP_A_TXN11 EXP_A_TXN12

EXP_A_TXN14

EXP_A_TXN13

EXP_A_TXN15

EXP_A_TXP0

EXP_A_TXP2

EXP_A_TXP1

EXP_A_TXP3

EXP_A_TXP4

EXP_A_TXP5

EXP_A_TXP7

EXP_A_TXP6

EXP_A_TXP8

EXP_A_TXP9 EXP_A_TXP10

EXP_A_TXP12

EXP_A_TXP11

EXP_A_TXP13 EXP_A_TXP14 EXP_A_TXP15

L_CLKCTLB

L_BKLTEN L_CLKCTLA

L_BKLTCTL

(3 OF 10)

LVDS

TV

VGA

PCI-EXPRESS GRAPHICS

IN

OUT

IN

OUT OUT

IN IN

OUT

IN

OUT

IO

IN

IN IN

IN

OUT

IN

OUT

IN

OUT

IN

OUT

OUT OUT

OUT

IN

IO IO

OUT

OUT OUT

OUT

OUT OUT

IN

OUT

IN

OUT

IO IO

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

Tie VCC_TXLVDS and VCCA_LVDS to GND. If SDVO is used

Can leave all signals NC if LVDS is not implemented

CRT Disable

TV-Out Disable

Composite: DACA only

TV-Out Signal Usage:

HSYNC and VSYNC to GND. Tie VCCA_CRTDAC to VCC Core

Unused DAC outputs must remain powered, but can omit

S-Video: DACB & DACC only

connect to GND through 75-ohm resistors.

Tie VCCD_TVDAC, VCCD_QTVDAC, VCCA_TVDACx, and

Component: DACA, DACB & DACC

rail, and tie VSSA_CRTDAC and VCC_SYNC to GND.

VCCA_TVBG to 1.5V power rail. Tie VSSA_TVBG to GND.

Tie DACx_OUT, IRTNx, and IREF to 1.5V power rail.

filtering components. Unused DAC outputs should

Tie R/R#/G/G#/B/B# and IREF to VCC Core rail, tie

VCCD_LVDS must remain powered with proper decoupling.

LVDS Disable

Otherwise, tie VCCD_LVDS to GND also.

SDVOC_CLKP

SDVOC_BLUE

SDVOC_GREEN

SDVOC_RED

SDVOB_BLUE SDVOB_CLKP

SDVOB_RED# SDVOB_GREEN# SDVOB_BLUE# SDVOB_CLKN SDVOC_RED# SDVOC_GREEN# SDVOC_BLUE# SDVOC_CLKN

SDVOB_RED SDVOB_GREEN

SDVO_FLDSTALL

SDVO_INT

SDVO_TVCLKIN

SDVO_INT#

SDVO_TVCLKIN#

SDVO Alternate Function

SDVO_FLDSTALL#

OMIT

945GM

NB

BGA

U1200

E23

D23

C26

C25

C22

B22

J22

A21 B21

H23

D40 D38

F34

G38

V34 W38

Y34 AA38

AB34

AC38

H34

J38

L34 M38

N34

P38 R34

T38

D34 F38

T34

V38 W34

Y38

AA34 AB38

G34

H38 J34

L38

M34 N38

P34 R38

F36

G40

V36 W40

Y36 AA40

AB36

AC40

H36

J40

L36 M40

N36

P40 R36

T40

D36 F40

T36

V40 W36

Y40

AA36 AB40

G36

H40 J36

L40

M36 N40

P36 R40

G23

D32 J30

H30

H29 G26

G25 B38

C35

F32 C33

C32

A32

A33

B37

C37

B34

B35

A36

A37

E26

E27

F30

G30

D29

D30

F28

F29

A16

C18

A19

J20 B16

B18 B19

24.9

1% 1/16W MF-LF 402

R1310

1

2

NB PEG / Video Interfaces

SYNC_DATE=09/15/2006

SYNC_MASTER=M59_MLB

13 87

06004051-7164

GND

TP_LVDS_CLKCTLB

PP1V5_S0_NB

LVDS_BKLTCTL

TP_LVDS_CLKCTLA

LVDS_BKLTEN

PEG_R2D_C_P<15>

PEG_R2D_C_P<14>

PEG_R2D_C_P<13>

PEG_R2D_C_P<11> PEG_R2D_C_P<12>

PEG_R2D_C_P<10>

PEG_R2D_C_P<9>

PEG_R2D_C_P<8>

PEG_R2D_C_P<6> PEG_R2D_C_P<7>

PEG_R2D_C_P<5>

PEG_R2D_C_P<4>

PEG_R2D_C_P<3>

PEG_R2D_C_P<1> PEG_R2D_C_P<2>

PEG_R2D_C_P<0>

PEG_R2D_C_N<15>

PEG_R2D_C_N<13> PEG_R2D_C_N<14>

PEG_R2D_C_N<12>

PEG_R2D_C_N<11>

PEG_R2D_C_N<10>

PEG_R2D_C_N<9>

PEG_R2D_C_N<8>

PEG_R2D_C_N<7>

PEG_R2D_C_N<4> PEG_R2D_C_N<5> PEG_R2D_C_N<6>

PEG_R2D_C_N<2> PEG_R2D_C_N<3>

PEG_R2D_C_N<0> PEG_R2D_C_N<1>

PEG_D2R_P<15>

PEG_D2R_P<13> PEG_D2R_P<14>

PEG_D2R_P<12>

PEG_D2R_P<11>

PEG_D2R_P<8> PEG_D2R_P<9> PEG_D2R_P<10>

PEG_D2R_P<7>

PEG_D2R_P<6>

PEG_D2R_P<5>

PEG_D2R_P<3> PEG_D2R_P<4>

PEG_D2R_P<2>

PEG_D2R_P<1>

PEG_D2R_P<0>

PEG_D2R_N<14>

PEG_D2R_N<13>

PEG_D2R_N<12>

PEG_D2R_N<11>

PEG_D2R_N<10>

PEG_D2R_N<8>

PEG_D2R_N<6>

PEG_D2R_N<5>

PEG_D2R_N<4>

PEG_D2R_N<3>

PEG_D2R_N<2>

PEG_D2R_N<1>

PEG_D2R_N<0>

PEG_COMP

LVDS_CONN_DDC_DATA

LVDS_CONN_DDC_CLK

LVDS_IBG TP_LVDS_VBG

GND GND

LVDS_VDDEN

LVDS_A_CLK_N LVDS_A_CLK_P LVDS_B_CLK_N LVDS_B_CLK_P

LVDS_A_DATA_N<0> LVDS_A_DATA_N<1> LVDS_A_DATA_N<2>

LVDS_A_DATA_P<0> LVDS_A_DATA_P<1> LVDS_A_DATA_P<2>

LVDS_B_DATA_N<0> LVDS_B_DATA_N<1> LVDS_B_DATA_N<2>

LVDS_B_DATA_P<0> LVDS_B_DATA_P<1> LVDS_B_DATA_P<2>

PP1V05_S0

TP_CRT_DDC_DATA

PP1V05_S0

TP_CRT_DDC_CLK

PP1V05_S0

PP1V05_S0 PP1V05_S0

PEG_D2R_N<15>

PEG_D2R_N<9>

PEG_D2R_N<7>

PP1V5_S0_NB

67D8

67D6

65A2

55A4

34C8

34C6

34B8

25D3

25C4

24D3

24C3

21C1

19D7

19D6

19D5

67C8

19D2

67C6

19D1

67B6

19C8

62A7

17D6

19D7

17D3

19D6

16D3

19D5

16C8

19D2

13B5

19D1

12C2

19C5

12B7

19C4

12A7

19C1

11C5

19B8

11B3

19B5

9B7

19A5

8C7

17C6

7D5

17B6

7B6

16D1

82A7

7B5

13D2

19D4

13C5

19D4

82A5

5D4

19D6

5D4

19D6

5D4

13C5

19D3

5D4

82A4

19D3

82A4

70B5

70C5

70D5

70B5

70C5

70D5

70B1

70C1

70D1

70B1

70C1

70D1

79C3

19D3

82A4

82D3

82C3

82D3

82C3

82D3

82C3

5B2

19D5

5B2

19D5

5B2

70B1

70C1

5D4

SM_CS0*

RSVD15

RSVD14

SM_CKE2

RSVD2 RSVD3

RSVD6

RSVD4 RSVD5

RSVD8

RSVD7

RSVD9

RSVD1

RSVD10 RSVD11 RSVD12 RSVD13

CFG1

CFG0

CFG2 CFG3 CFG4

CFG6

CFG5

CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14

CFG17

CFG16

CFG15

CFG18 CFG19 CFG20

PM_BM_BUSY* PM_EXTTS0* PM_EXTTS1* PW_THRMTRIP* PWROK RSTIN*

SDVO_CTRLCLK SDVO_CTRLDATA ICH_SYNC* CLK_REQ*

NC2 NC3 NC4 NC5 NC6 NC7 NC8 NC9

NC0 NC1

NC13

NC12

NC11

NC10

NC18

NC17

NC16

NC15

NC14

SM_CK0 SM_CK1 SM_CK2

SM_CK0*

SM_CK3

SM_CK1* SM_CK2* SM_CK3*

SM_CKE0 SM_CKE1

SM_CKE3

SM_CS1* SM_CS2* SM_CS3*

SMOCDCOMP0 SMOCDCOMP1

SM_ODT1

SM_ODT0

SM_ODT2

SMRCOMP*

SM_ODT3

SMRCOMP

SMVREF0 SMVREF1

G_CLKIN*

G_CLKIN

D_REFCLKIN*

D_REFCLKIN

D_REFSSCLKIN*

D_REFSSCLKIN

DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3

DMI_RXP0 DMI_RXP1 DMI_RXP2 DMI_RXP3

DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3

DMI_TXP0

DMI_TXP2

DMI_TXP1

DMI_TXP3

DDR MUXING

CFG

NC PM

CLKDMI

MISC

(2 OF 10)

RSVD

IN

OUT

IN

IO IO

OUT

OUT OUT

OUT

OUT OUT

IN

IN IN

IN

IN IN

IN

IN IN

IN

OUT

IN IN

IN

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

NC NC

IPD

(LA_DATAN3) (LA_DATAP3) (LB_DATAN3) (LB_DATAP3)

(H_EDRDY#)

(D_PLLMON1)

(H_PROCHOT#)

(TESTIN#) (TV_DCONSEL0) (TV_DCONSEL1)

(H_PLLMON1)

(H_PLLMON1#)

(H_PCREQ#)

(VSS_MCHDETECT)

(D_PLLMON1#)

NC NC NC

NC

NC NC NC NC NC NC NC NC NC

NC

NC NC NC NC NC

IPU

IPD

IPU

IPU IPU

IPU

NC

IPU

NC

OMIT

945GM

NB

BGA

U1200

K16

K18

E16 D15

G15

K15 C15

H16

G18 H15

J25 K27

J18

J26

F18

E15

F15 E18

D19 D16

G16

H32

A26

A27

D41

C40

AE35 AF39

AG35

AH39

AC35 AE39

AF35

AG39

AE37

AF41

AG37 AH41

AC37

AE41

AF37 AG41

AG33

AF33

K28

D1

C41

B2

AY41

AY1

AW41

AW1

A40

A4

A39

A3

C1

BA41

BA40 BA39

BA3

BA2 BA1

B41

G28

F25 H26

G6

AH33 AH34

T32

J29

A41

A35 A34

D28 D27

R32

F3 F7

AG11

AF11

H7

J19

K30

H28

H27

AY35

AW35

AR1

AT1

AW7

AY7

AW40

AY40

AU20

AT20

BA29 AY29

AW13

AW12 AY21

AW21

BA13 BA12

AY20 AU21

AL20

AF10

AT9

AV9

AK1

AK41

100

5% 1/16W MF-LF

402

R1430

1 2

1/16W MF-LF

5%

402

10K

R1441

1

2

MF-LF

1/16W

5%

402

10K

R1440

1

2

20% 10V CERM 402

0.1uF

C1416

1

2

20% 10V

CERM

402

0.1uF

C1415

1

2

80.6

MF-LF 402

1% 1/16W

R1410

1

2

80.6

MF-LF 402

1% 1/16W

R1411

1

2

10K

MF-LF

402

5%

1/16W

R1420

1

2

14 87

06004051-7164

SYNC_MASTER=M59_MLB

SYNC_DATE=09/15/2006

NB Misc Interfaces

TP_NB_XOR_FSB2_H7

NC_NB_XOR_LVDS_D27

NC_NB_XOR_LVDS_D28

NC_NB_XOR_LVDS_A34

MEMVREF_OUT

MEM_RCOMP

MEM_RCOMP_L

PP1V8_S3

MEM_CKE<2>

MEM_CS_L<1> MEM_CS_L<2> MEM_CS_L<3>

MEM_ODT<1> MEM_ODT<2>

NB_CFG<12>

MEM_CS_L<0>

NB_BSEL<1>

NB_BSEL<0>

NB_BSEL<2> NB_CFG<3> NB_CFG<4>

NB_CFG<6>

NB_CFG<5>

NB_CFG<7>

NB_CFG<9> NB_CFG<10>

TP_NB_CFG<14>

NB_CFG<17>

NB_CFG<16>

TP_NB_CFG<15>

NB_CFG<19> NB_CFG<20>

PM_BMBUSY_L

PM_THRMTRIP_L VR_PWRGOOD_DELAY

TP_SDVO_CTRLCLK TP_SDVO_CTRLDATA NB_SB_SYNC_L

MEM_CLK_P<0> MEM_CLK_P<1> MEM_CLK_P<2>

MEM_CLK_N<0>

MEM_CLK_P<3>

MEM_CLK_N<1> MEM_CLK_N<2> MEM_CLK_N<3>

MEM_CKE<0> MEM_CKE<1>

MEM_CKE<3>

MEM_ODT<0>

MEM_ODT<3>

NB_CLK100M_GCLKIN_N NB_CLK100M_GCLKIN_P

DMI_S2N_N<0> DMI_S2N_N<1> DMI_S2N_N<2> DMI_S2N_N<3>

DMI_S2N_P<0> DMI_S2N_P<1> DMI_S2N_P<2> DMI_S2N_P<3>

DMI_N2S_N<0> DMI_N2S_N<1> DMI_N2S_N<2> DMI_N2S_N<3>

DMI_N2S_P<0>

DMI_N2S_P<2>

DMI_N2S_P<1>

DMI_N2S_P<3>

PLT_RST_L

NB_CFG<8>

NB_CFG<11>

NB_CFG<13>

NB_CFG<18>

PP3V3_S0

PM_DPRSLPVR

TP_NB_TESTIN_L

NC_NB_XOR_LVDS_A35

NB_TV_DCONSEL0 NB_TV_DCONSEL1

PP3V3_S0

NB_CLK_DREFSSCLKIN_P

NB_CLK_DREFSSCLKIN_N

NB_CLK_DREFCLKIN_P

NB_CLK_DREFCLKIN_N

CLK_NB_OE_L

NB_RST_IN_L_R

PM_EXTTS_L

82D5

82C6

82B3

82A4

79D3

79A8

71D2

67C5

67C3

67B3

67A3

66B6

66B5

66B1

65D6

65B3

62A6

61D8

61A5

60D4

60C7

58C7

58C4

57B6

54D4

54B5

52D3

49C7

49C4

49B5

40B6

36D6

34A8

33D8

33D3

33C7

29A6

29A3

28A6

27D8

27D5

27D3

27C3

26D1

26B8

26B6

26B4

25D8

25D3

25C6

25C4

25B8

25B4

25A4

24D3

67B8

24C3

67B6

24B5

64C1

24B3

64A6

23D5

37B2

23B3

32C6

22B5

31C5

21D3

29D6

82A4

21C3

29D3

79A8

20B4

29B2

26C3

20A4

28D6

26C1

19C7

28D3

26B1

19C6

32B4

28B2

26A4

17C6

52D5

32B3

19D7

34C5

22A6

14D6

87C6

14C7

34B5

52D3

29D6

16B6

52C1

61C7

34C4

6C7

10C5

61C8

10C5

34B4

51B7

19D4

28D6

5D4

30D6

30C6

30D6

21C2

26B5

19D4

22A6

30D6

30C6

33B4

6C6

5D4

23C3

19D4

5D4

33B4

34B2

33B4

29C3

19D3

14C2

5B2

29C6

28B6

29B3

29B6

28B6

29B3

6C6

28B3

34B7

34C7

34B7

6D6

20C7

20B7

6D6

6D7

6D6

20C5

6D7

20B5

20A5

23C5

7C6

5A4

19D3

5A4

28D3

28A3

29A3

28D3

29D3

28A3

29A3

29D3

28C6

28C3

29C3

28B3

29B6

5B4

22D2

5C4

6D6

6C6

20B5

5A4

5B4

19D3

5A4

5B4

28C3

SA_DQ1

SA_DQ0

SA_DQ2 SA_DQ3 SA_DQ4 SA_DQ5 SA_DQ6 SA_DQ7 SA_DQ8 SA_DQ9 SA_DQ10

SA_DQ12

SA_DQ11

SA_DQ13 SA_DQ14 SA_DQ15 SA_DQ16 SA_DQ17 SA_DQ18 SA_DQ19 SA_DQ20 SA_DQ21 SA_DQ22 SA_DQ23 SA_DQ24 SA_DQ25 SA_DQ26 SA_DQ27

SA_DQ29

SA_DQ28

SA_DQ30 SA_DQ31 SA_DQ32 SA_DQ33

SA_DQ35

SA_DQ34

SA_DQ36 SA_DQ37 SA_DQ38 SA_DQ39 SA_DQ40 SA_DQ41 SA_DQ42 SA_DQ43 SA_DQ44

SA_DQ46

SA_DQ45

SA_DQ47 SA_DQ48 SA_DQ49 SA_DQ50 SA_DQ51 SA_DQ52 SA_DQ53 SA_DQ54 SA_DQ55 SA_DQ56 SA_DQ57 SA_DQ58 SA_DQ59 SA_DQ60 SA_DQ61 SA_DQ62 SA_DQ63

SA_BS1

SA_BS0

SA_BS2

SA_CAS*

SA_DM0 SA_DM1 SA_DM2 SA_DM3

SA_DM5

SA_DM4

SA_DM7

SA_DM6

SA_DQS0

SA_DQS2

SA_DQS1

SA_DQS3

SA_DQS5

SA_DQS4

SA_DQS6 SA_DQS7

SA_DQS3*

SA_DQS2*

SA_DQS4* SA_DQS5* SA_DQS6* SA_DQS7*

SA_MA1

SA_MA0

SA_MA2 SA_MA3

SA_MA5

SA_MA4

SA_MA6 SA_MA7

SA_MA9

SA_MA8

SA_MA10 SA_MA11 SA_MA12 SA_MA13

SA_RAS*

SA_RCVENIN*

SA_RCVENOUT*

SA_WE*

SA_DQS1*

SA_DQS0*

(4 OF 10)

DDR SYSTEM MEMORY A

IO

IO IO

IO

OUT

IO

OUT

IO IO

IO

IO IO

IO

IO IO

IO

IO IO

IO

IO IO

IO

SB_DQ1

SB_DQ0

SB_DQ2 SB_DQ3 SB_DQ4 SB_DQ5 SB_DQ6 SB_DQ7 SB_DQ8 SB_DQ9 SB_DQ10

SB_DQ12

SB_DQ11

SB_DQ13 SB_DQ14 SB_DQ15 SB_DQ16 SB_DQ17 SB_DQ18 SB_DQ19 SB_DQ20 SB_DQ21 SB_DQ22 SB_DQ23 SB_DQ24 SB_DQ25 SB_DQ26 SB_DQ27

SB_DQ29

SB_DQ28

SB_DQ30 SB_DQ31 SB_DQ32 SB_DQ33

SB_DQ35

SB_DQ34

SB_DQ36 SB_DQ37 SB_DQ38 SB_DQ39 SB_DQ40 SB_DQ41 SB_DQ42 SB_DQ43 SB_DQ44

SB_DQ46

SB_DQ45

SB_DQ47 SB_DQ48 SB_DQ49 SB_DQ50 SB_DQ51 SB_DQ52 SB_DQ53 SB_DQ54 SB_DQ55 SB_DQ56 SB_DQ57 SB_DQ58 SB_DQ59 SB_DQ60 SB_DQ61 SB_DQ62 SB_DQ63

SB_BS1

SB_BS0

SB_BS2

SB_CAS*

SB_DM0 SB_DM1 SB_DM2 SB_DM3

SB_DM5

SB_DM4

SB_DM7

SB_DM6

SB_DQS0

SB_DQS2

SB_DQS1

SB_DQS3

SB_DQS5

SB_DQS4

SB_DQS6 SB_DQS7

SB_DQS3*

SB_DQS2*

SB_DQS4* SB_DQS5* SB_DQS6* SB_DQS7*

SB_MA1

SB_MA0

SB_MA2 SB_MA3

SB_MA5

SB_MA4

SB_MA6 SB_MA7

SB_MA9

SB_MA8

SB_MA10 SB_MA11 SB_MA12 SB_MA13

SB_RAS*

SB_RCVENIN*

SB_RCVENOUT*

SB_WE*

SB_DQS1*

SB_DQS0*

(5 OF 10)

DDR SYSTEM MEMORY B

IO IO

IO

IO IO

IO

OUT

IO

OUT

IO

OUT

IO

IO IO

IO

OUT

IO

OUT OUT

OUT

IO

OUT

IO

OUT

IO

OUT OUT

OUT

IO

OUT

IO

IO IO

IO

IO IO

IO

IO IO

IO

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

NC NC

OMIT

NB

945GM

BGA

U1200

AU12

AV14

BA20

AY13 AJ33

AM35

AL26 AN22

AM14

AL9 AR3

AH4

AJ35

AJ34

AR31 AP31

AN38

AM36 AM34

AN33

AK26 AL27

AM26

AN24

AM31

AK28

AL28 AM24

AP26

AP23 AL22

AP21

AN20 AL23

AP24

AM33

AP20 AT21

AR12 AR14

AP13

AP12 AT13

AT12

AL14 AL12

AJ36

AK9

AN7 AK8

AK7 AP9

AN9

AT5 AL5

AY2

AW2

AK35

AP1

AN2

AV2 AT3

AN1 AL2

AG7

AF9 AG4

AF6

AJ32

AG9 AH6

AF4

AF8

AH31

AN35 AP33

AK33

AK32

AT33

AU33

AN28

AN27

AM22

AM21

AN12

AM12

AN8

AL8

AP3

AN3

AG5

AH5

AY16

AU14

AU13

AT17

AV20 AV12

AW16

BA16 BA17

AU16

AV17 AU17

AW17

AT16

AW14

AK23

AK24 AY14

OMIT

NB

945GM

BGA

U1200

AT24

AV23

AY28

AR24 AK36

AR38

AT36 BA31

AL17

AH8 BA5

AN4

AK39

AJ37

AU38 AV38

AP38

AR40 AW38

AY38

BA38 AV36

AR36

AP36

AP39

BA36

AU36 AP35

AP34

AY33 BA33

AT31

AU29 AU31

AW31

AR41

AV29 AW29

AM19 AL19

AP14

AN14 AN17

AM16

AP15 AL15

AJ38

AJ11

AH10

AJ9

AN10 AK13

AH11

AK10

AJ8

BA10

AW10

AK38

BA4

AW4

AY10

AY9

AW5 AY5

AV4

AR5 AK4

AK3

AN41

AT4 AK5

AJ5

AJ3

AP41

AT40 AV41

AM39

AM40

AT39

AU39

AU35

AT35

AR29

AP29

AR16

AP16

AR10

AT10

AR7

AT7

AN5

AP5

AY23

AW24

AV24

BA27

AY27 AR23

AY24

AR28 AT27

AT28

AU27 AV28

AV27

AW27

AU23

AK16

AK18 AR27

15 87

06004051-7164

NB DDR2 Interfaces

SYNC_MASTER=M59_MLB

SYNC_DATE=09/15/2006

MEM_A_DQ<5>

MEM_A_DQS_N<0> MEM_A_DQS_N<1>

MEM_A_WE_L

MEM_A_RAS_L

MEM_A_A<13>

MEM_A_A<12>

MEM_A_A<11>

MEM_A_A<10>

MEM_A_A<8> MEM_A_A<9>

MEM_A_A<7>

MEM_A_A<6>

MEM_A_A<4> MEM_A_A<5>

MEM_A_A<3>

MEM_A_A<2>

MEM_A_A<0> MEM_A_A<1>

MEM_A_DQS_N<7>

MEM_A_DQS_N<6>

MEM_A_DQS_N<5>

MEM_A_DQS_N<4>

MEM_A_DQS_N<2> MEM_A_DQS_N<3>

MEM_A_DQS_P<7>

MEM_A_DQS_P<6>

MEM_A_DQS_P<4> MEM_A_DQS_P<5>

MEM_A_DQS_P<3>

MEM_A_DQS_P<1> MEM_A_DQS_P<2>

MEM_A_DQS_P<0>

MEM_A_DM<6> MEM_A_DM<7>

MEM_A_DM<4> MEM_A_DM<5>

MEM_A_DM<3>

MEM_A_DM<2>

MEM_A_DM<1>

MEM_A_DM<0>

MEM_A_CAS_L

MEM_A_BS<2>

MEM_A_BS<0> MEM_A_BS<1>

MEM_A_DQ<63>

MEM_A_DQ<62>

MEM_A_DQ<61>

MEM_A_DQ<60>

MEM_A_DQ<59>

MEM_A_DQ<58>

MEM_A_DQ<57>

MEM_A_DQ<56>

MEM_A_DQ<55>

MEM_A_DQ<54>

MEM_A_DQ<53>

MEM_A_DQ<52>

MEM_A_DQ<51>

MEM_A_DQ<50>

MEM_A_DQ<49>

MEM_A_DQ<48>

MEM_A_DQ<47>

MEM_A_DQ<45> MEM_A_DQ<46>

MEM_A_DQ<44>

MEM_A_DQ<43>

MEM_A_DQ<42>

MEM_A_DQ<41>

MEM_A_DQ<40>

MEM_A_DQ<39>

MEM_A_DQ<38>

MEM_A_DQ<37>

MEM_A_DQ<36>

MEM_A_DQ<34> MEM_A_DQ<35>

MEM_A_DQ<33>

MEM_A_DQ<32>

MEM_A_DQ<31>

MEM_A_DQ<30>

MEM_A_DQ<28> MEM_A_DQ<29>

MEM_A_DQ<27>

MEM_A_DQ<26>

MEM_A_DQ<25>

MEM_A_DQ<24>

MEM_A_DQ<23>

MEM_A_DQ<22>

MEM_A_DQ<21>

MEM_A_DQ<20>

MEM_A_DQ<19>

MEM_A_DQ<18>

MEM_A_DQ<17>

MEM_A_DQ<16>

MEM_A_DQ<15>

MEM_A_DQ<14>

MEM_A_DQ<13>

MEM_A_DQ<11> MEM_A_DQ<12>

MEM_A_DQ<10>

MEM_A_DQ<9>

MEM_A_DQ<8>

MEM_A_DQ<7>

MEM_A_DQ<6>

MEM_A_DQ<4>

MEM_A_DQ<3>

MEM_A_DQ<2>

MEM_A_DQ<0> MEM_A_DQ<1>

MEM_B_DQS_N<0> MEM_B_DQS_N<1>

MEM_B_WE_L

MEM_B_RAS_L

MEM_B_A<13>

MEM_B_A<12>

MEM_B_A<11>

MEM_B_A<10>

MEM_B_A<8> MEM_B_A<9>

MEM_B_A<7>

MEM_B_A<6>

MEM_B_A<4> MEM_B_A<5>

MEM_B_A<3>

MEM_B_A<2>

MEM_B_A<0> MEM_B_A<1>

MEM_B_DQS_N<7>

MEM_B_DQS_N<6>

MEM_B_DQS_N<5>

MEM_B_DQS_N<4>

MEM_B_DQS_N<2> MEM_B_DQS_N<3>

MEM_B_DQS_P<7>

MEM_B_DQS_P<6>

MEM_B_DQS_P<4> MEM_B_DQS_P<5>

MEM_B_DQS_P<3>

MEM_B_DQS_P<1> MEM_B_DQS_P<2>

MEM_B_DQS_P<0>

MEM_B_DM<6> MEM_B_DM<7>

MEM_B_DM<4> MEM_B_DM<5>

MEM_B_DM<3>

MEM_B_DM<2>

MEM_B_DM<1>

MEM_B_DM<0>

MEM_B_CAS_L

MEM_B_BS<2>

MEM_B_BS<0> MEM_B_BS<1>

MEM_B_DQ<63>

MEM_B_DQ<62>

MEM_B_DQ<61>

MEM_B_DQ<60>

MEM_B_DQ<59>

MEM_B_DQ<58>

MEM_B_DQ<57>

MEM_B_DQ<56>

MEM_B_DQ<55>

MEM_B_DQ<54>

MEM_B_DQ<53>

MEM_B_DQ<52>

MEM_B_DQ<51>

MEM_B_DQ<50>

MEM_B_DQ<49>

MEM_B_DQ<48>

MEM_B_DQ<47>

MEM_B_DQ<45> MEM_B_DQ<46>

MEM_B_DQ<44>

MEM_B_DQ<43>

MEM_B_DQ<42>

MEM_B_DQ<41>

MEM_B_DQ<40>

MEM_B_DQ<39>

MEM_B_DQ<38>

MEM_B_DQ<37>

MEM_B_DQ<36>

MEM_B_DQ<34> MEM_B_DQ<35>

MEM_B_DQ<33>

MEM_B_DQ<32>

MEM_B_DQ<31>

MEM_B_DQ<30>

MEM_B_DQ<28> MEM_B_DQ<29>

MEM_B_DQ<27>

MEM_B_DQ<26>

MEM_B_DQ<25>

MEM_B_DQ<24>

MEM_B_DQ<23>

MEM_B_DQ<22>

MEM_B_DQ<21>

MEM_B_DQ<20>

MEM_B_DQ<19>

MEM_B_DQ<18>

MEM_B_DQ<17>

MEM_B_DQ<16>

MEM_B_DQ<15>

MEM_B_DQ<14>

MEM_B_DQ<13>

MEM_B_DQ<11> MEM_B_DQ<12>

MEM_B_DQ<10>

MEM_B_DQ<9>

MEM_B_DQ<8>

MEM_B_DQ<7>

MEM_B_DQ<6>

MEM_B_DQ<5>

MEM_B_DQ<4>

MEM_B_DQ<3>

MEM_B_DQ<2>

MEM_B_DQ<0> MEM_B_DQ<1>

30B6

30C6

30B6

30A6

30B6

30A6

28D6

28B6

28B3

28C6

28C3

28B6

28C6

28C3

28B3

28B6

28B3

28B6

28B3

28A3

28A6

28B6

28C6

28C3

28A3

28B6

28A6

28C3

28D6

28C6

28D6

28A6

28B3

28A3

28C6

28C3

28D3

28B6

28C6

28B6

28B3

28A3

28A6

28B6

28A6

28B3

28A3

28A6

28A3

28A6

28A3

28A6

28A3

28A6

28A3

28A6

28A3

28A6

28A3

28B6

28B3

28B6

28B3

28B6

28B3

28C3

28C6

28C3

28C6

28C3

28C6

28C3

28C6

28C3

28C6

28D3

28D6

28D3

28D6

28D3

28D6

28D3

29D6

29B6

29B3

29C6

29C3

29B6

29C6

29C3

29B3

29B6

29B3

29B6

29A6

29A3

29B3

29B6

29C6

29C3

29A6

29A3

29B6

29A3

29C3

29D6

29C6

29D6

29A6

29A3

29B3

29A6

29C6

29C3

29D3

29B6

29C6

29B6

29B3

29A3

29A6

29A3

29A6

29A3

29A6

29A3

29A6

29A3

29B3

29A3

29B3

29A6

29B6

29B3

29B6

29B3

29C3

29C6

29C3

29C6

29C3

29C6

29C3

29D6

29D3

29D6

29D3

29D6

29D3

29D6

29D3

29D6

29D3

29D6

VCC_SM19

VCC_SM107

VCC_SM105

VCC_SM106

VCC_SM102

VCC_SM104

VCC_SM103

VCC_SM100

VCC_SM101

VCC_SM98

VCC_SM99

VCC_SM97

VCC_SM95

VCC_SM96

VCC_SM93

VCC_SM94

VCC_SM92

VCC_SM91

VCC_SM90

VCC_SM89

VCC_SM88

VCC_SM86

VCC_SM87

VCC_SM85

VCC_SM84

VCC_SM83

VCC_SM81

VCC_SM80

VCC_SM82

VCC_SM79

VCC_SM78

VCC_SM77

VCC_SM74

VCC_SM75

VCC_SM76

VCC_SM73

VCC_SM72

VCC_SM70

VCC_SM71

VCC_SM68

VCC_SM67

VCC_SM69

VCC_SM65

VCC_SM66

VCC_SM64

VCC_SM63

VCC_SM62

VCC_SM61

VCC_SM60

VCC_SM59

VCC_SM58

VCC_SM56

VCC_SM57

VCC_SM55

VCC_SM53

VCC_SM54

VCC_SM52

VCC_SM50

VCC_SM51

VCC_SM49

VCC_SM48

VCC_SM46

VCC_SM47

VCC_SM44

VCC_SM45

VCC_SM43

VCC_SM41

VCC_SM42

VCC_SM40

VCC_SM39

VCC_SM37

VCC_SM38

VCC_SM36

VCC_SM34

VCC_SM35

VCC_SM32

VCC_SM33

VCC_SM30

VCC_SM31

VCC_SM28

VCC_SM29

VCC_SM27

VCC_SM26

VCC_SM25

VCC_SM23

VCC_SM24

VCC_SM22

VCC_SM21

VCC_SM20

VCC_SM18

VCC_SM16

VCC_SM17

VCC_SM15

VCC_SM13

VCC_SM14

VCC_SM11

VCC_SM12

VCC_SM10

VCC_SM9

VCC_SM8

VCC_SM7

VCC_SM6

VCC_SM5

VCC_SM4

VCC_SM3

VCC_SM0

VCC_SM1

VCC_SM2

VCC_110

VCC_109

VCC_108

VCC_105

VCC_106

VCC_107

VCC_104

VCC_103

VCC_101

VCC_100

VCC_102

VCC_98

VCC_99

VCC_96

VCC_97

VCC_95

VCC_94

VCC_93

VCC_92

VCC_91

VCC_90

VCC_88

VCC_89

VCC_87

VCC_86

VCC_85

VCC_83

VCC_84

VCC_82

VCC_80

VCC_81

VCC_79

VCC_78

VCC_76

VCC_77

VCC_74

VCC_73

VCC_75

VCC_72

VCC_71

VCC_70

VCC_69

VCC_68

VCC_67

VCC_66

VCC_65

VCC_64

VCC_62

VCC_63

VCC_61

VCC_60

VCC_59

VCC_57

VCC_58

VCC_55

VCC_56

VCC_53

VCC_54

VCC_52

VCC_50

VCC_51

VCC_49

VCC_46

VCC_47

VCC_48

VCC_44

VCC_45

VCC_43

VCC_42

VCC_41

VCC_40

VCC_39

VCC_38

VCC_37

VCC_36

VCC_34

VCC_35

VCC_33

VCC_32

VCC_31

VCC_30

VCC_28

VCC_29

VCC_25

VCC_26

VCC_27

VCC_24

VCC_23

VCC_21

VCC_20

VCC_22

VCC_13

VCC_14

VCC_12

VCC_16

VCC_15

VCC_17

VCC_18

VCC_19

VCC_11

VCC_10

VCC_9

VCC_8

VCC_7

VCC_4

VCC_5

VCC_6

VCC_2

VCC_3

VCC_0

VCC_1

(6 OF 10)

VCC

VCCAUX_NCTF57

VCCAUX_NCTF56

VCCAUX_NCTF55

VCCAUX_NCTF54

VCCAUX_NCTF53

VCCAUX_NCTF52

VCCAUX_NCTF51

VCCAUX_NCTF50

VCCAUX_NCTF49

VCCAUX_NCTF47 VCCAUX_NCTF48

VCCAUX_NCTF45

VCCAUX_NCTF44

VCCAUX_NCTF46

VCCAUX_NCTF40

VCCAUX_NCTF39

VCCAUX_NCTF37 VCCAUX_NCTF38

VCCAUX_NCTF36

VCCAUX_NCTF34 VCCAUX_NCTF35

VCCAUX_NCTF32 VCCAUX_NCTF33

VCCAUX_NCTF31

VCCAUX_NCTF30

VCCAUX_NCTF29

VCCAUX_NCTF27 VCCAUX_NCTF28

VCCAUX_NCTF26

VCCAUX_NCTF24 VCCAUX_NCTF25

VCCAUX_NCTF22

VCCAUX_NCTF21

VCCAUX_NCTF23

VCCAUX_NCTF42 VCCAUX_NCTF43

VCCAUX_NCTF41

VCCAUX_NCTF19 VCCAUX_NCTF20

VCCAUX_NCTF18

VCCAUX_NCTF17

VCCAUX_NCTF16

VCCAUX_NCTF14 VCCAUX_NCTF15

VCCAUX_NCTF13

VCCAUX_NCTF12

VCCAUX_NCTF11

VCCAUX_NCTF9

VCCAUX_NCTF10

VCCAUX_NCTF8

VCCAUX_NCTF7

VCCAUX_NCTF6

VCCAUX_NCTF5

VCCAUX_NCTF4

VCCAUX_NCTF3

VCCAUX_NCTF1

VCCAUX_NCTF0

VCCAUX_NCTF2

VSS_NCTF12

VSS_NCTF11

VSS_NCTF10

VSS_NCTF9

VSS_NCTF7 VSS_NCTF8

VSS_NCTF5 VSS_NCTF6

VSS_NCTF4

VSS_NCTF2 VSS_NCTF3

VSS_NCTF0 VSS_NCTF1

VCC_NCTF72

VCC_NCTF71

VCC_NCTF70

VCC_NCTF69

VCC_NCTF68

VCC_NCTF67

VCC_NCTF66

VCC_NCTF65

VCC_NCTF64

VCC_NCTF61 VCC_NCTF62 VCC_NCTF63

VCC_NCTF60

VCC_NCTF57 VCC_NCTF58 VCC_NCTF59

VCC_NCTF56

VCC_NCTF55

VCC_NCTF53 VCC_NCTF54

VCC_NCTF52

VCC_NCTF50 VCC_NCTF51

VCC_NCTF49

VCC_NCTF48

VCC_NCTF46 VCC_NCTF47

VCC_NCTF45

VCC_NCTF44

VCC_NCTF43

VCC_NCTF41

VCC_NCTF40

VCC_NCTF42

VCC_NCTF38 VCC_NCTF39

VCC_NCTF36 VCC_NCTF37

VCC_NCTF34 VCC_NCTF35

VCC_NCTF33

VCC_NCTF31 VCC_NCTF32

VCC_NCTF30

VCC_NCTF29

VCC_NCTF28

VCC_NCTF27

VCC_NCTF26

VCC_NCTF25

VCC_NCTF24

VCC_NCTF23

VCC_NCTF22

VCC_NCTF21

VCC_NCTF20

VCC_NCTF18 VCC_NCTF19

VCC_NCTF17

VCC_NCTF16

VCC_NCTF15

VCC_NCTF13 VCC_NCTF14

VCC_NCTF11 VCC_NCTF12

VCC_NCTF10

VCC_NCTF8 VCC_NCTF9

VCC_NCTF7

VCC_NCTF6

VCC_NCTF5

VCC_NCTF4

VCC_NCTF3

VCC_NCTF2

VCC_NCTF0 VCC_NCTF1

(7 OF 10)

NCTF

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

NCTF balls are Not Critical To Function

These connections can break without

impacting part performance.

Layout Note: Place near pin BA23

Place near pin BA15

Layout Note:

Layout Note: Place in cavity

1.05V or 1.5V

1.05V, External Graphics: 1500mA Max

1.5V, Internal Graphics: 5500mA Max

1.05V, Internal Graphics: 3500mA Max

667MTs 1700mA 3200mA

533MTs 1500mA 2800mA

400MTs 1300mA 2400mA

Speed 1 Channel 2 Channel

1.8V Max Current

OMIT

945GM

NB

BGA

U1200

AA33

W33

P32

M19

L19

N18

M18

L18

P17

N17

M17

N16

M16

N32

L16

M32

L32

J32

AA31

W31

V31

T31

R31

P33

P31

N31

M31

AA30

Y30

W30

V30

U30

T30

R30

N33

P30

N30

M30

L30

AA29

Y29

W29

V29

U29

R29

L33

P29

M29

L29

AB28

AA28

Y28

V28

U28

T28

R28

J33

P28

N28

M28

L28

P27

N27

M27

L27

P26

N26

AA32

L26

N25

M25

L25

P24

N24

M24

AB23

AA23

Y23

Y32

P23

N23

M23

L23

AC22

AB22

Y22

W22

P22

N22

W32

M22

L22

AC21

AA21

W21

N21

M21

L21

AC20

AB20

V32

Y20

W20

P20

N20

M20

L20

AB19

AA19

Y19

N19

AU41

AT41

AR34

AR6

AP6

AN6

AL6

AK6

AJ6

AV1

AJ1

BA30

AY30

AW30

AV30

AU30

AT30

AR30

AP30

AN30

AM41

AM30

AM29

AL29

AK29

AJ29

AH29

AJ28

AH28

AJ27

AH27

AU40

BA26

AY26

AW26

AV26

AU26

AT26

AR26

AJ26

AH26

AJ25

BA34

AH25

AJ24

AH24

BA23

AJ23

BA22

AY22

AW22

AV22

AU22

AY34

AT22

AR22

AP22

AK22

AJ22

AK21

AK20

BA19

AY19

AW19

AW34

AV19

AU19

AT19

AR19

AP19

AK19

AJ19

AJ18

AJ17

AH17

AV34

AJ16

AH16

BA15

AY15

AW15

AV15

AU15

AT15

AR15

AJ15

AU34

AJ14

AJ13

AH13

AK12

AJ12

AH12

AG12

AK11

BA8

AY8

AT34

AW8

AV8

AT8

AR8

AP8

BA6

AY6

AW6

AV6

AT6

10%

0.47UF

402

6.3V CERM-X5R

C1610

1

2

10uF

6.3V X5R

20%

603

C1621

1

2

603

20%

X5R

6.3V

10uF

C1620

1

2

OMIT

BGA

NB

945GM

U1200

AD27 AC27

AD26

AC26 AB26

AA26

Y26 W26

V26

U26 T26

R26

AB27

AD25 AC25

AB25 AA25

Y25

W25 V25

U25

T25 R25

AA27

AD24

AC24 AB24

AA24

Y24

W24

V24 U24

T24

R24

Y27

AD23

V23

U23 T23

R23

AD22

V22

U22 T22

R22

W27

AD21

V21

U21

T21 R21

AD20

V20

U20

T20 R20

V27

AD19

V19 U19

T19

AD18 AC18

AB18 AA18

Y18

W18

U27

V18

U18

T18

T27

R27

AG27

AF27

AG22 AF22

AG21

AF21 AG20

AF20 AG19

AF19

R19 AG18

AG26

AF18

R18 AG17

AF17

AE17 AD17

AB17 AA17

W17

V17

AF26

T17

R17

AG16 AF16

AE16

AD16 AC16

AB16 AA16

Y16

AG25

W16 V16

U16

T16 R16

AG15

AF15 AE15

AD15 AC15

AF25

AB15

AA15 Y15

W15

V15 U15

T15

R15

AG24

AF24 AG23

AF23

AE27 AE26

AC17

Y17 U17

AE25

AE24 AE23

AE22

AE21 AE20

AE19

AE18

CERM-X5R

6.3V

402

0.47UF

10%

C1611

1

2

10%

0.47UF

402

6.3V

CERM-X5R

C1612

1

2

10%

0.47UF

402

6.3V CERM-X5R

C1613

1

2

10%

0.47UF

402

6.3V

CERM-X5R

C1614

1

2

10%

0.47UF

402

6.3V CERM-X5R

C1615

1

2

16 87

06004051-7164

SYNC_MASTER=M59_MLB

SYNC_DATE=09/15/2006

NB Power 1

PP1V8_S3

NB_VCCSM_LF1

NB_VCCSM_LF2

NB_VCCSM_LF5

NB_VCCSM_LF4

PP1V05_S0

PP1V5_S0_NB

67D8

67D6

65A2

55A4

34C8

34C6

34B8

25D3

25C4

24D3

24C3

21C1

19D7

19D6

19D5

67C8

19D2

67C6

19D1

67B6

67B8

19C8

62A7

67B6

17D6

19D7

64C1

17D3

19D6

64A6

16D3

16C8

19D5

37B2

13B5

19D2

32C6

12C2

19D1

31C5

12B7

19C5

29D6

12A7

19C4

29D3

11C5

19C1

29B2

11B3

19B8

28D6

9B7

19B5

28D3

8C7

19A5

28B2

7D5

17C6

19D7

7B6

17B6

14C2

7B5

13D2

5D4

13C5

5B2

5D4

VTT0 VTT1 VTT2 VTT3 VTT4 VTT5 VTT6 VTT7 VTT8

VTT9 VTT10 VTT11 VTT12 VTT13

VTT15

VTT14

VTT16

VTT18

VTT17

VTT19 VTT20 VTT21 VTT22 VTT23 VTT24 VTT25

VTT27

VTT26

VTT28 VTT29

VTT31

VTT30

VTT32

VTT34

VTT33

VTT35 VTT36 VTT37

VTT39

VTT38

VTT40 VTT41 VTT42 VTT43 VTT44 VTT45

VTT48

VTT46 VTT47

VTT49 VTT50

VTT52

VTT51

VTT53

VTT55

VTT54

VTT57

VTT56

VTT58 VTT59 VTT60 VTT61 VTT62

VTT64

VTT63

VTT65 VTT66 VTT67

VTT69

VTT68

VTT70 VTT71

VTT73

VTT72

VTT74

VTT76

VTT75

VCCSYNC

VCC_TXLVDS0 VCC_TXLVDS1 VCC_TXLVDS2

VCC3G0 VCC3G1

VCC3G3

VCC3G2

VCC3G4

VCC3G6

VCC3G5

VCCA_3GPLL VCCA_3GBG VSSA_3GBG

VCCA_CRTDAC0 VCCA_CRTDAC1 VSSA_CRTDAC

VCCA_DPLLB

VCCA_DPLLA

VCCA_HPLL

VSSA_LVDS

VCCA_LVDS

VCCA_MPLL

VCCA_TVBG VSSA_TVBG

VCCA_TVDACC0 VCCA_TVDACC1 VCCA_TVDACB0 VCCA_TVDACB1 VCCA_TVDACA0 VCCA_TVDACA1

VCCD_HMPLL0 VCCD_HMPLL1

VCCD_LVDS2

VCCD_LVDS0 VCCD_LVDS1

VCCD_TVDAC

VCC_HV1 VCC_HV2

VCC_HV0

VCCD_QTVDAC

VCCAUX19

VCCAUX18

VCCAUX17

VCCAUX16

VCCAUX14 VCCAUX15

VCCAUX13

VCCAUX12

VCCAUX11

VCCAUX10

VCCAUX0 VCCAUX1 VCCAUX2 VCCAUX3 VCCAUX4

VCCAUX6

VCCAUX5

VCCAUX9

VCCAUX8

VCCAUX7

VCCAUX21

VCCAUX20

VCCAUX23 VCCAUX24

VCCAUX22

VCCAUX25 VCCAUX26

VCCAUX29

VCCAUX28

VCCAUX27

VCCAUX30 VCCAUX31

VCCAUX33

VCCAUX32

VCCAUX34 VCCAUX35 VCCAUX36

VCCAUX38

VCCAUX37

VCCAUX39 VCCAUX40

POWER

(8 OF 10)

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

1500mA Max VCC3G/3GPLL

800mA Max

2mA Max

60mA Max

70mA Max VCCA_CRTDAC/VCCSYNC

20mA Max

24mA Max

10mA Max

50mA Max 50mA Max

45mA Max

120mA Max

150mA Max

See VCCSYNC

40mA Max

1900mA Max

OMIT

BGA

NB

945GM

U1200

AJ41

AB41

Y41 V41

R41

N41 L41

A23 B23

B25

C30

B30

A30

G41

AC33

F21

E21

B26

C39

AF1

A38

AF2

H20

E19

F19

C20

D20

E20 F20

AK31 AF31

AE30

AD30 AC30

AG29

AF29 AE29

AD29

AC29 AG28

AF28

AE31

AE28

AH22

AJ21 AH21

AJ20

AH20 AH19

P19

P16

AH15

AC31

P15 AH14

AG14

AF14 AE14

Y14

AF13 AE13

AF12

AE12

AL30

AD12

AK30

AJ30 AH30

AG30 AF30

AH1

AH2

A28

B28

C28

H19

D21

H22

H41

G21

B39

G20

AC14

AB14

AD13 AC13

AB13 AA13

Y13

W13 V13

U13

T13 R13

W14

N13

M13 L13

AB12 AA12

Y12

W12 V12

U12

T12

V14

R12

P12

N12 M12

L12 R11

P11

N11 M11

R10

T14

P10 N10

M10

P9 N9

M9 R8

P8

N8 M8

R14

P7

N7 M7

R6

P6 M6

A6 R5

P5

N5

P14

M5

P4

N4 M4

R3

P3 N3

M3 R2

P2

N14

M2 D2

AB1

R1 P1

N1

M1

M14

L14

10%

0.47UF

6.3V

CERM-X5R

402

C1711

1

2

20%

0.22uF

6.3V

402

X5R

C1712

1

2

10%

0.47UF

CERM-X5R

6.3V

402

C1713

1

2

SYNC_DATE=09/15/2006

SYNC_MASTER=M59_MLB

NB Power 2

051-7164 06004

8717

PP1V5_S0_NB

PP1V05_S0

NB_VTTLF_CAP3

NB_VTTLF_CAP2 NB_VTTLF_CAP1

GND

PP2V5_S0

PP1V5_S0_NB_VCC3G

PP1V5_S0_NB_VCCA_3GPLL PP2V5_S0 GND

GND

PP1V5_S0_NB_VCCA_DPLLB

PP1V5_S0_NB_VCCA_DPLLA

PP1V5_S0_NB_VCCA_HPLL

GND

PP2V5_S0

PP1V5_S0_NB_VCCA_MPLL

PP1V5_S0_NB GND

PP1V5_S0_NB

PP3V3_S0

PP1V5_S0_NB

PP1V05_S0

82D5 82C6 82B3 82A4

79D3 79A8 71D2 67C5 67C3 67B3 67A3 66B6 66B5

66B1 65D6 65B3 62A6 61D8 61A5 60D4 60C7 58C7

58C4 57B6 54D4 54B5 52D3 49C7 49C4 49B5 40B6 36D6

34A8 33D8 33D3 33C7 29A6 29A3

67D8

28A6

67D8

67D6

27D8

67D6

65A2

27D5

65A2

55A4

27D3

55A4

34C8

27C3

34C8

34C6

26D1

34C6

34B8

26B8

34B8

25D3

26B6

25D3

25C4

26B4

25C4

24D3

25D8

24D3

24C3

25D3

24C3

21C1

25C6

21C1

19D7

25C4

19D7

67C8

19D6

67C8

25B8

67C8

19D6

67C6

19D5

67C6

25B4

67C6

19D5

67B6

19D2

67B6

25A4

67B6

19D2

62A7

19D1

62A7

24D3

62A7

19D1

19D7

19C8

19D7

24C3

19D7

19C8

19D6

17D6

19D6

24B5

19D6

17D3

19D5

16D3

82D3

19D5

24B3

19D5

16D3

19D2

16C8

82C5

82D3

19D2

23D5

19D2

16C8

19D1

13B5

67B6

82C5

19D1

23B3

19D1

13B5

19C5

12C2

67A8

67B6

19C5

22B5

19C5

12C2

19C4

12B7

67A6

67A8

19C4

21D3

19C4

12B7

19C1

12A7

66B5

67A6

19C1

21C3

19C1

12A7

19B8

11C5

63D1

66B5

19B8

20B4

19B8

11C5

19B5

11B3

19D7

63D1

19B5

20A4

19B5

11B3

19A5

9B7

19C5

19D7

19A5

19C7

19A5

9B7

17C6

8C7

19A8

19C5

17C6

19C6

17C6

8C7

17B6

7D5

19A6

19A8

17B6

14D6

17B6

7D5

16D1

7B6

19A4

19A6

16D1

14C7

16D1

7B6

13D2

7B5

17D6

19A4

13D2

10C5

13D2

7B5

13C5

5D4

17C6

34B2

17D6

13C5

5D4

13C5

5D4

5B2

5D4

19B3

5D4

19A6

19B6

5D4

19B6

5D4

5A4

5D4

5B2

VSS_1

VSS_0

VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7

VSS_9

VSS_8

VSS_10 VSS_11 VSS_12 VSS_13 VSS_14 VSS_15 VSS_16 VSS_17

VSS_19

VSS_18

VSS_20 VSS_21 VSS_22 VSS_23 VSS_24 VSS_25 VSS_26

VSS_28

VSS_27

VSS_29 VSS_30 VSS_31 VSS_32 VSS_33 VSS_34 VSS_35

VSS_37

VSS_36

VSS_39

VSS_38

VSS_40 VSS_41 VSS_42 VSS_43 VSS_44 VSS_45 VSS_46 VSS_47

VSS_49

VSS_48

VSS_50 VSS_51 VSS_52 VSS_53 VSS_54 VSS_55

VSS_57

VSS_56

VSS_59

VSS_58

VSS_61

VSS_60

VSS_64

VSS_63

VSS_62

VSS_65 VSS_66 VSS_67 VSS_68 VSS_69 VSS_70 VSS_71

VSS_73

VSS_72

VSS_74 VSS_75 VSS_76 VSS_77 VSS_78 VSS_79

VSS_82

VSS_80 VSS_81

VSS_84

VSS_83

VSS_85

VSS_87

VSS_86

VSS_89

VSS_88

VSS_91

VSS_90

VSS_92 VSS_93 VSS_94

VSS_96

VSS_95

VSS_97 VSS_98

VSS_99 VSS_100 VSS_101 VSS_102 VSS_103 VSS_104 VSS_105 VSS_106 VSS_107 VSS_108 VSS_109 VSS_110 VSS_111 VSS_112

VSS_114

VSS_113

VSS_115

VSS_117

VSS_116

VSS_118 VSS_119 VSS_120 VSS_121 VSS_122 VSS_123 VSS_124 VSS_125

VSS_127

VSS_126

VSS_128 VSS_129 VSS_130 VSS_131 VSS_132 VSS_133 VSS_134 VSS_135

VSS_137

VSS_136

VSS_138 VSS_139 VSS_140 VSS_141

VSS_143

VSS_142

VSS_144 VSS_145 VSS_146 VSS_147 VSS_148 VSS_149 VSS_150 VSS_151 VSS_152 VSS_153 VSS_154 VSS_155 VSS_156

VSS_158

VSS_157

VSS_159 VSS_160 VSS_161 VSS_162

VSS_164

VSS_163

VSS_165 VSS_166 VSS_167 VSS_168 VSS_169 VSS_170

VSS_172

VSS_171

VSS_173 VSS_174 VSS_175 VSS_176 VSS_177 VSS_178 VSS_179

VSS

(9 OF 10)

VSS_272

VSS_271

VSS_269 VSS_270

VSS_268

VSS_266 VSS_267

VSS_265

VSS_264

VSS_263

VSS_261 VSS_262

VSS_260

VSS_259

VSS_258

VSS_256 VSS_257

VSS_255

VSS_254

VSS_253

VSS_251 VSS_252

VSS_250

VSS_248 VSS_249

VSS_247

VSS_246

VSS_245

VSS_243 VSS_244

VSS_242

VSS_241

VSS_240

VSS_238 VSS_239

VSS_237

VSS_236

VSS_235

VSS_233 VSS_234

VSS_232

VSS_231

VSS_230

VSS_228 VSS_229

VSS_227

VSS_225 VSS_226

VSS_224

VSS_223

VSS_222

VSS_220 VSS_221

VSS_219

VSS_218

VSS_217

VSS_215 VSS_216

VSS_214

VSS_213

VSS_212

VSS_210 VSS_211

VSS_209

VSS_207 VSS_208

VSS_205 VSS_206

VSS_204

VSS_202 VSS_203

VSS_201

VSS_200

VSS_199

VSS_197 VSS_198

VSS_196

VSS_195

VSS_194

VSS_192 VSS_193

VSS_191

VSS_190

VSS_189

VSS_187 VSS_188

VSS_186

VSS_184 VSS_185

VSS_183

VSS_182

VSS_180 VSS_181

VSS_273 VSS_274

VSS_276

VSS_275

VSS_277

VSS_279

VSS_278

VSS_281

VSS_280

VSS_282 VSS_283 VSS_284

VSS_286

VSS_285

VSS_287 VSS_288 VSS_289

VSS_291

VSS_290

VSS_293

VSS_292

VSS_294

VSS_296

VSS_295

VSS_297

VSS_299

VSS_298

VSS_301 VSS_302

VSS_300

VSS_304

VSS_303

VSS_305 VSS_306 VSS_307

VSS_309

VSS_308

VSS_311

VSS_310

VSS_312 VSS_313 VSS_314 VSS_315

VSS_317

VSS_316

VSS_318 VSS_319 VSS_320

VSS_322

VSS_321

VSS_323 VSS_324 VSS_325

VSS_327

VSS_326

VSS_328 VSS_329 VSS_330

VSS_332

VSS_331

VSS_334

VSS_333

VSS_335

VSS_337

VSS_336

VSS_338 VSS_339 VSS_340

VSS_342 VSS_343

VSS_341

VSS_345

VSS_344

VSS_346 VSS_347 VSS_348

VSS_350

VSS_349

VSS_352

VSS_351

VSS_353 VSS_354 VSS_355 VSS_356 VSS_357 VSS_358 VSS_359 VSS_360

VSS

(10 OF 10)

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

OMIT

BGA

945GM

NB

U1200

AC41

AA41

AN40

AE34

AC34 C34

AW33

AV33 AR33

AE33

AB33 Y33

V33

AK40

T33 R33

M33 H33

G33

F33 D33

B33

AH32 AG32

AJ40

AF32

AE32 AC32

AB32 G32

B32

AY31 AV31

AN31

AJ31

AH40

AG31

AB31

Y31 AB30

E30 AT29

AN29

AB29 T29

N29

AG40

K29 G29

E29

C29 B29

A29 BA28

AW28

AU28 AP28

AF40

AM28

AD28 AC28

W28

J28 E28

AP27 AM27

AK27

J27

AE40

G27

F27

C27 B27

AN26

M26 K26

F26 D26

AK25

B40

P25 K25

H25

E25 D25

A25

BA24 AU24

AL24 AW23

AY39 AW39

W41

AV39

AR39 AN39

AJ39

AC39 AB39

AA39

Y39

W39

V39

T41

T39

R39

P39 N39

M39

L39 J39

H39 G39

F39

P41

D39 AT38

AM38

AH38 AG38

AF38

AE38

C38

AK37 AH37

M41

AB37

AA37

Y37

W37

V37

T37

R37

P37

N37

M37

J41

L37

J37

H37

G37

F37

D37 AY36

AW36

AN36 AH36

F41

AG36 AF36

AE36

AC36

C36

B36

BA35 AV35

AR35

AH35

AV40

AB35

AA35

Y35

W35

V35

T35

R35

P35

N35

M35

AP40

L35

J35

H35

G35

F35

D35 AN34

AK34

AG34

AF34

OMIT

BGA

945GM

NB

U1200

AT23 AN23

AM23 AH23

AC23

W23 K23

J23

F23 C23

AA22

K22 G22

F22 E22

D22

A22 BA21

AV21

AR21 AN21

AL21

AB21

Y21

P21

K21

J21

H21

C21

AW20

AR20 AM20

AA20

K20

B20

A20 AN19

AC19

W19

K19

G19

C19 AH18

P18

H18

D18

A18 AY17

AR17

AP17 AM17

AK17

AV16 AN16

AL16

J16

F16

C16 AN15

AM15

AK15

N15

M15

L15

B15

A15

BA14 AT14

AK14 AD14

AA14

U14

K14

H14

E14 AV13

AR13

AN13 AM13

AL13 AG13

P13

F13

D13

B13

AY12 AC12

K12

H12

E12

AD11 AA11

Y11

J11 D11

B11 AV10

AP10

AL10 AJ10

AG10

AC10 W10

U10

BA9 AW9

AR9 AH9

AB9

Y9 R9

G9

E9 A9

AG8

AD8 AA8

U8 K8

C8

BA7 AV7

AP7

AL7 AJ7

AH7

AF7 AC7

R7 G7

D7

AG6 AD6

AB6

Y6 U6

N6

K6 H6

B6 AV5

AF5

AD5 AY4

AR4

AP4 AL4

AJ4

Y4 U4

R4 J4

F4

C4 AY3

AW3

AV3 AL3

AH3

AG3 AF3

AD3 AC3

AA3

G3 AT2

AR2

AP2 AK2

AJ2

AD2 AB2

Y2 U2

T2

N2 J2

H2

F2 C2

AL1

18 87

06004051-7164

NB Grounds

SYNC_MASTER=M59_MLB

SYNC_DATE=09/15/2006

IN

IN IN

NR/FB

IN

EN

OUT

GND

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

800mA Max

These are the power signals that leave the NB "block"

Power Interface

40mA Max

MCH VCC_HV BYPASS (MCH HV BUFFER 3.3V PWR)

Layout Note: Route to caps, then GND

(MCH MEMORY PLL 1.5V PWR)

1500mA Max

1500mA Max 10mA Max?

GMCH CORE PWR 1.05V BYPASS

1900mA Max

3200mA Max

(MCH TVDAC DEDICATED PWR 1.5V)

(MCH TVDAC DIGITAL QUIET 1.5V PWR)

(MCH TV OUT CHANNEL A 3.3V PWR)

(MCH TV OUT CHANNEL B 3.3V PWR)

(MCH TV DAC BAND GAP 3.3V PWR)

(MCH TV OUT CHANNEL C 3.3V PWR)

(MCH CRTDAC ANALOG 2.5V PWR)

(MCH H/V SYNC 2.5V PWR)

Rail Totals:

2310mA Max?

?mA Max

?mA Max 100mA Max

800mA Max

3674mA Max

40mA Max

40mA Max?

2mA Max

150mA Max

3200mA Max

1500mA Max

24mA Max

70mA Max

?mA Max

Layout Note: Route to caps, then GND

10MA MAX

(MCH LVDS ANALOG 2.5V PWR)

MCH VCCA_LVDS BYPASS

132mA Max

?mA Max

60mA Max

GMCH VCC3G FILTER (PCI-E/DMI ANALOG 1.5V PWR)

1500mA Max

(3GIO PLL 1.5V PWR)

GMCH VCCA_3GPLL FILTER

Layout Note:

be close to MCH

10uF caps should

on opposite side.

(MCH DDR DLL&IO, FSB HSIO&IO PWR 1.5V)

GMCH VCCAUX FILTER

1900mA Max

(MCH PCIE/DMI BAND GAP 2.5V PWR)

2mA Max

MCH VCCA_3GBG BYPASS

be placed in cavity

3GPLL 10uF cap should

Layout Note:

Layout Note: Place L and C close to MCH

Place on the edge

Layout Note:

(SHARE C0940 470UF)

45mA Max

GMCH VCCA_HPLL FILTER (HOST PLL 1.5V PWR)

GMCH VCCA_MPLL FILTER

MCH VTT BYPASS (MCH FSB 1.05V PWR)

Layout Note: Place in cavity

100mA Max

(MCH LVDS DIGITAL 1.5V PWR)

MCH VCCD_LVDS BYPASS

20MA MAX

GMCH VCCA_DPLLA FILTER

50MA MAX

(CRT/TVOUT PLL 1.5V PWR)

GMCH VCCA_DPLLB FILTER (LVDS PLL 1.5V PWR)

1500mA Max

60MA MAX

(MCH LVDS TRANSMITTER 2.5V PWR)

MCH VCC_TXLVDS BYPASS

402

20%

6.3V X5R

0.22uF

C1907

1

2

10uF

6.3V

20%

603

X5R

C1972

1

2

6.3V

20%

402

X5R

0.22uF

C1967

1

2

6.3V

603

2.2uF

20% CERM1

C1966

1

2

6.3V

20%

603

CERM

4.7uF

C1965

1

2

20%

2.5V TANT D2T

470uF

CRITICAL

C1900

1

23

1210

91nH

L1970

1 2

0.1uF

402

20% 10V

CERM

C1916

1

2

0.22uF

X5R 402

20%

6.3V

C1906

1

2

0.1uF

CERM 402

20% 10V

C1991

1

2

4.7UF

6.3V

20%

603

CERM

C1990

1

2

10V

20%

402

CERM

0.1uF

C1993

1

2

10uF

X5R 603

20%

6.3V

C1992

1

2

0.1uF

CERM 402

20% 10V

C1995

1

2

20% 16V

CERM

402

0.01UF

C1994

1

2

20%

10uF

6.3V X5R 603

C1952

1

2

402

MF-LF

1/16W

1%

1.5K

R1990

1

2

SOT23-5

TPS73115

CRITICAL

U1900

3

2

1

4

5

402

CERM

1uF

10%

6.3V

C1950

1

2

402

CERM

0.01uF

10% 16V

C1951

1

2

402

MF-LF

1/16W

5%

0

R1954

1 2

402

MF-LF

1/16W

5%

0

NO STUFF

R1953

1 2

0.1uF

402

10V

20%

NO STUFF

CERM

C1953

1

2

10V

20%

402

CERM

0.1uF

C1915

1

2

0.1uF

402

CERM

10V

20%

C1954

1

2

CASE-B2

220UF

20%

2.5V POLY

C1970

1

2

20%

6.3V

603

X5R

10uF

C1914

1

2

402

0.22uF

X5R

20%

6.3V

C1905

1

2

20% 10V

402

CERM

0.1uF

C1935

1

2

FERR-120-OHM-0.2A

0603

L1934

1 2

402

CERM

20%

0.1uF

10V

C1937

1

2

10% CERM

1uF

6.3V 402

C1904

1

2

0603

FERR-120-OHM-0.2A

L1936

1 2

22UF

CERM

805

20%

6.3V

C1934

1

2

22UF

CERM

805

20%

6.3V

C1936

1

2

603

10uF

20% X5R

6.3V

C1903

1

2

10uF

603

20%

6.3V X5R

C1902

1

2

0.1uF

10V

20%

402

CERM

C1918

1

2

0.1uF

CERM 402

20% 10V

C1976

1

2

0805

1.0UH-220MA-0.12-OHM

L1975

1 2

10uF

X5R 603

20%

6.3V

C1975

1

2

1%

1/16W

0.51

402

MF-LF

R1975

1 2

6.3V

20%

603

X5R

10uF

C1971

1

2

19 87

06004051-7164

SYNC_MASTER=M57_MLB_MG

SYNC_DATE=08/08/2006

NB (GM) Decoupling

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

PP1V5_S0_NB_VCC3G

VOLTAGE=1.5V

PP2V5_S0

TPS73115_NR

VOLTAGE=1.5V

MIN_LINE_WIDTH=0.38 mm MIN_NECK_WIDTH=0.25 mm

PP1V5_S0_NB_VCCA_DPLLB

PP2V5_S0

VOLTAGE=1.5V

MIN_LINE_WIDTH=0.38 mm MIN_NECK_WIDTH=0.25 mm

PP1V5_S0_NB_DPLL

MIN_LINE_WIDTH=0.38 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=1.5V

PP1V5_S0_NB_VCCA_DPLLA

PP2V5_S0

PP1V5_S0_NB

MIN_NECK_WIDTH=0.4 mm

MIN_LINE_WIDTH=0.6 mm

PP1V5_S0_NB_3GPLL_F

VOLTAGE=1.5V

PP1V5_S0_NB_VCCA_MPLL

MIN_LINE_WIDTH=0.38 mm MIN_NECK_WIDTH=0.25 mm

PP1V5_S0_NB_VCCA_HPLL

VOLTAGE=1.5V

MIN_LINE_WIDTH=0.38 mm MIN_NECK_WIDTH=0.25 mm

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

VOLTAGE=1.5V

PP1V5_S0_NB_VCCA_3GPLL

PP1V5_S0_NB

PP1V05_S0

PP2V5_S0

GND

LVDS_IBG

GND

TP_CRT_DDC_DATA

MAKE_BASE=TRUE

TP_SDVO_CTRLDATA TP_SDVO_CTRLDATA

MAKE_BASE=TRUE

TP_SDVO_CTRLCLK TP_SDVO_CTRLCLK

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_NB_XOR_LVDS_D28 NC_NB_XOR_LVDS_D28

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_NB_XOR_LVDS_D27 NC_NB_XOR_LVDS_D27

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_NB_XOR_LVDS_A34 NC_NB_XOR_LVDS_A34

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_NB_XOR_LVDS_A35 NC_NB_XOR_LVDS_A35

MAKE_BASE=TRUE

TP_LVDS_CLKCTLB TP_LVDS_CLKCTLB

MAKE_BASE=TRUE

TP_LVDS_CLKCTLA TP_LVDS_CLKCTLA

PP1V5_S0_NB PP1V5_S0_NB

PP1V5_S0_NB

PP1V05_S0

PP1V5_S0_NB

PP1V05_S0

PP3V3_S0 PP3V3_S0

PP1V5_S0_NB

MAKE_BASE=TRUE

TP_CRT_DDC_CLK TP_CRT_DDC_CLK

PP1V05_S0

PP1V5_S0_NB

GND

PP1V5_S0_NB

PP1V05_S0

PP1V5_S0_NB

GND

PP1V05_S0

GND

PP1V5_S0_NB

GND

PP1V5_S0_NB

MAKE_BASE=TRUE

TP_CRT_DDC_DATA

PP1V5_S0_NB

GND

PP3V3_S0

PP1V05_S0

PP2V5_S0

GND

PP1V8_S3

PP1V5_S0_NB

PP1V05_S0

PP1V5_S0_NB

PP1V05_S0

82D5 82C6

82D5

82B3

82C6

82A4

82B3

79D3

82A4

79A8

79D3

71D2

79A8

67C5

71D2

67C3

67C5

67B3

67C3

67A3

67B3

66B6

67A3

66B5

66B6

66B1

66B5

65D6

66B1

65B3

65D6

62A6

65B3

61D8

62A6

61A5

61D8

60D4

61A5

60C7

60D4

58C7

60C7

58C4

58C7

57B6

58C4

54D4

57B6

54B5

54D4

52D3

54B5

49C7

52D3

49C4

49C7

49B5

49C4

40B6

49B5

36D6

40B6

34A8

36D6

33D8

34A8

33D3

33D8

33C7

33D3

29A6

33C7

29A3

29A6

67D8

28A6

67D8

29A3

67D8

67D6

27D8

67D6

67D8

28A6

67D6

65A2

27D5

65A2

67D6

27D8

65A2

55A4

27D3

55A4

65A2

27D5

55A4

34C8

27C3

34C8

55A4

27D3

34C8

34C6

26D1

34C6

34C8

27C3

34C6

34B8

26B8

34B8

34C6

26D1

34B8

25D3

26B6

25D3

34B8

26B8

25D3

25C4

26B4

25C4

25D3

26B6

25C4

24D3

25D8

24D3

25C4

26B4

24D3

24C3

25D3

24C3

24D3

25D8

24C3

21C1

25C6

21C1

24C3

25D3

21C1

19D7

25C4

19D7

21C1

25C6

19D7

19D6

25B8

19D6

19D7

25C4

19D6

67C8

19D5

67C8

19D5

67C8

25B4

67C8

19D5

67C8

19D6

67C8

25B8

19D5

67C8

19D5

67C8

19D5

67C8

67C6

67C8

19D2

67C6

67C8

19D2

67C6

25A4

67C6

19D2

67C6

19D5

67C8

19D5

67C6

67C8

25B4

19D2

67C6

19D2

67C6

19D2

67C6

67B6

67C6

19D1

67B6

67C6

19D1

67B6

24D3

67B6

19D1

67B6

19D1

67C6

19D2

67B6

67C6

25A4

19D1

67B6

19D1

67B6

19D1

67B6

62A7

67B6

19C8

62A7

67B6

19C8

62A7

24C3

62A7

19C8

62A7

19C8

67B6

19C8

62A7

67B6

24D3

19C8

62A7

19C8

62A7

19C8

62A7

19D7

62A7

17D6

19D7

62A7

17D6

19D7

24B5

19D7

17D6

19D7

17D6

62A7

17D6

19D7

62A7

24C3

17D6

19D7

17D6

19D7

17D6

19D7

19D6

19D7

17D3

19D6

19D7

17D3

19D6

24B3

19D6

17D3

19D6

17D3

19D7

17D3

19D6

19D7

24B5

17D3

19D6

17D3

19D6

17D3

19D6

19D5

19D6

16D3

19D5

16D3

19D5

23D5

19D5

16D3

19D5

16D3

19D6

16D3

19D5

19D6

24B3

16D3

82D3

19D5

16D3

19D5

16D3

82D3

19D5

19D2

19D5

16C8

82D3

19D2

16C8

19D2

23B3

19D2

16C8

19D2

16C8

19D5

16C8

19D2

19D5

23D5

16C8

82C5

19D2

16C8

19D2

16C8

82C5

19D2

19D1

19D2

13B5

82C5

19D1

13B5

19D1

22B5

19D1

13B5

19D1

13B5

19D1

13B5

19D1

19D2

23B3

13B5

67B6

19D1

13B5

19D1

13B5

67B6

19D1

19C5

19D1

12C2

67B6

19C5

12C2

19C5

21D3

19C5

12C2

19C5

12C2

19C5

12C2

19C5

19D1

22B5

12C2

67A8

19C5

12C2

19C5

12C2

67A8

19C5

19C4

19C5

12B7

67A8

19C4

12B7

19C4

21C3

19C4

12B7

19C4

12B7

19C4

12B7

19C4

19C5

21D3

12B7

67A6

19C4

12B7

19C4

12B7

67A6

19C4

19C1

12A7

67A6

19C1

12A7

19C1

20B4

19C1

12A7

19C1

12A7

19C1

12A7

19C1

19C4

21C3

12A7

66B5

19C1

12A7

19C1

12A7

66B5

19C1

19B8

11C5

66B5

19B8

11C5

19B8

20A4

19B8

11C5

19B8

11C5

19B8

11C5

19B8

19C1

20B4

11C5

63D1

19B8

11C5

19B8

11C5

63D1

19B8

19B5

11B3

63D1

19B5

11B3

19B5

19C7

19B5

11B3

19B5

11B3

19B5

11B3

19B5

20A4

11B3

19D7

19B5

11B3

19B5

11B3

19D7

19B5

19A5

9B7

19D7

19A5

9B7

19A5

19C6

19A5

9B7

19A5

9B7

19A5

9B7

19A5

19C7

9B7

19C5

19A5

9B7

19A5

9B7

19C5

19A8

17C6

8C7

19C5

17C6

8C7

17C6

8C7

17C6

8C7

17C6

8C7

17C6

8C7

19A8

17C6

8C7

17C6

8C7

19A6

19A8

19A6

17B6

7D5

19A8

17B6

7D5

17B6

14D6

17B6

7D5

17B6

7D5

17B6

7D5

17B6

14D6

7D5

19A6

17B6

7D5

17B6

7D5

19A4 19A4

19A4

16D1

7B6

19A6

16D1

7B6

16D1

14C7

16D1

7B6

16D1

7B6

16D1

7B6

16D1

14C7

7B6

19A4

16D1

7B6

16D1

7B6

17D6

13D2

7B5

17D6

13D2

7B5

13D2

10C5

13D2

7B5

13D2

7B5

13D2

7B5

13D2

10C5

7B5

17D6

13D2

7B5

13D2

7B5

17C6 17C6

34B2

17C6

13C5

5D4

17C6

19D6

19D3 19D4

13C5

5D4

13C5

5D4

13C5

19D5 19D6

5D4

13C5

5D4

13C5

5D4

13C5

19D5

13C5

5D4

17C6

13C5

5D4

13C5

5D4

17D6

5D4

17C6

5D4

17C6

5D4

17C6

17D6

5D4

5B2

5D4

13D5

13B5

14B6 14B6

14C6 14C6

13D5 13D5

5D4

5B2

5D4

5A4

5D4

13B5 13B5

5B2

5D4

5B2

5D4

5B2

5D4

13B5

5D4

5A4

5B2

5D4

5B2

5D4

5B2

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

Internal pull-ups

Internal pull-up

RESERVED

NB_CFG<11>

NB_CFG<10>

High = Mobile CPU

NB_CFG<7>

RESERVED

Internal pull-up

DMI x2 Select

PROBABLY NOT NEEDED

Lane Reversal

NB_CFG<4>

NB_CFG<3>

RESERVED

NB_CFG<13:12>

NB_CFG<14>

NB_CFG<5>

NB_CFG<15>

NB_CFG<16>

NB_CFG<6>

NB_CFG<17>

NB_CFG<18>

NB_CFG<8>

NB_CFG<9>

NB_CFG<19>

NB_CFG<20>

Low = DMIx2

High = DMIx4

Low = RESERVED

High = Normal

PCIE Graphics

RESERVED

CPU Strap

RESERVED

Low = Reversed

Internal pull-up

11 = Normal Operation

10 = All-Z Mode Enabled

01 = XOR Mode Enabled

00 = Partial Clock Gating Disable

RESERVED

Internal pull-up

RESERVED

High = Enabled

Low = Disabled

RESERVED

FSB Dynamic ODT

or PCIe x1

Low = Only SDVO

High = Both active

945 External Design Spec says reserved

Internal pull-down

Low = 1.05V

High = 1.5V

Low = Normal

High = Reversed DMI Lane Reversal

VCC Select

Interop. Mode

PCIe Backward

402

5%

2.2K

1/16W MF-LF

NBCFG_DMI_X2

R2075

1

2

5%

2.2K

1/16W MF-LF 402

NBCFG_DYN_ODT_DISABLE

R2085

1

2

402

1/16W

5%

2.2K

NBCFG_VCC_1V5

MF-LF

R2058

1

2

402

MF-LF

1/16W

5%

2.2K

NBCFG_DMI_REVERSE

R2059

1

2

NBCFG_SDVO_AND_PCIE

402

MF-LF

1/16W

5%

2.2K

R2060

1

2

NO STUFF

2.2K

5% 1/16W MF-LF 402

R2077

1

2

402

MF-LF

1/16W

5%

2.2K

NBCFG_PEG_REVERSE

R2079

1

2

20 87

06004051-7164

NB Config Straps

SYNC_MASTER=M59_MLB

SYNC_DATE=09/15/2006

PP3V3_S0

NB_CFG<18>

NB_CFG<19>

NB_CFG<20>

NB_CFG<16>

NB_CFG<5>

NB_CFG<9>

NB_CFG<7>

82D5

82C6

82D5

82B3

82C6

82A4

82B3

79D3

82A4

79A8

79D3

71D2

79A8

67C5

71D2

67C3

67C5

67B3

67C3

67A3

67B3

66B6

67A3

66B5

66B6

66B1

66B5

65D6

66B1

65B3

65D6

62A6

65B3

61D8

62A6

61A5

61D8

60D4

61A5

60C7

60D4

58C7

60C7

58C4

58C7

57B6

58C4

54D4

57B6

54B5

54D4

52D3

54B5

49C7

52D3

49C4

49C7

49B5

49C4

40B6

49B5

36D6

40B6

34A8

36D6

33D8

34A8

33D3

33D8

33C7

33D3

29A6

33C7

29A3

29A6

28A6

29A3

27D8

28A6

27D5

27D8

27D3

27D5

27C3

27D3

26D1

27C3

26B8

26D1

26B6

26B8

26B4

26B6

25D8

26B4

25D3

25D8

25C6

25D3

25C4

25C6

25B8

25C4

25B4

25B8

25A4

25B4

24D3

25A4

24C3

24D3

24B5

24C3

24B3

24B5

23D5

24B3

23B3

23D5

22B5

23B3

21D3

22B5

21C3

21D3

20B4

21C3

20A4

20B4

19C7

19C6

17C6

14D6

14C7

10C5

5D4

5A4

14C6

14B6

14C6

IO

IN

OUT

IN

OUT

IN

IO

IO IO

IO

IN

IO

DDACK*

SATARBIASN SATARBIASP

SATA_CLKN SATA_CLKP

SATA_2TXP

SATA_2TXN

SATA_2RXN SATA_2RXP

SATA_0TXP

SATA_0TXN

SATA_0RXP

SATA_0RXN

SATALED*

ACZ_SDOUT

ACZ_SDIN1 ACZ_SDIN2

ACZ_SDIN0

ACZ_SYNC

ACZ_BIT_CLK

LAN_TXD2

LAN_TXD0 LAN_TXD1

LAN_RXD1 LAN_RXD2

LAN_RSTSYNC

LAN_RXD0

LAN_CLK

EE_SHCLK

EE_CS

INTVRMEN

INTRUDER*

RTCRST*

RTCX2

RTCX1

THRMTRIP*

STPCLK*

NMI

SMI*

RCIN*

INTR

INIT*

INIT3_3V*

IGNNE*

GPIO49/CPUPWRGD

FERR*

TP1/DPRSTP*

TP2/DPSLP*

A20M*

CPUSPL*

A20GATE

LFRAME*

LDRQ1*/GPIO23

LDRQ0*

LAD3

LAD2

LAD0 LAD1

EE_DOUT EE_DIN

ACZ_RST*

DIOR*

IDEIRQ

DIOW*

IORDY DDREQ

DD0 DD1

DD3

DD2

DD5

DD4

DD6 DD7 DD8

DD11

DD9

DD10

DD12 DD13 DD14 DD15

DA0 DA1 DA2

DCS3*

DCS1*

AC-97/

AZALIA

RTC

LPC

LAN

CPU

IDE

SATA

(1 OF 6)

OUT

IN

OUT

IN IN

IN

OUT

IN

OUT

IN IN

IN

OUT

IO

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

(WEAK INT PU)

NOTE: ALL IDE PINS HAVE INTERNAL 33-OHM SERIES R’S

LAYOUT NOTE: PLACE R2101 & R2194 WHERE ACCESSIBLE

NOTE: DDREQ HAS INTERNAL 11.5K PD

NOTE: LAD<0-3> HAVE INTERNAL 20K PU

INTEL HIGH DEFINITION AUDIO

ACZ_SDOUT

ACZ_SYNC

ACZ_BIT_CLK

ACZ_RST#

ACZ_SDIN[0-2]

INTERNAL 20K PD ENABLED WHEN

INTERNAL 20K PD

AC ’07

- LSO BIT IN AC’97 GLOBAL CONTROL REG = 1; OR

- BOTH FUNCTION 2 & 3 OF DEVICE 30 ARE DISABLED

- LSO BIT IN AC’97 GLOBAL CONTROL REG = 1; OR

- BOTH FUNCTION 2 & 3 OF DEVICE 30 ARE DISABLED

INTERNAL 20K PD ENABLED DURING RESET AND WHEN

INTERNAL 20K PD

INTERNAL 20K PD ENABLED WHEN

- LSO BIT IN AC’97 GLOBAL CONTROL REG = 1; OR

NONE

INTERNAL 20K PD

INTERNAL 20K PD ONLY ENABLED IN S3COLD

NOTE: ENABLE INTERNAL 1.05V SUSPEND REG

NOTE: DD<7> HAS INTERNAL 11.5K PD

(HSTROBE) (STOP)

20K PD

(DSTROBE)

< 2 IN OF R2107 W/O STUB

LAYOUT NOTE: R2108 TO BE

CHANGED TO 54.9 FOR

LAYOUT NOTE: R2107 TO BE

< 2 IN OF SB

BOM CONSOLIDATION

NOTE: RISING-EDGE TRIGGERED AT CPU

NOTE: KEYBOARD CONTROLLER RESET CPU

POR IS SMC WILL PUT LAN INT’F

NOTE:

INTO RESET STATE TO SAVE PWR.

- BOTH FUNCTION 2 & 3 OF DEVICE 30 ARE DISABLED

INTEL CONFIRMS OK TO LEAVE PINS AS NC

NOTE: LDRQ<0-1># HAVE INTERNAL 20K PU

NOTE: PULLED UP PER INTEL

NOTE: R2110=56 IN CV. CHANGED TO 54.9 FOR BOM CONSOLIDATION

NOTE: R2108=56 IN CV.

(WEAK INT PD)

(INT PU)

NOTE: EE_CS HAS INTERNAL PD, ONLY ENABLED WHEN LAN_RST#=L

402

5%

0

MF-LF 1/16W

NOSTUFF

R2100

1 2

MF-LF

1/16W

5%

2.2K

402

NOSTUFF

R2101

1 2

1/16W

402

39

5%

MF-LF

R2195

1 2

39

R2198

1 2

39

R2197

1 2

39

R2196

1 2

MF-LF

1/16W

5%

10K

402

R2199

1

2

OMIT

ICH7-M

SB

BGA

U2100

AE22 AH28

U1

R5 T2 T3 T1

T4

R6

AG27

AH17 AE17 AF17

AE16 AD16

AB15 AE14

AB13 AC14 AF14 AH13 AH14 AC15

AG13 AF13 AD14 AC13 AD12 AC12 AE12 AF12

AF16

AE15

AF15 AH15

W1

W3

Y2

Y1

AG26

AG24

AH16

AG22

AF22

AG21

AF25

Y5 W4

AG16

AA6 AB5 AC4 Y6

V3

U3

U5 V4 T5

U7 V6 V7

AC3 AA5

AB3

AH24

AG23

AA3

AB1 AB2

AF3 AE3 AG2 AH2

AF7 AE7 AG6 AH6

AF1 AE1

AF18

AH10 AG10

AF23

AH22

AF26

AF24 AH25

MF-LF

1/16W

5%

10K

402

R2194

1

2

MF-LF

1/16W

1%

402

332K

R2105

1

2

402

1%

1/16W

MF-LF

24.9

R2107

1 2

54.9

1%

1/16W

MF-LF

402

R2108

1

2

1%

54.9

402

1/16W

MF-LF

R2110

1 2

SYNC_DATE=09/15/2006

SYNC_MASTER=M59_MLB

SB: 1 OF 4

051-7164

8721

06004

TP_SB_XOR_V7

TP_SB_XOR_V6

TP_SB_XOR_U7

TP_SB_XOR_Y2

TP_SB_XOR_Y1

TP_SB_XOR_W1

SB_INTVRMEN

PP1V05_S0

CPU_FERR_L

SB_A20GATE

CPU_RCIN_L

SATA_C_D2R_P

IDE_PDDACK_L

SATA_RBIAS SATA_RBIAS

SB_CLK100M_SATA_N SB_CLK100M_SATA_P

SATA_C_R2D_C_P

SATA_C_R2D_C_N

SATA_C_D2R_N

TP_SATA_A_R2DP

TP_SATA_A_R2DN

TP_SATA_A_D2RP

TP_SATA_A_D2RN

TP_SB_SATALED_L

SB_ACZ_SDATAOUT

TP_SB_ACZ_SDIN1 TP_SB_ACZ_SDIN2

ACZ_SDATAIN<0>

SB_ACZ_SYNC

SB_ACZ_BITCLK

SB_SM_INTRUDER_L

SB_RTC_X1

CPU_THERMTRIP_R

CPU_STPCLK_L

CPU_NMI

CPU_SMI_L

CPU_INTR

CPU_INIT_L

FWH_INIT_L

CPU_IGNNE_L

CPU_PWRGD

CPU_DPRSTP_L

CPU_DPSLP_L

CPU_A20M_L

TP_CPU_CPUSLP_L

SB_ACZ_RST_L

IDE_PDIOR_L

IDE_IRQ14

IDE_PDIOW_L

IDE_PDIORDY IDE_PDDREQ

IDE_PDD<0> IDE_PDD<1>

IDE_PDD<5>

IDE_PDD<4>

IDE_PDD<7> IDE_PDD<8>

IDE_PDD<11>

IDE_PDD<9> IDE_PDD<10>

IDE_PDD<12> IDE_PDD<13> IDE_PDD<14> IDE_PDD<15>

IDE_PDA<0> IDE_PDA<1> IDE_PDA<2>

IDE_PDCS3_L

IDE_PDCS1_L

ACZ_SYNC

SMC_RCIN_L

PP1V05_S0

PM_THRMTRIP_L

ACZ_SDATAOUT

IDE_PDD<6>

PP3V3_S0

LPC_AD<0> LPC_AD<1> LPC_AD<2> LPC_AD<3>

TP_SB_DRQ0_L LVDS_MUX_SEL_GPU

LPC_FRAME_L

SB_RTC_X2

SB_RTC_RST_L

ACZ_BITCLK

ACZ_RST_L

PP3V3_G3C_SB_RTC_D

TP_SB_XOR_U3

TP_SB_XOR_U5 TP_SB_XOR_V4 TP_SB_XOR_T5

TP_SB_XOR_W3

TP_SB_XOR_V3

IDE_PDD<2> IDE_PDD<3>

82D5

82C6

82B3

82A4

79D3

79A8

71D2

67C5

67C3

67B3

67A3

66B6

66B5

66B1

65D6

65B3

62A6

61D8

61A5

60D4

60C7

58C7

58C4

57B6

54D4

54B5

52D3

49C7

49C4

49B5

40B6

36D6

34A8

33D8

33D3

33C7

29A6

67D8

67D8 29A3

29A3

67D6

67D6 28A6

28A6

65A2

65A2 27D8

27D8

55A4

55A4 27D5

27D5

34C8

27D3

34C6

27C3

34B8

26D1

25D3

25D3 26B8

26B8

25C4

25C4 26B6

26B6

24D3

24D3 26B4

26B4

24C3

24C3 25D8

25D8

21C1

21C1 25D3

25D3

19D7

19D7 25C6

25C6

19D6

19D6 25C4

25C4

19D5

25B8

19D2

25B4

19D1

19D1 25A4

25A4

19C8

19C8 24D3

24D3

17D6

17D6 24C3

24C3

17D3

17D3 24B5

24B5

16D3

16D3 24B3

24B3

16C8

16C8 23D5

23D5

13B5

13B5 23B3

23B3

12C2

12C2 22B5

22B5

12B7

21D3

21C3

12A7

12A7 20B4

20B4

11C5

11C5 20A4

20A4

11B3

11B3 19C7

19C7

9B7

19C6

8C7

17C6

7D5

53C5

7D5

14D6

7B6

34C5

52D5

7B6

14C7

60C6

26D4

7B5

36A5

34C3

87B4

87C6

52D3

87C6

61C7

87C6

87B4

7B5

52C1

87B4

10C5

53C4

53C5

53C4

87B4

26D3

5D4

36A4

33B4

36A5

48B3

7C8

87C6

51D5

87C6

7B3

87C6

48B3

5D4

14B6

48B3

5D4

51D7

51C7

26D4

48B3

25A4

5B2

7C8

81A7

36C4

21B6

5A7

81B7

81A7

36A4

87B4

5C1

87B4

26D4

26C8

5B4

5C4

7C8

7D6

5C2

7C8

5B4

5C4

5B4

7C8

5B4

87B4

36C5

36C4

36C5

36D4

36C4

36C5

36C4

36C5

5C1

51C7

5B2

7C6

5C1

36C5

5A4

5D2

5C2

26C8

5B4

5C1

24B3

36C5

IN

IO

IN

OUT

IN

IN IN

IN

OUT OUT

OUT

IO

IO IO

IN

IO IO

IO

IO IO

IO

IO IO

IO

IO IO

IO

IO IO

IN

OUT

IN

OUT

IO

DMI_ZCOMP

DMI_CLKP

DMI_IRCOMP

USBRBIAS*

USBRBIAS

DMI0RXN DMI0RXP DMI0TXN DMI0TXP

DMI2TXN DMI2TXP

DMI3RXN

DMI3TXP

DMI3TXN

DMI3RXP

USBP0N USBP0P USBP1N USBP1P USBP2N USBP2P USBP3N USBP3P

USBP4P USBP5N USBP5P USBP6N USBP6P USBP7N USBP7P

USBP4N

OC0* OC1* OC2* OC3* OC4*

OC6*/GPIO30

OC5*/GPIO29

SPI_CLK SPI_CS*

SPI_MOSI SPI_MISO

SPI_ARB

DMI_CLKN

DMI2RXP

DMI2RXN

DMI1TXP

DMI1TXN

DMI1RXN DMI1RXP

PERN1 PERP1 PETN1 PETP1

PERN2 PERP2 PETN2 PETP2

PERN3 PERP3 PETN3 PETP3

PERN4 PERP4 PETN4 PETP4

PERN5 PERP5 PETN5 PETP5

PERN6 PERP6 PETN6 PETP6

OC7*/GPIO31

PCI-EXP

(3 OF 6)

DMI

SPI

USB

REQ4*/GPIO22

REQ0*

MCH_SYNC*

RSVD8

RSVD7

RSVD6

RSVD5

RSVD4

GPIO5/PIRQH*

GPIO4/PIRQG*

GPIO3/PIRQF*

GPIO2/PIRQE*

GPIO17/GNT5*

GPIO1/REQ5*

GNT4*/GPIO48

C/BE0* C/BE1*

DEVSEL*

PERR*

STOP*

PCIRST*

PME*

PLTRST*

TRDY*

FRAME*

IRDY*

PCICLK

PAR

PLOCK*

SERR*

AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31

C/BE2* C/BE3*

GNT0* REQ1* GNT1* REQ2* GNT2* REQ3* GNT3*

PIRQA* PIRQB* PIRQC* PIRQD*

RSVD0 RSVD1 RSVD2 RSVD3

MISC

INT I/F

PCI

(2 OF 6)

IO

OUT

IO IO

IO

IO IO

IO

IO IO

IO

IO IO

IO

IO IO

IO

IO IO

IO

IO IO

IO

IO IO

IO

IO IO

IO

IO IO

IO

IN

IO

OUT

IO

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

BLUETOOTH

TRACKPAD (GEYSER)

CAMERA

IR

AND PWROK=H

NOTE: R2210 WAS PD ON PIN A14 = FWH_TBL_L

BOM NOTE FOR PD ON PCI_GNT3_L:

EXTERNAL 2

EXTERNAL 1

EXTERNAL 0

NOTE:

STUFF - A16 SWAP OVERRIDE

(STRAPPED TO TOP-BLOCK SWAP MODE IE SB INVERTS A16 FOR ALL CYCLES TARGETING FWH BIOS SPACE)

SB BOOT BIOS SELECT

GNT4#GNT5#

TO RSVD[1-9]

NOTE: CHANGE SYMBOL

R2210STRAP

11

10

01

STUFF

UNSTUFF

UNSTUFF UNSTUFF

STUFF

UNSTUFF

SPI

PCI

LPC (DEFAULT)

NOTE:

LAYOUT NOTE: PLACE R2203 < 1/2 IN FROM SB

LAYOUT NOTE: PLACE R2204 < 1/2 IN FROM SB

GNT4# HAS INT PU; ENABLED ONLY WHEN PCIRST#=0 AND PWROK=H

(INT PD)

GNT5# HAS INT PU (NOMINAL=20K, SIMULATION=15K-35K)

NOTE: FWH_WP_L NOT USED

R2211

ENABLED ONLY WHEN PCIRST#=0

SB: 2 OF 4

(AKA TP3, INTERNAL 20K PU)

(INT 20K PU)

GNT[0-3]# HAVE INT 20K PU

NO STUFF - DEFAULT

NOTE: USBP[0-7]P/N HAVE INTERNAL 15K PD

1/16W

402

24.9

MF-LF

1%

R2203

1 2

10K

1/16W MF-LF

5%

402

USB_G_OC_PU

R2222

1

2

402

22.6

1% 1/16W MF-LF

R2204

1 2

1/16W

5%

10K

MF-LF 402

R2223

1

2

10K

5% 1/16W MF-LF 402

R2225

1

2

402

MF-LF

1/16W

10K

5%

R2226

1

2

10K

5% 1/16W MF-LF 402

R2299

1

2

OMIT

BGA

SB

ICH7-M

U2100

V26 V25 U28 U27

Y26 Y25 W28 W27

AB26 AB25 AA28 AA27

AD25 AD24 AC28 AC27

AE28 AE27

D25

C25

D3 C4 D5 D4 E5 C3 A2 B3

F26

H26

K26

M26

P26

T25

F25

H25

K25

M25

P25

T24

E28

G28

J28

L28

N28

R28

E27

G27

J27

L27

N27

R27

P1

R2 P6

P2

P5

F1 F2 G4 G3 H1 H2 J4 J3 K1 K2 L4 L5 M1 M2 N4 N3

D1

D2

SB

BGA

ICH7-M

OMIT

U2100

E18 C18

E14 D14 B12 C13 G15 G13 E12 C11 D11 A11

A16

A10 F11 F10

E9 D9 B9 A8 A6 C7 B6

F18

E6 D6

E16 A18 E17 A17 A15 C14

B15 C12 D12 C15

A12

F16

E7

D16

D17

F13

A14 C8 D8

G8 F7 F8 G7

A7

AH20

E10 A9

B18

C9

A3 B4 C5 B5

E11

C26

B19

D7

C16

C17

E13

A13

AE5 AD5 AG4 AH4 AD9

AE9 AG8 AH8 F21

B10 F15 F14

MF-LF

1/16W

5%

10K

402

R2200

1

2

402

MF-LF

1/16W

5%

10K

USB_C_OC_PU

R2250

1

2

10K

5% 1/16W MF-LF 402

USB_E_OC_PU

R2251

1

2

USB_D_OC_PU

MF-LF

1/16W

5%

10K

402

R2255

1

2

MF-LF 402

1/16W

5%

10K

R2298

1

2

MF-LF

402

5%

10K

1/16W

R2205

1

2

402

10K

MF-LF

5%

1/16W

NOSTUFF

R2206

1

2

MF-LF 1/16W

10K

402

5%

R2207

1

2

VOLTAGE=0V

1/16W MF-LF

5%

1K

402

R2211

1

2

051-7164

8722

06004

PCI_PME_FW_L

PP3V3_S0

SPI_SI

SPI_CE_L

SB_GPIO30

PCI_REQ2_L

BOOT_LPC_SPI_L

PCI_C_BE_L<2>

SPI_SCLK

PCI_STOP_L

PCI_REQ3_L

PCI_REQ1_L

PCI_REQ0_L

PCI_AD<1>

PCI_AD<6>

EXCARD_OC_L

SB_GPIO29

TP_SB_XOR_AE9 TP_SB_XOR_AG8

SB_CRT_TVOUT_MUX

TP_SB_XOR_AH8

TP_SB_XOR_AE5

TP_SB_XOR_AD9

TP_SB_XOR_AH4

TP_SB_XOR_AG4

TP_SB_XOR_AD5

INT_PIRQD_L

USB2_LT2_P

SPI_SO

SPI_ARB

LTUSB_OC_L UNUSED_USB_D_OC_L

UNUSED_USB_B_OC_L

RTUSB_OC_L

LTUSB_OC_L

PP3V3_S5

PP1V5_S0_SB_VCC1_5_B

LT2USB_OC_L

TP_PCIE_F_R2DP

TP_PCIE_F_R2DN

TP_PCIE_F_D2RP

TP_PCIE_F_D2RN

TP_PCIE_E_R2DP

TP_PCIE_E_R2DN

TP_PCIE_E_D2RP

TP_PCIE_E_D2RN

TP_PCIE_D_R2DP

TP_PCIE_D_R2DN

TP_PCIE_D_D2RP

TP_PCIE_D_D2RN

PCIE_C_R2D_C_P

PCIE_C_R2D_C_N

PCIE_EXCARD_D2R_P

PCIE_EXCARD_D2R_N

PCIE_B_R2D_C_P

PCIE_B_R2D_C_N

PCIE_MINI_D2R_P

PCIE_MINI_D2R_N

PCIE_A_R2D_C_P

PCIE_A_R2D_C_N

PCIE_A_D2R_P

PCIE_A_D2R_N

DMI_N2S_P<1>

DMI_N2S_N<1>

DMI_S2N_N<1> DMI_S2N_P<1>

DMI_N2S_N<2> DMI_N2S_P<2>

SB_CLK100M_DMI_N

SB_GPIO29 SB_GPIO30

USB2_EXCARD_N

USB2_LT2_N

USB_BT_P

USB_BT_N

USB_HUB_P

USB_HUB_N

USB2_EXCARD_P

USB2_CAMERA_P

USB2_CAMERA_N

USB2_LT_P

USB2_LT_N

USB_TRACKPAD_P

USB_TRACKPAD_N

USB2_RT_P

USB2_RT_N

DMI_N2S_P<3> DMI_S2N_N<3> DMI_S2N_P<3>

DMI_N2S_N<3>

DMI_S2N_P<2>

DMI_S2N_N<2>

DMI_S2N_P<0>

DMI_S2N_N<0>

DMI_N2S_P<0>

DMI_N2S_N<0>

USB_RBIAS_PN

SB_CLK100M_DMI_P

DMI_IRCOMP_R

INT_PIRQC_L

INT_PIRQB_L

INT_PIRQA_L

PCI_C_BE_L<3>

PCI_AD<31>

PCI_AD<30>

PCI_AD<29>

PCI_AD<28>

PCI_AD<27>

PCI_AD<26>

PCI_AD<25>

PCI_AD<24>

PCI_AD<23>

PCI_AD<22>

PCI_AD<21>

PCI_AD<20>

PCI_AD<19>

PCI_AD<18>

PCI_AD<17>

PCI_AD<16>

PCI_AD<15>

PCI_AD<14>

PCI_AD<13>

PCI_AD<12>

PCI_AD<11>

PCI_AD<10>

PCI_AD<9>

PCI_AD<8>

PCI_AD<7>

PCI_AD<5>

PCI_AD<4>

PCI_AD<3>

PCI_AD<2>

PCI_AD<0>

PCI_SERR_L

PCI_LOCK_L

PCI_PAR

PCI_CLK_SB

PCI_IRDY_L

PCI_FRAME_L

PCI_TRDY_L

PLT_RST_L

TP_PCI_PME_L

PCI_RST_L

PCI_PERR_L

PCI_DEVSEL_L

PCI_C_BE_L<1>

PCI_C_BE_L<0>

SB_GPIO2 SB_GPIO3 SB_DVI_HPD ODD_PWR_EN_L

TP_SB_RSVD9

NB_SB_SYNC_L

RTUSB_OC_L

EXCARD_OC_L

UNUSED_USB_B_OC_L

UNUSED_USB_D_OC_L

PP3V3_S5

TP_PCI_GNT1_L

TP_PCI_GNT0_L

TP_PCI_GNT2_L

PCI_GNT3_L

TP_PCI_GNT4_L

LT2USB_OC_L

82D5

82C6 82B3 82A4 79D3 79A8 71D2 67C5 67C3 67B3 67A3

66B6 66B5 66B1 65D6 65B3 62A6 61D8 61A5 60D4 60C7

58C7 58C4 57B6 54D4 54B5 52D3 49C7 49C4 49B5 40B6

36D6 34A8 33D8 33D3 33C7 29A6 29A3 28A6 27D8 27D5

27D3 27C3 26D1 26B8 26B6 26B4

79D5

25D8

67D5

25D3

67D3

25C6

67C3

25C4

66C5

25B8

65D8

25B4

65D2

25A4

65D1

24D3

65C8

24C3

63D8

24B5

56D4

24B3

26C5

23D5

25D2

23B3

25C8

21D3

25B6

21C3

24C3

20B4

24B3

82A4

24B3

20A4

24A5

79A8

24A5

19C7

23D8

26C3

23D8

19C6

23D4

26C1

23D4

17C6

52B3

23D1

26B1

52B3

23D1

14D6

48C3

47C5

48C3

23B7

48C3

50C6

50B6

50C6

26A4

47C5

48C3

23B7

48C3

14C7

22C4

22D8

23A7

22D8

50C5

50B5

50C5

81C4

47B5

14B7

22D8

23A7

22C4

10C5

53B4

6C3

6D3

22C4

6D3

22D8

6C3

50C3

50B3

50C3

34C5

6D3

34C5

6C7

6D3

6C3

22D8

22C6

6C3

5D4

56C1

56C7

22C4

51C7

56C7

37C3

6C1

37D3

56C1

6D1

6C3

6D3

6D2

6D1

11B5

25B6

6C1

50B6

50A6

50B6

48B6

48C6

14B4

34C3

22D8

6D2

14B4

34C3

37C6

37C3

37D3

37C3

6C6

37C2

37D3

6D2

6C1

6D3

6C3

11B5

6C1

37D3

5A4

51D5

51B5

6D5

26D2

5C2

37B6

51D5

26D2

37D6

5C1

22C4

26D2

51D5

5C1

6C1

6D1

5C1

5D4

24D5

5C1

50B3

50A3

50B3

50C3

5B1

50C3

5B1

39C5

39D5

5A7

14B4

33B4

22D8

6D5

6D1

14B4

5A7

33B4

26D2

37B6

37C6

6C5

37C6

37D6

26D2

37B6

34D6

26D2

5C4

5B4

26D2

37B6

37C6

26D2

26C2

80A1

36C7

6D1

5C1

6D1

6C1

5D4

5C1

IN

OUT

OUT OUT

OUT

IN

IO

OUT OUT

OUT

IN

IO

IN

IO

IN

IO

IN

OUT

IN

OUT

IN

OUT

GPIO19/SATA1GP

GPIO21/SATA0GP

GPIO36/SATA2GP

CLK48

GPIO37/SATA3GP

CLK14

SUSCLK

SLP_S3* SLP_S4* SLP_S5*

PWROK

TP0/BATLOW*

GPIO16/DPRSLPVR

PWRBTN*

LAN_RST*

RSMRST*

GPIO10

GPIO9

GPIO12

GPIO14

GPIO13

GPIO24

GPIO15

GPIO25 GPIO35 GPIO38 GPIO39

SMBCLK SMBDATA LINKALERT*

SMLINK1

SMLINK0

RI*

SYS_RST*

SPKR SUS_STAT*

GPIO0/BM_BUSY*

GPIO18/STPPCI*

GPIO11/SMBALERT*

GPIO20/STPCPU*

GPIO26

GPIO28

GPIO27

GPIO32/CLKRUN*

GPIO33/AZ_DOCK_EN*

WAKE*

GPIO34/AZ_DOCK_RST*

SERIRQ THRM*

GPIO7

GPIO6

VRMPWRGD

GPIO8

(4 OF 6)

SMB

GPIO

PWR MNGT

SYS GPIO

CLKS

SATA GPIO

IN

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

(INT 20K PU)

PLACE R2306-14 WHERE PHYSICALLY ACCESSIBLE

NOTE FOR R2323 (DEF=NOSTUFF) SB WILL DISABLE TCO TIMER

STRAPPING @ PWROK RISING: SYSTEM REBOOT FEATURE

NOT USED

NOTE: RESERVED FOR FUTURE

LAYOUT NOTE:

NOTE FOR GPIO25:

OD

DEF=GPI

IN RESET STATE TO SAVE PWR

SMC WILL DRIVE 0-1-0 TO KEEP LAN INT’F

NOTE:

NOTE: SV_SET_UP IS LINDACARD DETECT

LO = NOT PRESENT

HI = PRESENT

(INT WEAK PD)

NOTE: DPRSLPVR HAS INT 20K PD, ENABLED AT BOOT/RESET FOR STRAPPING FCN

DEF=GPI

- CAN NOT BE LOW FOR 35US AFTER RSMRST# ON BOOT (DMI AC COUPLING MODE STRAP)

- HAS INTERNAL 20K PU, ENABLED DURING RSMRST# AND DISABLED WITHIN 100MS AFTER RSMRST# DEASSERTS

DEF=GPI

100

R2302

1 2

100

R2303

1 2

100

R2305

1 2

NOSTUFF

402 5%

MF-LF

1/16W

10K

R2306

1

2

10K

402 5%

MF-LF

1/16W

R2307

1

2

402

1/16W MF-LF

5%

10K

R2308

1

2

5%

MF-LF

1/16W

0

402

NOSTUFF

R2309

1

2

402 5%

MF-LF

1/16W

10K

R2310

1

2

1/16W MF-LF

5%

NOSTUFF

402

10K

R2311

1

2

10K

1/16W MF-LF

5%

402

R2313

1

2

402

NOSTUFF

0

1/16W MF-LF

5%

R2314

1

2

402

10K

1/16W MF-LF

5%

R2316

1

2

MF-LF

402

10K

1/16W

5%

R2317

1

2

10K

402

1/16W MF-LF

5%

R2318

1

2

10K

1/16W MF-LF

5%

402

R2319

1

2

402 5%

MF-LF

1/16W

10K

R2320

1

2

1/16W

5%

10K

SM-LF

RP2300

1 2 3 4

8 7 6 5

5%

402

MF-LF

1/16W

100K

R2399

1 2

1/16W MF-LF

5%

402

1K

R2398

1

2

5%

MF-LF

8.2K

402

1/16W

R2397

1

2

MF-LF 5%

1/16W

10K

402

R2396

1

2

8.2K

1/16W MF-LF

402 5%

R2395

1

2

OMIT

BGA

SB

ICH7-M

U2100

AC1 B2

AB18

A20

B23

F19 E19 R4 E22

AC22

AC20

AH18

AF21

AF19

R3 D20

A21

B21 E23

AG18

AC19

U2

AD21

AH19 AE19

AD20 AE20

AC21 AC18

E21

E20

C19

A26

C23

AA4

A28

Y4

AH21

B24 D23 F22

C22 B22

B25 A25

A19 A27

C20

A22

AF20

C21

AD22

F20

402

1/16W MF-LF

5%

10K

R2388

1

2

MF-LF

402 5%

1K

1/16W

NO_REBOOT_MODE

R2323

1

2

NOSTUFF

10K

1/16W MF-LF 402 5%

R2326

1

2

NOSTUFF

5%

MF-LF

1/16W 402

10K

R2327

1

2

5%

402

8.2K

1/16W MF-LF

R2343

1

2

SB: 3 OF 4

SYNC_DATE=08/08/2006

SYNC_MASTER=M57_MLB_MG

051-7164

8723

06004

INT_SERIRQ

PP3V3_S0

SATA_C_PWR_EN_L

PM_DPRSLPVR

PM_BATLOW_L

SB_CLK48M_USBCTLR

SV_SET_UP

SMBUS_SB_SCL

SATA_C_DET_L

SB_GPIO19

SB_GPIO21

SB_GPIO37

SB_CLK14P3M_TIMER

TP_SB_SUS_CLK

PM_SLP_S3_L PM_SLP_S4_L PM_SLP_S5_L

PM_SB_PWROK

PM_SYSRST_L

PM_SUS_STAT_L

BIOS_REC

VR_PWRGD_CK410

PP3V3_S5

TP_SB_GPIO6

CRB_SV_DET

PP3V3_S5

FWH_MFG_MODE

BIOS_REC

PP3V3_S0

SATA_C_PWR_EN_L

PM_BMBUSY_L

SB_SPKR

SMBUS_SB_SDA

PP3V3_S5

SMC_RUNTIME_SCI_L

PM_RSMRST_L

PM_LAN_ENABLE

PM_PWRBTN_L

PCIE_WAKE_L

FWH_MFG_MODE

PM_STPPCI_L

SMB_ALERT_L

PM_THRM_L

SMC_EXTSMI_L

PM_CLKRUN_L

PM_STPCPU_L

TP_AZ_DOCK_RST_L

GPU_D3COLD_RESET_L

PP3V3_S5

SMS_INT_L

IDE_RESET_L

SV_SET_UP

CRB_SV_DET

TP_SB_GPIO25_DO_NOT_USE

SB_CLK100M_SATA_OE_L

SB_GPUVCORE_DISABLE_L

SB_GPIO26

SMC_WAKE_SCI_L

LAN_ENERGY_DET

SMC_SB_NMI

SMLINK<1>

SMLINK<0>

SMB_LINK_ALERT_L

PM_RI_L

82D5

82C6

82B3

82A4

79D3

79A8

71D2

67C5

67C3

67B3

67A3

66B6

66B5

66B1

65D6

65B3

62A6

61D8

61A5

60D4

60C7

58C7

58C4

57B6

54D4

54B5

52D3

49C7

49C4

49B5

40B6

36D6

34A8

33D8

33D3

33C7

29A6

29A3

28A6

27D8

27D5

27D3

27C3

26D1

26B8

26B6

26B4

79D5

26B4

79D5

25D8

67D5

25D8

67D5

25D3

67D3

25D3

67D3

25C6

67C3

25C6

67C3

25C4

66C5

25C4

66C5

25B8

65D8

25B8

65D8

25B4

65D2

25B4

65D2

25A4

65D1

25A4

65D1

24D3

65C8

24D3

65C8

24C3

63D8

24C3

63D8

24B5

56D4

24B5

56D4

24B3

26C5

24B3

26C5

23B3

25D2

23D5

25D2

22B5

25C8

22B5

25C8

21D3

81C3

25B6

21D3

81C3

25B6

21C3

48B3

66C8

24C3

21C3

48B3

24C3

20B4

46B6

66C6

24B3

20B4

46B6

24B3

20A4

33B6

66B6

24A5

20A4

33B6

24A5

19C7

29A6

65B8

23D8

19C7

29A6

23D8

23D4

19C6

28A6

55C3

23D4

19C6

28A6

23D1

17C6

27D8

51C5

23D1

23B7

23D1

17C6

27D8

23B7

14D6

27D7

43C8

60C6

23A7

23B7

14D6

27D7

23A7

60C6

14C7

87C6

27D6

42A8

53B5

22D8

14C7

27D6

22D8

60C6

22D8

53C5

10C5

61C8

53B5

27C6

6C7

39C8

52A2

51B7

52A2

22C6

10C5

27C6

22C6

48C3

53C4

22C6

53B5

51C7

5D4

14B7

23C3

27B6

6C6

32B3

51C5

26A6

26C5

51C5

26B8

11B5

5D4

27B6

11B5

51D7

39C6

33C4

51C5

33C4

11B5

52B2

23B6

66B7

5C2

5A4

23A3

5B4

51B7

34C7

5C2

5B1

36B5

34A6

5B4

5C4

5B4

5A2

5C2

23A6

5A4

5D4

23C3

5D4

23C5

5A4

23B3

14B6

5B1

5D4

51B7

5B4

51D7

5B1

23A6

5B4

51B7

5C2

5B4

26A4

5D4

51B5

36D5

5C2

23B6

33B4

66B6

51D5

40A3

51D7

(6 OF 6)

VSS

V5REF_SUS

VCC3_3

VCCDMIPLL

VCCSATAPLL

VCC3_3

VCCRTC

VCCUSBPLL

VCCSAUS1_5

VCC PAUX

USB CORE

VCC1_5_A

ARX

USB

PCI

IDE

VCCA3GP

CORE

ATX

VCC1_5_A

VCC3_3

VCCSUS3_3

VCC1_5_A

VCCSUS3_3

VCC1_5_A

VCCLAN1_5

V_CPU_IO

VCC3_3/VCCHDA

VCCSUS3_3/VCCSUSHDA

VCCLAN_3_3

VCC1_05

V5REF

VCC1_5_B

(5 OF 6)

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

NOTE FOR VCCLAN_3_3: S3 IF INTERNAL LAN IS USED S0 OR S3 IF NOT

CHANGE SYMBOL TO 1.05

SO NO CONNECT HERE

VOLTAGE GENERATED INTERNALLY

SO NO CONNECT HERE

VOLTAGE GENERATED INTERNALLY

NOTE: VCCHDA AND VCCSUSHDA CAN BE 1.5V OR 3.3V DEPENDING ON VIO OF AZALIA INTERFACE CODEC IC’S CONSIDERED SO FAR ARE 3.3V

0 0

OMIT

BGA

ICH7-M

SB

U2100

A4

A23

B1

B8 B11 B14 B17 B20 B26 B28 C2 C6 C27

D10

D13 D18 D21 D24 E1 E2 E4 E8 E15 F3

F4

F5 F12 F27 F28 G1 G2 G5 G6 G9 G14

G18

G21 G24 G25 G26 H3 H4 H5 H24 H27 H28

J1

J2 J5 J24 J25 J26 K24 K27 K28 L13 L15

L24

L25 L26 M3 M4 M5 M12 M13 M14 M15 M16

M17

M24 M27 M28 N1 N2 N5 N6 N11 N12 N13

N14

N15

N16 AE24 AE25

AF2 AF4

AF8 AF11 AF27 AF28

N17

AG1

AG3

AG7

AG11 AG14 AG17 AG20 AG25 AH1 AH3

N18

AH7 AH12 AH23 AH27

N24

N25

N26

P3

P4 P12 P13 P14 P15 P16 P17

P24

P27 P28

R1 R11 R12 R13 R14 R15 R16 R17

R18

T6 T12 T13 T14 T15 T16 T17

U4 U12 U13

U14

U15 U16 U17 U24 U25 U26

V2 V13 V15 V24

V27

V28

W6 W24 W25 W26

Y3 Y24 Y27 Y28 AA1

AA24

AA25 AA26

AB4 AB6

AB11 AB14 AB16 AB19 AB21 AB24

AB27

AB28

AC2 AC5 AC9

AC11

AD1

AD3 AD4 AD7 AD8

AD11

AD15 AD19 AD23 AE2 AE4 AE8 AE11 AE13 AE18 AE21

OMIT

BGA

SB

ICH7-M

U2100

G10

AD17

F6

AE23 AE26 AH26

L11

P18 T11 T18 U11 U18 V11 V12 V14 V16 V17

L12

V18

L14 L16 L17 L18 M11 M18 P11

AB7 AC6

AB9 AC10 AD10 AE10 AF10

AF9

AG9

AH9

AB17 AC17

AC7

T7 F17 G17

AB8 AC8

A1 H6 H7 J6 J7

AD6

AE6

AF5

AF6

AG5

AH5

AB10

AA22 AA23

AD28

D26

D27

D28

E24

E25

E26

F23

F24

G22

AB22

G23

H22

H23

J22

J23

K22

K23

L22

L23

M22

AB23

M23

N22

N23

P22

P23

R22

R23

R24

R25

R26

AC23

T22

T23

T26

T27

T28

U22

U23

V22

V23

W22

AC24

W23

Y22

Y23

AC25 AC26 AD26 AD27

U6

B27

AH11

AG19

A5 B13 B16 B7 C10 D15 F9 G11 G12

AA7

G16

AB12 AB20 AC16 AD13 AD18 AG12 AG15

AG28

AA2

Y7

V5 V1 W2 W7

W5

AD2

K7

C28 G20

R7

P7

A24

L1 L2 L3 L6 L7 M6 M7 N7

E3

C24 D19 D22 G19

K3 K4 K5 K6

C1

SYNC_DATE=09/15/2006

SYNC_MASTER=M59_MLB

SB: 4 OF 4

06004

24 87

051-7164

PP1V5_S0_SB_VCC1_5_B

PP5V_S0_SB_V5REF

PP5V_S5_SB_V5REF_SUS

PP1V05_S0

PP3V3_S0

PP3V3_S5

PP1V05_S0

PP3V3_S0

PP1V5_S0_SB_VCCDMIPLL

PP1V5_S0

PP3V3_S0

PP1V5_S0

PP3V3_S5

PP3V3_S0

PP3V3_G3C_SB_RTC_D

PP3V3_S5

PP1V5_S0

82D5

82C6

82D5

82C6

82B3

82C6

82B3

82A4

82B3

82A4

79D3

82A4

79D3

79A8

79D3

79A8

71D2

79A8

71D2

67C5

71D2

67C5

67C3

67C5

67C3

67B3

67C3

67B3

67A3

67B3

67A3

66B6

67A3

66B6

66B5

66B6

66B5

66B1

66B5

66B1

65D6

66B1

65D6

65B3

65D6

65B3

62A6

65B3

62A6

61D8

62A6

61D8

61A5

61D8

61A5

60D4

61A5

60D4

60C7

60D4

60C7

58C7

60C7

58C7

58C4

58C7

58C4

57B6

58C4

57B6

54D4

57B6

54D4

54B5

54D4

54B5

52D3

54B5

52D3

49C7

52D3

49C7

49C4

49C7

49C4

49B5

49C4

49B5

40B6

49B5

40B6

36D6

40B6

36D6

34A8

36D6

34A8

33D8

34A8

33D8

33D3

33D8

33D3

33C7

33D3

33C7

29A6

33C7

29A6

29A3

29A6

29A3

28A6

29A3

67D8

28A6

27D8

67D8

27D8

28A6

67D6

27D8

27D5

67D6

27D5

27D8

65A2

27D5

27D3

65A2

27D3

27D5

55A4

27D3

27C3

55A4

27C3

27D3

34C8

27C3

26D1

34C8

26D1

27C3

34C6

26D1

26B8

34C6

26B8

26D1

34B8

26B8

26B6

34B8

26B6

26B8

25D3

26B6

26B4

25D3

26B4

26B6

79D5

25C4

26B4

25D8

25C4

25D8

79D5

25D8

26B4

67D5

24C3

25D8

25D3

24D3

25D3

67D5

25D3

25D8

67D3

21C1

25D3

25C6

21C1

25C6

67D3

25C6

25D3

67C3

19D7

25C6

25C4

19D7

25C4

67C3

25C4

25C6

66C5

19D6

25C4

25B8

19D6

25B8

66C5

25B8

25C4

65D8

19D5

25B8

25B4

19D5

25B4

65D8

25B4

25B8

65D2

19D2

25B4

25A4

19D2

25A4

67C8

25A4

65D2

25A4

25B4

65D1

67C8

19D1

25A4

24D3

19D1

24D3

67C6

24D3

65D1

24D3

25A4

65C8

67C6

19C8

24C3

19C8

24C3

66C5

24C3

65C8

24C3

24D3

63D8

66C5

17D6

24B5

17D6

24B5

62C1

24B5

63D8

24B5

24C3

56D4

62C1

17D3

24B3

17D3

24B3

62A8

24B3

56D4

24B3

24B5

26C5

62A8

16D3

23D5

16D3

23D5

48B6

23D5

26C5

23D5

25D2

48B6

16C8

23B3

16C8

23B3

25D6

23B3

25D2

23B3

25C8

25D6

13B5

22B5

13B5

22B5

25C8

22B5

25C8

22B5

25B6

25C8

12C2

21D3

12C2

21D3

25C6

21D3

25B6

21D3

24C3

25C6

12B7

21C3

12B7

21C3

25C2

21C3

24C3

21C3

24B3

25C2

12A7

20B4

12A7

20B4

25B6

20B4

24B3

20B4

24A5

25B6

11C5

20A4

11C5

20A4

25B2

20A4

23D8

20A4

23D8

25B2

11B3

19C7

11B3

19C7

25A8

19C7

23D4

19C7

23D4

25A8

9B7

19C6

9B7

19C6

24B5

19C6

23D1

19C6

23D1

24B5

8C7

17C6

8C7

17C6

24A5

17C6

23B7

17C6

23B7

24A5

7D5

14D6

7D5

14D6

24A3

14D6

23A7

14D6

23A7

24A3

7B6

14C7

7B6

14C7

9B7

14C7

22D8

14C7

26D4

22D8

9B7

7B5

10C5

7B5

10C5

8B7

10C5

22C6

10C5

26D3

22C6

8B7

25B6

5D4

11B5

5D4

25A4

11B5

5D4

22C1

25D7

25C7

5B2

5A4

5B2

5A4

5D1

5A4

5D4

5A4

21D6

5D4

5D1

NC NC

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

SECONDARY SIDE OR 3.56MM ON PRIMARY

ICH VCCDMIPLL BYPASS

PLACE C2520 NEAR PIN E3 OF SB

PLACEMENT NOTE: PLACE C2503 < 2.54MM OF PIN AD17 OF SB ON SECONDARY SIDE OR 3.56MM ON PRIMARY

ON SECONDARY SIDE OR 3.56MM ON PRIMARY

PLACE C2504 < 2.54MM OF PIN F6 OF SB

PLACEMENT NOTE:

(ICH REFERENCE FOR 5V TOLERANCE ON RESUME WELL LOGIC)

ICH V5REF_SUS BYPASS

(ICH SUSPEND 3.3V PWR)

ICH VCCSUS3_3 BYPASS

(ICH LOGIC&IO[ATX] 1.5V PWR)

(ICH LOGIC&IO[ARX] 1.5V PWR)

ICH VCC1_5_A/ARX BYPASS

ICH VCC3_3 BYPASS

PLACE C2509 NEAR PIN B27 OF SB

PLACEMENT NOTE:

ICH VCC3_3 BYPASS

(ICH RTC 3.3V PWR)

ICH VCCRTC BYPASS

V5, W2, OR W7

3.56MM ON PRIMARY NEAR PINS AA7 ... AG19

3.56MM ON PRIMARY NEAR PIN AD2

ICH VCC_PAUX/VCCLAN3_3 BYPASS (ICH LAN I/F BUFFER 3.3V PWR)

PLACEMENT NOTE: PLACE CAPS NEAR PINS AB8 AND AC8 OF SB

ICH USB/VCCSUS3_3 BYPASS (ICH SUSPEND USB 3.3V PWR)

PLACE CAPS NEAR PINS K3 ... N7 OF SB

PLACE C2520 NEAR PIN C1 OF SB

NEAR PINS D28, T28, AD28

PLACEMENT NOTE:

ICH VCC1_5_A/ATX BYPASS

(ICH IO BUFFER 3.3V PWR)

(ICH REFERENCE FOR 5V TOLERANCE ON CORE WELL INPUT)

ICH VCCSATAPLL BYPASS (ICH SATA PLL 1.5V PWR)

PLACE < 2.54MM OF SB ON SECONDARY OR

ICH V_CPU_IO BYPASS (ICH CPU I/O 1.05V PWR)

ICH IDE/VCC3_3 BYPASS

PLACE < 2.54MM OF SB ON SECONDARY OR

(ICH PCI I/O 3.3V PWR)

A24 ... G19 AND P7 OF SB

DISTRIBUTE IN PCI SECTION OF SB NEAR PINS A5 ... G16

(ICH IO BUFFER 3.3V PWR)

3.56MM ON PRIMARY NEAR PIN AG9

3.56MM ON PRIMARY NEAR PIN AG5

PLACEMENT NOTE:

PLACEHOLDER FOR 270UF

PLACE CAPS NEAR PINS

PLACEMENT NOTE:

PLACE CAPS NEAR PIN W5 OF SB

PLACEMENT NOTE:

SB: 4 OF 4

PLACE < 2.54MM OF SB ON SECONDARY OR

ICH V5REF BYPASS

PLACEMENT NOTE:

ICH CORE/VCC1_05 BYPASS (ICH CORE 1.05V PWR)

PLACEMENT NOTE: PLACE CAP UNDER SB NEAR PINS V1,

3.56MM ON PRIMARY NEAR PIN U6

PLACEMENT NOTE:

(ICH SUSPEND 3.3V PWR)

ICH VCCSUS3_3 BYPASS

PLACEMENT NOTE:

ICH VCC1_5A BYPASS (ICH LOGIC&IO 1.5V PWR)

(ICH USB CORE 1.5V PWR)

3.56MM ON PRIMARY NEAR PINS A1 ... J7

PLACE < 2.54MM OF SB ON SECONDARY OR

ICH USB CORE/VCC1_5_A BYPASS

PLACEMENT NOTE:

3.56MM ON PRIMARY NEAR PIN AH11

PLACE < 2.54MM OF SB ON SECONDARY OR

PLACEMENT NOTE:

PLACE < 2.54MM OF SB ON SECONDARY OR

PLACEMENT NOTE:

(ICH IDE I/O 3.3V PWR)

ICH PCI/VCC3_3 BYPASS

(ICH DMI PLL 1.5V PWR)

(ICH USB PLL 1.5V PWR)

ICH VCCUSBPLL BYPASS

ON SECONDARY SIDE OR 3.56MM ON PRIMARY

PLACE C2500 & C2505-07 < 2.54MM OF SB

PLACE NEAR PINS AE23, AE26 & AH26 OF SB

(ICH INTEL HDA CORE 3.3V PWR)

ICH VCC3_3/VCCHDA BYPASS

PLACE CAPS AT EDGE OF SB

PLACEMENT NOTE:

PLACE < 2.54MM OF SB ON SECONDARY OR

PLACE < 2.54MM OF SB ON

ICH VCCA3GP(VCC1_5_B BYPASS

(ICH IO,LOGIC 1.5V PWR)

X5R

16V

10%

0.1UF

402

C2510

1

2

0

402

0.1UF

10% 16V X5R

C2512

1

2

0

1

5%

1/10W MF-LF

603

R2500

1 2

4.7UF

20%

6.3V CERM 603

C2524

1

2

0.1UF

10% 16V X5R 402

C2522

1

2

BAT54DW

SOT-363

D2502

1

6

5

BAT54DW

SOT-363

D2502

4

3

2

1206

0.28-OHM

L2507

1 2

CASE-B2

2.5V POLY

220UF

20%

C2500

1

2

0.1UF

402

10% 16V X5R

C2503

1

2

0

X5R

16V

10%

0.1UF

402

C2504

1

2

0

5%

MF-LF

1/16W 402

10

R2501

1 2

100-OHM-EMI

SM-3

L2500

1 2

0

0.1UF

10% 16V X5R 402

C2505

1

2

X5R

16V

10%

0.1UF

402

C2506

1

2

0.1UF

16V

10% X5R

402

C2507

1

2

0.01UF

10% 16V CERM 402

C2501

1

2

603

10UF

20%

6.3V X5R

C2508

1

2

0

10% 16V X5R 402

0.1UF

C2509

1

2

0

X5R 402

16V

10%

0.1UF

C2511

1

2

0

0.1UF

402

X5R

16V

10%

C2517

1

2

0

0.1UF

10% 16V X5R 402

C2513

1

2

0

402

6.3V CERM

10%

1UF

C2514

1

2

0

0.1UF

10% 16V X5R 402

C2520

1

2

402

X5R

16V

10%

0.1UF

C2515

1

2

0

CASE-C2

POLY

20%

2.5V

330UF

C2516

1

2

5%

1/16W 402

MF-LF

100

R2502

1

2

1UF

10%

6.3V CERM 402

C2502

1

2

402

0.1UF

10% 16V X5R

C2518

1

2

0

X5R

16V

10%

0.1UF

402

C2519

1

2

0

0.1UF

10% 16V

402

X5R

C2521

1

2

0

X5R

16V

10%

0.1UF

402

C2523

1

2

0

0.1UF

X5R

16V

10%

402

C2525

1

2

0

X5R

16V

10%

0.1UF

402

C2526

1

2

X5R

16V

10%

0.1UF

402

C2527

1

2

X5R

16V

10%

0.1UF

402

C2528

1

2

402

0.1UF

10% 16V X5R

C2529

1

2

0

402

0.1UF

10% 16V X5R

C2530

1

2

402

0.1UF

10% 16V X5R

C2534

1

2

0

402

0.1UF

10% 16V X5R

C2531

1

2

402

0.1UF

10% 16V X5R

C2532

1

2

0

402

0.1UF

10% 16V X5R

C2533

1

2

051-7164

8725

06004

PP1V5_S0

PP1V05_S0

PP3V3_S0

PP1V05_S0

PP1V5_S0

MIN_NECK_WIDTH=0.25MM

MIN_LINE_WIDTH=0.5MM

VOLTAGE=1.5V

PP1V5_S0_SB_VCCDMIPLL

PP1V5_S0_SB_VCCDMIPLL_F

VOLTAGE=1.5V MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.25MM

PP3V3_S0

PP1V5_S0

PP3V3_S5

PP1V5_S0

PP3V3_S5

PP3V3_S0

PP1V5_S0

PP3V3_S0

PP1V5_S0

PP3V3_S5

PP1V5_S0

PP3V3_S0

PP3V3_G3C_SB_RTC_D

PP5V_S5

PP3V3_S0

PP3V3_S5

PP5V_S0

PP5V_S5_SB_V5REF_SUS

MIN_NECK_WIDTH=0.25MM

VOLTAGE=5V

MIN_LINE_WIDTH=0.3MM

PP5V_S0_SB_V5REF

VOLTAGE=5V MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.25MM

VOLTAGE=1.5V MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.25MM

PP1V5_S0_SB_VCC1_5_B

82D5

82C6

82B3

82A4

79D3

79A8

71D2

67C5

67C3

67B3

67A3

66B6

66B5

66B1

65D6

65B3

62A6

61D8

61A5

60D4

60C7

58C7

58C4

57B6

54D4

54B5

52D3

49C7

49C4

49B5

40B6

36D6

34A8

33D8

33D3

33C7

29A6

29A3

67D8

28A6

67D8

28A6

67D6

27D8

67D6

27D8

65A2

27D5

65A2

27D5

55A4

27D3

55A4

27D3

34C8

27C3

34C8

27C3

34C6

26D1

34C6

26D1

34B8

26B8

34B8

26B8

25C4

26B6

25D3

26B6

79D5

26B6

79D5

26B6

24D3

26B4

24D3

26B4

67D5

79D5

26B4

67D5

26B4

79D5

24C3

25D8

24C3

25D8

67D3

67D5

25D8

67D3

25D8

25D3

67D5

21C1

25D3

21C1

25D3

67C3

67D3

25D3

67C3

25C6

67D3

19D7

25C6

19D7

25C6

66C5

67C3

25C6

25C4

66C5

25C4

67C3

19D6

25B8

19D6

25C4

65D8

66C5

25C4

25B8

65D8

25B8

66C5

19D5

25B4

19D5

25B8

65D2

65D8

25B4

25B8

25B4

65D2

25B4

65D8

19D2

25A4

19D2

25A4

65D1

65D2

25A4

67C8

25B4

25A4

67C8

65D1

25A4

65D2

81B3

67C8

19D1

24D3

19D1

67C8

24D3

67C8

65C8

67C8

65D1

24D3

67C6

24D3

67C6

65C8

67C8

24D3

65D1

80B5

67C6

19C8

24C3

19C8

67C6

24C3

67C6

63D8

67C6

65C8

24C3

66C5

24C3

66C5

63D8

67C6

24C3

65C8

80A1

66C5

17D6

24B5

17D6

66C5

24B5

66C5

56D4

66C5

63D8

24B5

62C1

24B5

62C1

56D4

66C5

24B5

63D8

79B8

62C1

17D3

24B3

17D3

62C1

24B3

62C1

26C5

62C1

56D4

24B3

62A8

24B3

62A8

26C5

62C1

24B3

71D7

24B3

56D4

71A6

62A8

16D3

23D5

16D3

62A8

23D5

62A8

25D2

62A8

26C5

23D5

48B6

23D5

48B6

25D2

62A8

23D5

67C3

23D5

26C5

67B3

48B6

16C8

23B3

16C8

48B6

23B3

48B6

25C8

48B6

25D2

23B3

25D6

23B3

25D6

25C8

48B6

23B3

67C1

23B3

25D2

67B1

25D6

13B5

22B5

13B5

25D6

22B5

25D6

25B6

25D6

25C8

22B5

25C8

22B5

25C8

25B6

25D6

22B5

67B1

22B5

25B6

67A1

25C6

25C8

12C2

21D3

12C2

25C8

21D3

25C8

24C3

25C8

24C3

21D3

25C6

21D3

25C6

24C3

25C8

21D3

66D8

21D3

24C3

66B5

25C2

12B7

21C3

12B7

25C6

21C3

25C6

24B3

25C6

24B3

21C3

25C2

21C3

25C2

24B3

25C6

21C3

66B8

21C3

24B3

62B1

25B6

12A7

20B4

12A7

25C2

20B4

25C2

24A5

25C2

24A5

20B4

25B6

20B4

25B6

24A5

25B6

20B4

65D6

20B4

24A5

61D7

25B2

11C5

20A4

11C5

25B2

20A4

25B6

23D8

25B6

23D8

20A4

25B2

20A4

25B2

23D8

25B2

20A4

65B7

20A4

23D8

58C7

25A8

11B3

19C7

11B3

25A8

19C7

25A8

23D4

25B2

23D4

19C7

25A8

19C7

25A8

23D4

25A8

19C7

64C8

19C7

23D4

58C4

24B5

9B7

19C6

9B7

24B5

19C6

24B5

23D1

24B5

23D1

19C6

24B5

19C6

24B5

23D1

24B5

19C6

62C8

19C6

23D1

57B5

24A5

8C7

17C6

8C7

24A5

17C6

24A5

23B7

24A5

23B7

17C6

24A5

17C6

24A5

23B7

24A5

17C6

62B6

17C6

23B7

55A8

24A3

7D5

14D6

7D5

24A3

14D6

24A3

23A7

24A3

23A7

14D6

24A3

14D6

24A3

23A7

24A3

14D6

62B2

14D6

23A7

53C4

9B7

7B6

14C7

7B6

9B7

14C7

9B7

22D8

9B7

22D8

14C7

9B7

14C7

9B7

22D8

9B7

14C7

26D4

62A4

14C7

22D8

36D6

8B7

7B5

10C5

7B5

8B7

10C5

8B7

22C6

8B7

22C6

10C5

8B7

10C5

8B7

22C6

8B7

10C5

26D3

52B5

10C5

22C6

31C5

5D4

11B5

5D4

11B5

5D4

11B5

5D4

24B3

47C7

5D4

11B5

5D4

24D5

5D1

5B2

5A4

5B2

5D1

24B5

5A4

5D1

5D4

5D1

5D4

5A4

5D1

5A4

5D1

5D4

5D1

5A4

21D6

5D4

5A4

5D4

5D2

24D5

22C1

IO

IN

IO IO

IO

IO IO

IO

OUT

IN

OUT

IN

OUT

IN

NCNC

IN

OUT

IO

IO IO

IO

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

Initial resistor values are based on CRB, but may change after characterization.

fault protection for RTC battery.

for use as DVI_HPD in muxed graphics solution.

Pullup on SB_GPIO4 removed as it now defaults low

Platform Reset Connections

NC

518S0452

NOTE: R2607 and D2600 form the double-

NC

Silk: "SYS RST"

Unbuffered

NC

SB RTC Crystal Circuit

1G00 used as small & cheap inverter

100-ohm on NB page

Linda Card represents 3 loads

This part is never stuffed,

NCNC

on the board to short or

LIO represents X loads (2?)

Hook to inverter PWM AND gate (except M59) This RST is used to mask a glitch output from

the NB PWM output during reset.

On M59 this RST is used for layout reasons

Buffered

D3Cold Reset for GPU

to solder a reset button.

it provides a set of pads

RTC Battery Connector

20K

1/16W

402

5%

MF-LF

R2600

1 2

20% 10V

CERM

402

0.1UF

C2611

1

2

1UF

10%

6.3V CERM 402

C2605

1

2

OMIT

402

MF-LF

100K

1/16W

5%

R2698

1

2

5% 1/16W MF-LF 402

1M

R2606

1

2

1/16W

5%

402

10K

MF-LF

R2697

1

2

1K

1/16W MF-LF

5%

402

R2607

2 1

50V

5%

402

CERM

12pF

C2608

1 2

402

5%

50V

12pF

CERM

C2609

1 2

32.768K

CRITICAL

SM-2

Y2600

2 4

1 3

5% 1/16W MF-LF

402

0

R2610

1 2

5% 1/16W MF-LF

402

10M

R2609

1

2

10V

402

CERM

20%

0.1UF

C2680

1

2

5% 1/16W

100K

402

MF-LF

R2680

1

2

MF-LF

0

402

1/16W

5%

R2681

1 2

5%

100

402

MF-LF

1/16W

R2683

1 2

402

5%

1/16W

0

MF-LF

R2684

1 2

5% 1/16W MF-LF

402

0

R2685

1 2

0

1/16W

5%

402

MF-LF

R2682

1 2

MF-LF

1/16W

5%

402

ITP

1K

R2696

1 2

SC70-5

MC74VHC1G00

U2603

3

2

1

4

5

SC70

MC74VHC1G08

U2680

3

2

1

4

5

MC74VHC1G08

SC70

U2601

3

2

1

4

5

SOT-363

BAT54DW

D2600

1

4

6

3

5

2

CRITICAL

M-RT-SM

BM02B-ACHKS-A-GAN-TF-LF

J2600

3

4

1 2

5% 1/16W

402

MF-LF

100K

R2688

1

2

MC74VHC1G08

SC70

U2685

3

2

1

4

5

402

10V

20%

CERM

0.1UF

C2685

1

2

10K

402

5%

MF-LF

1/16W

R2686

1

2

0

402

MF-LF

1/16W

5%

R2687

1 2

1K

MF-LF

1/16W

5%

402

R2689

1 2

0.001UF

CERM 402

50V

10%

C2689

1

2

1.8K

5%

MF-LF 402

1/16W

R2611

1

2

20% 10V

CERM

402

0.1UF

C2607

1

2

10K

5% 1/16W MF-LF

402

R2612

1

2

402

MF-LF

1/16W

5%

10K

R2622

1

2

8.2K

R2623

1 2

8.2K

R2624

1 2

8.2K

R2625

1 2

8.2K

R2626

1 2

8.2K

R2627

1 2

8.2K

R2628

1 2

8.2K

R2629

1 2

8.2K

R2630

1 2

8.2K

R2631

1 2

8.2K

R2632

1 2

8.2K

R2633

1 2

8.2K

R2634

1 2

8.2K

R2636

1 2

8.2K

R2637

1 2

8.2K

R2638

1 2

8.2K

R2639

1 2

8.2K

R2640

1 2

8.2K

R2642

1 2

1UF

CERM

10%

6.3V

402

C2610

1

2

SYNC_MASTER=(MASTER)

SYNC_DATE=(MASTER)

87

06004051-7164

26

SB Misc

GPU_SIGNAL_ENABLE

MAKE_BASE=TRUE

PP3V3_S5

PLTRST_D3COLD_L

GPU_SIGNAL_ENABLE

PEG_RESET_L

PP3V3_S0

GPU_D3COLD_RESET_L

PLT_RST_L

MAKE_BASE=TRUE

PP3V3_S0

TPM_LRESET_L

PLT_RST_L

GPU_D3COLD_RESET_L

MAKE_BASE=TRUE

LIO_PLT_RESET_L

PLT_RST_L

PP3V3_S0

PCI_IRDY_L

PCI_SERR_L PCI_DEVSEL_L PCI_PERR_L

PCI_REQ0_L PCI_REQ1_L PCI_REQ2_L PCI_REQ3_L

INT_PIRQA_L INT_PIRQB_L INT_PIRQC_L INT_PIRQD_L SB_GPIO2 SB_GPIO3

PP3V3_S0

VOLTAGE=3.3V

PPVBATT_G3C_RTC

SB_RTC_X2

ENET_RST_L

PP3V3_G3C_SB_RTC_D

VOLTAGE=3.3V

MAKE_BASE=TRUE

PCI_LOCK_L

PCI_STOP_L

PCI_TRDY_L

PCI_FRAME_L

PP3V3_G3C_SB_RTC_D

PP3V42_G3H

VOLTAGE=3.3V

PPVBATT_G3C_RTC_R

VR_PWRGOOD_DELAY

ALL_SYS_PWRGD

PM_SB_PWROK

VR_PWRGD_CK410_L

MAKE_BASE=TRUE

PM_SYSRST_L

MAKE_BASE=TRUE

SB_SM_INTRUDER_L

SB_RTC_X1

DEBUG_RST_L

SMC_LRESET_L

PLT_RST_L

VR_PWRGD_CK410

VR_PWRGD_CK410_L

SB_RTC_RST_L

SB_RTC_X1_R

XDP_DBRESET_L

PP3V3_S0

PLT_RST_BUF_L

82D5

82C6

82D5

82B3

82C6

82A4

82B3

79D3

82A4

79A8

79D3

71D2

79A8

67C5

71D2

67C3

67C5

67B3

67C3

67A3

67B3

66B6

67A3

66B5

66B6

66B1

66B5

65D6

66B1

65B3

65D6

62A6

65B3

61D8

62A6

61A5

61D8

60D4

61A5

60C7

60D4

58C7

60C7

58C4

58C7

57B6

58C4

54D4

57B6

54B5

54D4

52D3

54B5

49C7

52D3

49C4

49C7

49B5

49C4

40B6

49B5

36D6

40B6

34A8

36D6

33D8

34A8

33D3

33D8

33C7

33D3

29A6

33C7

29A3

29A6

28A6

29A3

27D8

28A6

27D5

27D8

27D3

27D5

27C3

27D3

26D1

27C3

26B8

26D1

26B8

26D1

26B6

26B8

26B4

79D5

25D8

67D5

25D3

67D3

25C6

67C3

25C4

66C5

25B8

81D4

25B8

65D8

25B4

69C8

25B4

65D2

25A4

69B8

25A4

65D1

24D3

69A8

24D3

65C8

24C3

68B8

24C3

63D8

24B5

67D5

24B5

56D4

24B3

67D3

24B3

25D2

23D5

66D2

23D5

25C8

23B3

66C8

23B3

25B6

22B5

66A8

22B5

24C3

21D3

53C4

21D3

24B3

21C3

82A4

21C3

52D7

82A4

21C3

24A5

20B4

82A4

20B4

82A4

79A8

20B4

52B7

79A8

20B4

23D8

20A4

79A8

20A4

79A8

26C3

20A4

52B5

26C3

20A4

23D4

19C7

26C1

19C7

26C3

26C1

19C7

52B1

26C1

19C7

23D1

19C6

26B1

19C6

26C1

26B1

19C6

51D4

26B1

19C6

23B7

17C6

26A4

17C6

26B1

26A4

17C6

51D3

26A4

17C6

23A7

14D6

22A6

14D6

22A6

14D6

51C2

22A6

14D6

82A7

22D8

82A7

14C7

14B7

14C7

14B7

14C7

37D3

14C7

26D3

26D4

47B5

14B7

61C7

14C7

80B2

82A7

22C6

80B2

10C5

6C7

10C5

6C7

48C3

6C7

10C5

22B6

10C5

25A4

35B7

61C7

6C7

33A4

10C5

26A2

80B2

11B5

26A2

70A5

5D4

26A4

6C6

5D4

60B7

6C6

26C1

6C6

5D4

37D3

37C3

37D3

6B5

37D3

5D4

24B3

37C3

37D3

24B3

27C3

66B1

33A4

53B4

51C7

6C6

26A7

5D4

26A1

5D4

26A1

5C4

5A4

23C5

5C4

5A4

5C4

5C1

5C4

5A4

22A6

22B6

6B3

22A7

22A6

5A4

21D6

39C6

21D6

22A6

22A7

21D6

5D2

51D7

26A8

21D6

5C2

5C4

5A4

37A7

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

(Write: 0x92 Read: 0x93)

SMC "Battery B" SMBus Connections

NOTE: SMC RMT bus remains powered and may be active in S3 state

SMC "A" SMBus Connections

Battery

SMC "Battery A" SMBus Connections

(Write: 0x16 Read: 0x17)

(See Table)

Left I/O Board

USB Hub

Top-Case

SMC "B" SMBus Connections

TMP106: U5650

Battery Chgr

(Write: 0x98 Read: 0x99)

TMP401: U1001

CPU Temp

SMC "0" SMBus Connections

GPU Temp

U5800

(MASTER)

SO-DIMM "B"

ICH7-M SMBus Connections

(WRITE: 0X98 READ: 0X99)

(WRITE: 0X92 READ: 0X93)

LIO/ALS Temp

TMP106: J5500

(Write: 0xD2 Read: 0xD3)

SO-DIMM "A"

M35B - TMP106

(Write: 0x72 Read: 0x73)

Left I/O SMBus Connections:

(Write: 0x92 Read: 0x93)

ExpressCard Slot

(Address determined by ARP)

(See Table)

J4900

Trackpad

(See Table)

U4900

(Write: 0x70 Read: 0x71)

(Write: 0x58 Read: 0x59)

USB_HUB - U4900

U1 - Trackpad Controller

J5500

(MASTER)

U5800

SMC

TMP275: J4900

ICH7-M

(Write: 0xA0 Read: 0xA1)

U2100

(MASTER)

(Write: 0x98 Read: 0x99)

TMP401: U6150

Remote Temps

MAX6695: U6100

U2 - Keyboard Controller

SMC

(MASTER)

U5800

(MASTER)

J2800

(MASTER)

SMC

U5800

J2900

J8250

SMC

Trackpad I2C Connections:

(Write: 0x30 Read: 0x31)

(Write: 0xA4 Read: 0xA5)

CY28445-5: U3301

Clock Chip

4.7K

5%

MF-LF

402

1/16W

R2700

1

2

5%

402

1/16W

4.7K

MF-LF

R2701

1

2

3.3K

MF-LF

402

5%

1/16W

R2780

1

2

3.3K

MF-LF 402

5% 1/16W

R2781

1

2

MF-LF 402

1/16W

5%

100K

R2791

1

2

5%

100K

402

MF-LF

1/16W

R2790

1

2

MF-LF 402

1/16W

5%

4.7K

R2761

1

2

4.7K

MF-LF

402

1/16W

5%

R2760

1

2

5%

402

MF-LF

1/16W

4.7K

R2771

1

2

4.7K

5%

MF-LF

402

1/16W

R2770

1

2

402

MF-LF

1/16W

5%

4.7K

R2751

1

2

402

4.7K

1/16W

5%

MF-LF

R2750

1

2

CERM

15pF

NO STUFF

5% 50V

402

C2701

1

2

CERM

5% 50V

402

15pF

C2761

1

2

5% 50V CERM 402

15pF

C2751

1

2

051-7164 06004

27 87

M57 SMBUS CONNECTIONS

SYNC_MASTER=(MASTER)

SYNC_DATE=(MASTER)

SMBUS_SMC_BSA_SCL

PP3V3_S0

SMBUS_SB_SDA

SMBUS_SMC_0_S0_SDA

PP3V3_S0

SMBUS_SB_SDA

SMBUS_SMC_0_S0_SCL SMBUS_SMC_B_S0_SCL

SMBUS_SMC_BSA_SDA SMBUS_SMC_BSA_SDA

SMBUS_SMC_BSB_SDA

SMBUS_SMC_BSA_SCL

SMBUS_SMC_BSB_SDA

MAKE_BASE=TRUE

SMBUS_SMC_BSB_SCL

MAKE_BASE=TRUE

PP3V42_G3H

PP3V3_S0

SMBUS_SMC_B_S0_SDA

PP3V3_S0

SMBUS_SMC_BSB_SCL

SMBUS_SMC_0_S0_SDA

SMBUS_SMC_0_S0_SCL

SMBUS_SMC_BSA_SDA

MAKE_BASE=TRUE

SMBUS_SMC_0_S0_SCL

MAKE_BASE=TRUE

SMBUS_SMC_0_S0_SCL

SMBUS_SMC_A_S3_SDA

SMBUS_SMC_A_S3_SCL

SMBUS_SMC_A_S3_SDA

SMBUS_SB_SDA

SMBUS_SB_SCL

SMBUS_SB_SDA

MAKE_BASE=TRUE

SMBUS_SB_SDA

SMBUS_SB_SCL

SMBUS_SB_SDA

SMBUS_SB_SCL

SMBUS_SMC_A_S3_SDA

SMBUS_SMC_A_S3_SCL

MAKE_BASE=TRUE

SMBUS_SMC_A_S3_SDA

MAKE_BASE=TRUE

SMBUS_SMC_B_S0_SCL

SMBUS_SMC_B_S0_SDA

SMBUS_SB_SCL

SMBUS_SB_SDA

SMBUS_SB_SCL

MAKE_BASE=TRUE

SMBUS_SB_SDA

SMBUS_SMC_A_S3_SCL

MAKE_BASE=TRUE

SMBUS_SMC_BSA_SCL

SMBUS_SMC_0_S0_SDA

MAKE_BASE=TRUE

SMBUS_SMC_0_S0_SDA

PP3V3_S3

SMBUS_SMC_B_S0_SDA

SMBUS_SMC_B_S0_SCL

SMBUS_SMC_B_S0_SDA

MAKE_BASE=TRUE

SMBUS_SMC_B_S0_SCL

MAKE_BASE=TRUE

82D5

82D5 82D5 82C6

82C6

82C6 82C6 82B3

82B3

82B3 82B3 82A4

82A4

82A4 82A4

79D3

79D3 79D3 79A8

79A8

79A8 79A8 71D2

71D2

71D2 71D2 67C5

67C5

67C5 67C5 67C3

67C3

67C3 67C3 67B3

67B3

67B3 67B3 67A3

67A3

67A3 67A3 66B6

66B6

66B6 66B6

66B5

66B5 66B5 66B1

66B1

66B1 66B1 65D6

65D6

65D6 65D6 65B3

65B3

65B3 65B3 62A6

62A6

62A6 62A6 61D8

61D8

61D8 61D8 61A5

61A5

61A5 61A5 60D4

60D4

60D4 60D4

60C7

60C7 60C7 58C7

58C7

58C7 58C7 58C4

58C4

58C4 58C4 57B6

57B6

57B6 57B6 54D4

54D4

54D4 54D4 54B5

54B5

54B5 54B5 52D3

52D3

52D3 52D3 49C7

49C7

49C7 49C7 49C4

49C4

49C4 49C4

49B5

49B5 49B5 40B6

40B6

40B6 40B6 36D6

36D6

36D6 36D6 34A8

34A8

34A8 34A8 33D8

33D8

33D8 33D8 33D3

33D3

33D3 33D3 33C7

33C7

33C7 33C7 29A6

29A6

29A6 29A6

29A3

29A3 29A3 28A6

28A6

28A6 28A6 27D5

27D8

27D8 27D8 27D3

27D5

27D3 27D5 27C3

27D3

27C3 27C3 26D1

26D1

26D1 26D1 26B8

26B8

26B8 26B8 26B6

26B6

26B6 26B6 26B4

26B4

26B4 26B4

25D8

25D8 25D8 25D3

25D3

25D3 25D3 25C6

25C6

25C6 25C6 25C4

25C4

25C4 25C4 25B8

25B8

81D4

25B8 25B8 25B4

25B4

69C8

25B4 25B4

81D4

25A4

69B8

25A4 25A4

81A5

24D3

69A8

24D3 24D3

67C5

24C3

68B8

24C3 24C3

67C3

24B5

67D5

24B5 24B5

66C6

24B3

67D3

24B3 24B3

65D1

23D5

66D2

23D5 23D5

63B7

23B3

66C8

23B3 23B3

60C2

22B5

81C3

22B5

81C3

66A8

22B5 22B5

81C3

59C6

21D3

48B3

21D3

48B3

53C4

21D3 21D3

81C3

48B3

81C3

57D4

21C3

46B6

21C3

46B6

52D7

21C3 21C3

48B3

46B6

48B3

52B1

20B4

33B6

20B4

33B6

52B7

20B4 20B4

46B6

33B6

46B6

46D6

20A4

29A6

20A4

29A6

52B5

20A4 20A4

33B6

29A6

33B6

46C3

19C7

28A6

19C7

28A6

52B1

19C7 19C7

29A6

28A6

29A6

46B3

19C6

27D8

19C6

27D8

51D4

19C6 19C6

81C3

28A6

27D8

81C3

27D8

28A6

81C3

41C5

17C6

27D7

17C6

27D7

51D3

17C6 17C6

54C2

51B5

81C3

51B5

27D7

51B5

81C3

51B5

27D7

27D8

51B5

37D7

51B5

68B2

14D6

27D6

54C2

14D6

27D6

54C2 51B5

68B2 68B2

68B2

51C2

14D6

51B5

14D6

54B3

68B2

54B3

54C2

48B6

51B5

48B6

27D6

48B6

51B5

48B6

49B5

27D6

48B6

68B2

54C2

37D5

49B5

51B5

14C7

27C6

54B3

14C7

27C6

54B3 49B5

51B5 51B5

51B5

47B5

14C7

49B5

14C7

51C5

51C7

51B5

51C7

54B3

27C6

48B6

27C5

27C6

48B6

27C6

27D3

27C6

51B5

54B3

37C3

27D3

49B5

27C2

10C5

27B6

51C5

10C5

27B6

51C7 27D2

27C2 27C3

27C3

35B7

10C5

27D2

10C5

27D6

27C3

27D6

51C7

27C5

27C3

27B6

27C5

27C6

27C3

27D2

27B6

27C5

27C3

51C5

37A7

27D2

27D3

27C1

5D4

23D5

27D5

5D4

23D5

27D5 27D1

27C1 27C2

51C7

27C2

51C7

51C5

26D6

5D4

27D1

5D4

51C5

27D5

27C1

27D5

27D6

27B3

27C3

27B3

23D5

27C3

27B3

27D1

23D5

27C3

27C1

27D6

32C5

27D1

5D1

5A4

5B1

27D3

5A4

5B1

27D3 10B3

5D1 5D1

27B2

5D1

27B3

5D2

5A4

10B3

5A4

27B2

27D3

5D1

27D3

5B1

10B3

5B1

5D1

27D3

5D4

10B3