TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_HEAD
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM
DRAWING
TABLE_TABLEOFCONTENTS_HEAD
DESCRIPTION
REFERENCE DES
BOM OPTION
QTY
PART NUMBER
CRITICAL
ANGLES
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.
2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.
DATE
APPD
ENG
DATE
APPD
CK
ECN
ZONE
REV
DO NOT SCALE DRAWING
X.XXX
X.XX
XX
DIMENSIONS ARE IN MILLIMETERS
THIRD ANGLE PROJECTION
D
SIZE
APPLICABLE
NOTED AS
MATERIAL/FINISH
NONE
SCALE
DESIGNER
MFG APPD
DESIGN CK
RELEASE
QA APPD
ENG APPD
DRAFTER
METRIC
OF
SHT
DRAWING NUMBER
TITLE
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
Apple Computer Inc.
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
DESCRIPTION OF CHANGE
Schematic / PCB #’s
SCHEMATIC,MACBOOK PRO 17"
9/26/2006
ALIASES RESOLVED
SCHEMATIC,MACBOOK PRO 17
?
? ??
?
871
051-7164 06004
(.CSA)
SYNC
DATE
CONTENTS
PAGE
LAST_MODIFIED=Tue Sep 26 13:17:56 2006
TITLE=TRUCKEE
ABBREV=DRAWING
44
M59_MLB
FireWire Ports
06/27/2006
46
SCHEM,TRUCKEE,M57
051-7164 CRITICAL
SCH1
PCBF,TRUCKEE,M57
CRITICAL
PCB1
820-2059
N/A
N/A
1
1
Table of Contents
PAGE
(.CSA)
SYNC
DATE
CONTENTS
45
M59_MLB
Camera Connector
09/15/2006
49
46
(MASTER)
Internal USB Hub
(MASTER)
50
47
M59_MLB
External USB Connector
09/15/2006
52
48
(MASTER)
Left I/O Board Connector
(MASTER)
55
49
(MASTER)
Current & Thermal Sensors
(MASTER)
56
50
(MASTER)
PCI-E Connections
(MASTER)
57
51
M59_MLB
SMC
09/15/2006
58
52
M59_MLB
SMC Support
09/15/2006
59
53
(MASTER)
LPC+ Debug Connector
(MASTER)
60
54
M59_MLB
Thermal Sensors
09/15/2006
61
55
M59_MLB
Current & Voltage Sensing
09/15/2006
62
56
M59_MLB
SPI BOOTROM
09/15/2006
63
57
(MASTER)
ALS Support
(MASTER)
64
58
(MASTER)
Fan Connectors
(MASTER)
65
59
M59_MLB
Sudden Motion Sensor (SMS)
09/15/2006
66
60
M59_MLB
TPM
09/15/2006
67
61
M59_MLB
IMVP6 CPU VCore Regulator
09/15/2006
75
62
M59_MLB
5V / 1.5V Power Supply
09/15/2006
76
63
M59_MLB
2.5V & 1.2V Regulators
09/15/2006
77
64
(MASTER)
1.8V Supply
(MASTER)
78
65
(MASTER)
3.3V / 1.05V Power Supplies
(MASTER)
79
66
M59_MLB
3.3V G3Hot Supply & Power Control
09/15/2006
80
67
(MASTER)
Power Aliases
(MASTER)
81
68
(MASTER)
DC-In & Battery Connectors
(MASTER)
82
69
M59_LIO
PBus Supply & Batt. Charger
09/15/2006
83
70
(MASTER)
ATI M56 PCI-E
(MASTER)
84
71
(MASTER)
GPU (M56) Core Supplies
(MASTER)
85
72
(MASTER)
ATI M56 Core Power
(MASTER)
86
73
(MASTER)
ATI M56 Frame Buffer I/F
(MASTER)
87
74
M57_MLB_MG
GPU Straps
08/08/2006
88
75
(MASTER)
GDDR3 Frame Buffer A
(MASTER)
89
76
(MASTER)
GDDR3 Frame Buffer B
(MASTER)
90
77
(MASTER)
ATI M56 GPIO/DVO/Misc
(MASTER)
91
78
(MASTER)
ATI M56 Video Interfaces
(MASTER)
93
79
M57_MLB_MG
Internal Display Connectors
08/08/2006
94
80
M59_MLB
External Display Connector
09/15/2006
97
81
(MASTER)
M57 SPECIFIC CONNECTORS
(MASTER)
98
82
M59_MLB
LVDS Interface Pull-downs
09/15/2006
99
83
(MASTER)
Revision History
(MASTER)
100
84
(MASTER)
Napa Platform Constraints
(MASTER)
101
85
(MASTER)
More System Constraints
(MASTER)
102
86
(MASTER)
M9 Spacing & Physical Constraints
(MASTER)
103
87
(MASTER)
M57 NET PROPERTIES
(MASTER)
104
(MASTER)
(MASTER)
2
2
System Block Diagram
(MASTER)
(MASTER)
3
3
Power Block Diagram
(MASTER)
(MASTER)
4
4
BOM CONFIGURATION
(MASTER)
(MASTER)
5
5
Functional / ICT Test
(MASTER)
(MASTER)
6
6
Signal Aliases
M59_MLB
09/15/2006
7
7
CPU 1 OF 2-FSB
M59_MLB
09/15/2006
8
8
CPU 2 OF 2-PWR/GND
M59_MLB
09/15/2006
9
9
CPU Decoupling & VID
M59_MLB
09/15/2006
10
10
CPU MISC1-TEMP SENSOR
(MASTER)
(MASTER)
11
11
CPU ITP700FLEX DEBUG
M59_MLB
09/15/2006
12
12
NB CPU Interface
M59_MLB
09/15/2006
13
13
NB PEG / Video Interfaces
M59_MLB
09/15/2006
14
14
NB Misc Interfaces
M59_MLB
09/15/2006
15
15
NB DDR2 Interfaces
M59_MLB
09/15/2006
16
16
NB Power 1
M59_MLB
09/15/2006
17
17
NB Power 2
M59_MLB
09/15/2006
18
18
NB Grounds
M57_MLB_MG
08/08/2006
19
19
NB (GM) Decoupling
M59_MLB
09/15/2006
20
20
NB Config Straps
M59_MLB
09/15/2006
21
21
SB: 1 OF 4
M59_MLB
09/15/2006
22
22
SB: 2 of 4
M57_MLB_MG
08/08/2006
23
23
SB: 3 OF 4
M59_MLB
09/15/2006
24
24
SB: 4 OF 4
M59_MLB
09/15/2006
25
25
SB Decoupling
(MASTER)
(MASTER)
26
26
SB Misc
(MASTER)
(MASTER)
27
27
M57 SMBUS CONNECTIONS
M59_MLB
09/15/2006
28
28
DDR2 SO-DIMM Connector A
M59_MLB
09/15/2006
29
29
DDR2 SO-DIMM Connector B
(MASTER)
(MASTER)
30
30
Memory Active Termination
M59_MLB
09/15/2006
31
31
Memory Vtt Supply
M59_MLB
09/15/2006
32
32
DDR2 VRef
M59_MLB
09/15/2006
33
33
CLOCKS
M59_MLB
09/15/2006
34
34
Clock Termination
M59_MLB
09/15/2006
35
37
Mobile Clocking
(MASTER)
(MASTER)
36
38
PATA Connector
M59_MLB
09/15/2006
37
39
FireWire Link (TSB83AA22)
M59_MLB
09/15/2006
38
40
FireWire PHY (TSB83AA22)
M59_MLB
09/15/2006
39
41
ETHERNET CONTROLLER
M59_MLB
09/15/2006
40
42
Ethernet Connector
M59_MLB
09/15/2006
41
43
Yukon Power Control
M59_MLB
09/15/2006
42
44
FW PHY Power Supply
(MASTER)
(MASTER)
43
45
FireWire Port Power
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
P.61-68,71
P.69
P.48
P.55
P.59
P.57
P.53
P. 60
P.51-52
P.58
P.56
P.48,54
P.45
Camera
P.81
P.70-74,77-78
P.75-76
P.80
P.79
Dual-Channel LVDS
PWM
MUX
S-Video/Composite
Dual-Channel TMDS
LVDS Graphics
P.43
Port Power
PCIe x16
DMI x4
PCIe x1
Batt Chgr/
PBUS Supply
ICH7-M
SB
LPC 33MHZ
PHY Power
P.42
1394a/b (FireWire)
Supplies
RJ45 (Ethernet)
Connector
P.40
Power
Connectors
P.27
P.27
P.36
P.45
P.32
P.28
P.29
P.30-31
P.12-20
P.11
P.7-9
P.10
DVI-I/DL Connector
ENET
Frame Buffer
128MB/256MB
GPU
H8S/2116
SMBus x5
Analog
Battery SMBus
DDR2 SO-DIMM B
SMC SMBus
PWM/Tach
Connectors
Fan
SMS
FW
PCI
Yukon Power
INVERTER
CONNECTOR
Connector
ODD
Connector
Geyser KB /
TP Connector
16BITS
66MHZ
PATA
SB SMBus
USB
USB
SMBus
BootROM
SPI
SMC
Sensors
609 BGA
USB
GDDR3
THERMAL
CPU Core Duo
945GM
1466UFCBGA
NB
FSB
CH.B
CH.A
479 BGA
CPU Debug
ITP700FLEX
Connector
PCIe x1
Azalia (HD-Audio)
BUFFER
DDR2 VREF
Left I/O &
Audio Board
Connector
J2900
J2800
DDR2 SO-DIMM A
DDR2 VTT
& REGULATOR
SENSOR
w/TV-Out Support
USB x2
Connectors
P.44
TSB83AA22 FireWire
Controller
P.37-38
P.41
P.39
Yukon Gig-E
ATI M56P
(Merom)
Factory/Upper Connector
Expansion/Lower Connector
RT ALS
P.21-26
Debug
LPC
Connector
TPM
P.79,82
LCD Panel
Connector
Sensors
Temperature
P.33-34
Controller
CK410 Clock
P.68
HDD/BT
USB
SATA
Right USB 2.0
Connector
P.47
PCIe x1
Controller
P.78
USB
USB
Connector
USB 2.0 Hub/Sleep LED IR
P.46,81
051-7164
872
06004
System Block Diagram
SYNC_MASTER=(MASTER)
SYNC_DATE=(MASTER)
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
ACIN_ENABLE_DIV_L
J8290
Connector
LIO Power
J8290
MLB DC in
Connector
Q8250
PP18V5_G3H_CHGR
Q7615
ENABLE
(ISL6255AHRZ)
PM_SLP_S3_LS5V_L
5.0V
PP1V8_S3
1.8V
3.3V
PPVCORE_S0_GPU
PGOOD
IMVP_PWRGD_IN
U7530
PP3V3_S5
PP1V05_S0
1.05V
PM_SLP_S3_L
Q7845
ENABLES
PPVCORE_S0_CPU
U7750
Q7770
"IMVP6"
PGOOD
RSMRST_PWRGD
Inverter
Connector
PPBUS_S5_FWPORT
12.6V - 9V
FWPWR_EN
5V/1.5V
U8500
PP3V3_S0
NC
1.5V
PGOOD
S5
3.3V
ENABLE
PGOOD
1.05V
U7950
S0
GPU VCore
ENABLE
3.3V
NC
(LTC3412)
S3
PGOOD
1.2V
ENABLE
1.2V
PP1V2_S3
2.5V
PGOOD
PP1V5_S0
5.0V
PP5V_S5
NC
PGOOD
ENABLES
U7600
5V
1.5V
SMC_PM_G2_ENABLE
VR_PWRGOOD_DELAY
S0
CPU VCore
IMVP_VR_ON
S0
ENABLE
ENABLE
NC
1.8V
U7800
S3
ENABLE
PGOOD
PM_SLP_S3_L
U3100
0.9V (Vtt)
S0
PP0V9_S0
0.9V
Q4565
1.2V
PM_SLP_S3_LS5V_L
1.8V
PM_SLP_S4_L
PM_SLP_S3_L
Q7947
(ISL9504)
(TPS5117RGY)
(TPS51100)
(ISL6269B)
(ISL6269B)
(ISL6269B)
S3
S5S0
2.5V
ENABLE
(TPS62510)
PP1V2_D3C
P1V2R2V5D3C_EN_LS5V
PP2V5_S3
NC
Q7721
2.5V
P1V2R2V5DC3_EN_LS5V
PP2V5_D3C
2.5V
Q7720
PP2V5_S0
PM_SLP_S3_LS5V
Q7945
3.3V
PP3V3_S3
3.3V
Q4300
PP3V3_S3AC
PM_SLP_S3BATT
PM_SLP_S3BATT
5.0V
PP5V_S0
5.0V
Q3820
PP5V_S0_IDE_ODD
ODD_PWR_EN_L (SB GPIO14)
PM_SLP_S3BATT
PM_SLP_S4_LS5V
PM_SLP_S3_LS5V
U7700
IMVP_PWRGD_IN/ALL_SYS_PWRGD
U7900
SMC_PM_G2_ENABLE
1.1V - 0.95V
=GPUVCORE_EN_L
PP1V8_D3C
J9450
1.25V - 0.8V
(LTC3728)
12.6V - 9V
G3Hot
U8000
PP3V42_G3H
3.425V
ENABLE
(LT3470)
3.425
PPBUS_G3H
12.6 - 9V
PBUS
SUPPLY
U8300
PPBUS_G3H
5.0V
Q7610
PM_SLP_S4_LS5V
PP5V_S3
18.5V - 9V
PPDCIN_G3H
3 87
06004051-7164
Power Block Diagram
SYNC_MASTER=(MASTER)
SYNC_DATE=(MASTER)
TABLE_BOMGROUP_ITEM
DESCRIPTION
REFERENCE DES
BOM OPTION
QTY
PART NUMBER
CRITICAL
DESCRIPTION
REFERENCE DES
BOM OPTION
QTY
PART NUMBER
CRITICAL
DESCRIPTION
REFERENCE DES
BOM OPTION
QTY
PART NUMBER
CRITICAL
BOM OPTIONS
BOM NAME
BOM NUMBER
TABLE_BOMGROUP_HEAD
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
DESCRIPTION
REFERENCE DES
BOM OPTION
QTY
PART NUMBER
CRITICAL
DESCRIPTION
REFERENCE DES
BOM OPTION
QTY
PART NUMBER
CRITICAL
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
PART NUMBER
ALTERNATE FOR
PART NUMBER
BOM OPTION
REF DES
COMMENTS:
TABLE_ALT_HEAD
TABLE_ALT_ITEM
TABLE_ALT_ITEM
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
BOM OPTIONS
BOM GROUP
TABLE_BOMGROUP_HEAD
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
BOM OPTIONS
BOM GROUP
TABLE_BOMGROUP_HEAD
BAR CODE LABELS / EEE #’S
ALTERNATE PARTS
MODULE PARTS
IS
Extra TPM options:
SMC_TPM_GPIO2
SMC_TPM_GPIO1
SMC_TPM_PP
VRAM_128_SAMSUNG
VRAM_128SAM
VRAM_256SAM
GPU_MEM_256M,VRAM_256_SAMSUNG
U3301
359S0109
1
IC,LOW POWER CLOCK SYNTHESIZER,68PIN
CRITICAL
IC, BOOTROM, FINAL, LOCKED, M57
341S1925
1
CRITICAL
U6301
BOOTROM_FINAL
1
341S1924 CRITICAL
IC, BOOTROM, DEVELOPMENT, UNLOCKED ,M57
U6301
BOOTROM_DEVEL
SYNC_MASTER=(MASTER)
4
051-7164
SYNC_DATE=(MASTER)
87
06004
BOM CONFIGURATION
353S1461353S1465
Screened ISL6262 for ISL9504
ALL
152S0287 152S0435
ALL
Alternates for Coilcraft MSS5131
IC,SGRAM,GDDR3,8MX32,700MHZ,136 FBGA
U8900,U8950,U9000,U9050
VRAM_128_HYNIX
4
333S0358 CRITICAL
353S1461
U7530
1
CRITICAL
IC,ISL9504,SYNC REG CTL,QFN 48
1
IC,88E8053,GIGABIT ENET XCVR,64P QFN, NO
338S0270
U4101
CRITICAL
IC,SGRAM,GDDR3,8MX32,700MHZ,136 FBGA
U8900,U8950,U9000,U9050
VRAM_128_INFINEON
CRITICAL333S0376
4
333S0351
IC,SGRAM,GDDR3,16MX32,700MHZ,136 FBGA
U8900,U8950,U9000,U9050
VRAM_256_HYNIX
4
CRITICAL
376S0445
ALL
Si7806ADN for FDM6296
376S0448
128S0093
KEMET IS ALT TO SANYO
128S0092
ALL
128S0083
1.86 MAX ALT TO 1.9 MAX
128S0073
C2516
333S0377
IC,SGRAM,GDDR3,16MX32,600MHZ,136 FBGA
U8900,U8950,U9000,U9050
VRAM_256_INFINEON
CRITICAL
4
4
333S0350
U8900,U8950,U9000,U9050
IC,SGRAM,GDDR3,16MX32,700MHZ,136 FBGA
VRAM_256_SAMSUNG
CRITICAL
333S0354
U8900,U8950,U9000,U9050
4
CRITICAL
VRAM_128_SAMSUNG
IC,SGRAM,GDDR3,8MX32,700MHZ,136 FBGA
338S0368
IC,ATI,M56P,GRPHSCTRL,880BGA,LF
U8400
1
CRITICAL
ITP,LPCPLUS
M57_DEBUG
M57_COMMON4
BOOTROM_DEVEL,SMC_PRGRM
M57_COMMON3
LVDS_PD,FW_PORT_FAULT_PU
M57_COMMON2
KBDLED_HAS,MEMVREF_S3,MEMVTT_EN_PU,RTUSB_ESD,USB_C_OC_PU,USB_D_OC_PU,USB_E_OC_PU
ENET_LOWPWR_EN,ENETPWR_S3AC,GPU_BB_CTL,D3CPGOOD_3V3,ISL6255A,NO_3G
M57_COMMON1
ALTERNATE,COMMON,M57_COMMON1,M57_COMMON2,M57_COMMON3,M57_COMMON4,M57_DEBUG
M57_COMMON
[EEE:WJK]
LBL,P/N LABEL,PCB,28MM X 6 MM
826-4393
1
CRITICAL
EEE_WJK
M57_TPM
TPM
IC,PRGRM,SMC(NEW),M57
1
U5800
CRITICAL341S1931
SMC_PRGRM
IC,SMC,HS8/2116
1
338S0274
U5800
SMC_BLANK
CRITICAL
1
IC,EEPROM,SERIAL IIC,8KBIT,SO8
341S1797
U4102
CRITICAL
IC, TPM, 28-PIN TSSOP
TPM1
341S1789
U6700
CRITICAL
335S0384
IC,16MBIT 8-PIN SPI SERIAL FLASH,SOIC8
1
CRITICAL
BOOTROM_BLANK
U6301
TRUCKEE,2.33GHZ,B2,256VRAM,SAM,M57
VRAM_256SAM,M57_COMMON,CPU_2_33GHZ_B2,EEE_WJK
630-7814
337S3393
1
U0700
CRITICAL
CPU_2_33GHZ_B2
IC,MDC,B2,PRQ,2.33GHZ,34W,667M,4M,479 BGA
1
343S0385 CRITICAL
U2100
IC,ICH7M,BGA
1
338S0269 CRITICAL
U1200
IC,945GM,NORTHBRIDGE
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
FUNC_TEST
FUNC_TEST
FUNC_TEST
SMC TPs
Thermal Sensors
Left I/O Data Connector
FUNC_TEST
LPC+ Debug Connector
FUNC_TEST
(=PP2V5_S3_ENET)
(=PP3V3_S3_ENET)
(=PP1V2_S3_ENET)
FUNC_TEST
MAC-1 TPs
FUNC_TEST
Fan Connectors
FUNC_TEST
Battery Connector
Functional Test Points
FUNC_TEST
(=PP3V3_S0_CK410)
Power Nets
FUNC_TEST
Characterization TPs
Request for at least 10 GND TPs
Request for at least 10 GND test points
FUNC_TEST
Resistor Calibration
Left I/O Power Connector
FUNC_TEST
Request for at least 2 GND TPs per resistor
Camera Connector
Inverter Connector
Misc EXPOSED_VIA Nets
CPU FSB NO_TESTs
Misc NO_TESTs
EXPOSED_VIA
NO_TEST
EXPOSED_VIA
NO_TEST
EXPOSED_VIA
NO_TEST
Power Supply NO_TESTs
EXPOSED_VIA property indicates that the net
should have a via with 10-mil soldermask
opening for use as engineering probe point.
EXPOSED_VIA
I134
I135
I138
I139
I140
I141
I142
I143
I164
I165
I166
I167
I168
I169
I172
I173
I174
I175
I176
I177
I178
I179
I182
I183
I184
I185
I186
I187
I188
I189
I190
I191
I192
I193
I194
I195
I197
I198
I199
I200
I201
I202
I203
I204
I205
I206
I207
I208
I209
I210
I211
I212
I213
I214
I215
I216
I217
I218
I219
I220
I221
I222
I223
I224
I225
I227
I228
I229
I230
I231
I232
I233
I234
I235
I236
I237
I238
I239
I240
I241
I242
I243
I244
I245
I246
I247
I248
I249
I250
I251
I252
I253
I254
I255
I256
I257
I258
I259
I260
I261
I262
I263
I264
I267
I269
I273
I275
I276
I277
I278
I279
I280
I281
I282
I283
I285
I286
SYNC_DATE=(MASTER)
SYNC_MASTER=(MASTER)
051-7164 06004
875
Functional / ICT Test
TRUE
USB2_CAMERA_P_F
TRUE
USB2_CAMERA_N_F
TRUE
TP_FW_CTL<0>
TRUE
USB_BT_N
GPUBBP_ADJ
TRUE
P3V42G3H_FB
TRUE
P1V05S0_FSET
TRUE
TRUE
P3V3S5_FSET
TRUE
P3V3S5_COMP
TRUE
P5VS5_RUNSS
IMVP6_RBIAS
TRUE
GPUVCORE_COMP
TRUE
TRUE
P2V5S3_SHDNRT
TRUE
P1V2S3_RT
P1V2S3_RUNSS
TRUE
P1V8S3_COMP
TRUE
TRUE
P2V5S3_MODE
P1V05S0_COMP
TRUE
TRUE
GPUVCORE_FSET
P1V8S3_FSET
TRUE
TRUE
P1V5S0_RUNSS
TRUE
USB_BT_P
TRUE
SB_CLK100M_SATA_P
TRUE
SB_CLK100M_SATA_N
DMI_N2S_N<1..0>
TRUE
TRUE
DMI_N2S_P<1..0>
TRUE
FSB_REQ_L<4..0>
FSB_LOCK_L
TRUE
TRUE
FSB_HITM_L
FSB_HIT_L
TRUE
TRUE TRUE
FSB_DSTBP_L<3..0>
FSB_DSTBN_L<3..0>
TRUE TRUE
FSB_DRDY_L
TRUE
TRUE TRUE
FSB_DINV_L<3..0>
FSB_DBSY_L
TRUE
TRUE
FSB_D_L<63..0>
TRUE
FSB_BNR_L
TRUE
FSB_BREQ0_L
TRUE
FSB_ADSTB_L<1..0>
TRUE
TRUE
FSB_ADS_L
TRUE
FSB_A_L<31..3>
TRUE
PP5V_S0_ISENSECAL
TRUE
PPVCORE_D3C_GPU
TRUE
GND
PP5V_S3_CAMERA_F
TRUE
GND_CHASSIS_INVERTER
TRUE
TRUE
PPBUS_S0_INVERTER
PP5V_INVERTER_SW
TRUE
INVERTER_PWM
TRUE
GND_CHASSIS_INVERTER
TRUE
TRUE
PPVCORE_S0_CPU
PP1V05_S0
TRUE
PP1V8_S3
TRUE
TRUE
PP5V_S3
TRUE
USB2_CAMERA_N
TRUE
USB2_CAMERA_P
PM_SUS_STAT_L
TRUE
SMC_TDI
TRUE
SMC_TCK
TRUE
SMC_RST_L
TRUE
TRUE
SMC_NMI
TRUE
SMC_RX_L
TRUE
SV_SET_UP
TRUE
ISENSE_CAL_EN
TRUE
PCIE_WAKE_L
TRUE
SMC_BC_ACOK
SMBUS_SMC_A_S3_SDA
TRUE
TRUE
ACZ_SDATAIN<0>
ACZ_SDATAOUT
TRUE
LT2USB_OC_L
TRUE
PM_SLP_S3_LS5V
TRUE
PM_SLP_S4_L
TRUE
SYS_ONEWIRE
TRUE
MINI_CLKREQ_L
TRUE
SMC_EXCARD_CP
TRUE
TRUE
EXCARD_CLKREQ_L
LIO_PLT_RESET_L
TRUE
ACZ_SYNC
TRUE
USB2_LT_N
TRUE
USB2_LT_P
TRUE
TRUE
USB2_EXCARD_N
USB2_EXCARD_P
TRUE
TRUE
PCIE_EXCARD_R2D_C_N
TRUE
PCIE_EXCARD_D2R_N
PCIE_CLK100M_EXCARD_P
TRUE
PCIE_CLK100M_EXCARD_N
TRUE
PCIE_MINI_R2D_C_N
TRUE
USB2_LT2_P
TRUE
ACZ_RST_L
TRUE
EXCARD_OC_L
TRUE
LTUSB_OC_L
TRUE
TRUE
SMC_EXCARD_PWR_EN
TRUE
PM_DPRSLPVR
TRUE
GND
TRUE
IMVP_VR_ON
TRUE
PM_SLP_S3BATT
PM_SLP_S5_L
TRUE
P1V5P1V05S0_PGOOD
TRUE
FSB_CLK_CPU_P
TRUE
CPU_STPCLK_L
TRUE
FSB_CLK_NB_P
TRUE
PLT_RST_L
TRUE
PP1V8_S3
TRUE
PP1V8_D3C
TRUE
PP3V3_S5
TRUE
PP5V_S0
TRUE
PP5V_S3
TRUE
PP5V_S5
TRUE
PPBUS_G3H
TRUE
TRUE
PP3V3_S3
PP1V05_S0
TRUE
PP1V2_S3
TRUE
PP1V5_S0_NB
TRUE
PP1V5_S0
TRUE
PP1V2_D3C
TRUE
PP0V9_S0
TRUE
TRUE
FSB_SLPCPU_L
PP2V5_S0
TRUE
TRUE
FAN_LT_PWM
FAN_LT_TACH
TRUE
FAN_RT_PWM
TRUE
TRUE
PM_CLKRUN_L
TRUE
SMC_TMS
TRUE
DEBUG_RST_L
TRUE
SMC_TRST_L
TRUE
SMC_TDO
SMC_MD1
TRUE
TRUE
SMC_TX_L
PCI_CLK_PORT80_LPC
TRUE
PP3V3_FWPHY
TRUE
PP3V3_FWPHY_AVDD
TRUE
TRUE
PP3V3_FWPHY_PLLVDD
PP1V95_FWPHY
TRUE
PP1V95_FWPHY_PLLVDD
TRUE
PP1V2_S3
TRUE
PP3V3_S3AC
TRUE
TRUE
BATT_POS
TRUE
SMBUS_SMC_BSA_SCL
PP5V_S0
TRUE
SMC_BS_ALRT_L
TRUE
TRUE
SMBUS_SMC_BSA_SDA
PP2V5_D3C
TRUE
PP3V3_S0
TRUE
TRUE
INT_SERIRQ
TRUE
FWH_INIT_L
TRUE
LPC_AD<3>
TRUE
LPC_AD<2>
IMVP_DPRSLPVR
TRUE
PM_SLP_S4_L
TRUE
CPU_DPRSTP_L
TRUE
FSB_CLK_CPU_N
TRUE
TRUE
TPM_LRESET_L
FSB_CLK_NB_N
TRUE
TRUE
CLK_NB_OE_L
TRUE
NB_CLK100M_GCLKIN_P
TRUE
NB_CLK100M_GCLKIN_N
TRUE
NB_CLK_DREFCLKIN_P
TRUE
NB_CLK_DREFCLKIN_N
TRUE
NB_CLK_DREFSSCLKIN_N
TRUE
NB_CLK_DREFSSCLKIN_P
TRUE
CPU_THERMTRIP_R
TRUE
TP_SB_SUS_CLK
TRUE
TP_CPU_CPUSLP_L
TRUE
CPU_DPSLP_L
TRUE
PM_LAN_ENABLE
TRUE
PCI_RST_L
TRUE
PM_SB_PWROK
TRUE
PM_RSMRST_L
TRUE
SB_RTC_RST_L
TRUE
PM_STPCPU_L
TRUE
PM_STPPCI_L
TRUE
VR_PWRGD_CK410
TRUE
VR_PWRGOOD_DELAY
TRUE
FSB_CPURST_L
TRUE
FSB_DPWR_L
TRUE
NB_SB_SYNC_L
TRUE
CPU_PWRGD
TRUE
PP2V5_S0_GPU_TPVDD
TRUE
PP2V5_S0_GPU_TXVDDR
TRUE
PP2V5_S0_GPU_AVDD
TRUE
PP2V5_S0_GPU_A2VDD
TRUE
PP2V5_S0_GPU_LPVDD
TRUE
PP2V5_S0_GPU_LVDDR
PP3V3_S0
TRUE
PP3V3_S0_CK410_VDD_REF
TRUE
TRUE
PP3V3_S0_CK410_VDD48
TRUE
PP3V3_S0_CK410_VDD_PCI
TRUE
PP3V3_S0_CK410_VDD_CPU_SRC
PM_SLP_S3_L
TRUE
TRUE
PP3V3_S0_CK410_VDDA
PP2V5_S3_ENET_AVDD
TRUE
PP2V5_S3
TRUE
PEG_RESET_L
TRUE
TRUE
PLT_RST_L
TRUE
IMVP6_VID<6..0>
SMC_LRESET_L
TRUE
GND
TRUE
TRUE
BATT_NEG
FAN_RT_TACH
TRUE
TRUE
ALS_GAIN
PCIE_EXCARD_D2R_P
TRUE
TRUE
USB2_LT2_N
PCIE_MINI_D2R_P
TRUE
TRUE
PP18V5_DCIN
TRUE
PPBUS_G3H
TRUE
PP1V5_S0
RSFSTHMSNS_D_P
TRUE
TRUE
HSTHMSNS_DX_P
TRUE
HSTHMSNS_DX_N
RSFSTHMSNS_D_N
TRUE
TRUE
SMC_ONOFF_L
TRUE
PM_SYSRST_L
PP5V_S0
TRUE
PP3V42_G3H
TRUE
LPC_AD<0>
TRUE
LPC_AD<1>
TRUE
LPC_FRAME_L
TRUE
TRUE
BOOT_LPC_SPI_L
TRUE
SMBUS_SMC_A_S3_SCL
SMBUS_SB_SDA
TRUE
SMBUS_SB_SCL
TRUE
TRUE
PCIE_EXCARD_R2D_C_P
TRUE
LTALS_OUT
ACZ_BITCLK
TRUE
PCIE_MINI_R2D_C_P
TRUE
PCIE_CLK100M_MINI_P
TRUE
PCIE_CLK100M_MINI_N
TRUE
PCIE_MINI_D2R_N
TRUE
82D5 82C6 82B3 82A4
79D3 79A8 71D2 67C5 67C3 67B3 67A3 66B6
66B5 66B1 65D6 65B3 62A6
61D8 61A5 60D4 60C7 58C7 58C4 57B6 54D4
54B5 52D3 49C7 49C4 49B5
40B6 36D6 34A8 33D8 33D3 33C7
29A6 29A3
67D8
67D8
28A6
67D6
67D6
27D8
65A2
65A2
27D5
55A4
55A4
27D3
34C8
34C8
27C3
34C6
34C6
26D1
34B8
34B8
26B8
25D3
25D3
26B6
25C4
79D5
25C4
26B4
24D3
67D5
24D3
25D8
24C3
67D3
24C3
25D3
21C1
67C3
21C1
25C6
19D7
66C5
19D7
25C4
81D4
19D6
65D8
19D6
81B3
25B8
81B3
69C8
19D5
65D2
19D5
67C8
80B5
25B4
80B5
69B8
19D2
65D1
19D2
67C6
80A1
25A4
67C8
80A1
69A8
19D1
65C8
79B7
19D1
67B6
79B8
24D3
79B7
67C6
79B8
68B8
19C8
67B8
63D8
71D7
19C8
62A7
71A6
24C3
71D7
66C5
71A6
67D5
17D6
67B6
56D4
71D7
69C1
17D6
19D7
67B3
24B5
69C1
62C1
67B3
67D3
17D3
64C1
26C5
67C3
68D5
17D3
19D6
67B1
24B3
68D5
62A8
67B1
66D2
16D3
64A6
25D2
67C1
67C3
16D3
19D5
82D3
67A1
23D5
67C3
48B6
67A1
66C8
16C8
37B2
82D7
25C8
67B1
67C1
16C8
19D2
82C5
66B5
23B3
67C1
25D6
66B5
66A8
13B5
32C6
76D8
25B6
66D8
65D6
13B5
19D1
67B6
62B1
22B5
65D6
25C8
62B1
53C4
81C3
81C3
12C2
66B8
82A4
31C5
76D5
24C3
66B8
65B7
12C2
19C5
67A8
61D7
66B8
21D3
66C8
82A4
65B7
25C6
61D7
52D7
48B3
48B3
12B7
66A6
79A8
29D6
75D8
24B3
65D6
64D7
12B7
19C4
67A6
58C7
66A6
21C3
66C6
79A8
64D7
25C2
58C7
52B7
46B6
46B6
12A7
64C8
26C3
29D3
75D5
24A5
65B7
64A6
12A7
19C1
66B5
44B8
67D3
58C4
64C8
20B4
66B6
26C3
64A6
25B6
58C4
52B5
33B6
33B6
87D6
77A7
67D3
11C5
81C6
51C5
26C1
29B2
73B8
23D8
81C6
64C8
62D7
11C5
19B8
63D1
44A8
67D1
57B5
51C5
20A4
65B8
26C1
62D7
25B2
57B5
52B1
29A6
29A6
12D6
72D8
79A6
79A6
67D1
11B3
81C4
81C3
48C3
26B1
28D6
73B5
23D4
81C4
62C8
61D7
11B3
19B5
19D7
43B8
41C4
55A8
82D7
48C3
19C7
55C3
26B1
61D7
25A8
55A8
51D4
28A6
28A6
87D6
87D6
87D6
12C6
71C1
79A5
79A5
61D1
9B7
67B3
51B5
66C7
47C7
52B3
26A4
28D3
73A8
23D1
67B3
62B6
61D4
9B7
67D8
19A5
19C5
42C4
42C1
67D8
39D8
53C4
78C8
47C7
19C6
51C5
67B8
26A4
61D4
24B5
53C4
51D3
81C3
27D8
27D8
81A4
81A4
12B4
12B4
12B4
12B6
87D6
71B7
45C5
45C5
55D7
8C7
67B1
45C3
45B3
60C6
53B5
69A6
48B6
48C3
66C6
41B6
48C6
48C6
48C6
48C6
50B6
48C6
48C3
48C3
66B5
22A6
28B2
73A5
23B7
67B1
62B2
55D3
8C7
67D6
17C6
19A8
53B4
38D7
38D5
67D6
39D6
68B2
36D6
68B2
77C6
53C5
41B6
17C6
43C8
67B6
22A6
50C6
48C6
50C6
55D3
24A5
36D6
51C2
51B5
27D7
27D7
50C6
22C2
22C2
34C5
34C5
87D6
7C4
7C4
7C4
7C4
87C6
12D4
67A8
45B5
45B5
55A6
7D5
62A2
22C2
22C2
53B5
52B3
68A6
27C6
22D8
62B3
23C3
48C3
48C3
22C2
22C2
22C2
22C2
50B5
48B6
48B6
22C2
22D8
22D8
87C6
66B3
34D5
34D5
14B7
19D7
72B8
23A7
62A2
62A4
43D8
7D5
63B3
17B6
19A6
60C6
52B3
38B5
38B2
63B3
39B8
51B5
31C5
51B5
77A8
60C6
52D5
60C6
60C6 23C3
34D5
34D5
34C5
34C5
34B5
34B5
87D6
14D6
42A8
63D4
14B7
50C5
22C2
50C5
43D8
24A3
81C4
31C5
47B5
60C6
60C6
60C6
48B6
27D6
27D6
48C6
48C6
50C5
6C3
6C3
34C3
34C3
12B4
87D6
87D6
87D6
7C3
7C3
87D6
7C3
87D6
7C3
87D6
87D6
12C4
87D6
12C4
67A6
6A8
6A8
9D7
7B6
52B8
6D3
6D3
52A2
53B5
53B5
53B5
52B2
53B5
48C3
52A2
27C5
87B4
87B4
22C4
48C3
6A2
52B2
34A4
52A2
34A4
87B4
6D3
6D3
6C3
6C3
50C6
50B3
34C5
34B5
50C6
6C3
87B4
22C4
22C4
61C8
52A2
66B2
34D3
87C6
34D3
6C7
16B6
67B8
22D8
52B8
52B5
42B8
7B6
39D7
16D1
19A4
53C4
53B4
53B4
52B2
6C6
6C6
39D7
39B5
69B1
27C3
25D8
68B2
27C3
67A8
53C5
52D3
53C5
53C5
6A2
61C7
34D3
34D3
34C4
34C4
34B4
34B4
34B4
34B4
23C3
87C6
61C7
12C4
87D6
87C6
14C7
39C8
63D3
6C7
51B5
50C3
6C3
50C3
42B8
9B7
52C6
51B7
25D8
35B7
53C4
53C4
53C4
53B4
27C6
27C6
27C6
50C6
87B4
50C6
34D5
34D5
50C3
6C2
66A6
63B7
66C6
6C2
33B4
33B4
22D2
22D2
12A4
12B4
12B4
12B4
7B4
7B4
12B4
7B4
12B4
7B4
12C4
12C4
7D8
12C4
7D8
55C7
6A6
6A6
8D7
7B5
45C3
6D2
6D2
51C5
52B2
52B2
52D6
53B5
51C7
23C3
55A8
39C6
51C5
27C3
48B3
48B3
6C3
6A2
6A1
51B7
34A3
51B7
34A3
48C3
48B3
6D2
6D2
6C2
6C2
50C5
48B6
34C3
34B3
50C5
6C2
48B3
6C3
6D3
51B7
23C3
61C7
51C5
65B8
33C4
21C4
33C4
6C6
14C2
67B6
22C6
45C3
47C7
41C6
7B5
39A8
13D2
12A4
17D6
51C5
52B2
53B4
53B4
52B2
53B4
51C7
53C5
6C5
6C5
39A8
39B4
68A2
27C2
5D4
52B2
27C2
67A6
51C7
51D5
51C7
51C7
87C6
6A1
21C4
33C4
60B7
33C4
33B4
33B4
33B4
34B2
34B2
33B4
33B4
6C7
21C4
51D7
37C2
26A6
51D7
26D4
33C4
33C4
26B8
26B5
11B5
12B4
22A6
21C4
10C5
32B3
40D5
63C3
70A5
6C6
61C7
51C7
68B2
48C4
48B6
6C2
48C6
68C5
41C6
8B7
52B2
26C5
5D4
27C3
51D7
51D7
51C7
51C7
27C5
27B6
27B6
50C5
57C7
48B3
50C5
34D4
34D4
48C6
45B5
45B5
37C3
6C1
71B7
66C3
65B7
65D6
65C6
62C5
61C7
71C7
63B6
41C4
65A7
71C7
62C4
6C1
21B6
21B6
14B4
14B4
7D8
7D6
7D6
7D6
7B3
7B3
7D6
7B3
7D6
7B3
7D6
7D6
7C8
7D6
7C8
55A5
45C5
5B2
79B5
79B5
79A5
5B2
8B5
5D4
5D4
6D1
6D1
23C5
51B5
51C5
51C3
51C1
47B5
23B6
51B7
23C8
48C3
27B3
21C7
21C7
6C1
6A1
5C4
48C3
33B4
48C3
33B4
26C1
21C7
6D1
6D1
6C1
6C1
48B6
22D4
33B4
33B4
48C6
6C1
21C7
6C1
6D1
48C3
14B7
51D7
41B5
23C3
61C7
7C6
7C8
12A6
5C4
5B2
64A4
11B5
5B2
25C8
5A1
5B2
5A4
13C5
7A3
17C6
58B6
58B6
58B3
23C8
51B5
26B1
51C1
51B5
51C1
47B5
34D6
6C3
38D5
38C6
6C3
38D3
5D4
39A5
68A1
27C1
5D2
51C5
27C1
63C1
23C8
21C4
21D4
21D4
61C7
5C1
7B3
7C6
26B1
12A6
14B6
14C4
14C4
14C4
14C4
14C4
14B4
21C2
6C6
21C4
7B3
23C3
22A6
23C3
23C1
21D6
23C8
23C8
23C5
14B6
7D6
7B3
14B6
7B3
78C7
78C7
78C7
78B7
78B7
78B7
5D4
33C5
23C3
39D5
39D3
26B1
5C4
9C1
26B1
68B1
58B3
6D5
22D4
6C1
22D4
68B8
5C4
5D4
54D5
54C5
54C5
51C5
23C5
5D2
26D6
21D4
21D4
21C5
22B3
27C3
23D5
23D5
48B6
48C3
21C7
48C6
33B4
33B4
22D4
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
Chassis connection to be made at the fan cutout near the right ALS. Not stuffed at Proto.
Chassis connection to be made on FW shell
Chassis connection to be made at the mounting hole east of the LVDS connector
Chassis connection to be made at the mounting hole southwest of the USB connector. Plated hole.
USB Port "G" = Bluetooth (M13P)
USB Port "H" = 2nd Left USB 2.0 Port
LVDS Pull Down Aliases
LEFT CLUTCH BARREL CABLING
Inverter PWM Reset Alias
NOTE: NB_CFG<13..12> require test access
FireWire Aliases
Add one through via per hole to GND or 2 blind vias per side per hole to GND
Top CPU TM Hole
Top GPU Right TM Hole
Right CPU TM Hole
NOTE: BOM options "USB_G_OC_PU" and
"ENET_LOWPWR_EN" are mutually-exclusive.
USB Port "E" = ExpressCard
USB Port "F" = USB 1.1 Hub
USB Port "D" = Camera
USB Port "B" = Trackpad (Geyser)
USB Port "A" (Debug Port) = Right USB 2.0 Port
USB Port "C" = Left USB 2.0 Port
Ethernet Powr Management Support
Lower Left GPU TM Hole
Thermal Module Holes
Frame holes
Left CPU TM Hole
Base net is PM_SLP_S4_L
Base net is PM_SLP_S3_LS5V
Chassis connection to be made at the mounting hole northwest of the DVI connector. Plated hole.
195R106
ZT0600
HOLE-VIA-P5RP25
ZT0603
1
HOLE-VIA-P5RP25
ZT0602
1
0
5%
1/16W
MF-LF
402
R0600
1 2
402
5%
1/16W
0
MF-LF
ENET_LOWPWR_EN
R0690
1 2
5%
1/16W
0
402
MF-LF
NO STUFF
R0601
1 2
0G-502620R
EMI-SPRING
NO STUFF
SH0601
1
402
X7R
50V
10%
0.01UF
C0613
1
2
402
X7R
50V
10%
0.01UF
C0619
1
2
10%
50V
X7R
402
0.01UF
C0615
1
2
HOLE-VIA-P5RP25
ZT0612
1
HOLE-VIA-P5RP25
ZT0611
1
HOLE-VIA-P5RP25
ZT0610
1
50V
10%
0.01UF
X7R
402
C0600
1
2
50V
0.01UF
10%
X7R
402
C0602
1
2
195R106
ZT0601
402
X7R
50V
10%
0.01UF
C0612
1
2
10%
50V
X7R
402
0.01UF
C0614
1
2
0.01UF
10%
50V
X7R
402
C0616
1
2
0.01UF
10%
50V
X7R
402
C0611
1
2
0.01UF
10%
50V
X7R
402
C0610
1
2
HOLE-VIA-P5RP25
ZT0613
1
0.01UF
10%
50V
X7R
402
C0618
1
2
0.01UF
10%
50V
X7R
402
C0617
1
2
HOLE-VIA-P5RP25
ZT0614
1
SHLD-SM-LF
OG-503040
SH0600
1
2
3
HOLE-VIA-P5RP25
ZT0604
1
MF-LF
402
0
1/16W
5%
NO STUFF
R0602
1 2
Signal Aliases
SYNC_DATE=(MASTER)
SYNC_MASTER=(MASTER)
051-7164 06004
876
VOLTAGE=0V
MIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.5 mm
GND_CHASSIS_FANFRAME
VOLTAGE=0V
MIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.5 mm
GND_CHASSIS_DVI_TOP
MAKE_BASE=TRUE
MIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.5 mm
MAKE_BASE=TRUE
VOLTAGE=0V
GND_CHASSIS_DVI_BOT
NC_CPU_A34_L
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_CPU_A36_L
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_CPU_A37_L
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_CPU_APM1_L
NO_TEST=TRUE
MAKE_BASE=TRUE
USB_HUB_P
USB_HUB_N
LT2USB_OC_L
USB2_LT2_N
=LVDS_PD_U_CLK_N
=LVDS_PD_U_CLK_P
LVDS_U_DATA_N<0>
=LVDS_PD_U_DATA_N<1>
LVDS_U_CLK_N
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=0V
MIN_LINE_WIDTH=0.5 mm
GND_CHASSIS_LNDACARD_HOLE
GND_CHASSIS_LEFT_DIMM_HOLE
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=0V
MIN_LINE_WIDTH=0.5 mm
GND_CHASSIS_ODD_HOLE
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=0V
MIN_LINE_WIDTH=0.5 mm
GND_CHASSIS_BATTCONN_HOLE
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=0V
MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.5 mm
VOLTAGE=0V
GND_CHASSIS_LIOFLEX_HOLE
MIN_NECK_WIDTH=0.25 mm
GND_CHASSIS_BATTCONN_HOLE
PCI_GNT3_L
MAKE_BASE=TRUE
MAKE_BASE=TRUE
PCI_REQ3_L
LVDS_L_DATA_N<1>
MAKE_BASE=TRUE
NC_CPU_A33_L
MAKE_BASE=TRUE
NO_TEST=TRUE
USB_BT_N
USB2_LT2_P
USB2_LT2_N
MAKE_BASE=TRUE
LT2USB_OC_L
MIN_NECK_WIDTH=0.20 mm
PP3V3_FWPHY
MIN_LINE_WIDTH=0.38 mm
MAKE_BASE=TRUE
VOLTAGE=3.3V
VOLTAGE=1.95V
MIN_LINE_WIDTH=0.38 mm
MAKE_BASE=TRUE
PP1V95_FWPHY
MIN_NECK_WIDTH=0.25 mm
NC_CPU_SPARE4
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
PPFW_PORTB_VP_UF
PP1V95_FWPHY
SMC_RSTGATE_L
=FW_PCI_IDSEL
PCI_GNT3_L
PCI_REQ3_L
NC_CPU_EXTBREF
NB_CFG<6>
NB_CFG<4..3>
ALS_GAIN
NC_CPU_APM0_L
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_CPU_A39_L
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_CPU_A38_L
NC_CPU_A35_L
NC_CPU_A34_L
PP3V3_FWPHY
MAKE_BASE=TRUE
SMC_RSTGATE_L
PP1V95_FWPHY
PP3V3_FWPHY
PP3V3_FWPHY
PP3V3_FWPHY
PP3V3_FWPHY
PP3V3_FWPHY
PPFW_PORTB_VP_UF
ENET_LOWPWR_EN
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_ENET_CTRL12 NC_ENET_CTRL12
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_ENET_CTRL25
RTALS_GAIN
MAKE_BASE=TRUE
RTALS_GAIN
NC_CPU_SPARE0NC_CPU_SPARE0
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_CPU_HFPLL
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_CPU_SPARE2
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_CPU_SPARE2
NC_CPU_SPARE1
NC_CPU_EXTBREF
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_CPU_A38_L
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_CPU_SPARE1
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_CPU_SPARE4
MEM_B_A<15..14>
NB_CFG<15..14>
NB_CFG<8>
MEM_A_A<15..14>
NC_CPU_A32_L
MAKE_BASE=TRUE
NO_TEST=TRUE
PP1V95_FWPHY
NB_CFG<13..12>
MAKE_BASE=TRUE
PCI_AD<19>
NB_CFG<17>
NC_CPU_HFPLL
NC_CPU_A32_L
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_MEM_B_A<15..14>
MAKE_BASE=TRUE
TP_NB_CFG<4..3>
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_MEM_A_A<15..14>
SB_GPIO30
USB2_RT_PUSB2_RT_P
MAKE_BASE=TRUE
USB2_RT_P
USB2_RT_N
RTUSB_OC_L
USB_TRACKPAD_N
USB_TRACKPAD_P
UNUSED_USB_B_OC_L
MAKE_BASE=TRUE
UNUSED_USB_B_OC_L
USB2_LT_P
USB2_LT_N
LTUSB_OC_L
MAKE_BASE=TRUE
LTUSB_OC_L
USB2_CAMERA_P
MAKE_BASE=TRUE
USB2_RT_NUSB2_RT_N
RTUSB_OC_L
MAKE_BASE=TRUE
RTUSB_OC_L
MAKE_BASE=TRUE
USB_TRACKPAD_PUSB_TRACKPAD_P
MAKE_BASE=TRUE
USB_TRACKPAD_NUSB_TRACKPAD_N
USB2_LT_P
MAKE_BASE=TRUE
USB2_LT_P
MAKE_BASE=TRUE
USB2_LT_NUSB2_LT_N
USB2_CAMERA_P
MAKE_BASE=TRUE
USB2_CAMERA_P
UNUSED_USB_D_OC_LUNUSED_USB_D_OC_L
MAKE_BASE=TRUE
USB2_CAMERA_N
USB2_EXCARD_N
USB2_EXCARD_P
EXCARD_OC_LEXCARD_OC_L
MAKE_BASE=TRUE
USB_BT_P
USB_BT_N
USB2_CAMERA_N
MAKE_BASE=TRUE
USB2_CAMERA_N
MAKE_BASE=TRUE
USB2_EXCARD_PUSB2_EXCARD_P
MAKE_BASE=TRUE
USB2_EXCARD_N
USB_BT_P
USB_BT_N
MAKE_BASE=TRUE
USB2_LT2_P
MAKE_BASE=TRUE
USB2_LT2_P
LVDS_L_DATA_P<1>
MAKE_BASE=TRUE
=LVDS_PD_L_CLK_N
=LVDS_PD_L_CLK_P
MAKE_BASE=TRUE
LVDS_L_DATA_P<0>LVDS_L_DATA_P<0>
LVDS_L_DATA_N<0>
MAKE_BASE=TRUE
LVDS_L_DATA_N<0>
MAKE_BASE=TRUE
LVDS_L_CLK_NLVDS_L_CLK_N
MAKE_BASE=TRUE
LVDS_L_CLK_PLVDS_L_CLK_P
LVDS_L_DATA_N<2>
MAKE_BASE=TRUE
=LVDS_PD_L_DATA_P<2>
LVDS_L_DATA_P<2>
MAKE_BASE=TRUE
=LVDS_PD_L_DATA_N<2>
MAKE_BASE=TRUE
LVDS_U_DATA_N<1>
MAKE_BASE=TRUE
LVDS_U_DATA_P<1>
MAKE_BASE=TRUE
LVDS_U_DATA_N<0>
LVDS_U_DATA_P<0>
MAKE_BASE=TRUE
LVDS_U_DATA_P<0>
MAKE_BASE=TRUE
LVDS_U_DATA_P<2>
=LVDS_PD_U_DATA_P<1>
LVDS_U_DATA_N<2>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
LVDS_U_CLK_N
LVDS_U_CLK_P
MAKE_BASE=TRUE
LVDS_U_CLK_P
PM_SLP_S4_LPM_SLP_S4_L
PM_SLP_S3_LS5VPM_SLP_S3_LS5V
USB_HUB_P USB_HUB_P
MAKE_BASE=TRUE
TP_USB2_3G_N
USB_HUB_N
USB2_EXCARD_N
TP_USB2_3G_P
NC_ENET_CTRL25
PPFW_PORTA_VP_UF
MAKE_BASE=TRUE
PPFW_PORTA_VP_UF
NC_CPU_A36_L
NC_CPU_A33_L
GND_CHASSIS_INVERTER
NC_CPU_A39_L
TP_SB_SUS_CLK
MAKE_BASE=TRUE
TP_NB_CFG<13..12>
NB_CFG<11..10>
MAKE_BASE=TRUE
TP_SB_SUS_CLK
MAKE_BASE=TRUE
TP_NB_CFG<17>
MAKE_BASE=TRUE
TP_NB_CFG<15..14>
MAKE_BASE=TRUE
TP_NB_CFG<11..10>
MAKE_BASE=TRUE
TP_NB_CFG<8>
MAKE_BASE=TRUE
TP_NB_CFG<6>
PLT_RST_LPLT_RST_L
NC_CPU_APM1_L
NC_CPU_APM0_L
NC_CPU_A35_L
NO_TEST=TRUE
MAKE_BASE=TRUE
TP_USB2_3G_N
MAKE_BASE=TRUE
TP_USB2_3G_P
MAKE_BASE=TRUE
MAKE_BASE=TRUE
USB2_LT2_N
MAKE_BASE=TRUE
USB_BT_P
USB_HUB_N
MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.5 mm
MAKE_BASE=TRUE
VOLTAGE=0V
MIN_NECK_WIDTH=0.25 mm
GND_CHASSIS_INVERTER
GND_CHASSIS_INVERTER
GND_CHASSIS_INVERTER
NC_CPU_A37_L
GND_CHASSIS_INVERTER
GND
MIN_LINE_WIDTH=0.5 mm
GND_CHASSIS_USB
MAKE_BASE=TRUE
VOLTAGE=0V
MIN_NECK_WIDTH=0.25 mm
MAKE_BASE=TRUE
GND_CHASSIS_LVDS
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=0V
MIN_LINE_WIDTH=0.5 mm
GND_CHASSIS_USB
GND_CHASSIS_USB
GND_CHASSIS_USB
GND_CHASSIS_LVDS
GND_CHASSIS_LVDS
GND_CHASSIS_LVDS
GND_CHASSIS_LVDS
GND_CHASSIS_ENET
GND_CHASSIS_ENET
GND_CHASSIS_ENET
GND_CHASSIS_DVI_BOT
GND_CHASSIS_DVI_BOT
GND_CHASSIS_DVI_TOP
GND_CHASSIS_DVI_TOP
GND_CHASSIS_ENET
VOLTAGE=0V
MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
66B8 66B8
44B8
44B8
44B8
44B8
44B8
44B8
66A6
66A6
82A4 82A4
44A8
44B8
44A8
44A8
44A8
44A8
44A8
64C8
64C8
79A8 79A8
43B8
44A8
43B8
43B8
43B8
43B8
43B8
51C5
51C5
26C3 26C3
42C4
42C1
42C1
43B8
42C1
42C4
42C4
42C4
42C4
42C4
48C3 48C3
79A6
26C1 26C1
79A6
79A6
79A6
38D7
38D5
38D5
42C4
38D5
38D7
38D7
38D7
38D7
38D7
42C1
47C5
48C6
48C6
45B3
52B3
52B3
45C3
48C6
48C6
81A4
48C6
47C7 47C7
66C7
66C7
46B7
79A5
26B1 26B1
48C6
81A4
46B3
79A6
79A5
79A5
79A5
79D3
79D3
79D3
79D3
46B7
46B3
48C3
48C6
82C8
82C3
81A4
48C6
48C6
48C3
38B5
38B2
38B2
38D7
38B2
38B5
38B5
38B5
38B5
38B5
38D5
47B5
47C5
48C6
48C6
48C3
48C3
45B3
47B5
22D8
47C5
81C4
81C4
22C2
48C6
22C2
48C6
22C2
45B3
45C3
48C6
48C6
48C3
48C3
81A4
81A4
22C2
45C3
22C2
48C6
22C2
81A4
22C2
48C6
22C2
82D8 82D8
82D8 82D8
82D8 82D8
82C8 82C8
82C8
82C8 82C8
82C3
82C3 82C3
41B6 41B6
66C6 66C6
46B3
48C6
45C5
26A4 26A4
22C2
22C2
46A7
79A5
45C5
45C5
45C5
79D3
47B2
47B2
47B2
79D2
79D2
79D2
79D2
44C1
44C1
44C1
80B5
46B3
46A7
22D8
22C2
82C3
82B8
37D3
22C2
22C2
22C2
22D8
6C6
6C6
6C6
37D3
38B5
6C6
6C6
6C6
6C6
6C6
6C6
38B2
47B5
22C2
47B5
47B5
22D8
81C4
81C4
22C2
22C2
22D8 22D8
22C2
22C2
47B5
22C4
22D8
22C2
81C4
22C2
81C4
6D3
22C2
6D3
22C2
6D3
22C2
22C2
22C2
22C2
22D8 22D8
22C2
22C2
6D3
22C2
6C3
22C2
6C3
22C2
6C3
22C2
6C3
82C3 82C3
82C3 82C3
82C3 82C3
82C3 82C3
82C3
82C3 82C3
82B8
82B8 82B8
23C3 23C3
62B3 62B3
22C2
22C2
45B5
22A6 22A6
6C3
6C3
22C2
45C5
45B5
45B5
45B5
47B2
79D2
44A3
44A3
44A3
79C3
79C3
79C3
79C3
44A1
44A1
44A1
80B5
80B5
80A5
80A5
44C1
80A5
80A2
22C2
22C2
22C4
6C3
79D7
79D7
37D3
26D2
82C3
6C2
6C2
6C2
22C4
6C3
6C3
44B3
6C5
51D7
37D3
26D2
51B5
6C5
51D7
6C5
6C5
6C5
6C5
6C5
6C5
44B3
6C5
22C2
6D3
22C2
22C2
22C4
22C2
22C2
22D8 22D8
6D3
6D3
22C4 22C4
6D3
6D3
22C2
6D3
22C4
6D3
22C2
6D3
22C2
6D1
6D2
6D1
6D2
6D1
6D2
22D8 22D8
6D3
6C3
6C3
22C4 22C4
6C3
6C3
6D1
6D2
6C1
6C2
6C1
6C2
6C1
6C3
6C1
82C3
79D7 79D7
79D7 79D7
79D7 79D7
79D7 79D7
82C3
82C3
82C3
82C3
79D7
79D7 79D7
82B3
82C3
79D7
79D7 79D7
6A2 6A1
48C3 48C3
6C3
6C2
44D3
44D3
6A8
23C3 23C3
14B7 14B7
6C1
6C1
6C3
45B5
6A8
6A8
6A8
44A3
79C3
44A1
44A1
44A1
79B2
79B2
79B2
79B2
40B2
40B2
40B2
80A2
80A2
80A3
80A3
44A1
80A3
6B6
7B8
7B8
7B8
7B8
6C3
6C3
6C3
6C2
78B3
78B3
69A1 69A1
22B6
22B6
79D7
7B8
6C1
6C1
6C1
6C1
5A4
5A4
7B6
43A2
6C3
37A8
22B6
22B6
7B6
48C4
7B8
7B8
7B8
7B8
7B8
6C3
37A8
6C3
6C3
6C3
6C3
6C3
6C3
43A2
39C8 39C8
39C8
57C4
7B6
7B6
7B8
7B6
7B6
7B6
7B6
7B8
7B6
7B6
7C8
6C3
37C6
7B8
7C8
22D8
6D3
6D1
6D2
6D3
6D3
6D3
6D3
22C4 22C4
6D2
6D2
6D3 6D1
6D2
6D1
6D2
6D1
6D2
6D1
6D2
6D1
6D2
5C1
6D1
5C1
6D1
5B2
6D1
22C4 22C4
6D2
6C2
6C2
6C3 6C1
6C2
6C2
5B2
6D1
5C1
6C1
5C1
6C1
5A7
6C2
5B1
79D7
78A3 78A3
78A3 78A3
78A3 78A3
78A3 78A3
79D7
79D7
79D7
79D7
78B3
78B3 78B3
79D7
79D7
78B3
78B3 78B3
5C4 5C4
6A2 6A1
6C1
46C3
6C1
46C3
39C8
43B2
43B2
7B8
7B8
6A6
7B8
6C7 6C6
6C7 6C6
7B8
7B8
7B8
46C3
46C3
5B1
5A7
6C1
6A6
6A6
6A6
7B8
6A6
44A1
79B2
6A8
6A8
6A8
6A8
6A8
6A8
6A8
6A8
6A8
6A8
6B8
6B8
6B8
6B8
40B2
6B6
6A6
6D7
6D7
6D7
6C7
6C2
6C2
5C1
5B1
82B8
82B8
6B1
82B8
6A1
6A4 6A6
6B3
6B3
78A3
6D7
5A7
5B1
5B1
5C1
6C7
6C3
5A4
6C5
37B7
6B5
6B5
6C8
14C6
14C6
5C1
6D7
6D7
6D8
6D8
6D8
5A4
6C3
5A4
5A4
5A4
5A4
5A4
5A4
6C5
39B8
6D4 6D5
6D4
6D4
6C8 6C7
6C7
6C7 6C8
6C8
6C7
6D7
6C7
6C8
14C6
6D7
5A4
14C6
22A7
14C6
6C8
6D8
29C3
28C3
22C4
6D2 6D1
6D2
6D2
6D2
6D2
6D3 6D1
5C1
5C1
5C1 5C1
5B2
6D1
6D1
6D1
6D1
5C1
5C1
5B2
6C3 6C1
5B2
5C1
5C1
5C1 5C1
5A7
5A7
5B2
5C1
5A7
5B1
78A3 82C8
82C8
6B2 6B1
6B2 6B1
6B2 6B1
6B2 6B1
78A3 82C8
78A3 82C8
78B3
78B3
6B2
6B2 6B1
78B3 82B8
78B3
6A2
6A2 6A1
5C1 5C1
5C1 5C1
6B2
5C1
6B2
6D5
6C5
6C3
6D8
6D8
5B2
6D8
5B4
14C6
5B4
14C6
5C4 5C4
6C8
6D8
6D7
6B3
6B3
5B2
5B2
5B2
6D8
5B2
6A6
6A6
6A6
6A6
6A6
6A6
6A6
6A6
6A6
6A6
6A6
6A6
6A6
6B6
6B6
6B6
6A6
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IN
IN
IN
IN
IN
IN
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
OUT
OUT
OUT
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
IN
IN
IN
IN
IN
IN
IN
IN
OUT
A7*
RSVD14
RSVD15
BCLK1
BCLK0
RSVD20
RSVD17
RSVD18
RSVD19
RSVD16
RSVD13
RSVD12
THERMTRIP*
THERMDC
THERMDA
PROCHOT*
DBR*
TRST*
TMS
TDO
TDI
TCK
PREQ*
PRDY*
BPM3*
BPM1*
BPM2*
BPM0*
HITM*
HIT*
TRDY*
RS2*
RS1*
RS0*
RESET*
LOCK*
INIT*
IERR*
BR0*
DBSY*
DRDY*
DEFER*
BPRI*
BNR*
ADS*
RSVD11
RSVD6
RSVD7
RSVD8
RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
RSVD9
RSVD10
SMI*
LINT0
LINT1
STPCLK*
IGNNE*
FERR*
A20M*
ADSTB1*
A30*
A31*
A27*
A28*
A29*
A26*
A25*
A24*
A22*
A23*
A21*
A20*
A19*
A18*
A17*
REQ4*
REQ3*
REQ1*
REQ0*
REQ2*
ADSTB0*
A14*
A15*
A16*
A13*
A12*
A11*
A10*
A9*
A8*
A6*
A5*
A4*
A3*
(1 OF 4)
THERM
HCLK
RESERVED
ADDR GROUP1 ADDR GROUP0
CONTROL
XDP/ITP SIGNALS
PSI*
SLP*
PWRGOOD
DPRSTP*
DPSLP*
DPWR*
COMP2
COMP3
COMP1
COMP0
DSTBP3*
DSTBN3*
DINV3*
D63*
D62*
D61*
D60*
D59*
D58*
D57*
D56*
D55*
D54*
D52*
D53*
D51*
D50*
D49*
D48*
DINV2*
DSTBN2*
D47*
DSTBP2*
D45*
D46*
D44*
D43*
D42*
D41*
D40*
D39*
D38*
D37*
D36*
D35*
D34*
D33*
D32*
BSEL2
DSTBN1*
BSEL0
BSEL1
TEST2
TEST1
DINV1*
DSTBP1*
D31*
D30*
D29*
D26*
D27*
D28*
D24*
D25*
D23*
D21*
D22*
D20*
D19*
D18*
D16*
D17*
DINV0*
DSTBP0*
DSTBN0*
D15*
D14*
D13*
D12*
D11*
D10*
D9*
D8*
D7*
D6*
D5*
D4*
D3*
D2*
D1*
D0*
GTLREF
NC
(2 OF 4)
MISC
DATA GRP0
DATA GRP2
DATA GRP1
DATA GRP3
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
0.1" AWAY
ROUTE TO TP VIA AND
SPARE[7-0],HFPLL:
STUB)
PM_THRMTRIP#
SHOULD CONNECT TO
CPU_PROCHOT_L TO SMC
COMP1,3 CONNECT WITH ZO=55OHM, MAKE
LAYOUT NOTE:
COMP0,2 CONNECT WITH ZO=27.4OHM, MAKE
TRACE LENGTH SHORTER THAN 0.5".
TRACE LENGTH SHORTER THAN 0.5".
ICH7-M AND GMCH
LAYOUT NOTE: 0.5" MAX LENGTH
PLACE TESTPOINT ON
FSB_IERR_L WITH A GND
PLACE GND VIA W/IN 1000 MILS
TCK PULL DOWN THROUGH 54.9 OHM(FOLLOW UP XDP DESIGN REFERENCE)
SO THE TDI PULL UP THROUGH 54.9 OHM,TMS PULL UP THROUGH 54.9 OHM
WE THROUGH THE ITP700FLEX CONNECTOR CONNECT TO PDB XDP BUFFER BOARD--ECM*50
CHANGE THE PULLS RESISTOR VALUE PER NAPA PLATFORM DG REV 0.9
WITHOUT T-ING (NO
AND CPU VR TO INFORM
CPU IS HOT
1/16W
402
MF-LF
54.9
1%
R0702
1
2
MF-LF
402
5%
1/16W
68
R0704
1
2
1/16W
1%
402
MF-LF
1K
R0705
1
2
1/16W
1%
402
MF-LF
2.0K
R0706
1
2
54.9
402
1%
R0719
1 2
27.4
R0718
1 2
54.9
4021%
R0717
1 2
402
27.4
R0716
1 2
0
402
NOSTUFF
R0730
1 2
NOSTUFF
1K
MF-LF
402
5%
1/16W
R0707
1
2
MF-LF
402
5%
1/16W
51
R0712
1
2
54.9
1%
1/16W
MF-LF
402
R0703
1
2
54.9
402
1%
R0720
1 2
1%
402
54.9
R0721
1 2
54.9
402
1%
R0722
1 2
BGA
YONAH
CPU
OMIT
U0700
N3
P5
P2
L1
P4
P1
R1
Y2
U5
R3
W6
A6
U4
Y5
U2
R4
T5
T3
W3
W5
Y4
J4
W2
Y1
L4
M3
K5
M1
N2
J1
H1
L2
V4
A22
A21
E2
AD4
AD3
AD1
AC4
G5
F1
C20
E1
H5
F21
A5
G6
E4
D20
C4
B3
C6
B4
H4
AC2
AC1
D21
K3
H2
K2
J3
L5
B1
F3
F4
G3
AA1
C3
B25
T22
D2
F6
D3
C1
AF1
D22
C23
AA4
C24
AB2
AA3
M4
N5
T2
V3
B2
A3
D5
AC5
AA6
AB3
A24
A25
C7
AB5
G2
AB6
CPU
YONAH
BGA
OMIT
U0700
B22
B23
C21
R26
U26
U1
V1
E22
F24
J24
J23
H26
F26
K22
H25
N22
K25
P26
R23
E26
L25
L22
L23
M23
P25
P22
P23
T24
R24
L26
H22
T25
N24
AA23
AB24
V24
V26
W25
U23
U25
U22
F23
AB25
W22
Y23
AA26
Y26
Y22
AC26
AA24
AC22
AC23
G25
AB22
AA21
AB21
AC25
AD20
AE22
AF23
AD24
AE21
AD21
E25
AE25
AF25
AF22
AF26
E23
K24
G24
J26
M26
V23
AC20
E5
B5
D24
H23
M24
W24
AD23
G22
N25
Y25
AE24
AD26
A2
AE6
D6
D7
C26
D25
SYNC_DATE=09/15/2006
SYNC_MASTER=M59_MLB
87
051-7164 06004
7
CPU 1 OF 2-FSB
FSB_RS_L<0>
FSB_RS_L<1>
XDP_BPM_L<5>
FSB_HITM_L
FSB_HIT_L
FSB_RS_L<2>
FSB_TRDY_L
PP1V05_S0
XDP_BPM_L<1>
FSB_DBSY_L
PP1V05_S0
PP1V05_S0
PP1V05_S0
XDP_TMS
XDP_TDI
XDP_TCK
FSB_A_L<3>
FSB_A_L<4>
FSB_A_L<5>
FSB_A_L<6>
FSB_A_L<8>
FSB_A_L<9>
FSB_A_L<10>
FSB_A_L<11>
FSB_A_L<12>
FSB_A_L<13>
FSB_A_L<16>
FSB_A_L<15>
FSB_A_L<14>
FSB_ADSTB_L<0>
FSB_REQ_L<2>
FSB_REQ_L<0>
FSB_REQ_L<1>
FSB_REQ_L<3>
FSB_REQ_L<4>
FSB_A_L<17>
FSB_A_L<18>
FSB_A_L<19>
FSB_A_L<20>
FSB_A_L<21>
FSB_A_L<23>
FSB_A_L<22>
FSB_A_L<24>
FSB_A_L<25>
FSB_A_L<26>
FSB_A_L<29>
FSB_A_L<28>
FSB_A_L<27>
FSB_A_L<31>
FSB_A_L<30>
FSB_ADSTB_L<1>
CPU_A20M_L
CPU_FERR_L
CPU_IGNNE_L
CPU_STPCLK_L
CPU_NMI
CPU_INTR
CPU_SMI_L
NC_CPU_APM1_L
NC_CPU_APM0_L
NC_CPU_A36_L
NC_CPU_A35_L
NC_CPU_A34_L
NC_CPU_A33_L
NC_CPU_A32_L
NC_CPU_A39_L
NC_CPU_A38_L
NC_CPU_A37_L
NC_CPU_HFPLL
FSB_DEFER_L
FSB_DRDY_L
FSB_BREQ0_L
FSB_IERR_L
CPU_INIT_L
FSB_LOCK_L
FSB_CPURST_L
XDP_BPM_L<0>
XDP_BPM_L<2>
XDP_BPM_L<3>
XDP_BPM_L<4>
XDP_TCK
XDP_TDI
XDP_TDO
XDP_TMS
XDP_TRST_L
XDP_DBRESET_L
CPU_PROCHOT_L
CPU_THERMD_P
CPU_THERMD_N
PM_THRMTRIP_L
NC_CPU_EXTBREF
NC_CPU_SPARE0
TP_CPU_SPARE3
TP_CPU_SPARE6
TP_CPU_SPARE5
NC_CPU_SPARE4
TP_CPU_SPARE7
FSB_CLK_CPU_P
FSB_CLK_CPU_N
NC_CPU_SPARE2
NC_CPU_SPARE1
FSB_A_L<7>
CPU_GTLREF
FSB_D_L<0>
FSB_D_L<1>
FSB_D_L<2>
FSB_D_L<3>
FSB_D_L<4>
FSB_D_L<5>
FSB_D_L<6>
FSB_D_L<7>
FSB_D_L<8>
FSB_D_L<9>
FSB_D_L<10>
FSB_D_L<11>
FSB_D_L<12>
FSB_D_L<13>
FSB_D_L<14>
FSB_D_L<15>
FSB_DSTBN_L<0>
FSB_DSTBP_L<0>
FSB_DINV_L<0>
FSB_D_L<17>
FSB_D_L<16>
FSB_D_L<18>
FSB_D_L<19>
FSB_D_L<20>
FSB_D_L<22>
FSB_D_L<21>
FSB_D_L<23>
FSB_D_L<25>
FSB_D_L<24>
FSB_D_L<28>
FSB_D_L<27>
FSB_D_L<26>
FSB_D_L<29>
FSB_D_L<30>
FSB_D_L<31>
FSB_DSTBP_L<1>
FSB_DINV_L<1>
CPU_TEST1
CPU_TEST2
CPU_BSEL<1>
CPU_BSEL<0>
FSB_DSTBN_L<1>
CPU_BSEL<2>
FSB_D_L<32>
FSB_D_L<33>
FSB_D_L<34>
FSB_D_L<35>
FSB_D_L<36>
FSB_D_L<37>
FSB_D_L<38>
FSB_D_L<39>
FSB_D_L<40>
FSB_D_L<41>
FSB_D_L<42>
FSB_D_L<43>
FSB_D_L<44>
FSB_D_L<46>
FSB_D_L<45>
FSB_DSTBP_L<2>
FSB_D_L<47>
FSB_DSTBN_L<2>
FSB_DINV_L<2>
FSB_D_L<48>
FSB_D_L<49>
FSB_D_L<50>
FSB_D_L<51>
FSB_D_L<53>
FSB_D_L<52>
FSB_D_L<54>
FSB_D_L<55>
FSB_D_L<56>
FSB_D_L<57>
FSB_D_L<58>
FSB_D_L<59>
FSB_D_L<60>
FSB_D_L<61>
FSB_D_L<62>
FSB_D_L<63>
FSB_DINV_L<3>
FSB_DSTBN_L<3>
FSB_DSTBP_L<3>
CPU_COMP<0>
CPU_COMP<1>
CPU_COMP<3>
CPU_COMP<2>
FSB_DPWR_L
CPU_DPSLP_L
CPU_DPRSTP_L
CPU_PWRGD
FSB_SLPCPU_L
CPU_PSI_L
FSB_ADS_L
FSB_BNR_L
FSB_BPRI_L
67D8
67D8
67D6
67D8
67D8
67D6
65A2
67D6
67D6
65A2
55A4
65A2
65A2
55A4
34C8
55A4
55A4
34C8
34C6
34C8
34C8
34C6
34B8
34C6
34C6
34B8
25D3
34B8
34B8
25D3
25C4
25D3
25D3
25C4
24D3
25C4
25C4
24D3
24C3
24D3
24D3
24C3
21C1
24C3
24C3
21C1
19D7
21C1
21C1
19D7
19D6
19D7
19D7
19D6
19D5
19D6
19D6
19D5
19D2
19D5
19D5
19D2
19D1
19D2
19D2
19D1
19C8
19D1
19D1
19C8
17D6
19C8
19C8
17D6
17D3
17D6
17D6
17D3
16D3
17D3
17D3
16D3
16C8
16D3
16D3
16C8
13B5
16C8
16C8
13B5
12C2
13B5
13B5
12C2
12B7
12C2
12C2
12B7
12A7
12B7
12B7
12A7
11C5
12A7
12A7
11C5
11B3
11C5
11C5
11B3
9B7
11B3
11B3
9B7
8C7
9B7
9B7
8C7
7D5
8C7
8C7
7D5
7B6
7D5
7D5
7B6
87D6
34D5
34D5
87D6
87D6
7B5
87D6
7B5
7B6
7B5
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87C6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87C6
87C6
87D6
87D6
87D6
12C4
52C1
34D3
34D3
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87C6
61C7
87C6
87D6
87D6
87D6
87D6
87C6
12B4
12B4
87D6
87D6
5D4
87C6
12B4
5D4
5D4
5D4
11B3
11B3
11B3
12D4
12D4
12D4
12D4
12D4
12D4
12D4
12D4
12D4
12D4
12C4
12D4
12D4
12C4
12A4
12B4
12B4
12A4
12A4
12C4
12C4
12C4
12C4
12C4
12C4
12C4
12C4
12C4
12C4
12C4
12C4
12C4
12C4
12C4
12C4
87C6
87C6
21C4
87C6
87C6
87C6
6C8
6D8
6D8
6D8
6D8
6D8
6D8
6D8
6D8
6D8
6C8
87D6
12B4
12C4
87C6
12B4
11B5
87C6
87C6
87C6
87C6
11B3
11B3
11B3
26C6
52D3
21C2
6C8
6C8
6C8
33C4
33C4
6C8
6C8
12D4
12D6
12D6
12D6
12D6
12D6
12D6
12D6
12D6
12D6
12D6
12D6
12D6
12D6
12C6
12C6
12C6
12B4
12B4
12B4
12C6
12C6
12C6
12C6
12C6
12C6
12C6
12C6
12C6
12C6
12C6
12C6
12C6
12C6
12C6
12C6
12B4
12B4
12B4
12C6
12C6
12C6
12C6
12C6
12C6
12C6
12B6
12B6
12B6
12B6
12B6
12B6
12B6
12B6
12B4
12B6
12B4
12B4
12B6
12B6
12B6
12B6
12B6
12B6
12B6
12B6
12B6
12B6
12B6
12B6
12B6
12B6
12B6
12B6
12B4
12B4
12B4
12B4
21C4
21C4
21C4
12A4
12C4
12C4
87D6
12A4
12A4
11B3
5B7
5B7
12A4
12A4
5B2
11B3
5B7
5B2
5B2
5B2
7C6
7C6
7C6
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5A7
5A7
5A7
5A7
5A7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
21C4
21C2
21C4
5C4
21C4
21C4
21C4
6C7
6D7
6D7
6D7
6D7
6D7
6D7
6D7
6D7
6D7
6C7
12B4
5B7
5B7
87C6
21C4
5A7
5A4
11B3
11B3
11B3
11B3
7A8
7B8
11B5
7B8
11B3
11B4
52C1
10B6
10B6
14B6
6C7
6C7
6C7
5C4
5C4
6C7
6C7
5B7
87C6
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
34B6
34C6
5B7
34B6
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
87C6
87C6
87C6
87C6
5A4
5B4
5C4
5B4
5A4
61C7
5B7
5B7
12C4
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
VSS_82
VSS_83
VSS_84
VSS_85
VSS_87
VSS_86
VSS_88
VSS_89
VSS_90
VSS_92
VSS_91
VSS_93
VSS_94
VSS_95
VSS_97
VSS_96
VSS_100
VSS_98
VSS_99
VSS_102
VSS_101
VSS_105
VSS_103
VSS_104
VSS_106
VSS_107
VSS_110
VSS_109
VSS_108
VSS_111
VSS_112
VSS_115
VSS_114
VSS_113
VSS_116
VSS_117
VSS_118
VSS_120
VSS_119
VSS_123
VSS_121
VSS_122
VSS_124
VSS_125
VSS_128
VSS_126
VSS_127
VSS_129
VSS_130
VSS_133
VSS_131
VSS_132
VSS_134
VSS_135
VSS_138
VSS_136
VSS_137
VSS_139
VSS_140
VSS_141
VSS_143
VSS_142
VSS_146
VSS_144
VSS_145
VSS_147
VSS_148
VSS_151
VSS_150
VSS_149
VSS_152
VSS_153
VSS_156
VSS_155
VSS_154
VSS_157
VSS_158
VSS_159
VSS_161
VSS_160
VSS_162
VSS_1
VSS_2
VSS_3
VSS_5
VSS_4
VSS_6
VSS_7
VSS_8
VSS_10
VSS_9
VSS_11
VSS_12
VSS_15
VSS_13
VSS_14
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_23
VSS_22
VSS_21
VSS_24
VSS_25
VSS_28
VSS_27
VSS_26
VSS_29
VSS_30
VSS_33
VSS_32
VSS_31
VSS_34
VSS_35
VSS_38
VSS_37
VSS_36
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_46
VSS_44
VSS_45
VSS_47
VSS_48
VSS_51
VSS_49
VSS_50
VSS_52
VSS_53
VSS_56
VSS_54
VSS_55
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_63
VSS_62
VSS_64
VSS_65
VSS_66
VSS_69
VSS_68
VSS_67
VSS_70
VSS_71
VSS_74
VSS_73
VSS_72
VSS_75
VSS_76
VSS_79
VSS_78
VSS_77
VSS_80
VSS_81
(4 OF 4)
VCC_67
VCC_64
VCC_66
VCC_65
VCC_63
VCC_62
VCC_61
VCC_59
VCC_60
VCC_58
VCC_57
VCC_56
VCC_54
VCC_55
VCC_53
VCC_51
VCC_52
VCC_49
VCC_50
VCC_48
VCC_47
VCC_46
VCC_44
VCC_45
VCC_43
VCC_41
VCC_42
VCC_40
VCC_39
VCC_38
VCC_36
VCC_37
VCC_33
VCC_35
VCC_34
VCC_31
VCC_32
VCC_29
VCC_30
VCC_28
VCC_26
VCC_27
VCC_23
VCC_25
VCC_24
VCC_22
VCC_21
VCC_20
VCC_18
VCC_19
VCC_17
VCC_16
VCC_15
VCC_13
VCC_14
VCC_12
VCC_10
VCC_11
VCC_8
VCC_9
VCC_7
VCC_6
VCC_5
VCC_3
VCC_4
VCC_2
VCC_1 VCC_68
VCC_69
VCC_71
VCC_70
VCC_72
VCC_74
VCC_76
VCC_75
VCC_78
VCC_77
VCC_79
VCC_81
VCC_80
VCC_84
VCC_82
VCC_83
VCC_86
VCC_85
VCC_87
VCC_89
VCC_88
VCC_90
VCC_91
VCC_92
VCC_94
VCC_93
VCC_95
VCC_96
VCC_97
VCC_99
VCC_98
VCC_100
VCCP_1
VCCP_2
VCCP_3
VCCP_4
VCCP_5
VCCP_6
VCCP_7
VCCP_9
VCCP_8
VCCP_11
VCCP_10
VCCP_12
VCCP_13
VCCP_14
VCCP_16
VCCP_15
VCCA
VID0
VID1
VID2
VID3
VID4
VID5
VID6
VSSSENSE
VCCSENSE
VCC_73
(3 OF 4)
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
VCCA=1.5 ONLY
LAYOUT NOTE: CONNECT R0803
PULL-DOWN
IF NO USE, NEED PULL-UP OR
VID FOR CPU POWER SUPPLY
TRANSMISSION LINE
RESISTORS TERMINATE THE 55 OHM
LAYOUT NOTE:
(CPU CORE POWER)
(CPU IO POWER 1.05V)
STUB.
LAYOUT NOTE:
VCCSENSE AND VSSSENSE LINES
SHOULD BE OF EQUAL LENGTH
LOCATION WHERE THE TWO 54.9 OHM
BETWEEN VCCSENSE AND VSSSENSE AT THE
TO CONNECT A DIFFERENCTIAL PROBE
PROVIDE A TEST POINT (WITH NO STUB)
LAYOUT NOTE:
TO TP_VSSSENSE WITH NO
(CPU INTERNAL PLL POWER 1.5V)
ZO=27.4 OHM DIFFERNTIAL TRACE ROUTING.
CPU_VCCSENSE_P/CPU_VCCSENSE_N USE
9C2
87B6
9C2
87B6
9C2
87B6
9C2
87B6
9C2
87B6
9C2
87B6
1/16W
1%
402
MF-LF
100
R0803
1
2
9C2
87B6
61A1 87B6
61B1 87B6
100
MF-LF
402
1%
1/16W
R0802
1
2
OMIT
BGA
YONAH
CPU
U0700
A4
B8
V25
W1
W4
W23
W26
Y3
Y6
Y21
Y24
AA2
B11
AA5
AA8
AA11
AA14
AA16
AA19
AA22
AA25
AB1
AB4
B13
AB8
AB11
AB13
AB16
AB19
AB23
AB26
AC3
AC6
AC8
B16
AC11
AC14
AC16
AC19
AC21
AC24
AD2
AD5
AD8
AD11
B19
AD13
AD16
AD19
AD22
AD25
AE1
AE4
AE8
AE11
AE14
B21
AE16
AE19
AE23
AE26
AF3
AF6
AF8
AF11
AF13
AF16
B24
AF19
AF21
AF24
C5
C8
C11
A8
C14
C16
C19
C2
C22
C25
D1
D4
D8
D11
A11
D13
D16
D19
D23
D26
E3
E6
E8
E11
E14
A14
E16
E19
E21
E24
F5
F8
F11
F13
F16
F19
A16
F2
F22
F25
G4
G1
G23
G26
H3
H6
H21
A19
H24
J2
J5
J22
J25
K1
K4
K23
K26
L3
A23
L6
L21
L24
M2
M5
M22
M25
N1
N4
N23
A26
N26
P3
P6
P21
P24
R2
R5
R22
R25
T1
B6 T4
T23
T26
U3
U6
U21
U24
V2
V5
V22
OMIT
BGA
YONAH
CPU
U0700
A7
B7
AF20
B9
B10
B12
B14
B15
B17
B18
B20
C9
A9
C10
C12
C13
C15
C17
C18
D9
D10
D12
D14
A10
D15
D17
D18
E7
E9
E10
E12
E13
E15
E17
A12
E18
E20
F7
F9
F10
F12
F14
F15
F17
F18
A13
F20
AA7
AA9
AA10
AA12
AA13
AA15
AA17
AA18
AA20
A15
AB9
AC10
AB10
AB12
AB14
AB15
AB17
AB18
AB20
AB7
A17
AC7
AC9
AC12
AC13
AC15
AC17
AC18
AD7
AD9
AD10
A18
AD12
AD14
AD15
AD17
AD18
AE9
AE10
AE12
AE13
AE15
A20
AE17
AE18
AE20
AF9
AF10
AF12
AF14
AF15
AF17
AF18
B26
V6
N6
R21
R6
T21
T6
V21
W21
G21
J6
K6
M6
J21
K21
M21
N21
AF7
AD6
AF5
AE5
AF4
AE3
AF2
AE2
AE7
CPU 2 OF 2-PWR/GND
051-7164 06004
8 87
SYNC_MASTER=M59_MLB
SYNC_DATE=09/15/2006
PPVCORE_S0_CPU
CPU_VCCSENSE_P
CPU_VCCSENSE_N
CPU_VID<6>
CPU_VID<5>
CPU_VID<4>
CPU_VID<3>
CPU_VID<2>
CPU_VID<1>
CPU_VID<0>
PP1V5_S0
PP1V05_S0
PPVCORE_S0_CPU
67D8 67D6
65A2 55A4 34C8 34C6 34B8 25D3 25C4 24D3 24C3 21C1
19D7 19D6 19D5
67C8
19D2
67C6
19D1
66C5
19C8
62C1
17D6
62A8
17D3
48B6
16D3
25D6
16C8
25C8
13B5
25C6
12C2
25C2
12B7
25B6
12A7
67D3
25B2
11C5
67D3
67D1
25A8
11B3
67D1
61D1
24B5
9B7
61D1
55D7
24A5
7D5
55D7
55A6
24A3
7B6
55A6
9D7
9B7
7B5
9D7
8D7
5D4
5D4
8B5
5B2
5D1
5B2
5B2
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
CPU VCORE VID Connections
NC NC
NOTE: This cap is shared
CPU VCORE HF AND BULK DECOUPLING
VCCP (CPU I/O) Decoupling
Will probably be removed before production
Resistors to allow for override of CPU VID
1x 10uF, 1x 0.01uF
between CPU and NB
1x 470uF, 6x 0.1uF 0402
VCCA (CPU AVdd) Decoupling
4x 330uF. 20x 22uF 0805
6.3V
20%
CERM
805
22UF
C0906
1
2
6.3V
20%
CERM
22UF
805
C0904
1
2
6.3V
20%
CERM
22UF
805
C0916
1
2
6.3V
20%
CERM
22UF
805
C0914
1
2
6.3V
20%
CERM
22UF
805
C0908
1
2
6.3V
20%
CERM
22UF
805
C0903
1
2
6.3V
20%
CERM
22UF
805
C0907
1
2
6.3V
20%
CERM
22UF
805
C0902
1
2
6.3V
20%
CERM
805
22UF
C0901
1
2
6.3V
20%
CERM
805
22UF
C0913
1
2
6.3V
20%
CERM
22UF
805
C0912
1
2
6.3V
20%
CERM
22UF
805
C0911
1
2
6.3V
20%
CERM
22UF
805
C0919
1
2
6.3V
20%
CERM
22UF
805
C0900
1
2
6.3V
20%
CERM
22UF
805
C0910
1
2
0.1UF
CERM
402
20%
10V
C0936
1
2
470uF
CRITICAL
D2T
TANT
2.5V
20%
C0935
1
2 3
6.3V
20%
CERM
22UF
805
C0905
1
2
6.3V
20%
CERM
22UF
805
C0909
1
2
20%
CERM
22UF
6.3V
805
C0915
1
2
6.3V
20%
CERM
22UF
805
C0917
1
2
0.1UF
CERM
402
20%
10V
C0937
1
2
0.1UF
CERM
402
20%
10V
C0938
1
2
0.1UF
CERM
402
20%
10V
C0939
1
2
0.1UF
CERM
402
20%
10V
C0940
1
2
0.1UF
CERM
402
20%
10V
C0941
1
2
22UF
CERM
20%
6.3V
805
C0918
1
2
16V
0.01UF
CERM
402
20%
C0981
1
2
X5R
10uF
20%
6.3V
603
C0980
1
2
SM-LF
1/16W
5%
0
RP0990
1
2
3
4
8
7
6
5
SM-LF
1/16W
5%
0
RP0991
1
2
3
4
8
7
6
5
330UF
20%
2.5V
POLY
D2T
CRITICAL
C0950
1
23
CRITICAL
D2T
POLY
2.5V
20%
330UF
C0952
1
23
330UF
20%
2.5V
POLY
D2T
CRITICAL
C0953
1
23
CRITICAL
D2T
POLY
2.5V
20%
330UF
C0954
1
23
CPU Decoupling & VID
051-7164
SYNC_DATE=09/15/2006
SYNC_MASTER=M59_MLB
06004
9 87
PPVCORE_S0_CPU
PP1V5_S0
PP1V05_S0
CPU_VID<0>
CPU_VID<1>
CPU_VID<2>
CPU_VID<3>
IMVP6_VID<0>
IMVP6_VID<1>
IMVP6_VID<2>
IMVP6_VID<3>
CPU_VID<4>
CPU_VID<5>
CPU_VID<6>
IMVP6_VID<4>
IMVP6_VID<5>
IMVP6_VID<6>
67D8 67D6 65A2 55A4
34C8 34C6 34B8 25D3 25C4 24D3 24C3 21C1 19D7
19D6 19D5
67C8
19D2
67C6
19D1
66C5
19C8
62C1
17D6
62A8
17D3
48B6
16D3
25D6
16C8
25C8
13B5
25C6
12C2
25C2
12B7
25B6
12A7
67D3
25B2
11C5
67D1
25A8
11B3
61D1
24B5
8C7
55D7
24A5
7D5
55A6
24A3
7B6
8D7
8B7
7B5
8B5
5D4
5D4
87B6
87B6
87B6
87B6
61C7
61C7
61C7
61C7
87B6
87B6
87B6
61C7
61C7
61C7
5B2
5D1
5B2
8B7
8B7
8B7
8B7
5C4
5C4
5C4
5C4
8B7
8B7
8B7
5C4
5C4
5C4
IO
IO
IN
OUT
GND
VDD
SDATA
SCLK
THM*
ALERT*/
D+
D-
THM2*
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
(TC0D)
(TO CPU INTERNAL THERMAL DIODE)
ROUTE CPU_THERMD_P AND
CPU_THERMD_N ON SAME
LAYER.
10 MIL TRACE
LAYOUT NOTE:
10 MIL SPACING
LAYOUT NOTE:
CPU_THERMD_N
FOR CPU_THERMD_P AND
ADD GND GUARD TRACE
CPU ZONE THERMAL SENSOR
PLACE U1001 NEAR THE U1200
0.001UF
10%
402
CERM
50V
C1001
1
2
0.1UF
X5R
16V
10%
402
C1002
1
2
CRITICAL
TMP401
MSOP
U1001
6
3
2
5
8
7
4
1
MF-LF
402
1/16W
5%
10K
R1005
1
2
1/16W
5%
402
10K
MF-LF
R1006
1
2
499
1%
1/16W
MF-LF
402
R1001
1 2
499
402
MF-LF
1/16W
1%
R1002
1 2
SYNC_DATE=09/15/2006
SYNC_MASTER=M59_MLB
051-7164 06004
10 87
CPU MISC1-TEMP SENSOR
PP3V3_S0
CPU_THERMD_P
THRM_CPU_DX_P
CPU_THERMD_N
THRM_CPU_DX_N
SMBUS_SMC_B_S0_SDA
SMBUS_SMC_B_S0_SCL
THRM_ALERT
THRM_ALERT_L
82D5 82C6 82B3 82A4 79D3 79A8 71D2 67C5
67C3 67B3 67A3 66B6 66B5 66B1 65D6 65B3
62A6 61D8 61A5 60D4 60C7 58C7 58C4 57B6 54D4
54B5 52D3 49C7 49C4 49B5 40B6 36D6 34A8 33D8
33D3 33C7 29A6 29A3 28A6 27D8 27D5 27D3 27C3
26D1 26B8 26B6 26B4 25D8 25D3 25C6 25C4 25B8
25B4 25A4 24D3 24C3 24B5 24B3 23D5 23B3 22B5 21D3
21C3 20B4 20A4 19C7 19C6 17C6
51B5
51B5
14D6
49B5
49B5
14C7
27D3
27D3
5D4
27D2
27D2
5A4
7C6
7C6
27D1
27D1
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IO
IO
IO
IO
IO
IO
OUT
IN
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
ROUTE THE TCK SIGNAL FROM ITP700FLEX CONNECTOR’S TCK PIN TO CPU’S
TCK PIN AND THEN FORK BACK FROM CPU TCK PIN AND ROUTE BACK TO ITP700FLEX
INDICATE THAT ITP IS USING TAP I/F, NC IN 945GM CHIPSET SYSTEM.
(FROM CK410M HOST 133/167MHZ)
(DEBUG PORT RESET)
(AND WITH RESET BUTTON)
TO ICH7M SYS_RST*, AND WITH SYSTEM RESET LOGIC
NC
NC
NC
(DBA#)
(DBR#)
(DEBUG PORT ACTIVE)
CPU ITP700FLEX DEBUG SUPPORT
(FBO)
(TCK)
518S0320
CONNECTOR’S FBO PIN.
ITP TCK SIGNAL LAYOUT NOTE:
MF-LF
22.6
1%
1/16W
402
ITP
R1100
1 2
ITP
402
1%
22.6
1/16W
MF-LF
R1102
1 2
54.9
1/16W
1%
402
MF-LF
ITP
R1103
1
2
402
X5R
16V
10%
0.1UF
C1100
1
2
1/16W
240
402
MF-LF
5%
R1104
1
2
F-RT-SM
52435-2872
CRITICAL
ITPCONN
J1101
1
10
11
12
13
14
15
16
17
18
19
2
20
21
22
23
24
25
26
27
28
29
3
30
4
5
6
7
8
9
1/16W
402
54.9
1%
MF-LF
R1101
1
2
680
402
5%
1/16W
MF-LF
R1106
1
2
CPU ITP700FLEX DEBUG
051-7164 06004
11 87
SYNC_MASTER=(MASTER)
SYNC_DATE=(MASTER)
PP1V05_S0
FSB_CPURST_L
XDP_BPM_L<0>
XDP_TCK
XDP_TDI
XDP_TDO
PP3V3_S5
PP1V05_S0
XDP_TMS
CPU_XDP_CLK_N
XDP_TRST_L
XDP_BPM_L<1>
XDP_BPM_L<2>
XDP_BPM_L<3>
XDP_BPM_L<4>
XDP_BPM_L<5>
XDP_TCK
CPU_XDP_CLK_P
ITP_TDO
XDP_DBRESET_L
ITPRESET_L
67D8
67D8
67D6
67D6
65A2
65A2
55A4
55A4
34C8
34C8
34C6
34C6
34B8
34B8
25D3
25D3
25C4
79D5
25C4
24D3
67D5
24D3
24C3
67D3
24C3
21C1
67C3
21C1
19D7
66C5
19D7
19D6
65D8
19D6
19D5
65D2
19D5
19D2
65D1
19D2
19D1
65C8
19D1
19C8
63D8
19C8
17D6
56D4
17D6
17D3
26C5
17D3
16D3
25D2
16D3
16C8
25C8
16C8
13B5
25B6
13B5
12C2
24C3
12C2
12B7
24B3
12B7
12A7
24A5
12A7
11C5
23D8
11B3
9B7
23D4
9B7
8C7
23D1
8C7
7D5
23B7
7D5
7B6
87D6
23A7
7B6
87C6
87C6
7B5
12C4
11B3
22D8
7B5
34D5
11B3
34D5
5D4
7D6
87C6
7C6
7C6
22C6
5D4
7C6
34D3
87C6
87C6
87C6
87C6
87C6
7C6
34D3
26C6
5B2
5A4
7C6
7A8
7B8
7C6
5D4
5B2
7B8
33C4
7C6
7C6
7C6
7C6
7C6
7C6
7A8
33C4
7C6
87C6
IO
IO
IO
OUT
OUT
OUT
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
OUT
IO
OUT
OUT
OUT
OUT
IO
IO
IO
IO
IO
IN
IO
IN
IO
IO
HD4*
HD6*
HD16*
HTRDY*
HSLPCPU*
HRS1*
HRS0*
HHITM*
HLOCK*
HHIT*
HDSTBP2*
HDTSBP3*
HDSTBP1*
HDSTBP0*
HDSTBN3*
HDSTBN1*
HDSTBN2*
HDSTBN0*
HDINV2*
HDINV3*
HDINV1*
HDINV0*
HDVREF
HDRDY*
HDPWR*
HDEFER*
HDBSY*
HCPURST*
HBREQ0*
HBPRI*
HBNR*
HAVREF
HCLKIN*
HCLKIN
HYSWING
HYRCOMP
HYSCOMP
HXSWING
HXSCOMP
HXRCOMP
HA13*
HADS*
HADSTB0*
HD3*
HD2*
HD1*
HD0*
HD63*
HD62*
HD61*
HD60*
HD59*
HD58*
HD57*
HD56*
HD55*
HD54*
HD53*
HD52*
HD51*
HD50*
HD49*
HD48*
HD47*
HD46*
HD45*
HD44*
HD43*
HD42*
HD41*
HD40*
HD39*
HD38*
HD37*
HD36*
HD35*
HD34*
HD33*
HD32*
HD31*
HD29*
HD28*
HD27*
HD26*
HD25*
HD24*
HD23*
HD22*
HD21*
HD20*
HD19*
HD18*
HD17*
HD15*
HD10*
HD11*
HD12*
HD13*
HD14*
HD5*
HD7*
HD8*
HD9*
HA30*
HA29*
HA28*
HA27*
HA26*
HA25*
HA24*
HA23*
HA31*
HA20*
HA19*
HA18*
HA16*
HA15*
HA14*
HA21*
HA22*
HA17*
HA9*
HA8*
HA7*
HA6*
HA5*
HA4*
HA3*
HA10*
HA11*
HA12*
HADSTB1*
HREQ0*
HREQ1*
HREQ2*
HREQ3*
HD30*
HREQ4*
HRS2*
(1 OF 10)
HOST
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
402
X5R
16V
10%
0.1uF
C1211
1
2
200
1%
1/16W
MF-LF
402
R1211
1
2
100
1%
1/16W
MF-LF
402
R1210
1
2
54.9
1%
1/16W
MF-LF
402
R1220
1
2
402
MF-LF
1/16W
1%
24.9
R1221
1
2
221
1%
1/16W
MF-LF
402
R1225
1
2
1%
1/16W
MF-LF
402
100
R1226
1
2
0.1uF
402
X5R
16V
10%
C1226
1
2
402
X5R
16V
10%
0.1uF
C1236
1
2
221
1%
1/16W
MF-LF
402
R1235
1
2
54.9
1%
1/16W
MF-LF
402
R1230
1
2
1%
1/16W
MF-LF
402
100
R1236
1
2
402
MF-LF
1/16W
1%
24.9
R1231
1
2
BGA
NB
945GM
OMIT
U1200
H11
J12
G14
D9
J14
H13
J15
F14
D12
A11
C11
A12
A13
E13
G13
F12
B12
B14
C12
A14
H9
C14
D14
C9
E11
G11
F11
G12
F9
E8
B9
C13
J13
C6
F6
C7
AG2
AG1
B7
F1
J1
K7
J8
H4
J3
K11
G4
T10
W11
T3
U7
H1
U9
U11
T11
W9
T1
T8
T4
W7
U5
T9
J6
W6
T5
AB7
AA9
W4
W3
Y3
Y7
W5
Y10
H3
AB8
W2
AA4
AA7
AA2
AA6
AA10
Y8
AA1
AB4
K2
AC9
AB11
AC11
AB3
AC2
AD1
AD9
AC1
AD7
AC6
G1
AB5
AD10
AD4
AC8
G2
K9
K1
A7
C3
J7
W8
U3
AB10
J9
H8
K4
T7
Y5
AC4
K3
T6
AA5
AC5
K13
D3
D4
B3
D8
G8
B8
F8
A8
B4
E6
D6
E3
E7
E1
E2
E4
Y1
U1
W1
SYNC_MASTER=M59_MLB
SYNC_DATE=09/15/2006
NB CPU Interface
06004
12 87
051-7164
NB_FSB_XRCOMP
PP1V05_S0
PP1V05_S0
PP1V05_S0
FSB_RS_L<2>
FSB_REQ_L<4>
FSB_D_L<30>
FSB_REQ_L<3>
FSB_REQ_L<2>
FSB_REQ_L<1>
FSB_REQ_L<0>
FSB_ADSTB_L<1>
FSB_A_L<12>
FSB_A_L<11>
FSB_A_L<10>
FSB_A_L<3>
FSB_A_L<4>
FSB_A_L<5>
FSB_A_L<6>
FSB_A_L<7>
FSB_A_L<8>
FSB_A_L<9>
FSB_A_L<17>
FSB_A_L<22>
FSB_A_L<21>
FSB_A_L<14>
FSB_A_L<15>
FSB_A_L<16>
FSB_A_L<18>
FSB_A_L<19>
FSB_A_L<20>
FSB_A_L<31>
FSB_A_L<23>
FSB_A_L<24>
FSB_A_L<25>
FSB_A_L<26>
FSB_A_L<27>
FSB_A_L<28>
FSB_A_L<29>
FSB_A_L<30>
FSB_D_L<14>
FSB_D_L<13>
FSB_D_L<12>
FSB_D_L<11>
FSB_D_L<15>
FSB_D_L<18>
FSB_D_L<19>
FSB_D_L<20>
FSB_D_L<21>
FSB_D_L<22>
FSB_D_L<23>
FSB_D_L<24>
FSB_D_L<25>
FSB_D_L<26>
FSB_D_L<27>
FSB_D_L<28>
FSB_D_L<29>
FSB_D_L<31>
FSB_D_L<32>
FSB_D_L<33>
FSB_D_L<34>
FSB_D_L<35>
FSB_D_L<36>
FSB_D_L<37>
FSB_D_L<38>
FSB_D_L<39>
FSB_D_L<40>
FSB_D_L<41>
FSB_D_L<42>
FSB_D_L<43>
FSB_D_L<44>
FSB_D_L<45>
FSB_D_L<46>
FSB_D_L<47>
FSB_D_L<48>
FSB_D_L<49>
FSB_D_L<50>
FSB_D_L<51>
FSB_D_L<52>
FSB_D_L<53>
FSB_D_L<54>
FSB_D_L<55>
FSB_D_L<56>
FSB_D_L<57>
FSB_D_L<58>
FSB_D_L<59>
FSB_D_L<60>
FSB_D_L<61>
FSB_D_L<62>
FSB_D_L<63>
FSB_ADSTB_L<0>
FSB_ADS_L
FSB_A_L<13>
NB_FSB_XSCOMP
NB_FSB_XSWING
NB_FSB_YSCOMP
NB_FSB_YRCOMP
NB_FSB_YSWING
FSB_CLK_NB_P
FSB_CLK_NB_N
FSB_BNR_L
FSB_BPRI_L
FSB_BREQ0_L
FSB_CPURST_L
FSB_DBSY_L
FSB_DEFER_L
FSB_DPWR_L
FSB_DRDY_L
FSB_DINV_L<3>
FSB_DSTBN_L<1>
FSB_DSTBP_L<0>
FSB_HIT_L
FSB_LOCK_L
FSB_HITM_L
FSB_RS_L<0>
FSB_RS_L<1>
FSB_SLPCPU_L
FSB_TRDY_L
FSB_D_L<16>
FSB_D_L<0>
FSB_D_L<3>
FSB_D_L<7>
FSB_D_L<8>
FSB_D_L<9>
FSB_D_L<10>
FSB_D_L<6>
FSB_D_L<5>
FSB_D_L<4>
FSB_D_L<2>
FSB_D_L<1>
NB_FSB_VREF
FSB_DINV_L<2>
FSB_DINV_L<1>
FSB_DSTBN_L<0>
FSB_DINV_L<0>
FSB_DSTBP_L<3>
FSB_DSTBP_L<2>
FSB_DSTBP_L<1>
FSB_DSTBN_L<3>
FSB_DSTBN_L<2>
FSB_D_L<17>
67D8
67D8
67D8
67D6
67D6
67D6
65A2
65A2
65A2
55A4
55A4
55A4
34C8
34C8
34C8
34C6
34C6
34C6
34B8
34B8
34B8
25D3
25D3
25D3
25C4
25C4
25C4
24D3
24D3
24D3
24C3
24C3
24C3
21C1
21C1
21C1
19D7
19D7
19D7
19D6
19D6
19D6
19D5
19D5
19D5
19D2
19D2
19D2
19D1
19D1
19D1
19C8
19C8
19C8
17D6
17D6
17D6
17D3
17D3
17D3
16D3
16D3
16D3
16C8
16C8
16C8
13B5
13B5
13B5
12B7
12C2
12C2
12A7
12B7
12A7
11C5
11C5
11C5
11B3
11B3
11B3
9B7
9B7
9B7
8C7
8C7
8C7
7D5
7D5
7D5
7B6
7B6
7B6
34D5
34D5
7B5
7B5
7B5
87D6
87D6
87D6
87D6
87D6
87D6
87C6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87C6
87D6
87D6
34D3
34D3
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
87D6
5D4
5D4
5D4
7D8
7B4
7D8
7D8
7D8
7D8
7C8
7D8
7D8
7D8
7D8
7D8
7D8
7D8
7D8
7D8
7D8
7C8
7C8
7C8
7D8
7D8
7D8
7C8
7C8
7C8
7C8
7C8
7C8
7C8
7C8
7C8
7C8
7C8
7C8
7C4
7C4
7C4
7C4
7C4
7B4
7B4
7B4
7B4
7B4
7B4
7B4
7B4
7B4
7B4
7B4
7B4
7B4
7C3
7C3
7C3
7C3
7C3
7C3
7C3
7C3
7C3
7C3
7C3
7C3
7C3
7C3
7C3
7C3
7C3
7C3
7B3
7B3
7B3
7B3
7B3
7B3
7B3
7B3
7B3
7B3
7B3
7B3
7B3
7B3
7D8
7D6
7D8
33C4
33C4
7B3
7B4
7C4
7D6
7D6
7D6
7A3
7C4
7C4
7C4
7C4
7C4
7C4
7C4
7C4
7C4
7C4
7C4
7C4
7C3
7B4
7C4
7C4
7B3
7C3
7B4
7B3
7C3
7C4
5B2
5B2
5B2
5A7
5B7
5A7
5A7
5A7
5A7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5C4
5B4
5B7
5B7
5B7
5B7
5A7
5B7
5A4
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
5B7
CRT_BLUE*
CRT_BLUE
CRT_GREEN*
CRT_GREEN
CRT_RED
CRT_DDC_CLK
CRT_RED*
HSYNC
CRT_DDC_DATA
CRT_VSYNC
CRT_IREF
TV_IRTNC
TV_IRTNB
TV_IREF
TV_IRTNA
TV_DACB_OUT
TV_DACC_OUT
TV_DACA_OUT
LB_DATA2
LB_DATA1
LB_DATA0
LB_DATA2*
LB_DATA1*
LB_DATA0*
LA_DATA2
LA_DATA1
LA_DATA0
LA_DATA2*
LA_DATA1*
LA_DATA0*
LB_CLK
LB_CLK*
LA_CLK
LA_CLK*
L_VDDEN
L_VREFL
L_VREFH
L_VBG
L_IBG
L_DDC_CLK
L_DDC_DATA
EXP_A_COMPI
EXP_A_COMPO
EXP_A_RXN0
EXP_A_RXN1
EXP_A_RXN2
EXP_A_RXN3
EXP_A_RXN4
EXP_A_RXN5
EXP_A_RXN6
EXP_A_RXN7
EXP_A_RXN8
EXP_A_RXN9
EXP_A_RXN10
EXP_A_RXN11
EXP_A_RXN12
EXP_A_RXN13
EXP_A_RXN15
EXP_A_RXN14
EXP_A_RXP0
EXP_A_RXP1
EXP_A_RXP2
EXP_A_RXP4
EXP_A_RXP3
EXP_A_RXP5
EXP_A_RXP6
EXP_A_RXP7
EXP_A_RXP10
EXP_A_RXP9
EXP_A_RXP8
EXP_A_RXP11
EXP_A_RXP12
EXP_A_RXP14
EXP_A_RXP13
EXP_A_RXP15
EXP_A_TXN1
EXP_A_TXN0
EXP_A_TXN3
EXP_A_TXN2
EXP_A_TXN6
EXP_A_TXN5
EXP_A_TXN4
EXP_A_TXN7
EXP_A_TXN8
EXP_A_TXN9
EXP_A_TXN10
EXP_A_TXN11
EXP_A_TXN12
EXP_A_TXN14
EXP_A_TXN13
EXP_A_TXN15
EXP_A_TXP0
EXP_A_TXP2
EXP_A_TXP1
EXP_A_TXP3
EXP_A_TXP4
EXP_A_TXP5
EXP_A_TXP7
EXP_A_TXP6
EXP_A_TXP8
EXP_A_TXP9
EXP_A_TXP10
EXP_A_TXP12
EXP_A_TXP11
EXP_A_TXP13
EXP_A_TXP14
EXP_A_TXP15
L_CLKCTLB
L_BKLTEN
L_CLKCTLA
L_BKLTCTL
(3 OF 10)
LVDS
TV
VGA
PCI-EXPRESS GRAPHICS
IN
IN
OUT
IN
OUT
OUT
OUT
OUT
IN
IN
OUT
OUT
OUT
OUT
IN
OUT
OUT
IO
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
IO
IO
OUT
OUT
OUT
OUT
OUT
OUT
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
OUT
OUT
OUT
OUT
OUT
OUT
IO
IO
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
Tie VCC_TXLVDS and VCCA_LVDS to GND. If SDVO is used
Can leave all signals NC if LVDS is not implemented
CRT Disable
TV-Out Disable
Composite: DACA only
TV-Out Signal Usage:
HSYNC and VSYNC to GND. Tie VCCA_CRTDAC to VCC Core
Unused DAC outputs must remain powered, but can omit
S-Video: DACB & DACC only
connect to GND through 75-ohm resistors.
Tie VCCD_TVDAC, VCCD_QTVDAC, VCCA_TVDACx, and
Component: DACA, DACB & DACC
rail, and tie VSSA_CRTDAC and VCC_SYNC to GND.
VCCA_TVBG to 1.5V power rail. Tie VSSA_TVBG to GND.
Tie DACx_OUT, IRTNx, and IREF to 1.5V power rail.
filtering components. Unused DAC outputs should
Tie R/R#/G/G#/B/B# and IREF to VCC Core rail, tie
VCCD_LVDS must remain powered with proper decoupling.
LVDS Disable
Otherwise, tie VCCD_LVDS to GND also.
SDVOC_CLKP
SDVOC_BLUE
SDVOC_GREEN
SDVOC_RED
SDVOB_BLUE
SDVOB_CLKP
SDVOB_RED#
SDVOB_GREEN#
SDVOB_BLUE#
SDVOB_CLKN
SDVOC_RED#
SDVOC_GREEN#
SDVOC_BLUE#
SDVOC_CLKN
SDVOB_RED
SDVOB_GREEN
SDVO_FLDSTALL
SDVO_INT
SDVO_TVCLKIN
SDVO_INT#
SDVO_TVCLKIN#
SDVO Alternate Function
SDVO_FLDSTALL#
OMIT
945GM
NB
BGA
U1200
E23
D23
C26
C25
C22
B22
J22
A21
B21
H23
D40
D38
F34
G38
V34
W38
Y34
AA38
AB34
AC38
H34
J38
L34
M38
N34
P38
R34
T38
D34
F38
T34
V38
W34
Y38
AA34
AB38
G34
H38
J34
L38
M34
N38
P34
R38
F36
G40
V36
W40
Y36
AA40
AB36
AC40
H36
J40
L36
M40
N36
P40
R36
T40
D36
F40
T36
V40
W36
Y40
AA36
AB40
G36
H40
J36
L40
M36
N40
P36
R40
G23
D32
J30
H30
H29
G26
G25
B38
C35
F32
C33
C32
A32
A33
B37
C37
B34
B35
A36
A37
E26
E27
F30
G30
D29
D30
F28
F29
A16
C18
A19
J20
B16
B18
B19
24.9
1%
1/16W
MF-LF
402
R1310
1
2
NB PEG / Video Interfaces
SYNC_DATE=09/15/2006
SYNC_MASTER=M59_MLB
13 87
06004051-7164
GND
GND
TP_LVDS_CLKCTLB
PP1V5_S0_NB
LVDS_BKLTCTL
TP_LVDS_CLKCTLA
LVDS_BKLTEN
PEG_R2D_C_P<15>
PEG_R2D_C_P<14>
PEG_R2D_C_P<13>
PEG_R2D_C_P<11>
PEG_R2D_C_P<12>
PEG_R2D_C_P<10>
PEG_R2D_C_P<9>
PEG_R2D_C_P<8>
PEG_R2D_C_P<6>
PEG_R2D_C_P<7>
PEG_R2D_C_P<5>
PEG_R2D_C_P<4>
PEG_R2D_C_P<3>
PEG_R2D_C_P<1>
PEG_R2D_C_P<2>
PEG_R2D_C_P<0>
PEG_R2D_C_N<15>
PEG_R2D_C_N<13>
PEG_R2D_C_N<14>
PEG_R2D_C_N<12>
PEG_R2D_C_N<11>
PEG_R2D_C_N<10>
PEG_R2D_C_N<9>
PEG_R2D_C_N<8>
PEG_R2D_C_N<7>
PEG_R2D_C_N<4>
PEG_R2D_C_N<5>
PEG_R2D_C_N<6>
PEG_R2D_C_N<2>
PEG_R2D_C_N<3>
PEG_R2D_C_N<0>
PEG_R2D_C_N<1>
PEG_D2R_P<15>
PEG_D2R_P<13>
PEG_D2R_P<14>
PEG_D2R_P<12>
PEG_D2R_P<11>
PEG_D2R_P<8>
PEG_D2R_P<9>
PEG_D2R_P<10>
PEG_D2R_P<7>
PEG_D2R_P<6>
PEG_D2R_P<5>
PEG_D2R_P<3>
PEG_D2R_P<4>
PEG_D2R_P<2>
PEG_D2R_P<1>
PEG_D2R_P<0>
PEG_D2R_N<14>
PEG_D2R_N<13>
PEG_D2R_N<12>
PEG_D2R_N<11>
PEG_D2R_N<10>
PEG_D2R_N<8>
PEG_D2R_N<6>
PEG_D2R_N<5>
PEG_D2R_N<4>
PEG_D2R_N<3>
PEG_D2R_N<2>
PEG_D2R_N<1>
PEG_D2R_N<0>
PEG_COMP
LVDS_CONN_DDC_DATA
LVDS_CONN_DDC_CLK
LVDS_IBG
TP_LVDS_VBG
GND
GND
LVDS_VDDEN
LVDS_A_CLK_N
LVDS_A_CLK_P
LVDS_B_CLK_N
LVDS_B_CLK_P
LVDS_A_DATA_N<0>
LVDS_A_DATA_N<1>
LVDS_A_DATA_N<2>
LVDS_A_DATA_P<0>
LVDS_A_DATA_P<1>
LVDS_A_DATA_P<2>
LVDS_B_DATA_N<0>
LVDS_B_DATA_N<1>
LVDS_B_DATA_N<2>
LVDS_B_DATA_P<0>
LVDS_B_DATA_P<1>
LVDS_B_DATA_P<2>
PP1V05_S0
TP_CRT_DDC_DATA
PP1V05_S0
TP_CRT_DDC_CLK
PP1V05_S0
PP1V05_S0
PP1V05_S0
PP1V05_S0
PP1V05_S0
PEG_D2R_N<15>
PEG_D2R_N<9>
PEG_D2R_N<7>
PP1V5_S0_NB
PP1V5_S0_NB
PP1V5_S0_NB
PP1V5_S0_NB
PP1V5_S0_NB
PP1V5_S0_NB
PP1V5_S0_NB
67D8
67D8
67D8
67D8
67D8
67D6
67D6
67D6
67D6
67D6
65A2
65A2
65A2
65A2
65A2
55A4
55A4
55A4
55A4
55A4
34C8
34C8
34C8
34C8
34C8
34C6
34C6
34C6
34C6
34C6
34B8
34B8
34B8
34B8
34B8
25D3
25D3
25D3
25D3
25D3
25C4
25C4
25C4
25C4
25C4
24D3
24D3
24D3
24D3
24D3
24C3
24C3
24C3
24C3
24C3
21C1
21C1
21C1
21C1
21C1
19D7
19D7
19D7
19D7
19D7
19D6
19D6
19D6
19D6
19D6
19D5
19D5
19D5
19D5
19D5
67C8
67C8
67C8
67C8
67C8
67C8
67C8
19D2
19D2
19D2
19D2
19D2
67C6
67C6
67C6
67C6
67C6
67C6
67C6
19D1
19D1
19D1
19D1
19D1
67B6
67B6
67B6
67B6
67B6
67B6
67B6
19C8
19C8
19C8
19C8
19C8
62A7
62A7
62A7
62A7
62A7
62A7
62A7
17D6
17D6
17D6
17D6
17D6
19D7
19D7
19D7
19D7
19D7
19D7
19D7
17D3
17D3
17D3
17D3
17D3
19D6
19D6
19D6
19D6
19D6
19D6
19D6
16D3
16D3
16D3
16D3
16D3
19D5
19D5
19D5
19D5
19D5
19D5
19D5
16C8
16C8
16C8
16C8
16C8
19D2
19D2
19D2
19D2
19D2
19D2
19D2
13B5
13B5
13B5
13B5
13B5
19D1
19D1
19D1
19D1
19D1
19D1
19D1
12C2
12C2
12C2
12C2
12C2
19C5
19C5
19C5
19C5
19C5
19C5
19C5
12B7
12B7
12B7
12B7
12B7
19C4
19C4
19C4
19C4
19C4
19C4
19C4
12A7
12A7
12A7
12A7
12A7
19C1
19C1
19C1
19C1
19C1
19C1
19C1
11C5
11C5
11C5
11C5
11C5
19B8
19B8
19B8
19B8
19B8
19B8
19B8
11B3
11B3
11B3
11B3
11B3
19B5
19B5
19B5
19B5
19B5
19B5
19B5
9B7
9B7
9B7
9B7
9B7
19A5
19A5
19A5
19A5
19A5
19A5
19A5
8C7
8C7
8C7
8C7
8C7
17C6
17C6
17C6
17C6
17C6
17C6
17C6
7D5
7D5
7D5
7D5
7D5
17B6
17B6
17B6
17B6
17B6
17B6
17B6
7B6
7B6
7B6
7B6
7B6
16D1
16D1
16D1
16D1
16D1
16D1
16D1
82A7
82A7
7B5
7B5
7B5
7B5
7B5
13D2
13D2
13D2
13D2
13D2
13D2
19D4
13C5
19D4
82A5
82A5
5D4
19D6
5D4
19D6
5D4
5D4
5D4
13C5
13C5
13C5
13C5
13C5
13C5
19D3
5D4
82A4
19D3
82A4
70B5
70B5
70B5
70B5
70B5
70B5
70C5
70C5
70C5
70C5
70C5
70D5
70D5
70D5
70D5
70D5
70B5
70B5
70B5
70B5
70B5
70B5
70C5
70C5
70C5
70C5
70C5
70C5
70D5
70D5
70D5
70D5
70B1
70B1
70B1
70B1
70B1
70C1
70C1
70C1
70C1
70C1
70C1
70D1
70D1
70D1
70D1
70D1
70B1
70B1
70B1
70B1
70B1
70C1
70C1
70C1
70C1
70D1
70D1
70D1
70D1
79C3
79C3
19D3
82A4
82D3
82D3
82C3
82C3
82D3
82D3
82D3
82D3
82D3
82D3
82D3
82C3
82D3
82D3
82C3
82C3
5B2
19D5
5B2
19D5
5B2
5B2
5B2
70B1
70C1
70C1
5D4
5D4
5D4
5D4
5D4
5D4
SM_CS0*
RSVD15
RSVD14
SM_CKE2
RSVD2
RSVD3
RSVD6
RSVD4
RSVD5
RSVD8
RSVD7
RSVD9
RSVD1
RSVD10
RSVD11
RSVD12
RSVD13
CFG1
CFG0
CFG2
CFG3
CFG4
CFG6
CFG5
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG17
CFG16
CFG15
CFG18
CFG19
CFG20
PM_BM_BUSY*
PM_EXTTS0*
PM_EXTTS1*
PW_THRMTRIP*
PWROK
RSTIN*
SDVO_CTRLCLK
SDVO_CTRLDATA
ICH_SYNC*
CLK_REQ*
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
NC0
NC1
NC13
NC12
NC11
NC10
NC18
NC17
NC16
NC15
NC14
SM_CK0
SM_CK1
SM_CK2
SM_CK0*
SM_CK3
SM_CK1*
SM_CK2*
SM_CK3*
SM_CKE0
SM_CKE1
SM_CKE3
SM_CS1*
SM_CS2*
SM_CS3*
SMOCDCOMP0
SMOCDCOMP1
SM_ODT1
SM_ODT0
SM_ODT2
SMRCOMP*
SM_ODT3
SMRCOMP
SMVREF0
SMVREF1
G_CLKIN*
G_CLKIN
D_REFCLKIN*
D_REFCLKIN
D_REFSSCLKIN*
D_REFSSCLKIN
DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3
DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3
DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3
DMI_TXP0
DMI_TXP2
DMI_TXP1
DMI_TXP3
DDR MUXING
CFG
NC PM
CLKDMI
MISC
(2 OF 10)
RSVD
IN
IN
IN
IN
IN
OUT
OUT
IN
IN
IN
IO
IO
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
NC
NC
IPD
IPD
(LA_DATAN3)
(LA_DATAP3)
(LB_DATAN3)
(LB_DATAP3)
(H_EDRDY#)
(D_PLLMON1)
(H_PROCHOT#)
(TESTIN#)
(TV_DCONSEL0)
(TV_DCONSEL1)
(H_PLLMON1)
(H_PLLMON1#)
(H_PCREQ#)
(VSS_MCHDETECT)
(D_PLLMON1#)
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
IPU
IPD
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
NC
NC
IPU
IPU
NC
NC
NC
OMIT
945GM
NB
BGA
U1200
K16
K18
E16
D15
G15
K15
C15
H16
G18
H15
J25
K27
J18
J26
F18
E15
F15
E18
D19
D16
G16
H32
A26
A27
D41
C40
AE35
AF39
AG35
AH39
AC35
AE39
AF35
AG39
AE37
AF41
AG37
AH41
AC37
AE41
AF37
AG41
AG33
AF33
K28
D1
C41
B2
AY41
AY1
AW41
AW1
A40
A4
A39
A3
C1
BA41
BA40
BA39
BA3
BA2
BA1
B41
G28
F25
H26
G6
AH33
AH34
T32
J29
A41
A35
A34
D28
D27
R32
F3
F7
AG11
AF11
H7
J19
K30
H28
H27
AY35
AW35
AR1
AT1
AW7
AY7
AW40
AY40
AU20
AT20
BA29
AY29
AW13
AW12
AY21
AW21
BA13
BA12
AY20
AU21
AL20
AF10
AT9
AV9
AK1
AK41
100
5%
1/16W
MF-LF
402
R1430
1 2
1/16W
MF-LF
5%
402
10K
R1441
1
2
MF-LF
1/16W
5%
402
10K
R1440
1
2
20%
10V
CERM
402
0.1uF
C1416
1
2
20%
10V
CERM
402
0.1uF
C1415
1
2
80.6
MF-LF
402
1%
1/16W
R1410
1
2
80.6
MF-LF
402
1%
1/16W
R1411
1
2
10K
MF-LF
402
5%
1/16W
R1420
1
2
14 87
06004051-7164
SYNC_MASTER=M59_MLB
SYNC_DATE=09/15/2006
NB Misc Interfaces
TP_NB_XOR_FSB2_H7
NC_NB_XOR_LVDS_D27
NC_NB_XOR_LVDS_D28
NC_NB_XOR_LVDS_A34
MEMVREF_OUT
MEMVREF_OUT
MEM_RCOMP
MEM_RCOMP_L
PP1V8_S3
MEM_CKE<2>
MEM_CS_L<1>
MEM_CS_L<2>
MEM_CS_L<3>
MEM_ODT<1>
MEM_ODT<2>
NB_CFG<12>
MEM_CS_L<0>
NB_BSEL<1>
NB_BSEL<0>
NB_BSEL<2>
NB_CFG<3>
NB_CFG<4>
NB_CFG<6>
NB_CFG<5>
NB_CFG<7>
NB_CFG<9>
NB_CFG<10>
TP_NB_CFG<14>
NB_CFG<17>
NB_CFG<16>
TP_NB_CFG<15>
NB_CFG<19>
NB_CFG<20>
PM_BMBUSY_L
PM_THRMTRIP_L
VR_PWRGOOD_DELAY
TP_SDVO_CTRLCLK
TP_SDVO_CTRLDATA
NB_SB_SYNC_L
MEM_CLK_P<0>
MEM_CLK_P<1>
MEM_CLK_P<2>
MEM_CLK_N<0>
MEM_CLK_P<3>
MEM_CLK_N<1>
MEM_CLK_N<2>
MEM_CLK_N<3>
MEM_CKE<0>
MEM_CKE<1>
MEM_CKE<3>
MEM_ODT<0>
MEM_ODT<3>
NB_CLK100M_GCLKIN_N
NB_CLK100M_GCLKIN_P
DMI_S2N_N<0>
DMI_S2N_N<1>
DMI_S2N_N<2>
DMI_S2N_N<3>
DMI_S2N_P<0>
DMI_S2N_P<1>
DMI_S2N_P<2>
DMI_S2N_P<3>
DMI_N2S_N<0>
DMI_N2S_N<1>
DMI_N2S_N<2>
DMI_N2S_N<3>
DMI_N2S_P<0>
DMI_N2S_P<2>
DMI_N2S_P<1>
DMI_N2S_P<3>
PLT_RST_L
NB_CFG<8>
NB_CFG<11>
NB_CFG<13>
NB_CFG<18>
PP3V3_S0
PM_DPRSLPVR
TP_NB_TESTIN_L
NC_NB_XOR_LVDS_A35
NB_TV_DCONSEL0
NB_TV_DCONSEL1
PP3V3_S0
NB_CLK_DREFSSCLKIN_P
NB_CLK_DREFSSCLKIN_N
NB_CLK_DREFCLKIN_P
NB_CLK_DREFCLKIN_N
CLK_NB_OE_L
NB_RST_IN_L_R
PM_EXTTS_L
82D5
82D5
82C6
82C6
82B3
82B3
82A4
82A4
79D3
79D3
79A8
79A8
71D2
71D2
67C5
67C5
67C3
67C3
67B3
67B3
67A3
67A3
66B6
66B6
66B5
66B5
66B1
66B1
65D6
65D6
65B3
65B3
62A6
62A6
61D8
61D8
61A5
61A5
60D4
60D4
60C7
60C7
58C7
58C7
58C4
58C4
57B6
57B6
54D4
54D4
54B5
54B5
52D3
52D3
49C7
49C7
49C4
49C4
49B5
49B5
40B6
40B6
36D6
36D6
34A8
34A8
33D8
33D8
33D3
33D3
33C7
33C7
29A6
29A6
29A3
29A3
28A6
28A6
27D8
27D8
27D5
27D5
27D3
27D3
27C3
27C3
26D1
26D1
26B8
26B8
26B6
26B6
26B4
26B4
25D8
25D8
25D3
25D3
25C6
25C6
25C4
25C4
25B8
25B8
25B4
25B4
25A4
25A4
24D3
24D3
67B8
24C3
24C3
67B6
24B5
24B5
64C1
24B3
24B3
64A6
23D5
23D5
37B2
23B3
23B3
32C6
22B5
22B5
31C5
21D3
21D3
29D6
82A4
21C3
21C3
29D3
79A8
20B4
20B4
29B2
26C3
20A4
20A4
28D6
26C1
19C7
19C7
28D3
26B1
19C6
19C6
32B4
32B4
28B2
26A4
17C6
17C6
52D5
32B3
32B3
19D7
34C5
34C5
22A6
14D6
87C6
14C7
34B5
34B5
52D3
29D6
29D6
16B6
52C1
61C7
34C4
34C4
6C7
10C5
61C8
10C5
34B4
34B4
34B4
34B4
51B7
19D4
19D4
19D4
28D6
28D6
5D4
30D6
30D6
30D6
30D6
30C6
30C6
30D6
21C2
26B5
19D4
19D4
22A6
30D6
30D6
30D6
30C6
30C6
33B4
33B4
6C6
5D4
23C3
19D4
5D4
33B4
33B4
34B2
34B2
33B4
29C3
19D3
19D3
19D3
14C2
14C2
5B2
29C6
28B6
29B3
29B6
28B6
29B3
6C6
28B3
34B7
34C7
34B7
6D6
6D6
6D6
20C7
20C7
20B7
6D6
6D7
6D6
20C5
6D7
20B5
20A5
23C5
7C6
5A4
19D3
19D3
5A4
28D3
28A3
29A3
28D3
29D3
28A3
29A3
29D3
28C6
28C3
29C3
28B3
29B6
5B4
5B4
22D2
22D2
22D2
22D2
22D2
22D2
22D2
22D2
22D2
22D2
22D2
22D2
5C4
6D6
6D6
6C6
20B5
5A4
5B4
19D3
5A4
5B4
5B4
5B4
5B4
5B4
28C3
SA_DQ1
SA_DQ0
SA_DQ2
SA_DQ3
SA_DQ4
SA_DQ5
SA_DQ6
SA_DQ7
SA_DQ8
SA_DQ9
SA_DQ10
SA_DQ12
SA_DQ11
SA_DQ13
SA_DQ14
SA_DQ15
SA_DQ16
SA_DQ17
SA_DQ18
SA_DQ19
SA_DQ20
SA_DQ21
SA_DQ22
SA_DQ23
SA_DQ24
SA_DQ25
SA_DQ26
SA_DQ27
SA_DQ29
SA_DQ28
SA_DQ30
SA_DQ31
SA_DQ32
SA_DQ33
SA_DQ35
SA_DQ34
SA_DQ36
SA_DQ37
SA_DQ38
SA_DQ39
SA_DQ40
SA_DQ41
SA_DQ42
SA_DQ43
SA_DQ44
SA_DQ46
SA_DQ45
SA_DQ47
SA_DQ48
SA_DQ49
SA_DQ50
SA_DQ51
SA_DQ52
SA_DQ53
SA_DQ54
SA_DQ55
SA_DQ56
SA_DQ57
SA_DQ58
SA_DQ59
SA_DQ60
SA_DQ61
SA_DQ62
SA_DQ63
SA_BS1
SA_BS0
SA_BS2
SA_CAS*
SA_DM0
SA_DM1
SA_DM2
SA_DM3
SA_DM5
SA_DM4
SA_DM7
SA_DM6
SA_DQS0
SA_DQS2
SA_DQS1
SA_DQS3
SA_DQS5
SA_DQS4
SA_DQS6
SA_DQS7
SA_DQS3*
SA_DQS2*
SA_DQS4*
SA_DQS5*
SA_DQS6*
SA_DQS7*
SA_MA1
SA_MA0
SA_MA2
SA_MA3
SA_MA5
SA_MA4
SA_MA6
SA_MA7
SA_MA9
SA_MA8
SA_MA10
SA_MA11
SA_MA12
SA_MA13
SA_RAS*
SA_RCVENIN*
SA_RCVENOUT*
SA_WE*
SA_DQS1*
SA_DQS0*
(4 OF 10)
DDR SYSTEM MEMORY A
IO
IO
IO
IO
IO
IO
OUT
OUT
OUT
OUT
OUT
IO
OUT
OUT
IO
IO
IO
IO
IO
IO
IO
IO
IO IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
SB_DQ1
SB_DQ0
SB_DQ2
SB_DQ3
SB_DQ4
SB_DQ5
SB_DQ6
SB_DQ7
SB_DQ8
SB_DQ9
SB_DQ10
SB_DQ12
SB_DQ11
SB_DQ13
SB_DQ14
SB_DQ15
SB_DQ16
SB_DQ17
SB_DQ18
SB_DQ19
SB_DQ20
SB_DQ21
SB_DQ22
SB_DQ23
SB_DQ24
SB_DQ25
SB_DQ26
SB_DQ27
SB_DQ29
SB_DQ28
SB_DQ30
SB_DQ31
SB_DQ32
SB_DQ33
SB_DQ35
SB_DQ34
SB_DQ36
SB_DQ37
SB_DQ38
SB_DQ39
SB_DQ40
SB_DQ41
SB_DQ42
SB_DQ43
SB_DQ44
SB_DQ46
SB_DQ45
SB_DQ47
SB_DQ48
SB_DQ49
SB_DQ50
SB_DQ51
SB_DQ52
SB_DQ53
SB_DQ54
SB_DQ55
SB_DQ56
SB_DQ57
SB_DQ58
SB_DQ59
SB_DQ60
SB_DQ61
SB_DQ62
SB_DQ63
SB_BS1
SB_BS0
SB_BS2
SB_CAS*
SB_DM0
SB_DM1
SB_DM2
SB_DM3
SB_DM5
SB_DM4
SB_DM7
SB_DM6
SB_DQS0
SB_DQS2
SB_DQS1
SB_DQS3
SB_DQS5
SB_DQS4
SB_DQS6
SB_DQS7
SB_DQS3*
SB_DQS2*
SB_DQS4*
SB_DQS5*
SB_DQS6*
SB_DQS7*
SB_MA1
SB_MA0
SB_MA2
SB_MA3
SB_MA5
SB_MA4
SB_MA6
SB_MA7
SB_MA9
SB_MA8
SB_MA10
SB_MA11
SB_MA12
SB_MA13
SB_RAS*
SB_RCVENIN*
SB_RCVENOUT*
SB_WE*
SB_DQS1*
SB_DQS0*
(5 OF 10)
DDR SYSTEM MEMORY B
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
OUT
OUT
OUT
IO
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IO
OUT
OUT
OUT
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
OUT
IO
IO
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IO
OUT
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
OUT
OUT
OUT
IO
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IO
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
NC
NC
NC
NC
OMIT
NB
945GM
BGA
U1200
AU12
AV14
BA20
AY13
AJ33
AM35
AL26
AN22
AM14
AL9
AR3
AH4
AJ35
AJ34
AR31
AP31
AN38
AM36
AM34
AN33
AK26
AL27
AM26
AN24
AM31
AK28
AL28
AM24
AP26
AP23
AL22
AP21
AN20
AL23
AP24
AM33
AP20
AT21
AR12
AR14
AP13
AP12
AT13
AT12
AL14
AL12
AJ36
AK9
AN7
AK8
AK7
AP9
AN9
AT5
AL5
AY2
AW2
AK35
AP1
AN2
AV2
AT3
AN1
AL2
AG7
AF9
AG4
AF6
AJ32
AG9
AH6
AF4
AF8
AH31
AN35
AP33
AK33
AK32
AT33
AU33
AN28
AN27
AM22
AM21
AN12
AM12
AN8
AL8
AP3
AN3
AG5
AH5
AY16
AU14
AU13
AT17
AV20
AV12
AW16
BA16
BA17
AU16
AV17
AU17
AW17
AT16
AW14
AK23
AK24
AY14
OMIT
NB
945GM
BGA
U1200
AT24
AV23
AY28
AR24
AK36
AR38
AT36
BA31
AL17
AH8
BA5
AN4
AK39
AJ37
AU38
AV38
AP38
AR40
AW38
AY38
BA38
AV36
AR36
AP36
AP39
BA36
AU36
AP35
AP34
AY33
BA33
AT31
AU29
AU31
AW31
AR41
AV29
AW29
AM19
AL19
AP14
AN14
AN17
AM16
AP15
AL15
AJ38
AJ11
AH10
AJ9
AN10
AK13
AH11
AK10
AJ8
BA10
AW10
AK38
BA4
AW4
AY10
AY9
AW5
AY5
AV4
AR5
AK4
AK3
AN41
AT4
AK5
AJ5
AJ3
AP41
AT40
AV41
AM39
AM40
AT39
AU39
AU35
AT35
AR29
AP29
AR16
AP16
AR10
AT10
AR7
AT7
AN5
AP5
AY23
AW24
AV24
BA27
AY27
AR23
AY24
AR28
AT27
AT28
AU27
AV28
AV27
AW27
AU23
AK16
AK18
AR27
15 87
06004051-7164
NB DDR2 Interfaces
SYNC_MASTER=M59_MLB
SYNC_DATE=09/15/2006
MEM_A_DQ<5>
MEM_A_DQS_N<0>
MEM_A_DQS_N<1>
MEM_A_WE_L
MEM_A_RAS_L
MEM_A_A<13>
MEM_A_A<12>
MEM_A_A<11>
MEM_A_A<10>
MEM_A_A<8>
MEM_A_A<9>
MEM_A_A<7>
MEM_A_A<6>
MEM_A_A<4>
MEM_A_A<5>
MEM_A_A<3>
MEM_A_A<2>
MEM_A_A<0>
MEM_A_A<1>
MEM_A_DQS_N<7>
MEM_A_DQS_N<6>
MEM_A_DQS_N<5>
MEM_A_DQS_N<4>
MEM_A_DQS_N<2>
MEM_A_DQS_N<3>
MEM_A_DQS_P<7>
MEM_A_DQS_P<6>
MEM_A_DQS_P<4>
MEM_A_DQS_P<5>
MEM_A_DQS_P<3>
MEM_A_DQS_P<1>
MEM_A_DQS_P<2>
MEM_A_DQS_P<0>
MEM_A_DM<6>
MEM_A_DM<7>
MEM_A_DM<4>
MEM_A_DM<5>
MEM_A_DM<3>
MEM_A_DM<2>
MEM_A_DM<1>
MEM_A_DM<0>
MEM_A_CAS_L
MEM_A_BS<2>
MEM_A_BS<0>
MEM_A_BS<1>
MEM_A_DQ<63>
MEM_A_DQ<62>
MEM_A_DQ<61>
MEM_A_DQ<60>
MEM_A_DQ<59>
MEM_A_DQ<58>
MEM_A_DQ<57>
MEM_A_DQ<56>
MEM_A_DQ<55>
MEM_A_DQ<54>
MEM_A_DQ<53>
MEM_A_DQ<52>
MEM_A_DQ<51>
MEM_A_DQ<50>
MEM_A_DQ<49>
MEM_A_DQ<48>
MEM_A_DQ<47>
MEM_A_DQ<45>
MEM_A_DQ<46>
MEM_A_DQ<44>
MEM_A_DQ<43>
MEM_A_DQ<42>
MEM_A_DQ<41>
MEM_A_DQ<40>
MEM_A_DQ<39>
MEM_A_DQ<38>
MEM_A_DQ<37>
MEM_A_DQ<36>
MEM_A_DQ<34>
MEM_A_DQ<35>
MEM_A_DQ<33>
MEM_A_DQ<32>
MEM_A_DQ<31>
MEM_A_DQ<30>
MEM_A_DQ<28>
MEM_A_DQ<29>
MEM_A_DQ<27>
MEM_A_DQ<26>
MEM_A_DQ<25>
MEM_A_DQ<24>
MEM_A_DQ<23>
MEM_A_DQ<22>
MEM_A_DQ<21>
MEM_A_DQ<20>
MEM_A_DQ<19>
MEM_A_DQ<18>
MEM_A_DQ<17>
MEM_A_DQ<16>
MEM_A_DQ<15>
MEM_A_DQ<14>
MEM_A_DQ<13>
MEM_A_DQ<11>
MEM_A_DQ<12>
MEM_A_DQ<10>
MEM_A_DQ<9>
MEM_A_DQ<8>
MEM_A_DQ<7>
MEM_A_DQ<6>
MEM_A_DQ<4>
MEM_A_DQ<3>
MEM_A_DQ<2>
MEM_A_DQ<0>
MEM_A_DQ<1>
MEM_B_DQS_N<0>
MEM_B_DQS_N<1>
MEM_B_WE_L
MEM_B_RAS_L
MEM_B_A<13>
MEM_B_A<12>
MEM_B_A<11>
MEM_B_A<10>
MEM_B_A<8>
MEM_B_A<9>
MEM_B_A<7>
MEM_B_A<6>
MEM_B_A<4>
MEM_B_A<5>
MEM_B_A<3>
MEM_B_A<2>
MEM_B_A<0>
MEM_B_A<1>
MEM_B_DQS_N<7>
MEM_B_DQS_N<6>
MEM_B_DQS_N<5>
MEM_B_DQS_N<4>
MEM_B_DQS_N<2>
MEM_B_DQS_N<3>
MEM_B_DQS_P<7>
MEM_B_DQS_P<6>
MEM_B_DQS_P<4>
MEM_B_DQS_P<5>
MEM_B_DQS_P<3>
MEM_B_DQS_P<1>
MEM_B_DQS_P<2>
MEM_B_DQS_P<0>
MEM_B_DM<6>
MEM_B_DM<7>
MEM_B_DM<4>
MEM_B_DM<5>
MEM_B_DM<3>
MEM_B_DM<2>
MEM_B_DM<1>
MEM_B_DM<0>
MEM_B_CAS_L
MEM_B_BS<2>
MEM_B_BS<0>
MEM_B_BS<1>
MEM_B_DQ<63>
MEM_B_DQ<62>
MEM_B_DQ<61>
MEM_B_DQ<60>
MEM_B_DQ<59>
MEM_B_DQ<58>
MEM_B_DQ<57>
MEM_B_DQ<56>
MEM_B_DQ<55>
MEM_B_DQ<54>
MEM_B_DQ<53>
MEM_B_DQ<52>
MEM_B_DQ<51>
MEM_B_DQ<50>
MEM_B_DQ<49>
MEM_B_DQ<48>
MEM_B_DQ<47>
MEM_B_DQ<45>
MEM_B_DQ<46>
MEM_B_DQ<44>
MEM_B_DQ<43>
MEM_B_DQ<42>
MEM_B_DQ<41>
MEM_B_DQ<40>
MEM_B_DQ<39>
MEM_B_DQ<38>
MEM_B_DQ<37>
MEM_B_DQ<36>
MEM_B_DQ<34>
MEM_B_DQ<35>
MEM_B_DQ<33>
MEM_B_DQ<32>
MEM_B_DQ<31>
MEM_B_DQ<30>
MEM_B_DQ<28>
MEM_B_DQ<29>
MEM_B_DQ<27>
MEM_B_DQ<26>
MEM_B_DQ<25>
MEM_B_DQ<24>
MEM_B_DQ<23>
MEM_B_DQ<22>
MEM_B_DQ<21>
MEM_B_DQ<20>
MEM_B_DQ<19>
MEM_B_DQ<18>
MEM_B_DQ<17>
MEM_B_DQ<16>
MEM_B_DQ<15>
MEM_B_DQ<14>
MEM_B_DQ<13>
MEM_B_DQ<11>
MEM_B_DQ<12>
MEM_B_DQ<10>
MEM_B_DQ<9>
MEM_B_DQ<8>
MEM_B_DQ<7>
MEM_B_DQ<6>
MEM_B_DQ<5>
MEM_B_DQ<4>
MEM_B_DQ<3>
MEM_B_DQ<2>
MEM_B_DQ<0>
MEM_B_DQ<1>
30B6
30B6
30C6
30C6
30C6
30C6
30C6
30C6
30C6
30C6
30C6
30C6
30C6
30C6
30C6
30C6
30B6
30B6
30B6
30B6
30A6
30A6
30B6
30B6
30B6
30B6
30B6
30B6
30B6
30B6
30B6
30B6
30B6
30B6
30B6
30B6
30A6
30A6
30A6
30A6
28D6
28D6
28D6
28B6
28B3
28B3
28C6
28C3
28B6
28C6
28C6
28C3
28C3
28B3
28B6
28B6
28B3
28B3
28B6
28B3
28A3
28A6
28B6
28C6
28C3
28A3
28A3
28B6
28A6
28C3
28D6
28C6
28D6
28A6
28A6
28B3
28A3
28C6
28C3
28D3
28D3
28B6
28C6
28B6
28B3
28B3
28A3
28A6
28B6
28B6
28A6
28B3
28A3
28A3
28A3
28A6
28A3
28A6
28A6
28A3
28A6
28A3
28A6
28A6
28A3
28A6
28A3
28A6
28A3
28B6
28B3
28B6
28B3
28B3
28B6
28B6
28B3
28C3
28C6
28C6
28C3
28C6
28C3
28C6
28C3
28C3
28C3
28C3
28C6
28C6
28C6
28C3
28C6
28D3
28D6
28D6
28D6
28D3
28D6
28D3
28D3
28D6
28D6
28D6
28D3
28D3
28D3
28D3
29D6
29D6
29B6
29B3
29B3
29C6
29C3
29B6
29C6
29C6
29C3
29C3
29B3
29B6
29B6
29B3
29B3
29B6
29A6
29A3
29B3
29B6
29C6
29C3
29A6
29A3
29B6
29A3
29C3
29D6
29C6
29D6
29A6
29A3
29B3
29A6
29C6
29C3
29D3
29D3
29B6
29C6
29B6
29B3
29A3
29A6
29A6
29A6
29A6
29A3
29A3
29A3
29A3
29A6
29A3
29A6
29A6
29A3
29A6
29A3
29A3
29B3
29A3
29B3
29A6
29A6
29B6
29B6
29B3
29B3
29B3
29B6
29B6
29B6
29B6
29B3
29C3
29C3
29C3
29C6
29C6
29C3
29C6
29C6
29C6
29C3
29C6
29C6
29C6
29C3
29C3
29C3
29D6
29D6
29D6
29D3
29D3
29D6
29D3
29D3
29D6
29D3
29D3
29D6
29D3
29D6
29D3
29D6
VCC_SM19
VCC_SM107
VCC_SM105
VCC_SM106
VCC_SM102
VCC_SM104
VCC_SM103
VCC_SM100
VCC_SM101
VCC_SM98
VCC_SM99
VCC_SM97
VCC_SM95
VCC_SM96
VCC_SM93
VCC_SM94
VCC_SM92
VCC_SM91
VCC_SM90
VCC_SM89
VCC_SM88
VCC_SM86
VCC_SM87
VCC_SM85
VCC_SM84
VCC_SM83
VCC_SM81
VCC_SM80
VCC_SM82
VCC_SM79
VCC_SM78
VCC_SM77
VCC_SM74
VCC_SM75
VCC_SM76
VCC_SM73
VCC_SM72
VCC_SM70
VCC_SM71
VCC_SM68
VCC_SM67
VCC_SM69
VCC_SM65
VCC_SM66
VCC_SM64
VCC_SM63
VCC_SM62
VCC_SM61
VCC_SM60
VCC_SM59
VCC_SM58
VCC_SM56
VCC_SM57
VCC_SM55
VCC_SM53
VCC_SM54
VCC_SM52
VCC_SM50
VCC_SM51
VCC_SM49
VCC_SM48
VCC_SM46
VCC_SM47
VCC_SM44
VCC_SM45
VCC_SM43
VCC_SM41
VCC_SM42
VCC_SM40
VCC_SM39
VCC_SM37
VCC_SM38
VCC_SM36
VCC_SM34
VCC_SM35
VCC_SM32
VCC_SM33
VCC_SM30
VCC_SM31
VCC_SM28
VCC_SM29
VCC_SM27
VCC_SM26
VCC_SM25
VCC_SM23
VCC_SM24
VCC_SM22
VCC_SM21
VCC_SM20
VCC_SM18
VCC_SM16
VCC_SM17
VCC_SM15
VCC_SM13
VCC_SM14
VCC_SM11
VCC_SM12
VCC_SM10
VCC_SM9
VCC_SM8
VCC_SM7
VCC_SM6
VCC_SM5
VCC_SM4
VCC_SM3
VCC_SM0
VCC_SM1
VCC_SM2
VCC_110
VCC_109
VCC_108
VCC_105
VCC_106
VCC_107
VCC_104
VCC_103
VCC_101
VCC_100
VCC_102
VCC_98
VCC_99
VCC_96
VCC_97
VCC_95
VCC_94
VCC_93
VCC_92
VCC_91
VCC_90
VCC_88
VCC_89
VCC_87
VCC_86
VCC_85
VCC_83
VCC_84
VCC_82
VCC_80
VCC_81
VCC_79
VCC_78
VCC_76
VCC_77
VCC_74
VCC_73
VCC_75
VCC_72
VCC_71
VCC_70
VCC_69
VCC_68
VCC_67
VCC_66
VCC_65
VCC_64
VCC_62
VCC_63
VCC_61
VCC_60
VCC_59
VCC_57
VCC_58
VCC_55
VCC_56
VCC_53
VCC_54
VCC_52
VCC_50
VCC_51
VCC_49
VCC_46
VCC_47
VCC_48
VCC_44
VCC_45
VCC_43
VCC_42
VCC_41
VCC_40
VCC_39
VCC_38
VCC_37
VCC_36
VCC_34
VCC_35
VCC_33
VCC_32
VCC_31
VCC_30
VCC_28
VCC_29
VCC_25
VCC_26
VCC_27
VCC_24
VCC_23
VCC_21
VCC_20
VCC_22
VCC_13
VCC_14
VCC_12
VCC_16
VCC_15
VCC_17
VCC_18
VCC_19
VCC_11
VCC_10
VCC_9
VCC_8
VCC_7
VCC_4
VCC_5
VCC_6
VCC_2
VCC_3
VCC_0
VCC_1
(6 OF 10)
VCC
VCCAUX_NCTF57
VCCAUX_NCTF56
VCCAUX_NCTF55
VCCAUX_NCTF54
VCCAUX_NCTF53
VCCAUX_NCTF52
VCCAUX_NCTF51
VCCAUX_NCTF50
VCCAUX_NCTF49
VCCAUX_NCTF47
VCCAUX_NCTF48
VCCAUX_NCTF45
VCCAUX_NCTF44
VCCAUX_NCTF46
VCCAUX_NCTF40
VCCAUX_NCTF39
VCCAUX_NCTF37
VCCAUX_NCTF38
VCCAUX_NCTF36
VCCAUX_NCTF34
VCCAUX_NCTF35
VCCAUX_NCTF32
VCCAUX_NCTF33
VCCAUX_NCTF31
VCCAUX_NCTF30
VCCAUX_NCTF29
VCCAUX_NCTF27
VCCAUX_NCTF28
VCCAUX_NCTF26
VCCAUX_NCTF24
VCCAUX_NCTF25
VCCAUX_NCTF22
VCCAUX_NCTF21
VCCAUX_NCTF23
VCCAUX_NCTF42
VCCAUX_NCTF43
VCCAUX_NCTF41
VCCAUX_NCTF19
VCCAUX_NCTF20
VCCAUX_NCTF18
VCCAUX_NCTF17
VCCAUX_NCTF16
VCCAUX_NCTF14
VCCAUX_NCTF15
VCCAUX_NCTF13
VCCAUX_NCTF12
VCCAUX_NCTF11
VCCAUX_NCTF9
VCCAUX_NCTF10
VCCAUX_NCTF8
VCCAUX_NCTF7
VCCAUX_NCTF6
VCCAUX_NCTF5
VCCAUX_NCTF4
VCCAUX_NCTF3
VCCAUX_NCTF1
VCCAUX_NCTF0
VCCAUX_NCTF2
VSS_NCTF12
VSS_NCTF11
VSS_NCTF10
VSS_NCTF9
VSS_NCTF7
VSS_NCTF8
VSS_NCTF5
VSS_NCTF6
VSS_NCTF4
VSS_NCTF2
VSS_NCTF3
VSS_NCTF0
VSS_NCTF1
VCC_NCTF72
VCC_NCTF71
VCC_NCTF70
VCC_NCTF69
VCC_NCTF68
VCC_NCTF67
VCC_NCTF66
VCC_NCTF65
VCC_NCTF64
VCC_NCTF61
VCC_NCTF62
VCC_NCTF63
VCC_NCTF60
VCC_NCTF57
VCC_NCTF58
VCC_NCTF59
VCC_NCTF56
VCC_NCTF55
VCC_NCTF53
VCC_NCTF54
VCC_NCTF52
VCC_NCTF50
VCC_NCTF51
VCC_NCTF49
VCC_NCTF48
VCC_NCTF46
VCC_NCTF47
VCC_NCTF45
VCC_NCTF44
VCC_NCTF43
VCC_NCTF41
VCC_NCTF40
VCC_NCTF42
VCC_NCTF38
VCC_NCTF39
VCC_NCTF36
VCC_NCTF37
VCC_NCTF34
VCC_NCTF35
VCC_NCTF33
VCC_NCTF31
VCC_NCTF32
VCC_NCTF30
VCC_NCTF29
VCC_NCTF28
VCC_NCTF27
VCC_NCTF26
VCC_NCTF25
VCC_NCTF24
VCC_NCTF23
VCC_NCTF22
VCC_NCTF21
VCC_NCTF20
VCC_NCTF18
VCC_NCTF19
VCC_NCTF17
VCC_NCTF16
VCC_NCTF15
VCC_NCTF13
VCC_NCTF14
VCC_NCTF11
VCC_NCTF12
VCC_NCTF10
VCC_NCTF8
VCC_NCTF9
VCC_NCTF7
VCC_NCTF6
VCC_NCTF5
VCC_NCTF4
VCC_NCTF3
VCC_NCTF2
VCC_NCTF0
VCC_NCTF1
(7 OF 10)
NCTF
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
NCTF balls are Not Critical To Function
These connections can break without
impacting part performance.
Layout Note:
Place near pin BA23
Place near pin BA15
Layout Note:
Layout Note:
Place in cavity
1.05V or 1.5V
1.05V, External Graphics: 1500mA Max
1.5V, Internal Graphics: 5500mA Max
1.05V, Internal Graphics: 3500mA Max
667MTs 1700mA 3200mA
533MTs 1500mA 2800mA
400MTs 1300mA 2400mA
Speed 1 Channel 2 Channel
1.8V Max Current
OMIT
945GM
NB
BGA
U1200
AA33
W33
P32
M19
L19
N18
M18
L18
P17
N17
M17
N16
M16
N32
L16
M32
L32
J32
AA31
W31
V31
T31
R31
P33
P31
N31
M31
AA30
Y30
W30
V30
U30
T30
R30
N33
P30
N30
M30
L30
AA29
Y29
W29
V29
U29
R29
L33
P29
M29
L29
AB28
AA28
Y28
V28
U28
T28
R28
J33
P28
N28
M28
L28
P27
N27
M27
L27
P26
N26
AA32
L26
N25
M25
L25
P24
N24
M24
AB23
AA23
Y23
Y32
P23
N23
M23
L23
AC22
AB22
Y22
W22
P22
N22
W32
M22
L22
AC21
AA21
W21
N21
M21
L21
AC20
AB20
V32
Y20
W20
P20
N20
M20
L20
AB19
AA19
Y19
N19
AU41
AT41
AR34
AR6
AP6
AN6
AL6
AK6
AJ6
AV1
AJ1
BA30
AY30
AW30
AV30
AU30
AT30
AR30
AP30
AN30
AM41
AM30
AM29
AL29
AK29
AJ29
AH29
AJ28
AH28
AJ27
AH27
AU40
BA26
AY26
AW26
AV26
AU26
AT26
AR26
AJ26
AH26
AJ25
BA34
AH25
AJ24
AH24
BA23
AJ23
BA22
AY22
AW22
AV22
AU22
AY34
AT22
AR22
AP22
AK22
AJ22
AK21
AK20
BA19
AY19
AW19
AW34
AV19
AU19
AT19
AR19
AP19
AK19
AJ19
AJ18
AJ17
AH17
AV34
AJ16
AH16
BA15
AY15
AW15
AV15
AU15
AT15
AR15
AJ15
AU34
AJ14
AJ13
AH13
AK12
AJ12
AH12
AG12
AK11
BA8
AY8
AT34
AW8
AV8
AT8
AR8
AP8
BA6
AY6
AW6
AV6
AT6
10%
0.47UF
402
6.3V
CERM-X5R
C1610
1
2
10uF
6.3V
X5R
20%
603
C1621
1
2
603
20%
X5R
6.3V
10uF
C1620
1
2
OMIT
BGA
NB
945GM
U1200
AD27
AC27
AD26
AC26
AB26
AA26
Y26
W26
V26
U26
T26
R26
AB27
AD25
AC25
AB25
AA25
Y25
W25
V25
U25
T25
R25
AA27
AD24
AC24
AB24
AA24
Y24
W24
V24
U24
T24
R24
Y27
AD23
V23
U23
T23
R23
AD22
V22
U22
T22
R22
W27
AD21
V21
U21
T21
R21
AD20
V20
U20
T20
R20
V27
AD19
V19
U19
T19
AD18
AC18
AB18
AA18
Y18
W18
U27
V18
U18
T18
T27
R27
AG27
AF27
AG22
AF22
AG21
AF21
AG20
AF20
AG19
AF19
R19
AG18
AG26
AF18
R18
AG17
AF17
AE17
AD17
AB17
AA17
W17
V17
AF26
T17
R17
AG16
AF16
AE16
AD16
AC16
AB16
AA16
Y16
AG25
W16
V16
U16
T16
R16
AG15
AF15
AE15
AD15
AC15
AF25
AB15
AA15
Y15
W15
V15
U15
T15
R15
AG24
AF24
AG23
AF23
AE27
AE26
AC17
Y17
U17
AE25
AE24
AE23
AE22
AE21
AE20
AE19
AE18
CERM-X5R
6.3V
402
0.47UF
10%
C1611
1
2
10%
0.47UF
402
6.3V
CERM-X5R
C1612
1
2
10%
0.47UF
402
6.3V
CERM-X5R
C1613
1
2
10%
0.47UF
402
6.3V
CERM-X5R
C1614
1
2
10%
0.47UF
402
6.3V
CERM-X5R
C1615
1
2
16 87
06004051-7164
SYNC_MASTER=M59_MLB
SYNC_DATE=09/15/2006
NB Power 1
PP1V8_S3
NB_VCCSM_LF1
NB_VCCSM_LF2
NB_VCCSM_LF5
NB_VCCSM_LF4
PP1V05_S0
PP1V05_S0
PP1V5_S0_NB
67D8
67D8
67D6
67D6
65A2
65A2
55A4
55A4
34C8
34C8
34C6
34C6
34B8
34B8
25D3
25D3
25C4
25C4
24D3
24D3
24C3
24C3
21C1
21C1
19D7
19D7
19D6
19D6
19D5
19D5
67C8
19D2
19D2
67C6
19D1
19D1
67B6
67B8
19C8
19C8
62A7
67B6
17D6
17D6
19D7
64C1
17D3
17D3
19D6
64A6
16D3
16C8
19D5
37B2
13B5
13B5
19D2
32C6
12C2
12C2
19D1
31C5
12B7
12B7
19C5
29D6
12A7
12A7
19C4
29D3
11C5
11C5
19C1
29B2
11B3
11B3
19B8
28D6
9B7
9B7
19B5
28D3
8C7
8C7
19A5
28B2
7D5
7D5
17C6
19D7
7B6
7B6
17B6
14C2
7B5
7B5
13D2
5D4
5D4
5D4
13C5
5B2
5B2
5B2
5D4
VTT0
VTT1
VTT2
VTT3
VTT4
VTT5
VTT6
VTT7
VTT8
VTT9
VTT10
VTT11
VTT12
VTT13
VTT15
VTT14
VTT16
VTT18
VTT17
VTT19
VTT20
VTT21
VTT22
VTT23
VTT24
VTT25
VTT27
VTT26
VTT28
VTT29
VTT31
VTT30
VTT32
VTT34
VTT33
VTT35
VTT36
VTT37
VTT39
VTT38
VTT40
VTT41
VTT42
VTT43
VTT44
VTT45
VTT48
VTT46
VTT47
VTT49
VTT50
VTT52
VTT51
VTT53
VTT55
VTT54
VTT57
VTT56
VTT58
VTT59
VTT60
VTT61
VTT62
VTT64
VTT63
VTT65
VTT66
VTT67
VTT69
VTT68
VTT70
VTT71
VTT73
VTT72
VTT74
VTT76
VTT75
VCCSYNC
VCC_TXLVDS0
VCC_TXLVDS1
VCC_TXLVDS2
VCC3G0
VCC3G1
VCC3G3
VCC3G2
VCC3G4
VCC3G6
VCC3G5
VCCA_3GPLL
VCCA_3GBG
VSSA_3GBG
VCCA_CRTDAC0
VCCA_CRTDAC1
VSSA_CRTDAC
VCCA_DPLLB
VCCA_DPLLA
VCCA_HPLL
VSSA_LVDS
VCCA_LVDS
VCCA_MPLL
VCCA_TVBG
VSSA_TVBG
VCCA_TVDACC0
VCCA_TVDACC1
VCCA_TVDACB0
VCCA_TVDACB1
VCCA_TVDACA0
VCCA_TVDACA1
VCCD_HMPLL0
VCCD_HMPLL1
VCCD_LVDS2
VCCD_LVDS0
VCCD_LVDS1
VCCD_TVDAC
VCC_HV1
VCC_HV2
VCC_HV0
VCCD_QTVDAC
VCCAUX19
VCCAUX18
VCCAUX17
VCCAUX16
VCCAUX14
VCCAUX15
VCCAUX13
VCCAUX12
VCCAUX11
VCCAUX10
VCCAUX0
VCCAUX1
VCCAUX2
VCCAUX3
VCCAUX4
VCCAUX6
VCCAUX5
VCCAUX9
VCCAUX8
VCCAUX7
VCCAUX21
VCCAUX20
VCCAUX23
VCCAUX24
VCCAUX22
VCCAUX25
VCCAUX26
VCCAUX29
VCCAUX28
VCCAUX27
VCCAUX30
VCCAUX31
VCCAUX33
VCCAUX32
VCCAUX34
VCCAUX35
VCCAUX36
VCCAUX38
VCCAUX37
VCCAUX39
VCCAUX40
POWER
(8 OF 10)
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
1500mA Max VCC3G/3GPLL
800mA Max
2mA Max
60mA Max
70mA Max VCCA_CRTDAC/VCCSYNC
20mA Max
24mA Max
10mA Max
50mA Max
50mA Max
45mA Max
45mA Max
120mA Max
150mA Max
See VCCSYNC
40mA Max
1900mA Max
OMIT
BGA
NB
945GM
U1200
AJ41
AB41
Y41
V41
R41
N41
L41
A23
B23
B25
C30
B30
A30
G41
AC33
F21
E21
B26
C39
AF1
A38
AF2
H20
E19
F19
C20
D20
E20
F20
AK31
AF31
AE30
AD30
AC30
AG29
AF29
AE29
AD29
AC29
AG28
AF28
AE31
AE28
AH22
AJ21
AH21
AJ20
AH20
AH19
P19
P16
AH15
AC31
P15
AH14
AG14
AF14
AE14
Y14
AF13
AE13
AF12
AE12
AL30
AD12
AK30
AJ30
AH30
AG30
AF30
AH1
AH2
A28
B28
C28
H19
D21
H22
H41
G21
B39
G20
AC14
AB14
AD13
AC13
AB13
AA13
Y13
W13
V13
U13
T13
R13
W14
N13
M13
L13
AB12
AA12
Y12
W12
V12
U12
T12
V14
R12
P12
N12
M12
L12
R11
P11
N11
M11
R10
T14
P10
N10
M10
P9
N9
M9
R8
P8
N8
M8
R14
P7
N7
M7
R6
P6
M6
A6
R5
P5
N5
P14
M5
P4
N4
M4
R3
P3
N3
M3
R2
P2
N14
M2
D2
AB1
R1
P1
N1
M1
M14
L14
10%
0.47UF
6.3V
CERM-X5R
402
C1711
1
2
20%
0.22uF
6.3V
402
X5R
C1712
1
2
10%
0.47UF
CERM-X5R
6.3V
402
C1713
1
2
SYNC_DATE=09/15/2006
SYNC_MASTER=M59_MLB
NB Power 2
051-7164 06004
8717
PP1V5_S0_NB
PP1V5_S0_NB
PP1V05_S0
NB_VTTLF_CAP3
NB_VTTLF_CAP2
NB_VTTLF_CAP1
GND
PP2V5_S0
PP1V5_S0_NB_VCC3G
PP1V5_S0_NB_VCCA_3GPLL
PP2V5_S0
GND
GND
PP1V5_S0_NB_VCCA_DPLLB
PP1V5_S0_NB_VCCA_DPLLA
PP1V5_S0_NB_VCCA_HPLL
GND
PP2V5_S0
PP1V5_S0_NB_VCCA_MPLL
PP1V5_S0_NB
GND
PP1V5_S0_NB
PP1V5_S0_NB
PP1V5_S0_NB
PP1V5_S0_NB
PP3V3_S0
PP1V5_S0_NB
PP1V5_S0_NB
PP1V05_S0
82D5 82C6 82B3 82A4
79D3 79A8 71D2 67C5 67C3 67B3 67A3 66B6 66B5
66B1 65D6 65B3 62A6 61D8 61A5 60D4 60C7 58C7
58C4 57B6 54D4 54B5 52D3 49C7 49C4 49B5 40B6 36D6
34A8 33D8 33D3 33C7 29A6 29A3
67D8
28A6
67D8
67D6
27D8
67D6
65A2
27D5
65A2
55A4
27D3
55A4
34C8
27C3
34C8
34C6
26D1
34C6
34B8
26B8
34B8
25D3
26B6
25D3
25C4
26B4
25C4
24D3
25D8
24D3
24C3
25D3
24C3
21C1
25C6
21C1
19D7
25C4
19D7
67C8
67C8
19D6
67C8
67C8
67C8
67C8
67C8
25B8
67C8
67C8
19D6
67C6
67C6
19D5
67C6
67C6
67C6
67C6
67C6
25B4
67C6
67C6
19D5
67B6
67B6
19D2
67B6
67B6
67B6
67B6
67B6
25A4
67B6
67B6
19D2
62A7
62A7
19D1
62A7
62A7
62A7
62A7
62A7
24D3
62A7
62A7
19D1
19D7
19D7
19C8
19D7
19D7
19D7
19D7
19D7
24C3
19D7
19D7
19C8
19D6
19D6
17D6
19D6
19D6
19D6
19D6
19D6
24B5
19D6
19D6
17D3
19D5
19D5
16D3
82D3
82D3
19D5
19D5
19D5
19D5
19D5
24B3
19D5
19D5
16D3
19D2
19D2
16C8
82C5
82C5
82D3
19D2
19D2
19D2
19D2
19D2
23D5
19D2
19D2
16C8
19D1
19D1
13B5
67B6
67B6
82C5
19D1
19D1
19D1
19D1
19D1
23B3
19D1
19D1
13B5
19C5
19C5
12C2
67A8
67A8
67B6
19C5
19C5
19C5
19C5
19C5
22B5
19C5
19C5
12C2
19C4
19C4
12B7
67A6
67A6
67A8
19C4
19C4
19C4
19C4
19C4
21D3
19C4
19C4
12B7
19C1
19C1
12A7
66B5
66B5
67A6
19C1
19C1
19C1
19C1
19C1
21C3
19C1
19C1
12A7
19B8
19B8
11C5
63D1
63D1
66B5
19B8
19B8
19B8
19B8
19B8
20B4
19B8
19B8
11C5
19B5
19B5
11B3
19D7
19D7
63D1
19B5
19B5
19B5
19B5
19B5
20A4
19B5
19B5
11B3
19A5
19A5
9B7
19C5
19C5
19D7
19A5
19A5
19A5
19A5
19A5
19C7
19A5
19A5
9B7
17C6
17C6
8C7
19A8
19A8
19C5
17C6
17C6
17C6
17C6
17C6
19C6
17C6
17C6
8C7
17B6
17B6
7D5
19A6
19A6
19A8
17B6
17B6
17B6
17B6
17B6
14D6
17B6
17B6
7D5
16D1
16D1
7B6
19A4
19A4
19A6
16D1
16D1
16D1
16D1
16D1
14C7
16D1
16D1
7B6
13D2
13D2
7B5
17D6
17D6
19A4
13D2
13D2
13D2
13D2
13D2
10C5
13D2
13D2
7B5
13C5
13C5
5D4
17C6
17C6
34B2
17D6
13C5
13C5
13C5
13C5
13C5
5D4
13C5
13C5
5D4
5D4
5D4
5B2
5D4
19B3
19B3
5D4
19A6
19A6
19B6
5D4
19B6
5D4
5D4
5D4
5D4
5D4
5A4
5D4
5D4
5B2
VSS_1
VSS_0
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_9
VSS_8
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_19
VSS_18
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_28
VSS_27
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_37
VSS_36
VSS_39
VSS_38
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_49
VSS_48
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_57
VSS_56
VSS_59
VSS_58
VSS_61
VSS_60
VSS_64
VSS_63
VSS_62
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_73
VSS_72
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_82
VSS_80
VSS_81
VSS_84
VSS_83
VSS_85
VSS_87
VSS_86
VSS_89
VSS_88
VSS_91
VSS_90
VSS_92
VSS_93
VSS_94
VSS_96
VSS_95
VSS_97
VSS_98
VSS_99
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_114
VSS_113
VSS_115
VSS_117
VSS_116
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_127
VSS_126
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_137
VSS_136
VSS_138
VSS_139
VSS_140
VSS_141
VSS_143
VSS_142
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_158
VSS_157
VSS_159
VSS_160
VSS_161
VSS_162
VSS_164
VSS_163
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_172
VSS_171
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS
(9 OF 10)
VSS_272
VSS_271
VSS_269
VSS_270
VSS_268
VSS_266
VSS_267
VSS_265
VSS_264
VSS_263
VSS_261
VSS_262
VSS_260
VSS_259
VSS_258
VSS_256
VSS_257
VSS_255
VSS_254
VSS_253
VSS_251
VSS_252
VSS_250
VSS_248
VSS_249
VSS_247
VSS_246
VSS_245
VSS_243
VSS_244
VSS_242
VSS_241
VSS_240
VSS_238
VSS_239
VSS_237
VSS_236
VSS_235
VSS_233
VSS_234
VSS_232
VSS_231
VSS_230
VSS_228
VSS_229
VSS_227
VSS_225
VSS_226
VSS_224
VSS_223
VSS_222
VSS_220
VSS_221
VSS_219
VSS_218
VSS_217
VSS_215
VSS_216
VSS_214
VSS_213
VSS_212
VSS_210
VSS_211
VSS_209
VSS_207
VSS_208
VSS_205
VSS_206
VSS_204
VSS_202
VSS_203
VSS_201
VSS_200
VSS_199
VSS_197
VSS_198
VSS_196
VSS_195
VSS_194
VSS_192
VSS_193
VSS_191
VSS_190
VSS_189
VSS_187
VSS_188
VSS_186
VSS_184
VSS_185
VSS_183
VSS_182
VSS_180
VSS_181
VSS_273
VSS_274
VSS_276
VSS_275
VSS_277
VSS_279
VSS_278
VSS_281
VSS_280
VSS_282
VSS_283
VSS_284
VSS_286
VSS_285
VSS_287
VSS_288
VSS_289
VSS_291
VSS_290
VSS_293
VSS_292
VSS_294
VSS_296
VSS_295
VSS_297
VSS_299
VSS_298
VSS_301
VSS_302
VSS_300
VSS_304
VSS_303
VSS_305
VSS_306
VSS_307
VSS_309
VSS_308
VSS_311
VSS_310
VSS_312
VSS_313
VSS_314
VSS_315
VSS_317
VSS_316
VSS_318
VSS_319
VSS_320
VSS_322
VSS_321
VSS_323
VSS_324
VSS_325
VSS_327
VSS_326
VSS_328
VSS_329
VSS_330
VSS_332
VSS_331
VSS_334
VSS_333
VSS_335
VSS_337
VSS_336
VSS_338
VSS_339
VSS_340
VSS_342
VSS_343
VSS_341
VSS_345
VSS_344
VSS_346
VSS_347
VSS_348
VSS_350
VSS_349
VSS_352
VSS_351
VSS_353
VSS_354
VSS_355
VSS_356
VSS_357
VSS_358
VSS_359
VSS_360
VSS
(10 OF 10)
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
OMIT
BGA
945GM
NB
U1200
AC41
AA41
AN40
AE34
AC34
C34
AW33
AV33
AR33
AE33
AB33
Y33
V33
AK40
T33
R33
M33
H33
G33
F33
D33
B33
AH32
AG32
AJ40
AF32
AE32
AC32
AB32
G32
B32
AY31
AV31
AN31
AJ31
AH40
AG31
AB31
Y31
AB30
E30
AT29
AN29
AB29
T29
N29
AG40
K29
G29
E29
C29
B29
A29
BA28
AW28
AU28
AP28
AF40
AM28
AD28
AC28
W28
J28
E28
AP27
AM27
AK27
J27
AE40
G27
F27
C27
B27
AN26
M26
K26
F26
D26
AK25
B40
P25
K25
H25
E25
D25
A25
BA24
AU24
AL24
AW23
AY39
AW39
W41
AV39
AR39
AN39
AJ39
AC39
AB39
AA39
Y39
W39
V39
T41
T39
R39
P39
N39
M39
L39
J39
H39
G39
F39
P41
D39
AT38
AM38
AH38
AG38
AF38
AE38
C38
AK37
AH37
M41
AB37
AA37
Y37
W37
V37
T37
R37
P37
N37
M37
J41
L37
J37
H37
G37
F37
D37
AY36
AW36
AN36
AH36
F41
AG36
AF36
AE36
AC36
C36
B36
BA35
AV35
AR35
AH35
AV40
AB35
AA35
Y35
W35
V35
T35
R35
P35
N35
M35
AP40
L35
J35
H35
G35
F35
D35
AN34
AK34
AG34
AF34
OMIT
BGA
945GM
NB
U1200
AT23
AN23
AM23
AH23
AC23
W23
K23
J23
F23
C23
AA22
K22
G22
F22
E22
D22
A22
BA21
AV21
AR21
AN21
AL21
AB21
Y21
P21
K21
J21
H21
C21
AW20
AR20
AM20
AA20
K20
B20
A20
AN19
AC19
W19
K19
G19
C19
AH18
P18
H18
D18
A18
AY17
AR17
AP17
AM17
AK17
AV16
AN16
AL16
J16
F16
C16
AN15
AM15
AK15
N15
M15
L15
B15
A15
BA14
AT14
AK14
AD14
AA14
U14
K14
H14
E14
AV13
AR13
AN13
AM13
AL13
AG13
P13
F13
D13
B13
AY12
AC12
K12
H12
E12
AD11
AA11
Y11
J11
D11
B11
AV10
AP10
AL10
AJ10
AG10
AC10
W10
U10
BA9
AW9
AR9
AH9
AB9
Y9
R9
G9
E9
A9
AG8
AD8
AA8
U8
K8
C8
BA7
AV7
AP7
AL7
AJ7
AH7
AF7
AC7
R7
G7
D7
AG6
AD6
AB6
Y6
U6
N6
K6
H6
B6
AV5
AF5
AD5
AY4
AR4
AP4
AL4
AJ4
Y4
U4
R4
J4
F4
C4
AY3
AW3
AV3
AL3
AH3
AG3
AF3
AD3
AC3
AA3
G3
AT2
AR2
AP2
AK2
AJ2
AD2
AB2
Y2
U2
T2
N2
J2
H2
F2
C2
AL1
18 87
06004051-7164
NB Grounds
SYNC_MASTER=M59_MLB
SYNC_DATE=09/15/2006
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
NR/FB
IN
EN
OUT
GND
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
800mA Max
These are the power signals that leave the NB "block"
Power Interface
40mA Max
MCH VCC_HV BYPASS
(MCH HV BUFFER 3.3V PWR)
Layout Note: Route to caps, then GND
(MCH MEMORY PLL 1.5V PWR)
1500mA Max
1500mA Max
10mA Max?
GMCH CORE PWR 1.05V BYPASS
1900mA Max
3200mA Max
(MCH TVDAC DEDICATED PWR 1.5V)
(MCH TVDAC DIGITAL QUIET 1.5V PWR)
(MCH TV OUT CHANNEL A 3.3V PWR)
(MCH TV OUT CHANNEL B 3.3V PWR)
(MCH TV DAC BAND GAP 3.3V PWR)
(MCH TV OUT CHANNEL C 3.3V PWR)
(MCH CRTDAC ANALOG 2.5V PWR)
(MCH H/V SYNC 2.5V PWR)
Rail Totals:
2310mA Max?
?mA Max
?mA Max
100mA Max
800mA Max
3674mA Max
40mA Max
40mA Max?
2mA Max
150mA Max
3200mA Max
1500mA Max
24mA Max
70mA Max
?mA Max
Layout Note: Route to caps, then GND
10MA MAX
(MCH LVDS ANALOG 2.5V PWR)
MCH VCCA_LVDS BYPASS
132mA Max
?mA Max
60mA Max
GMCH VCC3G FILTER
(PCI-E/DMI ANALOG 1.5V PWR)
1500mA Max
(3GIO PLL 1.5V PWR)
GMCH VCCA_3GPLL FILTER
Layout Note:
be close to MCH
10uF caps should
on opposite side.
(MCH DDR DLL&IO, FSB HSIO&IO PWR 1.5V)
GMCH VCCAUX FILTER
1900mA Max
(MCH PCIE/DMI BAND GAP 2.5V PWR)
2mA Max
MCH VCCA_3GBG BYPASS
be placed in cavity
3GPLL 10uF cap should
Layout Note:
Layout Note:
Place L and C
close to MCH
Place on the edge
Layout Note:
(SHARE C0940 470UF)
45mA Max
45mA Max
GMCH VCCA_HPLL FILTER
(HOST PLL 1.5V PWR)
GMCH VCCA_MPLL FILTER
MCH VTT BYPASS
(MCH FSB 1.05V PWR)
Layout Note:
Place in cavity
100mA Max
(MCH LVDS DIGITAL 1.5V PWR)
MCH VCCD_LVDS BYPASS
20MA MAX
GMCH VCCA_DPLLA FILTER
50MA MAX
50MA MAX
(CRT/TVOUT PLL 1.5V PWR)
GMCH VCCA_DPLLB FILTER
(LVDS PLL 1.5V PWR)
1500mA Max
60MA MAX
(MCH LVDS TRANSMITTER 2.5V PWR)
MCH VCC_TXLVDS BYPASS
402
20%
6.3V
X5R
0.22uF
C1907
1
2
10uF
6.3V
20%
603
X5R
C1972
1
2
6.3V
20%
402
X5R
0.22uF
C1967
1
2
6.3V
603
2.2uF
20%
CERM1
C1966
1
2
6.3V
20%
603
CERM
4.7uF
C1965
1
2
20%
2.5V
TANT
D2T
470uF
CRITICAL
C1900
1
23
1210
91nH
L1970
1 2
0.1uF
402
20%
10V
CERM
C1916
1
2
0.22uF
X5R
402
20%
6.3V
C1906
1
2
0.1uF
CERM
402
20%
10V
C1991
1
2
4.7UF
6.3V
20%
603
CERM
C1990
1
2
10V
20%
402
CERM
0.1uF
C1993
1
2
10uF
X5R
603
20%
6.3V
C1992
1
2
0.1uF
CERM
402
20%
10V
C1995
1
2
20%
16V
CERM
402
0.01UF
C1994
1
2
20%
10uF
6.3V
X5R
603
C1952
1
2
402
MF-LF
1/16W
1%
1.5K
R1990
1
2
SOT23-5
TPS73115
CRITICAL
U1900
3
2
1
4
5
402
CERM
1uF
10%
6.3V
C1950
1
2
402
CERM
0.01uF
10%
16V
C1951
1
2
402
MF-LF
1/16W
5%
0
R1954
1 2
402
MF-LF
1/16W
5%
0
NO STUFF
R1953
1 2
0.1uF
402
10V
20%
NO STUFF
CERM
C1953
1
2
10V
20%
402
CERM
0.1uF
C1915
1
2
0.1uF
402
CERM
10V
20%
C1954
1
2
CASE-B2
220UF
20%
2.5V
POLY
C1970
1
2
20%
6.3V
603
X5R
10uF
C1914
1
2
402
0.22uF
X5R
20%
6.3V
C1905
1
2
20%
10V
402
CERM
0.1uF
C1935
1
2
FERR-120-OHM-0.2A
0603
L1934
1 2
402
CERM
20%
0.1uF
10V
C1937
1
2
10%
CERM
1uF
6.3V
402
C1904
1
2
0603
FERR-120-OHM-0.2A
L1936
1 2
22UF
CERM
805
20%
6.3V
C1934
1
2
22UF
CERM
805
20%
6.3V
C1936
1
2
603
10uF
20%
X5R
6.3V
C1903
1
2
10uF
603
20%
6.3V
X5R
C1902
1
2
0.1uF
10V
20%
402
CERM
C1918
1
2
0.1uF
CERM
402
20%
10V
C1976
1
2
0805
1.0UH-220MA-0.12-OHM
L1975
1 2
10uF
X5R
603
20%
6.3V
C1975
1
2
1%
1/16W
0.51
402
MF-LF
R1975
1 2
6.3V
20%
603
X5R
10uF
C1971
1
2
19 87
06004051-7164
SYNC_MASTER=M57_MLB_MG
SYNC_DATE=08/08/2006
NB (GM) Decoupling
MIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.5 mm
PP1V5_S0_NB_VCC3G
VOLTAGE=1.5V
PP2V5_S0
TPS73115_NR
VOLTAGE=1.5V
MIN_LINE_WIDTH=0.38 mm
MIN_NECK_WIDTH=0.25 mm
PP1V5_S0_NB_VCCA_DPLLB
PP2V5_S0
VOLTAGE=1.5V
MIN_LINE_WIDTH=0.38 mm
MIN_NECK_WIDTH=0.25 mm
PP1V5_S0_NB_DPLL
MIN_LINE_WIDTH=0.38 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=1.5V
PP1V5_S0_NB_VCCA_DPLLA
PP2V5_S0
PP1V5_S0_NB
MIN_NECK_WIDTH=0.4 mm
MIN_LINE_WIDTH=0.6 mm
PP1V5_S0_NB_3GPLL_F
VOLTAGE=1.5V
VOLTAGE=1.5V
PP1V5_S0_NB_VCCA_MPLL
MIN_LINE_WIDTH=0.38 mm
MIN_NECK_WIDTH=0.25 mm
PP1V5_S0_NB_VCCA_HPLL
VOLTAGE=1.5V
MIN_LINE_WIDTH=0.38 mm
MIN_NECK_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.5 mm
VOLTAGE=1.5V
PP1V5_S0_NB_VCCA_3GPLL
PP1V5_S0_NB
PP1V5_S0_NB
PP1V05_S0
PP2V5_S0
GND
GND
GND
LVDS_IBG
GND
TP_CRT_DDC_DATA
MAKE_BASE=TRUE
TP_SDVO_CTRLDATA TP_SDVO_CTRLDATA
MAKE_BASE=TRUE
TP_SDVO_CTRLCLK TP_SDVO_CTRLCLK
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_NB_XOR_LVDS_D28 NC_NB_XOR_LVDS_D28
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_NB_XOR_LVDS_D27 NC_NB_XOR_LVDS_D27
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_NB_XOR_LVDS_A34 NC_NB_XOR_LVDS_A34
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_NB_XOR_LVDS_A35 NC_NB_XOR_LVDS_A35
MAKE_BASE=TRUE
TP_LVDS_CLKCTLB TP_LVDS_CLKCTLB
MAKE_BASE=TRUE
TP_LVDS_CLKCTLA TP_LVDS_CLKCTLA
PP1V5_S0_NB
PP1V5_S0_NB
PP1V5_S0_NB
PP1V05_S0
PP1V5_S0_NB
PP1V05_S0
PP3V3_S0
PP3V3_S0
PP1V5_S0_NB
MAKE_BASE=TRUE
TP_CRT_DDC_CLK TP_CRT_DDC_CLK
PP1V05_S0
PP1V05_S0
PP1V05_S0
PP1V05_S0
PP1V05_S0
PP1V05_S0
PP1V05_S0
PP1V05_S0
PP1V5_S0_NB
PP1V5_S0_NB
PP1V5_S0_NB
GND
PP1V5_S0_NB
PP1V05_S0
PP1V5_S0_NB
GND
PP1V05_S0
GND
PP1V5_S0_NB
PP1V5_S0_NB
PP1V5_S0_NB
PP1V5_S0_NB
PP1V5_S0_NB
PP1V5_S0_NB
GND
PP1V5_S0_NB
PP1V5_S0_NB
PP1V5_S0_NB
MAKE_BASE=TRUE
TP_CRT_DDC_DATA
PP1V5_S0_NB
PP1V5_S0_NB
PP1V5_S0_NB
GND
PP3V3_S0
PP1V05_S0
PP2V5_S0
PP2V5_S0
GND
PP1V8_S3
PP1V5_S0_NB
PP1V05_S0
PP1V5_S0_NB
PP1V5_S0_NB
PP1V05_S0
82D5 82C6
82D5
82B3
82C6
82A4
82B3
79D3
82A4
79A8
79D3
71D2
79A8
67C5
71D2
67C3
67C5
67B3
67C3
67A3
67B3
66B6
67A3
66B5
66B6
66B1
66B5
65D6
66B1
65B3
65D6
62A6
65B3
61D8
62A6
61A5
61D8
60D4
61A5
60C7
60D4
58C7
60C7
58C4
58C7
57B6
58C4
54D4
57B6
54B5
54D4
52D3
54B5
49C7
52D3
49C4
49C7
49B5
49C4
40B6
49B5
36D6
40B6
34A8
36D6
33D8
34A8
33D3
33D8
33C7
33D3
29A6
33C7
29A3
29A6
67D8
67D8
28A6
67D8
67D8
67D8
67D8
67D8
29A3
67D8
67D8
67D8
67D6
67D6
27D8
67D6
67D6
67D6
67D6
67D6
67D8
67D8
67D8
28A6
67D6
67D6
67D6
65A2
65A2
27D5
65A2
65A2
65A2
65A2
65A2
67D6
67D6
67D6
27D8
65A2
65A2
65A2
55A4
55A4
27D3
55A4
55A4
55A4
55A4
55A4
65A2
65A2
65A2
27D5
55A4
55A4
55A4
34C8
34C8
27C3
34C8
34C8
34C8
34C8
34C8
55A4
55A4
55A4
27D3
34C8
34C8
34C8
34C6
34C6
26D1
34C6
34C6
34C6
34C6
34C6
34C8
34C8
34C8
27C3
34C6
34C6
34C6
34B8
34B8
26B8
34B8
34B8
34B8
34B8
34B8
34C6
34C6
34C6
26D1
34B8
34B8
34B8
25D3
25D3
26B6
25D3
25D3
25D3
25D3
25D3
34B8
34B8
34B8
26B8
25D3
25D3
25D3
25C4
25C4
26B4
25C4
25C4
25C4
25C4
25C4
25D3
25D3
25D3
26B6
25C4
25C4
25C4
24D3
24D3
25D8
24D3
24D3
24D3
24D3
24D3
25C4
25C4
25C4
26B4
24D3
24D3
24D3
24C3
24C3
25D3
24C3
24C3
24C3
24C3
24C3
24D3
24D3
24D3
25D8
24C3
24C3
24C3
21C1
21C1
25C6
21C1
21C1
21C1
21C1
21C1
24C3
24C3
24C3
25D3
21C1
21C1
21C1
19D7
19D7
25C4
19D7
19D7
19D7
19D7
19D7
21C1
21C1
21C1
25C6
19D7
19D7
19D7
19D6
19D6
25B8
19D6
19D6
19D6
19D6
19D6
19D7
19D7
19D7
25C4
19D6
19D6
19D6
67C8
19D5
67C8
67C8
19D5
67C8
25B4
67C8
19D5
19D5
19D5
19D5
19D5
19D5
67C8
67C8
67C8
67C8
19D6
19D6
67C8
67C8
67C8
67C8
67C8
67C8
67C8
67C8
67C8
67C8
25B8
19D5
67C8
19D5
67C8
19D5
67C8
67C6
67C8
19D2
67C6
67C6
67C8
19D2
67C6
25A4
67C6
19D2
19D2
19D2
19D2
19D2
19D2
67C6
67C6
67C6
67C6
19D5
67C8
19D5
67C6
67C6
67C6
67C6
67C6
67C6
67C6
67C6
67C6
67C6
67C8
25B4
19D2
67C6
19D2
67C6
19D2
67C6
67B6
67C6
19D1
67B6
67B6
67C6
19D1
67B6
24D3
67B6
19D1
19D1
19D1
19D1
19D1
19D1
67B6
67B6
67B6
67B6
19D1
67C6
19D2
67B6
67B6
67B6
67B6
67B6
67B6
67B6
67B6
67B6
67B6
67C6
25A4
19D1
67B6
19D1
67B6
19D1
67B6
62A7
67B6
19C8
62A7
62A7
67B6
19C8
62A7
24C3
62A7
19C8
19C8
19C8
19C8
19C8
19C8
62A7
62A7
62A7
62A7
19C8
67B6
19C8
62A7
62A7
62A7
62A7
62A7
62A7
62A7
62A7
62A7
62A7
67B6
24D3
19C8
62A7
19C8
62A7
19C8
62A7
19D7
62A7
17D6
19D7
19D7
62A7
17D6
19D7
24B5
19D7
17D6
17D6
17D6
17D6
17D6
17D6
19D7
19D7
19D7
19D7
17D6
62A7
17D6
19D7
19D7
19D7
19D7
19D7
19D7
19D7
19D7
19D7
19D7
62A7
24C3
17D6
19D7
17D6
19D7
17D6
19D7
19D6
19D7
17D3
19D6
19D6
19D7
17D3
19D6
24B3
19D6
17D3
17D3
17D3
17D3
17D3
17D3
19D6
19D6
19D6
19D6
17D3
19D7
17D3
19D6
19D6
19D6
19D6
19D6
19D6
19D6
19D6
19D6
19D6
19D7
24B5
17D3
19D6
17D3
19D6
17D3
19D6
19D5
19D6
16D3
19D5
19D5
19D5
16D3
19D5
23D5
19D5
16D3
16D3
16D3
16D3
16D3
16D3
19D5
19D5
19D5
19D5
16D3
19D6
16D3
19D5
19D5
19D5
19D5
19D5
19D5
19D5
19D5
19D5
19D5
19D6
24B3
16D3
82D3
82D3
19D5
16D3
19D5
16D3
82D3
82D3
82D3
19D5
19D2
19D5
16C8
82D3
19D2
19D2
19D2
16C8
19D2
23B3
19D2
16C8
16C8
16C8
16C8
16C8
16C8
19D2
19D2
19D2
19D2
16C8
19D5
16C8
19D2
19D2
19D2
19D2
19D2
19D2
19D2
19D2
19D2
19D2
19D5
23D5
16C8
82C5
82C5
19D2
16C8
19D2
16C8
82C5
82C5
82C5
19D2
19D1
19D2
13B5
82C5
19D1
19D1
19D1
13B5
19D1
22B5
19D1
13B5
13B5
13B5
13B5
13B5
13B5
19D1
19D1
19D1
19D1
13B5
19D1
13B5
19D1
19D1
19D1
19D1
19D1
19D1
19D1
19D1
19D1
19D1
19D2
23B3
13B5
67B6
67B6
19D1
13B5
19D1
13B5
67B6
67B6
67B6
19D1
19C5
19D1
12C2
67B6
19C5
19C5
19C5
12C2
19C5
21D3
19C5
12C2
12C2
12C2
12C2
12C2
12C2
19C5
19C5
19C5
19C5
12C2
19C5
12C2
19C5
19C5
19C5
19C5
19C5
19C5
19C5
19C5
19C5
19C5
19D1
22B5
12C2
67A8
67A8
19C5
12C2
19C5
12C2
67A8
67A8
67A8
19C5
19C4
19C5
12B7
67A8
19C4
19C4
19C4
12B7
19C4
21C3
19C4
12B7
12B7
12B7
12B7
12B7
12B7
19C4
19C4
19C4
19C4
12B7
19C4
12B7
19C4
19C4
19C4
19C4
19C4
19C4
19C4
19C4
19C4
19C4
19C5
21D3
12B7
67A6
67A6
19C4
12B7
19C4
12B7
67A6
67A6
67A6
19C4
19C1
19C1
12A7
67A6
19C1
19C1
19C1
12A7
19C1
20B4
19C1
12A7
12A7
12A7
12A7
12A7
12A7
19C1
19C1
19C1
19C1
12A7
19C1
12A7
19C1
19C1
19C1
19C1
19C1
19C1
19C1
19C1
19C1
19C1
19C4
21C3
12A7
66B5
66B5
19C1
12A7
19C1
12A7
66B5
66B5
66B5
19C1
19B8
19B8
11C5
66B5
19B8
19B8
19B8
11C5
19B8
20A4
19B8
11C5
11C5
11C5
11C5
11C5
11C5
19B8
19B8
19B8
19B8
11C5
19B8
11C5
19B8
19B8
19B8
19B8
19B8
19B8
19B8
19B8
19B8
19B8
19C1
20B4
11C5
63D1
63D1
19B8
11C5
19B8
11C5
63D1
63D1
63D1
19B8
19B5
19B5
11B3
63D1
19B5
19B5
19B5
11B3
19B5
19C7
19B5
11B3
11B3
11B3
11B3
11B3
11B3
19B5
19B5
19B5
19B5
11B3
19B5
11B3
19B5
19B5
19B5
19B5
19B5
19B5
19B5
19B5
19B5
19B5
19B5
20A4
11B3
19D7
19D7
19B5
11B3
19B5
11B3
19D7
19D7
19D7
19B5
19A5
19A5
9B7
19D7
19A5
19A5
19A5
9B7
19A5
19C6
19A5
9B7
9B7
9B7
9B7
9B7
9B7
19A5
19A5
19A5
19A5
9B7
19A5
9B7
19A5
19A5
19A5
19A5
19A5
19A5
19A5
19A5
19A5
19A5
19A5
19C7
9B7
19C5
19C5
19A5
9B7
19A5
9B7
19C5
19C5
19A8
17C6
17C6
17C6
8C7
19C5
17C6
17C6
17C6
8C7
17C6
17C6
17C6
8C7
8C7
8C7
8C7
8C7
8C7
17C6
17C6
17C6
17C6
8C7
17C6
8C7
17C6
17C6
17C6
17C6
17C6
17C6
17C6
17C6
17C6
17C6
17C6
17C6
8C7
19A8
19A8
17C6
8C7
17C6
8C7
19A6
19A8
19A6
17B6
17B6
17B6
7D5
19A8
17B6
17B6
17B6
7D5
17B6
14D6
17B6
7D5
7D5
7D5
7D5
7D5
7D5
17B6
17B6
17B6
17B6
7D5
17B6
7D5
17B6
17B6
17B6
17B6
17B6
17B6
17B6
17B6
17B6
17B6
17B6
14D6
7D5
19A6
19A6
17B6
7D5
17B6
7D5
19A4 19A4
19A4
16D1
16D1
16D1
7B6
19A6
16D1
16D1
16D1
7B6
16D1
14C7
16D1
7B6
7B6
7B6
7B6
7B6
7B6
16D1
16D1
16D1
16D1
7B6
16D1
7B6
16D1
16D1
16D1
16D1
16D1
16D1
16D1
16D1
16D1
16D1
16D1
14C7
7B6
19A4
19A4
16D1
7B6
16D1
7B6
17D6
17D6
17D6
13D2
13D2
13D2
7B5
17D6
13D2
13D2
13D2
7B5
13D2
10C5
13D2
7B5
7B5
7B5
7B5
7B5
7B5
13D2
13D2
13D2
13D2
7B5
13D2
7B5
13D2
13D2
13D2
13D2
13D2
13D2
13D2
13D2
13D2
13D2
13D2
10C5
7B5
17D6
17D6
13D2
7B5
13D2
7B5
17C6 17C6
34B2
17C6
13C5
13C5
13C5
5D4
17C6
19D6
19D3 19D4
19D3 19D4
19D3 19D4
19D3 19D4
19D3 19D4
19D3 19D4
19D3 19D4
19D3 19D4
13C5
13C5
13C5
5D4
13C5
5D4
13C5
19D5 19D6
5D4
5D4
5D4
5D4
5D4
5D4
13C5
13C5
13C5
13C5
5D4
13C5
5D4
13C5
13C5
13C5
13C5
13C5
13C5
13C5
13C5
19D5
13C5
13C5
13C5
5D4
5D4
17C6
17C6
13C5
5D4
13C5
5D4
17D6
5D4
17C6
5D4
17C6
5D4
5D4
17C6
17C6
17D6
5D4
5D4
5B2
5D4
13D5
13B5
14B6 14B6
14B6 14B6
14C6 14C6
14C6 14C6
14C6 14C6
14C6 14C6
13D5 13D5
13D5 13D5
5D4
5D4
5D4
5B2
5D4
5A4
5D4
13B5 13B5
5B2
5B2
5B2
5B2
5B2
5B2
5D4
5D4
5D4
5D4
5B2
5D4
5B2
5D4
5D4
5D4
5D4
5D4
5D4
5D4
5D4
13B5
5D4
5D4
5D4
5A4
5B2
5D4
5D4
5D4
5B2
5D4
5B2
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
Internal pull-ups
Internal pull-up
RESERVED
RESERVED
NB_CFG<11>
NB_CFG<10>
High = Mobile CPU
NB_CFG<7>
RESERVED
Internal pull-up
DMI x2 Select
PROBABLY NOT NEEDED
PROBABLY NOT NEEDED
Lane Reversal
NB_CFG<4>
NB_CFG<3>
RESERVED
NB_CFG<13:12>
NB_CFG<14>
NB_CFG<5>
NB_CFG<15>
NB_CFG<16>
NB_CFG<6>
NB_CFG<17>
NB_CFG<18>
NB_CFG<8>
NB_CFG<9>
NB_CFG<19>
NB_CFG<20>
Low = DMIx2
High = DMIx4
Low = RESERVED
High = Normal
PCIE Graphics
RESERVED
CPU Strap
RESERVED
Low = Reversed
Internal pull-up
11 = Normal Operation
10 = All-Z Mode Enabled
01 = XOR Mode Enabled
00 = Partial Clock Gating Disable
RESERVED
Internal pull-up
RESERVED
High = Enabled
Low = Disabled
RESERVED
FSB Dynamic
ODT
or PCIe x1
Low = Only SDVO
High = Both active
945 External Design Spec says reserved
Internal pull-down
Internal pull-down
Internal pull-down
Low = 1.05V
High = 1.5V
Low = Normal
High = Reversed
DMI Lane
Reversal
VCC Select
Interop. Mode
PCIe Backward
402
5%
2.2K
1/16W
MF-LF
NBCFG_DMI_X2
R2075
1
2
5%
2.2K
1/16W
MF-LF
402
NBCFG_DYN_ODT_DISABLE
R2085
1
2
402
1/16W
5%
2.2K
NBCFG_VCC_1V5
MF-LF
R2058
1
2
402
MF-LF
1/16W
5%
2.2K
NBCFG_DMI_REVERSE
R2059
1
2
NBCFG_SDVO_AND_PCIE
402
MF-LF
1/16W
5%
2.2K
R2060
1
2
NO STUFF
2.2K
5%
1/16W
MF-LF
402
R2077
1
2
402
MF-LF
1/16W
5%
2.2K
NBCFG_PEG_REVERSE
R2079
1
2
20 87
06004051-7164
NB Config Straps
SYNC_MASTER=M59_MLB
SYNC_DATE=09/15/2006
PP3V3_S0
PP3V3_S0
PP3V3_S0
NB_CFG<18>
NB_CFG<19>
NB_CFG<20>
NB_CFG<16>
NB_CFG<5>
NB_CFG<9>
NB_CFG<7>
82D5
82D5
82C6
82C6
82D5
82B3
82B3
82C6
82A4
82A4
82B3
79D3
79D3
82A4
79A8
79A8
79D3
71D2
71D2
79A8
67C5
67C5
71D2
67C3
67C3
67C5
67B3
67B3
67C3
67A3
67A3
67B3
66B6
66B6
67A3
66B5
66B5
66B6
66B1
66B1
66B5
65D6
65D6
66B1
65B3
65B3
65D6
62A6
62A6
65B3
61D8
61D8
62A6
61A5
61A5
61D8
60D4
60D4
61A5
60C7
60C7
60D4
58C7
58C7
60C7
58C4
58C4
58C7
57B6
57B6
58C4
54D4
54D4
57B6
54B5
54B5
54D4
52D3
52D3
54B5
49C7
49C7
52D3
49C4
49C4
49C7
49B5
49B5
49C4
40B6
40B6
49B5
36D6
36D6
40B6
34A8
34A8
36D6
33D8
33D8
34A8
33D3
33D3
33D8
33C7
33C7
33D3
29A6
29A6
33C7
29A3
29A3
29A6
28A6
28A6
29A3
27D8
27D8
28A6
27D5
27D5
27D8
27D3
27D3
27D5
27C3
27C3
27D3
26D1
26D1
27C3
26B8
26B8
26D1
26B6
26B6
26B8
26B4
26B4
26B6
25D8
25D8
26B4
25D3
25D3
25D8
25C6
25C6
25D3
25C4
25C4
25C6
25B8
25B8
25C4
25B4
25B4
25B8
25A4
25A4
25B4
24D3
24D3
25A4
24C3
24C3
24D3
24B5
24B5
24C3
24B3
24B3
24B5
23D5
23D5
24B3
23B3
23B3
23D5
22B5
22B5
23B3
21D3
21D3
22B5
21C3
21C3
21D3
20B4
20B4
21C3
20A4
20A4
20B4
19C7
19C7
19C7
19C6
19C6
19C6
17C6
17C6
17C6
14D6
14D6
14D6
14C7
14C7
14C7
10C5
10C5
10C5
5D4
5D4
5D4
5A4
5A4
5A4
14C6
14C6
14B6
14C6
14C6
14C6
14C6
IO
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IO
IO
IO
IO
IN
IO
DDACK*
SATARBIASN
SATARBIASP
SATA_CLKN
SATA_CLKP
SATA_2TXP
SATA_2TXN
SATA_2RXN
SATA_2RXP
SATA_0TXP
SATA_0TXN
SATA_0RXP
SATA_0RXN
SATALED*
ACZ_SDOUT
ACZ_SDIN1
ACZ_SDIN2
ACZ_SDIN0
ACZ_SYNC
ACZ_BIT_CLK
LAN_TXD2
LAN_TXD0
LAN_TXD1
LAN_RXD1
LAN_RXD2
LAN_RSTSYNC
LAN_RXD0
LAN_CLK
EE_SHCLK
EE_CS
INTVRMEN
INTRUDER*
RTCRST*
RTCX2
RTCX1
THRMTRIP*
STPCLK*
NMI
SMI*
RCIN*
INTR
INIT*
INIT3_3V*
IGNNE*
GPIO49/CPUPWRGD
FERR*
TP1/DPRSTP*
TP2/DPSLP*
A20M*
CPUSPL*
A20GATE
LFRAME*
LDRQ1*/GPIO23
LDRQ0*
LAD3
LAD2
LAD0
LAD1
EE_DOUT
EE_DIN
ACZ_RST*
DIOR*
IDEIRQ
DIOW*
IORDY
DDREQ
DD0
DD1
DD3
DD2
DD5
DD4
DD6
DD7
DD8
DD11
DD9
DD10
DD12
DD13
DD14
DD15
DA0
DA1
DA2
DCS3*
DCS1*
AC-97/
AZALIA
RTC
LPC
LAN
CPU
IDE
SATA
(1 OF 6)
OUT
OUT
OUT
IN
OUT
IN
IN
IN
IN
OUT
OUT
OUT
OUT
IN
IN
OUT
OUT
OUT
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
(WEAK INT PU)
NOTE: ALL IDE PINS HAVE INTERNAL 33-OHM SERIES R’S
LAYOUT NOTE: PLACE R2101 & R2194 WHERE ACCESSIBLE
NOTE: DDREQ HAS INTERNAL 11.5K PD
NOTE: LAD<0-3> HAVE INTERNAL 20K PU
INTEL HIGH DEFINITION AUDIO
ACZ_SDOUT
ACZ_SYNC
ACZ_BIT_CLK
ACZ_RST#
ACZ_SDIN[0-2]
INTERNAL 20K PD ENABLED WHEN
INTERNAL 20K PD
AC ’07
- LSO BIT IN AC’97 GLOBAL CONTROL REG = 1; OR
- BOTH FUNCTION 2 & 3 OF DEVICE 30 ARE DISABLED
- LSO BIT IN AC’97 GLOBAL CONTROL REG = 1; OR
- BOTH FUNCTION 2 & 3 OF DEVICE 30 ARE DISABLED
INTERNAL 20K PD ENABLED DURING RESET AND WHEN
INTERNAL 20K PD
INTERNAL 20K PD ENABLED WHEN
- LSO BIT IN AC’97 GLOBAL CONTROL REG = 1; OR
NONE
INTERNAL 20K PD
INTERNAL 20K PD ONLY ENABLED IN S3COLD
NOTE: ENABLE INTERNAL 1.05V SUSPEND REG
NOTE: DD<7> HAS INTERNAL 11.5K PD
(HSTROBE)
(STOP)
20K PD
20K PD
20K PD
(DSTROBE)
< 2 IN OF R2107 W/O STUB
LAYOUT NOTE: R2108 TO BE
CHANGED TO 54.9 FOR
LAYOUT NOTE: R2107 TO BE
< 2 IN OF SB
BOM CONSOLIDATION
NOTE: RISING-EDGE TRIGGERED AT CPU
NOTE: KEYBOARD CONTROLLER RESET CPU
POR IS SMC WILL PUT LAN INT’F
NOTE:
INTO RESET STATE TO SAVE PWR.
- BOTH FUNCTION 2 & 3 OF DEVICE 30 ARE DISABLED
INTEL CONFIRMS OK TO LEAVE PINS AS NC
NOTE: LDRQ<0-1># HAVE INTERNAL 20K PU
NOTE: PULLED UP PER INTEL
NOTE: R2110=56 IN CV.
CHANGED TO 54.9 FOR
BOM CONSOLIDATION
NOTE: R2108=56 IN CV.
(WEAK INT PD)
(INT PU)
(INT PU)
NOTE: EE_CS HAS INTERNAL PD, ONLY ENABLED WHEN LAN_RST#=L
402
5%
0
MF-LF
1/16W
NOSTUFF
R2100
1 2
MF-LF
1/16W
5%
2.2K
402
NOSTUFF
R2101
1 2
1/16W
402
39
5%
MF-LF
R2195
1 2
39
R2198
1 2
39
R2197
1 2
39
R2196
1 2
MF-LF
1/16W
5%
10K
402
R2199
1
2
OMIT
ICH7-M
SB
BGA
U2100
AE22
AH28
U1
R5
T2
T3
T1
T4
R6
AG27
AH17
AE17
AF17
AE16
AD16
AB15
AE14
AB13
AC14
AF14
AH13
AH14
AC15
AG13
AF13
AD14
AC13
AD12
AC12
AE12
AF12
AF16
AE15
AF15
AH15
W1
W3
Y2
Y1
AG26
AG24
AH16
AG22
AF22
AG21
AF25
Y5
W4
AG16
AA6
AB5
AC4
Y6
V3
U3
U5
V4
T5
U7
V6
V7
AC3
AA5
AB3
AH24
AG23
AA3
AB1
AB2
AF3
AE3
AG2
AH2
AF7
AE7
AG6
AH6
AF1
AE1
AF18
AH10
AG10
AF23
AH22
AF26
AF24
AH25
MF-LF
1/16W
5%
10K
402
R2194
1
2
MF-LF
1/16W
1%
402
332K
R2105
1
2
402
1%
1/16W
MF-LF
24.9
R2107
1 2
54.9
1%
1/16W
MF-LF
402
R2108
1
2
1%
54.9
402
1/16W
MF-LF
R2110
1 2
SYNC_DATE=09/15/2006
SYNC_MASTER=M59_MLB
SB: 1 OF 4
051-7164
8721
06004
TP_SB_XOR_V7
TP_SB_XOR_V6
TP_SB_XOR_U7
TP_SB_XOR_Y2
TP_SB_XOR_Y1
TP_SB_XOR_W1
SB_INTVRMEN
PP1V05_S0
CPU_FERR_L
SB_A20GATE
CPU_RCIN_L
SATA_C_D2R_P
IDE_PDDACK_L
SATA_RBIAS
SATA_RBIAS
SB_CLK100M_SATA_N
SB_CLK100M_SATA_P
SATA_C_R2D_C_P
SATA_C_R2D_C_N
SATA_C_D2R_N
TP_SATA_A_R2DP
TP_SATA_A_R2DN
TP_SATA_A_D2RP
TP_SATA_A_D2RN
TP_SB_SATALED_L
SB_ACZ_SDATAOUT
TP_SB_ACZ_SDIN1
TP_SB_ACZ_SDIN2
ACZ_SDATAIN<0>
SB_ACZ_SYNC
SB_ACZ_BITCLK
SB_SM_INTRUDER_L
SB_RTC_X1
CPU_THERMTRIP_R
CPU_STPCLK_L
CPU_NMI
CPU_SMI_L
CPU_INTR
CPU_INIT_L
FWH_INIT_L
CPU_IGNNE_L
CPU_PWRGD
CPU_DPRSTP_L
CPU_DPSLP_L
CPU_A20M_L
TP_CPU_CPUSLP_L
SB_ACZ_RST_L
IDE_PDIOR_L
IDE_IRQ14
IDE_PDIOW_L
IDE_PDIORDY
IDE_PDDREQ
IDE_PDD<0>
IDE_PDD<1>
IDE_PDD<5>
IDE_PDD<4>
IDE_PDD<7>
IDE_PDD<8>
IDE_PDD<11>
IDE_PDD<9>
IDE_PDD<10>
IDE_PDD<12>
IDE_PDD<13>
IDE_PDD<14>
IDE_PDD<15>
IDE_PDA<0>
IDE_PDA<1>
IDE_PDA<2>
IDE_PDCS3_L
IDE_PDCS1_L
ACZ_SYNC
SMC_RCIN_L
PP1V05_S0
PM_THRMTRIP_L
ACZ_SDATAOUT
IDE_PDD<6>
PP3V3_S0
PP3V3_S0
LPC_AD<0>
LPC_AD<1>
LPC_AD<2>
LPC_AD<3>
TP_SB_DRQ0_L
LVDS_MUX_SEL_GPU
LPC_FRAME_L
SB_RTC_X2
SB_RTC_RST_L
ACZ_BITCLK
ACZ_RST_L
PP3V3_G3C_SB_RTC_D
TP_SB_XOR_U3
TP_SB_XOR_U5
TP_SB_XOR_V4
TP_SB_XOR_T5
TP_SB_XOR_W3
TP_SB_XOR_V3
IDE_PDD<2>
IDE_PDD<3>
82D5
82D5
82C6
82C6
82B3
82B3
82A4
82A4
79D3
79D3
79A8
79A8
71D2
71D2
67C5
67C5
67C3
67C3
67B3
67B3
67A3
67A3
66B6
66B6
66B5
66B5
66B1
66B1
65D6
65D6
65B3
65B3
62A6
62A6
61D8
61D8
61A5
61A5
60D4
60D4
60C7
60C7
58C7
58C7
58C4
58C4
57B6
57B6
54D4
54D4
54B5
54B5
52D3
52D3
49C7
49C7
49C4
49C4
49B5
49B5
40B6
40B6
36D6
36D6
34A8
34A8
33D8
33D8
33D3
33D3
33C7
33C7
29A6
29A6
67D8
67D8 29A3
29A3
67D6
67D6 28A6
28A6
65A2
65A2 27D8
27D8
55A4
55A4 27D5
27D5
34C8
34C8
27D3
27D3
34C6
34C6
27C3
27C3
34B8
34B8
26D1
26D1
25D3
25D3 26B8
26B8
25C4
25C4 26B6
26B6
24D3
24D3 26B4
26B4
24C3
24C3 25D8
25D8
21C1
21C1 25D3
25D3
19D7
19D7 25C6
25C6
19D6
19D6 25C4
25C4
19D5
19D5
25B8
25B8
19D2
19D2
25B4
25B4
19D1
19D1 25A4
25A4
19C8
19C8 24D3
24D3
17D6
17D6 24C3
24C3
17D3
17D3 24B5
24B5
16D3
16D3 24B3
24B3
16C8
16C8 23D5
23D5
13B5
13B5 23B3
23B3
12C2
12C2 22B5
22B5
12B7
12B7
21D3
21C3
12A7
12A7 20B4
20B4
11C5
11C5 20A4
20A4
11B3
11B3 19C7
19C7
9B7
9B7
19C6
19C6
8C7
8C7
17C6
17C6
7D5
53C5
7D5
14D6
14D6
7B6
34C5
34C5
52D5
7B6
14C7
14C7
60C6
60C6
60C6
26D4
7B5
36A5
36A5
34C3
34C3
87B4
87C6
52D3
87C6
61C7
87C6
87B4
7B5
52C1
87B4
10C5
10C5
53C4
53C5
53C4
87B4
87B4
26D3
5D4
36A4
36A4
33B4
33B4
36A5
36A5
36A5
36A5
48B3
7C8
87C6
87C6
87C6
87C6
51D5
87C6
7B3
7B3
7B3
87C6
48B3
5D4
14B6
48B3
5D4
5D4
51D7
51C7
51C7
26D4
48B3
48B3
25A4
5B2
7C8
81A7
36C4
21B6
21B6
5A7
5A7
81B7
81B7
81A7
36A4
36A4
36A4
36A4
87B4
5C1
87B4
87B4
26D4
26C8
5B4
5C4
7C8
7C8
7C8
7D6
5C2
7C8
5B4
5C4
5B4
7C8
5B4
87B4
36C5
36C4
36C4
36C5
36C5
36C5
36C5
36C5
36C5
36C5
36D4
36C4
36C4
36C4
36C4
36C4
36C4
36C4
36C4
36C4
36C5
36C4
36C5
5C1
51C7
5B2
7C6
5C1
36C5
5A4
5A4
5D2
5C2
5C2
26C8
5B4
5C1
5C1
24B3
36C5
36C5
IN
IO
IO
IO
IO
IO
IO
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IO
IO
IO
IO
IN
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IN
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IO
DMI_ZCOMP
DMI_CLKP
DMI_IRCOMP
USBRBIAS*
USBRBIAS
DMI0RXN
DMI0RXP
DMI0TXN
DMI0TXP
DMI2TXN
DMI2TXP
DMI3RXN
DMI3TXP
DMI3TXN
DMI3RXP
USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP4N
OC0*
OC1*
OC2*
OC3*
OC4*
OC6*/GPIO30
OC5*/GPIO29
SPI_CLK
SPI_CS*
SPI_MOSI
SPI_MISO
SPI_ARB
DMI_CLKN
DMI2RXP
DMI2RXN
DMI1TXP
DMI1TXN
DMI1RXN
DMI1RXP
PERN1
PERP1
PETN1
PETP1
PERN2
PERP2
PETN2
PETP2
PERN3
PERP3
PETN3
PETP3
PERN4
PERP4
PETN4
PETP4
PERN5
PERP5
PETN5
PETP5
PERN6
PERP6
PETN6
PETP6
OC7*/GPIO31
PCI-EXP
(3 OF 6)
DMI
SPI
USB
REQ4*/GPIO22
REQ0*
MCH_SYNC*
RSVD8
RSVD7
RSVD6
RSVD5
RSVD4
GPIO5/PIRQH*
GPIO4/PIRQG*
GPIO3/PIRQF*
GPIO2/PIRQE*
GPIO17/GNT5*
GPIO1/REQ5*
GNT4*/GPIO48
C/BE0*
C/BE1*
DEVSEL*
PERR*
STOP*
PCIRST*
PME*
PLTRST*
TRDY*
FRAME*
IRDY*
PCICLK
PAR
PLOCK*
SERR*
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
C/BE2*
C/BE3*
GNT0*
REQ1*
GNT1*
REQ2*
GNT2*
REQ3*
GNT3*
PIRQA*
PIRQB*
PIRQC*
PIRQD*
RSVD0
RSVD1
RSVD2
RSVD3
MISC
INT I/F
PCI
(2 OF 6)
IO
OUT
OUT
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IN
IO
IO
IO
IO
OUT
IO
IO
IO
IO
IO
IO
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
BLUETOOTH
TRACKPAD (GEYSER)
CAMERA
IR
AND PWROK=H
NOTE: R2210 WAS PD ON PIN A14 = FWH_TBL_L
BOM NOTE FOR PD ON PCI_GNT3_L:
EXTERNAL 2
EXTERNAL 1
EXTERNAL 0
NOTE:
STUFF - A16 SWAP OVERRIDE
(STRAPPED TO TOP-BLOCK SWAP MODE
IE SB INVERTS A16 FOR ALL CYCLES
TARGETING FWH BIOS SPACE)
SB BOOT BIOS SELECT
GNT4#GNT5#
TO RSVD[1-9]
NOTE: CHANGE SYMBOL
R2210STRAP
11
10
01
STUFF
UNSTUFF
UNSTUFF UNSTUFF
STUFF
UNSTUFF
SPI
PCI
LPC (DEFAULT)
NOTE:
LAYOUT NOTE:
PLACE R2203 < 1/2 IN FROM SB
LAYOUT NOTE:
PLACE R2204 < 1/2 IN FROM SB
GNT4# HAS INT PU; ENABLED ONLY WHEN PCIRST#=0 AND PWROK=H
(INT PD)
(INT PD)
GNT5# HAS INT PU (NOMINAL=20K, SIMULATION=15K-35K)
NOTE: FWH_WP_L NOT USED
R2211
ENABLED ONLY WHEN PCIRST#=0
SB: 2 OF 4
(AKA TP3, INTERNAL 20K PU)
(INT 20K PU)
GNT[0-3]# HAVE INT 20K PU
NO STUFF - DEFAULT
NOTE: USBP[0-7]P/N HAVE INTERNAL 15K PD
1/16W
402
24.9
MF-LF
1%
R2203
1 2
10K
1/16W
MF-LF
5%
402
USB_G_OC_PU
R2222
1
2
402
22.6
1%
1/16W
MF-LF
R2204
1 2
1/16W
5%
10K
MF-LF
402
R2223
1
2
10K
5%
1/16W
MF-LF
402
R2225
1
2
402
MF-LF
1/16W
10K
5%
R2226
1
2
10K
5%
1/16W
MF-LF
402
R2299
1
2
OMIT
BGA
SB
ICH7-M
U2100
V26
V25
U28
U27
Y26
Y25
W28
W27
AB26
AB25
AA28
AA27
AD25
AD24
AC28
AC27
AE28
AE27
D25
C25
D3
C4
D5
D4
E5
C3
A2
B3
F26
H26
K26
M26
P26
T25
F25
H25
K25
M25
P25
T24
E28
G28
J28
L28
N28
R28
E27
G27
J27
L27
N27
R27
P1
R2
P6
P2
P5
F1
F2
G4
G3
H1
H2
J4
J3
K1
K2
L4
L5
M1
M2
N4
N3
D1
D2
SB
BGA
ICH7-M
OMIT
U2100
E18
C18
E14
D14
B12
C13
G15
G13
E12
C11
D11
A11
A16
A10
F11
F10
E9
D9
B9
A8
A6
C7
B6
F18
E6
D6
E16
A18
E17
A17
A15
C14
B15
C12
D12
C15
A12
F16
E7
D16
D17
F13
A14
C8
D8
G8
F7
F8
G7
A7
AH20
E10
A9
B18
C9
A3
B4
C5
B5
E11
C26
B19
D7
C16
C17
E13
A13
AE5
AD5
AG4
AH4
AD9
AE9
AG8
AH8
F21
B10
F15
F14
MF-LF
1/16W
5%
10K
402
R2200
1
2
402
MF-LF
1/16W
5%
10K
USB_C_OC_PU
R2250
1
2
10K
5%
1/16W
MF-LF
402
USB_E_OC_PU
R2251
1
2
USB_D_OC_PU
MF-LF
1/16W
5%
10K
402
R2255
1
2
MF-LF
402
1/16W
5%
10K
R2298
1
2
MF-LF
402
5%
10K
1/16W
R2205
1
2
402
10K
MF-LF
5%
1/16W
NOSTUFF
R2206
1
2
MF-LF
1/16W
10K
402
5%
R2207
1
2
VOLTAGE=0V
1/16W
MF-LF
5%
1K
402
R2211
1
2
051-7164
8722
06004
PCI_PME_FW_L
PP3V3_S0
SPI_SI
SPI_CE_L
SB_GPIO30
PCI_REQ2_L
BOOT_LPC_SPI_L
PCI_C_BE_L<2>
SPI_SCLK
PCI_STOP_L
PCI_REQ3_L
PCI_REQ1_L
PCI_REQ0_L
PCI_AD<1>
PCI_AD<6>
EXCARD_OC_L
SB_GPIO29
TP_SB_XOR_AE9
TP_SB_XOR_AG8
SB_CRT_TVOUT_MUX
TP_SB_XOR_AH8
TP_SB_XOR_AE5
TP_SB_XOR_AD9
TP_SB_XOR_AH4
TP_SB_XOR_AG4
TP_SB_XOR_AD5
INT_PIRQD_L
USB2_LT2_P
SPI_SO
SPI_ARB
LTUSB_OC_L
UNUSED_USB_D_OC_L
UNUSED_USB_B_OC_L
RTUSB_OC_L
LTUSB_OC_L
PP3V3_S5
PP1V5_S0_SB_VCC1_5_B
LT2USB_OC_L
TP_PCIE_F_R2DP
TP_PCIE_F_R2DN
TP_PCIE_F_D2RP
TP_PCIE_F_D2RN
TP_PCIE_E_R2DP
TP_PCIE_E_R2DN
TP_PCIE_E_D2RP
TP_PCIE_E_D2RN
TP_PCIE_D_R2DP
TP_PCIE_D_R2DN
TP_PCIE_D_D2RP
TP_PCIE_D_D2RN
PCIE_C_R2D_C_P
PCIE_C_R2D_C_N
PCIE_EXCARD_D2R_P
PCIE_EXCARD_D2R_N
PCIE_B_R2D_C_P
PCIE_B_R2D_C_N
PCIE_MINI_D2R_P
PCIE_MINI_D2R_N
PCIE_A_R2D_C_P
PCIE_A_R2D_C_N
PCIE_A_D2R_P
PCIE_A_D2R_N
DMI_N2S_P<1>
DMI_N2S_N<1>
DMI_S2N_N<1>
DMI_S2N_P<1>
DMI_N2S_N<2>
DMI_N2S_P<2>
SB_CLK100M_DMI_N
SB_GPIO29
SB_GPIO30
USB2_EXCARD_N
USB2_LT2_N
USB_BT_P
USB_BT_N
USB_HUB_P
USB_HUB_N
USB2_EXCARD_P
USB2_CAMERA_P
USB2_CAMERA_N
USB2_LT_P
USB2_LT_N
USB_TRACKPAD_P
USB_TRACKPAD_N
USB2_RT_P
USB2_RT_N
DMI_N2S_P<3>
DMI_S2N_N<3>
DMI_S2N_P<3>
DMI_N2S_N<3>
DMI_S2N_P<2>
DMI_S2N_N<2>
DMI_S2N_P<0>
DMI_S2N_N<0>
DMI_N2S_P<0>
DMI_N2S_N<0>
USB_RBIAS_PN
SB_CLK100M_DMI_P
DMI_IRCOMP_R
INT_PIRQC_L
INT_PIRQB_L
INT_PIRQA_L
PCI_C_BE_L<3>
PCI_AD<31>
PCI_AD<30>
PCI_AD<29>
PCI_AD<28>
PCI_AD<27>
PCI_AD<26>
PCI_AD<25>
PCI_AD<24>
PCI_AD<23>
PCI_AD<22>
PCI_AD<21>
PCI_AD<20>
PCI_AD<19>
PCI_AD<18>
PCI_AD<17>
PCI_AD<16>
PCI_AD<15>
PCI_AD<14>
PCI_AD<13>
PCI_AD<12>
PCI_AD<11>
PCI_AD<10>
PCI_AD<9>
PCI_AD<8>
PCI_AD<7>
PCI_AD<5>
PCI_AD<4>
PCI_AD<3>
PCI_AD<2>
PCI_AD<0>
PCI_SERR_L
PCI_LOCK_L
PCI_PAR
PCI_CLK_SB
PCI_IRDY_L
PCI_FRAME_L
PCI_TRDY_L
PLT_RST_L
TP_PCI_PME_L
PCI_RST_L
PCI_PERR_L
PCI_DEVSEL_L
PCI_C_BE_L<1>
PCI_C_BE_L<0>
SB_GPIO2
SB_GPIO3
SB_DVI_HPD
ODD_PWR_EN_L
TP_SB_RSVD9
NB_SB_SYNC_L
RTUSB_OC_L
EXCARD_OC_L
UNUSED_USB_B_OC_L
UNUSED_USB_D_OC_L
PP3V3_S5
TP_PCI_GNT1_L
TP_PCI_GNT0_L
TP_PCI_GNT2_L
PCI_GNT3_L
TP_PCI_GNT4_L
LT2USB_OC_L
82D5
82C6 82B3 82A4 79D3 79A8 71D2 67C5 67C3 67B3 67A3
66B6 66B5 66B1 65D6 65B3 62A6 61D8 61A5 60D4 60C7
58C7 58C4 57B6 54D4 54B5 52D3 49C7 49C4 49B5 40B6
36D6 34A8 33D8 33D3 33C7 29A6 29A3 28A6 27D8 27D5
27D3 27C3 26D1 26B8 26B6 26B4
79D5
79D5
25D8
67D5
67D5
25D3
67D3
67D3
25C6
67C3
67C3
25C4
66C5
66C5
25B8
65D8
65D8
25B4
65D2
65D2
25A4
65D1
65D1
24D3
65C8
65C8
24C3
63D8
63D8
24B5
56D4
56D4
24B3
26C5
26C5
23D5
25D2
25D2
23B3
25C8
25C8
21D3
25B6
25B6
21C3
24C3
24C3
20B4
24B3
82A4
24B3
20A4
24A5
79A8
24A5
19C7
23D8
26C3
23D8
19C6
23D4
26C1
23D4
17C6
52B3
23D1
26B1
52B3
23D1
14D6
48C3
48C3
47C5
48C3
23B7
48C3
50C6
50B6
50C6
50C6
26A4
47C5
48C3
23B7
48C3
14C7
22C4
22C4
22C4
22D8
23A7
22D8
50C5
50B5
50C5
50C5
81C4
81C4
47B5
47B5
14B7
22D8
22D8
23A7
22C4
10C5
53B4
6C3
6D3
22C4
22C4
6D3
6D3
22D8
6C3
50C3
50B3
50C3
50C3
34C5
6D3
6D3
6D3
6D3
34C5
6C7
6D3
6C3
22D8
22D8
22C6
6C3
5D4
56C1
56C7
22C4
51C7
56C7
37C3
6C1
37D3
56C1
6D1
6C3
6D3
6D2
6D1
11B5
25B6
6C1
50B6
50B6
50B6
50A6
50B6
50B6
50B6
50B6
50B6
50B6
50B6
50B6
48B6
48B6
48C6
48C6
14B4
14B4
34C3
22D8
6D2
6D2
6D2
6D2
14B4
14B4
34C3
37C6
37C3
37D3
37D3
37C3
6C6
37C2
37D3
37D3
6D2
6C1
6D3
6C3
11B5
6C1
37D3
5A4
51D5
51B5
6D5
26D2
5C2
37B6
51D5
26D2
26D2
26D2
37D6
37D6
5C1
22C4
26D2
51D5
51D5
5C1
6C1
6D1
6D1
5C1
5D4
24D5
5C1
50B3
50B3
50B3
50A3
50B3
50B3
50B3
50B3
50B3
50B3
50B3
50B3
50C3
50C3
5B1
5B1
50C3
50C3
5B1
5B1
39C5
39C5
39D5
39D5
5A7
5A7
14B4
14B4
14B4
14B4
33B4
22D8
6D5
6D1
6D1
6D1
6D1
14B4
14B4
14B4
14B4
14B4
14B4
14B4
14B4
5A7
5A7
33B4
26D2
26D2
26D2
37B6
37C6
37C6
37C6
37C6
37C6
37C6
37C6
37C6
37C6
37C6
37C6
37C6
6C5
37C6
37C6
37C6
37C6
37C6
37C6
37C6
37C6
37C6
37C6
37C6
37D6
37D6
37D6
37D6
37D6
37D6
26D2
26D2
37B6
34D6
26D2
26D2
26D2
5C4
5B4
26D2
26D2
37B6
37C6
26D2
26C2
80A1
36C7
6D1
5C1
6D1
6C1
5D4
5C1
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
IN
IN
IO
IO
OUT
OUT
OUT
IN
IN
IO
IN
IN
IO
IN
IN
IN
IN
IO
IO
IN
OUT
IN
OUT
IN
OUT
GPIO19/SATA1GP
GPIO21/SATA0GP
GPIO36/SATA2GP
CLK48
GPIO37/SATA3GP
CLK14
SUSCLK
SLP_S3*
SLP_S4*
SLP_S5*
PWROK
TP0/BATLOW*
GPIO16/DPRSLPVR
PWRBTN*
LAN_RST*
RSMRST*
GPIO10
GPIO9
GPIO12
GPIO14
GPIO13
GPIO24
GPIO15
GPIO25
GPIO35
GPIO38
GPIO39
SMBCLK
SMBDATA
LINKALERT*
SMLINK1
SMLINK0
RI*
SYS_RST*
SPKR
SUS_STAT*
GPIO0/BM_BUSY*
GPIO18/STPPCI*
GPIO11/SMBALERT*
GPIO20/STPCPU*
GPIO26
GPIO28
GPIO27
GPIO32/CLKRUN*
GPIO33/AZ_DOCK_EN*
WAKE*
GPIO34/AZ_DOCK_RST*
SERIRQ
THRM*
GPIO7
GPIO6
VRMPWRGD
GPIO8
(4 OF 6)
SMB
GPIO
PWR MNGT
SYS GPIO
CLKS
SATA GPIO
IN
IN
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
(INT 20K PU)
PLACE R2306-14 WHERE PHYSICALLY ACCESSIBLE
NOTE FOR R2323 (DEF=NOSTUFF)
SB WILL DISABLE TCO TIMER
STRAPPING @ PWROK RISING:
SYSTEM REBOOT FEATURE
NOT USED
NOTE: RESERVED FOR FUTURE
LAYOUT NOTE:
NOTE FOR GPIO25:
OD
DEF=GPI
IN RESET STATE TO SAVE PWR
SMC WILL DRIVE 0-1-0 TO KEEP LAN INT’F
NOTE:
NOTE:
SV_SET_UP IS LINDACARD DETECT
LO = NOT PRESENT
HI = PRESENT
(INT WEAK PD)
NOTE: DPRSLPVR HAS INT 20K PD, ENABLED AT BOOT/RESET FOR STRAPPING FCN
DEF=GPI
- CAN NOT BE LOW FOR 35US AFTER RSMRST# ON BOOT (DMI AC COUPLING MODE STRAP)
- HAS INTERNAL 20K PU, ENABLED DURING RSMRST# AND DISABLED WITHIN 100MS AFTER RSMRST# DEASSERTS
DEF=GPI
100
R2302
1 2
100
R2303
1 2
100
R2305
1 2
NOSTUFF
402
5%
MF-LF
1/16W
10K
R2306
1
2
10K
402
5%
MF-LF
1/16W
R2307
1
2
402
1/16W
MF-LF
5%
10K
R2308
1
2
5%
MF-LF
1/16W
0
402
NOSTUFF
R2309
1
2
402
5%
MF-LF
1/16W
10K
R2310
1
2
1/16W
MF-LF
5%
NOSTUFF
402
10K
R2311
1
2
10K
1/16W
MF-LF
5%
402
R2313
1
2
402
NOSTUFF
0
1/16W
MF-LF
5%
R2314
1
2
402
10K
1/16W
MF-LF
5%
R2316
1
2
MF-LF
402
10K
1/16W
5%
R2317
1
2
10K
402
1/16W
MF-LF
5%
R2318
1
2
10K
1/16W
MF-LF
5%
402
R2319
1
2
402
5%
MF-LF
1/16W
10K
R2320
1
2
1/16W
5%
10K
SM-LF
RP2300
1 2 3 4
8 7 6 5
5%
402
MF-LF
1/16W
100K
R2399
1 2
1/16W
MF-LF
5%
402
1K
R2398
1
2
5%
MF-LF
8.2K
402
1/16W
R2397
1
2
MF-LF
5%
1/16W
10K
402
R2396
1
2
8.2K
1/16W
MF-LF
402
5%
R2395
1
2
OMIT
BGA
SB
ICH7-M
U2100
AC1
B2
AB18
A20
B23
F19
E19
R4
E22
AC22
AC20
AH18
AF21
AF19
R3
D20
A21
B21
E23
AG18
AC19
U2
AD21
AH19
AE19
AD20
AE20
AC21
AC18
E21
E20
C19
A26
C23
AA4
A28
Y4
AH21
B24
D23
F22
C22
B22
B25
A25
A19
A27
C20
A22
AF20
C21
AD22
F20
402
1/16W
MF-LF
5%
10K
R2388
1
2
MF-LF
402
5%
1K
1/16W
NO_REBOOT_MODE
R2323
1
2
NOSTUFF
10K
1/16W
MF-LF
402
5%
R2326
1
2
NOSTUFF
5%
MF-LF
1/16W
402
10K
R2327
1
2
5%
402
8.2K
1/16W
MF-LF
R2343
1
2
SB: 3 OF 4
SYNC_DATE=08/08/2006
SYNC_MASTER=M57_MLB_MG
051-7164
8723
06004
INT_SERIRQ
PP3V3_S0
SATA_C_PWR_EN_L
PM_DPRSLPVR
PM_BATLOW_L
SB_CLK48M_USBCTLR
SV_SET_UP
SMBUS_SB_SCL
SATA_C_DET_L
SB_GPIO19
SB_GPIO21
SB_GPIO37
SB_CLK14P3M_TIMER
TP_SB_SUS_CLK
PM_SLP_S3_L
PM_SLP_S4_L
PM_SLP_S5_L
PM_SB_PWROK
PM_SYSRST_L
PM_SUS_STAT_L
BIOS_REC
VR_PWRGD_CK410
PP3V3_S5
PP3V3_S5
TP_SB_GPIO6
CRB_SV_DET
PP3V3_S5
FWH_MFG_MODE
BIOS_REC
PP3V3_S0
SATA_C_PWR_EN_L
PM_BMBUSY_L
SB_SPKR
SMBUS_SB_SDA
PP3V3_S5
SMC_RUNTIME_SCI_L
PM_RSMRST_L
PM_LAN_ENABLE
PM_PWRBTN_L
PCIE_WAKE_L
FWH_MFG_MODE
PM_STPPCI_L
SMB_ALERT_L
PM_THRM_L
SMC_EXTSMI_L
PM_CLKRUN_L
PM_STPCPU_L
TP_AZ_DOCK_RST_L
GPU_D3COLD_RESET_L
PP3V3_S5
SMS_INT_L
IDE_RESET_L
SV_SET_UP
CRB_SV_DET
TP_SB_GPIO25_DO_NOT_USE
SB_CLK100M_SATA_OE_L
SB_GPUVCORE_DISABLE_L
SB_GPIO26
SMC_WAKE_SCI_L
LAN_ENERGY_DET
SMC_SB_NMI
SMLINK<1>
SMLINK<0>
SMB_LINK_ALERT_L
PM_RI_L
82D5
82D5
82C6
82C6
82B3
82B3
82A4
82A4
79D3
79D3
79A8
79A8
71D2
71D2
67C5
67C5
67C3
67C3
67B3
67B3
67A3
67A3
66B6
66B6
66B5
66B5
66B1
66B1
65D6
65D6
65B3
65B3
62A6
62A6
61D8
61D8
61A5
61A5
60D4
60D4
60C7
60C7
58C7
58C7
58C4
58C4
57B6
57B6
54D4
54D4
54B5
54B5
52D3
52D3
49C7
49C7
49C4
49C4
49B5
49B5
40B6
40B6
36D6
36D6
34A8
34A8
33D8
33D8
33D3
33D3
33C7
33C7
29A6
29A6
29A3
29A3
28A6
28A6
27D8
27D8
27D5
27D5
27D3
27D3
27C3
27C3
26D1
26D1
26B8
26B8
26B6
26B6
26B4
79D5
79D5
79D5
26B4
79D5
79D5
25D8
67D5
67D5
67D5
25D8
67D5
67D5
25D3
67D3
67D3
67D3
25D3
67D3
67D3
25C6
67C3
67C3
67C3
25C6
67C3
67C3
25C4
66C5
66C5
66C5
25C4
66C5
66C5
25B8
65D8
65D8
65D8
25B8
65D8
65D8
25B4
65D2
65D2
65D2
25B4
65D2
65D2
25A4
65D1
65D1
65D1
25A4
65D1
65D1
24D3
65C8
65C8
65C8
24D3
65C8
65C8
24C3
63D8
63D8
63D8
24C3
63D8
63D8
24B5
56D4
56D4
56D4
24B5
56D4
56D4
24B3
26C5
26C5
26C5
24B3
26C5
26C5
23B3
25D2
25D2
25D2
23D5
25D2
25D2
22B5
25C8
25C8
25C8
22B5
25C8
25C8
21D3
81C3
25B6
25B6
25B6
21D3
81C3
25B6
25B6
21C3
48B3
66C8
24C3
24C3
24C3
21C3
48B3
24C3
24C3
20B4
46B6
66C6
24B3
24B3
24B3
20B4
46B6
24B3
24B3
20A4
33B6
66B6
24A5
24A5
24A5
20A4
33B6
24A5
24A5
19C7
29A6
65B8
23D8
23D8
23D8
19C7
29A6
23D8
23D4
19C6
28A6
55C3
23D4
23D4
23D4
19C6
28A6
23D1
23D1
17C6
27D8
51C5
23D1
23B7
23D1
17C6
27D8
23B7
23B7
14D6
27D7
43C8
60C6
23A7
23A7
23B7
14D6
27D7
23A7
23A7
60C6
14C7
87C6
27D6
42A8
53B5
22D8
22D8
22D8
14C7
27D6
22D8
60C6
22D8
53C5
10C5
61C8
53B5
27C6
6C7
39C8
52A2
51B7
52A2
22C6
22C6
22C6
10C5
27C6
22C6
48C3
53C4
22C6
53B5
51C7
5D4
14B7
23C3
27B6
6C6
32B3
51C5
26A6
26C5
51C5
26B8
11B5
11B5
11B5
5D4
27B6
11B5
51D7
51D7
39C6
33C4
51C5
33C4
11B5
52B2
23B6
66B7
5C2
5A4
23A3
5B4
51B7
34C7
5C2
5B1
36B5
34A6
5B4
5C4
5C4
5B4
5A2
5C2
23A6
5A4
5D4
5D4
23C3
5D4
23C5
23C5
5A4
23B3
14B6
5B1
5D4
51B7
5B4
5B4
51D7
5B1
23A6
5B4
51B7
51B7
5C2
5B4
26A4
5D4
51B5
36D5
5C2
23B6
33B4
66B6
51D5
40A3
51D7
(6 OF 6)
VSS
V5REF_SUS
VCC3_3
VCCDMIPLL
VCCSATAPLL
VCC3_3
VCCRTC
VCCUSBPLL
VCCSAUS1_5
VCC PAUX
USB CORE
VCC1_5_A
ARX
USB
PCI
IDE
VCCA3GP
CORE
ATX
VCC1_5_A
VCC3_3
VCC3_3
VCCSUS3_3
VCC1_5_A
VCCSUS3_3
VCCSUS3_3
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCCLAN1_5
V_CPU_IO
VCC3_3/VCCHDA
VCCSUS3_3/VCCSUSHDA
VCCLAN_3_3
VCC1_05
V5REF
VCC1_5_B
(5 OF 6)
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
NOTE FOR VCCLAN_3_3:
S3 IF INTERNAL LAN IS USED
S0 OR S3 IF NOT
CHANGE SYMBOL TO 1.05
CHANGE SYMBOL TO 1.05
SO NO CONNECT HERE
VOLTAGE GENERATED INTERNALLY
SO NO CONNECT HERE
VOLTAGE GENERATED INTERNALLY
NOTE:
VCCHDA AND VCCSUSHDA CAN BE 1.5V OR 3.3V
DEPENDING ON VIO OF AZALIA INTERFACE
CODEC IC’S CONSIDERED SO FAR ARE 3.3V
0 0
OMIT
BGA
ICH7-M
SB
U2100
A4
A23
B1
B8
B11
B14
B17
B20
B26
B28
C2
C6
C27
D10
D13
D18
D21
D24
E1
E2
E4
E8
E15
F3
F4
F5
F12
F27
F28
G1
G2
G5
G6
G9
G14
G18
G21
G24
G25
G26
H3
H4
H5
H24
H27
H28
J1
J2
J5
J24
J25
J26
K24
K27
K28
L13
L15
L24
L25
L26
M3
M4
M5
M12
M13
M14
M15
M16
M17
M24
M27
M28
N1
N2
N5
N6
N11
N12
N13
N14
N15
N16
AE24
AE25
AF2
AF4
AF8
AF11
AF27
AF28
N17
AG1
AG3
AG7
AG11
AG14
AG17
AG20
AG25
AH1
AH3
N18
AH7
AH12
AH23
AH27
N24
N25
N26
P3
P4
P12
P13
P14
P15
P16
P17
P24
P27
P28
R1
R11
R12
R13
R14
R15
R16
R17
R18
T6
T12
T13
T14
T15
T16
T17
U4
U12
U13
U14
U15
U16
U17
U24
U25
U26
V2
V13
V15
V24
V27
V28
W6
W24
W25
W26
Y3
Y24
Y27
Y28
AA1
AA24
AA25
AA26
AB4
AB6
AB11
AB14
AB16
AB19
AB21
AB24
AB27
AB28
AC2
AC5
AC9
AC11
AD1
AD3
AD4
AD7
AD8
AD11
AD15
AD19
AD23
AE2
AE4
AE8
AE11
AE13
AE18
AE21
OMIT
BGA
SB
ICH7-M
U2100
G10
AD17
F6
AE23
AE26
AH26
L11
P18
T11
T18
U11
U18
V11
V12
V14
V16
V17
L12
V18
L14
L16
L17
L18
M11
M18
P11
AB7
AC6
AB9
AC10
AD10
AE10
AF10
AF9
AG9
AH9
AB17
AC17
AC7
T7
F17
G17
AB8
AC8
A1
H6
H7
J6
J7
AD6
AE6
AF5
AF6
AG5
AH5
AB10
AA22
AA23
AD28
D26
D27
D28
E24
E25
E26
F23
F24
G22
AB22
G23
H22
H23
J22
J23
K22
K23
L22
L23
M22
AB23
M23
N22
N23
P22
P23
R22
R23
R24
R25
R26
AC23
T22
T23
T26
T27
T28
U22
U23
V22
V23
W22
AC24
W23
Y22
Y23
AC25
AC26
AD26
AD27
U6
B27
AH11
AG19
A5
B13
B16
B7
C10
D15
F9
G11
G12
AA7
G16
AB12
AB20
AC16
AD13
AD18
AG12
AG15
AG28
AA2
Y7
V5
V1
W2
W7
W5
AD2
K7
C28
G20
R7
P7
A24
L1
L2
L3
L6
L7
M6
M7
N7
E3
C24
D19
D22
G19
K3
K4
K5
K6
C1
SYNC_DATE=09/15/2006
SYNC_MASTER=M59_MLB
SB: 4 OF 4
06004
24 87
051-7164
PP1V5_S0_SB_VCC1_5_B
PP5V_S0_SB_V5REF
PP5V_S5_SB_V5REF_SUS
PP1V05_S0
PP3V3_S0
PP3V3_S0
PP3V3_S5
PP1V05_S0
PP3V3_S0
PP1V5_S0_SB_VCCDMIPLL
PP1V5_S0
PP1V5_S0
PP3V3_S0
PP1V5_S0
PP3V3_S5
PP3V3_S0
PP3V3_S0
PP3V3_G3C_SB_RTC_D
PP3V3_S5
PP3V3_S5
PP1V5_S0
PP1V5_S0
PP1V5_S0
82D5
82D5
82D5
82D5
82D5
82C6
82C6
82C6
82C6
82D5
82C6
82B3
82B3
82B3
82B3
82C6
82B3
82A4
82A4
82A4
82A4
82B3
82A4
79D3
79D3
79D3
79D3
82A4
79D3
79A8
79A8
79A8
79A8
79D3
79A8
71D2
71D2
71D2
71D2
79A8
71D2
67C5
67C5
67C5
67C5
71D2
67C5
67C3
67C3
67C3
67C3
67C5
67C3
67B3
67B3
67B3
67B3
67C3
67B3
67A3
67A3
67A3
67A3
67B3
67A3
66B6
66B6
66B6
66B6
67A3
66B6
66B5
66B5
66B5
66B5
66B6
66B5
66B1
66B1
66B1
66B1
66B5
66B1
65D6
65D6
65D6
65D6
66B1
65D6
65B3
65B3
65B3
65B3
65D6
65B3
62A6
62A6
62A6
62A6
65B3
62A6
61D8
61D8
61D8
61D8
62A6
61D8
61A5
61A5
61A5
61A5
61D8
61A5
60D4
60D4
60D4
60D4
61A5
60D4
60C7
60C7
60C7
60C7
60D4
60C7
58C7
58C7
58C7
58C7
60C7
58C7
58C4
58C4
58C4
58C4
58C7
58C4
57B6
57B6
57B6
57B6
58C4
57B6
54D4
54D4
54D4
54D4
57B6
54D4
54B5
54B5
54B5
54B5
54D4
54B5
52D3
52D3
52D3
52D3
54B5
52D3
49C7
49C7
49C7
49C7
52D3
49C7
49C4
49C4
49C4
49C4
49C7
49C4
49B5
49B5
49B5
49B5
49C4
49B5
40B6
40B6
40B6
40B6
49B5
40B6
36D6
36D6
36D6
36D6
40B6
36D6
34A8
34A8
34A8
34A8
36D6
34A8
33D8
33D8
33D8
33D8
34A8
33D8
33D3
33D3
33D3
33D3
33D8
33D3
33C7
33C7
33C7
33C7
33D3
33C7
29A6
29A6
29A6
29A6
33C7
29A6
29A3
29A3
29A3
29A3
29A6
29A3
28A6
28A6
28A6
28A6
29A3
67D8
28A6
27D8
67D8
27D8
27D8
27D8
28A6
67D6
27D8
27D5
67D6
27D5
27D5
27D5
27D8
65A2
27D5
27D3
65A2
27D3
27D3
27D3
27D5
55A4
27D3
27C3
55A4
27C3
27C3
27C3
27D3
34C8
27C3
26D1
34C8
26D1
26D1
26D1
27C3
34C6
26D1
26B8
34C6
26B8
26B8
26B8
26D1
34B8
26B8
26B6
34B8
26B6
26B6
26B6
26B8
25D3
26B6
26B4
25D3
26B4
26B4
26B4
26B6
79D5
79D5
25C4
26B4
25D8
25C4
25D8
25D8
79D5
25D8
26B4
67D5
67D5
24C3
25D8
25D3
24D3
25D3
25D3
67D5
25D3
25D8
67D3
67D3
21C1
25D3
25C6
21C1
25C6
25C6
67D3
25C6
25D3
67C3
67C3
19D7
25C6
25C4
19D7
25C4
25C4
67C3
25C4
25C6
66C5
66C5
19D6
25C4
25B8
19D6
25B8
25B8
66C5
25B8
25C4
65D8
65D8
19D5
25B8
25B4
19D5
25B4
25B4
65D8
25B4
25B8
65D2
65D2
19D2
25B4
25A4
19D2
25A4
67C8
67C8
25A4
65D2
25A4
25B4
65D1
65D1
67C8
67C8
67C8
19D1
25A4
24D3
19D1
24D3
67C6
67C6
24D3
65D1
24D3
25A4
65C8
65C8
67C6
67C6
67C6
19C8
24C3
24C3
19C8
24C3
66C5
66C5
24C3
65C8
24C3
24D3
63D8
63D8
66C5
66C5
66C5
17D6
24B5
24B5
17D6
24B5
62C1
62C1
24B5
63D8
24B5
24C3
56D4
56D4
62C1
62C1
62C1
17D3
24B3
24B3
17D3
24B3
62A8
62A8
24B3
56D4
24B3
24B5
26C5
26C5
62A8
62A8
62A8
16D3
23D5
23D5
16D3
23D5
48B6
48B6
23D5
26C5
23D5
23D5
25D2
25D2
48B6
48B6
48B6
16C8
23B3
23B3
16C8
23B3
25D6
25D6
23B3
25D2
23B3
23B3
25C8
25C8
25D6
25D6
25D6
13B5
22B5
22B5
13B5
22B5
25C8
25C8
22B5
25C8
22B5
22B5
25B6
25B6
25C8
25C8
25C8
12C2
21D3
21D3
12C2
21D3
25C6
25C6
21D3
25B6
21D3
21D3
24C3
24C3
25C6
25C6
25C6
12B7
21C3
21C3
12B7
21C3
25C2
25C2
21C3
24C3
21C3
21C3
24B3
24B3
25C2
25C2
25C2
12A7
20B4
20B4
12A7
20B4
25B6
25B6
20B4
24B3
20B4
20B4
24A5
24A5
25B6
25B6
25B6
11C5
20A4
20A4
11C5
20A4
25B2
25B2
20A4
23D8
20A4
20A4
23D8
23D8
25B2
25B2
25B2
11B3
19C7
19C7
11B3
19C7
25A8
25A8
19C7
23D4
19C7
19C7
23D4
23D4
25A8
25A8
25A8
9B7
19C6
19C6
9B7
19C6
24B5
24B5
19C6
23D1
19C6
19C6
23D1
23D1
24B5
24B5
24B5
8C7
17C6
17C6
8C7
17C6
24A5
24A5
17C6
23B7
17C6
17C6
23B7
23B7
24A5
24A5
24A5
7D5
14D6
14D6
7D5
14D6
24A3
24A3
14D6
23A7
14D6
14D6
23A7
23A7
24A3
24A3
24A3
7B6
14C7
14C7
7B6
14C7
9B7
9B7
14C7
22D8
14C7
14C7
26D4
22D8
22D8
9B7
9B7
9B7
7B5
10C5
10C5
7B5
10C5
8B7
8B7
10C5
22C6
10C5
10C5
26D3
22C6
22C6
8B7
8B7
8B7
25B6
5D4
5D4
5D4
5D4
5D4
5D4
5D4
5D4
11B5
5D4
5D4
25A4
11B5
11B5
5D4
5D4
5D4
22C1
25D7
25C7
5B2
5A4
5A4
5B2
5A4
5D1
5D1
5A4
5D4
5A4
5A4
21D6
5D4
5D4
5D1
5D1
5D1
NC NC
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
SECONDARY SIDE OR 3.56MM ON PRIMARY
ICH VCCDMIPLL BYPASS
PLACE C2520 NEAR PIN E3 OF SB
PLACEMENT NOTE:
PLACE C2503 < 2.54MM OF PIN AD17 OF SB
ON SECONDARY SIDE OR 3.56MM ON PRIMARY
ON SECONDARY SIDE OR 3.56MM ON PRIMARY
PLACE C2504 < 2.54MM OF PIN F6 OF SB
PLACEMENT NOTE:
(ICH REFERENCE FOR 5V TOLERANCE ON RESUME WELL LOGIC)
ICH V5REF_SUS BYPASS
(ICH SUSPEND 3.3V PWR)
ICH VCCSUS3_3 BYPASS
(ICH LOGIC&IO[ATX] 1.5V PWR)
(ICH LOGIC&IO[ARX] 1.5V PWR)
ICH VCC1_5_A/ARX BYPASS
ICH VCC3_3 BYPASS
PLACE C2509 NEAR PIN B27 OF SB
PLACEMENT NOTE:
ICH VCC3_3 BYPASS
(ICH RTC 3.3V PWR)
ICH VCCRTC BYPASS
V5, W2, OR W7
3.56MM ON PRIMARY NEAR PINS AA7 ... AG19
3.56MM ON PRIMARY NEAR PIN AD2
ICH VCC_PAUX/VCCLAN3_3 BYPASS
(ICH LAN I/F BUFFER 3.3V PWR)
PLACEMENT NOTE:
PLACE CAPS NEAR PINS
AB8 AND AC8 OF SB
ICH USB/VCCSUS3_3 BYPASS
(ICH SUSPEND USB 3.3V PWR)
PLACE CAPS NEAR PINS
K3 ... N7 OF SB
PLACE C2520 NEAR PIN C1 OF SB
NEAR PINS D28, T28, AD28
PLACEMENT NOTE:
ICH VCC1_5_A/ATX BYPASS
(ICH IO BUFFER 3.3V PWR)
(ICH REFERENCE FOR 5V TOLERANCE ON CORE WELL INPUT)
ICH VCCSATAPLL BYPASS
(ICH SATA PLL 1.5V PWR)
PLACE < 2.54MM OF SB ON SECONDARY OR
ICH V_CPU_IO BYPASS
(ICH CPU I/O 1.05V PWR)
ICH IDE/VCC3_3 BYPASS
PLACE < 2.54MM OF SB ON SECONDARY OR
(ICH PCI I/O 3.3V PWR)
A24 ... G19 AND P7 OF SB
DISTRIBUTE IN PCI SECTION OF SB
NEAR PINS A5 ... G16
(ICH IO BUFFER 3.3V PWR)
3.56MM ON PRIMARY NEAR PIN AG9
3.56MM ON PRIMARY NEAR PIN AG5
PLACEMENT NOTE:
PLACEHOLDER
FOR 270UF
PLACE CAPS NEAR PINS
PLACEMENT NOTE:
PLACE CAPS NEAR PIN W5 OF SB
PLACEMENT NOTE:
PLACEMENT NOTE:
SB: 4 OF 4
PLACE < 2.54MM OF SB ON SECONDARY OR
ICH V5REF BYPASS
PLACEMENT NOTE:
ICH CORE/VCC1_05 BYPASS
(ICH CORE 1.05V PWR)
PLACEMENT NOTE:
PLACE CAP UNDER SB NEAR PINS V1,
3.56MM ON PRIMARY NEAR PIN U6
PLACEMENT NOTE:
PLACEMENT NOTE:
PLACEMENT NOTE:
(ICH SUSPEND 3.3V PWR)
ICH VCCSUS3_3 BYPASS
PLACEMENT NOTE:
PLACEMENT NOTE:
ICH VCC1_5A BYPASS
(ICH LOGIC&IO 1.5V PWR)
(ICH USB CORE 1.5V PWR)
3.56MM ON PRIMARY NEAR PINS A1 ... J7
PLACE < 2.54MM OF SB ON SECONDARY OR
ICH USB CORE/VCC1_5_A BYPASS
PLACEMENT NOTE:
PLACEMENT NOTE:
PLACEMENT NOTE:
3.56MM ON PRIMARY NEAR PIN AH11
PLACE < 2.54MM OF SB ON SECONDARY OR
PLACEMENT NOTE:
PLACE < 2.54MM OF SB ON SECONDARY OR
PLACEMENT NOTE:
(ICH IDE I/O 3.3V PWR)
ICH PCI/VCC3_3 BYPASS
(ICH DMI PLL 1.5V PWR)
(ICH USB PLL 1.5V PWR)
ICH VCCUSBPLL BYPASS
ON SECONDARY SIDE OR 3.56MM ON PRIMARY
PLACE C2500 & C2505-07 < 2.54MM OF SB
PLACE NEAR PINS AE23, AE26 & AH26 OF SB
(ICH INTEL HDA CORE 3.3V PWR)
ICH VCC3_3/VCCHDA BYPASS
PLACE CAPS AT EDGE OF SB
PLACEMENT NOTE:
PLACE < 2.54MM OF SB ON SECONDARY OR
PLACE < 2.54MM OF SB ON
ICH VCCA3GP(VCC1_5_B BYPASS
(ICH IO,LOGIC 1.5V PWR)
X5R
16V
10%
0.1UF
402
C2510
1
2
0
402
0.1UF
10%
16V
X5R
C2512
1
2
0
1
5%
1/10W
MF-LF
603
R2500
1 2
4.7UF
20%
6.3V
CERM
603
C2524
1
2
0.1UF
10%
16V
X5R
402
C2522
1
2
BAT54DW
SOT-363
D2502
1
6
5
BAT54DW
SOT-363
D2502
4
3
2
1206
0.28-OHM
L2507
1 2
CASE-B2
2.5V
POLY
220UF
20%
C2500
1
2
0.1UF
402
10%
16V
X5R
C2503
1
2
0
X5R
16V
10%
0.1UF
402
C2504
1
2
0
5%
MF-LF
1/16W
402
10
R2501
1 2
100-OHM-EMI
SM-3
L2500
1 2
0
0.1UF
10%
16V
X5R
402
C2505
1
2
X5R
16V
10%
0.1UF
402
C2506
1
2
0.1UF
16V
10%
X5R
402
C2507
1
2
0.01UF
10%
16V
CERM
402
C2501
1
2
603
10UF
20%
6.3V
X5R
C2508
1
2
0
10%
16V
X5R
402
0.1UF
C2509
1
2
0
X5R
402
16V
10%
0.1UF
C2511
1
2
0
0.1UF
402
X5R
16V
10%
C2517
1
2
0
0.1UF
10%
16V
X5R
402
C2513
1
2
0
0
402
6.3V
CERM
10%
1UF
C2514
1
2
0
0.1UF
10%
16V
X5R
402
C2520
1
2
402
X5R
16V
10%
0.1UF
C2515
1
2
0
0
CASE-C2
POLY
20%
2.5V
330UF
C2516
1
2
5%
1/16W
402
MF-LF
100
R2502
1
2
1UF
10%
6.3V
CERM
402
C2502
1
2
402
0.1UF
10%
16V
X5R
C2518
1
2
0
X5R
16V
10%
0.1UF
402
C2519
1
2
0
0.1UF
10%
16V
402
X5R
C2521
1
2
0
X5R
16V
10%
0.1UF
402
C2523
1
2
0
0.1UF
X5R
16V
10%
402
C2525
1
2
0
X5R
16V
10%
0.1UF
402
C2526
1
2
X5R
16V
10%
0.1UF
402
C2527
1
2
X5R
16V
10%
0.1UF
402
C2528
1
2
402
0.1UF
10%
16V
X5R
C2529
1
2
0
402
0.1UF
10%
16V
X5R
C2530
1
2
402
0.1UF
10%
16V
X5R
C2534
1
2
0
402
0.1UF
10%
16V
X5R
C2531
1
2
402
0.1UF
10%
16V
X5R
C2532
1
2
0
402
0.1UF
10%
16V
X5R
C2533
1
2
051-7164
8725
06004
PP1V5_S0
PP1V5_S0
PP1V05_S0
PP3V3_S0
PP1V05_S0
PP1V5_S0
MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.5MM
VOLTAGE=1.5V
PP1V5_S0_SB_VCCDMIPLL
PP1V5_S0_SB_VCCDMIPLL_F
VOLTAGE=1.5V
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM
PP3V3_S0
PP1V5_S0
PP3V3_S5
PP1V5_S0
PP3V3_S5
PP3V3_S0
PP1V5_S0
PP3V3_S0
PP3V3_S0
PP1V5_S0
PP3V3_S5
PP1V5_S0
PP3V3_S0
PP3V3_G3C_SB_RTC_D
PP5V_S5
PP3V3_S0
PP3V3_S5
PP5V_S0
PP5V_S5_SB_V5REF_SUS
MIN_NECK_WIDTH=0.25MM
VOLTAGE=5V
MIN_LINE_WIDTH=0.3MM
PP5V_S0_SB_V5REF
VOLTAGE=5V
MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.25MM
VOLTAGE=1.5V
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM
PP1V5_S0_SB_VCC1_5_B
82D5
82D5
82D5
82D5
82D5
82D5
82D5
82C6
82C6
82C6
82C6
82C6
82C6
82C6
82B3
82B3
82B3
82B3
82B3
82B3
82B3
82A4
82A4
82A4
82A4
82A4
82A4
82A4
79D3
79D3
79D3
79D3
79D3
79D3
79D3
79A8
79A8
79A8
79A8
79A8
79A8
79A8
71D2
71D2
71D2
71D2
71D2
71D2
71D2
67C5
67C5
67C5
67C5
67C5
67C5
67C5
67C3
67C3
67C3
67C3
67C3
67C3
67C3
67B3
67B3
67B3
67B3
67B3
67B3
67B3
67A3
67A3
67A3
67A3
67A3
67A3
67A3
66B6
66B6
66B6
66B6
66B6
66B6
66B6
66B5
66B5
66B5
66B5
66B5
66B5
66B5
66B1
66B1
66B1
66B1
66B1
66B1
66B1
65D6
65D6
65D6
65D6
65D6
65D6
65D6
65B3
65B3
65B3
65B3
65B3
65B3
65B3
62A6
62A6
62A6
62A6
62A6
62A6
62A6
61D8
61D8
61D8
61D8
61D8
61D8
61D8
61A5
61A5
61A5
61A5
61A5
61A5
61A5
60D4
60D4
60D4
60D4
60D4
60D4
60D4
60C7
60C7
60C7
60C7
60C7
60C7
60C7
58C7
58C7
58C7
58C7
58C7
58C7
58C7
58C4
58C4
58C4
58C4
58C4
58C4
58C4
57B6
57B6
57B6
57B6
57B6
57B6
57B6
54D4
54D4
54D4
54D4
54D4
54D4
54D4
54B5
54B5
54B5
54B5
54B5
54B5
54B5
52D3
52D3
52D3
52D3
52D3
52D3
52D3
49C7
49C7
49C7
49C7
49C7
49C7
49C7
49C4
49C4
49C4
49C4
49C4
49C4
49C4
49B5
49B5
49B5
49B5
49B5
49B5
49B5
40B6
40B6
40B6
40B6
40B6
40B6
40B6
36D6
36D6
36D6
36D6
36D6
36D6
36D6
34A8
34A8
34A8
34A8
34A8
34A8
34A8
33D8
33D8
33D8
33D8
33D8
33D8
33D8
33D3
33D3
33D3
33D3
33D3
33D3
33D3
33C7
33C7
33C7
33C7
33C7
33C7
33C7
29A6
29A6
29A6
29A6
29A6
29A6
29A6
29A3
29A3
29A3
29A3
29A3
29A3
29A3
67D8
28A6
67D8
28A6
28A6
28A6
28A6
28A6
28A6
67D6
27D8
67D6
27D8
27D8
27D8
27D8
27D8
27D8
65A2
27D5
65A2
27D5
27D5
27D5
27D5
27D5
27D5
55A4
27D3
55A4
27D3
27D3
27D3
27D3
27D3
27D3
34C8
27C3
34C8
27C3
27C3
27C3
27C3
27C3
27C3
34C6
26D1
34C6
26D1
26D1
26D1
26D1
26D1
26D1
34B8
26B8
34B8
26B8
26B8
26B8
26B8
26B8
26B8
25C4
26B6
25D3
26B6
79D5
26B6
26B6
26B6
79D5
26B6
26B6
24D3
26B4
24D3
26B4
67D5
79D5
26B4
26B4
26B4
67D5
26B4
26B4
79D5
24C3
25D8
24C3
25D8
67D3
67D5
25D8
25D8
25D8
67D3
25D8
25D3
67D5
21C1
25D3
21C1
25D3
67C3
67D3
25D3
25D3
25D3
67C3
25C6
25C6
67D3
19D7
25C6
19D7
25C6
66C5
67C3
25C6
25C6
25C4
66C5
25C4
25C4
67C3
19D6
25B8
19D6
25C4
65D8
66C5
25C4
25C4
25B8
65D8
25B8
25B8
66C5
19D5
25B4
19D5
25B8
65D2
65D8
25B4
25B8
25B4
65D2
25B4
25B4
65D8
19D2
25A4
19D2
25A4
65D1
65D2
25A4
67C8
25B4
25A4
67C8
65D1
25A4
25A4
65D2
81B3
67C8
67C8
19D1
24D3
19D1
67C8
24D3
67C8
65C8
67C8
65D1
24D3
67C6
24D3
24D3
67C6
65C8
67C8
24D3
24D3
65D1
80B5
67C6
67C6
19C8
24C3
19C8
67C6
24C3
67C6
63D8
67C6
65C8
24C3
66C5
24C3
24C3
66C5
63D8
67C6
24C3
24C3
65C8
80A1
66C5
66C5
17D6
24B5
17D6
66C5
24B5
66C5
56D4
66C5
63D8
24B5
62C1
24B5
24B5
62C1
56D4
66C5
24B5
24B5
63D8
79B8
62C1
62C1
17D3
24B3
17D3
62C1
24B3
62C1
26C5
62C1
56D4
24B3
62A8
24B3
24B3
62A8
26C5
62C1
24B3
71D7
24B3
56D4
71A6
62A8
62A8
16D3
23D5
16D3
62A8
23D5
62A8
25D2
62A8
26C5
23D5
48B6
23D5
23D5
48B6
25D2
62A8
23D5
67C3
23D5
26C5
67B3
48B6
48B6
16C8
23B3
16C8
48B6
23B3
48B6
25C8
48B6
25D2
23B3
25D6
23B3
23B3
25D6
25C8
48B6
23B3
67C1
23B3
25D2
67B1
25D6
25D6
13B5
22B5
13B5
25D6
22B5
25D6
25B6
25D6
25C8
22B5
25C8
22B5
22B5
25C8
25B6
25D6
22B5
67B1
22B5
25B6
67A1
25C6
25C8
12C2
21D3
12C2
25C8
21D3
25C8
24C3
25C8
24C3
21D3
25C6
21D3
21D3
25C6
24C3
25C8
21D3
66D8
21D3
24C3
66B5
25C2
25C2
12B7
21C3
12B7
25C6
21C3
25C6
24B3
25C6
24B3
21C3
25C2
21C3
21C3
25C2
24B3
25C6
21C3
66B8
21C3
24B3
62B1
25B6
25B6
12A7
20B4
12A7
25C2
20B4
25C2
24A5
25C2
24A5
20B4
25B6
20B4
20B4
25B6
24A5
25B6
20B4
65D6
20B4
24A5
61D7
25B2
25B2
11C5
20A4
11C5
25B2
20A4
25B6
23D8
25B6
23D8
20A4
25B2
20A4
20A4
25B2
23D8
25B2
20A4
65B7
20A4
23D8
58C7
25A8
25A8
11B3
19C7
11B3
25A8
19C7
25A8
23D4
25B2
23D4
19C7
25A8
19C7
19C7
25A8
23D4
25A8
19C7
64C8
19C7
23D4
58C4
24B5
24B5
9B7
19C6
9B7
24B5
19C6
24B5
23D1
24B5
23D1
19C6
24B5
19C6
19C6
24B5
23D1
24B5
19C6
62C8
19C6
23D1
57B5
24A5
24A5
8C7
17C6
8C7
24A5
17C6
24A5
23B7
24A5
23B7
17C6
24A5
17C6
17C6
24A5
23B7
24A5
17C6
62B6
17C6
23B7
55A8
24A3
24A3
7D5
14D6
7D5
24A3
14D6
24A3
23A7
24A3
23A7
14D6
24A3
14D6
14D6
24A3
23A7
24A3
14D6
62B2
14D6
23A7
53C4
9B7
9B7
7B6
14C7
7B6
9B7
14C7
9B7
22D8
9B7
22D8
14C7
9B7
14C7
14C7
9B7
22D8
9B7
14C7
26D4
62A4
14C7
22D8
36D6
8B7
8B7
7B5
10C5
7B5
8B7
10C5
8B7
22C6
8B7
22C6
10C5
8B7
10C5
10C5
8B7
22C6
8B7
10C5
26D3
52B5
10C5
22C6
31C5
5D4
5D4
5D4
5D4
5D4
5D4
5D4
5D4
11B5
5D4
11B5
5D4
5D4
5D4
5D4
5D4
11B5
5D4
5D4
24B3
47C7
5D4
11B5
5D4
24D5
5D1
5D1
5B2
5A4
5B2
5D1
24B5
5A4
5D1
5D4
5D1
5D4
5A4
5D1
5A4
5A4
5D1
5D4
5D1
5A4
21D6
5D4
5A4
5D4
5D2
24D5
24D5
22C1
IO
IO
IN
IN
IN
IN
IO
IO
IO
IO
IO
IO
OUT
OUT
IN
IN
OUT
IN
OUT
IN
NCNC
IN
OUT
OUT
IO
IO
IO
IO
IO
IO
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
Initial resistor values are based on CRB,
but may change after characterization.
fault protection for RTC battery.
for use as DVI_HPD in muxed graphics solution.
Pullup on SB_GPIO4 removed as it now defaults low
Platform Reset Connections
NC
518S0452
NOTE: R2607 and D2600 form the double-
NC
Silk: "SYS RST"
Unbuffered
NC
NC
SB RTC Crystal Circuit
1G00 used as small & cheap inverter
100-ohm on NB page
Linda Card represents 3 loads
This part is never stuffed,
NCNC
on the board to short or
LIO represents X loads (2?)
Hook to inverter PWM AND gate (except M59)
This RST is used to mask a glitch output from
the NB PWM output during reset.
On M59 this RST is used for layout reasons
Buffered
D3Cold Reset for GPU
to solder a reset button.
it provides a set of pads
RTC Battery Connector
20K
1/16W
402
5%
MF-LF
R2600
1 2
20%
10V
CERM
402
0.1UF
C2611
1
2
1UF
10%
6.3V
CERM
402
C2605
1
2
OMIT
402
MF-LF
100K
1/16W
5%
R2698
1
2
5%
1/16W
MF-LF
402
1M
R2606
1
2
1/16W
5%
402
10K
MF-LF
R2697
1
2
1K
1/16W
MF-LF
5%
402
R2607
2 1
50V
5%
402
CERM
12pF
C2608
1 2
402
5%
50V
12pF
CERM
C2609
1 2
32.768K
CRITICAL
SM-2
Y2600
2 4
1 3
5%
1/16W
MF-LF
402
0
R2610
1 2
5%
1/16W
MF-LF
402
10M
R2609
1
2
10V
402
CERM
20%
0.1UF
C2680
1
2
5%
1/16W
100K
402
MF-LF
R2680
1
2
MF-LF
0
402
1/16W
5%
R2681
1 2
5%
100
402
MF-LF
1/16W
R2683
1 2
402
5%
1/16W
0
MF-LF
R2684
1 2
5%
1/16W
MF-LF
402
0
R2685
1 2
0
1/16W
5%
402
MF-LF
R2682
1 2
MF-LF
1/16W
5%
402
ITP
1K
R2696
1 2
SC70-5
MC74VHC1G00
U2603
3
2
1
4
5
SC70
MC74VHC1G08
U2680
3
2
1
4
5
MC74VHC1G08
SC70
U2601
3
2
1
4
5
SOT-363
BAT54DW
D2600
1
4
6
3
5
2
CRITICAL
M-RT-SM
BM02B-ACHKS-A-GAN-TF-LF
J2600
3
4
1
2
5%
1/16W
402
MF-LF
100K
R2688
1
2
MC74VHC1G08
SC70
U2685
3
2
1
4
5
402
10V
20%
CERM
0.1UF
C2685
1
2
10K
402
5%
MF-LF
1/16W
R2686
1
2
0
402
MF-LF
1/16W
5%
R2687
1 2
1K
MF-LF
1/16W
5%
402
R2689
1 2
0.001UF
CERM
402
50V
10%
C2689
1
2
1.8K
5%
MF-LF
402
1/16W
R2611
1
2
20%
10V
CERM
402
0.1UF
C2607
1
2
10K
5%
1/16W
MF-LF
402
R2612
1
2
402
MF-LF
1/16W
5%
10K
R2622
1
2
8.2K
R2623
1 2
8.2K
R2624
1 2
8.2K
R2625
1 2
8.2K
R2626
1 2
8.2K
R2627
1 2
8.2K
R2628
1 2
8.2K
R2629
1 2
8.2K
R2630
1 2
8.2K
R2631
1 2
8.2K
R2632
1 2
8.2K
R2633
1 2
8.2K
R2634
1 2
8.2K
R2636
1 2
8.2K
R2637
1 2
8.2K
R2638
1 2
8.2K
R2639
1 2
8.2K
R2640
1 2
8.2K
R2642
1 2
1UF
CERM
10%
6.3V
402
C2610
1
2
SYNC_MASTER=(MASTER)
SYNC_DATE=(MASTER)
87
06004051-7164
26
SB Misc
GPU_SIGNAL_ENABLE
GPU_SIGNAL_ENABLE
MAKE_BASE=TRUE
PP3V3_S5
PLTRST_D3COLD_L
GPU_SIGNAL_ENABLE
PEG_RESET_L
PP3V3_S0
GPU_D3COLD_RESET_L
PLT_RST_L
MAKE_BASE=TRUE
PP3V3_S0
TPM_LRESET_L
PLT_RST_L
GPU_D3COLD_RESET_L
MAKE_BASE=TRUE
MAKE_BASE=TRUE
LIO_PLT_RESET_L
LIO_PLT_RESET_L
PLT_RST_L
PLT_RST_L
PP3V3_S0
PCI_IRDY_L
PCI_SERR_L
PCI_DEVSEL_L
PCI_PERR_L
PCI_REQ0_L
PCI_REQ1_L
PCI_REQ2_L
PCI_REQ3_L
INT_PIRQA_L
INT_PIRQB_L
INT_PIRQC_L
INT_PIRQD_L
SB_GPIO2
SB_GPIO3
PP3V3_S0
VOLTAGE=3.3V
PPVBATT_G3C_RTC
SB_RTC_X2
ENET_RST_L
PP3V3_G3C_SB_RTC_D
VOLTAGE=3.3V
MAKE_BASE=TRUE
PCI_LOCK_L
PCI_STOP_L
PCI_TRDY_L
PCI_FRAME_L
PP3V3_G3C_SB_RTC_D
PP3V42_G3H
VOLTAGE=3.3V
PPVBATT_G3C_RTC_R
VR_PWRGOOD_DELAY
ALL_SYS_PWRGD
PM_SB_PWROK
VR_PWRGD_CK410_L
MAKE_BASE=TRUE
PM_SYSRST_L
MAKE_BASE=TRUE
SB_SM_INTRUDER_L
SB_RTC_X1
DEBUG_RST_L
SMC_LRESET_L
PLT_RST_L
VR_PWRGD_CK410
VR_PWRGD_CK410_L
SB_RTC_RST_L
SB_RTC_X1_R
XDP_DBRESET_L
PP3V3_S0
PLT_RST_BUF_L
82D5
82D5
82C6
82C6
82D5
82D5
82D5
82B3
82B3
82C6
82C6
82C6
82A4
82A4
82B3
82B3
82B3
79D3
79D3
82A4
82A4
82A4
79A8
79A8
79D3
79D3
79D3
71D2
71D2
79A8
79A8
79A8
67C5
67C5
71D2
71D2
71D2
67C3
67C3
67C5
67C5
67C5
67B3
67B3
67C3
67C3
67C3
67A3
67A3
67B3
67B3
67B3
66B6
66B6
67A3
67A3
67A3
66B5
66B5
66B6
66B6
66B6
66B1
66B1
66B5
66B5
66B5
65D6
65D6
66B1
66B1
66B1
65B3
65B3
65D6
65D6
65D6
62A6
62A6
65B3
65B3
65B3
61D8
61D8
62A6
62A6
62A6
61A5
61A5
61D8
61D8
61D8
60D4
60D4
61A5
61A5
61A5
60C7
60C7
60D4
60D4
60D4
58C7
58C7
60C7
60C7
60C7
58C4
58C4
58C7
58C7
58C7
57B6
57B6
58C4
58C4
58C4
54D4
54D4
57B6
57B6
57B6
54B5
54B5
54D4
54D4
54D4
52D3
52D3
54B5
54B5
54B5
49C7
49C7
52D3
52D3
52D3
49C4
49C4
49C7
49C7
49C7
49B5
49B5
49C4
49C4
49C4
40B6
40B6
49B5
49B5
49B5
36D6
36D6
40B6
40B6
40B6
34A8
34A8
36D6
36D6
36D6
33D8
33D8
34A8
34A8
34A8
33D3
33D3
33D8
33D8
33D8
33C7
33C7
33D3
33D3
33D3
29A6
29A6
33C7
33C7
33C7
29A3
29A3
29A6
29A6
29A6
28A6
28A6
29A3
29A3
29A3
27D8
27D8
28A6
28A6
28A6
27D5
27D5
27D8
27D8
27D8
27D3
27D3
27D5
27D5
27D5
27C3
27C3
27D3
27D3
27D3
26D1
26D1
27C3
27C3
27C3
26B8
26B8
26D1
26B8
26D1
26B6
26B6
26B6
26B6
26B8
26B4
26B4
26B4
26B4
26B4
79D5
25D8
25D8
25D8
25D8
25D8
67D5
25D3
25D3
25D3
25D3
25D3
67D3
25C6
25C6
25C6
25C6
25C6
67C3
25C4
25C4
25C4
25C4
25C4
66C5
25B8
25B8
25B8
25B8
81D4
25B8
65D8
25B4
25B4
25B4
25B4
69C8
25B4
65D2
25A4
25A4
25A4
25A4
69B8
25A4
65D1
24D3
24D3
24D3
24D3
69A8
24D3
65C8
24C3
24C3
24C3
24C3
68B8
24C3
63D8
24B5
24B5
24B5
24B5
67D5
24B5
56D4
24B3
24B3
24B3
24B3
67D3
24B3
25D2
23D5
23D5
23D5
23D5
66D2
23D5
25C8
23B3
23B3
23B3
23B3
66C8
23B3
25B6
22B5
22B5
22B5
22B5
66A8
22B5
24C3
21D3
21D3
21D3
21D3
53C4
21D3
24B3
21C3
21C3
82A4
21C3
21C3
52D7
82A4
21C3
24A5
20B4
82A4
20B4
82A4
82A4
79A8
20B4
20B4
52B7
79A8
20B4
23D8
20A4
79A8
20A4
79A8
79A8
26C3
20A4
20A4
52B5
26C3
20A4
23D4
19C7
26C1
19C7
26C3
26C3
26C1
19C7
19C7
52B1
26C1
19C7
23D1
19C6
26B1
19C6
26C1
26C1
26B1
19C6
19C6
51D4
26B1
19C6
23B7
17C6
26A4
17C6
26B1
26A4
26A4
17C6
17C6
51D3
26A4
17C6
23A7
14D6
22A6
14D6
22A6
22A6
22A6
14D6
14D6
51C2
22A6
14D6
82A7
22D8
82A7
14C7
14B7
14C7
14B7
14B7
14B7
14C7
37D3
14C7
26D3
26D4
47B5
14B7
61C7
14C7
80B2
82A7
22C6
80B2
10C5
6C7
10C5
6C7
48C3
48C3
6C7
6C7
10C5
22B6
10C5
25A4
25A4
35B7
61C7
6C7
33A4
10C5
26A2
80B2
11B5
26A2
70A5
5D4
26A4
6C6
5D4
60B7
6C6
26C1
26C1
6C6
6C6
5D4
37D3
37C3
37D3
37D3
6B5
37D3
5D4
24B3
37C3
37C3
37D3
24B3
27C3
66B1
33A4
53B4
51C7
6C6
26A7
5D4
26A1
26A1
5D4
26A1
5C4
5A4
23C5
5C4
5A4
5C4
5C4
5C1
5C1
5C4
5C4
5A4
22A6
22A6
22A6
22A6
22B6
22B6
22B6
6B3
22A7
22A7
22A7
22A7
22A6
22A6
5A4
21D6
39C6
21D6
22A6
22A6
22A6
22A7
21D6
5D2
51D7
26A8
21D6
21D6
5C2
5C4
5C4
5A4
37A7
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
(Write: 0x92 Read: 0x93)
SMC "Battery B" SMBus Connections
NOTE: SMC RMT bus remains powered and may be active in S3 state
SMC "A" SMBus Connections
Battery
SMC "Battery A" SMBus Connections
(Write: 0x16 Read: 0x17)
(See Table)
Left I/O Board
USB Hub
Top-Case
SMC "B" SMBus Connections
TMP106: U5650
Battery Chgr
(Write: 0x98 Read: 0x99)
TMP401: U1001
CPU Temp
SMC "0" SMBus Connections
GPU Temp
U5800
(MASTER)
SO-DIMM "B"
ICH7-M SMBus Connections
(WRITE: 0X98 READ: 0X99)
(WRITE: 0X92 READ: 0X93)
LIO/ALS Temp
TMP106: J5500
(Write: 0xD2 Read: 0xD3)
SO-DIMM "A"
M35B - TMP106
(Write: 0x72 Read: 0x73)
Left I/O SMBus Connections:
(Write: 0x92 Read: 0x93)
ExpressCard Slot
(Address determined by ARP)
(See Table)
J4900
Trackpad
(See Table)
U4900
(Write: 0x70 Read: 0x71)
(Write: 0x58 Read: 0x59)
USB_HUB - U4900
U1 - Trackpad Controller
J5500
(MASTER)
U5800
SMC
TMP275: J4900
ICH7-M
(Write: 0xA0 Read: 0xA1)
U2100
(MASTER)
(Write: 0x98 Read: 0x99)
TMP401: U6150
Remote Temps
MAX6695: U6100
U2 - Keyboard Controller
SMC
SMC
(MASTER)
U5800
U5800
(MASTER)
J2800
(MASTER)
SMC
U5800
J2900
J8250
SMC
Trackpad I2C Connections:
(Write: 0x30 Read: 0x31)
(Write: 0xA4 Read: 0xA5)
CY28445-5: U3301
Clock Chip
4.7K
5%
MF-LF
402
1/16W
R2700
1
2
5%
402
1/16W
4.7K
MF-LF
R2701
1
2
3.3K
MF-LF
402
5%
1/16W
R2780
1
2
3.3K
MF-LF
402
5%
1/16W
R2781
1
2
MF-LF
402
1/16W
5%
100K
R2791
1
2
5%
100K
402
MF-LF
1/16W
R2790
1
2
MF-LF
402
1/16W
5%
4.7K
R2761
1
2
4.7K
MF-LF
402
1/16W
5%
R2760
1
2
5%
402
MF-LF
1/16W
4.7K
R2771
1
2
4.7K
5%
MF-LF
402
1/16W
R2770
1
2
402
MF-LF
1/16W
5%
4.7K
R2751
1
2
402
4.7K
1/16W
5%
MF-LF
R2750
1
2
CERM
15pF
NO STUFF
5%
50V
402
C2701
1
2
CERM
5%
50V
402
15pF
C2761
1
2
5%
50V
CERM
402
15pF
C2751
1
2
051-7164 06004
27 87
M57 SMBUS CONNECTIONS
SYNC_MASTER=(MASTER)
SYNC_DATE=(MASTER)
SMBUS_SMC_BSA_SCL
PP3V3_S0
SMBUS_SB_SDA
SMBUS_SMC_0_S0_SDA
PP3V3_S0
SMBUS_SB_SDA
SMBUS_SMC_0_S0_SCL SMBUS_SMC_B_S0_SCL
SMBUS_SMC_BSA_SDA SMBUS_SMC_BSA_SDA
SMBUS_SMC_BSB_SDA
SMBUS_SMC_BSA_SCL
SMBUS_SMC_BSB_SDA
MAKE_BASE=TRUE
SMBUS_SMC_BSB_SCL
MAKE_BASE=TRUE
PP3V42_G3H
PP3V3_S0
SMBUS_SMC_B_S0_SDA
PP3V3_S0
SMBUS_SMC_BSB_SCL
SMBUS_SMC_0_S0_SDA
SMBUS_SMC_0_S0_SCL
SMBUS_SMC_BSA_SDA
MAKE_BASE=TRUE
SMBUS_SMC_0_S0_SCL
MAKE_BASE=TRUE
SMBUS_SMC_0_S0_SCL
SMBUS_SMC_A_S3_SDA
SMBUS_SMC_A_S3_SCL
SMBUS_SMC_A_S3_SDA
SMBUS_SB_SDA
SMBUS_SB_SCL
SMBUS_SB_SCL
SMBUS_SB_SDA
MAKE_BASE=TRUE
SMBUS_SB_SDA
SMBUS_SB_SCL
SMBUS_SB_SDA
SMBUS_SB_SCL
SMBUS_SMC_A_S3_SDA
SMBUS_SMC_A_S3_SCL
SMBUS_SMC_A_S3_SCL
MAKE_BASE=TRUE
SMBUS_SMC_A_S3_SDA
MAKE_BASE=TRUE
SMBUS_SMC_B_S0_SCL
SMBUS_SMC_B_S0_SDA
SMBUS_SB_SCL
SMBUS_SB_SCL
SMBUS_SB_SDA
SMBUS_SB_SCL
SMBUS_SB_SCL
MAKE_BASE=TRUE
SMBUS_SB_SDA
SMBUS_SMC_A_S3_SCL
MAKE_BASE=TRUE
SMBUS_SMC_BSA_SCL
SMBUS_SMC_0_S0_SDA
MAKE_BASE=TRUE
SMBUS_SMC_0_S0_SDA
PP3V3_S3
SMBUS_SMC_B_S0_SDA
SMBUS_SMC_B_S0_SCL
SMBUS_SMC_B_S0_SDA
MAKE_BASE=TRUE
SMBUS_SMC_B_S0_SCL
MAKE_BASE=TRUE
82D5
82D5
82D5 82D5 82C6
82C6
82C6 82C6 82B3
82B3
82B3 82B3 82A4
82A4
82A4 82A4
79D3
79D3
79D3 79D3 79A8
79A8
79A8 79A8 71D2
71D2
71D2 71D2 67C5
67C5
67C5 67C5 67C3
67C3
67C3 67C3 67B3
67B3
67B3 67B3 67A3
67A3
67A3 67A3 66B6
66B6
66B6 66B6
66B5
66B5
66B5 66B5 66B1
66B1
66B1 66B1 65D6
65D6
65D6 65D6 65B3
65B3
65B3 65B3 62A6
62A6
62A6 62A6 61D8
61D8
61D8 61D8 61A5
61A5
61A5 61A5 60D4
60D4
60D4 60D4
60C7
60C7
60C7 60C7 58C7
58C7
58C7 58C7 58C4
58C4
58C4 58C4 57B6
57B6
57B6 57B6 54D4
54D4
54D4 54D4 54B5
54B5
54B5 54B5 52D3
52D3
52D3 52D3 49C7
49C7
49C7 49C7 49C4
49C4
49C4 49C4
49B5
49B5
49B5 49B5 40B6
40B6
40B6 40B6 36D6
36D6
36D6 36D6 34A8
34A8
34A8 34A8 33D8
33D8
33D8 33D8 33D3
33D3
33D3 33D3 33C7
33C7
33C7 33C7 29A6
29A6
29A6 29A6
29A3
29A3
29A3 29A3 28A6
28A6
28A6 28A6 27D5
27D8
27D8 27D8 27D3
27D5
27D3 27D5 27C3
27D3
27C3 27C3 26D1
26D1
26D1 26D1 26B8
26B8
26B8 26B8 26B6
26B6
26B6 26B6 26B4
26B4
26B4 26B4
25D8
25D8
25D8 25D8 25D3
25D3
25D3 25D3 25C6
25C6
25C6 25C6 25C4
25C4
25C4 25C4 25B8
25B8
81D4
25B8 25B8 25B4
25B4
69C8
25B4 25B4
81D4
25A4
25A4
69B8
25A4 25A4
81A5
24D3
24D3
69A8
24D3 24D3
67C5
24C3
24C3
68B8
24C3 24C3
67C3
24B5
24B5
67D5
24B5 24B5
66C6
24B3
24B3
67D3
24B3 24B3
65D1
23D5
23D5
66D2
23D5 23D5
63B7
23B3
23B3
66C8
23B3 23B3
60C2
22B5
81C3
22B5
81C3
66A8
22B5 22B5
81C3
81C3
81C3
81C3
59C6
21D3
48B3
21D3
48B3
53C4
21D3 21D3
81C3
48B3
48B3
48B3
48B3
81C3
57D4
21C3
46B6
21C3
46B6
52D7
21C3 21C3
48B3
46B6
46B6
46B6
46B6
48B3
52B1
20B4
33B6
20B4
33B6
52B7
20B4 20B4
46B6
33B6
33B6
33B6
33B6
46B6
46D6
20A4
29A6
20A4
29A6
52B5
20A4 20A4
33B6
29A6
29A6
29A6
29A6
33B6
46C3
19C7
28A6
19C7
28A6
52B1
19C7 19C7
29A6
28A6
28A6
28A6
28A6
29A6
46B3
19C6
27D8
19C6
27D8
51D4
19C6 19C6
81C3
81C3
28A6
27D8
27D8
81C3
81C3
27D8
27D8
28A6
81C3
41C5
17C6
27D7
17C6
27D7
51D3
17C6 17C6
54C2
54C2
54C2
51B5
81C3
51B5
27D7
27D7
27D7
51B5
81C3
51B5
51B5
51B5
27D7
27D7
27D8
51B5
37D7
51B5
51B5
68B2
14D6
27D6
54C2
14D6
27D6
54C2 51B5
68B2 68B2
68B2
51C2
14D6
51B5
14D6
54B3
54B3
68B2
54B3
54C2
48B6
51B5
48B6
27D6
27D6
27D6
48B6
51B5
48B6
49B5
49B5
27D6
27D6
27D6
48B6
68B2
54C2
37D5
49B5
49B5
51B5
51B5
51B5
14C7
27C6
54B3
14C7
27C6
54B3 49B5
51B5 51B5
51B5
47B5
14C7
49B5
14C7
51C5
51C7
51B5
51C7
54B3
27C6
48B6
27C5
27C6
27C6
27C6
27C6
48B6
27C6
27D3
27D3
27C6
27C6
27C6
27C6
51B5
54B3
37C3
27D3
27D3
49B5
49B5
27C2
10C5
27B6
51C5
10C5
27B6
51C7 27D2
27C2 27C3
27C3
35B7
10C5
27D2
10C5
27D6
27D6
27C3
27D6
51C7
27C5
27C5
27C3
27B6
27B6
27B6
27C5
27C6
27C3
27D2
27D2
27B6
27B6
27B6
27C5
27C3
51C5
37A7
27D2
27D2
27D3
27D3
27C1
5D4
23D5
27D5
5D4
23D5
27D5 27D1
27C1 27C2
51C7
27C2
51C7
51C5
26D6
5D4
27D1
5D4
51C5
27D5
27D5
27C1
27D5
27D6
27B3
27C3
27B3
23D5
23D5
23D5
27C3
27C3
27B3
27D1
27D1
23D5
23D5
23D5
27C3
27C1
27D6
32C5
27D1
27D1
27D1
27D1
5D1
5A4
5B1
27D3
5A4
5B1
27D3 10B3
5D1 5D1
27B2
5D1
27B3
27B3
5D2
5A4
10B3
5A4
27B2
27D3
27D3
5D1
27D3
27D3
5B1
5B1
5B1
5B1
5B1
5B1
5B1
5B1
5B1
10B3
10B3
5B1
5B1
5B1
5B1
5D1
27D3
5D4
10B3
10B3
10B3
10B3
VSS2
DQS0*
DQ5
VSS0
DQ4
VSS5
DQ6
VSS29
DM0
VSS7
DM1
DQ7
VDD1
DQ30
DQ23
VSS22
NC/ODT1
RAS*
SA1
SA0
VSS58
DQ63
DQ62
VSS56
DQS7
DQS7*
VSS54
DQ60
VSS52
DQ54
VSS50
VSS48
CK1*
CK1
VSS46
DQ53
DQ52
VSS44
VSS42
DQS5
DQS5*
VSS39
DQ45
DQ44
VSS37
DQ39
DQ38
VSS35
DM4
VSS34
DQ37
DQ36
VSS32
NC3
VDD11
NC/A13
ODT0
VDD9
S0*
BA1
VDD7
A0
A2
A4
VDD5
A6
A7
A11
VDD3
NC/A14
NC/A15
NC/CKE1
VSS30
DQ31
DQS3
DQ29
DQ28
VSS24
DQ22
DM2
NC0
VSS19
DQ21
DQ20
VSS17
VSS15
DQ15
DQ14
VSS13
CK0*
CK0
VSS11
DQ13
DQ12
DQ47
DQ46
DQ61
DQ55
DM6
VDDSPD
SCL
SDA
VSS57
DQ59
DQ58
VSS55
DM7
VSS53
DQ56
VSS51
DQ50
VSS49
DQS6*
VSS47
NC_TEST
VSS45
DQ49
DQ48
VSS43
VSS41
DM5
VSS40
DQ41
VSS38
DQ35
VSS36
DQS4
DQS4*
VSS33
DQ33
DQ32
VSS31
VDD10
NC/S1*
CAS*
VDD8
WE*
BA0
A10/AP
VDD6
A1
A3
A5
VDD4
A8
A9
A12
VDD2
BA2
NC2
VDD0
CKE0
DQ27
DQ26
VSS27
NC1
DM3
DQ25
DQ24
VSS23
DQ19
DQ18
VSS21
DQS2
DQS2*
VSS18
DQ17
DQ16
VSS16
VSS14
DQ11
DQ10
VSS12
DQS1
DQS1*
DQ9
DQ8
VSS8
DQ3
DQ2
VSS6
DQS0
VREF
DQ34
DQ40
DQ42
DQ43
DQS6
DQ51
DQ57
KEY
VSS9
DQ1
VSS4
DQ0
VSS1
DQS3*
VSS26
VSS28
VSS25
VSS10
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
NC
DDR2 Bypass Caps
(For return current)
ADDR=0xA0(WR)/0xA1(RD)
NC
NC
NC
NC
- =PPSPD_S0_MEM (2.5V - 3.3V)
- =PP1V8_S3_MEM
BOM options provided by this page:
(NONE)
Power aliases required by this page:
NC
- =I2C_SODIMMA_SCL
- =I2C_SODIMMA_SDA
NOTE: This page does not supply VREF.
The reference voltage must be provided
by another page.
Signal aliases required by this page:
Page Notes
516S0471
"Expansion" (surface-mount) slot
10%
1UF
CERM
6.3V
402
C2813
1
2
10%
1UF
CERM
6.3V
402
C2812
1
2
6.3V
20%
603
X5R
10UF
C2809
1
2
10%
1UF
CERM
6.3V
402
C2811
1
2
6.3V
20%
603
X5R
10UF
C2808
1
2
10%
1UF
CERM
6.3V
402
C2810
1
2
1UF
CERM
6.3V
10%
402
C2819
1
2
1UF
CERM
6.3V
10%
402
C2818
1
2
10%
1UF
CERM
6.3V
402
C2817
1
2
10%
1UF
CERM
6.3V
402
C2816
1
2
1UF
CERM
6.3V
10%
402
C2821
1
2
1UF
CERM
6.3V
10%
402
C2820
1
2
10%
1UF
CERM
6.3V
402
C2815
1
2
10%
1UF
CERM
6.3V
402
C2814
1
2
10V
20%
402
CERM
0.1uF
C2800
1
2
DDR2-SODIMM-DUAL
CRITICAL
F-RT-SM-M9
J2800
102A
105A
90A89A
101A
100A
99A
98A97A
94A
92A
93A
91A
107A
106A
85A
113A
30A
32A
164A
166A
79A
10A
26A
52A
67A
130A
147A
170A
185A
5A
35A
37A
20A
22A
36A
38A
43A
45A
55A
57A
7A
44A
46A
56A
58A
61A
63A
73A
75A
62A
64A
17A
74A
76A
123A
125A
135A
137A
124A
126A
134A
136A
19A
141A
143A
151A
153A
140A
142A
152A
154A
157A
159A
4A
173A
175A
158A
160A
174A
176A
179A
181A
189A
191A
6A
180A
182A
192A
194A
14A
16A
23A
25A
13A
11A
31A
29A
51A
49A
70A
68A
131A
129A
148A
146A
169A
167A
188A
186A
201
202
203
204
116A
86A
84A
80A
119A
115A
50A
69A
83A
120A
163A
114A
108A
110A
198A
200A
197A
195A
81A
117A 118A
82A
87A 88A
95A 96A
103A 104A
111A 112A
199A
1A 2A
27A 28A
33A 34A
39A 40A
41A 42A
47A 48A
3A
53A 54A
59A 60A
65A 66A
71A 72A
77A
8A
78A
121A 122A
127A 128A
132A
133A
138A
139A
144A
145A
149A 150A
155A 156A
161A 162A
165A
168A
171A
9A
172A
177A 178A
183A 184A
187A
190A
193A
196A
12A
15A
18A
21A
24A
109A
6.3V
CERM1
603
20%
2.2uF
C2801
1
2
28 87
06004051-7164
DDR2 SO-DIMM Connector A
SYNC_MASTER=M59_MLB
SYNC_DATE=09/15/2006
PP1V8_S3
MEM_A_DQ<28>
MEM_A_DQ<25>
MEM_A_DQ<30>
MEM_A_A<10>
MEM_A_DQ<43>
MEM_A_DQ<56>
MEM_A_DQS_N<7>
MEM_A_DQ<63>
MEM_A_DQS_P<7>
MEM_A_DQ<62>
MEM_A_DQ<57>
MEM_A_DQ<60>
MEM_A_DQ<55>
MEM_A_DQ<45>
MEM_A_DQ<61>
MEM_A_DQ<59>
MEM_A_DQS_N<1>
MEM_A_DQS_P<1>
MEM_A_DQ<10>
MEM_A_DM<1>
MEM_A_DQ<15>
MEM_A_DQ<9>
MEM_A_DQ<3>
MEM_A_DQ<26>
MEM_A_DQS_P<3>
MEM_A_DQ<44>
PM_EXTTS_L
MEM_A_DQ<49>
MEM_A_DQ<52>
MEM_A_DQS_P<6>
MEM_A_DQS_N<6>
MEM_A_DQ<54>
MEM_A_DQ<47>
MEM_A_DM<5>
MEM_CLK_N<1>
MEM_A_DQ<42>
MEM_A_DQ<40>
MEM_A_DQ<36>
MEM_A_DQ<32>
MEM_A_DM<4>
MEM_A_DQ<34>
MEM_A_DQ<38>
MEM_A_A<13>
MEM_CS_L<0>
MEM_A_A<2>
MEM_A_A<4>
MEM_A_A<6>
MEM_A_A<7>
NC_MEM_A_A<14>
NC_MEM_A_A<15>
MEM_A_DQ<21>
MEM_A_DQ<0>
MEM_CLK_N<0>
MEM_CLK_P<0>
MEM_A_DQ<8>
SMBUS_SB_SCL
SMBUS_SB_SDA
MEM_A_DQ<48>
MEM_A_DQ<53>
MEM_A_DM<6>
MEM_A_DQ<50>
MEM_A_DQ<51>
MEM_A_DQ<46>
MEM_A_DQ<41>
MEM_A_DQS_P<5>
MEM_A_DQS_N<5>
MEM_A_DQ<58>
MEM_A_DM<7>
MEM_A_DQ<33>
MEM_A_DQ<37>
MEM_A_DQS_P<4>
MEM_A_DQS_N<4>
MEM_A_DQ<39>
MEM_A_DQ<35>
MEM_ODT<1>
MEM_A_DQ<7>
MEM_A_WE_L
MEM_A_BS<0>
MEM_A_A<1>
MEM_A_A<3>
MEM_A_A<5>
MEM_A_A<8>
MEM_A_A<9>
MEM_A_A<12>
MEM_A_BS<2>
MEM_CKE<0>
MEM_A_DQ<27>
MEM_A_DM<3>
MEM_A_DQ<16>
MEM_A_DQ<20>
MEM_A_DQS_P<2>
MEM_A_DQS_N<2>
MEM_A_DQ<18>
MEM_A_DQ<19>
MEM_A_DQ<6>
MEM_A_DQS_P<0>
MEM_A_DQS_N<0>
MEM_A_DQ<4>
MEM_A_DQ<5>
MEM_A_DQ<11>
MEM_A_DQ<14>
MEM_CKE<1>
MEM_A_BS<1>
MEM_A_DQ<1>
MEM_A_DQ<22>
MEM_A_DM<2>
MEM_A_DQ<17>
MEM_A_DQ<29>
MEM_A_DQ<24>
MEM_A_DQ<31>
MEM_A_A<11>
MEM_A_A<0>
MEM_A_RAS_L
MEM_ODT<0>
MEM_CS_L<1>
MEM_A_CAS_L
MEM_A_DQ<23>
MEM_A_DQS_N<3>
MEM_A_DQ<12>
MEM_A_DQ<13>
MEM_A_DQ<2>
PP1V8_S3
PP3V3_S0
PP1V8_S3
MEM_CLK_P<1>
MEM_A_DM<0>
MEMVREF_OUT
82D5
82C6 82B3 82A4 79D3 79A8 71D2 67C5 67C3
67B3 67A3 66B6 66B5 66B1 65D6 65B3 62A6
61D8 61A5 60D4 60C7 58C7 58C4 57B6 54D4
54B5 52D3 49C7 49C4 49B5 40B6 36D6 34A8 33D8
33D3 33C7 29A6 29A3 27D8 27D5 27D3 27C3 26D1
26B8 26B6 26B4 25D8 25D3 25C6 25C4 25B8 25B4
25A4 24D3 24C3
67B8
67B8
24B5
67B8
67B6
67B6
24B3
67B6
64C1
64C1
23D5
64C1
64A6
64A6
23B3
64A6
37B2
37B2
22B5
37B2
32C6
81C3
81C3
32C6
21D3
32C6
31C5
48B3
48B3
31C5
21C3
31C5
29D6
46B6
46B6
29D6
20B4
29D6
29D3
33B6
33B6
29D3
20A4
29D3
29B2
29A6
29A6
29B2
19C7
29B2
28D6
27D8
27D8
28D3
19C6
28D6
28D3
27D7
27D7
28B2
17C6
28B2
19D7
52D5
27D6
27D6
19D7
14D6
19D7
16B6
52D3
27C6
27C6
16B6
14C7
16B6
32B4
14C2
51B7
27B6
27B6
14C2
10C5
14C2
32B3
5D4
30C6
29C3
30C6
30D6
30C6
30C6
30C6
30C6
23D5
23D5
30C6
30B6
30B6
30C6
30C6
30C6
30C6
30C6
30C6
30B6
30D6 30D6
30B6
30C6
30C6
30B6
30C6
30D6
30B6
5D4
5D4
5D4
29D6
5B2
15C7
15C7
15C7
15B5
15B7
15B7
15C5
15A7
15C5
15A7
15B7
15A7
15B7
15B7
15A7
15B7
15C5
15C5
15C7
15D5
15C7
15C7
15D7
15C7
15C5
15B7
14B7
15B7
15B7
15C5
15C5
15B7
15B7
15C5
14D4
15B7
15B7
15B7
15C7
15C5
15B7
15B7
15B5
14C4
15C5
15B5
15B5
15B5
6D7
6D7
15C7
15D7
14D4
14D4
15C7
5B1
5B1
15B7
15B7
15C5
15B7
15B7
15B7
15B7
15C5
15C5
15B7
15C5
15C7
15B7
15C5
15C5
15B7
15B7
14C4
15D7
15B5
15D5
15C5
15B5
15B5
15B5
15B5
15B5
15D5
14C4
15C7
15C5
15C7
15C7
15C5
15C5
15C7
15C7
15D7
15C5
15C5
15D7
15D7
15C7
15C7
14C4
15D5
15D7
15C7
15D5
15C7
15C7
15C7
15C7
15B5
15C5
15B5
14C4
14C4
15D5
15C7
15C5
15C7
15C7
15D7
5B2
5A4
5B2
14D4
15D5
14C2
VSS7
VSS12
VSS9
KEY
DQ57
DQ51
DQS6
DQ43
DQ42
DQ40
DQ34
DQ1
DQ0
VSS1
DQS0*
DQS0
VSS6
DQ2
DQ3
DQ8
DQ9
VSS10
DQS1*
DQS1
DQ10
DQ11
VSS14
VSS16
DQ16
DQ17
VSS18
DQS2*
DQS2
VSS21
DQ18
DQ19
VSS23
DQ24
DQ25
VSS25
DM3
NC1
VSS27
DQ26
DQ27
VSS29
CKE0
VDD0
NC2
BA2
VDD2
A12
A9
A8
VDD4
A5
A3
A1
VDD6
A10/AP
BA0
WE*
VDD8
CAS*
NC/S1*
VDD10
NC/ODT1
VSS31
DQ32
DQ33
VSS33
DQS4*
DQS4
VSS36
DQ35
VSS38
DQ41
VSS40
DM5
VSS41
VSS43
DQ48
DQ49
VSS45
NC_TEST
VSS47
DQS6*
VSS49
DQ50
VSS51
DQ56
VSS53
DM7
VSS55
DQ58
DQ59
VSS57
SDA
SCL
VDDSPD
DM6
DQ55
DQ61
DQ46
DQ47
DQ12
DM1
DM0
DQ7
DQ13
VSS11
CK0
CK0*
VSS13
DQ14
DQ15
VSS15
VSS17
DQ20
DQ21
VSS19
NC0
DM2
VSS22
DQ22
DQ23
VSS24
DQ28
DQ29
VSS26
DQS3*
DQS3
VSS28
DQ30
DQ31
VSS30
NC/CKE1
VDD1
NC/A15
NC/A14
VDD3
A11
A7
A6
VDD5
A4
A2
A0
VDD7
BA1
RAS*
S0*
VDD9
ODT0
NC/A13
VDD11
NC3
VSS32
DQ36
DQ37
VSS34
DM4
VSS35
DQ38
DQ39
VSS37
DQ44
DQ45
VSS39
DQS5*
DQS5
VSS42
VSS44
DQ52
DQ53
VSS46
CK1
CK1*
VSS48
VSS50
DQ54
VSS52
DQ60
VSS54
DQS7*
DQS7
VSS56
DQ62
DQ63
VSS58
SA0
SA1
DQ5
VSS2
VREF
VSS4
VSS8
VSS0
DQ4
VSS5
DQ6
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
"Factory" (thru-hole) slot
DDR2 Bypass Caps
(For return current)
ADDR=0xA4(WR)/0xA5(RD)
Resistor prevents pwr-gnd short
NC
NC
NC
NC
NC
BOM options provided by this page:
- =PPSPD_S0_MEM (2.5V - 3.3V)
- =PP1V8_S3_MEM
Power aliases required by this page:
(NONE)
Signal aliases required by this page:
NC
Page Notes
- =I2C_SODIMMB_SCL
- =I2C_SODIMMB_SDA
by another page.
The reference voltage must be provided
NOTE: This page does not supply VREF.
516-0140
402
CERM
1UF
10%
6.3V
C2913
1
2
402
CERM
1UF
10%
6.3V
C2912
1
2
6.3V
20%
603
X5R
10UF
C2909
1
2
10V
0.1uF
CERM
402
20%
C2911
1
2
603
20%
6.3V
X5R
10UF
C2908
1
2
402
CERM
1UF
10%
6.3V
C2910
1
2
10V
0.1uF
CERM
402
20%
C2919
1
2
10V
0.1uF
CERM
402
20%
C2918
1
2
0.1uF
CERM
402
20%
10V
C2917
1
2
402
CERM
1UF
10%
6.3V
C2916
1
2
10V
0.1uF
CERM
402
20%
C2921
1
2
0.1uF
10V
CERM
402
20%
C2920
1
2
402
CERM
1UF
10%
6.3V
C2915
1
2
402
CERM
1UF
10%
6.3V
C2914
1
2
402
MF-LF
1/16W
5%
10K
R2900
1
2
CRITICAL
DDR2-SODIMM-DUAL
F-RT-TH1
J2900
102B
105B
90B89B
101B
100B
99B
98B97B
94B
92B
93B
91B
107B
106B
85B
113B
30B
32B
164B
166B
79B
10B
26B
52B
67B
130B
147B
170B
185B
5B
35B
37B
20B
22B
36B
38B
43B
45B
55B
57B
7B
44B
46B
56B
58B
61B
63B
73B
75B
62B
64B
17B
74B
76B
123B
125B
135B
137B
124B
126B
134B
136B
19B
141B
143B
151B
153B
140B
142B
152B
154B
157B
159B
4B
173B
175B
158B
160B
174B
176B
179B
181B
189B
191B
6B
180B
182B
192B
194B
14B
16B
23B
25B
13B
11B
31B
29B
51B
49B
70B
68B
131B
129B
148B
146B
169B
167B
188B
186B
201
202
116B
86B
84B
80B
119B
115B
50B
69B
83B
120B
163B
114B
108B
110B
198B
200B
197B
195B
81B
117B 118B
82B
87B 88B
95B 96B
103B 104B
111B 112B
199B
1B 2B
27B 28B
33B 34B
39B 40B
41B 42B
47B 48B
3B
53B 54B
59B 60B
65B 66B
71B 72B
77B
8B
78B
121B 122B
127B 128B
132B
133B
138B
139B
144B
145B
149B 150B
155B 156B
161B 162B
165B
168B
171B
9B
172B
177B 178B
183B 184B
187B
190B
193B
196B
12B
15B
18B
21B
24B
109B
0.1uF
CERM
402
20%
10V
C2900
1
2
2.2uF
20%
603
CERM1
6.3V
C2901
1
2
8729
051-7164 06004
SYNC_MASTER=M59_MLB
SYNC_DATE=09/15/2006
DDR2 SO-DIMM Connector B
MEM_B_DQ<1>
MEM_CLK_N<3>
MEM_B_DQ<0>
PP1V8_S3
MEM_B_DQ<20>
PP1V8_S3
MEM_B_DQ<27>
NC_MEM_B_A<15>
MEM_B_DQ<31>
MEM_B_DQ<30>
MEM_B_DQ<26>
MEM_B_DQ<7>
MEM_B_DQ<5>
MEM_B_DQ<2>
MEM_B_DQ<3>
MEM_B_DQ<6>
MEM_B_DQ<4>
MEM_CLK_P<3>
MEM_B_DM<0>
MEM_B_DQ<10>
MEM_B_DQ<13>
MEM_B_DQS_P<1>
MEM_B_DQS_N<1>
MEM_B_DQ<22>
PM_EXTTS_L
MEM_B_DQS_P<0>
MEM_B_DQ<8>
MEM_B_DQ<59>
MEM_B_DQ<58>
MEM_B_DQ<63>
MEM_B_DQ<62>
MEM_CLK_P<2>
MEM_B_DM<7>
MEM_B_DQ<56>MEM_B_DQ<60>
MEM_B_DQ<57>MEM_B_DQ<61>
MEM_B_DQ<47>
MEM_B_DQS_N<7>
MEM_B_DQS_N<6>
MEM_B_DQS_P<6>
MEM_B_DQS_P<7>
MEM_B_A<5>
MEM_CKE<3>
NC_MEM_B_A<14>
MEM_B_DM<3>
MEM_B_DQ<19>
MEM_B_DQ<11>
MEM_B_DQ<9>
MEM_B_BS<1>
MEM_B_A<0>
MEM_B_A<2>
MEM_B_A<4>
MEM_B_A<6>
MEM_B_A<7>
MEM_B_A<11>
MEM_B_DQS_P<3>
MEM_B_DQS_N<3>
MEM_B_DQ<28>
MEM_B_DQ<16>
MEM_B_DQ<17>
MEM_B_DM<2>
MEM_B_DQ<12>
MEM_B_DQ<32>
MEM_B_DQ<55>
MEM_CLK_N<2>
MEM_B_DQ<46>
MEM_B_DQS_P<5>
MEM_B_DQS_N<5>
MEM_B_DQ<45>
MEM_B_DQ<44>
MEM_B_DQ<39>
MEM_B_DQ<38>
MEM_B_DM<4>
MEM_B_DQ<37>
MEM_B_A<13>
MEM_ODT<2>
MEM_CS_L<2>
MEM_B_RAS_L
MEM_B_DQ<42>
MEM_B_DQ<49>
MEM_B_DQ<52>
MEM_B_DM<6>
MEM_B_DQ<51>
MEM_B_DQ<54>
MEM_B_DQ<43>
MEM_B_DM<5>
MEM_B_DQ<41>
MEM_B_DQ<40>
MEM_B_DQ<35>
MEM_B_DQ<34>
MEM_B_DQS_P<4>
MEM_B_DQS_N<4>
MEM_B_DQ<33>
MEM_B_DQ<36>
MEM_ODT<3>
MEM_CS_L<3>
MEM_B_CAS_L
MEM_B_WE_L
MEM_B_BS<0>
MEM_B_A<10>
MEM_B_A<1>
MEM_B_A<3>
MEM_B_A<8>
MEM_B_A<9>
MEM_B_A<12>
MEM_B_BS<2>
MEM_CKE<2>
MEM_B_DQ<25>
MEM_B_DQ<24>
MEM_B_DQ<29>
MEM_B_DQ<23>
MEM_B_DQS_P<2>
MEM_B_DQS_N<2>
MEM_B_DQ<21>
MEM_B_DQS_N<0>
MEM_B_DQ<14>
MEM_B_DM<1>
MEM_B_DQ<15>
PP3V3_S0
SMBUS_SB_SCL
SMBUS_SB_SDA
MEM_B_DQ<48>
MEM_B_DQ<53>
MEM_B_DQ<50>
SODIMM_A_SA1
PP3V3_S0
MEMVREF_OUT
MEM_B_DQ<18>
PP1V8_S3
82D5
82D5
82C6
82C6
82B3
82B3
82A4
82A4
79D3
79D3
79A8
79A8
71D2
71D2
67C5
67C5
67C3
67C3
67B3
67B3
67A3
67A3
66B6
66B6
66B5
66B5
66B1
66B1
65D6
65D6
65B3
65B3
62A6
62A6
61D8
61D8
61A5
61A5
60D4
60D4
60C7
60C7
58C7
58C7
58C4
58C4
57B6
57B6
54D4
54D4
54B5
54B5
52D3
52D3
49C7
49C7
49C4
49C4
49B5
49B5
40B6
40B6
36D6
36D6
34A8
34A8
33D8
33D8
33D3
33D3
33C7
33C7
29A3
29A6
28A6
28A6
27D8
27D8
27D5
27D5
27D3
27D3
27C3
27C3
26D1
26D1
26B8
26B8
26B6
26B6
26B4
26B4
25D8
25D8
25D3
25D3
25C6
25C6
25C4
25C4
25B8
25B8
25B4
25B4
25A4
25A4
24D3
24D3
24C3
24C3
67B8 67B8
24B5
24B5
67B8
67B6 67B6
24B3
24B3
67B6
64C1 64C1
23D5
23D5
64C1
64A6 64A6
23B3
23B3
64A6
37B2 37B2
22B5
22B5
37B2
32C6 32C6
21D3
81C3
21D3
32C6
31C5
31C5
21C3
48B3
21C3
31C5
29D6 29D3
20B4
46B6
20B4
29D6
29B2 29B2
20A4
33B6
20A4
29D3
28D6 28D6
19C7
28A6
19C7
28D6
28D3 28D3
19C6
27D8
19C6
28D3
28B2 28B2
17C6
27D7
17C6
28B2
19D7 19D7
52D5
14D6
27D6
14D6
19D7
16B6 16B6
52D3
14C7
27C6
14C7
32B4
16B6
14C2 14C2
51B7
10C5
27B6
10C5
32B3
14C2
5D4 5D4
28C3
30B6
30D6
30A6
30B6
30B6
30B6
30B6
30B6
30B6
30B6
30C6
30D6
30A6
30C6
30D6
30A6
30A6
30A6
30B6
30B6
30B6
30B6
30B6
30B6
30A6
30D6
5D4
23D5
5D4
28D6
5D4
15D4
14D4
15D4
5B2
15C4
5B2
15C4
6D7
15C4
15C4
15C4
15D4
15D4
15D4
15D4
15D4
15D4
14D4
15D2
15C4
15C4
15C2
15C2
15C4
14B7
15C2
15C4
15B4
15B4
15A4
15A4
14D4
15C2
15B4 15A4
15B4 15A4
15B4
15C2
15C2
15C2
15C2
15B2
14C4
6D7
15C2
15C4
15C4
15C4
15D2
15C2
15C2
15B2
15B2
15B2
15B2
15C2
15C2
15C4
15C4
15C4
15D2
15C4
15C4
15B4
14D4
15B4
15C2
15C2
15B4
15B4
15B4
15B4
15C2
15B4
15B2
14C4
14C4
15B2
15B4
15B4
15B4
15C2
15B4
15B4
15B4
15C2
15B4
15B4
15B4
15B4
15C2
15C2
15C4
15B4
14C4
14C4
15D2
15B2
15D2
15B2
15C2
15B2
15B2
15B2
15B2
15D2
14C4
15C4
15C4
15C4
15C4
15C2
15C2
15C4
15C2
15C4
15D2
15C4
5A4
5B1
15B4
15B4
15B4
5A4
14C2
15C4
5B2
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
One cap for each side of every RPAK, one cap for every two discrete resistors
Ensure CS_L and ODT resistors are close to SO-DIMM connector
0.1uF
CERM
20%
10V
402
C3051
1
2
20%
10V
CERM
402
0.1uF
C3053
1
2
20%
402
10V
CERM
0.1uF
C3052
1
2
402
10V
20%
0.1uF
CERM
C3050
1
2
0.1uF
402
CERM
10V
20%
C3055
1
2
20%
10V
CERM
402
0.1uF
C3057
1
2
0.1uF
402
CERM
10V
20%
C3059
1
2
10V
20%
0.1uF
402
CERM
C3058
1
2
0.1uF
20%
10V
CERM
402
C3056
1
2
20%
10V
CERM
0.1uF
402
C3054
1
2
0
1
2
3
5
4
6
7
8
9
10
11
12
13
0
2
1
15B2 15C2 29B3 29B6 29C3 29C6
15D2 29B3 29B6 29C6
15B2 29B3
15D2 29B6
15B2 29B6
56
1/16W
5%
SM-LF
RP3004
2 7
5%
1/16W
56
SM-LF
RP3001
3 6
SM-LF
5%
1/16W
56
RP3010
2 7
56
5%
1/16W
SM-LF
RP3012
4 5
56
5%
1/16W
SM-LF
RP3012
3 6
SM-LF
56
1/16W
5%
RP3003
4 5
SM-LF
1/16W
5%
56
RP3012
2 7
1/16W
SM-LF
56
5%
RP3001
1 8
5%
1/16W
56
SM-LF
RP3004
1 8
56
1/16W
5%
SM-LF
RP3002
2 7
56
5%
1/16W
SM-LF
RP3006
1 8
56
1/16W
5%
SM-LF
RP3007
1 8
56
1/16W
5%
SM-LF
RP3002
4 5
56
1/16W
SM-LF
5%
RP3010
1 8
5%
SM-LF
1/16W
56
RP3003
1 8
56
5%
1/16W
SM-LF
RP3006
4 5
5%
1/16W
56
SM-LF
RP3005
3 6
56
1/16W
5%
SM-LF
RP3005
4 5
5%
1/16W
56
SM-LF
RP3003
2 7
5%
1/16W
SM-LF
56
RP3006
3 6
5%
1/16W
SM-LF
56
RP3005
2 7
56
SM-LF
1/16W
5%
RP3006
2 7
1/16W
56
5%
SM-LF
RP3002
3 6
5%
1/16W
56
SM-LF
RP3003
3 6
56
5%
1/16W
SM-LF
RP3001
2 7
56
SM-LF
1/16W
5%
RP3004
4 5
5%
SM-LF
1/16W
56
RP3012
1 8
SM-LF
1/16W
5%
56
RP3001
4 5
SM-LF
1/16W
5%
56
RP3005
1 8
SM-LF
56
1/16W
5%
RP3004
3 6
SM-LF
5%
1/16W
56
RP3008
2 7
SM-LF
5%
1/16W
56
RP3002
1 8
56
1/16W
5%
SM-LF
RP3013
4 5
56
5%
1/16W
SM-LF
RP3008
3 6
56
1/16W
5%
SM-LF
RP3008
4 5
56
5%
1/16W
SM-LF
RP3009
1 8
SM-LF
5%
1/16W
56
RP3011
2 7
SM-LF
56
1/16W
5%
RP3011
1 8
SM-LF
1/16W
56
5%
RP3009
2 7
SM-LF
56
1/16W
5%
RP3011
3 6
5%
SM-LF
1/16W
56
RP3008
1 8
1/16W
SM-LF
5%
56
RP3009
3 6
56
5%
1/16W
SM-LF
RP3007
4 5
1/16W
5%
56
SM-LF
RP3013
2 7
SM-LF
56
1/16W
5%
RP3011
4 5
1/16W
5%
56
SM-LF
RP3010
4 5
5%
1/16W
56
SM-LF
RP3009
4 5
SM-LF
5%
1/16W
56
RP3007
2 7
SM-LF
5%
1/16W
56
RP3010
3 6
5%
1/16W
56
SM-LF
RP3013
1 8
56
1/16W
5%
SM-LF
RP3007
3 6
SM-LF
5%
1/16W
56
RP3013
3 6
0
1
0
1
1
0
2
0
1
2
3
4
5
6
7
10
11
9
8
13
12
14C4 28B3 28B6 29B3 29B6
14C4 28C3 28C6 29C3 29C6
15B5 15C5 28B3 28B6 28C3 28C6
15D5 28B3 28B6 28C6
15B5 28B3
15D5 28B6
15B5 28B6
2
3
2
3
0.1uF
402
CERM
10V
20%
C3039
1
2
10V
402
CERM
20%
0.1uF
C3038
1
2
0.1uF
402
CERM
10V
20%
C3033
1
2
0.1uF
CERM
10V
20%
402
C3032
1
2
0.1uF
20%
10V
CERM
402
C3031
1
2
402
10V
20%
0.1uF
CERM
C3030
1
2
CERM
20%
10V
0.1uF
402
C3011
1
2
CERM
10V
20%
402
0.1uF
C3010
1
2
10V
0.1uF
402
CERM
20%
C3007
1
2
0.1uF
20%
10V
CERM
402
C3005
1
2
0.1uF
402
CERM
10V
20%
C3002
1
2
0.1uF
20%
10V
CERM
402
C3000
1
2
20%
10V
CERM
402
0.1uF
C3037
1
2
0.1uF
20%
10V
CERM
402
C3036
1
2
0.1uF
402
CERM
10V
20%
C3035
1
2
0.1uF
20%
10V
CERM
402
C3034
1
2
0
1
2
3
14C4 28B3 28B6 29B3 29B6
051-7164 06004
8730
Memory Active Termination
SYNC_MASTER=(MASTER)
SYNC_DATE=(MASTER)
MEM_B_BS<2..0>
MEM_B_A<13..0>
MEM_ODT<3..0>
MEM_CKE<3..0>
MEM_CS_L<3..0>
MEM_A_BS<2..0>
MEM_A_A<13..0>
PP0V9_S0
MEM_A_WE_L
MEM_B_RAS_L
MEM_A_CAS_L
MEM_A_RAS_L
MEM_B_WE_L
MEM_B_CAS_L
67D8 67D6 66B5 31C2
5D4
VLDOIN
VIN
VTT
VTTSNS
VTTREF
VDDQSNS
S3
S5
PGND
THRML
GND
PAD
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
DDR2 Vtt Regulator
If power inputs are not S0,
MEMVTT_EN can be used to
disable MEMVTT in sleep.
leave 1.8V powered in S3.
Okay to turn off 5V and
(NONE)
(NONE)
Power aliases required by this page:
Signal aliases required by this page:
BOM options provided by this page:
- =PP5V_S0_MEMVTT
- =PP1V8_S0_MEMVTT
- =PP0V9_S0_MEMVTT_LDO
Page Notes
20%
X5R
0.1UF
25V
402
C3102
1
2
MSOP
TPS51100
CRITICAL
U3100
8
4
7
9
11
1
10
2
3
6
5
4.7UF
6.3V
603
CERM
20%
C3104
1
2
10UF
20%
X5R
6.3V
603
C3101
1
2
1K
402
MF-LF
1/16W
5%
MEMVTT_EN_PU
R3100
1
2
22UF
20%
6.3V
X5R
805
C3105
1
2
22UF
20%
6.3V
X5R
805
C3106
1
2
31 87
06004051-7164
Memory Vtt Supply
SYNC_MASTER=M59_MLB
SYNC_DATE=09/15/2006
PP5V_S0
MEMVTT_EN
PP1V8_S3
MEMVTT_VREF
PP0V9_S0
81B3 80B5 80A1 79B8
67B8
71A6
67B6
67B3
64C1
67B1
64A6
67A1
37B2
66B5
32C6
62B1
29D6
61D7
29D3
58C7
29B2
58C4
28D6
57B5
28D3
55A8
28B2
53C4
19D7
67D8
36D6
16B6
67D6
25D8
14C2
66B5
5D4
5D4
30D5
5D2
5B2
5D4
V+
V-
IN
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
CRITICAL
MAX4236EUTT
SOT23-6-LF
U3200
3
4
1
5
6
2
20%
0.1UF
402
10V
CERM
C3200
1
2
CERM
402
220pF
25V
5%
C3205
1
2
10K
1/16W
1%
402
MF-LF
R3206
1
2
10K
MF-LF
402
1%
1/16W
R3205
1
2
100K
MEMVREF_S3
MF-LF
402
5%
1/16W
R3202
1
2
5%
1/16W
MF-LF
402
0
MEMVREF_S0
R3203
12
32 87
06004051-7164
DDR2 VRef
SYNC_MASTER=M59_MLB
SYNC_DATE=09/15/2006
MEMVREF_SHDN_L
PP3V3_S3
PM_SLP_S3_L
MEMVREF_OUT
MEMVREF_OUT
MEMVREF_OUT
MEMVREF_UNBUF
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0.9V
PP1V8_S3
MIN_NECK_WIDTH=0.15 mm
VOLTAGE=0.9V
MIN_LINE_WIDTH=0.2 mm
MAKE_BASE=TRUE
MEMVREF_OUT
81D4
81A5 67C5 67C3 66C6
67B8
65D1
67B6
63B7
64C1
60C2
64A6
59C6
37B2
57D4
31C5
52B1
29D6
46D6
29D3
46C3
29B2
46B3
28D6
41C5
28D3
37D7
28B2
37D5
32B4
32B4
32B4
19D7
37C3
32B3
32B3
32B3
16B6
37A7
29D6
29D6
29D6
14C2
27C5
28D6
28D6
28D6
5D4
5D4
14C2
14C2
14C2
5B2
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
OUT
OUT
OUT
OUT
OUT
OUT
IN
IO
OUT
IN
IO
IO
OUT
OUT
IN
IN
IN
IN
OUT
OUT
IN
OUT
OUT
OUT
OUT
OUT
OUT
IN
VSS_SRC
THRML_PAD
VSS_REF
VSS_PCI
VSS_CPU
VSS_48
NC
SDA
PCIF_1
PCIF_0/ITP_EN
PCI_5/FCT_SEL_1
PCI_4
PCI_3
PCI_2
PCI_1
FS_B_TEST_MODE
REF_1/FCT_SEL_0
REF_0/FS_C/TEST_SEL
48M/FS_A
VTT_PWRGD*/PD
VDD_A
VSS_A
XTAL_IN
XTAL_OUT
CLKREQ_8*
CLKREQ_6*
CLKREQ_5*
CLKREQ_4*
CLKREQ_3*
CLKREQ_1*
CPU_STOP*
PCI_STOP*
VDD_CPU
VDD_48
SCL
CPU_0*
CPU_0
CPU_1
CPU_1*
CPU_ITP/SRC_11*
CPU_ITP/SRC_11
SRC_0/LCD_CLK
SRC_0/LCD_CLK*
SRC_1
SRC_1*
SRC_2*
SRC_2
SRC_3
SRC_3*
SRC_4
SRC_4*
SRC_5*
SRC_5
SRC_7*
SRC_7
SRC_8*
SRC_6*
SRC_6
SRC_8
DOT_96*/27M_SS*
DOT_96/27M
VDD_SRC
VDD_REF
VDD_PCI
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
(FW PCI 33MHZ)
(FOR PCI-E CARD)
NEED TO CHECK CAP VALUE
(ICH7M USB 48MHZ)
(FROM CPU VCORE PWR GOOD)
(GMCH D_REFCLKIN DISPLAY PLL A 96MHZ)
(WIRELESS PCI-E 100 MHZ )
(FROM GMCH CLK_REQ*)
(FROM ICH7 GPIO35)
(ICH7M DMI 100 MHZ )
NEED TO DECIDE THE CLKREQ CONNECTION,TO GPIO?
(GPU PCI-E 100 MHZ )
(INT PU)
(INT PU)
(EACH POWER PIN PLACED ONE 0.1UF)
(SMC LPC 33MHZ)
(TPM LPC 33MHZ)
(ICH SATA 100 MHZ)
FCTSEL0
SRCC0
SRCC0
SRCC0
SRCT0
TBD
SPREAD
27M
11
1
10
0 0
FCTSEL1
100MC_SST
PIN 11
PIN 7
DOT96C
SRCT0
SRCT0
* FOR INT. GRAPHIC SYSTEM
PIN 6
(INT PU)
(INT PD)
(INT PD)
(CPU HOST 133/167MHZ)
(GMCH D_REFSSCLKIN DISPLAY PLL B 100MHZ)
(ITP HOST 133/167MHZ)
(FROM ICH7 GPIO20 STPCPU* )
(FROM ICH7 GPIO18 STPPCI* )
(GMCH G_CLKIN 100 MHZ )
(INT PD)
(ICH7M,SIO,LPC REF. 14.318MHZ)
(INT PU)
0
(ICH7M PCI 33MHZ)
(ICH SM BUS)
(PULL UP PIN 68 TO ENABLE ITP HOST CLK)
(NO USED)
(PORT80 LPC 33MHZ)
(PLACED 0.1UF NEAR THE RELATIVE POWER PIN)
OFF LOW
SPREAD
27M NON
DOT96T
DOT96T
DOT96C 100MT_SST
PIN 10
* FOR EXT. GRAPHIC SYSTEM
(GMCH HOST 133/167MHZ)
(INT PU)
(INT PU)
(INT PU)
(INT PU)
(GIGA LAN PCI-E 100 MHZ )
(NB CRT/TV GRAPHICS DOTCLK 100MHZ)
6.3V
20%
10UF
X5R
603
C3309
1
2
402
16V
X5R
10%
0.1UF
C3305
1
2
0.1UF
10%
402
X5R
16V
C3306
1
2
402
10%
0.1UF
X5R
16V
C3307
1
2
X5R
16V
402
10%
0.1UF
C3308
1
2
NO STUFF
1/16W
402
475
1%
MF-LF
R3300
1
2
603
X5R
6.3V
10UF
20%
C3312
1
2
10%
X5R
402
0.1UF
16V
C3311
1
2
402
10%
16V
X5R
0.1UF
C3304
1
2
X5R
16V
402
0.1UF
10%
C3303
1
2
0.1UF
10%
16V
X5R
402
C3302
1
2
402
X5R
16V
0.1UF
10%
C3301
1
2
402
10%
CERM
6.3V
1UF
C3310
1
2
10UF
6.3V
20%
X5R
603
C3316
1
2
10%
X5R
16V
402
0.1UF
C3315
1
2
402
6.3V
CERM
10%
1UF
C3314
1
2
1
MF-LF
5%
1/16W
402
R3303
1 2
X5R
10UF
20%
6.3V
603
C3317
1
2
1/16W
402
MF-LF
5%
10K
R3301
1
2
14.31818
5X3.2-SM
CRITICAL
Y3301
1 2
CRITICAL
SLG8LP436
QFN
OMIT
U3301
4
9
59
20
60
25
34
45
44
42
41
37
36
55
6
7
8
40
57
58
63
64
65
56
68
1
54
53
47
48
10
11
13
14
15
16
18
19
21
22
23
24
26
27
29
30
33
32
69
33843616749121728
35
5
39
46
62
66
52
31
2
51
50
0402-LF
FERR-120-OHM-1.5A
L3302
1 2
0402-LF
FERR-120-OHM-1.5A
L3301
1 2
12PF
402
CERM
5%
50V
C3389
1
2
12PF
5%
CERM
402
50V
C3390
1
2
SYNC_DATE=09/15/2006
SYNC_MASTER=M59_MLB
CLOCKS
8733
051-7164 06004
PP3V3_S0_CK410_VDD_CPU_SRC_A
MIN_NECK_WIDTH=0.2mm
MIN_LINE_WIDTH=0.5mm
VOLTAGE=3.3V
PP3V3_S0
PP3V3_S0
PP3V3_S0_CK410_VDD48_PCI
VOLTAGE=3.3V
MIN_NECK_WIDTH=0.2mm
MIN_LINE_WIDTH=0.5mm
SMBUS_SB_SCL
SMBUS_SB_SDA
CK410_PCI2_CLK
CK410_IREF
CK410_PCI1_CLK
CK410_PCIF0_CLK
CK410_PCI5_FCTSEL1
PCIE_CLK100M_EXCARD_P
PCIE_CLK100M_EXCARD_N
FSB_CLK_CPU_P
CK410_SRC_CLKREQ8_L
CK410_27M_SPREAD
CK410_REF1_FCTSEL0
FSB_CLK_CPU_N
FSB_CLK_NB_P
MIN_NECK_WIDTH=0.2mm
MIN_LINE_WIDTH=0.5mm
VOLTAGE=3.3V
PP3V3_S0_CK410_VDD_REF
PM_STPPCI_L
PM_STPCPU_L
FSB_CLK_NB_N
CPU_XDP_CLK_N
CPU_XDP_CLK_P
NB_CLK_DREFSSCLKIN_N
NB_CLK_DREFSSCLKIN_P
PEG_CLK100M_GPU_N
PEG_CLK100M_GPU_P
CK410_SRC_CLKREQ1_L
SB_CLK100M_DMI_N
SB_CLK100M_DMI_P
EXCARD_CLKREQ_L
SB_CLK100M_SATA_N
SB_CLK100M_SATA_P
SB_CLK100M_SATA_OE_L
NB_CLK100M_GCLKIN_N
NB_CLK100M_GCLKIN_P
CLK_NB_OE_L
PCIE_CLK100M_MINI_P
PCIE_CLK100M_MINI_N
MINI_CLKREQ_L
CK410_SRC7_N
CK410_SRC7_P
ENET_CLK100M_PCIE_N
ENET_CLK100M_PCIE_P
CK410_27M_NONSPREAD
VR_PWRGD_CK410_L
CK410_USB48_FSA
CK410_CLK14P3M_TIMER
CK410_FSB_TEST_MODE
CK410_PCI3_CLK
TP_CK410_PCI4_CLK
CK410_PCIF1_CLK
PP3V3_S0
CK410_XTAL_OUT
CK410_XTAL_IN
82D5
82D5
82D5
82C6
82C6
82C6
82B3
82B3
82B3
82A4
82A4
82A4
79D3
79D3
79D3
79A8
79A8
79A8
71D2
71D2
71D2
67C5
67C5
67C5
67C3
67C3
67C3
67B3
67B3
67B3
67A3
67A3
67A3
66B6
66B6
66B6
66B5
66B5
66B5
66B1
66B1
66B1
65D6
65D6
65D6
65B3
65B3
65B3
62A6
62A6
62A6
61D8
61D8
61D8
61A5
61A5
61A5
60D4
60D4
60D4
60C7
60C7
60C7
58C7
58C7
58C7
58C4
58C4
58C4
57B6
57B6
57B6
54D4
54D4
54D4
54B5
54B5
54B5
52D3
52D3
52D3
49C7
49C7
49C7
49C4
49C4
49C4
49B5
49B5
49B5
40B6
40B6
40B6
36D6
36D6
36D6
34A8
34A8
34A8
33D3
33D8
33D8
33C7
33C7
33D3
29A6
29A6
29A6
29A3
29A3
29A3
28A6
28A6
28A6
27D8
27D8
27D8
27D5
27D5
27D5
27D3
27D3
27D3
27C3
27C3
27C3
26D1
26D1
26D1
26B8
26B8
26B8
26B6
26B6
26B6
26B4
26B4
26B4
25D8
25D8
25D8
25D3
25D3
25D3
25C6
25C6
25C6
25C4
25C4
25C4
25B8
25B8
25B8
25B4
25B4
25B4
25A4
25A4
25A4
24D3
24D3
24D3
24C3
24C3
24C3
24B5
24B5
24B5
24B3
24B3
24B3
23D5
23D5
23D5
23B3
23B3
23B3
22B5
22B5
22B5
21D3
21D3
81C3
81C3
21D3
21C3
21C3
48B3
48B3
21C3
20B4
20B4
46B6
46B6
20B4
20A4
20A4
29A6
29A6
20A4
19C7
19C7
28A6
28A6
19C7
19C6
19C6
27D8
27D8
19C6
17C6
17C6
27D7
27D7
17C6
14D6
14D6
27D6
27D6
14D6
14C7
14C7
27C6
27C6
48B6
48B6
34D5
34D5
34D5
34D5
87C6
34B5
34B5
34C5
34C5
34C5
34C5
48C6
48C6
14C7
10C5
10C5
27B6
27B6
34C5
34B5
34D3
34D3
34D3
34D3
34D5
34B4
34B4
70A5
70A5
34C5
34C5
34C3
34C3
34C4
34C4
34D5
34D5
39C6
39C6
61C7
10C5
5D4
5D4
23D5
23D5
34C3
34B3
7C6
7C6
12A6
23C8
23C8
12A6
34D3
14C4
14B4
34B5
34B5
34C3
34C3
21B6
21B6
14C4
14C4
14B6
34D4
34D4
34C5
34C5
26A8
34D8
5D4
5A4
5A4
5B1
5B1
34D8
34D8
34A8
5B1
5B1
5C4
34A4
34B5
34A8
5C4
5C4
5A4
5B4
5B4
5B4
11B3
5B4
5B4
34B4
34B4
34A4
22C2
22C2
5A7
5A7
23C3
5B4
5B4
5B4
5B1
5B1
34B5
34B5
34C3
34C3
34B5
26A7
34C8
34B8
34B8
34D6
5A4
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
IN
IN
IN
IN
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
OUT
IN
OUT
OUT
OUTOUT
OUT
IO
IO
OUT
IN
OUT
OUT
IN
IN
IN
IN
IN
OUT
OUT
IN
OUT
IN
IN
IN
OUT
OUT
OUT
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
OUT
OUT
OUT
IN
IN
IN
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
(NB LVDS GRAPHICS 100MHZ)
(NB CRT/TV GRAPHICS DOTCLK 100MHZ)
Yukon CLK OE*
GPU CLK OE*
(CPU HOST 133/167MHZ)
(ICH7M SATA 100MHZ)
166M
200M
(GPU 27MHz Spread / Non-Spread)
(Yukon PCI-E 100MHZ)
0
FS_B
CPU
FS_C
0
0 0
0
0
0 0
0
0
1
1
1
1 1
1 1
1 1 1
100M
333M
0
0
1#
#
133M
266M
(GMCH G_CLKIN 100MHZ)
(ICH7M DMI 100MHZ)
NOSTUFF R3450,R3451,R3453 FOR MANUAL CPU FREQUENCY
(ExpressCard Slot)
(GMCH HOST 133/167MHZ)
(ITP HOST 133/167MHZ)
(WIRELESS PCI-E MINI 100MHZ)
FS_A
1
400M
RESERVED
# NAPA PLATFORM ONLY SUPPORT 133M/166M CPU SPEED
(GPU PCI-E Graphics 100MHz)
(FROM CPU FS_A)
(FROM CPU FS_B)
(TO MCH FS_B)
NEED TO CHECK THE BSEL PULLS
(TO MCH FS_A)
(FROM CPU FS_C)
(ICH7M 14.318MHZ)
(TO MCH FS_C)
PLACEMENT of these
caps should be close
as possible to the resistors
(TO FIREWIRE PCI 33MHZ)
(TO TPM PCI 33MHZ)
(TO SMC PCI 33MHZ)
(TO ICH7M PCI 33MHZ)
(PORT80 LPC 33MHZ)
(TO ICH7M USB 48MHZ)
33A4 34C5 39C6
33A4 34C5 39C6
22C2 33B4 34C5
MF-LF
33
402
5%
1/16W
R3429
1 2
1/16W
5%
402
MF-LF
33
TPM
R3430
1 2
33
MF-LF
402
5%
1/16W
R3433
1 2
33
1/16W
402
5%
MF-LF
R3432
1 2
37B6
60C6
51C7
22A6
5C2
53C5
402
33
MF-LF
5%
1/16W
R3463
1 2
22C2 33B4 34C5
5%
MF-LF
10K
402
1/16W
R3467
1
2
1/16W
5%
402
MF-LF
10K
R3466
1
2
MF-LF
1/16W
5%
402
1K
R3469
1
2
1/16W
5%
402
MF-LF
1K
R3468
1 2
1/16W
5%
402
MF-LF
1K
R3472
1 2
1/16W
5%
402
MF-LF
1K
R3470
1
2
1/16W
5%
402
MF-LF
1K
R3471
1 2
1/16W
5%
402
MF-LF
1K
R3473
1
2
1/16W
5%
402
MF-LF
1K
R3475
1 2
1/16W
5%
402
MF-LF
1K
R3474
1 2
23D3
5A7
21B6 33B4 34C5
5A7
21B6 33B4 34C5
NOSTUFF
1/16W
5%
MF-LF
1K
402
R3480
1
2
1/16W
5%
402
MF-LF
33
R3476
1 2
1/16W
5%
402
MF-LF
0
R3450
1 2
1/16W
5%
402
MF-LF
0
R3453
1 2
1/16W
5%
402
MF-LF
1K
NOSTUFF
R3454
1
2
1/16W
5%
402
MF-LF
0
R3451
1 2
NOSTUFF
1/16W
5%
402
1K
MF-LF
R3452
1
2
5B1
33B4 34C5 48B6
5B1
33B4 34B5 48B6
5C4
12A6 33C4 34D5
5B4
12A6 33C4 34D5
5C4 7C6
33C4 34D5
5%
1K
1/16W
402
MF-LF
R3486
1 2
5%
1K
MF-LF
1/16W
402
R3485
1 2
5C4 7C6
33C4 34D5
11B3 33C4 34D5 87C6
11B3 33C4 34D5 87C6
MF-LF
402
1/16W
0
5%
R3424
1 2
5%
0
1/16W
402
MF-LF
R3425
1 2
1/16W
5%
0
402
MF-LF
NO STUFF
R3443
1 2
NO STUFF
5%
1/16W
MF-LF
402
0
R3444
1 2
1%
71.5
1/16W
402
MF-LF
NO STUFF
R3402
1 2
1%
71.5
1/16W
402
MF-LF
R3405
1 2
1%
121
MF-LF
402
1/16W
R3418
1 2
56
5%
1/16W
402
MF-LF
R3419
1 2
MF-LF
5%
1/16W
402
100K
NO STUFF
R3426
1
2
NOSTUFF
5%
15PF
402
CERM
50V
C3404
1
2
NOSTUFF
5%
15PF
50V
CERM
402
C3403
1
2
NOSTUFF
5%
15PF
50V
CERM
402
C3402
1
2
NOSTUFF
5%
15PF
CERM
402
50V
C3401
1
2
NOSTUFF
15PF
5%
50V
CERM
402
C3400
1
2
1/16W
5%
402
MF-LF
33
R3417
1 2
1/16W
5%
402
MF-LF
2.2K
R3401
1 2
051-7164 06004
8734
SYNC_MASTER=M59_MLB
SYNC_DATE=09/15/2006
Clock Termination
PCI_CLK_SMC
PCI_CLK_TPM
PCI_CLK_FW
PCI_CLK_SB
PCI_CLK_PORT80_LPC
MAKE_BASE=TRUE
TP_CK410_PCI4_CLK
NB_BSEL<0>
SB_CLK14P3M_TIMER
CK410_FSB_TEST_MODE
NB_BSEL<2>
CPU_BSEL<2>
NB_BSEL<1>
CPU_BSEL<1>
CPU_BSEL<0>
SB_CLK48M_USBCTLR
CK410_CLK14P3M_TIMER
CPU_BSEL_R<2>
CPU_BSEL_R<1>
CPU_BSEL_R<0>
CK410_USB48_FSA
PP1V05_S0
PP1V05_S0
PP1V05_S0
CK410_PCI3_CLK
TP_CK410_PCI4_CLK
CK410_PCI2_CLK
CK410_PCI1_CLK
CK410_PCIF1_CLK
CK410_PCIF0_CLK
NB_CLK100M_GCLKIN_N
PP1V5_S0_NB_VCCA_DPLLA
NB_CLK_DREFCLKIN_P
NB_CLK_DREFCLKIN_P
CK410_SRC7_N
CK410_SRC7_P
NB_CLK_DREFCLKIN_N
SB_CLK100M_SATA_P
FSB_CLK_NB_N
MAKE_BASE=TRUE
SB_CLK100M_SATA_P
MAKE_BASE=TRUE
FSB_CLK_NB_N
SB_CLK100M_SATA_N
MAKE_BASE=TRUE
SB_CLK100M_SATA_N
MAKE_BASE=TRUE
PCIE_CLK100M_MINI_NPCIE_CLK100M_MINI_N
MAKE_BASE=TRUE
SB_CLK100M_DMI_NSB_CLK100M_DMI_N
MAKE_BASE=TRUE
NB_CLK_DREFSSCLKIN_PNB_CLK_DREFSSCLKIN_P
NB_CLK_DREFSSCLKIN_N
MAKE_BASE=TRUE
NB_CLK_DREFSSCLKIN_N
PEG_CLK100M_GPU_N
MAKE_BASE=TRUE
PEG_CLK100M_GPU_N
MAKE_BASE=TRUE
PEG_CLK100M_GPU_P
MAKE_BASE=TRUE
PCIE_CLK100M_EXCARD_NPCIE_CLK100M_EXCARD_N
MAKE_BASE=TRUE
PCIE_CLK100M_EXCARD_PPCIE_CLK100M_EXCARD_P
MAKE_BASE=TRUE
ENET_CLK100M_PCIE_NENET_CLK100M_PCIE_N
MAKE_BASE=TRUE
ENET_CLK100M_PCIE_PENET_CLK100M_PCIE_P
MAKE_BASE=TRUE
SB_CLK100M_DMI_PSB_CLK100M_DMI_P
MAKE_BASE=TRUE
NB_CLK100M_GCLKIN_N
MAKE_BASE=TRUE
NB_CLK100M_GCLKIN_PNB_CLK100M_GCLKIN_P
MAKE_BASE=TRUE
PCIE_CLK100M_MINI_PPCIE_CLK100M_MINI_P
MAKE_BASE=TRUE
CPU_XDP_CLK_NCPU_XDP_CLK_N
MAKE_BASE=TRUE
CPU_XDP_CLK_PCPU_XDP_CLK_P
MAKE_BASE=TRUE
FSB_CLK_NB_PFSB_CLK_NB_P
MAKE_BASE=TRUE
FSB_CLK_CPU_NFSB_CLK_CPU_N
MAKE_BASE=TRUE
FSB_CLK_CPU_PFSB_CLK_CPU_P
PEG_CLK100M_GPU_P
CK410_PCI5_FCTSEL1
CK410_REF1_FCTSEL0
PP3V3_S0
CK410_27M_NONSPREAD
MAKE_BASE=TRUE
CK410_27M_SPREAD
MAKE_BASE=TRUE
EXCARD_CLKREQ_L
MAKE_BASE=TRUE
EXCARD_CLKREQ_L
MINI_CLKREQ_L
MAKE_BASE=TRUE
MINI_CLKREQ_L
CK410_SRC_CLKREQ8_L
CK410_SRC_CLKREQ1_L
NB_CLK_DREFCLKIN_N
CK410_27M_SPREAD
GPU_CLK27MSS_IN
CK410_27M_NONSPREAD
GPU_CLK27M GPU_CLK27M
GPU_CLK27MSS_IN
82D5 82C6 82B3 82A4 79D3 79A8
71D2 67C5 67C3 67B3 67A3 66B6
66B5 66B1 65D6 65B3 62A6 61D8
61A5 60D4 60C7 58C7 58C4 57B6
54D4 54B5 52D3 49C7 49C4 49B5
40B6 36D6 33D8 33D3 33C7 29A6
29A3 28A6
67D8
67D8
67D8
27D8
67D6
67D6
67D6
27D5
65A2
65A2
65A2
27D3
55A4
55A4
55A4
27C3
34C8
34C6
34C8
26D1
34C6
34B8
34B8
26B8
25D3
25D3
25D3
26B6
25C4
25C4
25C4
26B4
24D3
24D3
24D3
25D8
24C3
24C3
24C3
25D3
21C1
21C1
21C1
25C6
19D7
19D7
19D7
25C4
19D6
19D6
19D6
25B8
19D5
19D5
19D5
25B4
19D2
19D2
19D2
25A4
19D1
19D1
19D1
24D3
19C8
19C8
19C8
24C3
17D6
17D6
17D6
24B5
17D3
17D3
17D3
24B3
16D3
16D3
16D3
23D5
16C8
16C8
16C8
23B3
13B5
13B5
13B5
22B5
12C2
12C2
12C2
21D3
12B7
12B7
12B7
21C3
12A7
12A7
12A7
20B4
11C5
11C5
11C5
20A4
11B3
11B3
11B3
19C7
9B7
9B7
9B7
19C6
8C7
8C7
8C7
17C6
7D5
7D5
7D5
34C4
34C3
34D3
34C3
48C6 48C6
34B5 34B4
34B5 34B4
48B6
48B6
34C5
34C5 34C4
48C6 48C6
87C6
87C6
34D3
34D3
34D3
14D6
7B6
7B6
7B6
33B4
33B4
33C4
33B4
34D5 34D4
34C3
33B4 33B4
33B4 33B4
70A5 70A5
70A5
34B3
34C3
39C6
39C6
34C3
33B4
33B4 33B4
34D5 34D4
34D3
34D3
33C4
33C4
33C4
70A5
14C7
48C3 48C3
48C3 48C3
77C3
77A5
77A5
77C3
7B5
7B5
7B5
34D6
14C4
34B4
34B2
34B2
21B6
12A6
21B6
33B4 33B4
33B4
14B4 14B4
14C4 14C4
34B4 34B5
34B5
33B4
33B4
34C3
34C3
33B4
14C4
14C4 14C4
33B4 33B4
33C4
33C4
12A6
7C6
7C6
34B4
10C5
34A4 34A3
34A4 34A3
34B4
74C8
74C2
74C2
74C8
34D8
5D4
5D4
5D4
33B6
5B4
19A6
14C4
14C4
14C4
5A7
5B4
5A7
5B1 5B1
22C2
5B4 5B4
5B4 5B4
33B4 33B4
33B4
5B1
5B1
33A4
33A4
22C2
5B4
5B4 5B4
5B1 5B1
11B3
11B3
5C4
5C4
5C4
33B4
5D4
34B5
34B5
33B4 33B4
33B4 33B4
14C4
34B5 74C5
34B5 74C1
74C1
74C5
33B6
14C6
33C6
14C6
7B4
14C6
7B4
7B4
23D3
33A4
33A4
5B2
5B2
5B2
33B6
33B6
33B6
33B6
33B7
17C6
5B4
5B4
33B4
33B4
5B4
33B6
33A4
5A4
33A4
33A4
5C1 5C1
5C1 5C1
33A4
33B4
5B4
33A4 34B2
33A4 34B2
34B4
34B4
NC7
NC6
NC5
NC4
NC2
NC3
OUT
VDD
NC0
NC1
VIO
GND
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
NC
NC
TPM Crystal Circuit
SMC G3Hot Oscillator
NC
NC
NC
NC
NC
NC
NC
NC
TPM
32.768K
CRITICAL
SM-2
Y3720
2 4
1 3
TPM
MF-LF
1/16W
0
402
5%
R3721
1 2
10M
NO STUFF
MF-LF
402
5%
1/16W
R3720
1
2
32.768KHZ-9-3.6V
CRITICAL
SG-3040LC-SM
U3750
6
2
3
4
5
8
9
10
11
7
12
1
0.1uF
20%
402
CERM
10V
C3751
1
2
FERR-EMI-100-OHM
SM
L3750
1 2
6.3V
603
CERM
20%
4.7uF
C3750
1
2
402
22
MF-LF
1/16W
5%
R3750
1 2
TPM
5%
402
CERM
50V
15pF
C3720
1 2
TPM
50V
5%
402
CERM
15pF
C3721
1 2
35 87
06004051-7164
SYNC_MASTER=M59_MLB
SYNC_DATE=09/15/2006
Mobile Clocking
SMC_CLK32K_SUSCLK
MAKE_BASE=TRUE
SMC_CLK32K_SUSCLK
MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.2 mm
PP3V42_G3H_SMC_CLK_F
VOLTAGE=3.425V
TPM_XTALO
PP3V42_G3H
SMC_CLK32K_SUSCLK_R
TPM_XTALO_R
TPM_XTALI
81D4 69C8
69B8 69A8 68B8 67D5 67D3 66D2 66C8 66A8 53C4 52D7
52B7 52B5 52B1 51D4 51D3 51C2 47B5 27C3
51C5
51C5
26D6
35B3 35B2
60C6
5D2
60C6
IN
IO
IO
IO
IO
IO
IN
IO
IO
IO
IN
IN
IN
IN
OUT
G
D
S
IN
IO
IO
IO
IO
IO
IO
IO
IO
IN
OUT
OUT
IN
OUT
IN
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
ODD to keep SB GPIO <= 3.3V
Counters 10K pull-up to 5V in
(UATA_CS0*)
(UATA_HSTROBE)
(UATA_DSTROBE)
NC
(UATA_CS1*)
from ball of SB
Place within 12.7mm
Placement note
(UATA_STOP)
IDE (ODD) Connector
516S0335
Indicates disk presence
5%
MF-LF
402
100
1/16W
R3850
1
2
CRITICAL
M-ST-SM1-LF
J3800
1
10
11
12
13
14
15
16
17
18
19
2
20
21
22
23
24
25 26
27
28
29
3
30
31
32
33
34
35
36
37
38
39
4
40
41
42
43
44
45
46
47
48
49
5
50
6
7
8
9
402
MF-LF
1/16W
24.9
1%
R3860
1
2
5%
4.7K
NO STUFF
MF-LF
402
1/16W
R3801
1
2
1/16W
5%
MF-LF
4.7K
402
R3802
1
2
1/16W
5%
402
MF-LF
6.2K
R3803
1
2
1/16W
5%
402
MF-LF
33K
R3810
1
2
FDZ293P
CRITICAL
BGA
Q3820
C1
C2
C3
A1
A2
A3
B1
B2
B3
10K
MF-LF
402
5%
1/16W
R3820
1
2
20%
6.3V
X5R
402
0.22uF
C3821
1 2
1/16W
5%
402
MF-LF
10K
R3821
1
2
15K
5%
402
MF-LF
1/16W
R3811
1
2
051-7164 06004
36 87
PATA Connector
SYNC_MASTER=(MASTER)
SYNC_DATE=(MASTER)
PP3V3_S0
IDE_PDIOW_L
SMC_ODD_DETECT
PP5V_S0_IDE_ODD
VOLTAGE=5V
MIN_NECK_WIDTH=0.4 mm
MIN_LINE_WIDTH=0.6 mm
IDE_PDDREQ
IDE_PDIOR_L
IDE_PDIORDY
IDE_PDD<3>
IDE_IRQ14
ODD_PWR_EN_L_RC
IDE_PDD<0>
PP5V_S0
IDE_PDD<13>
ODD_PWR_EN_L
MAKE_BASE=TRUE
SATA_RBIAS
MAKE_BASE=TRUE
TP_SATA_A_R2DN
MAKE_BASE=TRUE
TP_SATA_A_D2RNTP_SATA_A_D2RN
MAKE_BASE=TRUE
TP_SATA_A_D2RPTP_SATA_A_D2RP
MAKE_BASE=TRUE
TP_SATA_A_R2DPTP_SATA_A_R2DP
SATA_C_DET_L
TP_SATA_A_R2DN
IDE_PDD<4>
IDE_PDCS3_L
IDE_PDA<1>
IDE_PDDACK_L
IDE_PDD<15>
IDE_PDD<14>
IDE_PDD<11>
IDE_PDD<10>
IDE_PDD<9>
IDE_PDD<8>
IDE_PDD<1>
IDE_PDD<2>
IDE_PDD<5>
IDE_PDD<6>
IDE_PDD<7>
IDE_PDA<0>
IDE_PDCS1_L
IDE_PDA<2>
SATA_RBIAS
SATA_RBIAS
IDE_PDD<12>
IDE_RESET_L
82D5 82C6 82B3 82A4 79D3 79A8
71D2 67C5 67C3 67B3 67A3 66B6 66B5 66B1 65D6
65B3 62A6 61D8 61A5 60D4 60C7 58C7 58C4 57B6
54D4 54B5 52D3 49C7 49C4 49B5 40B6 34A8 33D8
33D3 33C7 29A6 29A3 28A6 27D8 27D5 27D3 27C3 26D1
26B8 26B6 26B4 25D8 25D3 25C6 25C4 25B8 25B4
25A4
81B3
24D3
80B5
24C3
80A1
24B5
79B8
24B3
71A6
23D5
67B3
23B3
67B1
22B5
67A1
21D3
66B5
21C3
62B1
20B4
61D7
20A4
58C7
19C7
58C4
19C6
57B5
17C6
55A8
14D6
53C4
14C7
31C5
10C5
25D8
36A5
36A5
5D4
5D4
36A5
36A5
36A5 36A4
36A5 36A4
36A5 36A4
36A4
36A4
36A4
5A4
21B6
51B7
21B6
21B6
21B6
21B5
21B6
21C5
5D2
21B5
22A6
21B6
21B6
21B6 21B6
21B6 21B6
21B6 21B6
23D2
21B6
21B5
21B5
21B5
21B6
21B5
21B5
21B5
21B5
21B5
21B5
21B5
21B5
21B5
21B5
21B5
21B5
21B5
21B5
21B6
21B6
21B5
23C3
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
OUT
OUT
IN
IN
IN
IN
OUT
IO
IO
IO
IO
IO
IO
OUT
IN
IN
IO
IO
OUT
OUT
SDA
SCL
PCI_AD19
PCI_AD18
PCI_AD17
PCI_AD16
PCI_AD15
PCI_AD14
PCI_AD13
PCI_AD12
PCI_AD11
PCI_AD10
PCI_AD31
PCI_AD30
PCI_AD28
PCI_AD29
PCI_AD27
PCI_AD25
PCI_AD26
PCI_AD24
PCI_AD23
PCI_AD21
PCI_AD20
PCI_AD9
PCI_AD8
PCI_AD7
PCI_AD6
PCI_AD5
PCI_AD4
PCI_AD3
PCI_AD2
PCI_PAR
PCI_CLK
PCI_IDSEL
GND
PCI_AD1
PCI_AD0
VCC
MFUNC
G_RST_L
REG18_1
REG18_0
REG_EN_L
PHY_PINT
PHY_PCLK
PHY_LREQ
PHY_LPS
PHY_LINKON
PHY_LCLK
PHY_D7
PHY_D6
PHY_D5
PHY_D4
PHY_D3
PHY_D1-D1
PHY_D2
PHY_D0-D0
PHY_CTL1-CTL1
PHY_CTL0-CTL0
PCI_ACK64_L
PCI_TRDY_L
PCI_STOP_L
PCI_SERR_L
PCI_RST_L
PCI_REQ64_L
PCI_REQ_L
PCI_PME_L
PCI_PERR_L
PCI_IRDY_L
PCI_INTA_L
PCI_GNT_L
PCI_FRAME_L
PCI_DEVSEL_L
VCCP
PCI_AD22
PCI_C_BE2_L
PCI_C_BE0_L
PCI_C_BE3_L
PCI_C_BE1_L
IN
D
S
G
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
RC Reset Option
From PCI clock generator via 33 Ohms
Gated Platform Reset Option
THIS IS FROM ICH-7M
G_RST* assertion min 2ms
(OK if VCCP and VCC are
It must not be taken high
aliased to the same rail)
G_RST* is clamped to VCCP
when there’s no power on VCCP
Might use
MFUNC as a
GPIO
X5R
10V
1uF
10%
402
C3908
1
2
10%
1uF
X5R
402
10V
C3909
1
2
10V
402
X5R
1uF
10%
C3904
1
2
1uF
10%
X5R
402
10V
C3903
1
2
402
X5R
10%
1uF
10V
C3902
1
2
402
X5R
10V
1uF
10%
C3901
1
2
1uF
402
10V
X5R
10%
C3900
1
2
4.7K
5%
1/16W
MF-LF
402
R3902
1
2
1/16W
MF-LF
402
5%
4.7K
R3901
1
2
220
402
MF-LF
1/16W
5%
R3990
1
2
1K
402
MF-LF
1/16W
5%
R3980
1
2
220
5%
1/16W
MF-LF
402
R3991
1
2
10K
5%
1/16W
MF-LF
402
R3910
1
2
1/16W
402
MF-LF
1K
1%
R3904
1 2
10%
10V
1UF
X5R
402
C3977
1
2
0
402
MF-LF
1/16W
5%
R3879
1 2
(2 OF 2)
BGA
CRITICAL
TSB83AA22AZAJ
U3900
E4
C7
C8
F7F8F9
F10
G6G7G8
G9
G10
H6D6H7H8H9
H10
J8
J9
J10
K10
D7E6E7E8E9
E10
F6
A1
N12
L12
N11
N6
M6
M7
K9
K8
M5
K3
N1
L4
M2
M11
M1
L1
J4
H3
H4
J3
H2
G3
H1
F1
N10
F2
G4
M10
K12
M9
N9
L8
M8
N8
M3
K5
K2
D3
N2
L3
E3
L2
B3
K4
N3
L6
F4
J13
F3
D1
L7
L5
J5
F13
F12
E13
E12
C13
B9
B10
C11
B12
A11
B7
B4
A2
D4
B6
A3
G11
G12
C2
C3
C4
D5D8D9E5F5
H11J6J7
J11
E11
F11
10K
1/16W
402
MF-LF
5%
R3977
1
2
50V
10%
0.001uF
402
CERM
C3979
1
2
10K
5%
1/16W
MF-LF
402
R3979
1 2
SOT23-LF
2N7002
Q3970
3
1
2
22
MF-LF
402
5%
1/16W
R3900
1 2
16V
10%
402
X5R
0.1uF
C3910
1
2
402
X5R
16V
10%
0.1uF
C3911
1
2
402
MF-LF
5%
1/16W
100
R3903
1 2
SYNC_DATE=09/15/2006
SYNC_MASTER=M59_MLB
37 87
06004051-7164
FireWire Link (TSB83AA22)
PP3V3_S3
FW_LKON
=FW_PCI_IDSEL
PCI_RST_L
PP3V3_S3
SMC_RSTGATE_RC_L
FW_G_RST_L
FW_G_RST_L_R
PLT_RST_BUF_L
SMC_RSTGATE_L
PCI_C_BE_L<1>
PCI_C_BE_L<2>
PCI_AD<22>
PCI_C_BE_L<3>
PCI_C_BE_L<0>
PP3V3_S3
PCI_DEVSEL_L
PCI_FRAME_L
PCI_GNT3_L
INT_PIRQD_L
PCI_IRDY_L
PCI_PERR_L
PCI_PME_FW_L
PCI_REQ3_L
PCI_REQ64_L
PCI_RST_FW_L
PCI_SERR_L
PCI_STOP_L
PCI_TRDY_L
PCI_ACK64_L
TP_FW_CTL<0>
TP_FW_CTL<1>
TP_FW_DATA<0>
FW_DATA<2>
TP_FW_DATA<1>
FW_DATA<3>
FW_DATA<4>
FW_DATA<5>
FW_DATA<6>
FW_DATA<7>
CLKFW_PHY_LCLK
FW_PHY_LKON
FW_LPS
FW_LREQ
CLKFW_LINK_PCLK
FW_PINT
FW_LLC_PP1V8LDO_EN_L
PP1V8_S3
FW_G_RST_L
FW_MFUNC
PCI_AD<0>
PCI_AD<1>
FW_PCI_IDSEL
PCI_CLK_FW
PCI_PAR
PCI_AD<2>
PCI_AD<3>
PCI_AD<4>
PCI_AD<5>
PCI_AD<6>
PCI_AD<7>
PCI_AD<8>
PCI_AD<9>
PCI_AD<20>
PCI_AD<21>
PCI_AD<23>
PCI_AD<24>
PCI_AD<26>
PCI_AD<25>
PCI_AD<27>
PCI_AD<29>
PCI_AD<28>
PCI_AD<30>
PCI_AD<31>
PCI_AD<10>
PCI_AD<11>
PCI_AD<12>
PCI_AD<13>
PCI_AD<14>
PCI_AD<15>
PCI_AD<16>
PCI_AD<17>
PCI_AD<18>
PCI_AD<19>
FW_SCL
FW_SDA
PP3V3_S3
81D4
81D4
81D4 81D4
81A5
81A5
81A5 81A5
67C5
67C5
67C5 67C5
67C3
67C3
67C3 67C3
66C6
66C6
66C6
67B8
66C6
65D1
65D1
65D1
67B6
65D1
63B7
63B7
63B7
64C1
63B7
60C2
60C2
60C2
64A6
60C2
59C6
59C6
59C6
32C6
59C6
57D4
57D4
57D4
31C5
57D4
52B1
52B1
52B1
29D6
52B1
46D6
46D6
46D6
29D3
46D6
46C3
46C3
46C3
29B2
46C3
46B3
46B3
46B3
28D6
46B3
41C5
41C5
41C5
28D3
41C5
37D7
37D7
37D7
28B2
37D5
37D5
37D5
37C3
19D7
37C3
37A7
37C3
37A7
26D2
16B6
37A7
32C5
32C5
51D7
32C5
22B6
22B6
14C2
32C5
27C5
38C3
22A6
27C5
46C7
6C5
27C5
26D2
26D2
6B5
26D2
26D2
26D2
6B5
26D2
26D2
26D2
5D4
46C7
22A7
27C5
5D4
38A3
6C3
5B4
5D4
37B2
26B3
6C3
22B6
22B6
22A7
22B6
22B6
5D4
22A6
22A7
6B3
22A7
22A6
22A6
22B5
6B3
22A6
22A6
22A6
5A7
38B6
38B6
38B6
38B6
38B6
38B6
38C5
38C5
38C5
38C3
38C3
5B2
37A5
22B7
22B7
34D6
22A6
22B7
22B7
22B7
22B7
22B7
22B7
22B7
22B7
22A7
22A7
22A7
22A7
22A7
22A7
22A7
22A7
22A7
22A7
22A7
22B7
22B7
22B7
22B7
22B7
22B7
22B7
22B7
22B7
6C5
5D4
SE
SM
RESET
D7
D5
D6
D4
D3
D2
CPS
PD
BMODE
PC2
PC0
PC1
LREQ
LPS
DS1
LCLK
DS0
XI
R1
R0
TESTM
TESTW
TPBIAS0
TPBIAS1
TPB1N
TPB1P
TPB0N
TPB0P
TPA1N
TPA1P
TPA0P
TPA0N
PINT
PCLK
AVDD_3P3
DVDD_3P3
DVDD_CORE
PLLVDD_3P3
PLLVDD_CORE
PLLGND
LKON_DS2
CNA
IO
IO
IO
IO
IO
IO
IO
IO
OUT
OUT
OUT
OUT
TRI-ST/NC
VCC
GND
IN
IN
IN IO
OUT
IO
IO
IO
IO
IO
IO
IO
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
FW_B is BILINGUAL
FW_A is DS_ONLY
DUAL PORT DEVICES ARE POWER CLASS 4 (’100’)
INTERNAL PULLUP PROVIDES
CAPACITOR IN CONJUCTION WITH
RECEIVES POWER
RESET PULSE WHEN PHY FIRST
NC
IMPLEMENT 1K PULLUP OR PULLDOWN ON PORT PAGE
SINGLE PORT DEVICES ARE POWER CLASS 0 (’000’)
1MA (MAX) BUS HOLDERS
NC
X5R
0.22uF
402
20%
6.3V
C4050
1
2
390K
1/16W
5%
402
MF-LF
R4055
1 2
TSB83AA22AZAJ
(1 OF 2)
BGA
CRITICAL
U3900
D10
D11G5H5
L9
M12
A5
D13
C9
C10
C12
B13
B11
A6
B8
D12
H12
J12K7K6C5C6
G13
L13
N13
K13
N4
M4
N5
H13
K11
M13
A10
A7
A8
A12
A13
L10
A4
B5
L11
N7
E2
E1
J1
J2
B1
C1
G1
G2
D2
K1
A9
20%
402
0.01uF
16V
CERM
C4010
1
2
10V
X5R
10%
1uF
402
C4002
1
2
402
X5R
10V
10%
1uF
C4021
1
2
6.34K
1%
1/16W
402
MF-LF
R4062
2 1
X5R
10V
402
10%
1uF
C4001
1
2
1uF
10V
X5R
10%
402
C4003
1
2
X5R
10%
1uF
402
10V
C4004
1
2
10V
X5R
10%
1uF
402
C4011
1
2
10V
X5R
10%
1uF
402
C4012
1
2
402
1uF
10%
X5R
10V
C4013
1
2
402
1uF
10%
X5R
10V
C4014
1
2
CRITICAL
98P3040MHZ
SM
G4080
2
3 1
4
1K
402
5%
1/16W
MF-LF
R4045
1
2
1/16W
5%
402
MF-LF
1K
R4042
1
2
1uF
X5R
402
10%
10V
C4031
1
2
X5R
10V
10%
1uF
402
C4030
1
2
603
CERM1
6.3V
2.2uF
10%
C4035
1
2
MF-LF
402
5%
1/16W
10K
R4056
12
MF-LF
402
5%
1/16W
4.7
R4086
1 2
1K
NO STUFF
MF-LF
402
1%
1/16W
R4063
1
2
402
1
MF-LF
1/16W
5%
R4000
1 2
1
402
MF-LF
1/16W
5%
R4035
1 2
402
MF-LF
1/16W
5%
1
R4020
1 2
5%
22
402
MF-LF
1/16W
R4080
1 2
6.3V
20%
0.22uF
402
X5R
C4080
1
2
MF-LF
402
1/16W
470
1%
R4061
2
1
1/16W
1K
5%
MF-LF
402
R4091
1
2
MF-LF
1K
402
5%
1/16W
R4040
1
2
5%
1K
1/16W
402
MF-LF
R4090
1
2
FireWire PHY (TSB83AA22)
SYNC_DATE=09/15/2006
051-7164 06004
8738
SYNC_MASTER=M59_MLB
MIN_NECK_WIDTH=0.20 mm
MIN_LINE_WIDTH=0.25 mm
VOLTAGE=1.83V
PP1V8_FWPHY_OSC
CLK98P304M_FW_XI_R
PP1V95_FWPHY
FW_LKON
PPBUS_S5_FW_FET
FW_PORT1_TPB_P
FW_LKON
PP1V95_FWPHY_PLLVDD
VOLTAGE=1.95V
MIN_LINE_WIDTH=0.38 mm
MIN_NECK_WIDTH=0.22 mm
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.38 mm
PP3V3_FWPHY_PLLVDD
MIN_NECK_WIDTH=0.25 mm
PP1V95_FWPHY
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.38 mm
PP3V3_FWPHY_AVDD
MIN_NECK_WIDTH=0.22 mm
CLKFW_LINK_PCLK
FW_PINT
FW_PORT2_TPA_N
FW_PORT2_TPA_P
FW_PORT1_TPA_P
FW_PORT1_TPA_N
FW_PORT2_TPB_P
FW_PORT2_TPB_N
FW_PORT1_TPB_N
FW_B_TPBIAS
FW_A_TPBIAS
FW_TESTW
FW_TESTM
FW_R0
FW_R1
CLK98P304_FW_XI
CLKFW_PHY_LCLK
FW_B_DS
FW_LPS
FW_LREQ
PP3V3_FWPHY
FW_BMODE
FW_CPS
FW_DATA<2>
FW_DATA<3>
FW_DATA<4>
FW_DATA<6>
FW_DATA<5>
FW_DATA<7>
FW_PHY_RESET_L
PP3V3_FWPHY
FW_A_DS
44B8
44B8
44A8
44A8
43B8
43B8
42C1
42C1
42C4
42C4
38D5 67C3
38B2
38D7
38B5
6C6
67C1
44D7
6C6
44D7
44D7
44D7
6C6
6C6
6C5
43D3
44C5
6C5
44C7
44C7
44C5
44C5
44C7
44C7
44C5
6C5
6C5
6C3
38C3
43B5
44B7
38A3
6C3
44C5
44C5
44B7
44B7
44C5
44C5
44B7
6C3
6C3
5A4
37C3
42C8
44B5
37C3
5A4
5A4
5A4
5A4
37C4
37C4
44B4
44B4
44B5
44B5
44B4
44B4
44B5
44D7
44D7
37C4
37C4
37C4
5A4
37C4
37C4
37C4
37C4
37C4
37C4
5A4
OUT
OUT
AVDDL0
AVDDL4
AVDD
THRML_PAD
VDDO_TTL0
AVDDL6
VDDO_TTL1
RX_N
TESTMODE
TSTPT
LINK*
LED_LINK10/100*
LED_LINK1000*
LED_ACT*
RSET
CTRL25
CTRL12
HSDACN
HSDACP
SWITCH_VAUX
SWITCH_VCC
VMAIN_AVLBL
VAUX_AVLBL
LOM_DISABLE*
XTALO
XTALI
SPI_DO
SPI_CLK
SPI_CS
SPI_DI
VPD_CLK
VPD_DATA
MDIP3
MDIN3
MDIN2
MDIP2
MDIN1
MDIP1
MDIN0
MDIP0
WAKE*
REFCLKN
TX_N
VDDO_TTL3
VDDO_TTL2
VDDO_TTL4
VDD0
VDD1
VDD3
VDD2
VDD6
VDD5
VDD4
VDD7
AVDDL1
AVDDL2
AVDDL5
VDD25
PERST*
REFCLKP
RX_P
AVDDL3
TX_P
PU_VDDO_TTL0
PU_VDDO_TTL1
TEST
TEST
TWSI
SPI
MAIN CLK
PCI EXPRESS
ANALOG
MEDIA
LED
E2
WC*
NC0
NC1
VCC
VSS
SCL
SDA
IN
IN
IO
IO
IO
IO
IO
IO
IO
IO
G
D
S
IN
IN
IN
OUT
OUT
OUT
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
find correct topolgy
to help constraint manager
Setting attribute VOLTAGE
to arbitrary value
NC
INTERNAL PULL-UP
NC
NC
1. KEEP ENET_XTALI AND ENET_XTALO
NC
NC
NC
NC
2. DO NOT ROUTE UNDER CRYSTAL
NC
NC
SCHEME MATCHES DOC MVL100258-01 SCHEME MATCHES DOC MVL100258-01
PLACE C4107 NEAR U4101 AVDD
12 MIL OF U4101 PIN 49 AND 50
PLACE C4110 AND C4111 WITHIN
SCHEME MATCHES DOC MVL100258-01
PLACE C4100-C4106 NEAR PINS AVDLL0-AVDLL6.
NO PULL-UP NEEDED
PLACE C4135-C4139 NEAR VDDO_TTL0-VDD_TTL4 ON U4101
PLACE C4140 NEAR U4102 VCC
PLACE RESISTORS CLOSE TO U4101
TRACE LENGTH <12MIL
ASF IS UNAVAILABLE ON 8053
PLACE C4127-C4134 NEAR PINS VDD0-VDD7 ON U4101
OPTIONAL EXTERNAL LDO
12 MIL OF U2100 E27 AND E28
PLACE C4113 AND C4112 WITHIN
NC
NC
NC
27pF
50V
CERM
5%
402
C4151
1
2
10K
5%
402
MF-LF
1/16W
R4122
1 2
10K
1/16W
402
5%
MF-LF
R4123
1 2
402
16V
X5R
10%
0.1UF
C4101
1
2
CRITICAL
OMIT
QFN
88E8053
U4101
23
19222832515257
3
4
25
24
59
60
62
63
10
18
21
27
31
17
20
26
30
5
42
43
56
55
16
53
54
37
36
35
34
9
11
46
65
29
50
49
12
2
7
13643339444858
1
8
404561
47
38
41
6
15
14
16V
10%
0.1UF
402
X5R
C4140
1
2
OMIT
M24C08
CRITICAL
SO8
U4102
3
1
2
6
5
8
4
7
1/16W
1%
4.87K
MF-LF
402
R4102
1 2
0.1UF
X5R
402
10%
16V
C4107
1
2
402
10%
16V
X5R
0.1UF
C4110
1 2
16V
10%
0.1UF
402
X5R
C4111
1 2
10%
0.1UF
402
16V
X5R
C4112
1 2
402
X5R
16V
10%
0.1UF
C4113
1 2
402
MF-LF
1%
49.9
1/16W
R4106
1
2
402
1%
1/16W
MF-LF
49.9
R4117
1
2
402
MF-LF
1/16W
49.9
1%
R4118
1
2
1%
49.9
1/16W
MF-LF
402
R4119
1
2
402
1/16W
1%
MF-LF
49.9
R4120
1
2
MF-LF
49.9
402
1%
1/16W
R4103
1
2
402
MF-LF
1/16W
1%
49.9
R4104
1
2
402
MF-LF
1/16W
1%
49.9
R4105
1
2
0.001UF
CERM
402
10%
50V
C4116
1
2
402
10%
0.001UF
50V
CERM
C4118
1
2
0.001UF
CERM
10%
402
50V
C4117
1
2
402
50V
10%
CERM
0.001UF
C4115
1
2
402
CERM
6.3V
10%
1UF
C4100
1
2
4.7K
5%
1/16W
MF-LF
402
R4131
1
2
402
MF-LF
1/16W
5%
4.7K
R4130
1
2
SOT23-LF
2N7002
Q4100
3
1
2
4.7K
5%
402
MF-LF
1/16W
R4101
1
2
0402-LF
FERR-120-OHM-1.5A
L4100
1 2
100K
5%
1/16W
MF-LF
402
R4132
1
2
0.001UF
CERM
10%
50V
402
C4105
1
2
X5R
10%
0.1UF
16V
402
C4104
1
2
402
0.1UF
X5R
10%
16V
C4103
1
2
10%
0.1UF
X5R
402
16V
C4102
1
2
0.001UF
402
CERM
50V
10%
C4106
1
2
402
16V
0.1UF
X5R
10%
C4128
1
2
0.001UF
10%
402
50V
CERM
C4133
1
2
50V
402
CERM
0.001UF
10%
C4134
1
2
402
CERM
0.001UF
10%
50V
C4131
1
2
10%
0.001UF
CERM
402
50V
C4132
1
2
16V
10%
X5R
402
0.1UF
C4127
1
2
10%
X5R
402
16V
0.1UF
C4126
1
2
16V
402
X5R
0.1UF
10%
C4129
1
2
16V
10%
402
X5R
0.1UF
C4130
1
2
402
CERM
10%
50V
0.001UF
C4139
1
2
0.001UF
50V
CERM
402
10%
C4138
1
2
16V
0.1UF
X5R
402
10%
C4137
1
2
402
10%
X5R
0.1UF
16V
C4136
1
2
402
X5R
0.1UF
10%
16V
C4135
1
2
25.0000M
SM-3.2X2.5MM
CRITICAL
Y4101
24
13
27pF
402
CERM
50V
5%
C4150
1
2
06004051-7164
87
ETHERNET CONTROLLER
39
SYNC_MASTER=M59_MLB
SYNC_DATE=09/15/2006
PP2V5_S3
PP2V5_S3_ENET_AVDD
MIN_NECK_WIDTH=0.22MM
MIN_LINE_WIDTH=0.4MM
VOLTAGE=2.5V
ENET_VPD_DATA
ENET_VPD_CLK
PP3V3_S3AC
PM_SLP_S3_L
ENET_RSET
PP1V2_S3
ENET_MDI_N<0>
ENET_LOM_DIS_L
NC_ENET_CTRL25
ENET_MDI_P<2>
ENET_MDI_N<2>
VOLTAGE=1.234V
ENET_MDI2
ENET_MDI_N<1>
PP1V2_S3
NC_ENET_CTRL12
ENET_VPD_CLK
PP3V3_S3AC
PCIE_A_D2R_P
PCIE_A_D2R_N
PCIE_A_D2R_C_N
PP3V3_S3AC
VOLTAGE=1.234V
ENET_MDI3
PCIE_A_R2D_C_P
PCIE_A_R2D_C_N
ENET_PU_VDD_TTL0
PCIE_A_R2D_P
PP3V3_S3AC
ENET_PU_VDD_TTL1
PCIE_WAKE_L
PCIE_A_D2R_C_P
ENET_PU_VDD_TTL1
ENET_CLK100M_PCIE_P
ENET_CLK100M_PCIE_N
ENET_RST_L
ENET_PU_VDD_TTL0
ENET_VPD_DATA
ENET_MDI_P<0>
PCIE_A_R2D_N
ENET_MDI_P<1>
ENET_MDI_N<3>
ENET_MDI_P<3>
ENET_XTALI
ENET_XTALO
PP3V3_S3AC
VOLTAGE=1.234V
ENET_MDI1ENET_MDI0
VOLTAGE=1.234V
ENET_LOWPWR_EN
PP3V3_S3AC
ENET_LOM_DIS_L
66C8 66C6
67D3
66B6
67D3
67D3
67D3
67D3
67D3
67D1
65B8
67D1
67D1
67D1
67D1
67D1
41C4
55C3
41C4
41C4
41C4
41C4
41C4
67B8
39D8
51C5
67D8
67D8
39D8
39D8
39D8
39D6
39D8
67B6
39D6
43C8
67D6
67D6
39D6
39B8
39D6
39B8
39D6
63D4
39B8
42A8
63B3
63B3 39B8
39B5
39B8
39B5
39B5
63D3
39B5
32B3
39A8
39D7 39B5
39B4
39B4
48C3
34C5
34C5
39B4
39B4
63C3
40D5
39A5
23C3
5D4
40C4
6D5
40C4
5D4
6D5
39B4
39A5
39A5
23C8
34C3
34C3
39A5
39A5
5A4
5A4
39C6
39C6
5A4
5C4
5A4
40B7
39B7
6D4
40C4
40C4
40A7
5A4
6D4
39A2
5A4
22D4
22D4
5A4
22D4
22D4
39C6
5A4
39B6
5B1
39A6
33A4
33A4
26B1
39A6
39A2
40D4
40C4
40B4
40C4
5A4
6D4
5A4
39C8
SYM_VER2
NC2
NC3
NC4
LINE
SIDE
CHIP
SIDE
NC1
SYM_VER2
NC2
NC3
NC4
LINE
SIDE
CHIP
SIDE
NC1
IN
IO
IO
IO
IO
IO
IO
IO
IO
OUT
V-
V+
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
LAN ENERGY DETECT
Short shielded RJ-45
Place close to connector
Transformers should be
sides of the board
mirrored on opposite
Place one cap at each pin of transformer
514-0277
BOM options provided by this page:
PHYSICAL
PROVIDED
ELECTRICAL_CONSTRAINT_SET
NET_TYPE
SPACING
Page Notes
Power aliases required by this page:
(NONE)
Signal aliases required by this page:
(NONE)
- =PP2V5_ENET
BY
ETHERNET
PHY
- =GND_CHASSIS_ENET
PLACE C4220 & C4221
NEAR ENET_MDI_N<0/1>
find correct topolgy
to help constraint manager
Setting attribute VOLTAGE
to arbitrary value
0
MF-LF
5%
1/16W
402
NO STUFF
R4210
1 2
402
CERM
10%
6.3V
1uF
C4203
1
2
402
CERM
10%
6.3V
1uF
C4202
1
2
3KV
10%
1808
CERM
100pF
C4204
21
75
5%
1/16W
402
MF-LF
R4203
1
2
75
MF-LF
402
5%
1/16W
R4202
1
2
75
MF-LF
402
5%
1/16W
R4201
1
2
75
402
5%
MF-LF
1/16W
R4200
1
2
CERM
10%
1uF
402
6.3V
C4201
1
2
402
10%
6.3V
CERM
1uF
C4200
1
2
1000BT-824-00275
CRITICAL
XFR-SM
T4200
1
10
11
14
15
16
2
3
6
7
8 9
4
5
12
13
CRITICAL
1000BT-824-00275
XFR-SM
T4201
1
10
11
14
15
16
2
3
6
7
8 9
4
5
12
13
F-RT-TH-RJ45
JM36113-P2054-7F
CRITICAL
J4200
9
10
11
12
1
2
3
4
5
6
7
8
0.1uF
10%
16V
X5R
402
C4223
1
2
MF-LF
100K
1/16W
402
1%
R4224
1
2
402
MF-LF
1/16W
5%
3.3K
R4223
1
2
SM-LF
LMC7211
U4200
4
3
1
5
2
402
MF-LF
1%
1/16W
51.1K
R4225
1
2
5%
50V
CERM
402
NO STUFF
100pF
C4222
1
2
MF-LF
2.4K
1/16W
402
5%
R4220
1 2
402-1
50V
5%
68PF
CERM
C4220
1 2
2.4K
MF-LF
1/16W
402
5%
R4221
1 2
402-1
50V
5%
68PF
CERM
C4221
1 2
1%
1/16W
MF-LF
402
470K
R4227
1
2
MMDT3904XF
SOT-363-LF
Q4220
2
6
1
SOT-363-LF
MMDT3904XF
Q4220
5
3
4
1%
MF-LF
392K
1/16W
402
R4228
1
2
MF-LF
10K
5%
1/16W
402
R4226
1
2
SYNC_DATE=09/15/2006
SYNC_MASTER=M59_MLB
Ethernet Connector
87
051-7164
40
06004
LAN_ENERGY_DET
ED_MDIN0_C
VOLTAGE=1.234V
ENETCONN_P<2>
ENET_MDI_N<2>
ENET_MDI_P<2>
ENET_100D
ENETCONN
ENETCONN_P<2>
ENET_100D
ENETCONN
ENETCONN_N<2>
ENET_100D
ENETCONN
ENETCONN_P<3>
ENET_100D
ENETCONN
ENETCONN_P<0>
ENET_100D
ENETCONN
ENETCONN_N<0>
ENET_100D
ENETCONN
ENETCONN_N<1>
ENET_100D
ENETCONN
ENETCONN_N<3>
ENET_100D
ENETCONN
ENETCONN_P<1>
ENETCONN_P<1>
ENETCONN_P<0>
ENETCONN_N<0>
ENETCONN_N<1>
ENETCONN_P<3>
GND_CHASSIS_ENET
ENET_CTAP1
ENET_MDI_P<0>
ENET_MDI_N<0>
ENET_MDI_P<1>
ENET_MDI_N<1>
ENET_MDI_P<3>
ENET_MDI_N<3>
ENET_CTAP_COMMON
MIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.5 mm
ENETCONN_N<2>
ENET_CTAP2
ENET_CTAP3
PP2V5_S3_ENET_AVDD
ENET_MDI_N<0>
ED_MDIN1_C
VOLTAGE=1.234V
ENET_MDI_N<1>
ED_MDIN_R
ENET_CTAP0
ENETCONN_N<3>
EDET_REF
EDET_ACT
EDET_MDIN_AMP
PP3V3_S0
82D5 82C6
82B3 82A4 79D3 79A8 71D2 67C5 67C3 67B3 67A3
66B6 66B5 66B1 65D6 65B3 62A6 61D8 61A5
60D4 60C7 58C7 58C4 57B6 54D4 54B5 52D3 49C7
49C4 49B5
36D6 34A8 33D8 33D3 33C7 29A6 29A3 28A6 27D8
27D5 27D3
27C3 26D1 26B8 26B6 26B4 25D8 25D3 25C6 25C4
25B8 25B4
25A4 24D3 24C3 24B5 24B3 23D5 23B3 22B5 21D3 21C3
20B4 20A4 19C7 19C6 17C6 14D6
44C1
14C7
44A1
10C5
6A8
40B7
40A7
39D5
40C4
40C4
5D4
23C3
40D7
39C3
39C3
40C3
40C3
40C3
40D3
40C3
40C3
40B3
40C3
40D7
40D7
40D7
40D7
40D7
6A6
39C3
39C3
39C3
39C3
39C3
39C3
40D7
5A4
39C3
39C3
40D7
5A4
N-CHN
S
D
G
P-CHN
G
D
S
G
D
S
G
D
S
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
Allows powering Yukon down during battery sleep to save power
When ENETPWR_S3 BOMOPTION is active:
When ENETPWR_S3AC BOMOPTION is active:
Yukon Power Control
1.2V enable has pull-up to 3.3V
State FWPWR_EN_L PM_SLP_S4_L PM_SLP_S3BATT PM_SLP_S3BATT_L P2V5S3_EN P1V2S3_RUNSS
S0 AC 0V 3.3V 0V (3.3V ON) 3.3V 3.3V (2.5V ON) 3.3V (1.2V ON)
S0 Batt 0V 3.3V 0V (3.3V ON) 3.3V 3.3V (2.5V ON) 3.3V (1.2V ON)
S3 AC 0V 3.3V 0V (3.3V ON) 3.3V 3.3V (2.5V ON) 3.3V (1.2V ON)
S3 Batt PBUS 3.3V PBUS (3.3V OFF) 0V 0V (2.5V OFF) 0V (1.2V OFF)
S5 AC 0V 0V PBUS (3.3V OFF) 0V 0V (2.5V OFF) 0V (1.2V OFF)
S5 Batt PBUS 0V PBUS (3.3V OFF) 0V 0V (2.5V OFF) 0V (1.2V OFF)
G3H Batt PBUS 0V PBUS (3.3V OFF) 0V 0V (2.5V OFF) 0V (1.2V OFF)
S3 3.3V 0V (3.3V ON) 3.3V 3.3V (2.5V ON) 3.3V (1.2V ON)
S0 3.3V 0V (3.3V ON) 3.3V 3.3V (2.5V ON) 3.3V (1.2V ON)
State PM_SLP_S4_L PM_SLP_S3BATT PM_SLP_S3BATT_L P2V5S3_EN P1V2S3_RUNSS
S5 0V PBUS (3.3V OFF) 0V 0V (2.5V OFF) 0V (1.2V OFF)
G3H 0V PBUS (3.3V OFF) 0V 0V (2.5V OFF) 0V (1.2V OFF)
470K
402
MF-LF
1/16W
5%
R4302
1
2
402
5%
1/16W
100K
MF-LF
R4304
1
2
5%
1/16W
MF-LF
402
ENETPWR_S3AC
0
R4300
1 2
ENETPWR_S3
5%
1/16W
MF-LF
402
0
R4301
1
2
FDG6332C_NL
SC70-6
Q4300
6
2
1
FDG6332C_NL
SC70-6
Q4300
3
5
4
SOT23-LF
2N7002
Q4302
3
1
2
2N7002
SOT23-LF
Q4304
3
1
2
41 87
06004051-7164
Yukon Power Control
SYNC_MASTER=M59_MLB
SYNC_DATE=09/15/2006
PM_SLP_S3BATT_L
MAKE_BASE=TRUE
PPVIN_S3_P2V5S3_SVIN
PM_SLP_S3BATT_L
PM_SLP_S3BATT
P1V2S3_RUNSS
PP3V3_S3
PP3V3_S3AC
FWPWR_EN_L_OR_GND
PM_SLP_S4_L
PPBUS_G3H
FWPWR_EN_L
81D4
81A5 67C5 67C3
79B7
66C6
71D7
65D1
69C1
63B7
68D5
60C2
67C3
59C6
67C1
57D4
65D6
52B1
66B8
65B7
46D6
66A6
64D7
46C3 67D3
64C8
64A6
46B3 67D1
51C5
62D7
37D7 39D8
48C3
61D7
37D5 39D6
47C7
61D4
37C3 39B8
23C3
55D3
37A7 39B5
6A2
43D8
32C5 39B4
6A1
42B8
63D8
63D8
63B7
27C5 39A5
5C4
5C4
41C3
63D6
41C4
5C4
5D7
5D4 5A4
5C1
5A1
43C7
OUT
IN
NR
NC
THRML
EN
GND
PAD
FB
BIAS
SW
SHDN*
NC
VIN
BOOST
GND
D
S
G
G
D
S
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
PBUS S0 FET
3.3V Supply for FWPHY
<Rb>
NC
<Ra>
200mA max output
Vout = 3.316
NC
Vout = 1.25V * (1 + Ra / Rb)
(Switcher limit)
1.95V Supply for FW PHY
165MA MAX LOAD
20%
2.2uF
402
X5R
4V
C4422
1
2
10%
16V
CERM
402
0.01uF
C4421
1
2
10%
6.3V
1uF
CERM
402
C4420
1
2
SON
TPS799195
CRITICAL
U4420
4
3
6
5
2
1
7
324K
1/16W
1%
402
MF-LF
R4410
1
2
196K
1/16W
1%
402
MF-LF
R4411
1
2
5%
402
CERM
22pF
50V
C4410
1
2
0.22uF
X5R
402
20%
6.3V
C4405
1
2
4.7UF
50V
1206
10%
X7R-CERM
C4400
1
2
LT3470
TSOT23-8
CRITICAL
U4400
7
6
8
4
2
1
5
3
SC-59
SMD20E40C-X-F
D4400
1
2
3
CDPH4D19F-SM
33uH
CRITICAL
L4400
1 2
22UF
20%
6.3V
X5R
805
C4401
1
2
IRLML6302PBF
SOT23
Q4450
3
1
2
402
MF-LF
1/16W
5%
470K
R4450
1
2
330K
5%
1/16W
MF-LF
402
R4451
1
2
SOT23-LF
2N7002
Q4451
3
1
2
402
CERM
50V
10%
0.0022UF
C4450
1
2
FW PHY Power Supply
SYNC_DATE=09/15/2006
SYNC_MASTER=M59_MLB
051-7164 06004
8742
PPBU_S0_FW_EN_DIV
PPBU_S0_FW_EN
PM_SLP_S3_L
PPBUS_G3H
FWPHY3V3_SW
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
SWITCH_NODE=TRUE
FWPHY3V3_FB
PP3V3_FWPHY
PP1V95_FWPHY
FWPHY_CORE_NR
FWPHY3V3_BOOST
PP5VR33V_FWPHY3V3
PPBU_S0_FW
PPBUS_S5_FW_FET
PP3V3_FWPHY
PPBU_S0_FW
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=12.6V
79B7 71D7 69C1 68D5 67C3
67C1 65D6
66C8
65B7
66C6
64D7
44B8
44B8
66B6
64A6
44A8
44A8
65B8
62D7
43B8
43B8
55C3
61D7
42C4
42C4
51C5
61D4
38D7
38D5
38D7
43C8
55D3
38B5
38B2
67C3
38B5
39C8
43D8
6C6 6C6
67C1
6C6
32B3
41C6
6C5 6C5
43D3
6C5
23C3
5C4
6C3 6C3
43B5
6C3
5C4
5A1
5A4 5A4
42B6
38B7
5A4
42C8
G
D
S
G
D
S
S
G
D
GND
SENSEB
OUTA
FAULTB_L
FAULTA_L
ONB
INB
ONA
ONQ1
INA
GATE1A
GATE2A
SENSEA
GATE1B
GATE2B
OUTB
V-
V+
S
G
D
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
as +1 if over the limit (at any point during the period)
MAX5944 current limiter trips if integrator (counter)
reaches 16. A new sample (taken every 125 us) is weighted
and -1/128 if under the limit. As a result, the device
tends to trip easily on devices that produce periodic current
spikes. Current limit has been set higher to compensate.
Page Notes
Power aliases required by this page:
- =FWPWR_PWRON (see related text note below)
Port Power Switch
Current Limit/Active Late-VG Protection
Late-VG Event Detection
- =PPBUS_S0_FWPWRSW (system supply for bus power)
Signal aliases required by this page:
BOM options provided by this page:
Enables port power when machine
is running or on AC.
- =PP3V3_S0_FWPORTPWRSW
NC
NC
(NONE)
0.020 ohm => 2.4A
Current Limits
0.033 ohm => 1.5A
0.030 ohm => 1.66A (Ideal)
0.025 ohm => 2A
2.81V when port power is off
2.95V when port power is on
FWLATEVG_3V_REF:
5%
330K
MF-LF
1/16W
402
R4566
1
2
0.01uF
CERM
402
20%
16V
C4565
1
2
MF-LF
5%
1/16W
470K
402
R4565
1
2
SOI-LF
NDS9407
CRITICAL
Q4565
5
6
7
8
4
1
2
3
SOT-363
2N7002DW-X-F
Q4560
3
5
4
SOT-363
2N7002DW-X-F
Q4560
6
2
1
MINISMDC
CRITICAL
1.5A-24V
F4565
1 2
SI2318DS
SOT23-3
Q4520
3
1
2
X7R
805
35V
10%
1uF
C4525
1
2
35V
10%
805
X7R
1uF
C4520
1
2
MF
805
0.25W
1%
0.020
CRITICAL
R4520
1 2
CRITICAL
SOIC
MAX5944
U4520
3
11
15
7
14
6
12
1
9
2
10
4
13
5
16
8
SMB
B340XF
CRITICAL
D4565
1 2
SM-LF
LMC7211
U4500
4
3
1
5
2
200K
MF-LF
1%
402
1/16W
R4500
1 2
0.1UF
20%
10V
CERM
402
C4500
1
2
0.33uF
603
CERM-X5R
10V
10%
C4509
1
2
MBR0540XXG
SOD-123
D4500
12
MF-LF
2.0M
1/16W
5%
402
R4509
1
2
10K
1/16W
MF-LF
402
1%
R4505
1
2
CRITICAL
0.25W
1%
805
MF
0.020
R4525
1 2
100pF
CERM
402
50V
5%
C4501
1
2
80.6K
402
1%
1/16W
MF-LF
R4506
1
2
1/16W
10K
5%
402
MF-LF
R4501
1
2
SI2318DS
SOT23-3
Q4525
3
1
2
FW_PORT_FAULT_PU
100K
402
5%
1/16W
MF-LF
R4529
1
2
SYNC_DATE=(MASTER)
SYNC_MASTER=(MASTER)
FireWire Port Power
06004051-7164
43 87
MIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.5 mm
VOLTAGE=12.6V
PPBUS_S5_FW_FET_D
VOLTAGE=33V
MIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.5 mm
PPFW_PORTB_ISENSE
MIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.5 mm
PPFW_PORTA_ISENSE
VOLTAGE=33V
PP3V3_FWPHY
FW_PORT_FAULT_L
FWLATEGV_3V_REF
LATEVG_EVENT_L
FW_PORTPWR_EN
PP2V4_FWLATEVG
VOLTAGE=33V
MIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.5 mm
PPFW_PORTA_VP_UF
FW_PORTA_PWRCTRL
VOLTAGE=33V
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
PPFW_PORTB_VP_UF
PPBUS_S5_FW_FET
FW_PORTB_PWRCTRL
PPBUS_S5_FW_FET
MIN_NECK_WIDTH=0.2 mm
FWPWR_EN_L
MIN_LINE_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.5 mm
PPBUS_S5_FWPWRSW_F
VOLTAGE=12.6V
MIN_NECK_WIDTH=0.25 mm
SMC_ADAPTER_EN
PM_SLP_S3_L
MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.2 mm
FWPWR_EN_L_DIV
MIN_NECK_WIDTH=0.1 mm
MIN_LINE_WIDTH=0.1 mm
PP2V4_FWLATEVG_RC
PPBUS_G3H
79B7 71D7 69C1 68D5 67C3 67C1 65D6
66C8
65B7
66C6
64D7
44B8
66B6
64A6
44A8
65B8
62D7
42C4
55C3
61D7
38D7
51C5
61D4
38B5
67C3
67C3
42A8
55D3
6C6
67C1
67C1
39C8
42B8
6C5
44D5
44D3
44B3
43D3
43B5
68A6
32B3
41C6
6C3
44B5
6C5
6C5
42C8
42C8
52A2
23C3
5C4
5A4
44A5
6C3
6C3
38B7
38B7
41B6
51D5
5C4
5A1
TPO#
TPI
TPO
TPI#
VGND
VP
SYM_VER-2
SYM_VER-2
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
DESCRIPTION
REFERENCE DES
BOM OPTION
QTY
PART NUMBER
CRITICAL
(PPFW_PORT2_VP)
(GND_FW_PORT2_VG)
ELECTRICAL_CONSTRAINT_SET
Page Notes
- =PP3V3_S5_FWLATEVG
the necessary aliases to map the
FireWire TPA/TPB pairs to their
pin 5 of connector
Place C4629 close to
DFM rules for only Rs and Cs
placement in an area restricted by
were changed to resistors to allow
Note: The peaking inductors
Note:Trace PPFW_PORT1_VP should handle up to 5A
(GND_FW_PORT1_VG)
(PPFW_PORT1_VP)
(FW_PORT1_BREF)
TPB+
per 1394b V1.33
Place close to FireWire PHY
Termination
and connection detection currents
BREF should be hard-connected to
logic ground for speed signaling
"Snapback" & "Late VG" Protection
"Snapback" & "Late VG" Protection
Cable Power
1394A
(TPA+)
PORT 2
514S0133
BILINGUAL
PORT 1
OUTPUT
TPB<R>
AREF needs to be isolated from
When a bilingual device is
connected to a beta-only device,
there is no DC path between them
(to avoid ground offset issue)
PAGE
(NONE)
to apply to entire TPA/TPB XNets.
1394b implementation based on Apple
(NONE)
514-0255
(TPB-)
(TPB+)
(TPA-)
all local grounds per 1394b spec
Cable Power
TPA-
PP2V4_FWLATEVG needs to be biased
Late-VG Protection Power
to at least 2.1V for FW signal integrity
and should be biased to 2.4V for margin
R4690 should be 390 Ohms max for a 3.3V rail
- =PPFW_PORT1
BY
PHY
INPUT
TPB-
TPA+
TPA<R>
VP
VG
NCNC
provide the appropriate constraints
FireWire Design Guide (FWDG 0.6, 5/14/03)
PHYSICAL
assumed that FireWire PHY page will
constrained on this page. It is
NOTE: FireWire TPA/TPB pairs are NOT
NET_TYPE
SPACING
- =GND_CHASSIS_FW_PORT1
PROVIDED
Power aliases required by this page:
Signal aliases required by this page:
NOTE: This page is expected to contain
appropriate connectors and/or to
properly terminate unused signals.
BOM options provided by this page:
ESD and late-VG rail
for snap-back diodes
(Common to all ports)
TI PHYs require 1uF even though
FW spec calls out 0.33uF
to arbitrary value
Setting attribute VOLTAGE
to help constraint manager
find correct topolgy
CERM
402
6.3V
10%
1uF
C4650
1
2
1/16W
402
MF-LF
1%
56.2
R4651
1
2
MF-LF
402
1%
1/16W
56.2
R4650
1
2
MF-LF
402
56.2
1%
1/16W
R4653
1
2
MF-LF
402
1%
1/16W
56.2
R4652
1
2
1/16W
1%
402
MF-LF
4.99K
R4654
1
2
220pF
25V
5%
402
CERM
C4654
1
2
1/16W
5%
402
MF-LF
0
R4699
1 2
SM
FERR-250-OHM
L4630
1 2
0.001uF
CERM
50V
20%
402
C4634
1
2
BAV99DW-X-F
SOT-363
DP4630
4
5
3
1394A
CRITICAL
F-RT-TH-LF
J4630
7 8 9
10
4
3
6
5
2
1
CERM
402
16V
20%
0.01uF
C4636
1
2
603
50V
0.01uF
CERM
20%
C4635
1
2
BAV99DW-X-F
SOT-363
DP4631
4
5
3
X7R
10%
0.01uF
402
50V
C4631
1
2
SOT-363
BAV99DW-X-F
DP4630
1
2
6
X7R
10%
0.01uF
402
50V
C4630
1
2
X7R
10%
0.01uF
402
50V
C4633
1
2
SOT-363
BAV99DW-X-F
DP4631
1
2
6
X7R
10%
0.01uF
402
50V
C4632
1
2
56.2
1%
MF-LF
1/16W
402
R4663
1
2
1/16W
4.99K
1%
MF-LF
402
R4664
1
2
56.2
1%
1/16W
402
MF-LF
R4662
1
2
25V
5%
402
CERM
220pF
C4664
1
2
402
1%
56.2
1/16W
MF-LF
R4661
1
2
CERM
402
10%
6.3V
1uF
C4660
1
2
1%
56.2
402
MF-LF
1/16W
R4660
1
2
NO STUFF
CERM
20%
16V
0.01uF
402
C4627
1
2
0.1uF
10%
50V
X7R
603-1
C4629
1
2
1M
5%
402
MF-LF
1/16W
R4629
1
2
0.001uF
50V
20%
402
CERM
C4624
1
2
SM
FERR-250-OHM
L4620
1 2
603
CERM
50V
20%
0.01uF
C4625
1
2
0.01uF
20%
16V
CERM
402
C4626
1
2
0.01uF
10%
X7R
402
50V
C4620
1
2
BAV99DW-X-F
SOT-363
DP4620
1
2
6
X7R
10%
0.01uF
402
50V
C4621
1
2
SOT-363
BAV99DW-X-F
DP4620
4
5
3
SOT-363
BAV99DW-X-F
DP4621
1
2
6
BAV99DW-X-F
SOT-363
DP4621
4
5
3
402
50V
0.01uF
10%
X7R
C4623
1
2
X7R
10%
0.01uF
402
50V
C4622
1
2
1%
332
402
MF-LF
1/16W
R4690
1 2
0.01UF
10%
50V
X7R
402
C4691
1
2
CRITICAL
MMBZ5227B
SOT23
D4690
1
3
F-RT-SM1
CRITICAL
1394B-UG31903
J4620
1
10
11
2
3
4
5
6
7
8
9
CRITICAL
90-OHM-100MA
1210-4SM1
FL4630
1
2 3
4
1210-4SM1
CRITICAL
90-OHM-100MA
FL4631
1
2 3
4
OMIT
1/16W
402
MF-LF
0
5%
L4660
1
2
OMIT
0
MF-LF
402
1/16W
5%
L4661
1
2
OMIT
5%
1/16W
402
MF-LF
0
L4662
1
2
OMIT
0
MF-LF
402
1/16W
5%
L4663
1
2
CRITICAL
4
IND,18nH-15mA,0402
L4660,L4661,L4662,L4663
152S0414
SYNC_MASTER=M59_MLB
SYNC_DATE=06/27/2006
8744
06004051-7164
FireWire Ports
FW_PORT2_TPB_N
FW_PORT2_TPB_P
FW_PORT2_TPB_FL_P
FW_PORT2_TPA_N
FW_PORT2_TPA_P
FW_PORT2_TPA_FL_P
FW_PORT2_TPA_FL_N
FW_A_TPBIAS
VOLTAGE=1.234V
VOLTAGE=2.4V
MIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.38 mm
PP2V4_FWLATEVG
FW_PORT1_TPB_N
FW_PORT2_TPB_P
PP3V3_FWPHY
FW_PORT1_TPA_N
FW_PORT2_TPB_N
FW_PORT2_TPB_FL_P
FW_110D
FW
FW_PORT1_TPA_P
FW_110D
FW
GND_CHASSIS_ENET
PP3V3_FWPHY
GND_CHASSIS_USB
FW_PORT1_TPB_P
FW_PORT1_TPA_P
FW_PORT2_TPA_P
FW_PORT2_TPA_N
MAKE_BASE=TRUE
FW_PORT2_TPA_P
MAKE_BASE=TRUE
FW_PORT2_TPB_N
MAKE_BASE=TRUE
FW_PORT2_TPB_P
MAKE_BASE=TRUE
FW_PORT1_TPA_P
MAKE_BASE=TRUE
FW_PORT1_TPB_P
MAKE_BASE=TRUE
FW_PORT1_TPB_N
MAKE_BASE=TRUE
VOLTAGE=33V
MIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.5 mm
PPFW_PORT2_VP
PPFW_PORTB_VP_UF
FW_PORT1_TPA_P
FW_PORT2_TPA_N
FW_PORT1_TPA_N
MAKE_BASE=TRUE
VOLTAGE=1.234V
FW_PORT2_TPB_C
PPFW_PORTA_VP_UF
FW_PORT1_AREF
PP2V4_FWLATEVG
FW_PORT2_TPA_FL_N
FW_110D
FW
FW_PORT2_TPA_FL_P
FW
FW_110D
FW_PORT1_TPB_P
FW_110D
FW
FW_PORT1_TPA_N
FW_110D
FW
FW_PORT1_TPB_N
FW_PORT1_TPB_P
FW_PORT1_TPA_N
PP3V3_FWPHY
PP3V3_FWPHY
VOLTAGE=33V
MIN_NECK_WIDTH=0.25 mm
PPFW_PORT1_VP
MIN_LINE_WIDTH=0.5 mm
PP2V4_FWLATEVG
VOLTAGE=1.234V
FW_B_TPA_L_P
FW_B_TPBIAS
VOLTAGE=1.234V
VOLTAGE=1.234V
FW_B_TPA_L_N
VOLTAGE=1.234V
FW_B_TPB_L_N
VOLTAGE=1.234V
FW_B_TPB_L_P
VOLTAGE=1.234V
FW_PORT1_TPB_C
FW_PORT2_TPB_FL_N
FW
FW_110D
FW_PORT1_TPB_N
FW_110D
FW
GND_CHASSIS_USB
GND_CHASSIS_ENET
FW_PORT2_TPB_FL_N
44B8
44B8
44A8
44B8
44A8
43B8
43B8
43B8
42C4
42C4
42C4
38D7
38D7
38D7
38B5
38B5
38B5
44D7
6C6
44D7
44C5
44A1
6C6
47B2
44D7
44D7 44D7
44D7
44D7
44D7
44D7
44C5
44C5
44D7
44D7
44D7
6C6
44C5
47B2
44C1
44C7
44C7
44C7
44C7
44D5
44C5
44C5
6C5
44C5
44C5
44B7
40B2
6C5
44A1
44C5
44C5
44C5
44C7
44C7
44C7
44C7
44C5
44C5
44C5
43A2
44B7
44C5
44C5
43B2
44B5
44B7
44B7
44B7
44B7
44B7
6C5
44D5
44B7
44A3
40B2
44C5
44C5
44C5
44C5
44B5
44B5
44B4
6C3
44B5
44B4
44B5
6A8
6C3
6A8
44B5
44B5
44B4
44B4
44B4
44B4
44B4
44B7
44B7
44B7
6C5
44B5
44B4
44B7
6C5
44A5
44B5
44B5
44B5
44B5
44B5
6C3
44A5
44B5
6A8
6A8
38B3
38B3
44D7
38B3
38B3
44D7
44D7
38B3
43B8
38B3
38B3
5A4
38B3
38B3
44B2
38B3
6A6
5A4
6A6
38B3
38B3
38B3
38B3
38B3
38B3
38B3
38B3
38B3
38B3
6C3
38B3
38B3
38B3
6C3
43B8
44B2
44B2
38B3
38B3
38B3
38B3
38B3
5A4
43B8
38B3
44B2
38B3
6A6
6A6
44D7
IO
IO
SYM_VER-1
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
Connector shield
NC
NC
518S0371
(40 AWG)
Connector shield
Standard wires
Twin-Ax Pair 1
(28 AWG)
(40 AWG)
Twin-Ax Pair 2
Camera Connector
402
X7R
50V
10%
0.01UF
C4932
1
2
CRITICAL
FERR-220-OHM-2A
0603
L4931
1 2
0402
FERR-220-OHM
L4930
1 2
F-RT-SM
CAMERA-M1-CUS
CRITICAL
J4931
7
8
1
2
3
4
5
6
50V
20%
402
CERM
0.001uF
NO STUFF
C4931
1
2
0603
FERR-220-OHM-2A
CRITICAL
L4950
1 2
1210-4SM1
90-OHM-100MA
CRITICAL
FL4935
1
2 3
4
051-7164 06004
8745
SYNC_MASTER=M59_MLB
SYNC_DATE=09/15/2006
Camera Connector
PP5V_S3
USB2_CAMERA_P_F
USB2_CAMERA_N_F
USB2_CAMERA_P
USB2_CAMERA_N
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=5V
MIN_LINE_WIDTH=0.25 mm
PP5V_S3_CAMERA_F
GND_CHASSIS_INVERTER
GND_CHASSIS_INVERTER
GND_CHASSIS_INVERTER
81C6 81C4
79A6
79A6
67B3
79A5
79A5
79A6
67B1
22C2
22C2
45C5
45C5
79A5
62A2
6D3
6D3
45B5
45B5
45B5
52B8
6D2
6D2
6A8
6A8
6A8
5D4
6D1
6D1
6A6
6A6
6A6
5B2
5A7
5A7
5B2
5B2
5B2
5B2
5B2
5B2
GR1/NON_REM0
GR2/NON_REM1
PRTPWR_POL
PRTPWR
CFG_SEL1
SDA/SMBDATA
SCL/SMBCLK/CFG_SEL0
USBDN0
USBDP0
VBUS_DET
OCS*
RBIAS
USBDP2
USBDN2
USBDN1
USBDP1
XTAL2
XTAL1/CLKIN
CLKIN_EN
RESET*
SELF_PWR
ATEST/REG_EN
TEST
VDD33CR
VDD18
VDD18PLL
VDDA33PLL
VDDA33
SERIAL PORT
PAD
MISC
UPS USB2.0
VSS
THRML
2-PORT USB2.0
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
311S0279
R4912 should be placed as close as possible to U4900.36 and isolated by 0.9mm from other signals.
197S0162
NC
NC
NC
NC
PRTPWR_POL High = PRTPWR goes high whenever USB HUB is enumerated
Test point should be on TOP side.
REG_EN High = internal 1.8V
SM-2
24.000MHZ-12PF-60PPM
CRITICAL
3G
Y5000
2 4
1 3
CERM
12PF
5%
50V
402
3G
C5002
1
2
12PF
5%
50V
CERM
402
3G
C5001
1
2
MF-LF
1/16W
1M
402
1%
3G
R5001
1 2
USB2502
QFN
CRITICAL
3G
U5000
18
28
12K
5%
MF-LF
402
1/16W
3G
R5012
1 2
20%
CERM
10V
0.1UF
402
3G
C5000
1
2
10V
20%
0.1UF
CERM
402
3G
C5007
1
2
20%
10V
CERM
402
0.1UF
3G
C5008
1
2
0.1UF
402
CERM
10V
20%
3G
C5003
1
2
20%
402
10V
0.1UF
CERM
3G
C5004
1
2
CERM
402
10V
0.1UF
20%
3G
C5005
1
2
10V
0.1UF
CERM
20%
402
3G
C5006
1
2
4.7UF
6.3V
603
20%
CERM
3G
C5011
1
2
20%
6.3V
603
4.7UF
CERM
3G
C5010
1
2
4.7UF
6.3V
20%
603
CERM
3G
C5012
1
2
603
6.3V
20%
4.7UF
CERM
3G
C5013
1
2
0
1/16W
MF-LF
402
5%
3G
R5005
1 2
603
6.3V
20%
4.7UF
CERM
3G
C5014
1
2
1/16W
MF-LF
402
5%
0
3G
R5006
1 2
1/16W
MF-LF
402
0
5%
NO_3G
R5004
1 2
1/16W
MF-LF
402
0
5%
NO_3G
R5003
1 2
Internal USB Hub
SYNC_DATE=(MASTER)
SYNC_MASTER=(MASTER)
051-7164 06004
8746
PP3V3_S3
PP3V3_S3
TP_USB_HUB_ENUM
SMBUS_SB_SDA
SMBUS_SB_SCL
USB_HUB_N
PP3V3_S3
TP_USB2_3G_P
TP_USB2_3G_N
USB_IR_N
USB_IR_P
USB_HUB_XTAL_OUT
USB_HUB_G_RST_L
USB_HUB_XTAL_OUT_R
FW_G_RST_L
USB_IR_N
USB_HUB_N
USB_HUB_P
USB_IR_P
USB_HUB_RBIAS
USB_HUB_P
USB_HUB_XTAL_IN
PP1V8_USB_HUB_INTERNAL_VDD18PLL
VOLTAGE=1.8V
MIN_NECK_WIDTH=0.2 MM
MIN_LINE_WIDTH=0.5 MM
PP1V8_USB_HUB_INTERNAL_VDD18
VOLTAGE=1.8V
MIN_NECK_WIDTH=0.2 MM
MIN_LINE_WIDTH=0.5 MM
81D4
81D4
81D4
81A5
81A5
81A5
67C5
67C5
67C5
67C3
67C3
67C3
66C6
66C6
66C6
65D1
65D1
65D1
63B7
63B7
63B7
60C2
60C2
60C2
59C6
59C6
59C6
57D4
57D4
81C3
57D4
52B1
52B1
48B3
52B1
46C3
46D6
33B6
46D6
46B3
46B3
29A6
46C3
41C5
41C5
28A6
41C5
37D7
37D7
27D8
37D7
37D5
37D5
27D7
37D5
37C3
37C3
27D6
46A7
37C3
46B3
46B3
46B7
37A7
37A7
27C6
22C2
37A7
22C2
22C2
22C2
32C5
32C5
27B6
6C3
32C5
6C3
6C3
6C3
27C5
27C5
23D5
6C2
27C5
6B3
6B3
81C6
81C6
37B2
81C6
6C2
6C2
81C6
6C2
5D4
5D4
5B1
6C1
5D4
6B2
6B2
46A5
46B5
37A5
46C3
6C1
6C1
46C3
6C1
OUT
VBUS
D-
D+
GND
IN
IN
OUT
OUT
OUT
EN
OC*
GND
THRML
PAD
VDD
THRM_PAD
GND
0I0 Y0
SEL
1I1
1I0
0I1
Y1
IO
IO
IO
IO
SYM_VER-1
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
SEL=1 Choose USB
SEL=0 Choose SMC
514S0115
Right USB Port
Port Power Switch
USB/SMC Debug Mux
Place L5200, L5205 and L5206 across moat
CRITICAL
0603
FERR-220-OHM-2A
L5205
1 2
100UF
POLY
B2
20%
6.3V
C5296
1
2
20%
6.3V
805-1
CERM
10uF
C5295
1
2
805-1
10uF
6.3V
20%
CERM
C5290
1
2
0.1UF
CERM
402
20%
10V
C5291
1
2
0.01uF
20%
CERM
16V
402
C5205
1
2
CERM
16V
402
20%
0.01uF
C5206
1
2
CRITICAL
FERR-220-OHM-2A
0603
L5206
1 2
CRITICAL
UAR2X
F-RT-SM-USB-RGT1
J5200
1
2
3
4
5
6
7
8
CRITICAL
RTUSB_ESD
SC-75
RCLAMP0502B
D5200
3
12
MSOP
TPS2051
CRITICAL
U5290
4
1
2
3
5
8
7
6
9
TDFN
PI3USB10
CRITICAL
U5250
12
10
11
9
157
6
13
2
8
3
4
20%
10V
CERM
0.1UF
402
C5250
1
2
402
MF-LF
1/16W
5%
10K
R5250
1
2
CRITICAL
1210-4SM1
90-OHM-100MA
L5200
1
2 3
4
47 87
06004051-7164
SYNC_MASTER=M59_MLB
SYNC_DATE=09/15/2006
External USB Connector
USB_DEBUGPRT_EN_L
PP3V42_G3H
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.5 mm
VOLTAGE=5V
PP5V_S3_RTUSB_F
VOLTAGE=0V
MIN_NECK_WIDTH=0.5 mm
GND_RTUSB
MIN_LINE_WIDTH=0.5 mm
PM_SLP_S4_L
PP5V_S5
GND_CHASSIS_USB
MIN_LINE_WIDTH=0.5 mm
PP5V_S3_RTUSB_ILIM
VOLTAGE=5V
MIN_NECK_WIDTH=0.5 mm
USB2_RT_P
SMC_RX_L
SMC_TX_L
USB2_RT_N
RTUSB_OC_L
USB2_RT_F_N
USB2_RT_F_P
USB2_RT_MUXED_P
USB2_RT_MUXED_N
81D4 69C8
69B8 69A8 68B8 67D5 67D3
71D7
66D2
67C3
66C8
67C1
66A8
67B1
53C4
66D8
52D7
66B8
66B8
52B7
66A6
65D6
52B5
64C8
65B7
52B1
51C5
64C8
51D4
48C3
62C8
51D3
41B6
62B6
51C2
23C3
62B2
53B4
22D8
35B7
6A2
62A4
44A3
22C2
52B3
22C2
22C4
27C3
6A1
52B5
44A1
6D3
52B2
6D3
6D3
26D6
5C4
25C8
6A8
6D2
51C7
6D2
6D2
52B3
5D2
5C1
5D4
6A6
6D1
5C2
6D1
6D1
IN
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
NC
516S0361
Left I/O Board Connector
NCNC
NC
NC NC
NC
CRITICAL
F-ST-SM
QT510806-L111-7F
J5500
1
10
1112
1314
1516
1718
19
2
20
2122
2324
2526
2728
29
3
30
3132
3334
3536
3738
39
4
40
4142
4344
4546
4748
49
5
50
5152
5354
5556
5758
59
6
60
6162
6364
6566
6768
69
7
70
7172
7374
7576
7778
79
8
80
81
8283
84
9
48 87
06004051-7164
Left I/O Board Connector
SYNC_MASTER=(MASTER)
SYNC_DATE=(MASTER)
USB2_LT2_N
USB2_LT2_P
USB2_LT_N
USB2_LT_P
PCIE_MINI_D2R_N
PCIE_MINI_D2R_P
SMBUS_SB_SDA
ACZ_SDATAOUT
ACZ_SDATAIN<0>
ACZ_SYNC
ACZ_RST_L
SMBUS_SMC_A_S3_SDA
PCIE_EXCARD_D2R_P
PCIE_CLK100M_MINI_P
PCIE_CLK100M_MINI_N
USB2_EXCARD_P
USB2_EXCARD_N
ACZ_BITCLK
SMBUS_SB_SCL
PCIE_WAKE_L
PM_SLP_S4_L
SMC_EXCARD_PWR_EN
PM_SLP_S3_LS5V
SMC_EXCARD_CP
EXCARD_OC_L
MINI_CLKREQ_L
EXCARD_CLKREQ_L
LIO_PLT_RESET_L
LTALS_OUT
ALS_GAIN
SYS_ONEWIRE
LTUSB_OC_L
LT2USB_OC_L
SMC_BC_ACOK
SMBUS_SMC_A_S3_SCL
PCIE_EXCARD_R2D_C_P
PCIE_CLK100M_EXCARD_P
PP1V5_S0
PCIE_EXCARD_R2D_C_N
PCIE_EXCARD_D2R_N
PCIE_MINI_R2D_C_P
PCIE_CLK100M_EXCARD_N
PCIE_MINI_R2D_C_N
67C8 67C6 66C5 62C1 62A8 25D6 25C8
81C3
81C3
25C6
46B6
46B6
66B8
25C2
33B6
33B6
66A6
25B6
29A6
29A6
64C8
25B2
28A6
28A6
51C5
25A8
27D8
81C3
27D8
47C7
24B5
27D7
51B5
27D7
41B6
66C7
52B3
81C3
24A5
22C2
22C2
22C2
22C2
50C6
50C6
27D6
27C6
50C6
22C2
22C2
27D6
23C3
66C6
22D8
22D8
22D8
69A6
51B5
24A3
50B6
6C3
6C3
6D3
6D3
50C5
50C5
27C6
27C5
50C5
34D5
34D5
6C3
6C3
27C6
6A2
62B3
22C4
34A4
34A4
22C4
22C4
68A6
27C6
34C5
9B7
50B5
34B5
6C2
6C2
6D2
6D2
50C3
50C3
27B6
87B4
87B4
87B4
87B4 27C3
50C3
34D4
34D4
6C2
6C2
87B4
27B6
39C6
6A1
6A2
52A2
6C3
34A3
34A3
51B5
52B2
6D3
6C3
52A2
27C5
50C6
34C3
8B7
50C6
50B3
50C6
34B3
50C6
6C1
6C1
6D1
6D1
22D4
22D4
23D5
21C7
21C7
21C7
21C7 27B3
22D4
33B4
33B4
6C1
6C1
21C7
23D5
23C8
5C4
51B7
6A1
51B7
6C1
33B4
33B4
26C1
57C7
6D5
51B7
6D1
6C1
51C5
27C3
50C5
33B4
5D4
50C5
22D4
50C5
33B4
50C5
5B1
5B1
5C1
5C1
5B1
5B1
5B1
5C1
5C1
5C1
5C1 5B1
5B1
5B1
5B1
5C1
5C1
5C1
5B1
5B1
5C1
5C1
5C1
5C1
5C1
5C1
5C1
5C1
5C1
5C1
5C1
5C1
5C1
5B1
5B1
5C1
5B1
5D1
5C1
5B1
5B1
5B1
5B1
GND
OUT
VIN+ VIN-
V+
ALERT
A0
SCL
SDA
GNDS
V+
GND
OUT
VIN+ VIN-
V+
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
Placement Note:
Place near R8307
near L8300 and
bottom side
Q8301 and Q8302
DCIn Current Sense
Place sensor on
TMP106 Thermal Sensor
Battery Current Sense
Place near R8308
Placement Note:
Temp Sensor has address x92,x93
1/16W
MF-LF
0
5%
402
R5651
1
2
0
402
MF-LF
1/16W
5%
NO STUFF
R5650
1
2
INA193
SOT23-5
CRITICAL
U5605
2
15
3 4
402
1uF
CERM
6.3V
10%
C5615
1
2
1uF
402
CERM
10%
6.3V
C5605
1
2
402
20%
0.1uF
CERM
10V
C5650
1
2
CRITICAL
TMP106
WCSP-6
U5650
C2
B2
A2
B1
A1
C1
SOT23-5
INA193
CRITICAL
U5615
2
15
3 4
06004
8749
051-7164
Current & Thermal Sensors
SYNC_MASTER=(MASTER)
SYNC_DATE=(MASTER)
CHGR_CSO_R_P
CHGR_CSO_R_N
LIO_BATT_ISENSE
TMPSNSR_A0
SMBUS_SMC_B_S0_SCL
SMBUS_SMC_B_S0_SDA
PP3V3_S0
LIO_DCIN_ISENSE
CHGR_CSI_P
PP3V3_S0PP3V3_S0
CHGR_CSI_R_N
82D5
82D5 82D5
82C6
82C6 82C6
82B3
82B3 82B3
82A4
82A4 82A4
79D3
79D3 79D3
79A8
79A8 79A8
71D2
71D2
71D2
67C5
67C5
67C5
67C3
67C3 67C3
67B3
67B3 67B3
67A3
67A3 67A3
66B6
66B6 66B6
66B5
66B5 66B5
66B1
66B1 66B1
65D6
65D6 65D6
65B3
65B3
65B3
62A6
62A6 62A6
61D8
61D8 61D8
61A5
61A5 61A5
60D4
60D4 60D4
60C7
60C7 60C7
58C7
58C7 58C7
58C4
58C4 58C4
57B6
57B6 57B6
54D4
54D4
54D4
54B5
54B5 54B5
52D3
52D3 52D3
49C7
49C7 49C4
49C4
49B5 49B5
40B6
40B6 40B6
36D6
36D6 36D6
34A8
34A8 34A8
33D8
33D8 33D8
33D3
33D3
33D3
33C7
33C7 33C7
29A6
29A6 29A6
29A3
29A3 29A3
28A6
28A6 28A6
27D8
27D8 27D8
27D5
27D5 27D5
27D3
27D3 27D3
27C3
27C3 27C3
26D1
26D1 26D1
26B8
26B8 26B8
26B6
26B6 26B6
26B4
26B4 26B4
25D8
25D8 25D8
25D3
25D3 25D3
25C6
25C6 25C6
25C4
25C4 25C4
25B8
25B8 25B8
25B4
25B4 25B4
25A4
25A4 25A4
24D3
24D3 24D3
24C3
24C3 24C3
24B5
24B5 24B5
24B3
24B3 24B3
23D5
23D5 23D5
23B3
23B3 23B3
22B5
22B5 22B5
21D3
21D3 21D3
21C3
21C3 21C3
20B4
20B4 20B4
20A4
20A4 20A4
19C7
19C7 19C7
19C6
19C6 19C6
17C6
17C6 17C6
51B5
51B5
14D6
14D6 14D6
27D3
27D3
14C7
14C7 14C7
27D2
27D2
10C5
10C5 10C5
69D6
27D1
27D1
5D4
5D4 5D4
69B2
69C2
55C3
10B3
10B3
5A4
55C5
69D4
5A4 5A4
69D3
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
Place caps close to SB
Place caps close to SB
PCI-E x1 Port "A" = Ethernet (Yukon)
PCI-E x1 Port "B" = PCI-E Mini Card
PCI-E x1 Port "C" = ExpressCard
PCI-E x1 Port "D" = Unused
PCI-E x1 Port "E" = Unused
PCI-E x1 Port "F" = Unused
0.1uF
10%
16V
X5R
402
C5710
1 2
0.1uF
10%
16V
X5R
402
C5711
1 2
0.1uF
10%
16V
X5R
402
C5721
1 2
0.1uF
10%
16V
X5R
402
C5720
1 2
051-7164 06004
8750
PCI-E Connections
SYNC_MASTER=(MASTER)
SYNC_DATE=(MASTER)
MAKE_BASE=TRUE
TP_PCIE_F_D2RP
MAKE_BASE=TRUE
TP_PCIE_F_D2RN
MAKE_BASE=TRUE
TP_PCIE_F_R2DP
TP_PCIE_F_D2RP
TP_PCIE_F_D2RN
TP_PCIE_F_R2DN
MAKE_BASE=TRUE
TP_PCIE_E_D2RP
MAKE_BASE=TRUE
TP_PCIE_E_D2RN
MAKE_BASE=TRUE
TP_PCIE_E_R2DN
MAKE_BASE=TRUE
TP_PCIE_E_R2DP
TP_PCIE_E_D2RP
TP_PCIE_E_D2RN
TP_PCIE_E_R2DN
TP_PCIE_E_R2DP
TP_PCIE_D_R2DP
TP_PCIE_D_R2DN
TP_PCIE_D_D2RN
TP_PCIE_D_D2RP
MAKE_BASE=TRUE
TP_PCIE_D_R2DP
MAKE_BASE=TRUE
TP_PCIE_D_R2DN
MAKE_BASE=TRUE
TP_PCIE_D_D2RN
MAKE_BASE=TRUE
TP_PCIE_D_D2RP
PCIE_EXCARD_D2R_P
PCIE_EXCARD_D2R_N
PCIE_C_R2D_C_N
PCIE_C_R2D_C_P
PCIE_EXCARD_D2R_N
MAKE_BASE=TRUE
PCIE_EXCARD_D2R_P
MAKE_BASE=TRUE
PCIE_EXCARD_R2D_C_N
MAKE_BASE=TRUE
PCIE_EXCARD_R2D_C_P
MAKE_BASE=TRUE
PCIE_EXCARD_D2R_N
PCIE_EXCARD_D2R_P
PCIE_EXCARD_R2D_C_N
PCIE_EXCARD_R2D_C_P
PCIE_MINI_R2D_C_P
MAKE_BASE=TRUE
PCIE_MINI_D2R_P
MAKE_BASE=TRUE
PCIE_MINI_D2R_P
PCIE_MINI_D2R_N
MAKE_BASE=TRUE
MAKE_BASE=TRUE
PCIE_MINI_R2D_C_N
PCIE_B_R2D_C_N
PCIE_MINI_R2D_C_P
PCIE_MINI_R2D_C_N
PCIE_MINI_D2R_N
PCIE_MINI_D2R_P
MAKE_BASE=TRUE
TP_PCIE_F_R2DN
PCIE_MINI_D2R_N
PCIE_B_R2D_C_P
TP_PCIE_F_R2DP
50B6
50C6
50C6
50C6
50C6
50B6
50B3
50C3
50B5
50C5
50C3
50C6
50C3
50C5
50C5
50C6
50C5
50B5
48B6
48B6
50B3
50C3
48C6
50C5
48C6
50C3
50C3
50C5
48B6
48B6
22D4
22D4
48B6
48B6
50C5
50C5
22D4
48C6
22D4
50C5
50C5
48C6
48C6
48C6
50B3
50A3
50B3
50B6
50A6
50B6
50B3
50B3
50B3
50B3
50B6
50B6
50B6
50B6
50B6
50B6
50B6
50B6
50B3
50B3
50B3
50B3
22D4
22D4
5B1
5B1
22D4
22D4
48B6
48B6
5B1
22D4
5B1
48C6
48C6
22D4
22D4
50B3
22D4
50B6
22C4
22C4
22C4
22C4
22C4
22C4
22C4
22C4
22C4
22C4
22C4
22C4
22C4
22C4
22D4
22D4
22D4
22D4
22D4
22D4
22D4
22D4
5B1
5B1
22D4
22D4
5B1
5B1
5C1
5C1
5B1
22D4
5B1
5B1
5B1
5B1
22C4
5B1
22D4
22C4
IN
IN
IN
OUT
OUT
OUT
OUT
IN
IN
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
IN
IN
OUT
OUT
OUT
P16
P51
P50
P42/SDA1
P97/IRQ15*/SDA0
P95/IRQ14*
P94/IRQ13*
P93/IRQ12*
P92/IRQ0*
P91/IRQ1*
P86/IRQ5*/SCK1/SCL1
P83/LPCPD*
P82/CLKRUN*
P80/PME*
P35/LRESET*
P34/LFRAME*
P10
P12
P13
P14
P15
P17
P31/LAD1
P30/LAD0
P32/LAD2
P33/LAD3
P36/LCLK
P37/SERIRQ
P44/TMO1
P77/AN7
P76/AN6
P81/GA20
P96/EXCL
P11
P47/PWX1/PWM1
P45
P46/PWX0/PWM0
P40/TMIO
P43/TMI1/EXSCK1
P27
P26
P25
P24
P23
P22
P21
P20
P41/TMO0
P52/SCL0
P60/KIN0*
P61/KIN1*
P62/KIN2*
P63/KIN3*
P64/KIN4*
P65/KIN5*
P66/IRQ6*/KIN6*
P67/IRQ7*/KIN7*
P70/AN0
P71/AN1
P72/AN2
P73/AN3
P74/AN4
P75/AN5
P84/IRQ3*/TXD1
P85/IRQ4*/RXD1
P90/IRQ2*
(1 OF 4)
PA2/KIN10*/PS2AC
PA3/KIN11*/PS2AD
PA5/KIN13*/PS2BD
PA4/KIN12*/PS2BC
PB2
PB3
PB4
PE0
PG6/EXIRQ14*/EXSDAB
PG5/EXIRQ13*/EXSCLA
PH1/EXIRQ7*
PH0/EXIRQ6*
PG7/EXIRQ15*/EXSCLB
PG4/EXIRQ12*/EXSDAA
PH3/EXEXCL
PH2/FWE
PB5
PF4/PWM4
PF2/IRQ10*/TMOY
PG2/EXIRQ10*/SDA2
PG0/EXIRQ8*/TMIX
PF7/PWM7
PC3/TIOCD0/TCLKB/WUE11*
PH5
PB7
PB6
PH4
PF5/PWM5
PF6/PWM6
PG1/EXIRQ9*/TMIY
PA6/KIN14*/PS2CC
PA7/KIN15*/PS2CD
PD0/AN8
PD1/AN9
PD2/AN10
PD3/AN11
PD4/AN12
PD5/AN13
PD6/AN14
PD7/AN15
PF0/IRQ8*/PWM2
PF1/IRQ9*/PWM3
PB0/LSMI*
PB1/LSCI
PC0/TIOCA0/WUE8*
PC1/TIOCB0/WUE9*
PC2/TIOCC0/TCLKA/WUE10*
PC4/TIOCA1/WUE12*
PC5/TIOCB1/TCLKC/WUE13*
PC6/TIOCA2/WUE14*
PC7/TIOCB2/TCLKD/WUE15*
PG3/EXIRQ11*/SCL2
PF3/IRQ11*/TMOX
PA1/KIN9*/PA2DD
PA0/KIN8*/PA2DC
PE1*/ETCK
PE2*/ETDI
PE3*/ETDO
PE4*/ETMS
(2 OF 4)
VCL
AVREF
VCC
VCC
VCC
AVCC
XTAL
EXTAL
AVCC
VCC
MD1
MD2
NMI
RES*
ETRST*
AVREF
AVSS
VSS
(3 OF 4)
NC22
NC21
NC20
NC19
NC18
NC17
NC16
NC15
NC14
NC13
NC12
NC9
NC6
NC11
NC10
NC8
NC7
NC5
NC4
NC3
NC2
NC1
NC0
(4 OF 4)
OUT
OUT
IO
OUT
IN
IN
IN
OUT
IN
IO
IN
IO
OUT
OUT
IN
IN
OUT
OUT
IN
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
IN
IN
IN
OUT
OUT
OUT
OUT
IO
IO
IO
IO
IO
IO
IO
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
OUT
IN
IN
OUT
OUT
IN
OUT
OUT
IN
OUT
OUT
OUT
IO
IO
IO
IO
IN
IN
IN
OUT
OUT
OUT
IO
IN
IN
IN
IN
IO
IO
IN
IN
IO
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
THEY ARE SET BY SOFTWARE TO BE
DRIVEN OUTPUTS ALWAYS SO THEY
LAYOUT NOTE:
PLACE C5807 NEAR PIN F1
VCL IS INTERNAL RAIL
PLACE R5899 AND C5820 NEAR SMC PIN N14,N15
SMC
LAYOUT NOTE:
UNUSED PINS HAVE THE FORMAT
CAN BE LEFT NO-CONNECTED.
SMC_XXX WHERE XXX IS THE PORT NUMBER.
805
20%
6.3V
CERM
22UF
C5802
1
2
CERM-X5R
6.3V
0.47UF
402
10%
C5807
1
2
10V
0.1UF
20%
CERM
402
C5803
1
2
0.1UF
20%
CERM
10V
402
C5820
1
2
5%
1/16W
4.7
402
MF-LF
R5899
1 2
0.1UF
20%
10V
CERM
402
C5804
1
2
SM
XW5800
1 2
402
10V
20%
0.1UF
CERM
C5805
1
2
20%
10V
CERM
402
0.1UF
C5806
1
2
SMC_H8S2116
OMIT
BGA
U5800
B12
C13
A15
B14
B15
C14
D12
C15
D13
D14
D15
E12
E14
E15
E13
F14
D9
C9
A9
B9
D8
C8
A8
D7
A5
B5
D5
C3
B1
C2
D3
C1
G1
G4
F2
L13
L14
L15
K12
K13
K14
J12
J13
N12
R13
P13
R14
P14
R15
N13
P15
C7
A7
B7
D6
C6
A6
B6
K4
J2
J1
J3
J4
H2
H1
G2
OMIT
SMC_H8S2116
BGA
U5800
R3
P3
R2
N3
R1
N2
M4
N1
B10
A10
D10
A11
B11
C11
A12
D11
G14
G15
G13
G12
H14
H15
H13
H12
M11
P11
R11
N11
P10
R10
N10
M10
M3
M2
M1
L4
L2
M7
P6
R6
N6
M6
R5
P5
N5
P9
R9
N9
P8
R8
M8
P7
R7
E1
F3
K2
C4
D4
B3
BGA
SMC_H8S2116
OMIT
U5800
N14
N15
M14
M15
P12
R12
L1
B2
E2
K1
F4
E3
P2P1J15A1F1
D1P4R4
F12
F13
B13
A13
A4B4D2
A2
BGA
SMC_H8S2116
OMIT
U5800
G3
H3
K15
J14
F15
A14
C12
C10
C5
A3
B8
E4
K3
H4
M9
N8
L3
N4
M5
N7
M12
M13
L12
MF-LF
5%
402
1/16W
10K
R5809
1
2
MF-LF
402
5%
10K
1/16W
R5801
1
2
1/16W
5%
10K
MF-LF
402
R5802
1
2
0
5%
1/16W
MF-LF
402
NOSTUFF
R5803
1
2
10K
MF-LF
5%
1/16W
402
R5898
1
2
051-7164 06004
51 87
IMVP_VR_ON
SMC_RX_L
SMC_TX_L
SMBUS_SMC_BSB_SDA
SMBUS_SMC_0_S0_SDA
PM_SLP_S5_L
PM_SLP_S4_L
PM_SLP_S3_L
SMC_BS_ALRT_L
SMC_BC_ACOK
SMBUS_SMC_BSB_SCL
PM_SUS_STAT_L
PM_CLKRUN_L
SMC_WAKE_SCI_L
SMC_LRESET_L
LPC_FRAME_L
PM_LAN_ENABLE
ALL_SYS_PWRGD
RSMRST_PWRGD
SMC_SB_NMI
PM_RSMRST_L
PM_PWRBTN_L
LPC_AD<1>
LPC_AD<0>
LPC_AD<2>
LPC_AD<3>
PCI_CLK_SMC
INT_SERIRQ
TP_SMC_XDP_TRST_L
SMC_P1V5S0_NB_ISENSE
SMC_BATT_ISENSE
SMC_TPM_GPIO
SMC_CLK32K_SUSCLK
SMC_RSTGATE_L
SMC_SYS_KBDLED
TP_SMC_XDP_TCK
TP_SMC_SYS_LED
TP_SMC_XDP_TMS
SMC_TPM_PP
TP_SMC_P27
TP_SMC_P26
SMC_BATT_CHG_EN
SMC_BATT_TRICKLE_EN_L
TP_SMC_P23
TP_SMC_P22
TP_SMC_P21
TP_SMC_P20
SMC_SYS_LED_16B
SMBUS_SMC_0_S0_SCL
SMC_PM_G2_EN
SMC_ADAPTER_EN
SPI_ARB
SPI_SCLK
SPI_SI
SPI_SO
SMC_PROCHOT_3_3_L
FWH_INIT_L
SMC_CPU_ISENSE
SMC_GPU_ISENSE
SMC_GPU_VSENSE
SMC_DCIN_ISENSE
SMC_PBUS_VSENSE
SC_TX_L
SC_RX_L
SMC_ONOFF_L
SMC_CPU_VSENSE
SMC_XTAL
SMC_EXTAL
PP3V3_AVCC_SMC
MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.20 MM
PP3V42_G3H
KBC_MDE
SMC_MD1
PP3V3_AVREF_SMC
SMC_TRST_L
SMC_NMI
GND_SMC_AVSS
GND_SMC_AVSS
PP3V42_G3H
SMC_VCL
PP3V42_G3H
SMC_RST_L
SMC_TMS
SMC_TDO
SMC_TDI
SMC_TCK
SMC_RCIN_L
BOOT_LPC_SPI_L
SMC_CPU_RESET_3_3_L
SMBUS_SMC_BSA_SCL
TP_SMC_FAN_3_TACH
TP_SMC_FAN_2_TACH
SMC_FAN_1_TACH
SMC_FAN_0_TACH
TP_SMC_FAN_2_CTL
SMC_FAN_1_CTL
SMC_FAN_0_CTL
SMC_RUNTIME_SCI_L
SMC_EXTSMI_L
TP_SMC_PF1
TP_SMC_PF0
ALS_RIGHT
ALS_LEFT
SMC_MEM_ISENSE
SMC_P1V05S0_ISENSE
TP_SMC_ANALOG_ID
SMS_Z_AXIS
SMS_Y_AXIS
SMS_X_AXIS
PM_BATLOW_L
SYS_ONEWIRE
SMC_XDP_TCK_3_3
SMC_SYS_ISET
TP_SMC_BATT_VSET
SMS_INT_L
SMC_EXCARD_OC_L
SMS_ONOFF_L
TP_SMC_FAN_3_CTL
TP_SMC_SYS_VSET
SPI_CE_L
SMBUS_SMC_BSA_SDA
SMC_LID
SMC_BATT_ISET
SMC_EXCARD_PWR_EN
SMC_FWE
ALS_GAIN
SMBUS_SMC_A_S3_SDA
SMBUS_SMC_B_S0_SCL
SMC_PROCHOT
SMC_THRMTRIP
SMBUS_SMC_A_S3_SCL
SMBUS_SMC_B_S0_SDA
SMC_CASE_OPEN
SMC_EXCARD_CP
ISENSE_CAL_EN
SMC_ODD_DETECT
PM_EXTTS_L
PM_THRM_L
SMC_USB_DEBUG_MUX
PM_SYSRST_L
SMC_XDP_TDO_3_3
81D4
81D4
81D4
69C8
69C8
69C8
69B8
69B8
69B8
69A8
69A8
69A8
68B8
68B8
68B8
67D5
67D5
67D5
67D3
67D3
67D3
66D2
66D2
66D2
66C8
66C8
66C8
66A8
66A8
66A8
53C4
53C4
53C4
52D7
57C6
57C6
52D7
52D7
52B7
57C2
57C2
52B7
52B7
52B5
55D6
55D6
52B5
52B5
52B1
55C6
55C6
52B1
52B1
51D4
55C1
55C1
51D4
51D3
51D3
55B7
55B7
51C2
51C2
53B5
53B4
54C2
69A6
60C6
54C2
53C5
47B5
55B5
55B5
47B5
47B5
68B2
68B2
52D5
52B3
52B3
54B3
68A6
53B5
60C6
60C6
60C6
60C6
60C6
60C6
60C6
54B3
52D5
81C4
35B7
55B3
55B3
35B7
35B7
27C3
27C3
52D3
52B2
52B2
27D6
52A2
68B2
52A2
52A2
53C4
53C4
65C7
53C4
53C4
53C5
53C5
53C5
55B4
37A8
27D6
68A6
52D3
52C6
27C3
55B1
55B1
27C3
27C3
53B5
53B4
53B4
53B5
53B5 53B4
27C2
55B2
52B2
27C2
48C4
52A2
29C3
26C5
61C7
47B5
47B5
27B3
27D5
23C3
52B2
48C3
27B3
23C5
23C8
26B1
21C5
23C3
66B1
52A5
23C1
21D4
21D4
21D4
21D4
23C8
52C5
52D5
35B3
6C5
52D5
52D5
52C5
52C5
52C5
69A6
69A3
52C5
52C5
52C5
52C5
27D5
52A2
56C7
56C1
56C1
21C4
52B2
26D6
53B4
53B4
53B5
52B6
52B6
26D6
26D6
52D6
52B2
52B2
52B2
52B2 22B3
27C1
52D5
52D5
52D5
52C5
52C5
52D5
52D5
48C3
52D5
52B2
52D5
52D5
56C7
27C1
81C4
48C3
6D5
48C3
55A8
28C3
23C5
5C4
5C2
5C2
27B2
27D3
5C4
5D1
5B1
27B2
5C2
5C2
23C1
5C4
5C2
5B4
26A5
52A4
23C3
5B4
23C3
5C2
5D2
5C2
5C2
34D6
5C2
52C3
52D3
55C2
52C5
35B2
6C3
57A6
52D3
52D3
52C3
52B5
52C3
52C3
52A2
52A2
52C3
52C3
52C3
52C3
52A8
27D3
66A8
43C8
22C6
22C6
22C6
22C6
52D1
5C2
55B7
55B6
55C6
55C4
55D2
52B5
52B5
5A2
55D6
52C8
52C8
5D2
5C2
52B6
5C2
5C2
51C4
51B2
5D2
5D2
5C2
5C2
5C2
5C2
5C2
21C3
5C2
52B2
5D1
52D3
52D3
58B4
58B7
52D3
58B4
58B7
23C8
23B8
52C3
52C3
57D2
57C7
52A2
52D3
52D3
59C3
59C3
59C3
23C1
5C1
52B2
69A8
52D3
23C3
52B5
59C6
52D3
52D3
22C6
5D1
52B2
69A8
5C1
52B2
5C1
52C2
52C2
52A2
5C1
5B2
36C4
14B7
23C8
52B5
5A2
52B2
G
D
S
G
D
S
IN
OUT
GND
IN
OUT
V-
V+
V-
V+
OUT
NC
CD
GND
OUT
VDD
OUT
OUT
G
D
S
IN
OUT
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
Reports when 5V S5 and 3.3V S5 are in regulation
SMC Crystal Circuit
5V Comp threshold set to 4.480V (89.6%)
ISL6269 undervoltage threshold 81-87% (2.67 - 2.87V)
SMC AVREF Supply
SMC 3.3V to 1.05V Level Shifting
Debug Power Button
Silk: "PWR BTN"
1.71V Reference
NOTE: R5965 acts as 10K pull-up for PGOOD signal
System (Sleep) LED Circuit
NC
SMC Reset Button / Brownout Detect
Silk: "SMC RST"
1.05V Mid-Reference
SMC 1.05V to 3.3V Level Shifting
SMC PWRGD Circuit
0.1uF
CERM
402
20%
10V
C5900
1
2
SMC_TPM_GPIO1
0
1/16W
5%
MF-LF
402
R5990
1 2
0
SMC_TPM_GPIO2
5%
1/16W
MF-LF
402
R5991
1 2
2N7002DW-X-F
SOT-363
Q5995
6
2
1
2N7002DW-X-F
SOT-363
Q5995
3
5
4
1/16W
MF-LF
0
5%
402
R5992
1 2
1/16W
MF-LF
0
5%
402
R5993
1 2
0.1uF
CERM
402
20%
10V
C5977
1
2
1K
MF-LF
402
5%
1/16W
R5971
1
2
5%
402
6.2K
1/16W
MF-LF
R5970
1
2
402
CERM-X5R
6.3V
0.47UF
10%
C5965
1
2
0.01uF
20%
16V
CERM
402
C5967
1
2
6.3V
20%
X5R
10uF
603
C5966
1
2
SOT23-3
REF3133
CRITICAL
VR5965
3
1 2
0.1uF
10V
20%
402
CERM
C5960
1
2
10K
MF-LF
402
1%
1/16W
R5961
1
2
MF-LF
402
1%
1/16W
10K
R5962
1
2
5%
402
MF-LF
10K
1/16W
R5965
1
2
LMC7211
SM-LF
U5977
4
3
1
5
2
SM-LF
LMC7211
U5960
4
3
1
5
2
402
MF-LF
5%
1/16W
0
R5994
1 2
1/16W
MF-LF
SMC_TPM_PP
5%
402
0
R5995
1 2
402
MF-LF
5%
1/16W
10K
R5931
1 2
402
10K
1/16W5%MF-LF
R5932
1 2
100K
402
MF-LF
5%
1/16W
R5933
1 2
10K
1/16W5%MF-LF
402
R5934
1 2
402
MF-LF
5%
1/16W
10K
R5935
1 2
100K
5%
MF-LF
402
1/16W
R5936
1 2
2.0K
402
MF-LF
5%
1/16W
R5937
1 2
402
MF-LF
5%
1/16W
100K
R5938
1 2
402
MF-LF
5%
1/16W
10K
R5939
1 2
10K
1/16W
5%
402
MF-LF
R5940
1 2
10K
402
5%
1/16W MF-LF
R5941
1 2
10K
1/16W
5%
402
MF-LF
R5942
1 2
10K
1/16W5%MF-LF
402
R5943
1 2
402
MF-LF
5%
1/16W
10K
R5944
1 2
402
MF-LF
5%
1/16W
10K
R5945
1 2
1/16W5%MF-LF
402
10K
R5946
1 2
470K
402
MF-LF
5%
1/16W
R5947
1 2
10K
1/16W5%MF-LF
402
R5948
1 2
402
MF-LF
5%
1/16W
10K
R5930
1 2
20.00MHZ
5X3.2-SM
CRITICAL
Y5920
1
2
SOT23-5
RN5VD30A-F
CRITICAL
U5900
5
3
4
1
2
10K
1/16W
1%
402
MF-LF
R5964
1
2
16.2K
MF-LF
402
1%
1/16W
R5963
1
2
CERM
402
0.0022uF
10%
50V
C5969
1
2
402
MF-LF
5%
1/16W
10K
R5980
1 2
5%
10K
1/16W MF-LF
402
R5981
1 2
1/16W
10K
5%
MF-LF
402
R5982
1 2
MF-LF
402
5%
1/16W
100K
R5983
1 2
100K
1/16W5%MF-LF
402
R5984
1 2
100K
1/16W5%MF-LF
402
R5985
1 2
402
MF-LF
5%
1/16W
0
R5996
1 2
1/16W
5%
402
MF-LF
1K
R5900
1
2
OMIT
0
MF-LF
603
5%
1/10W
R5901
1
2
MF-LF
603
5%
OMIT
0
1/10W
R5910
1
2
2N7002
SOT23-LF
Q5952
3
1
2
2N3906
SOT23-LF
Q5950
1
3
2
100
MF-LF
402
5%
1/16W
R5950
1
2
1/16W
5%
402
MF-LF
2.2K
R5951
1
2
MF-LF
402
1/16W
10K
5%
R5952
1
2
15pF
CERM
402
5%
50V
C5920
1 2
15pF
402
CERM
50V
5%
C5921
1 2
CERM
10%
16V
0.01UF
402
C5901
1
2
SYNC_DATE=09/15/2006
SYNC_MASTER=M59_MLB
52
051-7164 06004
87
SMC Support
SMC_MEM_ISENSE
SMC_TPM_GPIO
MAKE_BASE=TRUE
TP_SMC_P26TP_SMC_P26
PP3V42_G3H
SMC_XDP_TDO_3_3
SMC_USB_DEBUG_MUX
EXCARD_OC_L
SMC_EXCARD_OC_L
CPU_PROCHOT_L
PM_SLP_S5_L
SMC_BATT_CHG_EN
SMC_TX_L
TPM_GPIO1
SMC_RX_L
TPM_PP
SC_RX_L
SMC_TPM_PP
SC_TX_L
SMC_PROCHOT_3_3_L
PP3V3_S0
VOLTAGE=0.46V
P0V46_SMC_LSREF
TP_SMC_PF1
MAKE_BASE=TRUE
TP_SMC_PF1
TP_SMC_PF0 TP_SMC_PF0
MAKE_BASE=TRUE
TP_SMC_P27 TP_SMC_P27
MAKE_BASE=TRUE
TP_SMC_P23 TP_SMC_P23
MAKE_BASE=TRUE
TP_SMC_P22 TP_SMC_P22
MAKE_BASE=TRUE
TP_SMC_P21
MAKE_BASE=TRUE
TP_SMC_P21
TP_SMC_P20
MAKE_BASE=TRUE
TP_SMC_P20
TP_SMC_XDP_TRST_L
MAKE_BASE=TRUE
TP_SMC_XDP_TRST_L
TP_SMC_XDP_TMS
MAKE_BASE=TRUE
TP_SMC_XDP_TMS
TP_SMC_XDP_TCK TP_SMC_XDP_TCK
MAKE_BASE=TRUE
TP_SMC_FAN_3_CTL
MAKE_BASE=TRUE
TP_SMC_FAN_3_CTL
TP_SMC_FAN_3_TACH
TP_SMC_FAN_2_TACH TP_SMC_FAN_2_TACH
MAKE_BASE=TRUE
TP_SMC_FAN_2_CTL TP_SMC_FAN_2_CTL
MAKE_BASE=TRUE
TP_SMC_SYS_VSET
MAKE_BASE=TRUE
TP_SMC_SYS_VSET
TP_SMC_BATT_VSET
MAKE_BASE=TRUE
TP_SMC_BATT_VSET
TP_SMC_SYS_LED
MAKE_BASE=TRUE
TP_SMC_SYS_LED
TP_SMC_ANALOG_ID TP_SMC_ANALOG_ID
MAKE_BASE=TRUE
SMC_P1V5S0_NB_ISENSE
MAKE_BASE=TRUE
SMC_P1V5S0_NB_ISENSE
PM_EXTTS_L
MAKE_BASE=TRUE
PM_EXTTS_L
SMC_P1V05S0_ISENSE SMC_P1V05S0_ISENSE
MAKE_BASE=TRUE
FWH_INIT_L
MAKE_BASE=TRUE
FWH_INIT_L
SMC_RST_L
SMC_MANUAL_RST_L
PP3V42_G3H
SMC_SYS_LED_16B
SYS_LED_L_VDIV
SYS_LED_ANODE
SYS_LED_L
PP5V_S3
SYS_LED_ILIM
RSMRST_PWRGD
P5VS5_COMP_POS
P1V71_SMC_REF
P5VS5_PGOOD
MAKE_BASE=TRUE
RSMRST_PWRGD
PP3V42_G3H
PP5V_S5
SMC_ONOFF_L
SMC_THRMTRIP
SMC_PROCHOT
PM_THRMTRIP_L
CPU_PROCHOT_L
PP3V42_G3H
MIN_NECK_WIDTH=0.2 mm
PP3V3_AVREF_SMC
MIN_LINE_WIDTH=0.4 mm
VOLTAGE=3.3V
SMC_BATT_TRICKLE_EN_L
SMC_EXCARD_CP
PM_SUS_STAT_L
GND_SMC_AVSS
MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.4 mm
VOLTAGE=0V
SMC_BC_ACOK
SMC_CASE_OPEN
SMC_ADAPTER_EN
SMC_CPU_RESET_3_3_L
SMC_TCK
SMC_XDP_TCK_3_3
SMC_TDI
SMC_TDO
SMC_BS_ALRT_L
SMC_TMS
SMC_XTAL
SMC_EXTAL
SYS_ONEWIRE
PP3V3_S3
PP3V3_S3
SMC_RX_L
SMC_TX_L
SMC_FWE
SMC_ONOFF_L
SMC_LID
SMC_TPM_RESET_L
SMS_INT_L
TPM_GPIO2
TP_SMC_FAN_3_TACH
MAKE_BASE=TRUE
USB_DEBUGPRT_EN_L
82D5 82C6 82B3 82A4 79D3 79A8 71D2
67C5 67C3 67B3
67A3 66B6 66B5 66B1 65D6 65B3 62A6
61D8 61A5 60D4 60C7 58C7 58C4 57B6 54D4 54B5
49C7 49C4 49B5 40B6 36D6 34A8 33D8 33D3 33C7
29A6 29A3 28A6 27D8 27D5 27D3 27C3 26D1 26B8 26B6
26B4 25D8 25D3
25C6 25C4
81D4
25B8
81D4
81D4
81D4
81D4
81D4
69C8
25B4
69C8
69C8
69C8
81A5
81A5
69B8
25A4
69B8
69B8
69B8
67C5
67C5
69A8
24D3
69A8
69A8
69A8
67C3
67C3
68B8
24C3
68B8
68B8
68B8
66C6
66C6
67D5
24B5
67D5
67D5
67D5
65D1
65D1
67D3
24B3
67D3
67D3
71D7
67D3
63B7
63B7
66D2
23D5
66D2
66D2
67C3
66D2
60C2
60C2
66C8
23B3
66C8
66C8
67C1
66C8
59C6
59C6
66A8
22B5
66A8
66A8
67B1
66A8
57D4
57D4
53C4
21D3
53C4
53C4
66D8
53C4
52B1
52B1
52D7
21C3
52B7
52D7
66B8
52D7
57C6
46D6
46D6
52B7
20B4
52B5
52B7
65D6
52B5
57C2
46C3
46C3
52B5
20A4
52B1
52B1
65B7
52B1
55D6
46B3
46B3
51D4
19C7
51D4
81C6
51D4
64C8
51D4
55C6
41C5
41C5
51D3
19C6
51D3
81C4
51D3
62C8
51D3
55C1
37D7
37D7
51C2
48C3
17C6
51C2
67B3
51C2
62B6
51C2
55B7
37D5
37D5
47B5
22D8
53B4
53B5
14D6
52D3 52D5
53C5
53C5
47B5
67B1
47B5
62B2
47B5
60C6
55B5
69A6
37C3
37C3
53B5
53B4
35B7
22C4
52B2
52B2
14C7
51B7 51B7
52D3
52D5
35B7
62A2
65C7
35B7
62A4
81C4
35B7
53B5
55B3
68A6
37A7
37A7
52B3
52B3
81C4
27C3
6C3
51C5
51C7
51C7
10C5
55B4 55B4
29C3 29C3
55B2 55B2
51D5
51D5
53B5
27C3
45C3
52A4
66A8
65C7
27C3
47C7
52B2
21C2
27C3
51B7
51C5
55B1
51C5
68A6
53B5
53B5
53B4
68B2
53B4
51B7
32C5
32C5
51C7
51C7
52C6
52C5 52C3
26D6
6C1
52C1
23C3
69A6
47B5
47B5
5D4
52C3 52C5
52C3 52C5
52C3 52C5
52C3 52C5
52C3 52C5
52C3 52C5
52C3 52C5
52C3 52C5
52C3
52C5
52D3 52D5
52D3 52D5
52D3
52D3 52D5
52D3 52D5
52D3 52D5
52D3 52D5
52D3 52D5
52D3 52D5
52D3 52D5
28C3 28C3
52D3 52D5
21C4
21C4
51C3
26D6
5D4
51D7
66A6
52A5
26D6
25C8
51C5
14B6
52D3
26D6
69A3
48C3
23C5
51C4
48C3
51D5
51C5
51B5
51B5
51C5
51B5
48C3
27C5
27C5
47B5
47B5
51C5
81C4
51B5
52D5
51A7
51D5
51D7 51D7
5D2
51B7
51B7
5C1
51B7
7C6
5C4
51D7
5C2
60C6
5C2
60C6
51C5
51C7
51C5
51D5
5A4
51B5 51B5
51B5 51B5
51D7 51D7
51D7 51D7
51D7 51D7
51D7 51D7
51D7 51D7
51C7 51C7
51C7 51C7
51C7 51C7
51B7 51B7
51B7
51B7 51B7
51B7 51B7
51B5 51B5
51B5 51B5
51C7 51C7
51A7 51A7
51D5 51D5
14B7 14B7
51A7 51A7
5C2 5C2
5C2
5D2
51C7
81C6
5B2
65D7
51D7
5D2
5D4
5A2
51B5
51B5
7C6
7C6
5D2
51D2
51D7
5C1
5C2
51B2
5B1
51C5
43C8
51B5
5C2
51B5
5C2
5C2
5D1
5C2
51C3
51C3
5C1
5D4
5D4
5C2
5C2
51B5
5A2
51B5
60B7
23C3
60C6
51B7
47B3
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
(GPIO15)
NC
516S0384
NC
NCNC
CRITICAL
LPCPLUS
M-ST-SM
QT500306-L021-9F
J6000
1
10
11
12
13
14
15
16
17
18
19
2
20
21
22
23
24
25
26
27
28
29
3
30
31
32
33
34
4
5
6
7
8
9
53 87
06004051-7164
LPC+ Debug Connector
SYNC_MASTER=(MASTER)
SYNC_DATE=(MASTER)
PP3V42_G3H
PP5V_S0
FWH_INIT_L
PCI_CLK_PORT80_LPC
LPC_AD<2>
LPC_AD<3>
INT_SERIRQ
PM_SUS_STAT_L
SMC_TDI
SMC_TCK
SMC_RST_L
SMC_NMI
SMC_RX_L
SV_SET_UP
LPC_AD<0>
LPC_AD<1>
BOOT_LPC_SPI_L
LPC_FRAME_L
PM_CLKRUN_L
SMC_TMS
DEBUG_RST_L
SMC_TRST_L
SMC_TDO
SMC_MD1
SMC_TX_L
81D4
69C8 69B8
81B3
69A8
80B5
68B8
80A1
67D5
79B8
67D3
71A6
66D2
67B3
66C8
67B1
66A8
67A1
52D7
66B5
52B7
62B1
52B5
61D7
52B1
58C7
51D4
58C4
51D3
57B5
51C2
55A8
47B5
36D6
52D5
60C6
52B3
52B3
35B7
31C5
52D3
60C6
60C6
60C6
52A2
52B2
60C6
60C6
60C6
60C6
52B2
27C3
25D8
51D5
51C7
51C7
51C7
51C5
52B2
52B2
52D6
51C7
23C3
51D7
51D7
51C7
51C7
51C5
52B2
52B2
51C7
26D6
5D4
21C4
34D6
21D4
21D4
23C8
23C5
51B5
51C5
51C3
51C1
47B5
23B6
21D4
21D4
22B3
21C5
23C8
51B5
26B1
51C1
51B5
51C1
47B5
5D2
5D2
5C2
5C2
5C2
5C2
5C2
5C2
5C2
5C2
5C2
5C2
5C2
5C2
5D2
5C2
5C2
5C2
5C2
5C2
5C2
5C2
5C2
5C2
5C2
SMBDATA
SMBCLK
ALERT*
OT2*
DXP2
OT1*
DXN
DXP1
GND
VCC
IO
IO
GND
VDD
SDATA
SCLK
THM*
ALERT*/
D+
D-
THM2*
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
to U6100 as possible
Keep all 4 XWs as close
Placement note:
Place in between VRAM
NC
NC
NC
Placement note:
Placement note:
NC
NC
NC
NC
518S0452
Place on left side of fan cutout
Placement note:
GPU/Heat Pipe & Bottom Case Skin Thermal Sensor
Place U6150 near GPU
(TG0H)
(TG0T)
518S0452
GPU Die Thermal Sensor
(Th1H)
(Th0H)
UMAX
MAX6695AUB
CRITICAL
U6100
8
3
2
4
6
5
10
7
9
1
50V
CERM
402
10%
0.0022uF
C6120
1
2
SM
XW6120
1 2
SM
XW6121
1 2
SM
XW6111
1 2
SM
XW6110
1 2
0.001UF
10%
402
CERM
50V
C6160
1
2
0.1uF
CERM
402
20%
10V
C6100
1
2
BM02B-ACHKS-A-GAN-TF-LF
CRITICAL
M-RT-SM
J6120
3
4
1
2
1/16W
MF-LF
402
5%
10K
R6152
1
2
47
MF-LF
5%
1/16W
402
R6100
1 2
0.1UF
X5R
402
10%
16V
C6150
1
2
1/16W
10K
5%
402
MF-LF
R6151
1
2
MSOP
TMP401
U6150
6
3
2
5
8
7
4
1
402
MF-LF
1/16W
1%
499
R6160
1 2
402
MF-LF
1/16W
1%
499
R6161
1 2
M-RT-SM
CRITICAL
BM02B-ACHKS-A-GAN-TF-LF
J6160
3
4
1
2
10%
402
CERM
0.0022uF
50V
C6110
1
2
SYNC_MASTER=M59_MLB
SYNC_DATE=09/15/2006
051-7164 06004
8754
Thermal Sensors
HSTHMSNS_DX_P
PP3V3_S0
SMBUS_SMC_0_S0_SCL
RSFSTHMSNS_D_N
RSFSTHMSNS_D_P
ATI_TDIODE_N
ATI_TDIODE_P
HSTHMSNS_DX_N
SMBUS_SMC_0_S0_SDA
GPUTHMSNS_DXN
GPUTHMSNS_DXP
RSTHMSNS_ALERT_L
RSTHMSNS_THM_L
PP3V3_S0
REMTHMSNS_DXP1
REMTHMSNS_DXN
REMTHMSNS_DXP2
SMBUS_SMC_0_S0_SCL
SMBUS_SMC_0_S0_SDA
MAKE_BASE=TRUE
VOLTAGE=3.3V
MIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.38 mm
PP3V3_S0_GPUTHMSNS_R
82D5
82D5
82C6
82C6
82B3
82B3
82A4
82A4
79D3
79D3
79A8
79A8
71D2
71D2
67C5
67C5
67C3
67C3
67B3
67B3
67A3
67A3
66B6
66B6
66B5
66B5
66B1
66B1
65D6
65D6
65B3
65B3
62A6
62A6
61D8
61D8
61A5
61A5
60D4
60D4
60C7
60C7
58C7
58C7
58C4
58C4
57B6
57B6
54D4
54B5
52D3
52D3
49C7
49C7
49C4
49C4
49B5
49B5
40B6
40B6
36D6
36D6
34A8
34A8
33D8
33D8
33D3
33D3
33C7
33C7
29A6
29A6
29A3
29A3
28A6
28A6
27D8
27D8
27D5
27D5
27D3
27D3
27C3
27C3
26D1
26D1
26B8
26B8
26B6
26B6
26B4
26B4
25D8
25D8
25D3
25D3
25C6
25C6
25C4
25C4
25B8
25B8
25B4
25B4
25A4
25A4
24D3
24D3
24C3
24C3
24B5
24B5
24B3
24B3
23D5
23D5
23B3
23B3
22B5
22B5
21D3
21D3
21C3
21C3
20B4
20B4
20A4
20A4
19C7
19C7
19C6
19C6
17C6
17C6
14D6
54C2
54C2
14D6
54B3
54B3
14C7
51C7
51C5
14C7
51C7
51C5
10C5
27D6
27D6
10C5
27D6
27D6
5D4
27D5
27D5
5D4
27D5
27D5
5A2
5A4
27D3
5A2
5A2
77A3
77A3
5A2
27D3
5A4
27D3
27D3
IN
OUT
N-CHN
S
D
G
P-CHN
G
D
S
N-CHN
S
D
G
P-CHN
G
D
S
D
S
G
D
S
G
D
S
G
OUT
OUT
IN
OUT
IN
OUT
IN IN
OUT
OUT
IN
OUT
IN
OUT
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
Current Sense Calibration Circuit
Switches in fixed load on power supplies to calibrate current sense circuits
Place RC close to SMC
CPU Current Sense Filter
Place RC close to SMC
Rthevanin = 4573 ohms
Place RC close to SMC
Place RC close to SMC Place RC close to SMC
Place RC close to SMC
1.05V S0 (NB) Current Sense Filter
Place RC close to SMC
Place RC close to SMC
1.2A / 1.44W
Place RC close to SMC
Battery Current Sense Filter
Place short near U8400 center
DCIN Current Sense Filter
GPU Current Sense Filter
GPU Voltage Sense / Filter
Place short near U0700 center
CPU Voltage Sense / Filter
1.5V S0 (NB) Current Sense Filter
Enables PBUS VSense divider when high.
PBUS Voltage Sense Enable & Filter
1.05A / 1.1W
470K
5%
1/16W
MF-LF
402
R6228
1
2
402
MF-LF
1/16W
5%
100K
R6227
1
2
27.4K
1%
1/16W
MF-LF
402
R6285
1
2
6.3V
0.22UF
402
X5R
20%
C6285
1
2
5.49K
402
MF-LF
1/16W
1%
R6286
1
2
FDG6332C_NL
SC70-6
Q6229
6
2
1
FDG6332C_NL
SC70-6
Q6229
3
5
4
SC70-6
FDG6332C_NL
Q6215
6
2
1
FDG6332C_NL
SC70-6
Q6215
3
5
4
FDM6296
CRITICAL
MICROFET3X3
Q6220
5
4
1 2 3
MICROFET3X3
FDM6296
CRITICAL
Q6221
5
4
1 2 3
MICROFET3X3
CRITICAL
FDM6296
Q6223
5
4
1 2 3
0.22UF
20%
6.3V
X5R
402
C6259
1
2
1%
1/16W
MF-LF
402
4.53K
R6259
1 2
1/16W
4.53K
402
MF-LF
1%
R6270
1 2
6.3V
0.22UF
402
X5R
20%
C6270
1
2
20%
X5R
402
0.22UF
6.3V
C6275
1
2
1%
1/16W
MF-LF
402
4.53K
R6275
1 2
6.3V
0.22UF
402
X5R
20%
C6280
1
2
4.53K
402
MF-LF
1/16W
1%
R6280
1 2
1%
1/16W
MF-LF
402
4.53K
R6290
1 2
20%
X5R
402
0.22UF
6.3V
C6290
1
2
20%
X5R
402
0.22UF
6.3V
C6240
1
2
1%
1/16W
MF-LF
402
4.53K
R6240
1 2
6.3V
0.22UF
402
X5R
20%
C6235
1
2
4.53K
402
MF-LF
1%
1/16W
R6235
1 2
SM
XW6259
1 2
402
1%
4.53K
MF-LF
1/16W
R6209
1 2
402
X5R
6.3V
20%
0.22UF
C6209
1
2
SM
XW6209
1 2
1206
MF-LF
1/4W
1%
1.00
R6220
1
2
470K
5%
1/16W
MF-LF
402
R6229
1
2
1206
MF-LF
1/4W
1%
1.00
R6221
1
2
1206
MF-LF
1/4W
1%
1.00
R6223
1
2
SYNC_DATE=09/15/2006
SYNC_MASTER=M59_MLB
Current & Voltage Sensing
55 87
06004051-7164
ISENSE_CAL_EN_LS5V
MIN_NECK_WIDTH=0.20 mm
MIN_LINE_WIDTH=0.50 mm
P1V05S0_ISENSE_CAL
PP1V05_S0
PM_SLP_S3_L
PPBUS_G3H
P1V05S0_IOUT
PPVCORE_D3C_GPU
PPVCORE_S0_CPU
GND_SMC_AVSS
PPVCORE_D3C_GPU
GND_SMC_AVSS
SMC_CPU_VSENSE
SMC_GPU_VSENSE
CPUVSENSE_IN
GPUVSENSE_IN
GND_SMC_AVSSGND_SMC_AVSSGND_SMC_AVSS
SMC_P1V05S0_ISENSE
SMC_P1V5S0_NB_ISENSE
P1V5S0_NB_IOUTSMC_GPU_ISENSE
GPUVCORE_IOUTCPUVCORE_IOUT
GND_SMC_AVSS
SMC_BATT_ISENSELIO_BATT_ISENSE
GND_SMC_AVSS
SMC_DCIN_ISENSE
PPVCORE_S0_CPU
LIO_DCIN_ISENSE
GND_SMC_AVSS
ISENSE_CAL_EN_L
PP5V_S0
ISENSE_CAL_EN
VOLTAGE=12.6V
PPBUS_G3H_VSENSE
SMC_PBUS_VSENSE
GND_SMC_AVSS
SMC_CPU_ISENSE
CPUVCORE_ISENSE_CAL
MIN_LINE_WIDTH=0.50 mm
MIN_NECK_WIDTH=0.20 mm
GPUVCORE_ISENSE_CAL
MIN_LINE_WIDTH=0.50 mm
MIN_NECK_WIDTH=0.20 mm
PBUSVSENS_EN_L
67D8 67D6 65A2
34C8 34C6 34B8 25D3 25C4 24D3 24C3
21C1 19D7 19D6 19D5 19D2
81B3
19D1
80B5
19C8
79B7
80A1
17D6
71D7
79B8
17D3
69C1
71A6
16D3
68D5
67B3
16C8
67C3
67B1
13B5
67C1
67A1
12C2
65D6
57C6
57C6 57C6
57C6
66B5
12B7
66C8
65B7
57C6
57C6
57C2 57C6 57C6
57C2 57C2
57C2
62B1
57C6
12A7
66C6
64D7
57C2
57C2
55D6 57C2 57C2
55D6 55D6
55D6
61D7
57C2
11C5
66B6
64A6
55C6
55D6
55C6 55D6 55D6
55C6 55C6
55C6
58C7
55D6
11B3
65B8
62D7
77A7
67D3
55C1
77A7
55C1
55C1 55C6 55C6
55C1 55C1
67D3
55C1
58C4
55C6
9B7
51C5
61D7
72D8
67D1
55B7
72D8
55B7
55B7 55C1 55C1
55B7 55B7
67D1
55B7
57B5
55B7
8C7
43C8
61D4
71C1 61D1
55B5
71C1
55B5
55B5 55B7 55B5
55B5 55B5
61D1
55B5
53C4
55B5
7D5
42A8
43D8
71B7 55D7
55B3
71B7
55B3
55B3 55B3 55B3
55B3 55B3
55A6
55B3
36D6
55B3
7B6
39C8
42B8
67A8
9D7
55B1
67A8
55B1
55B1 55B1 55B1
55B1 55B1
9D7
55B1
31C5
55B1
7B5
32B3
41C6
67A6
8D7
52B6
67A6
52B6
52B6 52B6 52B6
52D5 52D5
52B6 52B6
8D7
52B6
25D8
52B6
5D4
23C3
5C4
55C7
8B5
51C4
55A5
51C4
51C4 51C4 51C4
52D3 52D3
51C4 51C4
8B5
51C4
5D4
51B7
51C4
5B2
5C4
5A1
65B1
5B2 5B2
51B2
5B2
51B2
51D5
51D5
51B2 51B2 51B2
51A7 51D5 62A6 51D5 71D1 61A5
51B2
51D5 49C6
51B2
51D5
5B2
49C2
51B2
5D2
5B2
51D5
51B2
51D5
SCK
SO
WP*
SI
VDD
CE*
HOLD*
VSS
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
R6307 AND R6306 SHOULD BE PLACED LESS THAN 100 MILS FORM ICH7M
R6303 SHOULD BE PLACED LESS THAN 100 MILS FORM FLASH ROM
ICH7M AND TEKOA(LAN CHIP)
R6309 IS NOT NEEDED WHEN SHARING SPI FLASH WITH
0.1UF
20%
10V
CERM
402
C6312
1
2
3.3K
MF-LF
5%
402
1/16W
R6301
1
2
MF-LF
1/16W
5%
3.3K
402
R6302
1
2
50V
5%
CERM
402
22pF
C6301
1
2
47
1/16W
5%
402
MF-LF
R6307
1 2
CERM
5%
50V
22pF
402
C6308
1
2
22pF
402
50V
CERM
5%
C6309
1
2
1/16W
5%
47
MF-LF
402
R6303
1 2
402
5%
MF-LF
1/16W
47
R6306
1 2
50V
5%
CERM
402
22pF
C6311
1
2
SOI
SST25VF016B
16MBIT
CRITICAL
OMIT
U6301
1
7
6
5
2
8
4
3
MF-LF
1/16W
10K
5%
402
R6308
1 2
402
MF-LF
1/16W
5%
10K
NOSTUFF
R6309
1 2
SYNC_MASTER=M59_MLB
SYNC_DATE=09/15/2006
87
06004051-7164
SPI BOOTROM
56
PP3V3_S5
SPI_SO_R
SPI_SI_RSPI_SCLK
SPI_SCLK_R
SPI_SI
SPI_SO
SPI_CE_L
SPI_HOLD_L
SPI_WP_L
79D5 67D5 67D3 67C3 66C5 65D8
65D2 65D1 65C8 63D8 26C5 25D2 25C8 25B6 24C3 24B3
24A5 23D8 23D4 23D1 23B7 23A7 22D8 22C6 11B5
51D5 51D5
51D5
51B5
5D4
22C6 22C6
22C6
22C6
V+
V-
G
D
S
IN
OUT
NC
CNTRL
THRML_PAD
VDD
SW
AGNDPGND
FB
VOUT
IN
IN
OUT
OUT
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
Left ALS circuit has 1K series-R
Left ALS Filter
Keyboard LED Driver
NC
NC
Right ALS Circuit
RTALS_OP_IN and RTALS_OP_COMP need to be matched
CRITICAL
SOT23-6-LF
MAX4236EUTT
U6405
3
4
1
5
6
2
0.1UF
10V
20%
402
CERM
C6405
1
2
1/16W
5%
402
MF-LF
120K
R6406
1
2
6.3V
20%
402
X5R
0.22UF
C6406
1
2
1/16W
1%
402
MF-LF
15.0K
R6407
1
2
1/16W
1%
402
MF-LF
1K
R6408
1
2
1K
1/16W
1%
402
MF-LF
R6401
1 2
CRITICAL
TH
BS520EOF
PD6400
1
2
1/16W
5%
402
MF-LF
5.1M
R6400
1
2
402
16V
20%
CERM
0.01UF
C6400
1
2
SOT23-LF
2N7002
Q6408
3
1
2
1/16W
1%
402
MF-LF
4.53K
R6410
1 2
402
6.3V
20%
X5R
0.22UF
C6410
1
2
CRITICAL
LLP
MM3120
U6450
2
3
46
5
7
9
1
8
CRITICAL
3.8x3.8x1.5MM
22uH
L6450
1 2
6.3V
10%
402
CERM
1uF
C6450
1
2
1/16W
5%
402
MF-LF
10K
KBDLED_NOT
R6451
1
2
402
10K
KBDLED_HAS
1/16W
5%
MF-LF
R6452
1
2
603
X5R
25V
20%
0.22uF
C6455
1
2
MF-LF
1/8W
1%
805
25.5
R6455
1
2
0.22UF
X5R
402
20%
6.3V
C6430
1
2
3.48K
MF-LF
402
1%
1/16W
R6430
1 2
06004051-7164
8757
ALS Support
SYNC_MASTER=(MASTER)
SYNC_DATE=(MASTER)
RTALS_GAIN
RTALS_OP_COMP
PP3V3_S3
ALS_RT_OUT
ALS_RIGHT
GND_SMC_AVSS
RTALS_OP_IN
RTALS_PHOTODIODE
RTALS_GAIN_L
SMC_SYS_KBDLED
PP3V3_S0
KBDLED_RETURN
KBDLED_ANODE
KBDLED_SW
PP5V_S0
GND_SMC_AVSS
LTALS_OUT
ALS_LEFT
82D5 82C6 82B3 82A4
79D3 79A8 71D2 67C5 67C3 67B3 67A3 66B6 66B5
66B1 65D6 65B3 62A6 61D8 61A5 60D4 60C7 58C7
58C4 54D4 54B5 52D3 49C7 49C4 49B5 40B6 36D6 34A8
33D8 33D3 33C7 29A6 29A3 28A6 27D8 27D5 27D3 27C3
26D1 26B8 26B6 26B4 25D8 25D3 25C6 25C4 25B8
81D4
25B4
81A5
25A4
81B3
67C5
24D3
80B5
67C3
24C3
80A1
66C6
24B5
79B8
65D1
24B3
71A6
63B7
23D5
67B3
60C2
23B3
67B1
59C6
22B5
67A1
52B1
21D3
66B5
46D6
57C6
21C3
62B1
57C2
46C3
55D6
20B4
61D7
55D6
46B3
55C6
20A4
58C7
55C6
41C5
55C1
19C7
58C4
55C1
37D7
55B7
19C6
55A8
55B7
37D5
55B5
17C6
53C4
55B5
37C3
55B3
14D6
36D6
55B3
37A7
55B1
14C7
31C5
55B1
32C5
52B6
10C5
25D8
52B6
27C5
51C4
5D4
5D4
51C4
48C3
6D4
5D4
51A7
51B2
51C7
5A4
81C3
81C3
5D2
51B2
5C1
51A7
G
S D
G
S D
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
NC
NC
Right Fan
NC
NC
Left Fan
518S0369 518S0369
1/16W
5%
MF-LF
402
47K
R6550
1
2
47K
402
MF-LF
1/16W
5%
R6555
1 2
47K
5%
1/16W
MF-LF
402
R6560
1
2
5%
1/16W
MF-LF
402
47K
R6565
1 2
100K
1/16W
5%
MF-LF
402
R6551
1
2
M-RT-SM
SM04B-ACH
CRITICAL
J6550
5
6
1
2
3
4
SM04B-ACH
CRITICAL
M-RT-SM
J6560
5
6
1
2
3
4
SOT-363
2N7002DW-X-F
Q6560
3
5
4
402
MF-LF
5%
1/16W
100K
R6561
1
2
2N7002DW-X-F
SOT-363
Q6560
6
2
1
58 87
051-7164 06004
Fan Connectors
SYNC_MASTER=(MASTER)
SYNC_DATE=(MASTER)
FAN_LT_PWM
SMC_FAN_0_TACH
FAN_RT_TACH
FAN_RT_PWM
PP5V_S0PP5V_S0
FAN_LT_TACH
PP3V3_S0 PP3V3_S0
SMC_FAN_0_CTL SMC_FAN_1_CTL
SMC_FAN_1_TACH
82D5 82D5 82C6 82C6 82B3 82B3 82A4 82A4 79D3 79D3 79A8 79A8
71D2 71D2 67C5 67C5 67C3 67C3 67B3 67B3 67A3 67A3 66B6 66B6 66B5 66B5 66B1 66B1 65D6 65D6
65B3 65B3 62A6 62A6 61D8 61D8 61A5 61A5 60D4 60D4 60C7 60C7 58C4 58C7 57B6 57B6 54D4 54D4
54B5 54B5 52D3 52D3 49C7 49C7 49C4 49C4 49B5 49B5 40B6 40B6 36D6 36D6 34A8 34A8 33D8 33D8
33D3 33D3 33C7 33C7 29A6 29A6 29A3 29A3 28A6 28A6 27D8 27D8 27D5 27D5 27D3 27D3 27C3 27C3
26D1 26D1 26B8 26B8 26B6 26B6 26B4 26B4 25D8 25D8 25D3 25D3 25C6 25C6 25C4 25C4 25B8 25B8 25B4 25B4
81B3 81B3
25A4 25A4
80B5 80B5
24D3 24D3
80A1 80A1
24C3 24C3
79B8 79B8
24B5 24B5
71A6 71A6
24B3 24B3
67B3 67B3
23D5 23D5
67B1 67B1
23B3 23B3
67A1 67A1
22B5 22B5
66B5 66B5
21D3 21D3
62B1 62B1
21C3 21C3
61D7 61D7
20B4 20B4
58C7 58C4
20A4 20A4
57B5 57B5
19C7 19C7
55A8 55A8
19C6 19C6
53C4 53C4
17C6 17C6
36D6 36D6
14D6 14D6
31C5 31C5
14C7 14C7
25D8 25D8
10C5 10C5
5D4 5D4
5D4 5D4
5D2
51B7
5D2
5D2
5D2 5D2
5D2
5A4 5A4
51B7 51B7
51B7
CS*
SCL/SCLK
ADDR/SDI
MOT_ENABLE
ENABLE
VDD
X
Y
Z
FF/MOT
SDA/SDO
GND
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
M59 placement: Bottom-side
+Y
+X
+Z (up)
1
Package Top
Top-through View
+Y
+Z (dn)
+X
Desired orientation whenDesired orientation when
1
placed on board top-side:
placed on board bottom-side:
APN:338S0354
10V
20%
402
CERM
0.1uF
C6620
1
2
0.033UF
X7R
402
20%
10V
C6605
1
2
0.033UF
X7R
402
20%
10V
C6606
1
2
KXPS5-2050
CRITICAL
LGA
U6620
3
2
6
11
10
12
5
4
11314
7
8
9
1/16W
5%
402
MF-LF
10K
R6620
1
2
10V
20%
402
X7R
0.033UF
C6604
1
2
SYNC_DATE=09/15/2006
SYNC_MASTER=M59_MLB
Sudden Motion Sensor (SMS)
051-7164 06004
8759
TP_SMS_FF
SMS_Z_AXIS
SMS_Y_AXIS
SMS_X_AXIS
PP3V3_S3
SMS_ONOFF_L
81D4
81A5 67C5 67C3 66C6 65D1 63B7 60C2 57D4 52B1 46D6
46C3 46B3 41C5 37D7 37D5 37C3 37A7 32C5 27C5
51A7
51B7
51B7
5D4
51A5
IN
IO
IO
IO
LAD1
LAD2
LCLK
LFRAME*
LRESET*
LPCPD*
SERRIRQ
LAD0
CLKRUN/GPIO*
PP/GPIO
GPIO_EXPRESS_00
GPIO/SM_DAT
GPIO/SM_CLK
XTALI/32K_IN
TESTBI/BADD/GPIO
TESTI
3V0
3V1
3V2
3VSB
VNC
VBAT
XTALO
GND2
GND3
GND0
GND1
LAD3
IO
IO
IN
IN
IO
IN
IN
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
VSB
BASE ADDR = 0X4E/4F
GPIO2
TESTBI/BADD
1/8W (R6704/R6705) IS USED FOR NOW
SINCE CURRENT OF VSB IS NOT YET ON SPEC,
NOTE:
PLACE R6702-03 WHERE ACCESSIBLE
LAYOUT NOTE:
PLACE WHERE ACCESSIBLE
LAYOUT NOTE:
BASE ADDR = 0X2E/2F
NC
NC
NC
CLKRUN*
GPIO
PP
NC
VDD
VDD
VDD
NC
NC
GND
(INT PD)
0.1UF
10%
16V
X5R
402
TPM
C6700
1
2
10%
16V
X5R
402
0.1UF
TPM
C6701
1
2
402
X5R
16V
10%
0.1UF
TPM
C6702
1
2
402
X5R
16V
10%
0.1UF
TPM
C6703
1
2
402
MF-LF
1/16W
5%
0
NOSTUFF
R6700
1
2
OMIT
TSSOP
TPM
U6700
10
19
24
5
15
4
111825
2
1
6
26
23
20
17
21
22
28
16
7
27
9
8
12
3
13
14
402
10K
5%
1/16W
MF-LF
TPM
R6702
1
2
402
10K
MF-LF
1/16W
5%
NOSTUFF
R6703
1
2
0
5%
1/8W
MF-LF
805
TPM
R6704
1 2
0
5%
1/8W
MF-LF
805
NOSTUFF
R6705
1
2
402
1/16W
MF-LF
5%
0
TPM
R6798
1 2
402
1/16W
NOSTUFF
0
5%
MF-LF
R6799
1 2
8760
06004051-7164
TPM
SYNC_DATE=09/15/2006
SYNC_MASTER=M59_MLB
SMC_TPM_RESET_L
TPM_LRESET_L
PP3V3_S0
PP3V3_S3
LPC_AD<3>
TPM_XTALO
MIN_NECK_WIDTH=0.15MM
MIN_LINE_WIDTH=0.6MM
VOLTAGE=3.3V
PP3V3_TPM_3VSB
PP3V3_S0
TPM_BADD
TPM_XTALI
TPM_GPIO2
TPM_GPIO1
TPM_PP
PM_CLKRUN_L
LPC_AD<0>
INT_SERIRQ
PM_SUS_STAT_L
TPM_RST_L
LPC_FRAME_L
PCI_CLK_TPM
LPC_AD<2>
LPC_AD<1>
82D5
82D5
82C6
82C6
82B3
82B3
82A4
82A4
79D3
79D3
79A8
79A8
71D2
71D2
67C5
67C5
67C3
67C3
67B3
67B3
67A3
67A3
66B6
66B6
66B5
66B5
66B1
66B1
65D6
65D6
65B3
65B3
62A6
62A6
61D8
61D8
61A5
61A5
60D4
60C7
58C7
58C7
58C4
58C4
57B6
57B6
54D4
54D4
54B5
54B5
52D3
52D3
49C7
49C7
49C4
49C4
49B5
49B5
40B6
40B6
36D6
36D6
34A8
34A8
33D8
33D8
33D3
33D3
33C7
33C7
29A6
29A6
29A3
29A3
28A6
28A6
27D8
27D8
27D5
27D5
27D3
27D3
27C3
27C3
26D1
26D1
26B8
26B8
26B6
26B6
26B4
26B4
25D8
25D8
25D3
25D3
25C6
25C6
25C4
25C4
25B8
25B8
25B4
81D4
25B4
25A4
81A5
25A4
24D3
67C5
24D3
24C3
67C3
24C3
24B5
66C6
24B5
24B3
65D1
24B3
23D5
63B7
23D5
23B3
59C6
23B3
22B5
57D4
22B5
21D3
52B1
21D3
21C3
46D6
21C3
20B4
46C3
20B4
20A4
46B3
20A4
19C7
41C5
19C7
19C6
37D7
19C6
17C6
37D5
17C6
14D6
37C3
14D6
53B5
14C7
37A7
53C5
14C7
53C4
53C4
53C5
52A2
53C4
53C5
53C4
10C5
32C5
51C7
10C5
51C5
51D7
51C7
51C5
51C7
51C7
51D7
26B1
5D4
27C5
21D4
5D4
23C8
21D4
23C8
23C5
21C5
21D4
21D4
52B2
5C4
5A4
5D4
5C2
35D5
5A4
35C5
52C3
52C3
52B3
5C2
5D2
5C2
5C2
5C2
34D6
5C2
5C2
IN
IN
IN
IN
OUT
IN
OUT
OUT
V-
V+
+
-
NC
VW
COMP
FB
FB2
RBIAS
VR_TT*
NTC
VR_ON
PGOOD
CLK_EN*
PGD_IN
PSI*
RTN
VSEN
DFB
DROOP
VO
OCSET
VSUM
ISEN2
VID0
VID1
VID3
VID2
VID4
VID5
VID6
PGND2
VIN VDD
PVCC
LGATE2
PHASE2
UGATE2
ISEN1
PGND1
LGATE1
UGATE1
PHASE1
BOOT1
BOOT2
3V3
DPRSTP*
VDIFF
SOFT
DPRSLPVR
TPAD
GND
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
<Ra + Rb>
Vout = Gain * ((2.1 mV/A * Iload) + Voffset)
(IMVP6_VO)
(IMVP6_PHASE2)
(IMVP6_ISEN1)
These caps for Q7500 These caps for Q7550
0 1 0 1-Phase CCM
0 1 1 2-Phase CCM
(IMVP6_NTC)
CPU VCore Current Sense
<Rc>
Vout @ 36A = 2.44V-2.60V
Gain = Rc / (Ra + Rb)
Voffset worst-case ~2.3mV (+/- ~1A offset)
Voffset = (Vdrp_offset * Kdroop) + Vamp_offset
<Rc>
(IMVP6_VO)
(IMVP6_VSUM)
<Ra>
(IMVP6_ISEN2)
<Rb>
(IMVP6_VW)
(GND)
(GND_IMVP6_SGND)
(IMVP6_COMP)
DPRSLPVR DPRSTP* PSI* Operation Mode
1 0 1 1-Phase DCM
36A max output
(Inductors limit)
Vout = Variable
(IMVP6_PHASE2)
1 1 0 1-Phase DCM
(GND)
(GND_IMVP6_SGND)
(IMVP6_FB)
402
CERM
NO STUFF
10%
0.0022UF
50V
C7501
1
2
NO STUFF
CERM
402
50V
10%
0.0022UF
C7502
1
2
402
10K
MF-LF
1/16W
1%
R7505
1 2
0.22UF
20%
X5R
6.3V
402
C7505
1 2
603
1/10W
1%
MF-LF
3.65K
R7506
1
2
147K
1%
1/16W
402
MF-LF
R7532
1
2
10%
402
0.015uF
16V
X7R
C7532
1
2
0.1uF
10%
402
X5R
16V
C7531
1
2
1.82K
402
1%
1/16W
MF-LF
R7535
1
2
4.42K
402
1%
MF-LF
1/16W
R7537
1
2
5%
CERM
50V
47pF
402
C7537
1
2
107K
1/16W
402
MF-LF
1%
R7534
1
2
470pF
CERM
402
10%
50V
C7535
1
2
25V
X5R
603
0.22uF
20%
C7500
1
2
603
X5R
25V
0.22uF
20%
C7550
1
2
402
1/16W
1%
MF-LF
13.7K
R7542
1
2
1/16W
1%
402
MF-LF
3.01K
R7540
1 2
402
MF-LF
1K
1%
1/16W
R7541
1
2
180pF
5%
402
CERM
50V
C7540
1
2
499
1%
1/16W
402
MF-LF
R7545
1 2
5C4 7B3
21C4
5B4
14B7 23C3 87C6
7A3
5C4
65B8 66B2 66B3 66B5
26A7 26A8 33A4
5C4
51D7
5A4
14B6 26B5
10K
402
1%
MF-LF
1/16W
R7555
1 2
20%
6.3V
X5R
402
0.22UF
C7555
1 2
1/10W
603
3.65K
1%
MF-LF
R7556
1
2
0.0022UF
CERM
10%
50V
402
NO STUFF
C7552
1
2
402
CERM
0.0022UF
10%
50V
NO STUFF
C7551
1
2
1uF
10%
402
6.3V
CERM
C7530
1
2
1/16W
5%
10
402
MF-LF
R7530
1 2
402
1%
2.0K
NO STUFF
MF-LF
1/16W
R7536
1
2
301
1%
1/16W
402
MF-LF
R7533
1
2
820pF
CERM
402
10%
50V
C7533
1
2
6.3V
402
0.22uF
X5R
20%
C7544
1
2
402
11K
1/16W
1%
MF-LF
R7543
1
2
MF-LF
1/16W
1%
30.1K
402
R7593
1 2
30.1K
1%
402
1/16W
MF-LF
R7591
1 2
X5R
10%
1uF
16V
603
C7528
1
2
4.7uF
CERM
6.3V
20%
603
C7529
1
2
MF-LF
402
1/16W
10
5%
R7531
1 2
1/16W
5%
10
402
MF-LF
R7528
1 2
CERM
16V
10%
0.01uF
402
C7546
1
2
402
1/16W
1%
4.02K
MF-LF
R7547
1
2
402
MF-LF
1/16W
1%
499
R7544
1
2
20%
6.3V
X5R
402
0.22UF
C7541
1
2
10%
CERM
402
0.0068uF
25V
C7580
1
2
NO STUFF
0.001uF
50V
10%
402
CERM
C7542
1
2
402
1%
1/16W
MF-LF
5.23K
R7548
1
2
0.01uF
10%
16V
CERM
402
C7543
1
2
402
5%
1
1/16W
MF-LF
R7507
1
2
402
1
MF-LF
1/16W
5%
R7557
1
2
NO STUFF
CERM
10%
16V
0.01uF
402
C7581
1
2
402
CERM
0.01uF
16V
10%
C7582
1
2
1/16W
MF-LF
5%
402
0
R7581
1 2
5%
1/16W
MF-LF
402
0
R7582
1 2
MF-LF
1/16W
1%
1M
402
R7598
1 2
1/16W
402
MF-LF
1M
1%
R7592
1 2
55B8
1uF
402
10%
6.3V
CERM
C7595
1
2
CRITICAL
10KOHM-5%
0603-LF
R7549
1
2
10%
402
CERM
50V
470pF
C7598
1 2
10%
50V
CERM
470pF
402
C7592
1 2
CERM
50V
10%
402
820pF
C7534
1
2
CRITICAL
470K
402
R7546
1
2
CRITICAL
0.36uH-30A-1.2M-OHM
SM-IHLP
L7505
1 2
CRITICAL
SM-IHLP
0.36UH-30A-1.2M-OHM
L7555
1 2
MF-LF
402
0
5%
1/16W
R7594
1 2
402
CERM
10V
20%
NO STUFF
0.1uF
C7594
1
2
SM
XW7530
12
603
10%
1uF
16V
X5R
C7511
1
2
CRITICAL
16V
20%
33uF
POLY
CASED2E-SM
C7510
1
2
10%
1uF
16V
X5R
603
C7561
1
2
CRITICAL
CASED2E-SM
20%
33uF
16V
POLY
C7560
1
2
RJK0305DPB
LFPAK
CRITICAL
Q7500
5
4
1 2 3
LFPAK
RJK0305DPB
CRITICAL
Q7550
5
4
1 2 3
RJK0301DPB
CRITICAL
LFPAK
Q7501
5
4
1 2 3
CRITICAL
RJK0301DPB
LFPAK
Q7502
5
4
1 2 3
LFPAK
RJK0301DPB
CRITICAL
Q7551
5
4
1 2 3
LFPAK
RJK0301DPB
CRITICAL
Q7552
5
4
1 2 3
CRITICAL
16V
20%
33uF
POLY
CASED2E-SM
C7515
1
2
CRITICAL
HPA00141AIDCKR
SC70-5
U7595
1
3
4
2
5
OMIT
QFN
ISL9504CRZ
U7530
48
36
26
47
10
17
45
46
16
11
12
21
24
23
32
30
25
6
8
3
33
29
1
34
28
2
31
4
15
7
49
35
27
22
13
37
38
39
40
41
42
43
20
18
44
5
14
19
9
051-7164 06004
61 87
SYNC_DATE=09/15/2006
SYNC_MASTER=M59_MLB
IMVP6 CPU VCore Regulator
MIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.25 mm
VOLTAGE=12V
PPVIN_S0_IMVP6_R
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=5V
MIN_LINE_WIDTH=0.25 mm
PP5V_S0_IMVP6_VDD
PP5V_S0
IMVP6_VID<4>
GND_IMVP6_SGND
IMVP6_VID<5>
MIN_LINE_WIDTH=0.25 mm
PP3V3_S0_IMVP6_R
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=3.3V
IMVP6_VID<6>
PM_DPRSLPVR
IMVP6_VW
IMVP6_COMP
IMVP6_FB
IMVP6_FB2
IMVP6_RBIAS
IMVP6_VR_TT
IMVP6_NTC
IMVP_VR_ON
VR_PWRGOOD_DELAY
VR_PWRGD_CK410_L
P1V5P1V05S0_PGOOD
CPU_PSI_L
IMVP6_VSEN_N
IMVP6_VSEN_P
IMVP6_DFB
IMVP6_DROOP
IMVP6_VO
IMVP6_OCSET
IMVP6_VSUM
IMVP6_ISEN2
IMVP6_VID<0>
IMVP6_VID<1>
IMVP6_VID<3>
IMVP6_VID<2>
IMVP6_LGATE2
MIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.5 mm
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
IMVP6_PHASE2
IMVP6_UGATE2
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
IMVP6_ISEN1
MIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.5 mm
IMVP6_LGATE1
MIN_NECK_WIDTH=0.25 mm
IMVP6_UGATE1
MIN_LINE_WIDTH=0.5 mm
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
IMVP6_PHASE1
IMVP6_BOOT1
IMVP6_BOOT2
CPU_DPRSTP_L
IMVP6_VDIFF
IMVP6_SOFT
IMVP_DPRSLPVR
IMVP6_COMP_RC
PPBUS_G3H
PPVCORE_S0_CPU
IMVP6_NTC_R
PP3V3_S0
PPBUS_G3H
CPUISENS_NEG_RC
CPU_VCCSENSE_N
CPU_VCCSENSE_P
IMVP6_VO_R
IMVP6_VDIFF_RC
PP3V3_S0
CPUVCORE_IOUT
CPUISENS_POS
IMVP6_DROOP
CPUISENS_NEG
82D5
82D5
82C6
82C6
82B3
82B3
82A4
82A4
79D3
79D3
79A8
79A8
71D2
71D2
67C5
67C5
67C3
67C3
67B3
67B3
67A3
67A3
66B6
66B6
66B5
66B5
66B1
66B1
65D6
65D6
65B3
65B3
62A6
62A6
61A5
61D8
60D4
60D4
60C7
60C7
58C7
58C7
58C4
58C4
57B6
57B6
54D4
54D4
54B5
54B5
52D3
52D3
49C7
49C7
49C4
49C4
49B5
49B5
40B6
40B6
36D6
36D6
34A8
34A8
33D8
33D8
33D3
33D3
33C7
33C7
29A6
29A6
29A3
29A3
28A6
28A6
27D8
27D8
27D5
27D5
27D3
27D3
27C3
27C3
26D1
26D1
26B8
26B8
26B6
26B6
26B4
26B4
25D8
25D8
25D3
25D3
25C6
25C6
25C4
25C4
25B8
25B8
25B4
25B4
81B3
25A4
25A4
80B5
24D3
24D3
80A1
79B7
24C3
79B7
24C3
79B8
71D7
24B5
71D7
24B5
71A6
69C1
24B3
69C1
24B3
67B3
68D5
23D5
68D5
23D5
67B1
67C3
23B3
67C3
23B3
67A1
67C1
22B5
67C1
22B5
66B5
65D6
21D3
65D6
21D3
62B1
65B7
21C3
65B7
21C3
58C7
64D7
20B4
64D7
20B4
58C4
64A6
20A4
64A6
20A4
57B5
62D7
67D3
19C7
62D7
19C7
55A8
61D7
67D1
19C6
61D4
19C6
53C4
55D3
55D7
17C6
55D3
17C6
36D6
43D8
55A6
14D6
43D8
14D6
31C5
42B8
9D7
14C7
42B8
14C7
25D8
41C6
8D7
10C5
41C6
10C5
5D4
9C1
9C1
9C1
9C1
9C1
9C1
9C1
87C6
5C4
8B5
5D4
5C4
87B6
87B6
5D4
5D2
5C4
5C4
5C4
5D7
87B6
87B6
61A2
5C4
5C4
5C4
5C4
5C4
5A1
5B2
5A4
5A1
8B6
8B6
5A4
61C6
NC4
NC3
NC2
NC1
EXTVCC
FCB
INTVCC
PGOOD
3_3VOUT
RUN_SS2
ITH2
RUN_SS1
ITH1
SW1
TG1
BOOST1
BG1
PLLIN
SENSE1+
SENSE1-
VOSENSE1
BOOST2
TG2
BG2
SW2
PLLFLTR
SENSE2+
VOSENSE2
SENSE2-
THRML_PAD
SGND
PGND
VIN
D
S
G
D
S
G
D
S
G
R1-
R1+
R2
V-
V+
+
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
Connect to RUNSS pins to control outputs.
<Ra>
Vout = 4.98V
NC
NC
NC
<Ra>
<Rb>
Vout = 1.49V
8A max output
(L7660 & Q7660 limit)
If unconnected, powers up with VIN.
<Rb>
NOTE: Be aware of pull-ups to VIN on these signals.
NC
NC
NC
Vout = 0.8V * (1 + Ra / Rb)
5V S0 FET
5V S3 FET
Placement Note:
PLACE C7675 NEAR U7670 PIN 7
11.5A max output
(Q7621 limit)
CRITICAL
CMDSH-3
SOD-323
D7624
1
2
1uF
CERM
402
10%
6.3V
C7605
1
2
16V
10%
402
0.01uF
CERM
C7607
1
2
MF-LF
1/16W
5%
402
1M
R7630
1
2
CERM
20%
0.1uF
402
10V
C7630
1
2
470pF
50V
10%
402
CERM
C7625
1
2
50V
5%
402
47pF
CERM
C7626
1
2
10
402
1/16W
MF-LF
5%
R7600
1
2
10%
X5R
603
1uF
16V
C7600
1
2
LTC3728LXC
QFN
CRITICAL
U7600
7
18
17
21
4
20
5
8
10
16
29
32
19
27
2
28 13
30 12
11
6
15
26
14
33
1 9
CRITICAL
CMDSH-3
SOD-323
D7664
1
2
10V
20%
402
CERM
0.1uF
C7670
1
2
470pF
10%
CERM
50V
402
C7665
1
2
100pF
CERM
402
5%
50V
C7666
1
2
10K
MF-LF
402
5%
1/16W
R7665
1
2
CERM
50V
0.001uF
402
10%
C7662
1
2
52.3K
1/16W
402
MF-LF
1%
R7627
1
2
25V
402
X7R
1000pF
10%
NO STUFF
C7628
1
2
10K
1/16W
MF-LF
402
1%
R7628
1
2
IHLP2525CZ-SM
2.2uH-14A
CRITICAL
L7660
1 2
402
1%
1/16W
MF-LF
39.2K
R7668
1
2
NO STUFF
25V
10%
402
X7R
1000pF
C7668
1
2
34.0K
1/16W
1%
MF-LF
402
R7667
1
2
50V
10%
402
CERM
470pF
C7667
1
2
MF-LF
1/16W
5%
402
1M
R7670
1
2
402
6.3V
10%
1uF
CERM
C7602
1
2
603
6.3V
20%
4.7uF
CERM
C7601
1
2
30K
MF-LF
402
5%
1/16W
R7603
1
2
10K
MF-LF
402
5%
1/16W
R7604
1
2
CERM
402
10%
16V
0.01uF
C7604
1
2
10%
1uF
16V
X5R
603
C7641
1
2
MF-LF
402
1/16W
0
5%
R7664
1
2
MF-LF
0
402
5%
1/16W
R7624
1
2
NO STUFF
10%
X7R
402
1000pF
25V
C7661
1
2
402
CERM
10V
20%
0.1uF
C7664
1
2
805
CERM
6.3V
20%
22UF
C7690
1
2
805
CERM
6.3V
20%
22UF
C7691
1
2
0.1uF
20%
10V
CERM
402
C7624
1
2
NO STUFF
1000pF
402
X7R
25V
10%
C7621
1
2
10%
CERM
50V
402
0.001uF
C7622
1
2
6.3V
POLY
CRITICAL
20%
150UF
CASE-C3
C7652
1
2
20%
22UF
6.3V
CERM
805
C7650
1
2
CERM
805
22UF
20%
6.3V
C7651
1
2
1/16W
5%
402
MF-LF
0
P5VP1V5_SKIP
R7606
1
2
P5VP1V5_CONT
0
MF-LF
402
5%
1/16W
R7607
1
2
SM
XW7600
1 2
16V
X5R
402
10%
0.1uF
C7620
1
2
0.1uF
10%
16V
X5R
402
C7623
1
2
1%
402
MF-LF
1/16W
4.02K
R7623
1
2
10%
16V
X5R
402
0.1uF
C7660
1
2
1%
402
1/16W
MF-LF
3.65K
R7660
1
2
402
X5R
16V
10%
0.1uF
C7663
1
2
1%
909
402
MF-LF
1/16W
R7663
1
2
20%
POLY
CRITICAL
330UF
CASE-D2E-LF
2.5V
C7692
1
2
IRF7832Z
SO-8
CRITICAL
Q7661
5 6 7 8
4
1 2 3
MF-LF
1/16W
402
1%
1.21K
R7669
1
2
1%
MF-LF
1/16W
402
23.7K
R7629
1
2
20%
6.3V
CERM
805
22UF
C7617
1
2
20%
6.3V
CERM
805
22UF
C7616
1
2
0.0022uF
402
CERM
50V
10%
C7615
1
2
100K
5%
1/16W
MF-LF
402
R7615
1 2
FDC638P
SM-LF
CRITICAL
Q7610
1
2
5
6
3
4
0.0022uF
402
CERM
10%
50V
C7610
1 2
MF-LF
1/16W
5%
402
100K
R7610
1 2
CRITICAL
MICROFET3X3
FDM6296
Q7621
5
4
123
MICROFET3X3
FDM6296
CRITICAL
Q7620
5
4
123
MICROFET3X3
FDM6296
CRITICAL
Q7660
5
4
1 2 3
CASED2E-SM
POLY
16V
20%
33uF
CRITICAL
C7640
1
2
1uF
10%
16V
X5R
603
C7681
1
2
CASED2E-SM
POLY
33uF
20%
16V
CRITICAL
C7680
1
2
SM-IHLP
2.0UH
CRITICAL
L7620
1 2
IRF7707PBF
TSSOP
CRITICAL
Q7615
1 5 8
4
2 3 6 7
402
MF-LF
1/16W
1%
10
R7671
1 2
10%
16V
0.1UF
402
X5R
C7675
1
2
0.001UF
10%
50V
CERM
402
C7674
1
2
INA326EA-250
MSOP
CRITICAL
U7670
3
2
6
1
8
5
4
7
100K
1%
1/16W
402
MF-LF
R7674
1
2
22UF
805
20%
CERM
6.3V
C7671
1
2
22UF
20%
6.3V
805
CERM
C7672
1
2
0.002
1%
1/4W
MF-LF
1206
R7675
1 2
402
MF-LF
1/16W
1%
2.0K
R7672
1
2
4.53K
1%
402
MF-LF
1/16W
R7620
1
2
33K
MF-LF
5%
1/16W
402
R7625
1
2
47PF
5%
CERM
50V
402
C7627
1
2
SYNC_MASTER=M59_MLB
SYNC_DATE=09/15/2006
051-7164 06004
8762
5V / 1.5V Power Supply
P5VS0_EN_L_RC
PP5V_S5
P5VS5_VOSNS
P5VS5_ITH_RC
MIN_LINE_WIDTH=0.6 mm
VOLTAGE=0V
MIN_NECK_WIDTH=0.25 mm
GND_P5VP1V5_SGND
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm
P5VS5_SNS_P
P5VS5_SW
MIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.6 mm
NB1V5_ISENSE_R1_N
NB1V5_ISENSE_R1_P
PP5V_S0
PP1V5_S0_NB
PP5V_S5
P5VP1V5_FCB
VOLTAGE=5V
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm
PP5V_S5_P5VP1V5_INTVCC
TP_P5V_P1V5_PGOOD
P1V5S0_RUNSS
P1V5S0_ITH
P5VS5_RUNSS
P5VS5_ITH
P5VS5_TG
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.6 mm
VOLTAGE=12V
MIN_NECK_WIDTH=0.25 mm
PPVIN_S5_P5VP1V5_R
MIN_LINE_WIDTH=0.6 mm
P5VS5_BOOST
MIN_NECK_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.6 mm
P5VS5_BG
MIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.6 mm
P5VS5_SNS_N
P1V5S0_BOOST
MIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.6 mm
P1V5S0_TG
P5VP1V5_FSEL
MIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.6 mm
P1V5S0_SNS_R_P
P1V5S0_VOSNS
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm
P1V5S0_SNS_R_N
PP3V3_S0
PM_SLP_S4_LS5V
P5VS3_EN_L_RC
PP5V_S3PP5V_S5
PM_SLP_S3_LS5V
PP5V_S5
PP1V5_S0
MIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.6 mm
P1V5S0_BOOST_RC
P5VS5_BOOST_RC
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm
PPBUS_G3H
P5VP1V5_FSEL
PP5V_S5_P5VP1V5_INTVCCPP5V_S5_P5VP1V5_INTVCC
P1V5S0_ITH_RC
P1V5S0_BG
MIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.6 mm
P1V5S0_SW
MIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.6 mm
P1V5S0_NB_IOUT
NB1V5_ISENSE_R2
NB1V5_ISENSE_VCC
PP1V5_S0
82D5
82C6 82B3 82A4 79D3 79A8 71D2 67C5 67C3 67B3 67A3
66B6 66B5 66B1 65D6 65B3 61D8 61A5 60D4 60C7 58C7
58C4 57B6 54D4 54B5 52D3 49C7 49C4 49B5 40B6 36D6
34A8 33D8 33D3 33C7 29A6 29A3 28A6 27D8 27D5 27D3
27C3 26D1 26B8 26B6 26B4 25D8 25D3 25C6 25C4 25B8
25B4
81B3
67C8
25A4
80B5
67C6
24D3
67C8
67C8
80A1
67B6
24C3
67C6
79B7
67C6
79B8
19D7
24B5
66C5
71D7
66C5
71D7
71A6
19D6
71D7
24B3
71D7
71D7
62A8
69C1
62C1
67C3
67B3
19D5
67C3
23D5
67C3
67C3
48B6
68D5
48B6
67C1
67B1
19D2
67C1
23B3
67C1
67C1
25D6
67C3
25D6
67B1
67A1
19D1
67B1
22B5
67B1
67B1
25C8
67C1
25C8
66D8
66B5
19C5
66D8
21D3
66D8
66D8
25C6
65D6
25C6
66B8
61D7
19C4
66B8
21C3
66B8
66B8
25C2
65B7
25C2
65D6
58C7
19C1
65D6
20B4
65D6
65D6
25B6
64D7
25B6
65B7
58C4
19B8
65B7
20A4
65B7
65B7
25B2
64A6
25B2
64C8
57B5
19B5
64C8
19C7
81C6 64C8
64C8
25A8
61D7
25A8
62B6
55A8
19A5
62C8
19C6
81C4 62C8
62C8
24B5
61D4
24B5
62B2
53C4
17C6
62B2
17C6
67B3 62B6
66C7
62B6
24A5
55D3
24A5
62A4
36D6
17B6
62A4
14D6
67B1 62B2
66C6
62A4
24A3
43D8
24A3
52B5
31C5
16D1
52B5
14C7
52B8 52B5
48C3
52B5
9B7
42B8
9B7
47C7
25D8
13D2
47C7
10C5
66B7
45C3 47C7
6A2
47C7
8B7
41C6
8B7
25C8
5D4
13C5
25C8
62D6
66C2
5D4
66B6
5D4
25C8
6A1
25C8
5D4
5C4
62D6 62D3
5D4
5D4
5D2
5D4
5D4
62D3
66C1
62B3
5A4
65D3
5B2 5D4
5C1
5D4
5D1
5A1
62C4
62B3 62B3
55B5
5D1
SW
SGND PGND
PAD
THERM
SVIN PVIN
PGOOD
VFB
ITH
SYNC/MODE
RUN/SS
RT
THRM_PAD
PVINAVIN
PG
MODE
OVT FB
AGND PGND
SWEN
D
S
G
D
S
G
D
S
G
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
1.5A max output
(U7700 limit)
Vout = 2.50V
1.2V S3 Regulator
2.5A max output
(Switcher limit)
Vout = 1.205V
2.5V S0 FET
Vout = 0.6V * (1 + Ra / Rb)
<Ra>
<Rb>
<Rc>
Vout = 0.8V * (1 + Ra / (Rb + Rc))
If unconnected, powers up with PVIN.
Connect RUNSS off-page to control
NOTE: Be aware of pull-up on this signal.
Burst
Continuous
2.5V S3 Regulator
<Ra>
<Rb>
2.5V D3Cold FET
1.2V D3Cold FET
SM-MSS5131
2.2uH-1.9A-23M-OHM
CRITICAL
L7700
1 2
5%
CERM
402
50V
10pF
C7706
1
2
402
MF-LF
634K
1%
1/16W
R7707
1
2
200K
1/16W
1%
402
MF-LF
R7708
1
2
0.1uF
16V
X5R
10%
402
C7701
1
2
1
MF-LF
402
5%
1/16W
R7700
1 2
22UF
805
20%
6.3V
CERM
C7756
1
2
22UF
CERM
805
20%
6.3V
C7755
1
2
22UF
CERM
805
20%
6.3V
C7752
1
2
805
22UF
CERM
6.3V
20%
C7751
1
2
50V
5%
402
CERM
22pF
C7750
1
2
1/16W
1%
402
MF-LF
47.0K
R7750
1
2
MF-LF
402
1%
1/16W
61.9K
R7751
1
2
SM-LF
CRITICAL
1.0UH-3.48A
L7750
1 2
MF-LF
402
1%
1/16W
30.9K
R7752
1
2
CRITICAL
TSSOP-LF
LTC3412
U7750
3
12
13
2
9
16
5
7
8
1
10
11
14
15
6
17
4
SM
XW7750
1 2
309K
MF-LF
402
1%
1/16W
R7754
1
2
50V
470pF
CERM
402
10%
C7757
1
2
1/16W
5%
402
MF-LF
0
NO STUFF
R7755
1
2
1M
1/16W
5%
402
MF-LF
R7757
1
2
0
MF-LF
402
5%
1/16W
R7756
1
2
CERM
402
5%
50V
22pF
C7754
1
2
MF-LF
402
1%
1/16W
8.25K
R7753
1
2
CERM
402
10%
50V
0.0022uF
C7753
1
2
50V
0.0022uF
10%
CERM
402
C7720
1
2
402
5%
1/16W
MF-LF
100K
R7720
1 2
0.0022uF
10%
50V
402
CERM
C7770
1
2
100K
5%
1/16W
MF-LF
402
R7770
1 2
6.3V
20%
805
CERM
22uF
C7700
1
2
TPS62510
BQA
CRITICAL
U7700
3
9
6
4
7
5
8
2
10
1
11
FDC637AN
SOT23
Q7720
1
2
5
6
3
4
FDC637AN
SOT23
Q7721
1
2
5
6
3
4
402
CERM
10%
0.0022uF
50V
C7721
1
2
160K
402
5%
1/16W
MF-LF
R7721
1 2
CERM
6.3V
20%
805
22UF
C7759
1
2
6.3V
20%
805
CERM
22UF
C7758
1
2
SOT23
FDC637AN
CRITICAL
Q7770
1
2
5
6
3
4
6.3V
20%
22UF
CERM
805
C7710
1
2
6.3V
20%
22UF
CERM
805
C7711
1
2
X7R
50V
0.01UF
402
10%
C7722
1
2
6.3V
20%
22UF
CERM
805
C7709
1
2
SYNC_DATE=09/15/2006
SYNC_MASTER=M59_MLB
2.5V & 1.2V Regulators
06004051-7164
63 87
PP2V5_S3
P2V5S3_VFB
P1V2D3C_EN_RC
PP1V2_D3C
PP1V2_S3
PM_SLP_S3BATT_L
P2V5S3_SW
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
PP3V3_S3
P1V2S3_RT
P1V2S3_VFB_DIV
P1V2S3_ITH_RC
P1V2S3_RUNSS
P1V2S3_MODE
P1V2S3_ITH
MIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.25 mm
VOLTAGE=0V
GND_P1V2S3_SGND
P1V2R2V5D3C_EN_LS5V
TP_P2V5S3_P1V2S3_PGOOD
MIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.6 mm
P1V2S3_SW
P1V2S3_VFB
TP_P2V5S3_P1V2S3_PGOOD
PM_SLP_S3_LS5V_L
PP2V5_S3
P2V5S0_EN_RC
PP2V5_S0
PP2V5_S3
P1V2R2V5D3C_EN_LS5V
PP1V2_S3
PP3V3_S5
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
PPVIN_S3_P2V5S3_SVIN
PP2V5_D3C
P2V5D3C_EN_RC
79D5 67D5 67D3 67C3 66C5
81D4
65D8
81A5
65D2
67C5
65D1
67C3
65C8
66C6
56D4
65D1
26C5
60C2
25D2
59C6
82D3
25C8
57D4
82C5
25B6
52B1
67B6
24C3
46D6
67A8
24B3
46C3
67A6
24A5
46B3
66B5
23D8
82D7
41C5
19D7
23D4
77B8
67D8
37D7
19C5
67D8
23D1
82D7
67B8
70C7
67D6
37D5
67B8 19A8
67B8
67D6
23B7
78C8
67B6
70A1
63B3
37C3
71C8
67B6 19A6
67B6
71C8
63B3
23A7
77C6
63D3
67D8
39D7
37A7
66D8
63D4 19A4
63D4
66D8
39D7
22D8
77A8
63C3
67D6
39A8
32C5
66D7
66B8
66B8
63C3 17D6
63D3
66D7
39A8
22C6
67A8
39D3
67C6
5D4
41C4
27C5
41C4
66D4
66B7
66B7
66D5
39D3 17C6
39D3
66D4
5D4
11B5
67A6
5A4
5D4
5A4
41C3
5D4
5D7
5D7
63C3
63C8
63B5
66D4
5A4 5D4
5A4
63B3
5A4
5D4
41C3
5D4
G
S
D
V5DRV
LL
VOUT
PGOOD
VFB
TRIP
DRVL
DRVH
TON
EN_PSV
VBST
THRM_PAD
GND
PGND
V5FILT
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
Vout = 0.75V * (1 + Ra / Rb)
(L7820 limit)
18A max output
<Rb>
(P1V8S3_FB)
1.8V D3Cold FET
Vout = 1.825V
<Ra>
POLY
CASE-D2E-LF
20%
330UF
2.5V
C7842
1
2
21K
MF-LF
1%
402
1/16W
R7821
1
2
1/16W
402
MF-LF
15K
5%
R7822
1
2
X5R
16V
603
10%
1uF
C7802
1
2
805
6.3V
CERM
22UF
20%
C7841
1
2
POLY
20%
CASE-D2E-LF
330UF
2.5V
C7843
1
2
20%
CERM
805
6.3V
22UF
C7847
1
2
CERM
22UF
805
6.3V
20%
C7846
1
2
25V
0.0047UF
10%
CERM
402
C7845
1
2
150K
402
MF-LF
1/16W
5%
R7845
1 2
5%
47PF
402
CERM
50V
C7820
1
2
402
MF-LF
1/16W
5%
470K
R7846
1
2
FDM6296
MICROFET3X3
CRITICAL
Q7845
5
4
1
2
3
X5R
16V
603
10%
1uF
C7831
1
2
CASED2E-SM
POLY
16V
20%
33uF
C7830
1
2
1uF
10%
603
16V
X5R
C7832
1
2
CRITICAL
LFPAK
RJK0305DPB
Q7820
5
4
1 2 3
CRITICAL
RJK0303DPB
LFPAK
Q7822
5
4
1 2 3
CRITICAL
RJK0303DPB
LFPAK
Q7821
5
4
1 2 3
1.2UH
FDA1055
CRITICAL
L7820
1 2
6.3V
603
4.7UF
CERM
20%
C7801
1
2
10
MF-LF
402
1%
1/16W
R7801
1 2
402
10%
16V
0.1UF
X5R
C7803
1
2
MF-LF
402
1/16W
1%
12.1K
R7804
1
2
1%
1/16W
402
MF-LF
182K
R7803
1
2
6.3V
10%
CERM
1UF
402
C7800
1
2
CRITICAL
QFN
TPS51117RGY_QFN14
U7800
13
9
1
7128
6
15
2
11
10
4
14
5
3
SYNC_MASTER=(MASTER)
SYNC_DATE=(MASTER)
1.8V Supply
051-7164
64 87
06004
PP1V8_S3
SWITCH_NODE=TRUE
MIN_LINE_WIDTH=0.6 mm
P1V8S3_LL
MIN_NECK_WIDTH=0.25 mm
P1V8D3C_EN
PP1V8_S3
P1V8D3C_EN_RC
PPBUS_G3H
PPBUS_G3H
MIN_NECK_WIDTH=0.25 mm
P1V8S3_DRVH
MIN_LINE_WIDTH=0.6 mm
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm
P1V8S3_DRVL
P1V8S3_VBST
P1V8S3_TON
PM_SLP_S4_L
MIN_LINE_WIDTH=0.25 mm
VOLTAGE=5V
MIN_NECK_WIDTH=0.25 mm
P1V8S3_V5FILT
PP5V_S5
P1V8S3_TRIP
TP_P1V8S3_PGOOD
P1V8S3_FB
PP1V8_D3C
79B7
79B7
67B8
67B8
71D7
71D7
67B6
67B6
69C1
69C1
71D7
64A6
64C1
68D5
68D5
67C3
37B2
37B2
67C3
67C3
67C1
32C6
32C6
67C1
67C1
67B1
82D7
31C5
31C5
65D6
65D6
66D8
76D8
29D6
29D6
65B7
65B7
66B8
66B8
76D5
29D3
29D3
64D7
64A6
66A6
65D6
75D8
29B2
29B2
62D7
62D7
51C5
65B7
75D5
28D6
28D6
61D7
61D7
48C3
62C8
73B8
28D3
28D3
61D4
61D4
47C7
62B6
73B5
28B2
28B2
55D3
55D3
41B6
62B2
73A8
19D7
19D7
43D8
43D8
23C3
62A4
73A5
16B6
16B6
42B8
42B8
6A2
52B5
72B8
14C2
14C2
41C6
41C6
6A1
47C7
67B8
5D4
66D6
5D4
5C4
5C4
5C4
25C8
66C2
67B6
5B2
66D5
5B2
5A1
5A1
5C1
5D4
66C1
5D4
PGND
PHASE
UG
LG
PVCC
FCCM
EN
PGOOD
COMP
FSET
ISEN
FB
VO
BOOT
VIN
THRML
PAD
VCC
OUT
D
S
G
D
S
G
D
S
G
V-
V+
+
-
PGND
PHASE
UG
LG
PVCC
FCCM
EN
PGOOD
COMP
FSET
ISEN
FB
VO
BOOT
VIN
THRML
PAD
VCC
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
Placement Note:
Keep C7990, C7991,
R7990, R7994 and R7997
3.3V S0 FET
close to inductor
3.3V D3Cold FET
1.05V Current Sense
1.05V S0 Regulator
3.3V S5 Regulator
Vout = 0.6V * (1 + Ra / Rb)
Vout = 0.6V * (1 + Ra / Rb)
<Rb>
(P1V05S0_FB)
<Ra>
Vout = 1.05V
10A max output
(L7920 limit)
<Ra>
<Rb>
Vout = 3.32V
3.3V S3 FET
4.5A max output
(L7970 limit)
603
X5R
10%
1uF
16V
C7951
1
2
ISL6269BCRZ
CRITICAL
QFN
U7950
13
5
4
6
3
7
9
11
10
16
15
12
17
14
2
1
8
50V
5%
402
CERM
15PF
C7957
1
2
CERM
402
20%
16V
0.01uF
C7958
1
2
MF-LF
402
1%
1/16W
30.9K
R7958
1
2
1/16W
5%
MF-LF
0
NO STUFF
402
R7954
1
2
0
MF-LF
402
5%
1/16W
R7955
1
2
57.6K
1%
402
MF-LF
1/16W
R7956
1
2
16V
10%
402
CERM
0.01UF
C7956
1
2
IRF7832Z
CRITICAL
SO-8
Q7971
5 6 7 8
4
1 2 3
CASE-D2E-LF
POLY
20%
330UF
2.5V
C7989
1
2
470pF
402
50V
CERM
10%
C7998
12
CERM
1uF
402
10%
6.3V
C7995
1
2
402
MF-LF
1/16W
1M
1%
R7998
1 2
50V
470pF
402
CERM
10%
C7992
12
402
MF-LF
1/16W
1M
1%
R7992
1 2
CRITICAL
0603-LF
10KOHM-5%
R7997
1
2
1/16W
MF-LF
402
0
5%
R7996
1
2
1%
20.0K
402
1/16W
MF-LF
R7993
1 2
10%
CERM-X5R
0.47UF
6.3V
402
C7990
12
MF-LF
1%
1/16W
20.0K
402
R7991
1 2
1%
MF-LF
402
1/16W
10K
R7994
1 2
1%
1/16W
402
MF-LF
649
R7990
1
2
55B3
0
402
5%
1/16W
MF-LF
R7949
1 2
20%
16V
0.01uF
402
CERM
NO STUFF
C7949
1
2
402
10%
25V
CERM
0.0047uF
C7920
1
2
0
1/16W
MF-LF
402
5%
R7920
12
CERM
25V
0.0047uF
10%
402
C7947
1 2
FDC638P
SM-LF
Q7947
1
2
5
6
3
4
1/16W
100K
5%
MF-LF
402
R7947
1 2
0.0022uF
402
CERM
50V
10%
C7945
1 2
SM-LF
FDC638P
Q7945
1
2
5
6
3
4
402
MF-LF
1/16W
5%
100K
R7945
1 2
MF-LF
402
1/16W
5%
0
R7909
1
2
6.3V
20%
X5R
402
0.22uF
C7909
1
2
0.22uF
402
X5R
6.3V
20%
C7959
1
2
402
CERM
10%
0.0022uF
50V
NO STUFF
C7970
1
2
402
MF-LF
1/16W
0
5%
NO STUFF
R7970
1
2
MICROFET3X3
CRITICAL
FDM6296
Q7920
5
4
1 2 3
MICROFET3X3
FDM6296
CRITICAL
Q7921
5
4
1 2 3
FDM6296
MICROFET3X3
CRITICAL
Q7970
5
4
1 2 3
CRITICAL
33uF
CASED2E-SM
POLY
16V
20%
C7980
1
2
1/16W
1%
402
5.62K
MF-LF
R7910
1 2
SM-LF
FDC638P
Q7948
1
2
5
6
3
4
402
MF-LF
1/16W
5%
150K
R7948
1 2
10%
25V
CERM
0.0047uF
402
C7948
1
2
1.8UH
SM-IHLP
CRITICAL
L7970
1 2
CRITICAL
33UF
20%
16V
POLY
CASED2E-SM
C7930
1
2
402
6.3V
0.22UF
CERM-X5R
10%
C7991
12
CRITICAL
SC70-5
HPA00141AIDCKR
U7995
1
3
4
2
5
4.7
402
MF-LF
1/16W
5%
R7959
1
2
150UF
CASE-C3
POLY
20%
6.3V
C7942
1
2
603
CERM1
20%
6.3V
2.2UF
C7902
1
2
1000pF
402
X7R
25V
10%
NO STUFF
C7921
1
2
SM
XW7900
1 2
6.3V
2.2UF
CERM1
603
20%
C7900
1
2
1uF
16V
X5R
603
10%
C7901
1
2
QFN
CRITICAL
ISL6269BCRZ
U7900
13
5
4
6
3
7
9
11
10
16
15
12
17
14
2
1
8
10%
470pF
CERM
402
50V
C7907
1
2
0.022uF
CERM-X5R
10%
16V
402
C7908
1
2
MF-LF
5%
0
402
1/16W
NO STUFF
R7904
1
2
51.1K
402
MF-LF
1/16W
1%
R7908
1
2
5%
402
MF-LF
0
1/16W
R7905
1
2
MF-LF
1%
402
57.6K
1/16W
R7906
1
2
0.01UF
CERM
402
10%
16V
C7906
1
2
22UF
805
6.3V
CERM
20%
C7941
1
2
805
22UF
20%
6.3V
CERM
C7940
1
2
1/16W
402
MF-LF
3.32K
0.1%
R7921
1
2
732
402
0.1%
MF-LF
1/16W
R7922
1
2
IHLP
CRITICAL
4.7uH
L7920
1 2
2.2UF
CERM1
603
20%
6.3V
C7952
1
2
20%
22UF
CERM
6.3V
805
C7986
1
2
805
22UF
20%
6.3V
CERM
C7985
1
2
1/16W
1%
402
MF-LF
3.32K
R7971
1
2
1/16W
1%
MF-LF
4.42K
402
R7972
1
2
402
MF-LF
1%
1/16W
2.8K
R7960
1 2
NO STUFF
1000pF
402
X7R
25V
10%
C7971
1
2
SM
XW7950
1 2
2.2UF
CERM1
603
20%
6.3V
C7950
1
2
051-7164
65 87
06004
3.3V / 1.05V Power Supplies
SYNC_MASTER=(MASTER)
SYNC_DATE=(MASTER)
P3V3S0_EN_L_RC
PP3V3_S5
P3V3D3C_EN_L_RC
PPBUS_G3H
P3V3S5_UG
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm
P3V3S5_LG
MIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm
P3V3S5_PHASE
SWITCH_NODE=TRUE
MIN_LINE_WIDTH=0.6 mm
P3V3S5_ISEN
P3V3S5_BOOT_R
MIN_LINE_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.25 mm
P3V3S5_COMP_R
P3V3S5_FCCM
P3V3S5_BOOT
MIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.25 mm
P1V05ISENS_NTC
PP3V3_S5
PP3V3_S3
P3V3S3_EN_L_RCPM_SLP_S4_LS5V
P5VS5_PGOOD
P3V3S5_FB_RC
P1V05S0_COMP_R
GND_P1V05S0_SGND
P1V05S0_FB_RC
P3V3S5_FSET
P3V3S5_COMP
GND_P3V3S5_SGND
P3V3S5_FB
RSMRST_PWRGD
PP5V_S5
P3V3S0_EN_L
PP3V3_S0
PP3V3_D3C
PP3V3_S5
P1V05ISENS_RC
PP3V3_S0
P1V05S0_IOUT
P1V05ISENS_POS
P1V05S0_BOOT_R
MIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.25 mm
P3V3S5_EN_RC
PPBUS_G3H
MIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.25 mm
P1V05S0_BOOT
P1V05S0_FB
P1V05S0_ISEN
P1V05S0_FSET
P1V05S0_COMP
P1V5P1V05S0_PGOOD
PM_SLP_S3_L
P1V05S0_FCCM
PP5V_S5
P1V05S0_LG
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm
P1V05S0_UG
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.6 mm
SWITCH_NODE=TRUE
P1V05S0_PHASE
P3V3D3C_EN_L
PP3V3_S5
PP1V05_S0
P1V05ISENS_NEG
82D5 82C6 82B3
82A4 79D3 79A8 71D2 67C5 67C3 67B3 67A3 66B6
66B5 66B1 65D6 62A6 61D8 61A5 60D4 60C7
58C7 58C4 57B6 54D4 54B5 52D3 49C7 49C4 49B5
40B6 36D6 34A8 33D8 33D3 33C7 29A6 29A3
28A6 27D8
67D8
27D5
67D6
27D3
55A4
27C3
34C8
26D1
34C6
26B8
34B8
26B6
25D3
26B4
25C4
79D5
79D5
79D5
25D8
79D5
24D3
67D5
67D5
67D5
25D3
67D5
24C3
67D3
67D3
67D3
25C6
67D3
21C1
67C3
67C3
67C3
25C4
67C3
19D7
66C5
66C5
66C5
25B8
66C5
19D6
65D8
65D8
81D4
65D2
25B4
65D8
19D5
65D2
65D1
81A5
65D1
25A4
65D2
19D2
65C8
65C8
67C5
65C8
24D3
65D1
19D1
63D8
79B7
63D8
67C3
63D8
24C3
79B7
63D8
19C8
56D4
71D7
56D4
66C6
56D4
24B5
71D7
56D4
17D6
26C5
69C1
26C5
63B7
71D7
26C5
24B3
69C1
71D7
26C5
17D3
25D2
68D5
25D2
60C2
67C3
25D2
23D5
68D5
67C3
25D2
16D3
25C8
67C3
25C8
59C6
67C1
82D7
25C8
23B3
67C3
67C1
25C8
16C8
25B6
67C1
25B6
57D4
67B1
82A7
25B6
22B5
67C1
67B1
25B6
13B5
24C3
65B7
24C3
52B1
66D8
80D5
24C3
21D3
65D6
66D8
24C3
12C2
24B3
64D7
24B3
46D6
66B8
80B2
24B3
21C3
64D7
66C8
66B8
24B3
12B7
24A5
64A6
24A5
46C3
65B7
77D2
24A5
20B4
64A6
66C6
65D6
24A5
12A7
23D8
62D7
23D8
46B3
64C8
77C6
23D8
20A4
62D7
66B6
64C8
23D8
11C5
23D4
61D7
23D4
41C5
62C8
77B7
23D4
19C7
61D7
55C3
62C8
23D4
11B3
23D1
61D4
23D1
37D7
62B6
74D6
23D1
19C6
61D4
51C5
62B6
23D1
9B7
23B7
55D3
23B7
37D5
62B2
74B2
23B7
17C6
55D3
43C8
62B2
23B7
8C7
23A7
43D8
23A7
37C3
62A4
71C4
23A7
14D6
43D8
66B5
42A8
62A4
23A7
7D5
22D8
42B8
22D8
37A7
52B5
71B8
22D8
14C7
42B8
66B3
39C8
52B5
22D8
7B6
22C6
41C6
22C6
32C5
66B7
66A8
52A5
47C7
71A4
22C6
10C5
41C6
66B2
32B3
47C7
22C6
7B5
11B5
5C4
11B5
27C5
66B6
66A6
52A4
25C8
67A5
11B5
5D4
5C4
61C7
23C3
25C8
66D7
11B5
5D4
5D4
5A1
5D4
5D4
62A4
52A4
5D7
5D7
51D7
5D4
66D5
67A3
5D4
5A4
5A1
5D7
5D7
5C4
5C4
5D4
66D5
5D4
5B2
FB
BIAS
SW
SHDN*
NC
VIN
BOOST
GND
G
D
S
G
D
S
G
D
S
V3
V4
RST*
V2
V1
GND
V-
V+
OUT
IN
G
D
S
G
D
S
OUT
G
D
S
G
D
S
G
D
S
G
D
S
G
D
S
G
D
S
IN
IN
IN
IN
IN
IN
IN
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
LTC2903 guaranteed threshold is 93.5% (3.055V, 4.725V, 2.325V, 0.840V)
Power Control Signals
(PM_SLP_S3_L)
ISL6269 undervoltage threshold 81-87% (0.85 - 0.91V)
Other S0 Rails PWRGD Circuit
5V Enable has pull-up to PBUS
Reports when 1.5V S0 and 1.05V S0 are in regulation
0.89V Reference
1.5V Comp threshold set to 1.32V (88%)
NOTE: R8065 acts as 10K pull-up for PGOOD signal
LTC2903 guaranteed threshold is 93.5% (3.055V, 4.725V, 2.325V, 0.840V)
3.425V "G3Hot" Supply
<Ra>
Unused PGOOD Signals
GPU core voltage.
PowerPlay is changing
(PM_SLP_S4_L)
(P5VS5_PGOOD)
by ethernet power control circuit.
Vout = 1.25V * (1 + Ra / Rb)
NC
<Rb>
Vout = 3.425
200mA max output
(Switcher limit)
PM_SLP_S3_L
1
0
0
0
PM_SLP_S4_L
1
1
0
0
SMC_PM_G2_ENABLE
1
1
1
0
Battery Off (G3Hot)
Run (S0)
Sleep (S3)
Soft-Off (S5)
State
Supply needs to guarantee 3.31V delivered to SMC VRef generator
2.5V S3 and 1.2V S3 supplies are controlled
ISL6269 PGOOD does not
Need to ensure that
1.8V Enable has pull-up to PBUS
1.5V Enable has pull-up to PBUS
3.3V rise after VCore is up.
GPU requires 1.2V, 1.8V, 2.5V and
deassert while GPU
Does not include D3C rails for GPU!!
1.5V / 1.05V PWRGD Circuit
extension all D3Cold rails) by driving
The SB can turn off the GPUVcore (and by
GPIO38 low.
This signal was used as an option previously
But was disconnected for C8053 placement.
to test for 2v5 and 1v2 S3 valid for GPUVCORE_EN.
CRITICAL
TSOT23-8
LT3470
U8000
7
6
8
4
2
1 5
3
2N7002DW-X-F
SOT-363
Q8056
3
5
4
25V
10%
X5R
10UF
1206-1
C8000
1
2
1/16W
5%
402
MF-LF
10K
R8069
1
2
1/16W
5%
402
MF-LF
10K
R8068
1
2
SOT-363
2N7002DW-X-F
Q8058
3
5
4
2N7002DW-X-F
SOT-363
Q8058
6
2
1
CRITICAL
TSOT-23
LTC2903
U8070
2
6
1
3
4
5
402
CERM
10V
20%
0.1uF
C8070
1
2
22UF
CERM
805
20%
6.3V
C8015
1
2
200K
MF-LF
1%
1/16W
402
R8011
1
2
10K
5%
1/16W
MF-LF
402
R8065
1
2
10V
20%
402
CERM
0.1uF
C8081
1
2
SC70
MC74VHC1G08
U8081
3
2
1
4
5
402
10K
5%
MF-LF
1/16W
R8081
1
2
10V
20%
402
CERM
0.1uF
C8060
1
2
1/16W
402
MF-LF
10K
5%
R8076
1
2
MF-LF
402
1%
1/16W
845K
R8070
1
2
CERM
0.1UF
20%
10V
402
C8071
1
2
100K
MF-LF
402
1%
1/16W
R8071
1
2
1/16W
1%
402
MF-LF
365K
R8072
1
2
CERM
0.1UF
20%
10V
402
C8073
1
2
100K
MF-LF
402
1%
1/16W
R8073
1
2
402
10V
20%
0.1UF
CERM
C8075
1
2
68.1K
1/16W
1%
402
MF-LF
R8074
1
2
1/16W
1%
402
MF-LF
100K
R8075
1
2
0.047UF
10%
16V
CERM
402
C8053
1
2
SM-LF
LMC7211
U8060
4
3
1
5
2
SC70
MC74VHC1G08
U8080
3
2
1
4
5
402
CERM
10V
20%
0.1UF
C8080
1
2
5C4
61C7 65B8 66B3 66B5
1/16W
1%
402
MF-LF
4.99K
R8063
1
2
1/16W
1%
402
MF-LF
27.4K
R8061
1
2
1/16W
1%
402
MF-LF
10K
R8064
1
2
1/16W
402
MF-LF
10K
1%
R8062
1
2
5C4
61C7 65B8 66B2 66B3
5%
402
MF-LF
1/16W
10K
R8051
1
2
10K
1/16W
5%
402
MF-LF
R8050
1
2
SOT-363
2N7002DW-X-F
Q8057
6
2
1
2N7002DW-X-F
SOT-363
Q8050
6
2
1
26A5 51D7
1/16W
5%
402
MF-LF
100K
R8054
1
2
SOT-363
2N7002DW-X-F
Q8057
3
5
4
348K
MF-LF
402
1%
1/16W
R8010
1
2
5%
402
MF-LF
10K
1/16W
R8055
1
2
SOT-363
2N7002DW-X-F
Q8055
6
2
1
2N7002DW-X-F
SOT-363
Q8055
3
5
4
CRITICAL
33uH
CDPH4D19F-SM
L8010
1 2
2N7002DW-X-F
SOT-363
Q8059
3
5
4
470K
MF-LF
402
5%
1/16W
R8059
1
2
2N7002DW-X-F
SOT-363
Q8059
6
2
1
2N7002DW-X-F
SOT-363
Q8050
3
5
4
63B3 63C3
66D4 66D7
71C8
22pF
CERM
402
5%
50V
C8010
1
2
402
1/16W
MF-LF
5%
100K
R8056
1
2
5C4
23C3
32B3
39C8
42A8
43C8
51C5
55C3
65B8
66B6
66C6
MF-LF
5%
402
1/16W
100K
R8057
1
2
5C1 5C4 6A1
6A2
23C3
41B6 47C7 48C3
51C5 64C8
66A6
1/16W
5%
402
MF-LF
100K
R8058
1
2
52A4 65D7
66A6
51D5
0.22uF
X5R
402
20%
6.3V
C8005
1
2
63B5 63C8
66B7 66B8
63B5 63C8
66B7 66B8
1/16W
402
10K
5%
MF-LF
R8053
1
2
10K
MF-LF
402
1/16W
5%
R8052
1
2
3.3V G3Hot Supply & Power Control
SYNC_DATE=09/15/2006
8766
051-7164 06004
SYNC_MASTER=M59_MLB
PM_SLP_S3_L_GPUVCORE_EN
SB_GPUVCORE_DISABLE_L
MAKE_BASE=TRUE
SB_GPUVCORE_DISABLE_L
P3V3D3C_EN_L
MAKE_BASE=TRUE
P1V2R2V5D3C_EN_LS5V
MAKE_BASE=TRUE
TP_P2V5S3_P1V2S3_PGOOD
MAKE_BASE=TRUE
S0PGOOD_PWROK
PP3V3_S0
PM_SLP_S3_L
MAKE_BASE=TRUE
PP5V_S5
PM_SLP_S3_L
PM_SLP_S3_L
MAKE_BASE=TRUE
P5VS5_PGOOD
PM_SLP_S3_LS5V_L
MAKE_BASE=TRUE
P3V3S0_EN_L P3V3S0_EN_L
MAKE_BASE=TRUE
P1V8D3C_EN P1V8D3C_EN
P1V2R2V5D3C_EN_LS5V
P3V3D3C_EN_L
P1V2R2V5D3C_EN_LS5V
P1V5P1V05S0_PGOOD
PM_SLP_S3
PM_SLP_S4_LS5V
PPDCIN_G3H
P1V5S0_PGOOD
P3V42G3H5_BOOST
MIN_NECK_WIDTH=0.25 mm
SWITCH_NODE=TRUE
P3V42G3H_SW
MIN_LINE_WIDTH=0.5 mm
P3V42G3H_FB
PP3V42_G3H
PM_SLP_S4_LS5V
MAKE_BASE=TRUE
PM_SLP_S3_L
PM_SLP_S3_L
PM_SLP_S4_LS5V
PM_SLP_S4_L
PM_SLP_S4_L
PM_SLP_S4_L
P5VS5_PGOOD
SMC_PM_G2_EN_L
SMC_PM_G2_EN
PP1V5_S0
MAKE_BASE=TRUE
P1V5P1V05S0_PGOOD
ALL_SYS_PWRGD
P1V5P1V05S0_PGOOD
P1V0_P1V5PG_REF
P1V5S0_COMP_POS
TP_P5V_P1V5_PGOOD
MAKE_BASE=TRUE
TP_P1V8S3_PGOOD
MAKE_BASE=TRUE
TP_P1V8S3_PGOOD
TP_P2V5S3_P1V2S3_PGOOD
PP5V_S5
PM_SLP_S4_L
MAKE_BASE=TRUE
TP_P2V5S3_P1V2S3_PGOOD
PP3V3_S0
TP_P5V_P1V5_PGOOD
PGOOD_MUXED_S0_OR_S0D3C
PP3V3_S5
PP3V42_G3H
P1V2R2V5D3C_EN_LS5V
PM_SLP_S3_LS5V
P1V5S0_RUNSS
PM_SLP_S3_LS5V
P5VS5_RUNSS
GPUVCORE_EN
MAKE_BASE=TRUE
GPUVCORE_EN
PM_SLP_S3_LS5V_L
MAKE_BASE=TRUE
PP3V3_S3
MAKE_BASE=TRUE
PM_SLP_S3_LS5V
PP3V42_G3H
PP5V_S0
S0PGOOD_5V_DIV
PP3V3_S0
PP2V5_S0
S0PGOOD_2V5_DIV
S0PGOOD_0V9_DIV
PP0V9_S0
82D5
82D5
82C6
82C6
82B3
82B3
82A4
82A4
79D3
79D3
79A8
79A8
71D2
71D2
67C5
67C5
67C3
67C3
67B3
67B3
67A3
67A3
66B6
66B6
66B5
66B1
65D6
65D6
65B3
65B3
62A6
62A6
61D8
61D8
61A5
61A5
60D4
60D4
60C7
60C7
58C7
58C7
58C4
58C4
57B6
57B6
54D4
54D4
54B5
54B5
52D3
52D3
49C7
49C7
49C4
49C4
49B5
49B5
40B6
40B6
36D6
36D6
34A8
34A8
33D8
33D8
33D3
33D3
33C7
33C7
29A6
29A6
29A3
29A3
28A6
28A6
27D8
27D8
27D5
27D5
27D3
27D3
27C3
27C3
26D1
26D1
26B8
26B8
26B6
26B6
26B4
26B4
25D8
79D5
25D8
25D3
67D5
25D3
25C6
67D3
25C6
25C4
67C3
25C4
81D4
25B8
65D8
81D4
81D4
25B8
69C8
25B4
65D2
69C8
81D4
69C8
25B4
69B8
25A4
65D1
69B8
81A5
69B8
81B3
25A4
69A8
67C8
24D3
65C8
69A8
67C5
69A8
80B5
24D3
68B8
67C6
24C3
63D8
68B8
67C3
68B8
80A1
24C3
67D5
62C1
24B5
56D4
67D5
65D1
67D5
79B8
24B5
71D7
67D3
62A8
71D7
24B3
26C5
67D3
63B7
67D3
71A6
24B3
67C3
66D2
48B6
67C3
23D5
25D2
66D2
60C2
66C8
67B3
23D5
67C1
66C8
25D6
67C1
23B3
25C8
66A8
59C6
66A8
67B1
23B3
82D3
67B1
53C4
25C8
67B1
22B5
25B6
53C4
57D4
53C4
67A1
22B5
82C5
66B8
66C8
52D7
66C8
66C8
66B8
66B8
66B8
25C6
66D8
21D3
24C3
52D7
52B1
52D7
62B1
21D3
67B6
65D6
66C6
66C8
52B7
66C6
66C6
66A6
66A6
66A6
25C2
65D6
21C3
24B3
52B7
46D6
52B7
61D7
21C3
67A8
65B7
66B6
66C6
52B5
66B6
66B6
64C8
64C8
64C8
25B6
65B7
20B4
24A5
52B5
46C3
52B5
58C7
20B4
67A6
64C8
65B8
65B8
52B1
65B8
65B8
51C5
51C5
51C5
25B2
64C8
20A4
23D8
52B1
46B3
52B1
58C4
20A4
63D1
62C8
55C3
55C3
51D4
55C3
55C3
48C3
48C3
48C3
25A8
62C8
19C7
23D4
51D4
41C5
51D4
57B5
19C7
19D7
62B6
51C5
51C5
51D3
51C5
51C5
47C7
47C7
47C7
24B5
62B6
19C6
23D1
51D3
66C7
66C7
37D7
51D3
55A8
19C6
19C5
62B2
43C8
43C8
71C8
71C8
51C2
43C8
43C8
41B6
41B6
41B6
24A5
62B2
17C6
23B7
51C2
66C6
66C6
37D5
66C6
51C2
53C4
17C6
19A8
71C8
62A4
42A8
42A8
66D8
66D8
47B5
42A8
42A8
23C3
23C3
23C3
24A3
66B5
62A4
14D6
23A7
47B5
62B3
62B3
37C3
62B3
47B5
36D6
14D6
19A6
67D8
66D8
52B5
39C8
39C8
66D7
66D7
66B7
69B2
35B7
39C8
39C8
66B7
6A2
6A2
6A2
9B7
66B2
52B5
14C7
22D8
35B7
48C3
48C3
37A7
48C3
35B7
31C5
14C7
19A4
67D6
66D4
66B8
47C7
32B3
32B3
66D4
66D4
66B6
68C4
27C3
66B6
32B3
32B3
66B6
6A1
6A1
6A1
66A8
8B7
65B8
47C7
10C5
22C6
27C3
6A2
6A2
32C5
6A2
27C3
25D8
10C5
17D6
31C2
66D5
63C3
63C8
82D5
25C8
23C3
23C3
66D5
66D5
66D5
66D5
66D6
63C3
66D7
63C3
65D3
67A8
26D6
65D3
23C3
23C3
65D3
5C4
5C4
5C4
65D7
5D4
61C7
66C2
66C2 66C1
25C8
5D4
66C1
11B5
26D6
6A1
62C4
6A1
62C5
71C8
71C8
66D4
27C5
6A1
26D6
5D4
5D4
17C6
30D5
65C8
63B3
63B5
82A4
5D4
5C4
5C4
63D3
65D8
65D8
64A6
64A6
63B3
65C8
63B3
62A4
67A6
5D7
5D2
62A4
5C4
5C4
62A4
5C1
5C1
5C1
52A4
5D1
5C4
62B3
64B4 64B4
5D4
5A4
62B3
82A2
5D4
5D2
5C1
5D7
5C1
5D7
66B5
66B5
63D3
5D4
5C1
5D2
5D2
5A4
5D4
5D4
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
"S3AC" rail is ON in S3 on AC, OFF in S3 on battery
SYNC_MASTER=(MASTER)
Power Aliases
87
06004
67
051-7164
SYNC_DATE=(MASTER)
PP5V_S0
PP5V_S0
VOLTAGE=5V
MAKE_BASE=TRUE
MIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.6 mm
PP5V_S0
PP5V_S0
PP5V_S0
PP5V_S0
PP5V_S0
PP5V_S0
PP5V_S0
PP5V_S0
PP5V_S0
PP5V_S0
PP5V_S3
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=5V
MAKE_BASE=TRUE
PP5V_S5
PP5V_S5
PP5V_S5
PP5V_S5
PP5V_S5
PP5V_S5
PP5V_S5
PP5V_S5
PP5V_S3
PP5V_S3
PP5V_S5
PPBUS_S5_FW_FET
PPBUS_S5_FW_FET
PPBUS_S5_FW_FET
MIN_NECK_WIDTH=0.3 mm
MIN_LINE_WIDTH=0.5 mm
VOLTAGE=33V
MAKE_BASE=TRUE
PPBUS_S5_FW_FET
PPBUS_G3H
PPBUS_G3H
PPBUS_G3H
PPBUS_G3H
PPBUS_G3H
PPBUS_G3H
PPBUS_G3H
PPBUS_G3H
PPBUS_G3H
PPBUS_G3H
PPBUS_G3H
PPBUS_G3H
MAKE_BASE=TRUE
PPBUS_G3H
VOLTAGE=12.6V
MIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.5 mm
MIN_LINE_WIDTH=0.5 mm
PPVCORE_S0_CPU
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.1V
MAKE_BASE=TRUE
PPBB_S0_GPU
PP3V42_G3H
PP5V_S3
PP5V_S0
PP3V42_G3H
PP3V42_G3H
PP3V3_S5
PP3V3_S5
PP3V3_S5
PP3V3_S5
PP3V3_S5
PP3V3_S3
PP3V3_S3
MIN_NECK_WIDTH=0.2 MM
MIN_LINE_WIDTH=0.5 MM
MAKE_BASE=TRUE
VOLTAGE=1.8V
PP1V8_S3
PP0V9_S0
PP1V2_S3
MIN_LINE_WIDTH=0.25 mm
MAKE_BASE=TRUE
PPBB_S0_GPU
VOLTAGE=1.9V
MIN_NECK_WIDTH=0.25 mm
PP1V2_S3
PPBUS_S5_FW_FET
PP5V_S5
MAKE_BASE=TRUE
VOLTAGE=1.2V
MIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.6 mm
PPVCORE_D3C_GPU
PP1V5_S0_NB
PP1V8_S3
PP1V8_D3C
PP1V8_D3C
PP1V8_S3
PP1V8_S3
PP1V8_S3
PP1V5_S0_NB
PP1V5_S0_NB
PP1V5_S0
VOLTAGE=1.2V
MIN_LINE_WIDTH=0.6 mm
PP1V2_D3C
MIN_NECK_WIDTH=0.25 mm
MAKE_BASE=TRUE
PP1V5_S0
PP1V5_S0
PP1V5_S0
PP1V2_D3C
PP1V2_S3
PP1V5_S0_NB
PP5V_S0
PP3V3_D3C
PP3V3_D3C
PP3V3_D3C
PP3V3_D3C
PP3V3_D3C
PP2V5_D3C
PP2V5_D3C
PP2V5_S0
PP1V05_S0
PP2V5_D3C
PP1V05_S0
PP1V05_S0
PP1V05_S0
PP1V05_S0
PP5V_S0
PP5V_S0
PNBB_S0_GPU
MAKE_BASE=TRUE
VOLTAGE=-0.7V
MIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.25 mm
PNBB_S0_GPU
PP3V3_S3ACPP3V3_S3AC
PPVCORE_S0_CPU
PPBB_S0_GPU
PNBB_S0_GPU
PP3V3_S3AC
MIN_LINE_WIDTH=0.38 mm
MIN_NECK_WIDTH=0.22 mm
VOLTAGE=3.3V
MAKE_BASE=TRUE
PP5V_S3
PPBUS_G3H
PP1V05_S0
PP1V05_S0
PP1V2_D3C
PP1V5_S0PP1V5_S0
PPVCORE_D3C_GPU
PPDCIN_G3H
PP2V5_S0
PP1V5_S0
PP2V5_D3C
PPDCIN_G3H
PP2V5_S3
PP2V5_S3
PP2V5_S0
PP2V5_S0
PP1V8_D3C
VOLTAGE=2.5V
MIN_LINE_WIDTH=0.6 mm
PP2V5_S0
MAKE_BASE=TRUE
MIN_NECK_WIDTH=0.25 mm
PP1V2_D3C
MIN_NECK_WIDTH=0.22 mm
MIN_LINE_WIDTH=0.6 mm
VOLTAGE=1.2V
PP1V2_S3
MAKE_BASE=TRUE
PPVCORE_D3C_GPU
PP3V3_D3C
PP5V_S5
PP1V2_D3C
PP2V5_S0
MAKE_BASE=TRUE
VOLTAGE=2.5V
PP2V5_D3C
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm
PP2V5_D3C
PPVCORE_D3C_GPU
PPDCIN_G3H
MIN_NECK_WIDTH=0.2 mm
MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.4 mm
VOLTAGE=18.5V
PPDCIN_G3H
PP3V3_D3C
PP3V3_D3C
PP3V3_D3C
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.425V
MIN_LINE_WIDTH=0.25 mm
PP3V42_G3H
MAKE_BASE=TRUE
PP3V42_G3H
PP3V42_G3H
PP3V42_G3H
PP3V42_G3H
PP3V42_G3H
PP3V42_G3H
PP3V3_S5
PP3V3_S5
PP3V3_S5
PP3V3_S5
PP3V3_S5
PP3V3_S5
PP3V3_S5
PP3V3_S5
PP3V3_S3
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S3
PP3V3_S0
PP3V3_S0
PP3V3_D3C
PP3V3_D3C
PP3V3_D3C
PP0V9_S0
PP3V42_G3H
PP3V3_S5
PP3V42_G3H
MAKE_BASE=TRUE
VOLTAGE=0.9V
MIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.38 mm
PP0V9_S0
VOLTAGE=5V
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
PP5V_S3
MAKE_BASE=TRUE
PP5V_S5
PPVCORE_S0_CPU
PP1V05_S0
PP1V8_S3
PP1V8_S3
PP1V5_S0_NB
PP1V5_S0_NB
PP1V5_S0_NB
PP1V5_S0_NB
PP1V5_S0_NB
PP1V5_S0_NB
MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.5 mm
VOLTAGE=1.5V
MIN_NECK_WIDTH=0.25 mm
PP1V5_S0_NB
PP3V3_S3
PP3V3_S3
PP3V3_S3
PP3V3_S3
PP3V3_S5
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.25 mm
MAKE_BASE=TRUE
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP1V5_S0
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
MAKE_BASE=TRUE
PP1V5_S0
VOLTAGE=1.5V
PP1V05_S0
MIN_NECK_WIDTH=0.25 mm
MAKE_BASE=TRUE
VOLTAGE=1.05V
MIN_LINE_WIDTH=0.5 mm
PP3V3_D3C
VOLTAGE=3.3V
MAKE_BASE=TRUE
MIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.5 mm
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S3
PP3V3_S3
PP3V3_S3
PP3V3_S3
PP3V3_S3
PP3V3_S3
MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.5 MM
VOLTAGE=3.3V
MIN_NECK_WIDTH=0.2 MM
PP3V3_S3
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
MAKE_BASE=TRUE
VOLTAGE=3.3V
PP1V5_S0
PP1V5_S0
PP1V5_S0
PP1V2_D3C
MAKE_BASE=TRUE
MIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.6 mm
PP1V8_D3C
VOLTAGE=1.8V
PP2V5_S0
PP2V5_S3
PP1V8_D3C
MAKE_BASE=TRUE
PP2V5_S3
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=2.5V
PP1V8_S3
VOLTAGE=0V
GND
MIN_LINE_WIDTH=0.6mm
MIN_NECK_WIDTH=0.25mm
82D5
82D5
82D5
82D5
82D5
82D5
82D5
82D5
82D5
82D5
82D5
82D5
82D5
82D5
82C6
82C6
82C6
82C6
82C6
82C6
82C6
82C6
82C6
82C6
82C6
82C6
82C6
82C6
82B3
82B3
82B3
82B3
82B3
82B3
82B3
82B3
82B3
82B3
82B3
82B3
82B3
82B3
82A4
82A4
82A4
82A4
82A4
82A4
82A4
82A4
82A4
82A4
82A4
82A4
82A4
82A4
79D3
79D3
79D3
79D3
79D3
79D3
79D3
79D3
79D3
79D3
79D3
79D3
79D3
79D3
79A8
79A8
79A8
79A8
79A8
79A8
79A8
79A8
79A8
79A8
79A8
79A8
79A8
79A8
71D2
71D2
71D2
71D2
71D2
71D2
71D2
71D2
71D2
71D2
71D2
71D2
71D2
71D2
67C5
67C5
67C5
67C5
67C5
67C5
67C5
67C5
67C5
67C5
67C5
67C5
67C5
67C5
67C3
67C3
67C3
67C3
67C3
67C3
67C3
67C3
67C3
67C3
67C3
67C3
67C3
67C3
67B3
67B3
67B3
67B3
67B3
67B3
67B3
67B3
67B3
67B3
67B3
67B3
67B3
67B3
67A3
67A3
67A3
67A3
67A3
67A3
67A3
67A3
67A3
67A3
67A3
67A3
67A3
67A3
66B6
66B6
66B6
66B6
66B6
66B6
66B6
66B6
66B6
66B6
66B6
66B6
66B6
66B6
66B5
66B5
66B5
66B5
66B5
66B5
66B5
66B5
66B5
66B5
66B5
66B5
66B5
66B5
66B1
66B1
66B1
66B1
66B1
66B1
66B1
66B1
66B1
66B1
66B1
66B1
66B1
66B1
65D6
65D6
65D6
65D6
65D6
65D6
65D6
65D6
65D6
65D6
65D6
65D6
65D6
65D6
65B3
65B3
65B3
65B3
65B3
65B3
65B3
65B3
65B3
65B3
65B3
65B3
65B3
65B3
62A6
62A6
62A6
62A6
62A6
62A6
62A6
62A6
62A6
62A6
62A6
62A6
62A6
62A6
61D8
61D8
61D8
61D8
61D8
61D8
61D8
61D8
61D8
61D8
61D8
61D8
61D8
61D8
61A5
61A5
61A5
61A5
61A5
61A5
61A5
61A5
61A5
61A5
61A5
61A5
61A5
61A5
60D4
60D4
60D4
60D4
60D4
60D4
60D4
60D4
60D4
60D4
60D4
60D4
60D4
60D4
60C7
60C7
60C7
60C7
60C7
60C7
60C7
60C7
60C7
60C7
60C7
60C7
60C7
60C7
58C7
58C7
58C7
58C7
58C7
58C7
58C7
58C7
58C7
58C7
58C7
58C7
58C7
58C7
58C4
58C4
58C4
58C4
58C4
58C4
58C4
58C4
58C4
58C4
58C4
58C4
58C4
58C4
57B6
57B6
57B6
57B6
57B6
57B6
57B6
57B6
57B6
57B6
57B6
57B6
57B6
57B6
54D4
54D4
54D4
54D4
54D4
54D4
54D4
54D4
54D4
54D4
54D4
54D4
54D4
54D4
54B5
54B5
54B5
54B5
54B5
54B5
54B5
54B5
54B5
54B5
54B5
54B5
54B5
54B5
52D3
52D3
52D3
52D3
52D3
52D3
52D3
52D3
52D3
52D3
52D3
52D3
52D3
52D3
49C7
49C7
49C7
49C7
49C7
49C7
49C7
49C7
49C7
49C7
49C7
49C7
49C7
49C7
49C4
49C4
49C4
49C4
49C4
49C4
49C4
49C4
49C4
49C4
49C4
49C4
49C4
49C4
49B5
49B5
49B5
49B5
49B5
49B5
49B5
49B5
49B5
49B5
49B5
49B5
49B5
49B5
40B6
40B6
40B6
40B6
40B6
40B6
40B6
40B6
40B6
40B6
40B6
40B6
40B6
40B6
36D6
36D6
36D6
36D6
36D6
36D6
36D6
36D6
36D6
36D6
36D6
36D6
36D6
36D6
34A8
34A8
34A8
34A8
34A8
34A8
34A8
34A8
34A8
34A8
34A8
34A8
34A8
34A8
33D8
33D8
33D8
33D8
33D8
33D8
33D8
33D8
33D8
33D8
33D8
33D8
33D8
33D8
33D3
33D3
33D3
33D3
33D3
33D3
33D3
33D3
33D3
33D3
33D3
33D3
33D3
33D3
33C7
33C7
33C7
33C7
33C7
33C7
33C7
33C7
33C7
33C7
33C7
33C7
33C7
33C7
29A6
29A6
29A6
29A6
29A6
29A6
29A6
29A6
29A6
29A6
29A6
29A6
29A6
29A6
29A3
29A3
29A3
29A3
29A3
29A3
29A3
29A3
29A3
29A3
29A3
29A3
29A3
29A3
67D8
67D8
67D8
67D8
67D8
28A6
28A6
28A6
28A6
28A6
28A6
28A6
28A6
28A6
28A6
28A6
28A6
67D8
28A6
28A6
67D6
67D6
67D6
67D6
67D6
27D8
27D8
27D8
27D8
27D8
27D8
67D6
27D8
27D8
27D8
27D8
27D8
27D8
67D6
27D8
27D8
65A2
65A2
65A2
65A2
65A2
27D5
27D5
27D5
27D5
27D5
27D5
65A2
27D5
27D5
27D5
27D5
27D5
27D5
65A2
27D5
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20A4
46B3
46B3
46B3
46B3
25B2
25B2
25B2
82D7
73B8
63D1
75D5
29B2
57B5
57B5
57B5
57B5
57B5
81C6
62C8
62C8
62C8
81C4
62C8
61D7
61D7
61D7
61D7
67D1
51D4
51D4
51D4
23D4
23D4
23D4
23D4
41C5
41C5
28D6
62C8
72D8
19B5
28D6
73B5
73B5
28D6
28D6
28D6
19B5
19B5
25A8
77B8
25A8
25A8
25A8
77B8
19B5
74D6
74D6
77B7
74D6
74D6
82D7
82D7
19D7
11B3
82D7
11B3
11B3
11B3
41C4
41C4
67D1
61D7
11B3
77B8
25A8
25A8
77A7
19D7
25A8
19D7
19D7
73B5
19D7
77B8
72D8
74D6
82D7
19D7
82D7
82D7
72D8
74D6
74D6
74D6
51D4
51D4
51D4
51D4
23D4
23D4
23D4
23D4
23D4
41C5
19C7
19C7
19C7
19C7
19C7
19C7
74D6
74D6
74D6
51D4
67D1
11B3
28D6
28D6
19B5
19B5
19B5
19B5
19B5
19B5
41C5
41C5
41C5
41C5
23D4
19C7
19C7
19C7
19C7
19C7
19C7
25A8
11B3
74D6
19C7
19C7
41C5
41C5
41C5
41C5
25A8
25A8
25A8
77B8
73B5
19D7
73B8
28D6
55A8
55A8
55A8
55A8
55A8
81C4
62B6
62B6
62B6
67B3
62B6
61D4
61D4
61D4
61D4
61D1
51D3
51D3
51D3
23D1
23D1
23D1
23D1
37D7
37D7
28D3
67D8
62B6
71C1
19A5
28D3
73A8
73A8
28D3
28D3
28D3
19A5
19A5
24B5
70C7
24B5
24B5
24B5
70C7
67D8
19A5
74B2
74B2
74D6
74B2
74B2
78C8
78C8
19C5
9B7
78C8
9B7
9B7
9B7
39D8
39D8
61D1
61D4
9B7
70C7
24B5
24B5
72D8
19C5
24B5
82D7
67B8
67B8
19C5
19C5
73A8
19C5
70C7
67D8
71C1
74B2
77B8
19C5
78C8
78C8
71C1
74B2
74B2
74B2
51D3
51D3
51D3
51D3
23D1
23D1
23D1
23D1
23D1
37D7
19C6
19C6
19C6
19C6
19C6
19C6
74B2
74B2
74B2
51D3
61D1
9B7
28D3
28D3
19A5
19A5
19A5
19A5
19A5
19A5
37D7
37D7
37D7
37D7
23D1
19C6
19C6
19C6
19C6
19C6
19C6
24B5
9B7
74B2
19C6
19C6
37D7
37D7
37D7
37D7
24B5
24B5
24B5
70C7
73A8
19C5
73B5
67B8
28D3
53C4
53C4
53C4
53C4
53C4
67B1
62B2
62B2
62B2
67B1
62B2
67C3
67C3
67C3
55D3
55D3
55D3
55D3
55D7
51C2
51C2
51C2
23B7
23B7
23B7
23B7
37D5
37D5
28B2
67D8
67D6
67D6
62B2
71B7
17C6
28B2
73A5
73A5
28B2
28B2
28B2
17C6
17C6
24A5
70A1
24A5
24A5
24A5
70A1
67D6
17C6
71C4
71C4
74B2
71C4
71C4
77C6
77C6
19A8
8C7
77C6
8C7
8C7
8C7
39D6
39D6
55D7
55D3
8C7
70A1
24A5
24A5
71C1
19A8
24A5
78C8
67B6
67B6
19A8
19A8
73A5
19A8
70A1
67D6
71B7
71C4
70C7
19A8
77C6
77C6
71B7
71C4
71C4
71C4
51C2
51C2
51C2
51C2
23B7
23B7
23B7
23B7
23B7
37D5
17C6
17C6
17C6
17C6
17C6
17C6
71C4
71C4
71C4
51C2
67D8
55D7
8C7
28B2
28B2
17C6
17C6
17C6
17C6
17C6
17C6
37D5
37D5
37D5
37D5
23B7
17C6
17C6
17C6
17C6
17C6
17C6
24A5
8C7
71C4
17C6
17C6
37D5
37D5
37D5
37D5
24A5
24A5
24A5
70A1
73A5
19A8
67B6
73A8
67B6
28B2
36D6
36D6
36D6
36D6
36D6
62A2
62A4
62A4
62A4
62A2
62A4
67C1
67C1
67C1
43D8
43D8
43D8
43D8
55A6
47B5
47B5
47B5
23A7
23A7
23A7
23A7
37C3
37C3
19D7
67D6
63B3
63B3
67C1
62A4
67A8
17B6
19D7
72B8
72B8
19D7
19D7
19D7
17B6
17B6
24A3
67D8
24A3
24A3
24A3
67D8
63B3
17B6
71B8
71B8
71C4
71B8
71B8
77A8
77A8
19A6
7D5
77A8
7D5
7D5
7D5
39B8
39B8
55A6
43D8
7D5
67D8
24A3
24A3
71B7
69B2
19A6
24A3
77C6
69B2
63D4
63D4
19A6
19A6
72B8
19A6
67D8
63B3
67A8
71B8
70A1
19A6
77A8
77A8
67A8
69B2
69B2
71B8
71B8
71B8
47B5
47B5
47B5
47B5
23A7
23A7
23A7
23A7
23A7
37C3
14D6
14D6
14D6
14D6
14D6
14D6
71B8
71B8
71B8
67D6 47B5
67D6
55A6
7D5
19D7
19D7
17B6
17B6
17B6
17B6
17B6
17B6
37C3
37C3
37C3
37C3
23A7
14D6
14D6
14D6
14D6
14D6
14D6
24A3
7D5
71B8
14D6
14D6
37C3
37C3
37C3
37C3
24A3
24A3
24A3
67D8
72B8
19A6
63D4
73A5
63D4
19D7
31C5
31C5
31C5
31C5
31C5
52B8
52B5
52B5
52B5
52B8
52B5
43D3
43D3
43D3
42B8
42B8
42B8
42B8
9D7
72D6
35B7
35B7
35B7
22D8
22D8
22D8
22D8
37A7
37A7
16B6
66B5
39D7
72D6
39D7
43D3
52B5
67A6
16D1
16B6
67B8
67B8
16B6
16B6
16B6
16D1
16D1
9B7
67D6
9B7
9B7
9B7
67D6
39D7
16D1
71A4
71A4
71B8
71A4
71A4
67A8
67A8
19A4
7B6
67A8
7B6
7B6
7B6
72D2
72D2
39B5 39B5
9D7
42B8
7B6
67D6
9B7
9B7
67A6
68C4
19A4
9B7
77A8
68C4
63D3
63D3
19A4
19A4
67B8
19A4
67D6
39D7
67A6
71A4
67D6
19A4
67A8
67A8
67A6
68C4
68C4
71A4
71A4
71A4
35B7
35B7
35B7
35B7
22D8
22D8
22D8
22D8
22D8
37A7
14C7
14C7
14C7
14C7
14C7
14C7
71A4
71A4
71A4
66B5 35B7
66B5
9D7
7B6
16B6
16B6
16D1
16D1
16D1
16D1
16D1
16D1
37A7
37A7
37A7
37A7
22D8
14C7
14C7
14C7
14C7
14C7
14C7
9B7
7B6
71A4
14C7
14C7
37A7
37A7
37A7
37A7
9B7
9B7
9B7
67D6
67B8
19A4
63D3
72B8
63D3
16B6
25D8
25D8
25D8
25D8
25D8
45C3
47C7
47C7
47C7
45C3
47C7
43B5
43B5
43B5
41C6
41C6
41C6
41C6
8D7
71B5
27C3
27C3
27C3
22C6
22C6
22C6
22C6
32C5
32C5
14C2
31C2
39A8
71B5
39A8
43B5
47C7
55C7
13D2
14C2
67B6
67B6
14C2
14C2
14C2
13D2
13D2
8B7
67C6
8B7
8B7
8B7
67C6
39A8
13D2
67A5
67A5
71A4
67A5
67A5
67A6
67A6
17D6
7B5
67A6
7B5
7B5
7B5
71A2
71A2
39B4
39B4
8D7
72D6
72D2
41C6
7B5
67C6
8B7 8B7
55C7
67A8
17D6
8B7
67A6
67A8
63C3
63C3
17D6
17D6
67B6
17D6
67C6
39A8
55C7
67A5
67C6
17D6
67A6
67A6
55C7
67A8
67A8
67A5
67A5
67A5
27C3
27C3
27C3
27C3
22C6
22C6
22C6
22C6
22C6
32C5
10C5
10C5
10C5
10C5
10C5
10C5
67A5
67A5
67A5
31C2 27C3
31C2
8D7
7B5
14C2
14C2
13D2
13D2
13D2
13D2
13D2
13D2
32C5
32C5
32C5
32C5
22C6
10C5
10C5
10C5
10C5
10C5
10C5
8B7
7B5
67A5
10C5
10C5
32C5
32C5
32C5
32C5
8B7
8B7
8B7
67C6
67B6
17D6
63C3
67B6
63C3
14C2
5D4
5D4
5D4
5D4
5D4
5D4
25C8
25C8
25C8
5D4
25C8
42C8
42C8
42C8
5C4
5C4
5C4
5C4
8B5
67D3
26D6
26D6
26D6
11B5
11B5
11B5
11B5
27C5
27C5
5D4
30D5
5D4
67D3
5D4
42C8
25C8
55A5
13C5
5D4
64A4
64A4
5D4
5D4
5D4
13C5
13C5
5D4
63B1
5D4
5D4
5D4
63B1
5D4
13C5
67A3
67A3
67A3
67A3
67A3
63C1
63C1
17C6
5D4
63C1
5D4
5D4
5D4
67D3
67D3
39A5 39A5
8B5
71B5
71A2
5C4
5D4
63B1
5D4 5D4
55A5
67A6
17C6
5D4
63C1
67A6
39D3
39D3
17C6
17C6
64A4
17C6
63B1
5D4
55A5
67A3
63B1
17C6
63C1
63C1
55A5
67A6
67A6
67A3
67A3
67A3
26D6
26D6
26D6
26D6
11B5
11B5
11B5
11B5
11B5
27C5
5D4
5D4
5D4
5D4
5D4
5D4
67A3
67A3
67A3
30D5
26D6
30D5
8B5
5D4
5D4
5D4
13C5
13C5
13C5
13C5
13C5
13C5
27C5
27C5
27C5
27C5
11B5
5D4
5D4
5D4
5D4
5D4
5D4
5D4
5D4
67A3
5D4
5D4
27C5
27C5
27C5
27C5
5D4
5D4
5D4
63B1
64A4
17C6
39D3
64A4
39D3
5D4
5D2
5D2
5D2
5D2
5D2
5B2
5D4
5D4
5D4
5B2
5D4
38B7
38B7
38B7
5A1
5A1
5A1
5A1
5B2
67D1
5D2
5D2
5D2
5D4
5D4
5D4
5D4
5D4
5D4
5B2
5D4
5A4
67D1
5A4
38B7
5D4
5B2
5D4
5B2
5D4
5D4
5B2
5B2
5B2
5D4
5D4
5D1
5D4
5D1
5D1
5D1
5D4
5A4
5D4
65C7
65C7
65C7
65C7
65C7
5D4
5D4
5D4
5B2
5D4
5B2
5B2
5B2
67D1
67D1
5A4 5A4
5B2
67D1
67D1
5A1
5B2
5D4
5D1 5D1
5B2
66D5
5D4
5D1
5D4
66D5
5A4
5A4
5D4
5D4
5D4
5D4
5D4
5A4
5B2
65C7
5D4
5D4
5D4
5D4
5B2
66D5
66D5
65C7
65C7
65C7
5D2
5D2
5D2
5D2
5D4
5D4
5D4
5D4
5D4
5D4
5A4
5A4
5A4
5A4
5A4
5A4
65C7
65C7
65C7
5D4 5D2
5D4
5B2
5B2
5B2
5B2
5D4
5D4
5D4
5D4
5D4
5D4
5D4
5D4
5D4
5D4
5D4
5A4
5A4
5A4
5A4
5A4
5A4
5D1
5B2
65C7
5A4
5A4
5D4
5D4
5D4
5D4
5D1
5D1
5D1
5D4
5D4
5D4
5A4
5D4
5A4
5B2
IO
OUT
V-
V+
S1
GATE
S2
S3 D4
D3
D2
D1
G
D
S
IO
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
Worst case Vth: min:12.47V, max: 13.54V
Assuming 1% variance for R8210-R8215 and 3.42V:
REQ of R8210 (on M57 LIO), R8212, & R8213 is 36.9K.
to A52 adapter for system load detection.
System must provide 10K-70K impedance
NOTE: R8210 is on M57 LIO!
ACIN Detection
Battery Connector
(HOST_DETECT_L)
<R1b>
<R2a>
<R1a>
Vth = (Vref / (R2b / (R1b + R2b))
Inrush Limiter
518S0457
518S0456
DC-In Connector
<R2b>
Vref = 3.42V * (R2a / (R1a + R2a))
Vref = 1.23V
Vth = 13.0V
CRITICAL
M-RT-SM
87438-0832-BLK
J8290
1
2
3
4
5
6
7
8
1SS355
SOD-323
D8201
1 2
5%
47
1/8W
MF-LF
805
R8207
1 2
CRITICAL
LMC7211
SM-LF
U8200
4
3
1
5
2
CRITICAL
SO-8
SI4405DY-E3
Q8250
5
6
7
8
4
1
2
3
0.22uF
25V
20%
603
X5R
C8250
1
2
1/16W
5%
402
1M
MF-LF
R8216
12
1/16W
1%
402
MF-LF
102K
R8214
1
2
1/16W
1%
402
MF-LF
57.6K
R8215
1
2
102K
MF-LF
402
1/16W
1%
R8212
1
2
MF-LF
1/16W
1%
402
10.7K
R8213
1
2
10V
20%
0.1uF
402
CERM
C8210
1
2
1%
402
MF-LF
1/16W
470K
R8221
1
2
402
1/16W
5%
MF-LF
330K
R8250
1
2
2N7002
SOT23-LF
Q8210
3
1
2
SC70
MC74VHC1G08
U8250
3
2
1
4
5
CRITICAL
M-RT-SM
87438-1043-BLK
J8250
1
10
2
3
4
5
6
7
8
9
DC-In & Battery Connectors
SYNC_MASTER=(MASTER)
051-7164
68 87
06004
SYNC_DATE=(MASTER)
PP3V42_G3H
PP18V5_DCIN
PPBUS_G3H
VOLTAGE=18.5V
MIN_LINE_WIDTH=0.60mm
MIN_NECK_WIDTH=0.20mm
PP18V5_DCIN
MIN_LINE_WIDTH=0.50mm
PPDCIN_G3H_R
VOLTAGE=18.5V
MIN_NECK_WIDTH=0.20mm
PP3V42_G3H
SMC_BC_ACOK
MIN_LINE_WIDTH=0.6mm
MIN_NECK_WIDTH=0.2mm
MAKE_BASE=TRUE
VOLTAGE=18.5V
PP18V5_G3H_CHGR
PP18V5_G3H_CHGR
ACOK_AND_PS_ON
ACIN_1V20_REF
ACIN_ENABLE_DIV2_L
MIN_LINE_WIDTH=0.2mm
MIN_NECK_WIDTH=0.2mm
ACIN_ENABLE_DIV_L
ACIN_DIV
SMBUS_SMC_BSA_SDA
BATT_POS
BATT_NEG
BATT_POS
PP18V5_G3H_CHGR
BATT_POS
MIN_LINE_WIDTH=0.6mm
MAKE_BASE=TRUE
MIN_NECK_WIDTH=0.25mm
SMC_BS_ALRT_L
SMBUS_SMC_BSA_SCL
PPDCIN_G3H
SMC_ADAPTER_EN
MIN_NECK_WIDTH=0.25mm
MIN_LINE_WIDTH=0.6mm
BATT_NEG
MAKE_BASE=TRUE
GND
81D4
69C8 69B8 69A8 68B8 67D5
79B7
67D3
71D7
66D2
69C1
66C8
67C3
66A8
67C1
53C4
65D6
52D7
65B7
52B7
64D7
52B5
64A6
52B1
62D7
51D4
61D7
51D3
61D4
51C2
55D3
47B5
43D8
69A6
35B7
42B8
52A2
69B1
69B1
69B2
27C3
41C6
51C5
69B1
68A2
68A2
67A8
52A2
26D6
68C5
5C4
68B8
48C3
69D8
69D8
68A1
68A1
69D8
68A1
67A6
51D5
68B2
5D2
5B1
5A1
5B1
5B1
68B3
68B3
5D1
5D1
68B3
5D1
66D5
43C8
5D1
G
D
S
G
D
S
G
D
S
G
D
S
S1
GATE
S2
S3 D4
D3
D2
D1
G
D
S
G
D
S
G
D
S
G
D
S
V-
V+
+
-
VDDP
VDD
ACLIM
ICM
ICOMP
VCOMP
VADJ
CELLS
CSOP
CHLIM
CSON
ACPRN
VREF
SGATE
CSIN
DCIN
BGATE
BOOT
UGATE
LGATE
PHASE
DCSET
PGND
THRML_PAD
DCPRN
CSIP
EN
ACSET
GND
G
D
S
S3
S2
D1
D2
D3
D4
GATE
S1
S1
GATE
S2
S3 D4
D3
D2
D1
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
CRITICAL BOM OPTION
TABLE_5_HEAD
PART#
DESCRIPTION
QTY
REFERENCE DESIGNATOR(S)
TABLE_5_ITEM
TABLE_5_ITEM
Battery Charge Current Limit
As shown, Ichg = 3.3A max
10A MAX, LIMITED BY L8300, Q8301
Battery Charge FET
353S1244
Adapter Input Current Limit
SINKING CURRENT FROM VREF.
VOLTAGE FOLLOWER GUARANTEES CURRENT LIMIT CIRCUITS
As shown, Isys =~4.6A max
ARE PROVIDED WITH SUFFICIENT CURRENT WITHOUT
PBus Supply & Battery Charger
SM
XW8300
1 2
100
1/16W
1%
402
MF-LF
R8302
1 2
402
6.3V
1uF
10%
CERM
C8312
1
2
402
10%
1uF
6.3V
CERM
C8311
1 2
D
S
G
IRLML5203-2.6A
SM
Q8340
3
1
2
SOT-363
2N7002DW-X-F
Q8322
3
5
4
SOT-363
2N7002DW-X-F
Q8322
6
2
1
603
CERM
25V
0.1UF
20%
C8340
1
2
SOT-363
2N7002DW-X-F
Q8324
3
5
4
2N7002DW-X-F
SOT-363
Q8324
6
2
1
MF-LF
3.01K
402
1/16W
1%
R8360
1 2
16V
0.047UF
402
CERM
10%
C8361
1
2
1/16W
1%
24.3K
MF-LF
402
R8362
1 2
16V
10%
0.01UF
402
CERM
C8362
1
2
20.0K
MF-LF
402
1/16W
1%
R8363
1
2
59.0K
402
1%
MF-LF
1/16W
R8366
1
2
5%
MF
27
3W
2525
R8320
1 2
50V
402
0.001UF
10%
CERM
C8330
1
2
11.3K
1/16W
402
MF-LF
1%
R8341
1
2
402
118K
MF-LF
1/16W
1%
R8340
1
2
SO-8
SI4405DY-E3
CRITICAL
Q8321
5
6
7
8
4
1
2
3
CRITICAL
1206
8AMP-24V
F8302
1 2
88.7K
MF-LF
1%
1/16W
402
R8367
1
2
CERM
NO STUFF
402
10%
50V
680pF
C8315
1 2
2.2
5%
402
1/16W
MF-LF
R8303
1 2
ISL6255A
270
1/16W
MF-LF
402
5%
R8304
1 2
NO STUFF
25V
603
CERM
20%
0.1UF
C8307
1
2
CERM
10%
402
0.22uF
10V
C8325
1
2
MF-LF
1/16W
1%
470K
402
R8330
1
2
603
MF-LF
1/16W
0.5%
49.9
R8370
1 2
603
0.0022uF
CERM
50V
10%
C8370
1
2
1%
1/16W
100K
MF-LF
402
R8344
1
2
MF-LF
5%
47
1/8W
805
R8321
1 2
402
1/16W
100K
1%
MF-LF
R8324
1
2
1W
0.02
0.5%
MF
0612
R8307
1 2
SM
XW8301
1
2
SM
XW8302
1
2
1SS355
SOD-323
D8321
1 2
SOT23
MMBD914XXG
D8340
1
3
16V
20%
CASED2E-SM
POLY
33UF
CRITICAL
C8308
1
2
X5R
10%
1UF
603
16V
C8310
1
2
RJK0305DPB
LFPAK
CRITICAL
Q8301
5
4
1 2 3
LFPAK
CRITICAL
RJK0305DPB
Q8302
5
4
1 2 3
3.48K
402
MF-LF
1/16W
1%
R8368
1
2
SOT-363
2N7002DW-X-F
Q8360
6
2
1
2N7002DW-X-F
SOT-363
Q8360
3
5
4
5%
402
MF-LF
1/16W
10K
R8369
1
2
402
16V
10%
X5R
0.1uF
C8341
1
2
2N7002DW-X-F
SOT-363
Q8361
3
5
4
SOT-363
2N7002DW-X-F
Q8361
6
2
1
5%
10K
402
MF-LF
1/16W
R8379
1
2
SM
XW8304
1
2
SM
XW8303
1
2
ISL6257H
MF-LF
1/16W
1%
402
34.8K
R8392
1
2
MF-LF
34.8K
1/16W
1%
402
ISL6255A
R8393
1
2
SC70-5
HPA00141AIDCKR
CRITICAL
U8301
1
3
4
2
5
402
CERM
10V
0.1UF
20%
C8380
1
2
CRITICAL
20%
POLY
22UF
25V
CASE-D2-LF
C8306
1
2
X5R-CERM
CRITICAL
10%
25V
805
2.2UF
C8316
1
2
X5R-CERM
805
25V
10%
2.2UF
CRITICAL
C8317
1
2
POLY
20%
22UF
25V
CASE-D2-LF
CRITICAL
C8305
1
2
ELEC
16V
20%
100UF
CRITICAL
6.3X5.5SM1
C8309
1
2
SM
CRITICAL
4.7UH
L8300
1
2
3
0.0033uF
ISL6257H
402
10%
CERM
50V
C8390
1
2
ISL6255A
10%
402
0.0033uF
50V
CERM
C8391
1
2
CRITICAL
BOMOPTION=ISL6255A
ISL6255AHRZ
QFN
U8300
8
23
27
17
14
2
7
20
19
22
21
25
24
28
1
10
5
3
12
11
16
18
29
15
9
4
26
13
6
1/16W
MF-LF
402
100K
1%
R8350
1
2
2N7002
SOT23-LF
Q8350
3
1
2
402
10%
X5R
16V
0.033uF
C8300
1 2
CERM-X5R
402
0.022uF
16V
10%
C8301
12
SI4413ADY-E3
CRITICAL
SO-8
Q8300
100K
1%
402
MF-LF
1/16W
NO STUFF
R8310
1
2
0.1UF
CERM
20%
10V
402
C8304
1
2
SOD-123
B0530WXF
D8300
12
402
4.7
1/16W
MF-LF
5%
R8300
1 2
CERM
20%
0.1UF
25V
603
C8303
1 2
25V
0.0082uF
X7R
10%
402
C8302
1
2
1/16W
5%
18
402
MF-LF
R8305
1 2
1W
MF
0612
0.5%
0.01
R8308
1 2
402
1/16W
5%
MF-LF
2.2
R8306
1 2
SO-8
SI4405DY-E3
CRITICAL
Q8320
5
6
7
8
4
1
2
3
1/16W
5%
MF-LF
330K
402
R8331
1
2
1%
402
MF-LF
39.2K
1/16W
R8322
1
2
MF-LF
1/16W
1%
402
35.7K
R8323
1
2
16V
CERM
0.01uF
10%
402
C8320
1
2
402
X5R
0.1uF
10%
16V
C8321
1
2
402
CERM
0.01UF
20%
16V
NO STUFF
C8324
1
2
CERM
16V
402
0.01UF
NO STUFF
10%
C8322
1
2
402
1%
MF-LF
1/16W
10K
R8325
1 2
20%
402
CERM
10V
0.1UF
C8323
1
2
0.001UF
CERM
402
10%
50V
C8327
1
2
0 OHM,5%,1/16W,0402,SMD,LF
R8304
ISL6257H116S0004
1
ISL6257H,BATT CHGR,28P,QFN,LF
353S1510 ISL6257H
U8300
1
CRITICAL
051-7164
SYNC_MASTER=M59_LIO
06004
8769
SYNC_DATE=09/15/2006
PBus Supply & Batt. Charger
PPVDCIN_G3H_PRE
MIN_LINE_WIDTH=0.6mm
MIN_NECK_WIDTH=0.25mm
CHGR_VDDP
CHGR_BOOT_R
CHGR_PHASE_R
CHGR_ACSET
CHGR_ACSET_D
CHGR_ACPRN
PP3V42_G3H
CHGR_VDD
CHGR_DCIN
CHGR_VDD
CHGR_SGND
CHGR_EN
CHGR_ACLIM_R
SMC_SYS_ISET_L
PP3V42_G3H
CHGR_SGND
SMC_BC_ACOK_R
CHGR_VREF_VF
CHGR_CSO_P
CHGR_CSO_N
CHGR_SGND
SMC_BATT_CHG_EN
CHGR_ACPRN
CHGR_ACLIM
SMC_BATT_ISET_L
CHGR_SGND
CHGR_CHLIM_R
CHGR_CHLIM
SMC_BC_ACOK
SMC_SYS_ISET
SMC_BATT_ISET
CHG_EN_DIV2_L
TCHG_EN_DIV2_L
PPVBATT_G3H_DIO
MIN_NECK_WIDTH=0.25mm
VOLTAGE=12.6V
MIN_LINE_WIDTH=0.5mm
SMC_BATT_TRICKLE_EN_L
GND
CHGR_VREF_VF
MIN_NECK_WIDTH=0.2mm
CHG_EN_DIV_L
MIN_LINE_WIDTH=0.2mm
PPVBAT_G3H_CHGR_OUT
CHGR_VREF
CHGR_VREF_VF
CHGR_SGND
GND_CHASSIS_BATTCONN_HOLE
PP3V42_G3H
NO_TEST=TRUE
CHGR_CSI_R_N
MIN_NECK_WIDTH=0.25mm
MIN_LINE_WIDTH=0.6mm
PPVDCIN_G3H_R
MIN_NECK_WIDTH=0.25mm
PPVBAT_G3H_CHGR_OUT
MIN_LINE_WIDTH=0.6mm
CHGR_CSO_R_P
PPDCIN_G3H
MIN_LINE_WIDTH=0.2mm
TCHG_EN_DIV_L
MIN_NECK_WIDTH=0.2mm
PPVBATT_G3H_PRE
MIN_NECK_WIDTH=0.25mm
MIN_LINE_WIDTH=0.6mm
CHGR_VCOMP_C
PP18V5_G3H_CHGR
CHGR_CSO_R_N
PPBUS_G3H
NO_TEST=TRUE
CHGR_CSO_R_N
NO_TEST=TRUE
CHGR_CSI_P
TP_CHGR_DCPRN
TP_CHGR_DCSET
SWITCH_NODE=TRUE
MIN_NECK_WIDTH=0.2mm
MIN_LINE_WIDTH=0.6mm
CHGR_PHASE
MIN_NECK_WIDTH=0.2mm
MIN_LINE_WIDTH=0.6mm
CHGR_LGATE
NO_TEST=TRUE
NC_CHGR_BGATE
CHGR_DCIN
CHGR_CSI_N
MIN_LINE_WIDTH=0.2mm
MIN_NECK_WIDTH=0.2mm
CHGR_SGATE
CHGR_VREF
CHGR_ACPRN
CHGR_CSO_N
CHGR_CHLIM
CHGR_CSO_P
CHGR_SGND
TP_CHGR_VADJ
CHGR_ICM
CHGR_ACLIM
CHGR_VDD
CHGR_VDDP
CHGR_ACSET
PPVBATT_G3H_FET
MIN_NECK_WIDTH=0.25mm
MIN_LINE_WIDTH=0.6mm
MIN_NECK_WIDTH=0.25mm
MIN_LINE_WIDTH=0.6mm
BATT_POS
MIN_NECK_WIDTH=0.2mm
MIN_LINE_WIDTH=0.6mm
CHGR_BOOT
MIN_LINE_WIDTH=0.6mm
MIN_NECK_WIDTH=0.2mm
CHGR_UGATE
CHGR_EN
CHGR_VCOMP
CHGR_ICOMP
CHGR_ICM_R
CHGR_SGND
PP3V42_G3H
81D4
81D4
81D4
69C8
69C8
81D4
69B8
69B8
69B8
69C8
69A8
69A8
69A8
69B8
68B8
68B8
68B8
68B8
67D5
67D5
67D5
79B7
67D5
67D3
67D3
67D3
71D7
67D3
66D2
66D2
66D2
68D5
66D2
66C8
66C8
66C8
67C3
66C8
66A8
66A8
66A8
67C1
66A8
53C4
53C4
53C4
65D6
53C4
52D7
52D7
52D7
65B7
52D7
52B7
52B7
52B7
64D7
52B7
52B5
52B5
52B5
64A6
52B5
52B1
52B1
52B1
62D7
52B1
51D4
51D4
51D4
61D7
51D4
51D3
51D3
51D3
61D4
51D3
51C2
51C2
51C2
55D3
51C2
47B5
47B5
69D5
69D5
69D5
68A6
69D5
47B5
43D8
47B5
35B7
69C7
35B7
69C7
69C7
69C7
52A2
69C7
35B7
68C4
42B8
69D5
69D5
35B7
27C3
69C6
27C3
69C6
69C6
69C6
51C5
69C6
27C3
67A8
41C6
69C6
68A2
69C7
27C3
69C6
26D6
69D7
69D5
69B7
26D6
69B7
69B7
52A2
69C8
69B7
48C3
52A2
69B7
69B7
69B7
6A6
26D6
67A6
69C2
5C4
69D6
69C8
69B7
69D7
68A1
69B7
26D6
69D5
69C6
69A6
5D2
69D5
69D4
69C8
69A7
69C4
5D2
69A7
69B7
69C6
69C6
69A7
51D7
69C6
69D6
69A7
69C6
5B1
51B5
51B5
51D7
69A7
69C1
69C6
69A7
69A7
6A4
5D2
49D4
69B7
49D7
66D5
68B3
49D7
5A1
49D7
49D4
69D7
69B8
69A6
69C1
69A6
69B1
69A7
69A6
69C8
69C2
69D7
5D1
69C7
69A7
5D2
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
PCIE_PVSS
PCIE_VDDR_12
PCIE_PVDD_12
PCIE_VSS
(1.2V)
(1.2V)
PCIE_VSS
(2 OF 7)
PCI EXPRESS POWER & GROUND
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
PCIE_REFCLKP
PCIE_REFCLKN
PERST*
PERST*_MASK
PCIE_TEST
PCIE_RX15N
PCIE_RX14P
PCIE_RX13N
PCIE_RX12N
PCIE_RX12P
PCIE_RX1P
PCIE_TX0P
PCIE_TX0N
PCIE_TX1P
PCIE_TX2N
PCIE_TX1N
PCIE_TX2P
PCIE_TX3P
PCIE_TX3N
PCIE_TX4P
PCIE_TX4N
PCIE_TX5P
PCIE_TX5N
PCIE_TX6P
PCIE_TX6N
PCIE_TX7P
PCIE_TX7N
PCIE_TX8N
PCIE_TX8P
PCIE_TX9P
PCIE_TX10P
PCIE_TX9N
PCIE_TX10N
PCIE_TX11P
PCIE_TX11N
PCIE_TX12P
PCIE_TX12N
PCIE_TX13N
PCIE_TX13P
PCIE_TX14N
PCIE_TX14P
PCIE_TX15N
PCIE_TX15P
PCIE_CALRP
PCIE_CALRN
PCIE_CALI
PCIE_RX1N
PCIE_RX2N
PCIE_RX2P
PCIE_RX3P
PCIE_RX3N
PCIE_RX4P
PCIE_RX4N
PCIE_RX5P
PCIE_RX5N
PCIE_RX6N
PCIE_RX6P
PCIE_RX7N
PCIE_RX7P
PCIE_RX8P
PCIE_RX8N
PCIE_RX9P
PCIE_RX9N
PCIE_RX10P
PCIE_RX10N
PCIE_RX11P
PCIE_RX11N
PCIE_RX13P
PCIE_RX14N
PCIE_RX0N
PCIE_RX0P
PCIE_RX15P
PCI-EXPRESS BUS INTERFACE
(1 OF 7)
OUT
OUT
OUT
OUT
OUT
OUT
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
100mA
NC
2000mA
10% 16V
0.1uF
402X5R
C8481
1 2
10% 16V X5R
0.1uF
402
C8482
1 2
X5R10% 16V 402
0.1uF
C8479
1 2
10% 16V X5R
0.1uF
402
C8480
1 2
10% 16V X5R
0.1uF
402
C8477
1 2
0.1uF
10% 16V X5R 402
C8478
1 2
10% 16V X5R
0.1uF
402
C8475
1 2
10% 16V X5R
0.1uF
402
C8476
1 2
10% 16V X5R
0.1uF
402
C8473
1 2
10% 16V X5R
0.1uF
402
C8474
1 2
0.1uF
X5R16V10% 402
C8420
1 2
10% 16V X5R
0.1uF
402
C8471
1 2
10% 16V X5R
0.1uF
402
C8472
1 2
10% 16V X5R
0.1uF
402
C8469
1 2
10% 16V X5R
0.1uF
402
C8470
1 2
10% 16V X5R
0.1uF
402
C8467
1 2
402X5R16V
0.1uF
10%
C8421
1 2
10% 16V X5R
0.1uF
402
C8468
1 2
10% 16V X5R
0.1uF
402
C8465
1 2
10% 16V X5R
0.1uF
402
C8466
1 2
10% 16V X5R
0.1uF
402
C8463
1 2
10% 16V X5R
0.1uF
402
C8464
1 2
402
0.1uF
X5R16V10%
C8450
1 2
10% 16V X5R
0.1uF
402
C8461
1 2
10% 16V X5R 402
0.1uF
C8462
1 2
10% 16V X5R
0.1uF
402
C8459
1 2
10% 16V X5R
0.1uF
402
C8460
1 2
10% 16V X5R
0.1uF
402
C8457
1 2
0.1uF
402X5R16V10%
C8451
1 2
10% 16V X5R 402
0.1uF
C8458
1 2
562
1%
402
1/16W
MF-LF
R8496
1
2
1/16W
402
MF-LF
2.0K
1%
R8495
1
2
1/16W
MF-LF
402
1%
1.47K
R8497
1
2
OMIT
M56P
BGA
U8400
N23
P23
U23
V23
W23
N25
N26
AM28
AM29
AM30
AM31
N27
N28
N29
AL29
AL30
AL31
AL32
AM27
N24
N30
R25
R26
R29
R31
T24
T26
T27
T29
U24
U26
P24
U28
U29
U30
V24
V25
V26
V29
V31
W24
W26
P25
W27
W29
Y24
Y26
Y28
Y29
Y30
AA23
AA25
AA26
P26
AA29
AA31
AB23
AB26
AB27
AB29
AC23
AC24
AC26
AC28
P28
AC29
AC30
AD25
AD26
AD29
AD31
AE26
AE27
AE29
AF26
P29
AF28
AF29
AF30
AG25
AG26
AG29
AG31
AH24
AH26
AH27
P30
AH29
AJ26
AJ28
AJ29
AJ30
AJ32
AK26
AK29
AK30
AK31
R23
AK32
AL27
R24
10%
402
6.3V
1uF
CERM
C8402
1
2
402
0.1uF
X5R16V10%
C8448
1 2
1uF
6.3V
10%
CERM
402
C8401
1
2
402
CERM
6.3V
10%
1uF
C8407
1
2
402
0.1uF
X5R16V10%
C8449
1 2
1uF
402
CERM
6.3V
10%
C8413
1
2
10%
6.3V
CERM
402
1uF
C8406
1
2
6.3V
CERM
402
10%
1uF
C8411
1
2
1uF
402
CERM
6.3V
10%
C8412
1
2
22UF
6.3V
805
CERM
20%
C8400
1
2
22UF
6.3V
805
CERM
20%
C8410
1
2
402
0.1uF
X5R16V10%
C8446
1 2
20%
CERM
805
6.3V
22UF
C8405
1
2
0402
200-OHM-EMI
L8400
1
2
22UF
6.3V
805
CERM
20%
C8414
1
2
402
0.1uF
X5R16V10%
C8447
1 2
402
0.1uF
X5R16V10%
C8444
1 2
402
0.1uF
X5R16V10%
C8445
1 2
402
0.1uF
X5R16V10%
C8442
1 2
402
0.1uF
X5R16V10%
C8443
1 2
402
0.1uF
X5R16V10%
C8440
1 2
402
0.1uF
X5R16V10%
C8441
1 2
402
0.1uF
X5R16V10%
C8438
1 2
0.1uF
402X5R16V10%
C8439
1 2
402
0.1uF
X5R16V10%
C8436
1 2
402
0.1uF
X5R16V10%
C8437
1 2
402
0.1uF
X5R16V10%
C8434
1 2
402
0.1uF
X5R16V10%
C8435
1 2
402
0.1uF
X5R16V10%
C8432
1 2
402
0.1uF
X5R16V10%
C8433
1 2
402
0.1uF
X5R16V10%
C8430
1 2
0.1uF
402X5R16V10%
C8431
1 2
402
0.1uF
X5R16V10%
C8428
1 2
402
0.1uF
X5R16V10%
C8429
1 2
402
0.1uF
X5R16V10%
C8426
1 2
402
0.1uF
X5R16V10%
C8427
1 2
10% 402
0.1uF
X5R16V
C8424
1 2
402
0.1uF
X5R16V10%
C8425
1 2
16V 402X5R10%
0.1uF
C8422
1 2
402
0.1uF
X5R16V10%
C8423
1 2
402
0.1uF
X5R16V10%
C8455
1 2
402
0.1uF
X5R16V10%
C8456
1 2
OMIT
BGA
M56P
U8400
AB24
AE24
AD24
AK28
AL28
AH31
AJ31
V30
W30
U32
V32
T31
U31
R30
T30
P32
R32
N31
P31
AG30
AH30
AF32
AG32
AE31
AF31
AD30
AE30
AC32
AD32
AB31
AC31
AA30
AB30
Y32
AA32
W31
Y31
AA24
AJ27
AK27
W25
Y25
V28
W28
U27
V27
T25
U25
R28
T28
P27
R27
AH25
AJ25
AG28
AH28
AF27
AG27
AE25
AF25
AD28
AE28
AC27
AD27
AB25
AC25
AA28
AB28
Y27
AA27
AG24
AF24
10% 16V X5R
0.1uF
402
C8485
1 2
10% 16V X5R
0.1uF
402
C8486
1 2
10% 16V X5R
0.1uF
402
C8483
1 2
10% 16V X5R
0.1uF
402
C8484
1 2
SYNC_DATE=(MASTER)
SYNC_MASTER=(MASTER)
ATI M56 PCI-E
70 87
06004051-7164
PP1V2_D3C
PEG_D2R_C_P<15>
PEG_D2R_C_P<14>
PEG_D2R_C_P<13>
PEG_D2R_C_P<12>
PEG_D2R_C_P<11>
PEG_D2R_C_P<10>
PEG_D2R_C_P<9>
PEG_D2R_C_P<8>
PEG_D2R_C_P<7>
PEG_D2R_C_P<6>
PEG_D2R_C_P<5>
PEG_D2R_C_P<4>
PEG_D2R_C_P<3>
PEG_D2R_C_P<2>
PEG_D2R_C_P<1>
PEG_D2R_C_P<0>
PEG_D2R_N<15>
PEG_D2R_N<14>
PEG_D2R_P<15>
PEG_D2R_N<13>
PEG_D2R_P<14>
PEG_D2R_P<13>
PEG_D2R_P<12>
PEG_D2R_P<11>
PEG_D2R_N<11>
PEG_D2R_P<10>
PEG_D2R_N<10>
PEG_D2R_P<9>
PEG_D2R_N<9>
PEG_D2R_N<8>
PEG_D2R_P<8>
PEG_D2R_N<7>
PEG_D2R_P<7>
PEG_D2R_N<6>
PEG_D2R_N<5>
PEG_D2R_P<6>
PEG_D2R_P<5>
PEG_D2R_P<4>
PEG_D2R_N<4>
PEG_D2R_P<3>
PEG_D2R_N<3>
PEG_D2R_P<2>
PEG_D2R_N<2>
PEG_D2R_P<1>
PEG_D2R_N<0>
PEG_D2R_P<0>
PEG_D2R_C_N<15>
PEG_D2R_C_N<14>
PEG_D2R_C_N<13>
PEG_D2R_C_N<12>
PEG_D2R_C_N<11>
PEG_D2R_C_N<10>
PEG_D2R_C_N<9>
PEG_D2R_C_N<8>
PEG_D2R_C_N<7>
PEG_D2R_C_N<6>
PEG_D2R_C_N<5>
PEG_D2R_C_N<4>
PEG_D2R_C_N<3>
PEG_D2R_C_N<1>
PEG_D2R_C_N<0>
GPU_PCIE_CALRN
PEG_R2D_C_N<15>
PEG_CLK100M_GPU_N
PEG_RESET_L
PEG_CLK100M_GPU_P
PEG_R2D_C_P<15>
PEG_R2D_C_N<12>
PEG_R2D_C_P<13>
PEG_R2D_C_P<12>
PEG_R2D_C_N<11>
PEG_R2D_C_P<11>
PEG_R2D_C_N<10>
PEG_R2D_C_P<10>
PEG_R2D_C_N<9>
PEG_R2D_C_P<8>
PEG_R2D_C_N<8>
PEG_R2D_C_N<7>
PEG_R2D_C_P<7>
PEG_R2D_C_N<6>
PEG_R2D_C_N<5>
PEG_R2D_C_P<6>
PEG_R2D_C_N<4>
PEG_R2D_C_P<4>
PEG_R2D_C_N<3>
PEG_R2D_C_P<3>
PEG_R2D_C_N<2>
PEG_R2D_C_P<2>
PEG_R2D_C_P<1>
PEG_R2D_C_N<1>
PEG_R2D_C_P<0>
PEG_R2D_C_N<0>
PEG_R2D_P<15>
PEG_R2D_P<14>
PEG_R2D_P<13>
PEG_R2D_P<12>
PEG_R2D_P<11>
PEG_R2D_P<10>
PEG_R2D_P<9>
PEG_R2D_P<8>
PEG_R2D_P<7>
PEG_R2D_P<6>
PEG_R2D_P<4>
PEG_R2D_P<3>
PEG_R2D_P<2>
PEG_R2D_P<1>
PEG_R2D_P<0>
PEG_R2D_N<15>
PEG_R2D_N<14>
PEG_R2D_N<13>
PEG_R2D_N<12>
PEG_R2D_N<10>
PEG_R2D_N<11>
PEG_R2D_N<7>
PEG_R2D_N<8>
PEG_R2D_N<9>
PEG_R2D_N<5>
PEG_R2D_N<6>
PEG_R2D_N<3>
PEG_R2D_N<2>
PEG_R2D_N<1>
PEG_R2D_N<0>
GPU_PCIE_CALI
GPU_PCIE_CALRP
PEG_R2D_C_N<14>
PEG_R2D_C_P<14>
PEG_R2D_C_N<13>
PEG_R2D_C_P<5>
PEG_R2D_N<4>
PEG_D2R_C_N<2>
PEG_R2D_C_P<9>
PEG_R2D_P<5>
PEG_D2R_N<12>
PEG_D2R_N<1>
MIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.25 mm
VOLTAGE=1.2V
PP1V2_S0_PCIE_GPU_PVDD_F
PP1V2_D3C
PP1V2_D3C
82D7
82D7
82D7
77B8
77B8
77B8
70C7
70C7
70C7
70A1
70A1
67D8
67D8
67D8
67D6
67D6
67D6
67C6
34B5
34B5
67C6
67C6
63B1
34B4
26B1
34B4
63B1
63B1
5D4
13C3
13C3
13C3
13C3
13C3
13C3
13C3
13C3
13C3
13C3
13C3
13C3
13D3
13D3
13C3
13D3
13C3
13D3
13D3
13C3
13C3
13C3
13D3
13C3
13D3
13C3
13D3
13C3
13D3
13C3
13B3
33B4
5C4
33B4
13A3
13B3
13A3
13A3
13B3
13B3
13B3
13B3
13B3
13B3
13B3
13B3
13B3
13B3
13B3
13B3
13B3
13B3
13B3
13B3
13C3
13B3
13B3
13C3
13B3
13C3
13B3
13A3
13B3
13B3
13B3
13C3
13D3
5D4
5D4
PGND
PHASE
UG
LG
PVCC
FCCM
EN
PGOOD
COMP
FSET
ISEN
FB
VO
BOOT
VIN
THRML
PAD
VCC
PG
EN
VIN
ADJ
VOUT
GND
G
D
S
OUT
G
D
S
G
D
S
G
D
S
CAP-
FB
OUT
SHDN_L
CAP+
LIN/SKIP_L
IN
GND
V-
V+
+
-
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
<Rb>
<Rc>
GPU VCore Supply
close to inductor
Placement Note:
R8590, R8594 and R8597
Keep C8590, C8591
Req = Rb || Rc
Back-Bias Negative Supply
GPU VCore Current Sense
Back-bias negative supply provides VSS - 0.55V when active.
Vout = -0.55V
Vout = 1.10V / 0.95V
<Rb>
Recommended values:
Ra = Vin / 50 uA
Rb = -Vout / 50 uA
When inactive, provides VSS to BBN pins.
(LDO limit)
180mA max output
Vout = (1.58V /) 1.50V
Req = Rb || Rc
Vout(low) = 0.59V * (1 + Ra/Rb)
<Rc>
<Ra>
125mA max output
(Regulator limit)
Vout = -Vin * Rb / Ra
<Ra>
satisfy BBP FET Vgs (where Vs = 1.2V)
<Ra>
<Rb>
When inactive, provides VDDC to BBP pins.
For proper M56 power sequence, this
Vin must be > 2.8V
SI3446DV max Vgs is 1.6V
Pull-up voltage must be high enough to
NOTE: BBP tracks VDDC based on GPU voltage GPIO.
pull-up must be powered before VCore
Vout(high) = 0.59V * (1 + Ra/Req)
Back-bias positive supply provides VDDC + 0.5V when active.
Back-Bias Positive Supply
Vout(low) = 0.6V * (1 + Ra / Rb)
Vout(high) = 0.6V * (1 + Ra / Req)
(L8520 limit)
18A max output
(GPUVCORE_FB)
Stuff 4.7ohm for
decreased slew rate
2.5V
330UF
POLY
CASE-D2E-LF
20%
C8542
1
2
402
1%
MF-LF
1/16W
3.01K
R8521
1
2
402
1%
5.11K
MF-LF
1/16W
R8522
1
2
1/16W
1%
402
MF-LF
5.11K
R8510
1 2
20%
2.2UF
603
CERM1
6.3V
C8502
1
2
2.2UF
603
20%
CERM1
6.3V
C8500
1
2
603
X5R
16V
10%
1uF
C8501
1
2
QFN
ISL6269BCRZ
CRITICAL
U8500
13
5
4
6
3
7
9
11
10
16
15
12
17
14
2
1
8
5%
15pF
50V
402
CERM
C8507
1
2
150K
1/16W
1%
402
MF-LF
R8508
1
2
470pF
CERM
50V
402
10%
C8508
1
2
402
5%
MF-LF
1/16W
0
R8504
1
2
0
1/16W
5%
402
MF-LF
NO STUFF
R8505
1
2
57.6K
MF-LF
402
1%
1/16W
R8506
1
2
0.01UF
CERM
402
10%
16V
C8506
1
2
22UF
805
CERM
20%
6.3V
C8540
1
2
6.3V
22UF
20%
805
CERM
C8541
1
2
SM
XW8500
1 2
NO STUFF
25V
1000pF
X7R
402
10%
C8522
1
2
NO STUFF
402
25V
X7R
1000pF
10%
C8521
1
2
6.3V
20%
805
CERM
22UF
C8556
1
2
805
6.3V
CERM
20%
22UF
C8557
1
2
24.9K
1%
402
MF-LF
1/16W
R8555
1
2
MF-LF
402
1%
1/16W
16.2K
R8556
1
2
0.01UF
CERM
402
10%
16V
C8555
1
2
CRITICAL
SOT23-6-LF
FAN2558
U8550
53
2
4
1 6
20%
6.3V
2.2uF
603
CERM1
C8551
1
2
2.5V
330UF
20%
CASE-D2E-LF
POLY
C8543
1
2
7.32K
402
1%
MF-LF
1/16W
R8523
1 2
10K
MF-LF
402
5%
1/16W
R8560
1
2
SOT23-LF
2N7002
Q8570
3
1
2
MF-LF
1/16W
402
4.7K
1%
R8570
1
2
CERM
402
10%
0.0022uF
50V
NO STUFF
C8570
1
2
1/16W
5%
402
MF-LF
0
GPU_BB_CTL
R8561
1 2
10%
CERM
402
470pF
50V
C8598
12
55B6
10%
CERM
470pF
50V
402
C8592
12
1/16W
1%
1M
MF-LF
402
R8598
1 2
1/16W
MF-LF
1%
1M
402
R8592
1 2
6.3V
10%
402
CERM
1uF
C8595
1
2
1%
1/16W
402
MF-LF
20.0K
R8593
1 2
1/16W
402
MF-LF
1%
20.0K
R8591
1 2
402
MF-LF
1/16W
1%
649
R8590
1
2
1/16W
MF-LF
402
1K
1%
NO STUFF
R8594
1 2
10%
CERM-X5R
0.47UF
6.3V
402
C8590
12
0603-LF
10KOHM-5%
CRITICAL
R8597
1
2
402
1%
1K
1/16W
MF-LF
R8596
1
2
MF-LF
402
174K
1/16W
1%
NO STUFF
R8554
1
2
402
10%
16V
0.022uF
CERM-X5R
C8523
1
2
10K
402
MF-LF
1/16W
5%
R8524
1
2
1/16W
5%
MF-LF
402
10K
R8525
1 2
CERM
50V
10%
0.0022uF
NO STUFF
402
C8520
1
2
5%
1/16W
MF-LF
10K
402
R8526
1
2
2N7002DW-X-F
SOT-363
Q8523
3
5
4
SOT-363
2N7002DW-X-F
Q8523
6
2
1
SOT23-LF
2N7002
NO STUFF
Q8554
3
1
2
1%
MF-LF
1/16W
402
68.1K
R8587
1
2
MF-LF
1/16W
402
1%
11.3K
R8588
1
2
20%
6.3V
CERM1
603
2.2uF
C8581
1
2
603
20%
10uF
X5R
6.3V
C8580
1
2
6.3V
20%
CERM
22UF
805
C8589
1
2
MAX1673
SOI
CRITICAL
U8580
3
2
6
7
8
1
5
4
TSOP-LF
SI3446DV
Q8575
1
2
5
63
4
NO STUFF
0
MF-LF
402
5%
1/16W
R8520
1
2
20%
6.3V
X5R
402
0.22UF
C8509
1
2
20%
33uF
16V
POLY
CASED2E-SM
CRITICAL
C8530
1
2
RJK0305DPB
CRITICAL
LFPAK
Q8520
5
4
1 2 3
RJK0301DPB
CRITICAL
LFPAK
Q8522
5
4
1 2 3
RJK0301DPB
CRITICAL
LFPAK
Q8521
5
4
1 2 3
CRITICAL
1.2UH
FDA1055
L8520
1 2
10%
402
6.3V
0.22UF
CERM-X5R
C8591
12
HPA00141AIDCKR
CRITICAL
SC70-5
U8595
1
3
4
2
5
4.7
402
MF-LF
1/16W
5%
R8509
1
2
SM
XW8502
1 2
SM
XW8501
1 2
SYNC_DATE=(MASTER)
GPU (M56) Core Supplies
SYNC_MASTER=(MASTER)
06004
71 87
051-7164
MIN_NECK_WIDTH=0.25 mm
GPUVCORE_BOOT_R
MIN_LINE_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.25 mm
GPUVCORE_BOOT
GND_GPUVCORE_SGND
P1V2R2V5D3C_EN_LS5V
GPUISENS_POS
GPUVCORE_IOUT
PP3V3_S0
GPUBBP_ADJ
GPUBB_EN_L
PPVCORE_D3C_GPU
GPUBB_EN_L
PPBB_S0_GPU
GPUBB_EN
GPU_GENERICD
PP5V_S0
GPU_VCORE_HIGH
GPUBB_EN
PP3V3_D3C
GPUBBP_ADJ_LOW
GPUVCORE_COMP_R
GPUVCORE_FSET
GPUVCORE_COMP
GPUVCORE_FCCM
GPUVCORE_EN
GPU_VCORE_LOW
PP3V3_D3C
MIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.38 mm
GPUBBN_CAPN
MIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.38 mm
GPUBBN_CAPP
GPUBB_EN
GPUVCORE_FB_RC
GPUISENS_NTC
PNBB_S0_GPU
PP3V3_D3C
GPUBBN_FB
PP5V_S5
GPU_VCORE_HIGH
MIN_LINE_WIDTH=0.6 mm
GPUVCORE_UG
MIN_NECK_WIDTH=0.25 mm
GPUVCORE_ISEN
GPUISENS_RC
GPUISENS_NEG
PPBUS_G3H
MIN_NECK_WIDTH=0.25 mm
SWITCH_NODE=TRUE
GPUVCORE_PHASE
MIN_LINE_WIDTH=0.6 mm
GPUVCORE_FB_LOW
GPU_VCORE_HIGH_RC
GPUVCORE_FB
PPVCORE_D3C_GPU
GND_GPUVCORE_PGND
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm
GPUVCORE_LG
82D5 82C6 82B3 82A4 79D3 79A8
67C5 67C3 67B3 67A3 66B6 66B5 66B1 65D6 65B3
62A6 61D8 61A5 60D4 60C7 58C7 58C4 57B6 54D4
54B5 52D3 49C7 49C4 49B5 40B6 36D6 34A8 33D8
33D3 33C7 29A6 29A3 28A6 27D8 27D5 27D3 27C3 26D1
26B8 26B6 26B4 25D8 25D3 25C6 25C4 25B8 25B4
25A4
81B3
24D3
80B5
24C3
80A1
79B7
24B5
79B8
69C1
24B3
67B3
67C3
68D5
23D5
67B1
67C1
67C3
23B3
67A1
82D7
82D7
82D7
67B1
67C1
22B5
66B5
82A7
82A7
82A7
66D8
65D6
21D3
62B1
80D5
80D5
80D5
66B8
65B7
21C3
61D7
80B2
80B2
80B2
65D6
64D7
20B4
58C7
77D2
77D2
77D2
65B7
64A6
20A4
58C4
77C6
77C6
77C6
64C8
62D7
19C7
77A7
57B5
77B7
77B7
77B7
62C8
61D7
77A7
19C6
72D8
55A8
74D6
74D6
74D6
62B6
61D4
72D8
17C6
71C1
53C4
74B2
74B2
74B2
62B2
55D3
71B7
66D8
14D6
67A8
36D6
71C4
71C4
71B8
62A4
43D8
67A8
66D7
14C7
67A6
31C5
71A4
71B8
71A4
52B5
42B8
67A6
66D4
10C5
55C7
72D6
25D8
67A5 77C3
67A5
72D2
67A5
47C7
41C6
55C7
63C3
5D4
55A5
67D3
71B8
5D4
71A6
67A3 74C8
67A3
71B8
67D3
67A3
25C8
5C4
55A5
63B3
5A4
5C7
71B7
5B2
71A5
67D1
71A4
77C3
5D2
71B4
71A4
65C7
5C7
5D7
66B5
74C5
65C7
71A6
67D1
65C7
5D4
71A8
5A1
5B2
MEMORY & CORE POWER / GROUND
(1.0V/1.2V)
(1.0V/1.2V)
(7 OF 7)
VDDR1
VSS
VSS
(1.8V/2.0V)
VSS
VDDC
BBP BBN
VDDCI
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
100mA (Preliminary)
100mA (Preliminary)
2.0A @ 500MHz 1.8V GDDR3
14.2A @ 445/452MHz Core/Mem Clk for VDDC+VDDCI
- =PP1V5_GPU_VDD15
Power aliases required by this page:
Page Notes
Signal aliases required by this page:
BOM options provided by this page:
- =PP1VR1V3_GPU_VCORE
(NONE)
(NONE)
OMIT
BGA
M56P
U8400
K15
R10
Y23
AC17
K18
M23
V10
AC14
P14
P18
U15
U16
U17
V14
V15
V16
V18
W14
W15
W19
P19
AC11
AC12
AD11
R15
R17
R18
R19
T16
T17
T18
K14
P16
T14
T23
U19
W10
W17
A3
A9
F32
H13
H19
J1
J10
J11
J13
J18
J19
J20
A12
J32
K11
K13
K19
K20
K21
K24
L23
L24
L32
A15
M1
M10
N9
N10
P8
P9
P10
R1
R9
V1
A18
Y8
Y9
Y10
AA1
A21
A24
A30
C1
C32
K23
A2
B1
R3
R6
R14
R16
T10
T15
T19
U1
U5
U6
B32
U7
U8
U9
U10
U14
U18
V3
V6
V17
V19
C4
W16
W18
Y1
Y5
Y6
Y7
AA4
AA6
AC9
AC10
C5
AD6
AD7
AD8
AD9
AD10
AD13
AD14
AD15
AD16
AD17
C6
AE8
AE14
AE15
AE16
AE17
AF14
AF16
AG11
AG16
AG23
C9
AH10
AH11
AH16
AJ10
AK16
AL1
AL13
AM2
AM13
C10
C15
C18
C20
A8
C21
C24
C27
D11
D30
E5
E8
E9
E12
E13
A11
E16
E19
E25
E28
E30
E32
F3
F6
F10
F13
A13
F15
F16
F18
F19
F21
F22
F24
F27
F30
G13
A16
G16
G19
G20
G21
G22
G25
H1
H5
H7
H16
A19
H20
H21
H28
H32
J3
J6
J9
J12
J16
J21
A22
J24
J28
J30
K10
K12
K16
K17
K27
K30
L1
A25
L6
L7
L29
M3
M6
M7
M8
M9
M24
M28
A31
M32
N3
N7
N8
P1
P5
P6
P7
P15
P17
0.1uF
402
X5R
16V
10%
C8697
1
2
10%
402
1uF
CERM
6.3V
C8696
1
2
10%
402
1uF
CERM
6.3V
C8691
1
2
0.1uF
402
X5R
16V
10%
C8692
1
2
CERM
6.3V
1uF
402
10%
C8610
1
2
6.3V
CERM
1uF
402
10%
C8609
1
2
6.3V
CERM
1uF
402
10%
C8608
1
2
6.3V
CERM
1uF
402
10%
C8607
1
2
6.3V
CERM
1uF
402
10%
C8606
1
2
6.3V
CERM
1uF
402
10%
C8605
1
2
402
6.3V
CERM
1uF
10%
C8604
1
2
10%
402
1uF
CERM
6.3V
C8616
1
2
10%
402
1uF
CERM
6.3V
C8615
1
2
10%
402
1uF
CERM
6.3V
C8614
1
2
10%
402
1uF
CERM
6.3V
C8613
1
2
10%
402
1uF
CERM
6.3V
C8612
1
2
1/10W
603
0
5%
MF-LF
R8630
1
2
6.3V
CERM
1uF
402
10%
C8634
1
2
6.3V
CERM
1uF
402
10%
C8633
1
2
6.3V
CERM
1uF
402
10%
C8632
1
2
6.3V
CERM
1uF
402
10%
C8631
1
2
6.3V
CERM
1uF
402
10%
C8660
1
2
10%
402
1uF
CERM
6.3V
C8666
1
2
6.3V
CERM
1uF
402
10%
C8659
1
2
6.3V
CERM
1uF
402
10%
C8658
1
2
6.3V
CERM
1uF
402
10%
C8657
1
2
10%
402
1uF
CERM
6.3V
C8665
1
2
10%
402
1uF
CERM
6.3V
C8664
1
2
10%
402
1uF
CERM
6.3V
C8663
1
2
6.3V
CERM
1uF
402
10%
C8656
1
2
10%
402
1uF
CERM
6.3V
C8662
1
2
6.3V
CERM
1uF
402
10%
C8655
1
2
10%
402
1uF
CERM
6.3V
C8661
1
2
6.3V
CERM
1uF
402
10%
C8672
1
2
10%
402
1uF
CERM
6.3V
C8678
1
2
6.3V
CERM
1uF
402
10%
C8671
1
2
6.3V
CERM
1uF
402
10%
C8670
1
2
6.3V
CERM
1uF
402
10%
C8669
1
2
10%
402
1uF
CERM
6.3V
C8677
1
2
10%
402
1uF
CERM
6.3V
C8676
1
2
10%
402
1uF
CERM
6.3V
C8675
1
2
6.3V
CERM
1uF
402
10%
C8668
1
2
10%
402
1uF
CERM
6.3V
C8674
1
2
CERM
6.3V
1uF
402
10%
C8667
1
2
10%
402
1uF
CERM
6.3V
C8673
1
2
6.3V
CERM
22UF
805
20%
C8653
1
2
20%
6.3V
CERM
805
22UF
C8652
1
2
CERM
6.3V
22UF
805
20%
C8651
1
2
22UF
805
CERM
6.3V
20%
C8650
1
2
10%
402
1uF
CERM
6.3V
C8683
1
2
10%
402
1uF
CERM
6.3V
C8682
1
2
10%
402
1uF
CERM
6.3V
C8681
1
2
10%
402
1uF
CERM
6.3V
C8680
1
2
6.3V
CERM
1uF
402
10%
C8679
1
2
22UF
805
CERM
6.3V
20%
C8601
1
2
6.3V
CERM
1uF
402
10%
C8611
1
2
20%
6.3V
CERM
805
22UF
C8690
1
2
20%
6.3V
CERM
805
22UF
C8695
1
2
20%
6.3V
CERM
805
22UF
C8630
1
2
20%
6.3V
CERM
805
22UF
C8600
1
2
ATI M56 Core Power
06004051-7164
8772
SYNC_MASTER=(MASTER)
SYNC_DATE=(MASTER)
PNBB_S0_GPU
PP1V8_D3C
PPBB_S0_GPU
MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.5 mm
PPVCORE_S0_GPU_VDDCI
VOLTAGE=1.2V
PPVCORE_D3C_GPU
82D7
76D8 76D5 75D8 75D5 73B8
77A7
73B5
71C1
73A8
71B7
73A5
67A8
67B8
67A6
71A2
67B6
71B5
55C7
67D3
64A4
67D3
55A5
67D1
5D4
67D1
5B2
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IN
IN
IN
IN
IN
IN
IN
IN
IO
IO
IO
IO
IO
IO
IO
IO IO
IO
IO
IO
IO
IO
IO
IO
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
DQA_58
DQA_59
WEA1*
DQA_61
DQA_62
MVREFD_0
MVREFS_0
VDDRH0
MAA_0
MAA_1
MAA_2
MAA_3
MAA_4
MAA_5
MAA_6
MAA_7
MAA_8
MAA_9
MAA_10
MAA_11
MAA_12
MAA_13
MAA_14
MAA_15
DQMA_0*
DQMA_1*
DQMA_2*
DQMA_3*
DQMA_4*
DQMA_5*
DQMA_6*
DQMA_7*
QSA_1
QSA_2
QSA_0
QSA_3
QSA_4
QSA_5
QSA_6
QSA_7
QSA_0*
QSA_1*
QSA_2*
QSA_3*
QSA_4*
QSA_5*
QSA_6*
QSA_7*
CLKA0
CLKA0*
CSA0_0*
CKEA0
RASA0*
CASA0*
WEA0*
ODTA0
CLKA1*
CSA1_0*
CKEA1
RASA1*
CASA1*
ODTA1
DQA_0
DQA_1
DQA_2
DQA_3
DQA_4
DQA_5
DQA_6
DQA_7
DQA_8
DQA_9
DQA_10
DQA_11
DQA_12
DQA_13
DQA_14
DQA_15
DQA_16
DQA_17
DQA_18
DQA_19
DQA_20
DQA_21
DQA_22
DQA_23
DQA_24
DQA_25
DQA_26
DQA_27
DQA_28
DQA_29
DQA_30
DQA_31
DQA_32
DQA_33
DQA_34
DQA_35
DQA_36
DQA_37
DQA_38
DQA_39
DQA_40
DQA_41
DQA_42
DQA_43
DQA_45
DQA_44
DQA_46
DQA_47
DQA_48
DQA_50
DQA_51
DQA_49
DQA_52
DQA_53
DQA_54
DQA_55
DQA_56
DQA_57
DQA_60
DQA_63
VSSRH0
CLKA1
CSA0_1*
CSA1_1*
WRITE STROBE
READ STROBE
MEMORY INTERFACE A
(3 OF 7)
2.0V)
(1.8V/
DQB_62
VDDRH1
MVREFS_1
MAB_0
MAB_1
MAB_2
MAB_3
MAB_4
MAB_5
MAB_6
MAB_7
MAB_8
MAB_9
MAB_10
MAB_11
MAB_12
MAB_15
MAB_14
MAB_13
DQMB_0*
DQMB_1*
DQMB_2*
DQMB_3*
DQMB_4*
DQMB_5*
DQMB_6*
DQMB_7*
QSB_0
QSB_1
QSB_2
QSB_4
QSB_3
QSB_5
QSB_6
QSB_7
QSB_0*
QSB_1*
QSB_2*
QSB_3*
QSB_4*
QSB_5*
QSB_6*
QSB_7*
CLKB0*
CLKB0
CSB0_0*
CKEB0
RASB0*
WEB0*
CASB0*
ODTB0
CLKB1
CLKB1*
CKEB1
RASB1*
WEB1*
CASB1*
ODTB1
DRAM_RST
DQB_0
DQB_1
DQB_2
DQB_3
DQB_4
DQB_5
DQB_6
DQB_7
DQB_8
DQB_9
DQB_10
DQB_11
DQB_12
DQB_15
DQB_14
DQB_13
DQB_16
DQB_17
DQB_18
DQB_20
DQB_19
DQB_22
DQB_21
DQB_23
DQB_25
DQB_24
DQB_27
DQB_26
DQB_28
DQB_30
DQB_29
DQB_33
DQB_31
DQB_32
DQB_35
DQB_34
DQB_37
DQB_36
DQB_38
DQB_40
DQB_41
DQB_42
DQB_43
DQB_44
DQB_45
DQB_46
DQB_48
DQB_47
DQB_52
DQB_53
DQB_56
DQB_55
DQB_54
DQB_58
DQB_57
DQB_60
DQB_59
DQB_61
DQB_63
MVREFD_1
VSSRH1
TEST_MCLK
TEST_YCLK
MEMTEST
DQB_39
CSB1_0*
DQB_51
DQB_50
DQB_49
CSB0_1*
CSB1_1*
WRITE STROBE
READ STROBE
MEMORY INTERFACE B
(4 OF 7)
(1.8V/
2.0V)
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
- =PP1V8R2V0_S0_FB_GPU
BOM options provided by this page:
Signal aliases required by this page:
Power aliases required by this page:
(NONE)
(NONE)
NC
NC NC
NC
Page Notes
40.2
402
MF-LF
1/16W
1%
R8722
1
2
40.2
402
MF-LF
1/16W
1%
R8720
1
2
10%
16V
X5R
402
0.1uF
C8723
1
2
1%
1/16W
MF-LF
402
100
R8723
1
2
1%
MF-LF
402
100
1/16W
R8721
1
2
10%
X5R
402
0.1uF
16V
C8721
1
2
0.1uF
402
X5R
16V
10%
C8713
1
2
40.2
402
MF-LF
1/16W
1%
R8712
1
2
1/16W
1%
MF-LF
402
100
R8713
1
2
0.1uF
10%
16V
X5R
402
C8711
1
2
40.2
402
MF-LF
1/16W
1%
R8710
1
2
1%
1/16W
MF-LF
402
100
R8711
1
2
MF-LF
1/16W
1%
243
402
R8732
1
2
402
4.7K
5%
1/16W
MF-LF
R8731
1
2
MF-LF
1/16W
5%
402
4.7K
R8730
1
2
4.7K
402
MF-LF
1/16W
5%
R8733
1
2
OMIT
BGA
M56P
U8400
C29
B22
B30
C22
D31
E31
B20
C19
B29
C28
B23
C23
M31
M30
L28
L27
J27
H29
G29
G27
M26
L26
M25
L25
L31
J25
G28
H27
H26
F26
G26
H25
H24
H23
H22
L30
J23
J22
E23
D22
D23
E22
E20
F20
D19
D18
H30
B19
B18
C17
B17
C14
B14
C13
B13
D17
E18
G31
E17
F17
E15
E14
F14
D13
H18
H17
G18
G17
G30
G15
G14
H14
J14
F31
M27
M29
H31
J29
J26
G23
E21
B15
D14
J17
D26
F28
D29
B27
E27
E29
B25
C25
D28
D25
E24
E26
D27
F25
C26
B26
C31
C30
F29
D24
J31
K31
K29
K28
K25
K26
F23
G24
D20
D21
B16
C16
D16
D15
H15
J15
B28
B24
A27
A28
B31
B21
OMIT
BGA
M56P
U8400
D3
L2
C2
L3
B4
B5
N2
P3
D2
E3
K2
K3
B12
C12
E11
F11
F9
D8
D7
F7
G12
G11
H12
H11
B11
H9
E7
F8
G8
G6
G7
H8
J8
K8
L8
C11
K9
L9
K5
L4
K4
L5
N5
N6
P4
R4
C8
P2
R2
T3
T2
W3
W2
Y3
Y2
T4
R5
B7
T5
T6
V5
W5
W6
Y4
R8
T8
R7
T7
C7
V7
W7
W8
W9
B6
F12
D12
B8
D9
G9
K7
M5
V2
W4
T9
AA3
G4
E6
D4
F2
F5
D5
H2
H3
E4
H4
J5
G5
F4
H6
G3
G2
AA7
B3
C3
D6
J4
B9
B10
D10
E10
H10
G10
K6
J7
N4
M4
U2
U3
U4
V4
V8
V9
E2
J2
AA5
AA2
F1
E1
B2
M2
1uF
CERM
10%
402
6.3V
C8716
1
2
1uF
6.3V
CERM
402
10%
C8715
1
2
6.3V
CERM
1uF
402
10%
C8726
1
2
10%
402
1uF
CERM
6.3V
C8725
1
2
0402
FERR-220-OHM
L8725
1 2
0402
FERR-220-OHM
L8715
1 2
73 87
051-7164 06004
ATI M56 Frame Buffer I/F
SYNC_MASTER=(MASTER)
SYNC_DATE=(MASTER)
PP1V8_D3C
MIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.25 mm
PP1V8R2V0_S0_GPU_VDDRH0
VOLTAGE=1.8V
PP1V8_D3C
PP1V8R2V0_S0_GPU_VDDRH1
VOLTAGE=1.8V
MIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.25 mm
FB_B_DQ<17>
FB_B_DQ<18>
FB_A_CLK_P<0>
FB_A_CS_L<0>
FB_A_BA<2>
PP1V8_D3CPP1V8_D3C
FB_A_CLK_N<0>
FB_A_BA<0>
FB_B_MA<11>
FB_B_MA<10>
FB_A_MA<4>
FB_A_MA<3>
FB_A_DQ<0>
FB_B_DQ<62>
GPU_MVREFS1
FB_B_MA<0>
FB_B_MA<1>
FB_B_MA<2>
FB_B_MA<3>
FB_B_MA<4>
FB_B_MA<5>
FB_B_MA<6>
FB_B_MA<7>
FB_B_MA<8>
FB_B_MA<9>
NC_FB_B_MA12
FB_B_BA<1>
FB_B_BA<0>
FB_B_BA<2>
FB_B_DQM_L<0>
FB_B_DQM_L<1>
FB_B_DQM_L<2>
FB_B_DQM_L<3>
FB_B_DQM_L<4>
FB_B_DQM_L<5>
FB_B_DQM_L<6>
FB_B_DQM_L<7>
FB_B_RDQS<0>
FB_B_RDQS<1>
FB_B_RDQS<2>
FB_B_RDQS<4>
FB_B_RDQS<3>
FB_B_RDQS<5>
FB_B_RDQS<6>
FB_B_RDQS<7>
FB_B_WDQS<0>
FB_B_WDQS<1>
FB_B_WDQS<2>
FB_B_WDQS<3>
FB_B_WDQS<4>
FB_B_WDQS<5>
FB_B_WDQS<6>
FB_B_WDQS<7>
FB_B_CLK_N<0>
FB_B_CLK_P<0>
FB_B_CS_L<0>
FB_B_CKE<0>
FB_B_RAS_L<0>
FB_B_WE_L<0>
FB_B_CAS_L<0>
TP_FB_B_ODT<0>
FB_B_CLK_P<1>
FB_B_CLK_N<1>
FB_B_CKE<1>
FB_B_RAS_L<1>
FB_B_WE_L<1>
FB_B_CAS_L<1>
TP_FB_B_ODT<1>
FB_DRAM_RST
FB_B_DQ<0>
FB_B_DQ<1>
FB_B_DQ<2>
FB_B_DQ<3>
FB_B_DQ<4>
FB_B_DQ<5>
FB_B_DQ<6>
FB_B_DQ<7>
FB_B_DQ<8>
FB_B_DQ<9>
FB_B_DQ<10>
FB_B_DQ<11>
FB_B_DQ<12>
FB_B_DQ<15>
FB_B_DQ<14>
FB_B_DQ<13>
FB_B_DQ<16>
FB_B_DQ<20>
FB_B_DQ<19>
FB_B_DQ<22>
FB_B_DQ<21>
FB_B_DQ<23>
FB_B_DQ<25>
FB_B_DQ<24>
FB_B_DQ<27>
FB_B_DQ<26>
FB_B_DQ<28>
FB_B_DQ<30>
FB_B_DQ<29>
FB_B_DQ<33>
FB_B_DQ<31>
FB_B_DQ<32>
FB_B_DQ<35>
FB_B_DQ<34>
FB_B_DQ<37>
FB_B_DQ<36>
FB_B_DQ<38>
FB_B_DQ<40>
FB_B_DQ<41>
FB_B_DQ<42>
FB_B_DQ<43>
FB_B_DQ<44>
FB_B_DQ<45>
FB_B_DQ<46>
FB_B_DQ<48>
FB_B_DQ<47>
FB_B_DQ<52>
FB_B_DQ<53>
FB_B_DQ<56>
FB_B_DQ<55>
FB_B_DQ<54>
FB_B_DQ<58>
FB_B_DQ<57>
FB_B_DQ<60>
FB_B_DQ<59>
FB_B_DQ<61>
FB_B_DQ<63>
GPU_MVREFD1
GPU_TEST_MCLK
GPU_TEST_YCLK
GPU_MEMTEST
FB_B_DQ<39>
FB_B_CS_L<1>
FB_B_DQ<51>
FB_B_DQ<50>
FB_B_DQ<49>
FB_A_DQ<58>
FB_A_DQ<59>
FB_A_WE_L<1>
FB_A_DQ<61>
FB_A_DQ<62>
GPU_MVREFD0
FB_A_MA<0>
FB_A_MA<1>
FB_A_MA<2>
FB_A_MA<5>
FB_A_MA<6>
FB_A_MA<7>
FB_A_MA<11>
NC_FB_A_MA12
FB_A_DQM_L<0>
FB_A_DQM_L<1>
FB_A_DQM_L<2>
FB_A_DQM_L<3>
FB_A_DQM_L<4>
FB_A_CKE<0>
FB_A_RAS_L<0>
FB_A_CAS_L<0>
FB_A_WE_L<0>
TP_FB_A_ODT<0>
FB_A_CLK_N<1>
FB_A_CS_L<1>
FB_A_CKE<1>
FB_A_RAS_L<1>
FB_A_CAS_L<1>
TP_FB_A_ODT<1>
FB_A_DQ<1>
FB_A_DQ<2>
FB_A_DQ<3>
FB_A_DQ<4>
FB_A_DQ<5>
FB_A_DQ<6>
FB_A_DQ<7>
FB_A_DQ<8>
FB_A_DQ<9>
FB_A_DQ<10>
FB_A_DQ<11>
FB_A_DQ<12>
FB_A_DQ<13>
FB_A_DQ<14>
FB_A_DQ<15>
FB_A_DQ<16>
FB_A_DQ<17>
FB_A_DQ<18>
FB_A_DQ<19>
FB_A_DQ<20>
FB_A_DQ<21>
FB_A_DQ<22>
FB_A_DQ<23>
FB_A_DQ<24>
FB_A_DQ<25>
FB_A_DQ<26>
FB_A_DQ<27>
FB_A_DQ<28>
FB_A_DQ<29>
FB_A_DQ<30>
FB_A_DQ<31>
FB_A_DQ<32>
FB_A_DQ<33>
FB_A_DQ<34>
FB_A_DQ<35>
FB_A_DQ<36>
FB_A_DQ<37>
FB_A_DQ<38>
FB_A_DQ<39>
FB_A_DQ<40>
FB_A_DQ<41>
FB_A_DQ<42>
FB_A_DQ<43>
FB_A_DQ<45>
FB_A_DQ<44>
FB_A_DQ<46>
FB_A_DQ<47>
FB_A_DQ<48>
FB_A_DQ<50>
FB_A_DQ<51>
FB_A_DQ<49>
FB_A_DQ<52>
FB_A_DQ<53>
FB_A_DQ<54>
FB_A_DQ<55>
FB_A_DQ<56>
FB_A_DQ<63>
FB_A_CLK_P<1>
FB_A_MA<9>
FB_A_MA<8>
FB_A_MA<10>
FB_A_BA<1>
FB_A_DQM_L<7>
FB_A_DQM_L<6>
FB_A_RDQS<0>
FB_A_RDQS<1>
FB_A_RDQS<2>
FB_A_RDQS<3>
FB_A_RDQS<4>
FB_A_RDQS<5>
FB_A_RDQS<7>
FB_A_RDQS<6>
FB_A_WDQS<0>
FB_A_WDQS<1>
FB_A_WDQS<3>
FB_A_WDQS<2>
FB_A_WDQS<4>
FB_A_WDQS<5>
FB_A_WDQS<6>
FB_A_WDQS<7>
FB_A_DQ<60>
FB_A_DQM_L<5>
FB_A_DQ<57>
GPU_MVREFS0
82D7
82D7
82D7
82D7
76D8
76D8
76D8 76D8
76D5
76D5
76D5 76D5
75D8
75D8
75D8
75D8
75D5
75D5
75D5
75D5
73B8
73B8
73B8 73B5
73B5
73B5
73A8 73A8
73A5
73A8
73A5 73A5
72B8
72B8
72B8
72B8
67B8
67B8
67B8 67B8
76A8
67B6 67B6
67B6 67B6
76A5
64A4 64A4
75A8
64A4 64A4
75A8
76B8
76B8
75B8
75B8
76B8
76B8
76B8
76B8
76B8
76B8
76B8
76B8
76B8
76B8
74C2
76A8
76A8
76A8
75A8
75B8
75B8
75B8
75B8
75B8
75B8
75B8
74C2
75B8
75B8
75B8
75A8
5D4 5D4
76B6
76B6
75B8
75B8
75A5
5D4 5D4
75B8
75A5
76B5
76B5
75B5
75B5
75B6
76A3
76B5
76B5
76B5
76B5
76B5
76B5
76B5
76B5
76B5
76B5
74C1
76A5
76A5
76A5
76B6
76B6
76B6
76B6
76B3
76B3
76B3
76B3
76A8
76A8
76A8
76A5
76A8
76A5
76A5
76A5
76A8
76A8
76A8
76A8
76A5
76A5
76A5
76A5
76B8
76B8
76B8
76B8
76A8
76A8
76A8
76B5
76B5
76B5
76A5
76A5
76A5
75A5
76A6
76A6
76A6
76A6
76A6
76A6
76A6
76A6
76B6
76B6
76B6
76B6
76B6
76B6
76B6
76B6
76B6
76A6
76B6
76A6
76A6
76A6
76A6
76A6
76A6
76A6
76A6
76A6
76A6
76A3
76A6
76A3
76A3
76A3
76A3
76A3
76A3
76A3
76A3
76A3
76A3
76B3
76B3
76B3
76B3
76B3
76B3
76B3
76A3
76B3
76B3
76A3
76A3
76A3
76A3
76A3
76A3
76A3
76B5
76B3
76B3
76B3
75A3
75A3
75A5
75A3
75A3
75B5
75B5
75B5
75B5
75B5
75B5
75B5
74C1
75B6
75B6
75B6
75B6
75B3
75B8
75A8
75A8
75A8
75B5
75B5
75B5
75A5
75A5
75B6
75B6
75B6
75B6
75B6
75B6
75B6
75B6
75B6
75B6
75B6
75A6
75A6
75A6
75A6
75A6
75A6
75A6
75A6
75A6
75A6
75A6
75A6
75A6
75A6
75A6
75A6
75A6
75A6
75A6
75A6
75B3
75B3
75B3
75B3
75B3
75B3
75B3
75B3
75B3
75B3
75B3
75B3
75A3
75A3
75A3
75A3
75A3
75A3
75A3
75A3
75A3
75A3
75A3
75A3
75A3
75A3
75B5
75B5
75B5
75B5
75A5
75B3
75B3
75A8
75A8
75A8
75A8
75A5
75A5
75A5
75A5
75A8
75A8
75A8
75A8
75A5
75A5
75A5
75A5
75A3
75B3
75A3
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
TESTIN[9] PWRCNTL
SS_IN
Thm Mon Int
Required for debug access
Also required: GPIO10 - GPIO13
TESTOUT[9] ROMIDCFG[0]
IPD
ENA_BL TESTIN[7]
ROMSO TESTWR Reserved
ROMSI ROMIDCFG[3]
ROMSCK TESTOUT[8]
TESTOUT[10] ROMIDCFG[1]
IPD
IPD
IPD
IPD
TESTIN[8]
IPD
TESTIN[1] TX_DEEMPH_EN
Serial ROM TestBus Misc Straps
IPD
TESTIN[4] DEBUG_ACCESS
TESTOUT[11] ROMIDCFG[2]
VDD_VCL TESTIN[2] Reserved
TESTIN[3] Reserved
TESTIN[5] Reserved
TESTIN[6] Reserved
TESTIN[0] TX_PWRS_ENb
Unused signals
Renamed signals
ROMCFGID[3..0]
0100 = 64MB
0110 = Reserved
0010 = 256MB
0000 = 128MB
Required for debug access
Required for debug access
Required for debug access
Required for debug access
402
MF-LF
10K
5%
1/16W
R8800
1
2
GPU_DEEPMH_EN
10K
5%
1/16W
MF-LF
402
R8801
1
2
MF-LF
5%
1/16W
10K
402
NO STUFF
R8802
1
2
5%
1/16W
MF-LF
402
10K
NO STUFF
R8803
1
2
5%
10K
1/16W
402
MF-LF
NO STUFF
R8806
1
2
402
1/16W
5%
10K
MF-LF
NO STUFF
R8804
1
2
1/16W
MF-LF
10K
402
5%
NO STUFF
R8808
1
2
10K
402
MF-LF
1/16W
5%
R8805
1
2
5%
GPU_MEM_256M
1/16W
MF-LF
402
10K
R8812
1
2
1/16W
MF-LF
402
10K
NO STUFF
5%
R8809
1
2
NO STUFF
5%
1/16W
10K
402
MF-LF
R8811
1
2
402
MF-LF
10K
1/16W
5%
GPU_MEM_64M
R8813
1
2
402
4.7K
MF-LF
1/16W
5%
R8891
1
2
MF-LF
1/16W
4.7K
5%
402
R8890
1
2
MF-LF
402
10K
5%
GPU_MEM_256M
1/16W
R8824
1
2
1/16W
MF-LF
10K
402
5%
GPU_MEM_NOT_SAM
R8827
1
2
SYNC_DATE=08/08/2006
051-7164 06004
8774
GPU Straps
SYNC_MASTER=M57_MLB_MG
GPU_DDC_B_CLK
MAKE_BASE=TRUE
GPU_MEMID
MAKE_BASE=TRUE
GPU_MEM_256M
GPU_GPIO_2
GPU_GPIO_9
GPU_GPIO_3
GPU_GPIO_11
GPU_GPIO_6
GPU_GPIO_8
GPU_GPIO_12
GPU_GPIO_4
GPU_GPIO_5
MAKE_BASE=TRUE
TP_ATI_DVPDATA<23..16>
ATI_DVPDATA<23..16>
MAKE_BASE=TRUE
GPU_CLK27M GPU_CLK27M
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_GPU_XTALOUT NC_GPU_XTALOUT
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_ATI_ROMCS_L NC_ATI_ROMCS_L
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_FB_A_MA12 NC_FB_A_MA12
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_FB_B_MA12 NC_FB_B_MA12
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_GPU_GENERICA NC_GPU_GENERICA
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_GPU_GENERICB NC_GPU_GENERICB
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_GPU_GENERICC NC_GPU_GENERICC
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_GPU_VGA_G NC_GPU_VGA_G
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_GPU_VGA_R NC_GPU_VGA_R
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_GPU_VGA_B NC_GPU_VGA_B
MAKE_BASE=TRUE
TP_GPU_VGA_HSYNC TP_GPU_VGA_HSYNC
MAKE_BASE=TRUE
TP_GPU_VGA_VSYNC TP_GPU_VGA_VSYNC
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_GPU_TV_C NC_GPU_TV_C
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_GPU_TV_Y NC_GPU_TV_Y
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_GPU_TV_COMP NC_GPU_TV_COMP
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_LVDS_U_DATAP<3> NC_LVDS_U_DATAP<3>
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_LVDS_U_DATAN<3> NC_LVDS_U_DATAN<3>
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_LVDS_L_DATAP<3> NC_LVDS_L_DATAP<3>
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_ATI_DVPCLK NC_ATI_DVPCLK
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_LVDS_L_DATAN<3> NC_LVDS_L_DATAN<3>
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_ATI_DVPCNTL<2..0>
ATI_DVPCNTL<2..0>
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_ATI_DVPDATA<15..0>
ATI_DVPDATA<15..0>
MAKE_BASE=TRUE
GPU_VCORE_LOW
GPU_MEMID
GPU_MEM_256M
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_GPU_GPIO_25
NC_GPU_GPIO_21
MAKE_BASE=TRUE
NO_TEST=TRUE
GPU_GPIO_1
GPU_GPIO_0
MAKE_BASE=TRUE
GPU_BLON
TP_GPU_GPIO_10
MAKE_BASE=TRUE
MAKE_BASE=TRUE
GPU_CLK27MSS_IN
NC_GPU_GPIO_32
NC_GPU_GPIO_33
NC_GPU_GPIO_34
NC_GPU_GPIO_29
NC_GPU_GPIO_30
NC_GPU_GPIO_31
NC_GPU_GPIO_28
NC_GPU_GPIO_25
NC_GPU_GPIO_26
NC_GPU_GPIO_22
NC_GPU_GPIO_23
NC_GPU_GPIO_21
MAKE_BASE=TRUE
NC_GPU_GPIO_14
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_GPU_GPIO_17
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_GPU_GPIO_18
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_GPU_GPIO_20
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_GPU_GPIO_19
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_GPU_GPIO_23
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_GPU_GPIO_26
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_GPU_GPIO_28
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_GPU_GPIO_31
NO_TEST=TRUE
NC_GPU_GPIO_30
MAKE_BASE=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_GPU_GPIO_29
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_GPU_GPIO_34
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_GPU_GPIO_33
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_GPU_GPIO_32
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_GPU_GPIO_22
TP_GPU_GPIO_10
GPU_BLON
NC_GPU_GPIO_20
NC_GPU_GPIO_19
NC_GPU_GPIO_18
NC_GPU_GPIO_17
PP3V3_D3C
GPU_DDC_B_DATA
GPU_CLK27MSS_IN
GPU_VCORE_LOW
NC_GPU_GPIO_14
GPU_GPIO_13
PP3V3_D3C
82D7
82D7
82A7
82A7
80D5
80D5
80B2
80B2
77D2
77D2
77C6
77C6
77B7
77B7
74D6
74B2
71C4
71C4
71B8
71B8
77A5
77A5
77C3
71A4
77C3
71A4
74C1
74C2
77C3
82A4
74C8
82A4
67A5
74C5
77C3
67A5
77D5
77D5
77B3
34B4 34B4
77A5 77A5
77A3 77A3
74C1 74C2
74C1 74C2
77C3 77C3
77C3 77C3
77C3 77C3
78C3 78C3
78C3 78C3
78C3 78C3
78B3 78B3
78B3 78B3
78B3 78B3
78B3 78B3
78B3 78B3
78B3 78B3
78B3 78B3
78A3 78A3
77C3 77C3
78A3 78A3
77C3
74C8
77D5
77D5
77D5
77D5
77D3
77C3
34B4
77C5
77C5
77C5
77C5
77C5
77C5
77D5
77D5
77D5
77D5
77D5
77D5
77C3
77C3
77D5
77D5
77D5
77D5
77D5
77D5
77C5
77C5
77C5
77C5
77C5
77C5
77D5
77C3
77D3
77D5
77D5
77D5
77C3
67A3
34B4
74C5
77C3
67A3
78A3
74B8
74B8
77D3
77C3
77D3
77C3
77D3
77D3
77C3
77D3
77D3
77A3
34B2 34B2
74C1 74C2
74C1 74C2
73D5 73D5
73D1 73D1
74C1 74C2
74C1 74C2
74C1 74C2
74C1 74C2
74C1 74C2
74C1 74C2
74C1 74C2
74C1 74C2
74B1 74B2
74C1 74C2
74B1 74B2
74B1 74B2
74B1 74B2
74B1 74B2
74B1 74B2
74B1 74B2
77B3
77B3
71B4
74B6
74B6
74B8
74B8
77D3
77D3
74C8
74C8
34B2
74B7
74B7
74B7
74B7
74B7
74B7
74B7
74B7
74B7
74B7
74B7
74B7
74C8
74C8
74B8
74B8
74B8
74B8
74B8
74B8
74B8
74B8
74B8
74B8
74B8
74B8
74B8
74C5
74C5
74B7
74B7
74B7
74C5
65C7
78A3
34B2
71B4
74C5
77C3
65C7
DQ1
DQ0
DQ2
DQ3
DQ5
DQ6
DQ4
DQ8
DQ7
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ24
DQ23
DQ22
DQ25
DQ26
DQ27
DQ29
DQ28
DQ30
DQ31
RDQS3
RDQS2
RDQS1
RDQS0
SEN
RESET
MF
ZQ
RAS*
CAS*
WE*
CS*
CK*
A9
A6
A7
A3
A4
A2
A0
A1
CK
WDQS2
WDQS1
WDQS0
WDQS3
BA0
BA2
BA1
RFU1
RFU2
DM3
DM2
DM1
DM0
A5
A11
A8/AP
A10
CKE
MFHIGH
MFHIGH
MFHIGH
(1 OF 2)
VSS0
VSS1
VSS2
VSS5
VSS3
VSS4
VSS7
VSS6
VSSA0
VSSA1
VSSQ0
VSSQ1
VSSQ2
VSSQ3
VSSQ5
VSSQ6
VSSQ4
VSSQ7
VSSQ8
VSSQ9
VSSQ10
VSSQ11
VSSQ12
VSSQ13
VSSQ14
VSSQ16
VSSQ15
VSSQ17
VSSQ18
VSSQ19VDDQ19
VDDQ20
VDDQ21
VREF1
VREF0
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
VDDQ18
VDDQ16
VDDQ17
VDDQ9
VDDA1
VDDQ0
VDDQ1
VDDQ2
VDDQ5
VDDQ3
VDDQ4
VDDQ6
VDDQ7
VDDQ8
VDD0
VDD1
VDD2
VDD5
VDD3
VDD4
VDD6
VDD7
VDDA0
(2 OF 2)
IN
IN
IN
IN
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
DQ1
DQ0
DQ2
DQ3
DQ5
DQ6
DQ4
DQ8
DQ7
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ24
DQ23
DQ22
DQ25
DQ26
DQ27
DQ29
DQ28
DQ30
DQ31
RDQS3
RDQS2
RDQS1
RDQS0
SEN
RESET
MF
ZQ
RAS*
CAS*
WE*
CS*
CK*
A9
A6
A7
A3
A4
A2
A0
A1
CK
WDQS2
WDQS1
WDQS0
WDQS3
BA0
BA2
BA1
RFU1
RFU2
DM3
DM2
DM1
DM0
A5
A11
A8/AP
A10
CKE
MFHIGH
MFHIGH
MFHIGH
(1 OF 2)
VSS0
VSS1
VSS2
VSS5
VSS3
VSS4
VSS7
VSS6
VSSA0
VSSA1
VSSQ0
VSSQ1
VSSQ2
VSSQ3
VSSQ5
VSSQ6
VSSQ4
VSSQ7
VSSQ8
VSSQ9
VSSQ10
VSSQ11
VSSQ12
VSSQ13
VSSQ14
VSSQ16
VSSQ15
VSSQ17
VSSQ18
VSSQ19VDDQ19
VDDQ20
VDDQ21
VREF1
VREF0
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
VDDQ18
VDDQ16
VDDQ17
VDDQ9
VDDA1
VDDQ0
VDDQ1
VDDQ2
VDDQ5
VDDQ3
VDDQ4
VDDQ6
VDDQ7
VDDQ8
VDD0
VDD1
VDD2
VDD5
VDD3
VDD4
VDD6
VDD7
VDDA0
(2 OF 2)
IN
IN
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IN
IN
IO
IO
IN
IN
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
Connect to designated pin, then GND
DQA0-7 or DQA8-15. Bits can be swapped
how these bits are mapped for GPU to support
GDDR3 vendor/device identification scheme.
(NONE)
(NONE)
- =PP1V8_S0_FB_VDD
- =PP1V8_S0_FB_VDDQ
U8900.J12
U8900.J1
NC
NC NC
NC
Connect to designated pin, then GND
U8900.J1
U8900.J12
within byte-lane, but software must know
NOTE: U8900 DQ0-7 MUST connect to GPU
Page Notes
Power aliases required by this page:
Signal aliases required by this page:
BOM options provided by this page:
1/16W
1%
402
MF-LF
2.37K
R8930
1
2
402
1/16W
1%
MF-LF
5.49K
R8931
1
2
16V
10%
402
X5R
0.1uF
C8903
1
2
0.1uF
16V
10%
402
X5R
C8902
1
2
16V
10%
402
X5R
0.1uF
C8904
1
2
16V
10%
402
X5R
0.1uF
C8901
1
2
16V
10%
402
X5R
0.1uF
C8922
1
2
X5R
16V
10%
402
0.1uF
C8923
1
2
16V
10%
402
X5R
0.1uF
C8924
1
2
16V
10%
402
X5R
0.1uF
C8925
1
2
0.1uF
16V
10%
402
X5R
C8926
1
2
16MX32-GDDR3-500MHZ
K4J52324QC-BC20
OMIT
CRITICAL
FBGA
U8900
K9
H11
K11
L9
K10
M9
K4
H2
K3
L4
K2
M4
G9
G4
H3
F9
J11
J10
H9
F4
E3
E10
N10
N3
B2
B3
C11
C10
E11
F10
F11
G10
M11
L10
N11
M10
C2
R11
R10
T11
T10
M2
L3
N2
M3
R2
R3
C3
T2
T3
E2
F3
F2
G3
B11
B10
A9
H10
D3
D10
P10
P3
V9
J2
J3
V4
D2
D11
P11
P2
H4
A4
OMIT
CRITICAL
16MX32-GDDR3-500MHZ
K4J52324QC-BC20
FBGA
U8900
A2
A11
F1
F12
M1
M12
V2
V11
K1
K12
A1
A12
J4
J9
N1
N4
N9
N12
R1
R4
R9
R12
C1
V1
V12
C4
C9
C12
E1
E4
E9
E12
H1
H12
A3
A10
G1
G12
L1
L12
V3
V10
J1
J12
B1
B4
L2
L11
P1
P4
P9
P12
T1
T4
T9
T12
B9
B12
D1
D4
D9
D12
G2
G11
100
1/16W
5%
402
MF-LF
R8949
1
2
1K
1/16W
MF-LF
402
5%
R8941
1
2
1/16W
1%
402
MF-LF
243
R8948
1
2
1/16W
1%
402
MF-LF
60.4
R8945
1
2
60.4
MF-LF
402
1%
1/16W
R8946
1
2
0.1uF
X5R
402
10%
16V
C8933
1
2
2.37K
MF-LF
402
1%
1/16W
R8932
1
2
1/16W
1%
402
MF-LF
5.49K
R8933
1
2
10%
0.1uF
X5R
402
16V
C8921
1
2
FERR-220-OHM
0402
L8910
1 2
FERR-220-OHM
0402
L8915
1 2
16V
10%
402
X5R
0.1uF
C8915
1
2
10%
16V
402
X5R
0.1uF
C8910
1
2
1%
121
MF-LF
402
1/16W
R8940
1
2
1%
121
MF-LF
402
1/16W
R8947
1
2
1/16W
402
MF-LF
121
1%
R8944
1
2
MF-LF
1%
121
402
1/16W
R8943
1
2
1/16W
402
MF-LF
121
1%
R8942
1
2
1K
1/16W
5%
402
MF-LF
R8991
1
2
1/16W
402
MF-LF
121
1%
R8990
1
2
1%
121
MF-LF
402
1/16W
R8992
1
2
10%
0.1uF
X5R
402
16V
C8971
1
2
0.1uF
X5R
402
10%
16V
C8972
1
2
243
MF-LF
402
1%
1/16W
R8998
1
2
100
MF-LF
402
5%
1/16W
R8999
1
2
CRITICAL
OMIT
16MX32-GDDR3-500MHZ
K4J52324QC-BC20
FBGA
U8950
K9
H11
K11
L9
K10
M9
K4
H2
K3
L4
K2
M4
G9
G4
H3
F9
J11
J10
H9
F4
E3
E10
N10
N3
B2
B3
C11
C10
E11
F10
F11
G10
M11
L10
N11
M10
C2
R11
R10
T11
T10
M2
L3
N2
M3
R2
R3
C3
T2
T3
E2
F3
F2
G3
B11
B10
A9
H10
D3
D10
P10
P3
V9
J2
J3
V4
D2
D11
P11
P2
H4
A4
1/16W
402
MF-LF
121
1%
R8993
1
2
60.4
MF-LF
402
1%
1/16W
R8995
1
2
1%
121
MF-LF
402
1/16W
R8994
1
2
1/16W
402
MF-LF
121
1%
R8997
1
2
1/16W
1%
402
MF-LF
60.4
R8996
1
2
5.49K
MF-LF
402
1%
1/16W
R8981
1
2
2.37K
MF-LF
402
1%
1/16W
R8980
1
2
5.49K
MF-LF
402
1%
1/16W
R8983
1
2
1/16W
1%
402
MF-LF
2.37K
R8982
1
2
0.1uF
X5R
402
10%
16V
C8973
1
2
0.1uF
X5R
402
10%
16V
C8981
1
2
0.1uF
X5R
402
10%
16V
C8974
1
2
0.1uF
X5R
402
10%
16V
C8975
1
2
16V
10%
402
X5R
0.1uF
C8983
1
2
CRITICAL
OMIT
16MX32-GDDR3-500MHZ
K4J52324QC-BC20
FBGA
U8950
A2
A11
F1
F12
M1
M12
V2
V11
K1
K12
A1
A12
J4
J9
N1
N4
N9
N12
R1
R4
R9
R12
C1
V1
V12
C4
C9
C12
E1
E4
E9
E12
H1
H12
A3
A10
G1
G12
L1
L12
V3
V10
J1
J12
B1
B4
L2
L11
P1
P4
P9
P12
T1
T4
T9
T12
B9
B12
D1
D4
D9
D12
G2
G11
0.1uF
X5R
402
10%
16V
C8976
1
2
0402
FERR-220-OHM
L8965
1 2
0402
FERR-220-OHM
L8960
1 2
X5R
0.1uF
402
10%
16V
C8951
1
2
402
0.1uF
X5R
10%
16V
C8952
1
2
0.1uF
X5R
402
10%
16V
C8960
1
2
0.1uF
X5R
402
10%
16V
C8953
1
2
0.1uF
X5R
402
10%
16V
C8965
1
2
0.1uF
X5R
402
10%
16V
C8954
1
2
22UF
20%
805
CERM
6.3V
C8900
1
2
CERM
22UF
805
6.3V
20%
C8920
1
2
20%
6.3V
CERM
805
22UF
C8950
1
2
805
20%
6.3V
CERM
22UF
C8970
1
2
16V
10%
402
X5R
0.1uF
C8931
1
2
75 87
06004051-7164
GDDR3 Frame Buffer A
SYNC_MASTER=(MASTER)
SYNC_DATE=(MASTER)
FB_A_RDQS<7>
FB_A_RDQS<6>
FB_A_RAS_L<0>
FB_A_MA<0>
FB_A_MA<2>
FB_A_MA<3>
PP1V8_D3C
PP1V8_S0_FB_A0_VDDA0
MIN_LINE_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=1.8V
PP1V8_S0_FB_A0_VDDA1
MIN_LINE_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=1.8V
PP1V8_D3C
PP1V8_S0_FB_A1_VDDA1
MIN_LINE_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=1.8V
PP1V8_S0_FB_A1_VDDA0
MIN_LINE_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=1.8V
MIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.25 mm
FB_A1_VREF1
FB_A_DQ<46>
FB_A_DQ<43>
FB_A_DQ<42>
FB_A_DQ<41>
FB_A_DQ<40>
FB_A_DQ<38>
FB_A_DQ<37>
FB_A_DQ<36>
FB_A_DQ<33>
FB_A_DQ<34>
FB_A_MA<5>
FB_A_MA<4>
FB_A_CKE<0>
FB_A_CAS_L<0>
FB_DRAM_RST
FB_A_RDQS<0>
FB_A0_SEN
FB_A_RDQS<1>
FB_A_RDQS<2>
FB_A_RDQS<3>
FB_A_CLK_P<0>
FB_A_DQM_L<1>
FB_A_BA<2> FB_A_BA<2>
FB_A_RAS_L<1>
PP1V8_D3C
MIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.25 mm
FB_A0_VREF1
FB_A_WDQS<1>
FB_A_WDQS<2>
FB_A_MA<11>
FB_A_MA<6>
FB_A_MA<7>
FB_A_DQ<1>
FB_A_DQ<0>
FB_A_DQ<2>
FB_A_DQ<3>
FB_A_DQ<5>
FB_A_DQ<6>
FB_A_DQ<4>
FB_A_DQ<8>
FB_A_DQ<7>
FB_A_DQ<9>
FB_A_DQ<10>
FB_A_DQ<11>
FB_A_DQ<15>
FB_A_DQ<14>
FB_A_DQ<12>
FB_A_DQ<13>
FB_A_DQ<19>
FB_A_DQ<16>
FB_A_DQ<18>
FB_A_DQ<17>
FB_A_DQ<23>
FB_A_DQ<21>
FB_A_DQ<24>
FB_A_DQ<22>
FB_A_DQ<20>
FB_A_DQ<25>
FB_A_DQ<26>
FB_A_DQ<27>
FB_A_DQ<30>
FB_A_DQ<29>
FB_A_DQ<28>
FB_A_DQ<31>
FB_A0_MF
FB_A0_ZQ
FB_A_WE_L<0>
FB_A_CS_L<0>
FB_A_CLK_N<0>
FB_A_MA<9>
FB_A_MA<1>
FB_A_WDQS<0>
FB_A_WDQS<3>
FB_A_BA<0>
FB_A_BA<1>
FB_A_DQM_L<3>
FB_A_DQM_L<2>
FB_A_DQM_L<0>
FB_A_MA<8>
FB_A_MA<10>
FB_A_DQ<32>
FB_A_DQ<35>
FB_A_DQ<39>
FB_A_DQ<44>
FB_A_DQ<47>
FB_A_DQ<45>
FB_A_DQ<48>
FB_A_DQ<49>
FB_A_DQ<50>
FB_A_DQ<51>
FB_A_DQ<52>
FB_A_DQ<55>
FB_A_DQ<60>
FB_A_DQ<53>
FB_A_DQ<54>
FB_A_DQ<59>
FB_A_DQ<61>
FB_A_DQ<57>
FB_A_DQ<56>
FB_A_DQ<62>
FB_A_DQ<63>
FB_A_DQ<58>
FB_A_RDQS<5>
FB_A_RDQS<4>
FB_A1_SEN
FB_DRAM_RST
FB_A1_MF
FB_A1_ZQ
FB_A_CAS_L<1>
FB_A_WE_L<1>
FB_A_CS_L<1>
FB_A_CLK_N<1>
FB_A_MA<9>
FB_A_MA<6>
FB_A_MA<7>
FB_A_MA<3>
FB_A_MA<4>
FB_A_MA<2>
FB_A_MA<0>
FB_A_MA<1>
FB_A_CLK_P<1>
FB_A_WDQS<6>
FB_A_WDQS<5>
FB_A_WDQS<4>
FB_A_WDQS<7>
FB_A_BA<0>
FB_A_BA<1>
FB_A_DQM_L<7>
FB_A_DQM_L<6>
FB_A_DQM_L<5>
FB_A_DQM_L<4>
FB_A_MA<5>
FB_A_MA<11>
FB_A_MA<8>
FB_A_MA<10>
FB_A_CKE<1>
MIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.25 mm
FB_A1_VREF0
MIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.25 mm
FB_A0_VREF0
PP1V8_D3C
82D7
82D7
82D7 82D7
76D8
76D8
76D8 76D8
76D5
76D5
76D5 76D5
75D8
75D8
75D8 75D8
75D5
75D5
75D5 75D5
73B8
73B8
73B8 73B8
73B5
73B5
73B5 73B5
73A8
73A8
73A8 73A8
73A5
73A5
73A5 73A5
72B8
72B8
72B8 72B8
67B8 67B8
76A8
67B8
76A8
67B8
67B6 67B6
76A5
67B6
76A5
67B6
75B5
75B5
75B5
64A4 64A4
75B5
75B5
75A5
75A5 75A8
64A4
75B5
75B5
75B5
75B5
75B5
75A5
75A5
75B5
75B5
75A8
75B8
75B8
75B8
75B8
75B8
75B8
75B8
75B8
75A8
75A8
75B8
75B8
75B8
75B8
64A4
73C5
73C5
73B5
73D5
73D5
73D5
5D4 5D4
73B7
73C7
73C7
73C7
73C7
73C7
73C7
73C7
73C7
73C7
73D5
73D5
73B5
73B5
73A1
73C5
73C5
73C5
73C5
73B5
73C5
73D5 73D5
73B5
5D4
73C5
73C5
73D5
73D5
73D5
73D7
73D7
73D7
73D7
73D7
73D7
73D7
73D7
73D7
73D7
73D7
73D7
73D7
73D7
73D7
73D7
73C7
73D7
73C7
73D7
73C7
73C7
73C7
73C7
73C7
73C7
73C7
73C7
73C7
73C7
73C7
73C7
73B5
73B5
73B5
73D5
73D5
73C5
73C5
73D5
73D5
73C5
73C5
73D5
73D5
73D5
73C7
73C7
73C7
73B7
73B7
73B7
73B7
73B7
73B7
73B7
73B7
73B7
73B7
73B7
73B7
73B7
73B7
73B7
73B7
73B7
73B7
73B7
73C5
73C5
73A1
73B5
73B5
73B5
73B5
73D5
73D5
73D5
73D5
73D5
73D5
73D5
73D5
73B5
73C5
73C5
73C5
73C5
73D5
73D5
73C5
73C5
73C5
73C5
73D5
73D5
73D5
73D5
73B5
5D4
DQ1
DQ0
DQ2
DQ3
DQ5
DQ6
DQ4
DQ8
DQ7
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ24
DQ23
DQ22
DQ25
DQ26
DQ27
DQ29
DQ28
DQ30
DQ31
RDQS3
RDQS2
RDQS1
RDQS0
SEN
RESET
MF
ZQ
RAS*
CAS*
WE*
CS*
CK*
A9
A6
A7
A3
A4
A2
A0
A1
CK
WDQS2
WDQS1
WDQS0
WDQS3
BA0
BA2
BA1
RFU1
RFU2
DM3
DM2
DM1
DM0
A5
A11
A8/AP
A10
CKE
MFHIGH
MFHIGH
MFHIGH
(1 OF 2)
VSS0
VSS1
VSS2
VSS5
VSS3
VSS4
VSS7
VSS6
VSSA0
VSSA1
VSSQ0
VSSQ1
VSSQ2
VSSQ3
VSSQ5
VSSQ6
VSSQ4
VSSQ7
VSSQ8
VSSQ9
VSSQ10
VSSQ11
VSSQ12
VSSQ13
VSSQ14
VSSQ16
VSSQ15
VSSQ17
VSSQ18
VSSQ19VDDQ19
VDDQ20
VDDQ21
VREF1
VREF0
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
VDDQ18
VDDQ16
VDDQ17
VDDQ9
VDDA1
VDDQ0
VDDQ1
VDDQ2
VDDQ5
VDDQ3
VDDQ4
VDDQ6
VDDQ7
VDDQ8
VDD0
VDD1
VDD2
VDD5
VDD3
VDD4
VDD6
VDD7
VDDA0
(2 OF 2)
IN
IN
IN
IN
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
DQ1
DQ0
DQ2
DQ3
DQ5
DQ6
DQ4
DQ8
DQ7
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ24
DQ23
DQ22
DQ25
DQ26
DQ27
DQ29
DQ28
DQ30
DQ31
RDQS3
RDQS2
RDQS1
RDQS0
SEN
RESET
MF
ZQ
RAS*
CAS*
WE*
CS*
CK*
A9
A6
A7
A3
A4
A2
A0
A1
CK
WDQS2
WDQS1
WDQS0
WDQS3
BA0
BA2
BA1
RFU1
RFU2
DM3
DM2
DM1
DM0
A5
A11
A8/AP
A10
CKE
MFHIGH
MFHIGH
MFHIGH
(1 OF 2)
VSS0
VSS1
VSS2
VSS5
VSS3
VSS4
VSS7
VSS6
VSSA0
VSSA1
VSSQ0
VSSQ1
VSSQ2
VSSQ3
VSSQ5
VSSQ6
VSSQ4
VSSQ7
VSSQ8
VSSQ9
VSSQ10
VSSQ11
VSSQ12
VSSQ13
VSSQ14
VSSQ16
VSSQ15
VSSQ17
VSSQ18
VSSQ19VDDQ19
VDDQ20
VDDQ21
VREF1
VREF0
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
VDDQ18
VDDQ16
VDDQ17
VDDQ9
VDDA1
VDDQ0
VDDQ1
VDDQ2
VDDQ5
VDDQ3
VDDQ4
VDDQ6
VDDQ7
VDDQ8
VDD0
VDD1
VDD2
VDD5
VDD3
VDD4
VDD6
VDD7
VDDA0
(2 OF 2)
IN
IN
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IN
IN
IO
IO
IN
IN
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
Page Notes
Power aliases required by this page:
BOM options provided by this page:
Signal aliases required by this page:
(NONE)
(NONE)
- =PP1V8_S0_FB_VDD
- =PP1V8_S0_FB_VDDQ
U9000.J12
U9000.J1
NC
NC NC
NC
U9000.J1
U9000.J12
Connect to designated pin, then GNDConnect to designated pin, then GND
1/16W
1%
402
MF-LF
2.37K
R9030
1
2
1/16W
1%
402
MF-LF
5.49K
R9031
1
2
16V
10%
X5R
0.1uF
402
C9003
1
2
16V
10%
402
X5R
0.1uF
C9002
1
2
16V
10%
402
X5R
0.1uF
C9004
1
2
402
16V
10%
X5R
0.1uF
C9001
1
2
16V
10%
402
X5R
0.1uF
C9022
1
2
16V
10%
402
X5R
0.1uF
C9023
1
2
16V
10%
402
X5R
0.1uF
C9024
1
2
16V
10%
402
X5R
0.1uF
C9025
1
2
10%
X5R
0.1uF
402
16V
C9026
1
2
16MX32-GDDR3-500MHZ
K4J52324QC-BC20
FBGA
CRITICAL
OMIT
U9000
K9
H11
K11
L9
K10
M9
K4
H2
K3
L4
K2
M4
G9
G4
H3
F9
J11
J10
H9
F4
E3
E10
N10
N3
B2
B3
C11
C10
E11
F10
F11
G10
M11
L10
N11
M10
C2
R11
R10
T11
T10
M2
L3
N2
M3
R2
R3
C3
T2
T3
E2
F3
F2
G3
B11
B10
A9
H10
D3
D10
P10
P3
V9
J2
J3
V4
D2
D11
P11
P2
H4
A4
16MX32-GDDR3-500MHZ
K4J52324QC-BC20
CRITICAL
OMIT
FBGA
U9000
A2
A11
F1
F12
M1
M12
V2
V11
K1
K12
A1
A12
J4
J9
N1
N4
N9
N12
R1
R4
R9
R12
C1
V1
V12
C4
C9
C12
E1
E4
E9
E12
H1
H12
A3
A10
G1
G12
L1
L12
V3
V10
J1
J12
B1
B4
L2
L11
P1
P4
P9
P12
T1
T4
T9
T12
B9
B12
D1
D4
D9
D12
G2
G11
1/16W
5%
402
MF-LF
100
R9049
1
2
MF-LF
402
5%
1/16W
1K
R9041
1
2
1/16W
1%
402
MF-LF
243
R9048
1
2
1/16W
1%
402
MF-LF
60.4
R9045
1
2
60.4
MF-LF
402
1%
1/16W
R9046
1
2
0.1uF
X5R
402
10%
16V
C9033
1
2
MF-LF
402
1%
1/16W
2.37K
R9032
1
2
1/16W
1%
402
MF-LF
5.49K
R9033
1
2
16V
10%
X5R
0.1uF
402
C9021
1
2
FERR-220-OHM
0402
L9010
1 2
FERR-220-OHM
0402
L9015
1 2
16V
10%
402
X5R
0.1uF
C9015
1
2
16V
10%
402
X5R
0.1uF
C9010
1
2
1%
121
MF-LF
402
1/16W
R9040
1
2
1%
121
MF-LF
402
1/16W
R9047
1
2
1/16W
402
MF-LF
121
1%
R9044
1
2
1%
121
MF-LF
402
1/16W
R9043
1
2
1/16W
402
MF-LF
121
1%
R9042
1
2
1/16W
5%
402
MF-LF
1K
R9091
1
2
1/16W
402
MF-LF
121
1%
R9090
1
2
MF-LF
121
1%
402
1/16W
R9092
1
2
X5R
402
10%
16V
0.1uF
C9071
1
2
X5R
402
10%
16V
0.1uF
C9072
1
2
1/16W
402
MF-LF
243
1%
R9098
1
2
1/16W
402
MF-LF
5%
100
R9099
1
2
16MX32-GDDR3-500MHZ
K4J52324QC-BC20
OMIT
CRITICAL
FBGA
U9050
K9
H11
K11
L9
K10
M9
K4
H2
K3
L4
K2
M4
G9
G4
H3
F9
J11
J10
H9
F4
E3
E10
N10
N3
B2
B3
C11
C10
E11
F10
F11
G10
M11
L10
N11
M10
C2
R11
R10
T11
T10
M2
L3
N2
M3
R2
R3
C3
T2
T3
E2
F3
F2
G3
B11
B10
A9
H10
D3
D10
P10
P3
V9
J2
J3
V4
D2
D11
P11
P2
H4
A4
1%
MF-LF
402
1/16W
121
R9093
1
2
MF-LF
402
1%
1/16W
60.4
R9095
1
2
121
MF-LF
1/16W
1%
402
R9094
1
2
402
1%
1/16W
MF-LF
121
R9097
1
2
1/16W
1%
402
MF-LF
60.4
R9096
1
2
402
MF-LF
5.49K
1%
1/16W
R9081
1
2
402
MF-LF
2.37K
1%
1/16W
R9080
1
2
MF-LF
5.49K
402
1/16W
1%
R9083
1
2
MF-LF
402
1/16W
1%
2.37K
R9082
1
2
10%
402
X5R
16V
0.1uF
C9073
1
2
0.1uF
X5R
402
10%
16V
C9081
1
2
16V
10%
402
X5R
0.1uF
C9074
1
2
X5R
402
10%
16V
0.1uF
C9075
1
2
402
10%
16V
X5R
0.1uF
C9083
1
2
K4J52324QC-BC20
OMIT
CRITICAL
FBGA
16MX32-GDDR3-500MHZ
U9050
A2
A11
F1
F12
M1
M12
V2
V11
K1
K12
A1
A12
J4
J9
N1
N4
N9
N12
R1
R4
R9
R12
C1
V1
V12
C4
C9
C12
E1
E4
E9
E12
H1
H12
A3
A10
G1
G12
L1
L12
V3
V10
J1
J12
B1
B4
L2
L11
P1
P4
P9
P12
T1
T4
T9
T12
B9
B12
D1
D4
D9
D12
G2
G11
X5R
402
10%
16V
0.1uF
C9076
1
2
0402
FERR-220-OHM
L9065
1 2
0402
FERR-220-OHM
L9060
1 2
0.1uF
X5R
402
10%
16V
C9051
1
2
0.1uF
X5R
402
10%
16V
C9052
1
2
16V
10%
402
X5R
0.1uF
C9060
1
2
16V
10%
402
X5R
0.1uF
C9053
1
2
16V
10%
402
X5R
0.1uF
C9065
1
2
0.1uF
X5R
402
10%
16V
C9054
1
2
22UF
805
CERM
6.3V
20%
C9000
1
2
22UF
805
CERM
6.3V
20%
C9020
1
2
22UF
805
CERM
6.3V
20%
C9050
1
2
805
CERM
6.3V
20%
22UF
C9070
1
2
16V
10%
402
0.1uF
X5R
C9031
1
2
76 87
06004051-7164
GDDR3 Frame Buffer B
SYNC_MASTER=(MASTER)
SYNC_DATE=(MASTER)
FB_B_MA<4>
FB_B_CS_L<1>
FB_B_MA<9>
FB_B_DQ<2>
FB_B_DQ<7>
FB_B_DQ<24>
FB_B_DQ<13>
FB_B_DQ<14>
FB_B_DQ<12>
FB_B_DQ<15>
FB_B_DQM_L<3>
FB_B_WDQS<1>
FB_B_RDQS<0>
FB_B_RDQS<3>
FB_B_RDQS<2>
FB_DRAM_RST
FB_B0_ZQ
FB_B0_SEN
FB_B_DQ<23>
FB_B_CLK_N<1>
FB_B_CAS_L<1>
FB_B_WE_L<1>
FB_B_RAS_L<1>
FB_B1_ZQ
FB_B_DQ<61>
FB_B_DQ<46>
FB_B_CLK_P<1>
FB_B_MA<1>
FB_B_MA<2>
FB_B_MA<3>
FB_B_CKE<1>
FB_B_DQ<58>
FB_B_DQ<59>
PP1V8_D3C
FB_B_MA<5>
FB_B_MA<7>
FB_B_BA<0>
FB_B_BA<1>
FB_B_CKE<0>
FB_B_DQ<9>
FB_B_DQ<11>
FB_B_DQ<8>
FB_B_DQ<18>
FB_B_DQ<10>
FB_B_DQ<17>
FB_B_DQ<19>
FB_B_DQ<16>
FB_B_DQ<20>
FB_B_DQ<22>
FB_B_DQ<21>
FB_B_DQ<29>
FB_B_DQ<30>
FB_B_DQ<28>
FB_B_DQ<31>
FB_B_DQ<27>
FB_B_DQ<1>
FB_B_DQ<25>
FB_B_DQ<26>
FB_B_DQ<6>
FB_B_DQ<0>
FB_B_DQ<5>
FB_B_DQ<3>
FB_B_DQ<4>
FB_B_RDQS<1>
FB_B0_MF
FB_B_CAS_L<0>
FB_B_WE_L<0>
FB_B_CS_L<0>
FB_B_CLK_N<0>
FB_B_MA<9>
FB_B_MA<6>
FB_B_MA<7>
FB_B_MA<0>
FB_B_MA<1>
FB_B_WDQS<3>
FB_B_WDQS<2>
FB_B_WDQS<0>
FB_B_DQM_L<0>
FB_B_DQM_L<2>
FB_B_DQM_L<1>
FB_B_MA<5>
FB_B_MA<11>
FB_B_MA<8>
FB_B_MA<10>
FB_B_DQ<53>
FB_B_DQ<54>
FB_B_DQ<52>
FB_B_DQ<55>
FB_B_DQ<48>
FB_B_DQ<49>
FB_B_DQ<50>
FB_B_DQ<44>
FB_B_DQ<51>
FB_B_DQ<47>
FB_B_DQ<45>
FB_B_DQ<43>
FB_B_DQ<41>
FB_B_DQ<42>
FB_B_DQ<40>
FB_B_DQ<37>
FB_B_DQ<32>
FB_B_DQ<39>
FB_B_DQ<34>
FB_B_DQ<36>
FB_B_DQ<35>
FB_B_DQ<63>
FB_B_DQ<33>
FB_B_DQ<62>
FB_B_DQ<60>
FB_B_DQ<56>
FB_B_DQ<57>
FB_B_RDQS<7>
FB_B_RDQS<4>
FB_B_RDQS<6>
FB_B1_SEN
FB_DRAM_RST
FB_B1_MF
FB_B_MA<6>
FB_B_WDQS<4>
FB_B_WDQS<5>
FB_B_WDQS<6>
FB_B_WDQS<7>
FB_B_BA<0>
FB_B_BA<1>
FB_B_DQM_L<7>
FB_B_DQM_L<4>
FB_B_DQM_L<5>
FB_B_DQM_L<6>
FB_B_MA<11>
FB_B_MA<8>
FB_B1_VREF1
MIN_LINE_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.25 mm
FB_B1_VREF0
MIN_LINE_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.25 mm
FB_B0_VREF1
MIN_LINE_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.25 mm
FB_B0_VREF0
MIN_LINE_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.25 mm
FB_B_RAS_L<0>
FB_B_BA<2> FB_B_BA<2>
FB_B_RDQS<5>
FB_B_MA<10>
FB_B_DQ<38>
PP1V8_D3C
FB_B_MA<4>
FB_B_MA<3>
FB_B_MA<2>
FB_B_CLK_P<0>
VOLTAGE=1.8V
MIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.25 mm
PP1V8_S0_FB_B1_VDDA1
VOLTAGE=1.8V
MIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.25 mm
PP1V8_S0_FB_B1_VDDA0
PP1V8_D3C
VOLTAGE=1.8V
MIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.25 mm
PP1V8_S0_FB_B0_VDDA0
VOLTAGE=1.8V
MIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.25 mm
PP1V8_S0_FB_B0_VDDA1
PP1V8_D3C
FB_B_MA<0>
82D7 82D7
82D7
82D7
76D8 76D8
76D8
76D8
76D5 76D5
76D5
76D5
75D8 75D8
75D8
75D8
75D5 75D5
75D5
75D5
73B8 73B8
73B8
73B8
73B5 73B5
73B5
73B5
73A8 73A8
73A8
73A8
73A5 73A5
73A5
73A5
72B8 72B8
72B8
72B8
76A5
67B8
76A8
67B8
67B8 67B8
75A8
67B6
75A8
67B6
67B6 67B6
76B8
76B8
75A5
76B8
76B8
76B8
64A4
76B8
76B8
76A5
76A5
76B5
76B5
76B5
76B5
76B5
76B5
76B5
76B5
76B5
75A5
76B8
76A8
76A8
76B8
76B8
76A5 76A8
76B8
64A4
76B5
76B5
76B5
64A4 64A4
76B8
73D1
73B1
73D1
73D3
73D3
73C3
73D3
73D3
73D3
73D3
73C1
73C1
73C1
73C1
73C1
73A1
73C3
73B1
73B1
73B1
73B1
73B3
73B3
73B1
73D1
73D1
73D1
73B1
73B3
73B3
5D4
73D1
73D1
73D1
73D1
73B1
73D3
73D3
73D3
73C3
73D3
73D3
73C3
73D3
73C3
73C3
73C3
73C3
73C3
73C3
73C3
73C3
73D3
73C3
73C3
73D3
73D3
73D3
73D3
73D3
73C1
73B1
73B1
73B1
73B1
73D1
73D1
73D1
73D1
73D1
73C1
73C1
73C1
73D1
73C1
73C1
73D1
73D1
73D1
73D1
73B3
73B3
73B3
73B3
73B3
73B3
73B3
73B3
73B3
73B3
73B3
73C3
73C3
73C3
73C3
73C3
73C3
73C3
73C3
73C3
73C3
73B3
73C3
73B3
73B3
73B3
73B3
73C1
73C1
73C1
73A1
73D1
73C1
73C1
73C1
73C1
73D1
73D1
73C1
73C1
73C1
73C1
73D1
73D1
73B1
73D1 73D1
73C1
73D1
73C3
5D4
73D1
73D1
73D1
73B1
5D4 5D4
73D1
GPIO_0
GPIO_1
TESTEN
GPIO_2
GPIO_27
PLLTEST
XTALOUT
XTALIN
MPVSS
MPVDD
PVSS
PVDD
GPIO_16
GPIO_17
GPIO_15
GPIO_14
GPIO_13
GPIO_12
GPIO_11
GPIO_10
GPIO_9
GPIO_8
GPIO_7_BLON
GPIO_6
GPIO_5
GPIO_4
GPIO_3
VREFG
GPIO_33
GPIO_31
GPIO_32
GPIO_25
GPIO_26
GPIO_24
GPIO_21
GPIO_20
GPIO_19
DMINUS
DPLUS
ROMCS*
GPIO_34
GPIO_29
GPIO_30
NC_DVOVMODE_0
NC_DVOVMODE_1
DVPCLK
DVPCNTL_0
DVPCNTL_1
DVPCNTL_2
DVPDATA_2
DVPDATA_1
DVPDATA_0
DVPDATA_4
DVPDATA_3
DVPDATA_5
DVPDATA_7
DVPDATA_6
DVPDATA_9
DVPDATA_8
DVPDATA_10
DVPDATA_11
DVPDATA_13
DVPDATA_12
DVPDATA_15
DVPDATA_14
DVPDATA_16
DVPDATA_18
DVPDATA_17
DVPDATA_19
DVPDATA_21
DVPDATA_20
DVPDATA_23
DVPDATA_22
GENERICA
GENERICB
GENERICC
GENERICD
DIGON
VARY_BL
NC0
GPIO_18
VDDPLL
GPIO_28
GPIO_22
GPIO_23
GENERAL PURPOSE I/O
(1.2V)
(2.5V)
ROM
TEST
PLL & XTAL
VIP HOST / EXTERNAL TMDS
PANEL
CONTROL
VDDR3
(3.3V)
(2.5V)
VDD25
VDDR5
(1.8V/3.3V)
(1.8V/3.3V)
VDDR4
DIODE
THERMAL
(2.5V)
(6 OF 7)
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
20mA
70mA total for VDD25
Power aliases required by this page:
- =I2C_GPU_TMDS_SCL - I2C clock line for
Page Notes
(PP1V0R1V2_S0_GPU_MPVDD)
NC
NC
NC
NC
Signal aliases required by this page:
(PP2V5_S0_GPU_PVDD_F)
- =I2C_GPU_TMDS_SDA - I2C data line for
- =PP3V3_GPU_GPIOS
- =PP1V8_GPU_LVDS_PLL
external TMDS transmitters
(NONE)
- =PP2V5_PVDD
external TMDS transmitters
20mA
Typically <50mA
Typically <50mA
Typically <50mA
BOM options provided by this page:
100mA
10%
16V
X5R
0.1uF
402
C9112
1
2
6.3V
CERM
1uF
402
10%
C9111
1
2
402
1uF
6.3V
CERM
10%
C9116
1
2
6.3V
CERM
1uF
10%
402
C9117
1
2
10%
X5R
402
0.1uF
16V
C9137
1
2
6.3V
CERM
402
10%
1uF
C9136
1
2
FERR-220-OHM
0402
L9135
1 2
6.3V
CERM
1uF
402
10%
C9141
1
2
FERR-220-OHM
0402
L9140
1 2
X5R
16V
0.1uF
10%
402
C9142
1
2
5%
1/16W
MF-LF
402
1K
R9195
1
2
1%
499
1/16W
MF-LF
402
R9191
1
2
1%
499
402
MF-LF
1/16W
R9190
1
2
22UF
805
CERM
6.3V
20%
C9100
1
2
20%
6.3V
CERM
805
22UF
C9110
1
2
22UF
805
CERM
6.3V
20%
C9115
1
2
20%
6.3V
CERM
805
22UF
C9120
1
2
22UF
805
CERM
6.3V
20%
C9125
1
2
10%
402
1uF
6.3V
CERM
C9132
1
2
22UF
805
CERM
6.3V
20%
C9130
1
2
805
CERM
6.3V
20%
22UF
C9135
1
2
22UF
805
CERM
6.3V
20%
C9140
1
2
10%
16V
X5R
402
0.1uF
C9191
1
2
OMIT
BGA
M56P
U8400
AE11
AH12
AG12
AG1
AF2
AF1
AF3
AG2
AG3
AL3
AM3
AE6
AF4
AF5
AG4
AJ3
AH4
AJ4
AG5
AH2
AH5
AF6
AE7
AG6
AH3
AJ2
AJ1
AK2
AK1
AK3
AL2
AK22
AF23
AE23
AD23
AD4
AD2
AC4
AB3
AB4
AB5
AD5
AB8
AA8
AB7
AE13
AF13
AD1
AF9
AG7
AE10
AE9
AF7
AF8
AH6
AF10
AG10
AH9
AD3
AJ8
AH8
AG9
AH7
AG8
AC1
AC2
AC3
AB2
AC6
AC5
A6
A5
AB6
AK4
AL4
AG14
AJ14
AH14
AC7
AG22
AD12
K22
L10
AA10
AC13
AC16
AC18
AC15
AA9
AB9
AB10
AC19
AC20
AD18
AD19
AD20
AJ5
AK5
AL5
AM5
AE2
AE3
AE4
AE5
AC8
AL26
AM26
0.1uF
402
X5R
16V
10%
C9127
1
2
10%
402
1uF
CERM
6.3V
C9126
1
2
10%
16V
X5R
0.1uF
402
C9122
1
2
6.3V
CERM
1uF
10%
402
C9121
1
2
FERR-220-OHM
0402
L9120
1 2
FERR-220-OHM
0402
L9125
1 2
200-OHM-EMI
0402
L9130
1 2
10%
402
CERM
6.3V
1uF
C9131
1
2
10%
402
1uF
CERM
6.3V
C9101
1
2
6.3V
1uF
10%
402
CERM
C9102
1
2
6.3V
CERM
1uF
402
10%
C9103
1
2
77 87
06004051-7164
ATI M56 GPIO/DVO/Misc
SYNC_MASTER=(MASTER)
SYNC_DATE=(MASTER)
PP3V3_D3C
PP2V5_D3C
PP2V5_D3C
NC_GPU_GPIO_30
NC_GPU_GPIO_31
GPU_GPIO_8
NC_ATI_DVPDATA<0>
TP_ATI_DVPDATA<19>
NC_ATI_DVPDATA<2>
ATI_TDIODE_P
GPU_GPIO_0
GPU_GPIO_1
GPU_GPIO_2
GPU_MEMID
NC_GPU_XTALOUT
GPU_CLK27M
GPU_CLK27MSS_IN
NC_GPU_GPIO_17
GPU_VCORE_LOW
NC_GPU_GPIO_14
GPU_GPIO_13
GPU_GPIO_12
GPU_GPIO_11
TP_GPU_GPIO_10
GPU_GPIO_9
GPU_BLON
GPU_GPIO_6
GPU_GPIO_5
GPU_GPIO_3
NC_GPU_GPIO_33
NC_GPU_GPIO_32
NC_GPU_GPIO_25
NC_GPU_GPIO_26
NC_GPU_GPIO_21
NC_GPU_GPIO_20
NC_GPU_GPIO_19
ATI_TDIODE_N
NC_ATI_ROMCS_L
NC_GPU_GPIO_34
NC_GPU_GPIO_29
NC_ATI_DVPCLK
NC_ATI_DVPCNTL<0>
NC_ATI_DVPCNTL<1>
NC_ATI_DVPCNTL<2>
NC_ATI_DVPDATA<1>
NC_ATI_DVPDATA<4>
NC_ATI_DVPDATA<3>
NC_ATI_DVPDATA<5>
NC_ATI_DVPDATA<7>
NC_ATI_DVPDATA<6>
NC_ATI_DVPDATA<9>
NC_ATI_DVPDATA<8>
NC_ATI_DVPDATA<10>
NC_ATI_DVPDATA<11>
NC_ATI_DVPDATA<13>
NC_ATI_DVPDATA<12>
NC_ATI_DVPDATA<15>
NC_ATI_DVPDATA<14>
TP_ATI_DVPDATA<16>
TP_ATI_DVPDATA<18>
TP_ATI_DVPDATA<17>
TP_ATI_DVPDATA<21>
TP_ATI_DVPDATA<20>
TP_ATI_DVPDATA<23>
TP_ATI_DVPDATA<22>
NC_GPU_GENERICA
NC_GPU_GENERICB
NC_GPU_GENERICC
GPU_GENERICD
GPU_DIGON
GPU_VARY_BL
NC_GPU_GPIO_18
NC_GPU_GPIO_28
NC_GPU_GPIO_22
NC_GPU_GPIO_23
ATI_TESTEN
PP3V3_D3C
ATI_VREFG
GPU_MEM_256M
GPU_GPIO_4
MIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.25 mm
VOLTAGE=3.3V
PP1V8R3V3_S0_GPU_VDDR4_F
PP3V3_D3C
MIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.25 mm
VOLTAGE=3.3V
PP1V8R3V3_S0_GPU_VDDR5_F
PP3V3_D3C
MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.2 mm
VOLTAGE=1.2V
PP1V2_S0_GPU_VDDPLL
PP1V2_D3C
PP2V5_D3C
PPVCORE_D3C_GPU
MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.2 mm
VOLTAGE=1.2V
PPVCORE_S0_GPU_MPVDD
MIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.25 mm
VOLTAGE=2.5V
PP2V5_S0_GPU_PVDD_F
82D7
82D7
82D7
82D7
82A7
82A7
82A7
82A7
80D5
80D5
80D5
80D5
80B2
80B2
80B2
80B2
77D2
77D2
77D2
77C6
77C6
77C6
77B7
77B7
77B7
77B7
74D6
82D7
82D7
74D6
74D6
74D6
82D7
72D8
74B2
78C8
78C8
74B2
74B2
74B2
70C7
82D7
71C1
71C4
77C6
77C6
71C4
71C4
71C4
70A1
78C8
71B7
71B8
77A8
77A8
71B8
71B8
71B8
67D8
77C6
67A8
71A4
67A8
67A8
74C2
74C8
71A4
71A4
71A4
67D6
67A8
67A6
67A5
67A6
67A6
74C1
74C5
74C8
82A4
67A5
67A5
67A5
67C6
67A6
55C7
67A3
63C1
63C1
74B8
74B8
74B8
74C2
34B4
34B4
74C8
74C5
74C8
74C8
74C8
74B8
74B8
74B8
74B8
74B8
74B8
74B8
74C2
74B8
74B8
74B2
74C2
74C2
74C2
82B6
74B8
74B8
74B8
74B8
67A3
74B8
67A3
67A3
63B1
63C1
55A5
65C7
5D4
5D4
74B7
74B7
74C8
74B2
74B2
74B2
54B6
74D8
74C8
74C8
74B6
74C1
34B2
34B2
74C5
71B4
74C5
74C8
74C8
74C8
74C5
74C8
74C5
74C8
74C8
74C8
74B7
74B7
74B7
74B7
74B7
74B7
74B7
54B6
74C1
74B7
74B7
74B1
74B2
74B2
74B2
74B2
74B2
74B2
74B2
74B2
74B2
74B2
74B2
74B2
74B2
74B2
74B2
74B2
74B2
74B2
74B2
74B2
74B2
74B2
74B2
74B2
74C1
74C1
74C1
71A7
82A4
82A4
74B7
74B7
74B7
74B7
65C7
74B6 74C8
65C7
65C7
5D4
5D4
5B2
DDC3DATA
DDC3CLK
DDC2DATA
DDC2CLK
DDC1DATA
DDC1CLK
TXOUT_L3N
TXOUT_L3P
TXOUT_L2N
TXOUT_L2P
TXOUT_L1N
TXOUT_L1P
TXOUT_L0N
TXOUT_L0P
TXCLK_LP
TXCLK_LN
TXOUT_U3N
TXOUT_U2N
TXOUT_U3P
TXOUT_U2P
TXOUT_U1N
TXOUT_U1P
TXOUT_U0N
TXOUT_U0P
TXCLK_UN
TXCLK_UP
COMP
C
Y
V2SYNC
H2SYNC
B2
G2
R2
VSYNC
HSYNC
B
G
R
TX2M
TX2P
TX1M
TX0M
TX1P
TX0P
TXCM
HPD1
LPVSS
LPVDD
R2SET
VDD2DI
VSS2DI
A2VSSQ
NC_A2VDDQ
VSS1DI
RSET
AVSSQ
VDD1DI
TXCP
TPVSS
TPVDD
TX3P
TX3M
TX4P
TX4M
TX5P
TX5M
A2VSS
A2VDD
(2.5V)
AVSS
(2.5V)
AVDD
TXVSSR
IDENTIFICATION
(5 OF 7)
LVDDR
LVSSR
DAC (CRT)
DAC2 (TV/CRT2)
LVDS
MONITOR
TXVDDR
(2.5V)
(2.5V)
(2.5V)
(2.5V)
(2.5V)
(2.5V)
INTEGRATED TMDS
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IO
IO
IO
IO
IO
IO
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
Sum of peak currents on this page: 605mA
20mA peak
20mA peak
20mA peak
130mA peak
- =PP1V8R2V5_S0_GPU_LVDDR
- =PP2V5_S0_GPU
(NONE)
(NONE)
BOM options provided by this page:
NC
150mA peak
65mA peak
200mA peak
Comp B Pb
C R Pr
Y G Y
Composite/S-Video VGA Component
20mA peak
Signal aliases required by this page:
Power aliases required by this page:
Page Notes
BGA
M56P
OMIT
U8400
AL16
AM16
AL17
AM17
AK13
AL25
AM25
AJ24
AK25
AK23
AL24
AL15
AJ13
AH15
AH23
AH22
AG13
AH13
AF12
AE12
AM24
AM15
AF15
AF11
AJ23
AE19
AE18
AC21
AC22
AD21
AD22
AE20
AE21
AE22
AF19
AF20
AF17
AF18
AF21
AF22
AG17
AG19
AH17
AH19
AJ19
AK17
AL14
AK24
AK15
AK14
AL22
AM8
AL8
AK10
AL10
AL11
AM11
AL12
AM12
AK9
AJ9
AK11
AJ11
AK12
AJ12
AL18
AM18
AK21
AJ21
AL9
AM9
AK19
AL19
AL20
AM20
AL21
AM21
AK18
AJ18
AH18
AG18
AJ20
AK20
AH20
AG20
AG21
AH21
AJ6
AK6
AL6
AM6
AJ7
AK7
AK8
AL7
AM7
AG15
AM23
AJ16
AL23
AJ17
AJ22
AJ15
1/16W
1%
402
MF-LF
499
R9350
1
2
0.1uF
X5R
402
10%
16V
C9346
1
2
0.1uF
X5R
402
10%
16V
C9342
1
2
6.3V
402
CERM
1uF
10%
C9341
1
2
0402
FERR-220-OHM
L9300
1 2
1uF
CERM
10%
6.3V
402
C9301
1
2
1uF
CERM
402
10%
6.3V
C9306
1
2
0402
FERR-220-OHM
L9305
1 2
10%
402
X5R
0.1uF
16V
C9307
1
2
0402
FERR-220-OHM
L9330
1 2
6.3V
10%
402
CERM
1uF
C9331
1
2
X5R
402
10%
0.1uF
16V
C9322
1
2
1uF
402
10%
CERM
6.3V
C9321
1
2
0402
FERR-220-OHM
L9320
1 2
10%
402
X5R
0.1uF
16V
C9312
1
2
6.3V
10%
CERM
1uF
402
C9311
1
2
0402
FERR-220-OHM
L9310
1 2
16V
10%
X5R
0.1uF
402
C9317
1
2
402
CERM
6.3V
10%
1uF
C9316
1
2
16V
10%
402
X5R
0.1uF
C9327
1
2
6.3V
402
CERM
10%
1uF
C9326
1
2
0402
FERR-220-OHM
L9325
1 2
0402
FERR-220-OHM
L9315
1 2
0402
FERR-220-OHM
L9345
1 2
0.1uF
X5R
402
10%
16V
C9347
1
2
20%
6.3V
CERM
805
22UF
C9340
1
2
20%
6.3V
CERM
805
22UF
C9345
1
2
6.3V
10%
402
CERM
1uF
C9332
1
2
1uF
CERM
10%
402
6.3V
C9302
1
2
6.3V
CERM
805
22UF
20%
C9300
1
2
22UF
805
CERM
6.3V
20%
C9305
1
2
20%
6.3V
CERM
805
22UF
C9310
1
2
22UF
805
CERM
6.3V
20%
C9315
1
2
20%
CERM
22UF
805
6.3V
C9320
1
2
CERM
6.3V
20%
22UF
805
C9325
1
2
20%
6.3V
805
22UF
CERM
C9330
1
2
715
MF-LF
402
1%
1/16W
R9351
1
2
06004
78 87
051-7164
ATI M56 Video Interfaces
SYNC_MASTER=(MASTER)
SYNC_DATE=(MASTER)
NC_GPU_TV_C
NC_GPU_TV_COMP
NC_GPU_TV_Y
NC_GPU_VGA_R
NC_GPU_VGA_G
NC_GPU_VGA_B
GPU_R2
GPU_G2
GPU_B2
GPU_V2SYNC
ATI_R2SET
ATI_RSET
GPU_HPD
NC_LVDS_U_DATAN<3>
NC_LVDS_U_DATAP<3>
LVDS_U_DATA_N<1>
LVDS_U_DATA_P<1>
LVDS_L_CLK_P
LVDS_L_DATA_P<0>
LVDS_L_DATA_P<1>
LVDS_L_DATA_N<0>
TP_GPU_VGA_VSYNC
TP_GPU_VGA_HSYNC
LVDS_U_CLK_P
LVDS_U_CLK_N
LVDS_U_DATA_P<0>
LVDS_U_DATA_N<0>
TMDS_CLK_N
TMDS_DATA_N<0>
TMDS_DATA_N<1>
TMDS_DATA_N<2>
TMDS_DATA_N<5>
TMDS_DATA_N<4>
TMDS_DATA_N<3>
LVDS_L_DATA_N<1>
LVDS_L_DATA_N<2>
LVDS_L_DATA_P<2>
NC_LVDS_L_DATAP<3>
NC_LVDS_L_DATAN<3>
GPU_DDC_A_CLK
GPU_DDC_B_DATA
GPU_DDC_B_CLK
GPU_DDC_A_DATA
ATI_RSET
ATI_R2SET
LVDS_U_DATA_N<2>
LVDS_U_DATA_P<2>
LVDS_L_CLK_N
GPU_DDC_C_CLK
GPU_DDC_C_DATA
GPU_H2SYNC
TMDS_CLK_P
TMDS_DATA_P<5>
TMDS_DATA_P<4>
TMDS_DATA_P<3>
TMDS_DATA_P<2>
TMDS_DATA_P<1>
TMDS_DATA_P<0>
PP2V5_S0_GPU_TPVDD
MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.2 mm
VOLTAGE=2.5V
MIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.3 mm
PP2V5_S0_GPU_TXVDDR
VOLTAGE=2.5V
MIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.25 mm
PP2V5_S0_GPU_AVDD
VOLTAGE=2.5V
PP2V5_S0_GPU_VDD1DI
MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.2 mm
VOLTAGE=2.5V
MIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.3 mm
VOLTAGE=2.5V
PP2V5_S0_GPU_A2VDD
MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.2 mm
PP2V5_S0_GPU_LPVDD
VOLTAGE=2.5V
MIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.35 mm
VOLTAGE=2.5V
PP2V5_S0_GPU_LVDDR
PP2V5_D3C
PP2V5_S0_GPU_VDD2DI
MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.2 mm
VOLTAGE=2.5V
82D7 77C6
82C8
82D8
82C3
82C8
77A8
82C3
82C3
82B8
82C3
67A8
79D7
79D7
79D7
79D7
87B4
87A4
87A4
67A6
74B2
74B2
74C2
74C2
74C2
74C2
80C3
80C3
80C3
74B2
74B2
6B2
6B2
74C2
74C2
6A2
6B2
74B2
74B2
80B8
80B8
80D8
63C1
74B1
74B1
74C1
74C1
74C1
74C1
79D7
79D7
79D7
80D5
78A8
78A8
80A1
74B1
74B1
6B1
6B1
74C1
74C1
6A1
6B1
74B1
74B1
80B1
74A2
74A2
80B1
78B5
78B5
82A7
82A7
80C5
79C7
79C7
79C7
5A4
5A4
5A4
5A4
5A4
5A4
5D4
D
S
G
G
D
S
N-CHN
S
D
G
P-CHN
G
D
S
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
NC
NC
518S0369
ELECTRICAL_CONSTRAINT_SET
Panel has 2K pull-ups
100K pull-ups are for
no-panel case (development).
SPACING
PHYSICAL
INVERTER INTERFACE
NET_TYPE
NC
518S0289
INVERTER EXPECTS ACTIVE HIGH PWM SIGNAL
LCD (LVDS) INTERFACE
100K
MF-LF
402
5%
1/16W
R9450
1
2
0.001uF
CERM
402
20%
50V
C9454
1
2
50V
20%
402
CERM
0.001uF
C9452
1
2
CERM
50V
20%
402
0.001uF
C9450
1
2
10UF
X5R
603
20%
6.3V
C9451
1
2
SM-1
400-OHM-EMI
L9454
1 2
10V
20%
402
CERM
0.1uF
C9453
1
2
SM-1
400-OHM-EMI
L9452
1 2
0.001uF
CERM
20%
50V
402
C9420
1
2
402
0.001uF
CERM
20%
50V
C9410
1
2
0.001uF
20%
CERM
402
50V
C9421
12
MSC-RB30-5-FA
F-RT-SM
CRITICAL
J9400
33
34
1
10
11
12
13
14
15
16
17
18
19
2
20
21
22
23
24
25
26
27
28
29
3
30
4
5
6
7
8
9
0.001uF
CERM
20%
50V
402
C9401
1
2
SM
FERR-250-OHM
L9400
50V
CERM
0.0022uF
10%
402
C9400
1 2
100K
MF-LF
402
1/16W
5%
R9401
MF-LF
402
5%
1/16W
100K
R9400
1
2
TSOP-LF
SI3443DV
Q9400
1
2
5
63
4
2N7002
SOT23-LF
Q9401
3
1
2
100K
5%
1/16W
MF-LF
402
R9489
1
2
100K
5%
402
MF-LF
1/16W
R9494
1
2
MC74VHC1G08
SC70
U9453
3
2
1
4
5
SC70-6
FDG6332C_NL
Q9450
6
2
1
SC70-6
FDG6332C_NL
Q9450
3
5
4
MF-LF
1/16W
5%
100K
402
R9411
1
2
100K
5%
1/16W
MF-LF
402
R9410
1
2
CRITICAL
FERR-220-OHM-2A
0603
L9455
1
2
0603
FERR-220-OHM-2A
CRITICAL
L9450
1 2
CRITICAL
SM04B-ACH
M-RT-SM
J9450
5
6
1
2
3
4
SYNC_DATE=08/08/2006
SYNC_MASTER=M57_MLB_MG
79 87
06004051-7164
Internal Display Connectors
GND_CHASSIS_LVDS
PP5V_S0
PP5V_INVERTER_SW_F
MIN_LINE_WIDTH=0.5 mm
VOLTAGE=5V
MIN_NECK_WIDTH=0.25 mm
INVERTER_BKLTON
FP_PWR_EN_L
GND_CHASSIS_LVDS
GND_CHASSIS_LVDS
PP3V3_LCD_CONN
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=3.3V
GND_CHASSIS_LVDS
VOLTAGE=3.3V
MIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.5 mm
PP3V3_LCD_SW
LCD_PWREN_L_RC
LVDS_PANEL_EN
LCD_PWREN_L
PP3V3_S5
LVDS_L_DATA_CONN_P<0>
LVDS_L_DATA_CONN_N<0>
LVDS_U_DATA_CONN_N<0>
LVDS_L_CLK_CONN_N
LVDS_L_CLK_CONN_P
LVDS_L_DATA_CONN_P<2>
LVDS_L_DATA_CONN_N<2>
LVDS_L_DATA_CONN_P<1>
LVDS_L_DATA_CONN_N<1>
LVDS_U_DATA_CONN_P<0>
LVDS_U_DATA_CONN_N<1>
LVDS_U_DATA_CONN_P<1>
LVDS_U_DATA_CONN_N<2>
LVDS_U_DATA_CONN_P<2>
LVDS_U_CLK_CONN_N
LVDS_U_CLK_CONN_P
LVDSLVDS
LVDS_U_CLK_CONN_P
LVDS_U_CLK_CONN_N
LVDS LVDS
LVDS_U_DATA_CONN_P<2..0>
LVDSLVDS
LVDS_U_DATA_CONN_N<2..0>
LVDSLVDS
LVDS_L_CLK_CONN_P
LVDS LVDS
LVDS_L_CLK_CONN_N
LVDSLVDS
LVDS_L_DATA_CONN_P<2..0>
LVDSLVDS
TMDS_CLK_N
TMDS TMDS
TMDS_DATA_P<2..0>
TMDS TMDS
TMDS_DATA_P<5..3>
TMDS TMDS
LVDS_L_CLK_P
LVDSLVDS
LVDS_L_CLK_N
LVDS LVDS
LVDS_L_DATA_P<2..0>
LVDS LVDS
LVDS_L_DATA_N<2..0>
LVDSLVDS
GPU_G2
VGA VGA
LVDS_CONN_DDC_DATA
LVDS_CONN_DDC_CLK
PP3V3_S0
LVDS_U_CLK_N
LVDSLVDS
LVDS_U_DATA_P<2..0>
LVDS LVDS
LVDS_U_DATA_N<2..0>
LVDS LVDS
TMDS_DATA_N<2..0>
TMDS TMDS
TMDS_DATA_N<5..3>
TMDS TMDS
LVDS_L_DATA_CONN_N<2..0>
LVDS LVDS
TMDS_CLK_P
TMDS TMDS
LVDS_U_CLK_P
LVDSLVDS
GPU_B2
VGA VGA
GPU_R2
VGA VGA
GND_CHASSIS_INVERTER
PPBUS_G3H
VOLTAGE=12.8V
MIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.5 mm
PPBUS_S0_INVERTER
PP5V_INVERTER_SW
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=5V
INVERTER_PWM
GND_CHASSIS_INVERTER
INVERTER_PWM_F
INVERTER_PWM_UNBUF
PP3V3_S0
PLT_RST_L
82D5
82D5
82C6
82C6
82B3
82B3
82A4
82A4
79A8
79D3
71D2
71D2
67C5
67C5
67C3
67C3
67B3
67B3
67A3
67A3
66B6
66B6
66B5
66B5
66B1
66B1
65D6
65D6
65B3
65B3
62A6
62A6
61D8
61D8
61A5
61A5
60D4
60D4
60C7
60C7
58C7
58C7
58C4
58C4
57B6
57B6
54D4
54D4
54B5
54B5
52D3
52D3
49C7
49C7
49C4
49C4
49B5
49B5
40B6
40B6
36D6
36D6
34A8
34A8
33D8
33D8
33D3
33D3
33C7
33C7
29A6
29A6
29A3
29A3
28A6
28A6
27D8
27D8
27D5
27D5
27D3
27D3
27C3
27C3
26D1
26D1
26B8
26B8
26B6
26B6
26B4
26B4
67D5
25D8
25D8
67D3
25D3
25D3
67C3
25C6
25C6
66C5
25C4
25C4
65D8
25B8
25B8
65D2
25B4
25B4
81B3
65D1
25A4
25A4
80B5
65C8
24D3
24D3
80A1
63D8
24C3
71D7
24C3
71A6
56D4
24B5
69C1
24B5
67B3
26C5
24B3
68D5
24B3
67B1
25D2
23D5
67C3
23D5
67A1
25C8
23B3
67C1
23B3
66B5
25B6
22B5
65D6
22B5
62B1
24C3
21D3
65B7
21D3
61D7
24B3
21C3
64D7
21C3
58C7
24A5
20B4
64A6
20B4
82A4
58C4
23D8
20A4
62D7
20A4
26C3
57B5
23D4
19C7
61D7
19C7
26C1
55A8
23D1
19C6
82C8
61D4
19C6
26B1
53C4
23B7
17C6
82C3
82C8
79A5
55D3
17C6
26A4
79D2
36D6
79D3
79D3
79D3
23A7
82C8
82D8
82D8
82D8
14D6
82C3
82B3
82C3
82C3
45C5
43D8
14D6
22A6
79C3
31C5
79D2
79D2
79C3
22D8
82D1
87A4
87A4
82C3
82C3
82C3
82C3
14C7
82B8
78B3
78B3
87A4
87A4
82B8
45B5
42B8
14C7
14B7
79B2
25D8
79B2
79C3
79B2
22C6
82C1
82D1
87B4
80D8
80B8
78A3
78A3
78A3
78A3
82A7
82A7
10C5
78B3
6B2
6B2
80D8
80B8
87B4
78B3
6A8
41C6
10C5
6C7
6A8
5D4
6A8
6A8
6A8
11B5
82C1
82C1
82D1
82C1
82C1
82C1
82C1
82C1
82C1
82D1
82C1
82C1
82D1
82C1
82C1
82C1
82C1
82C1
79C2
82C1
82C1
82C1
82C1
80C8
80C8
80A8
6B2
6B2
6B2
6B2
80C3
82A5
82A5
5D4
6A2
6B1
6B1
80C8
80A8
82C1
80B8
6A2
80C3
80C3
6A6
5C4
5D4
6C6
6A6
5D2
82A2
6A6
6A6
6A6
82B6
82A2
5D4
79D7
79D7
79D7
79D7
79D7
79D7
79D7
79D7
79D7
79D7
79D7
79D7
79D7
79D7
79D7
79D7
79B2
79B2
79B2
79C2
79C2
79C2
79C2
78C3
78C3
78C3
6B1
6B1
6B1
6B1
78B3
13D5
13D5
5A4
6A1
6A1
6A1
78C3
78C3
79C2
78C3
6A1
78B3
78B3
5B2
5A1
5B2
5B2
5B2
82A2
5A4
5C4
G
SD
G
SD
G
SD
LCFILTER
LCFILTER
LCFILTER
SYM_VER-1
G
SD
SYM_VER-1
SYM_VER-1
SYM_VER-1
SYM_VER-1
SYM_VER-1
SYM_VER-1
G
S D
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
TMDS Filtering
SPACING
NET_TYPE
PHYSICAL
ELECTRICAL_CONSTRAINT_SET
PLACE U9750 & U9751 CLOSE TO DVI CONNECTOR
(DAC2 Comp)
(DAC2 Y)
PLACE CLOSE TO CONNECTOR
ANALOG FILTERING
VGA SYNC BUFFERS
DVI INTERFACE
DVI DDC CURRENT LIMIT
3V LEVEL SHIFTERS
PLACE NEAR 3, 11 & 19
514-0278
Isolation required for DVI power switch
(DAC2 C)
(PP5V_S0_DDC)
PLACE NEAR C5A & C5B
(55mA requirement per DVI spec)
Place termination components close to GPU, common mode chokes near connector.
1/16W
10K
402
MF-LF
5%
R9721
1
2
10K
MF-LF
402
5%
1/16W
R9720
1
2
2N7002DW-X-F
SOT-363
Q9711
6
2
1
2N7002DW-X-F
SOT-363
Q9711
3
5
4
1/16W
MF-LF
270K
402
5%
R9722
1
2
5%
100pF
50V
CERM
402
C9713
1
2
MF-LF
4.7K
1/16W
5%
402
R9712
1
2
5%
4.7K
MF-LF
402
1/16W
R9710
1
2
100pF
50V
5%
402
CERM
C9711
1
2
20%
50V
603
CERM
0.01uF
C9710
1
2
SM-1
400-OHM-EMI
L9710
1 2
2N7002DW-X-F
SOT-363
Q9714
3
5
4
SM-LF
0.5AMP-13.2V
CRITICAL
F9710
1 2
SOD-123
B0530WXF
D9710
1 2
402
50V
5%
CERM
100pF
C9714
1
2
100
1/16W
5%
402
MF-LF
R9711
1 2
402
100
1/16W
5%
MF-LF
R9713
1 2
MF-LF
402
5%
1/16W
100
R9714
1 2
0
1/16W
MF-LF
5%
402
R9730
12
402
1/16W
5%
MF-LF
0
R9731
12
50V
0.25%
402
CERM
3.3pF
C9741
1
2
75
MF-LF
402
1%
1/16W
R9742
1
2
75
MF-LF
402
1%
1/16W
R9740
1
2
75
MF-LF
402
1%
1/16W
R9741
1
2
50V
0.25%
402
CERM
3.3pF
C9742
1
2
50V
0.25%
402
CERM
3.3pF
C9740
1
2
SM-220MHZ-LF
CRITICAL
FL9740
1 2
3 4
CRITICAL
SM-220MHZ-LF
FL9741
1 2
3 4
SM-220MHZ-LF
CRITICAL
FL9742
1 2
3 4
402
MF-LF
1/16W
5%
33
R9750
1 2
33
MF-LF
402
5%
1/16W
R9751
1 2
CRITICAL
F-RT-TH-DVI
QH11121-RIG02-4F
J9700
C1
C2
C3
C4
C5AC5B
31
32
33
34
1
10
11
12
13
14
15
16
17
18
19
2
20
21
22
23
24
3
4
5
6
7
8
9
MF-LF
402
5%
1/16W
20K
R9715
1
2
1/16W
182
MF-LF
402
1%
R9786
1
2
182
1%
1/16W
MF-LF
402
R9782
1
2
182
402
1/16W
1%
MF-LF
R9778
1
2
5%
1/16W
MF-LF
0
402
R9773
1 2
0
1/16W
MF-LF
402
5%
R9772
1 2
1%
1/16W
MF-LF
182
402
R9770
1
2
1/16W
1%
402
182
MF-LF
R9766
1
2
370-OHM
SM
CRITICAL
L9706
1
2 3
4
CERM
20%
10V
0.1uF
402
C9751
1
2
20%
10V
CERM
402
0.1uF
C9750
1
2
MC74VHC1G08
SC70
U9750
3
2
1
4
5
MC74VHC1G08
SC70
U9751
3
2
1
4
5
1%
182
MF-LF
402
1/16W
R9762
1
2
0402
47nH
L9743
1
2
47nH
0402
L9748
1
2
47nH
0402
L9747
1
2
0402
47nH
L9746
1
2
47nH
0402
L9745
1
2
0402
47nH
L9744
1
2
SOT-363
2N7002DW-X-F
Q9715
6
2
1
402
MF-LF
1/16W
5%
270K
R9723
1
2
402
1%
MF-LF
1/16W
182
R9774
1
2
1210-4SM1
90-OHM-100MA
CRITICAL
L9700
1
2 3
4
CRITICAL
90-OHM-100MA
1210-4SM1
L9701
1
2 3
4
1210-4SM1
90-OHM-100MA
CRITICAL
L9702
1
2 3
4
CRITICAL
90-OHM-100MA
1210-4SM1
L9704
1
2 3
4
CRITICAL
90-OHM-100MA
1210-4SM1
L9703
1
2 3
4
CRITICAL
90-OHM-100MA
1210-4SM1
L9705
1
2 3
4
2N7002DW-X-F
SOT-363
Q9714
6
2
1
SYNC_MASTER=M59_MLB
External Display Connector
80 87
06004
SYNC_DATE=09/15/2006
051-7164
TMDS_DATA_N<0>
TMDS_DATA_F_P<0>
PP5V_S0_DDC
MIN_LINE_WIDTH=0.38 mm
VOLTAGE=5V
MIN_NECK_WIDTH=0.25 mm
DVI_DDC_DATA_R
DVI_DDC_CLK_R
TMDS_DATA_F_P<1>
TMDS_DATA_F_P<3>
DVI_HPD_R
TMDS_DATA_F_N<2>
TMDS_DATA_F_N<1>
TMDS_DATA_F_P<2>
TMDS_DATA_RL<0>
VOLTAGE=0V
NO_TEST=TRUE
TMDS_DATA_P<1>
TMDS_DATA_N<5>
TMDS_DATA_P<5>
TMDS_DATA_F_P<5>
TMDS_DATA_F_N<5>
TMDS_DATA_N<4>
TMDS_DATA_P<4>
TMDS_DATA_F_P<4>
TMDS_DATA_F_N<4>
TMDS_DATA_N<3>
TMDS_DATA_P<3>
TMDS_DATA_F_P<3>
TMDS_DATA_F_N<3>
TMDS_DATA_N<2>
TMDS_DATA_P<2>
TMDS_DATA_F_P<2>
TMDS_DATA_F_N<2>
TMDS_DATA_N<1>
TMDS_DATA_F_P<1>
TMDS_DATA_F_N<1>
TMDS_DATA_P<0>
TMDS_DATA_F_P<0>
TMDS_DATA_F_N<0>
GPU_V2SYNC
PP3V3_D3C
DVI_DDC_DATA
GND
GPU_DDC_A_DATA
GPU_DDC_A_CLK
VOLTAGE=5V
MIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.38 mm
PP5V_S0_DDC_F
PP5V_S0_DDC_PULLUPS
MIN_LINE_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=5V
GPU_B2
VOLTAGE=0V
NO_TEST=TRUE
TMDS_DATA_RL<5>
VGA_VSYNC
VGA_R
GND_CHASSIS_DVI_TOP
PP5V_S0
GND_CHASSIS_DVI_TOP
DVI_DDC_CLK
TMDS_CLK_F_P
TMDS_CLK_F_N
VGA_B
VGA_HSYNC
TMDS_DATA_F_N<5>
TMDS_DATA_F_P<5>
TMDS_CLK_F_P
TMDS_CLK_F_N
PP3V3_D3C
GPU_H2SYNC
VGA_HSYNC_R
VGA_HSYNC
VGA_VSYNC_R
VGA_VSYNC
VGA_B
VGA_G
VGA_R
GPU_G2
GPU_R2
VGA_G
GND_CHASSIS_DVI_BOT
NO_TEST=TRUE
VOLTAGE=0V
TMDS_DATA_RL<3>
TMDS_DATA_F_N<0>
TMDS_DATA_RL<1>
VOLTAGE=0V
NO_TEST=TRUE
VOLTAGE=0V
NO_TEST=TRUE
TMDS_DATA_RL<4>
TMDS_DATA_RL<2>
VOLTAGE=0V
NO_TEST=TRUE
TMDS_CLK_N
TMDS_CLK_P
TMDS_CLK_R_P
TMDS_CLK_R_N
TMDS_CLK_R_N
TMDSTMDS
TMDS_CLK_R_P
TMDSTMDS
TMDS_CLK_F_N
TMDSCONNTMDSCONN
TMDS_CLK_F_P
TMDSCONNTMDSCONN
TMDS_DATA_F_P<5..0>
TMDSCONN TMDSCONN
TMDS_DATA_F_N<5..0>
TMDSCONNTMDSCONN
GND_CHASSIS_DVI_BOT
TMDS_DATA_F_N<3>
TMDS_DATA_F_N<4>
TMDS_DATA_F_P<4>
GPU_SIGNAL_ENABLE
PP3V3_D3C
GPU_HPD
GPU_HPD_BILAT
SB_DVI_HPD
DVI_HPD
MAKE_BASE=TRUE
SB_DVI_HPD
PP5V_S0
81B3
81B3
80A1
80B5
79B8
79B8
71A6
71A6
67B3
67B3
82D7
67B1
82D7
67B1
82A7
67A1
82A7
82D7
67A1
80D5
66B5
80D5
82A7
66B5
80B2
62B1
80B2
80D5
62B1
77D2
61D7
77D2
77D2
61D7
77C6
58C7
77C6
77C6
58C7
77B7
58C4
77B7
77B7
58C4
74D6
57B5
74D6
74D6
57B5
74B2
55A8
74B2
87A4
87A4
74B2
55A8
71C4
53C4
71C4
80D6
80D6
71C4
53C4
71B8
36D6
71B8
80C6
80C6
71B8
36D6
71A4
31C5
71A4
80A2
80B6
80B6
80B5
71A4
31C5
87A4
87A4
87A4
87A4
87A4
87A4
87A4
87A4
87A4
87A4 87A4
87A4
87A4
87A4 87A4
87A4
87A4
87A4
87A4
87A4
87A4
87A4
87A4
87A4
87A4
87A4
87A4
87A4
87A4
87A4
67A5
80A5
25D8
80A3
87A4
87A4
87A4
87A4
87A4
67A5
6B8
87A4
87B4
87B4
87A4
87A4
80B5
80B5
6B8
87A4
87A4
87A4
82A7
67A5
25D8
79C7
80D6
80D1
80D1
80D1
80D1
80D1
79C7
79C7
79C7 80D1
80D1
79C7
79C7 80D1
80D1
79C7
79C7
80D1
80D1
79C7
79C7
80D1
80D1
79C7
80D1
80D1
79C7
80D1
80D1
67A3
79D7
6B8
5D4
6B8
80D1
80D1
80D1
80D1
80D1
67A3
79D7
79D7
6B6
80D6
79C7
79C7
80C6
80B6
80B3
80B3
6B6
80D1
80D1
80D1
26A2
67A3
80A1
80A1
5D4
78C3
80D1
80C6
80B6
80C6
80C6
80C6
78C3
78C3
78C3 80B5
80B5
78C3
78C3 80B3
80B3
78C3
78C3
80B3
80B3
78C3
78C3
80B3
80B3
78C3
80B3
80B3
78C3
80B5
80B5
78B3
65C7
78A3
78A3
78B3
80D3
80C1
6B6
5D2
6B6
80B6
80C6
80C1
80C3
80A6
80A6
80A5
65C7
78B3
80A5
80A3
80A5
80A3
80A3
78B3
78B3
80C1
6A6
80D1
78C3
78C3
80D1
80D1
80C7
80B7
80A5
80B5
80A6
80A6
6A6
80B6
80A6
80A6
26A1
65C7
78A5
22A6 22A6
5D2
IO
IO
IN
IN
IN
OUT
OUT
IO
IO
SYM_VER-1
SYM_VER-1
OUT
IN
IO
IO
IO
IO
OUT
OUT
IO
IO
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
Bluetooth (M13P) & SATA HDD Flex Connector
Top-Case Connector
516S0350
NC
NC
NC
516S0350
IR & Sleep LED Connector
518S0474
QT500166-L020
M-ST-SM
CRITICAL
J4960
1
10
1112
1314
1516
2
34
56
78
9
0.0047uF
CERM
25V
402
10%
PLACEMENT_NOTE=Place C4961 next to C4960
C4961
2 1
402
CERM
0.0047uF
25V
10%
PLACEMENT_NOTE=Place C4960 close to southbridge
C4960
2 1
PLACEMENT_NOTE=Place FL4960 close to southbridge
90-OHM-100MA
1210-4SM1
FL4960
PLACEMENT_NOTE=Place FL4965 close to J4960
90-OHM-100MA
1210-4SM1
FL4965
10%
CERM
402
0.0047uF
25V
PLACEMENT_NOTE=Place C4965 close to J4960
C4966
2 1
402
25V
CERM
10%
0.0047uF
PLACEMENT_NOTE=Place C4966 next to C4965
C4965
2 1
CRITICAL
M-RT-SM
88231-06001-01
J9800
7
8
1
2
3
4
5
6
M-ST-SM
CRITICAL
QT500166-L020
J4900
1
10
11 12
13 14
15 16
2
3 4
5 6
7 8
9
RCLAMP0502B
SC-75
CRITICAL
D4900
3
1
2
SYNC_DATE=(MASTER)
SYNC_MASTER=(MASTER)
051-7164 06004
8781
M57 SPECIFIC CONNECTORS
SATA_C_D2R_UF_N
SATA_C_D2R_UF_P
SATA_C_R2D_UF_P
SATA_C_R2D_UF_N
SATA_C_R2D_N
SATA_C_R2D_P
SATA_C_D2R_C_P
SATA_C_D2R_N
SATA_C_D2R_P
SATA_C_R2D_C_P
SATA_C_R2D_C_N
PP3V3_S3
SATA_C_D2R_C_N
PP5V_S0
USB_BT_P
USB_BT_N
PP5V_S3
USB_IR_N
USB_IR_P
SYS_LED_ANODE
PP3V42_G3H
PP5V_S3
USB_TRACKPAD_P
USB_TRACKPAD_N
KBDLED_ANODE
KBDLED_RETURN
SMBUS_SB_SCL
SMBUS_SMC_A_S3_SCL
SMBUS_SMC_A_S3_SDA
SMBUS_SB_SDA
SMC_LID
SMC_ONOFF_L
PP3V3_S3
69C8
81D4
69B8
81A5
67C5
80B5
69A8
67C5
67C3
80A1
68B8
67C3
66C6
79B8
67D5
66C6
65D1
71A6
67D3
65D1
63B7
67B3
66D2
63B7
60C2
67B1
66C8
60C2
59C6
67A1
66A8
59C6
57D4
66B5
53C4
57D4
52B1
62B1
52D7
52B1
46D6
61D7
52B7
46D6
46C3
58C7
52B5
46C3
46B3
58C4
52B1
46B3
41C5
57B5
81C4
51D4
81C6
41C5
37D7
55A8
67B3
51D3
67B3
37D7
37D5
53C4
67B1
51C2
67B1
37D5
37C3
36D6
22C2
62A2
47B5
62A2
37C3
37A7
31C5
6C3
52B8
35B7
52B8
22C2
22C2
52C6
37A7
32C5
25D8
6C2
45C3
27C3
45C3
6D3
6D3
52B2
32C5
27C5
5D4
6C1
5D4
46C3
46C3
26D6
5D4
6D2
6D2
52B2
51C5
27C5
21B6
21B6
21B6
21B6
5D4
5D2
5A7
5B2
46A5
46B5
52A7
5D2
5B2
6D1
6D1
57A4
57A4
51B5
5A2
5D4
SYM_VER-3
GND
SEL
DB19*
DB18*
DB17*
DB16*
DB15*
DB14*
DB13*
DB12*
DB11*
DB10*
DB9* DH19
DH14
DH13
DH12
DH11
DH10
DH9
DH15
DH16
DH17
DH18
DB4*
DB5*
DB6*
DB7*
DB8*
DB0*
DB1*
DB2*
DB3*
DH4
DH3
DH2
DH1
DH0
DH8
DH7
DH6
DH5
DA15
DA16
DA17
DA18
DA19
DA13
DA14
DA12
DA11
DA10
DA5
DA6
DA7
DA8
DA9
DA0
DA1
DA2
DA3
DA4
VDD
G
S D
G
S D
1B1
4B2
2B1
2B2
3B1
3B2
4B1
1B2
1A
2A
3A
4A
OE*
S
THRML
PAD
GND
VCC
SYM_VER-2
V3
V4
RST*
V2
V1
GND
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
GPU DDC Pass FETs
LVDS Interface Pull-downs
requirements. Resulting pump-up in LCD panel can cause startup
LVDS Mux Selection Qualification
that the GPU has turned on panel power and that the
eliminate need for LVDS pulldowns
panel power has risen to (near) 3.3V. This should
Enables the GPU LVDS path in the mux with the qualification
at 3.3V/3.315V. Schmitt trigger voltage max is 1.70V (@2.625V Vcc).
R9981 can also be used as pad for cap, creating an RC filter.
LVDS I/F Mux
NOTE: S = HIGH selects xB2
NOTE: SB_GPIO23 has internal 20K PU to default selection to GPU
Panel/Backlight Control Mux
NC
NOTE: SEL = LOW selects port B
NC
NC
NC
NB LVDS I/F
GPU LVDS I/F
on LVDS signals when they should be 0V.
and long-term reliability issues. Pull-down resistors reduce
when they should be tri-stated to meet panel power sequence
M56 part. Bias voltage is present on LVDS interface pins even
NOTE: These parts are to counter an invalid state caused by the
PGOOD Monitor for GPU Rails
the pump-up in the panel, though some voltage will still be seen
D3CPGOOD_3V3 BOM option uses only PP3V3_D3C to qualify D3CPGOOD.
D3CPGOOD_ALL BOM option stuffs LTC2903 circuit to monitor all D3C rails to qualify D3CPGOOD.
LTC2903 guaranteed threshold is 93.5% (3.055V, 2.325V, 1.685V, 1.120V)
Divider set to rise to 1.88V nom/1.74V min when panel power is
LVDS_PD
1/16W
SM-LF
8.2K
5%
RP9900
1 8
1/16W
8.2K
5%
LVDS_PD
SM-LF
RP9902
1 8
D3CPGOOD_ALL
5%
MF-LF
402
1/16W
470K
R9996
1
2
CBTV4020
CRITICAL
BGA-LF
U9950
F1
H1
K1
K3
K4
K6
J7
K9
J10
G10
E10
C10
A10
A8
A7
A5
B4
A2
B1
D1
G1
J1
K2
J4
K5
K7
K8
K10
H10
F10
D10
B10
A9
B7
A6
A4
A3
A1
C1
E1
F2
H2
J2
J3
J5
J6
J8
J9
H9
F9
E9
C9
B9
B8
B6
B5
B3
B2
C2
E2
C5C6D2D9G2G9H5
H6
E3
E8F3F8
MC74VHC1G08
SC70
U9985
3
2
1
4
5
402
0.1UF
CERM
10V
20%
C9985
1
2
SOT-363
2N7002DW-X-F
Q9970
6
2
1
SOT-363
2N7002DW-X-F
Q9970
3
5
4
D3CPGOOD_ALL
402
0.1UF
20%
10V
CERM
C9993
1
2
LVDS_PD
8.2K
5%
1/16W
SM-LF
RP9902
3 6
D3CPGOOD_ALL
402
10V
20%
0.1UF
CERM
C9995
1
2
D3CPGOOD_ALL
CERM
10V
20%
0.1UF
402
C9992
1
2
5%
10K
1/16W
402
MF-LF
R9997
1
2
MC74VHC1G08
SC70
U9961
3
2
1
4
5
NO STUFF
402
MF-LF
1/16W
5%
0
R9962
1
2
0.1UF
402
CERM
20%
10V
C9961
1
2
D3CPGOOD_3V3
6.3V
10%
1UF
402
CERM
C9996
1
2
LVDS_PD
5%
SM-LF
8.2K
1/16W
RP9902
4 5
LVDS_PD
8.2K
5%
1/16W
SM-LF
RP9903
2 7
8.2K
1/16W
5%
LVDS_PD
SM-LF
RP9903
1 8
5%
LVDS_PD
8.2K
SM-LF
1/16W
RP9903
3 6
8.2K
1/16W
5%
LVDS_PD
SM-LF
RP9903
4 5
LVDS_PD
8.2K
5%
SM-LF
1/16W
RP9900
2 7
LVDS_PD
SM-LF
8.2K
5%
1/16W
RP9900
4 5
402
0.1UF
CERM
10V
20%
C9950
1
2
8.2K
1/16W
SM-LF
5%
LVDS_PD
RP9900
3 6
10V
20%
CERM
402
0.1UF
C9960
1
2
LVDS_PD
8.2K
SM-LF
5%
1/16W
RP9901
2 7
15.8K
1%
402
1/16W
MF-LF
R9970
1
2
15.8K
1%
402
1/16W
MF-LF
R9971
1
2
CRITICAL
74CBTLV3257
QFN
U9960
42
3
75
6
9
11
10
1214
13
15
8117
16
1/16W
5%
SM-LF
LVDS_PD
8.2K
RP9901
1 8
402
CERM
10V
20%
0.1UF
C9980
1
2
402
10K
MF-LF
1/16W
5%
R9960
1
2
100K
MF-LF
1/16W
5%
402
R9961
1
2
1/16W
LVDS_PD
8.2K
5%
SM-LF
RP9901
3 6
SN74LVC1G132
SC70-5
CRITICAL
U9980
3
1
2
4
5
8.2K
1/16W
5%
LVDS_PD
SM-LF
RP9901
4 5
1/16W
402
5%
MF-LF
10K
R9980
12
1/16W
MF-LF
402
13.3K
1%
R9981
1
2
0.1uF
CERM
402
20%
10V
C9991
1
2
MC74VHC1G08
SC70
U9991
3
2
1
4
5
D3CPGOOD_ALL
402
0.1uF
CERM
20%
10V
C9990
1
2
LVDS_PD
8.2K
1/16W
5%
SM-LF
RP9902
2 7
CRITICAL
D3CPGOOD_ALL
LTC2903
TSOT-23
U9990
2
6
1
3
4
5
D3CPGOOD_ALL
365K
1/16W
1%
402
MF-LF
R9990
1
2
D3CPGOOD_ALL
MF-LF
1/16W
1%
237K
402
R9992
1
2
D3CPGOOD_ALL
1/16W
MF-LF
1%
402
124K
R9994
1
2
D3CPGOOD_ALL
MF-LF
1/16W
1%
402
100K
R9991
1
2
D3CPGOOD_ALL
100K
MF-LF
402
1%
1/16W
R9993
1
2
D3CPGOOD_ALL
100K
1/16W
1%
402
MF-LF
R9995
1
2
SYNC_MASTER=M59_MLB
051-7164
82
06004
87
SYNC_DATE=09/15/2006
LVDS Interface Pull-downs
PP2V5_D3C
D3CPGOOD_1V8_DIV
D3CPGOOD_1V2_DIV
D3CPGOOD_2V5_DIV
PP3V3_D3C
D3CPGOOD_PWROK
LVDS_L_CLK_P
LVDS_L_CLK_N
LVDS_U_CLK_P
INVERTER_BKLTON
GPU_VARY_BL
LVDS_BKLTCTL
LVDS_BKLTEN
LVDS_VDDEN
LVDS_PANEL_EN
GPU_DIGON
=LVDS_PD_U_CLK_P
=LVDS_PD_U_DATA_P<1>
=LVDS_PD_L_CLK_P
LVDS_U_DATA_N<0>
=LVDS_PD_U_DATA_N<1>
=LVDS_PD_L_CLK_N
LVDS_L_DATA_N<0>
LVDS_MUX_SEL_GPULVDS_MUX_SEL_GPU
MAKE_BASE=TRUE
LVDS_MUX_SEL_GPU
S0PGOOD_PWROK
S0D3CPGOOD_PWROK
INVERTER_PWM_UNBUF
PGOOD_MUXED_S0_OR_S0D3C
=LVDS_PD_L_DATA_P<2>
GPU_BLON
LVDS_L_DATA_P<0>
PP3V3_S0
S0D3CPGOOD_PWROK
=LVDS_PD_L_DATA_N<2>
LVDS_A_CLK_P
LVDS_B_DATA_P<0>
LVDS_B_DATA_N<2>
LVDS_B_DATA_N<0>
LVDS_A_DATA_P<2>
LVDS_A_DATA_P<0>
LVDS_A_DATA_N<0>
LVDS_A_CLK_N
LVDS_A_DATA_P<1>
LVDS_A_DATA_N<1>
LVDS_A_DATA_N<2>
LVDS_B_DATA_P<1>
LVDS_B_DATA_P<2>
LVDS_B_CLK_P
LVDS_B_CLK_N
LVDS_B_DATA_N<1>
LVDS_U_DATA_P<0>
LVDS_U_DATA_N<0>
LVDS_U_DATA_N<2>
LVDS_L_CLK_P
LVDS_L_CLK_N
LVDS_L_DATA_N<0>
LVDS_L_DATA_P<0>
LVDS_L_DATA_P<2>
LVDS_L_DATA_P<1>
LVDS_L_DATA_N<1>
LVDS_L_DATA_N<2>
LVDS_U_DATA_P<1>
LVDS_U_CLK_P
LVDS_U_CLK_N
LVDS_U_DATA_N<1>
LVDS_U_DATA_P<2>
LVDS_U_DATA_CONN_P<0>
LVDS_U_DATA_CONN_N<2>
LVDS_U_DATA_CONN_N<0>
LVDS_L_DATA_CONN_P<0>
LVDS_L_DATA_CONN_N<0>
LVDS_L_CLK_CONN_N
LVDS_L_CLK_CONN_P
LVDS_L_DATA_CONN_P<1>
LVDS_L_DATA_CONN_N<1>
LVDS_L_DATA_CONN_N<2>
LVDS_L_DATA_CONN_P<2>
LVDS_U_DATA_CONN_P<1>
LVDS_U_DATA_CONN_N<1>
LVDS_U_CLK_CONN_N
LVDS_U_CLK_CONN_P
LVDS_U_DATA_CONN_P<2>
PP2V5_S0
LVDS_MUX_SEL_GPU_L
PP3V3_LCD_SW
PP2V5_S0
LVDS_MUX_SEL_GPU
PANEL_PWR_ON
PP3V3_S0
=LVDS_PD_U_CLK_N
LVDS_U_CLK_N
LVDS_U_DATA_P<0>
PP3V3_S0
GPU_DIGON_AND_SELECTED
GPU_DIGON
PP1V2_D3C
PP1V8_D3C
S0PGOOD_PWROK
GPU_SIGNAL_ENABLE
PP3V3_D3C
LVDS_CONN_DDC_CLK
MAKE_BASE=TRUE
MAKE_BASE=TRUE
LVDS_CONN_DDC_DATA
GPU_DDC_C_CLK
GPU_DDC_C_DATA
LVDS_CONN_DDC_CLK
LVDS_CONN_DDC_DATA
PLT_RST_L
PP3V3_S0
LVDS_MUX_SEL_GPU_MUXED
LVDS_MUX_SEL_GPU
82C6
82D5
82D5
82D5
82B3
82B3
82C6
82C6
82A4
82A4
82A4
82B3
79D3
79D3
79D3
79D3
79A8
79A8
79A8
79A8
71D2
71D2
71D2
71D2
67C5
67C5
67C5
67C5
67C3
67C3
67C3
67C3
67B3
67B3
67B3
67B3
67A3
67A3
67A3
67A3
66B6
66B6
66B6
66B6
66B5
66B5
66B5
66B5
66B1
66B1
66B1
66B1
65D6
65D6
65D6
65D6
65B3
65B3
65B3
65B3
62A6
62A6
62A6
62A6
61D8
61D8
61D8
61D8
61A5
61A5
61A5
61A5
60D4
60D4
60D4
60D4
60C7
60C7
60C7
60C7
58C7
58C7
58C7
58C7
58C4
58C4
58C4
58C4
57B6
57B6
57B6
57B6
54D4
54D4
54D4
54D4
54B5
54B5
54B5
54B5
52D3
52D3
52D3
52D3
49C7
49C7
49C7
49C7
49C4
49C4
49C4
49C4
49B5
49B5
49B5
49B5
40B6
40B6
40B6
40B6
36D6
36D6
36D6
36D6
34A8
34A8
34A8
34A8
33D8
33D8
33D8
33D8
33D3
33D3
33D3
33D3
33C7
33C7
33C7
33C7
29A6
29A6
29A6
29A6
29A3
29A3
29A3
29A3
28A6
28A6
28A6
28A6
27D8
27D8
27D8
27D8
27D5
27D5
27D5
27D5
27D3
27D3
27D3
27D3
27C3
27C3
27C3
27C3
26D1
26D1
26D1
26D1
26B8
26B8
26B8
26B8
26B6
26B6
26B6
26B6
26B4
26B4
26B4
26B4
25D8
25D8
25D8
25D8
25D3
25D3
25D3
25D3
25C6
25C6
25C6
25C6
25C4
25C4
25C4
25C4
25B8
25B8
25B8
25B8
25B4
25B4
25B4
25B4
25A4
25A4
25A4
25A4
24D3
24D3
24D3
24D3
24C3
24C3
24C3
24C3
24B5
24B5
24B5
24B5
24B3
24B3
24B3
24B3
23D5
23D5
23D5
23D5
82A7
23B3
82C5
82D3
23B3
23B3
82D7
23B3
80D5
22B5
67B6
67B6
22B5
22B5
80D5
22B5
80B2
21D3
67A8
67A8 21D3
21D3
80B2
21D3
77D2
21C3
67A6
67A6 21C3
21C3
77D2
21C3
77C6
20B4
66B5
66B5
20B4
20B4
77C6
79A8
20B4
77B7
20A4
63D1
63D1
20A4
20A4
77B7
26C3
20A4
74D6
19C7
19D7
19D7
19C7
19C7
77B8
74D6
26C1
19C7
78C8
74B2
19C6
19C5
19C5
19C6
19C6
70C7
74B2
26B1
19C6
77C6
71C4
17C6
19A8
19A8 17C6
17C6
70A1
71C4
26A4
17C6
77A8
71B8
82C3
82C3
82C3
82C3
82C3
82C3
14D6
82C8
82C8
82C8
82D8
82B8
82B8
19A6
19A6 14D6
82C3
82C3
14D6
67D8
71B8
22A6
14D6
67A8
71A4
79D7
79D7
79D7
79D7
79D7
82B6
79D7
14C7
79D7
79D7
79D7
79D7
79D7
79D7
19A4
19A4 14C7
79D7
79D7
14C7
67D6
71A4
14B7
14C7
82B6
67A6
67A5
78A3
78A3
78B3
78B3
78A3
82B6
82A4
77D3
78A3
10C5
78B3
78B3
79D7
78A3
78A3
79D7
79D7
79D7
79D7
78B3
78B3
79D7
79D7
17D6
17D6
82A4
10C5
78B3
78B3
10C5
67C6
80B2
67A5
82A7
82A7
82A5
82A5
6C7
10C5
82A4
63C1
67A3
6B2
6B2
6A2
82B6
6B2
6B2
82A4
82A3
82D5
74C8
6B2 5D4
6B2
6B2
78B3
6B2
6B2
78A3
78A3
78A3
78B3
6A2
6A2
78B3
78B3
79D7
79D7
79D7
79D7
79D7
79D7
79D7
79D7
79D7
79D7
79D7
79D7
79D7
79D7
79D7
79D7
17C6
17C6
82A3
5D4
6A2
6B2
5D4
82A4
63B1
82A4
26A2
67A3
79C3
79C3
79C3
79C3
6C6
5D4
82A3
5D4
65C7
6B1
6B1
6A1
79B8
77C3
13D5
13D5
13D5 79D4
77C3
6B2
6A2
6B2
6B1
6A2
6B2
6B1
21D5
21D5
66A2
82C4
79A8
66B2
6B2
74C5
6B1 5A4
82A4
6B2
13C5
13C5
13C5
13C5
13C5
13C5
13C5
13D5
13C5
13C5
13C5
13C5
13C5
13C5
13C5
13C5
6B1
6B1
6A1
6B1
6B1
6B1
6B1
6B1
6B1
6A1
6A1
6B1
6A1
79C2
79C2
79C2
79C2
79C2
79C2
79C2
79C2
79C2
79C2
79C2
79C2
79C2
79B2
79B2
79B2
5D4
79D3
5D4
21D5
5A4
6B2
6A1
6B1
5A4
77C3
5D4
66A2
26A1
65C7
13D5
13D5
78A3
78A3
13D5
13D5
5C4
5A4
21D5
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
Revision History
83 87
06004051-7164
SYNC_DATE=(MASTER)
SYNC_MASTER=(MASTER)
Revision History
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
AREA_TYPE
SPACING_RULE_SET
NET_SPACING_TYPE1 NET_SPACING_TYPE2
TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
MINIMUM LINE WIDTH
ALLOW ROUTE
ON LAYER?
LAYER
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
LINE-TO-LINE SPACING
LAYER
SPACING_RULE_SET
WEIGHT
TABLE_SPACING_RULE_HEAD
MINIMUM LINE WIDTH
ALLOW ROUTE
ON LAYER?
LAYER
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
LINE-TO-LINE SPACING
LAYER
SPACING_RULE_SET
WEIGHT
TABLE_SPACING_RULE_HEAD
LINE-TO-LINE SPACING
LAYER
SPACING_RULE_SET
WEIGHT
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_ITEM
LINE-TO-LINE SPACING
LAYER
SPACING_RULE_SET
WEIGHT
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
AREA_TYPE
SPACING_RULE_SET
NET_SPACING_TYPE1 NET_SPACING_TYPE2
TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
LINE-TO-LINE SPACING
LAYER
SPACING_RULE_SET
WEIGHT
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
AREA_TYPE
SPACING_RULE_SET
NET_SPACING_TYPE1 NET_SPACING_TYPE2
TABLE_SPACING_ASSIGNMENT_HEAD
MINIMUM LINE WIDTH
ALLOW ROUTE
ON LAYER?
LAYER
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
LINE-TO-LINE SPACING
LAYER
SPACING_RULE_SET
WEIGHT
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
AREA_TYPE
SPACING_RULE_SET
NET_SPACING_TYPE1 NET_SPACING_TYPE2
TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
AREA_TYPE
SPACING_RULE_SET
NET_SPACING_TYPE1 NET_SPACING_TYPE2
TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
MINIMUM LINE WIDTH
ALLOW ROUTE
ON LAYER?
LAYER
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_SPACING_RULE_ITEM
LINE-TO-LINE SPACING
LAYER
SPACING_RULE_SET
WEIGHT
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
LINE-TO-LINE SPACING
LAYER
SPACING_RULE_SET
WEIGHT
TABLE_SPACING_RULE_HEAD
MINIMUM LINE WIDTH
ALLOW ROUTE
ON LAYER?
LAYER
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
MINIMUM LINE WIDTH
ALLOW ROUTE
ON LAYER?
LAYER
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
AREA_TYPE
SPACING_RULE_SET
NET_SPACING_TYPE1 NET_SPACING_TYPE2
TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTH
ALLOW ROUTE
ON LAYER?
LAYER
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTH
ALLOW ROUTE
ON LAYER?
LAYER
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_SPACING_RULE_ITEM
LINE-TO-LINE SPACING
LAYER
SPACING_RULE_SET
WEIGHT
TABLE_SPACING_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
MINIMUM LINE WIDTH
ALLOW ROUTE
ON LAYER?
LAYER
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
LINE-TO-LINE SPACING
LAYER
SPACING_RULE_SET
WEIGHT
TABLE_SPACING_RULE_HEAD
AREA_TYPE
SPACING_RULE_SET
NET_SPACING_TYPE1 NET_SPACING_TYPE2
TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
LINE-TO-LINE SPACING
LAYER
SPACING_RULE_SET
WEIGHT
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
Worst-case spacing is 2:1 within Data bus, with 3:1 spacing to the DSTBs.
DSTB complementary pairs are spaced 3:1, even in constraint areas.
Worst-case spacing is 2:1 within Addr bus, with 3:1 spacing to the ADSTBs.
Disk Interface Constraints
SOURCE: Napa Platform DG, Rev 0.9 (#17978), Sections 10.6 & 10.7.2
SOURCE: Napa Platform DG, Rev 0.9 (#17978), Sections 7.2, 9.2 & 10.5.2
PCI-Express / DMI Bus Constraints
Design Guide recommends FSB signals be routed only on internal layers.
SOURCE: Napa Platform DG, Rev 0.9 (#17978), Section 10.10.1.2
Internal Interface Constraints
DG says minimum spacing 50 mils to clocks
SOURCE: Napa Platform DG, Rev 0.9 (#17978), Section 10.9.1
Audio Interface Constraints
SOURCE: Napa Platform DG, Rev 0.9 (#17978), Section 6.2
SOURCE: Napa Platform DG, Rev 0.9 (#17978), Sections 4.4, 4.6.2, & 5.8.2.4
Need to support MEM_*-style wildcards!
Some signals require 27.4-ohm single-ended impedance.
NOTE: Design Guide allows closer spacing if signal lengths can be shortened.
Design Guide recommends each strobe/signal group is routed on the same layer.
NOTE: Design Guide does not indicate FSB spacing to other signals, assumed 3:1.
All FSB signals with impedance requirements are 55-ohm single-ended.
CPU Signal Constraints
DDR2 Memory Bus Constraints
Most CPU signals with impedance requirements are 55-ohm single-ended.
USB 2.0 Interface Constraints
Clock Signal Constraints
SOURCE: Napa Platform DG, Rev 0.9 (#17978), Section 10.17.1.1
FSB (Front-Side Bus) Constraints
SOURCE: Napa Platform DG, Rev 0.9 (#17978), Sections 4.2 & 4.3
DG recommends at least 25 mils, >50 mils preferred
?
FSB_DSTB
*
=3:1_SPACING
?
FSB_DATA2DSTB
*
=3:1_SPACING
?
FSB_DATA2DATA
*
=2:1_SPACING
?*
FSB_DATA
=3:1_SPACING
MEM_2OTHER
MEM_DATA
* *
MEM_2OTHER
MEM_CMD
**
20 MIL
*
PCIE
?
20 MIL
*
DMI
?
=STANDARD=STANDARD
=55_OHM_SE=55_OHM_SE=55_OHM_SE
Y*
AUDIO_55S
=1.8:1_SPACING
*
AUDIO
?
SPI_55S
* Y
=55_OHM_SE =55_OHM_SE =55_OHM_SE
=STANDARD =STANDARD
*
=4:1_SPACING
USB2
?
SMB_55S
* Y
=55_OHM_SE =55_OHM_SE =55_OHM_SE
=STANDARD =STANDARD
25 MIL
*
USB2_2CLK
?
=55_OHM_SE
CLK_SLOW_55S
* Y
=55_OHM_SE =55_OHM_SE
=STANDARD =STANDARD
MEM_CTRL2CTRL
=2:1_SPACING
* ?
MEM_2OTHER
MEM_DQS
**
25 MIL
MEM_2OTHER
* ?
*
=4:1_SPACING
MEM_CLK2MEM
?
=85_OHM_DIFF
Y
MEM_85D
=85_OHM_DIFF
=85_OHM_DIFF
*
=85_OHM_DIFF=85_OHM_DIFF
=55_OHM_SE
* Y
MEM_55S
=STANDARD =STANDARD
=55_OHM_SE=55_OHM_SE
25 MIL
CPU_GTLREF
* ?
25 MIL
*
CPU_COMP
?
*
FSB_ADSTB
=3:1_SPACING
?
CPU_27P4S
=STANDARD=STANDARD
=27P4_OHM_SE=27P4_OHM_SE=27P4_OHM_SE
Y*
=45_OHM_SE=45_OHM_SE
Y
MEM_45S
=STANDARD
=45_OHM_SE
=STANDARD
*
MEM_CTRL
MEM_CTRL2MEM
MEM_CLK
*
MEM_CTRL
*
MEM_CTRL2CTRL
MEM_CTRL
MEM_CTRL2MEM
*
=3:1_SPACING
?
*
=1.8:1_SPACING
IDE
?
=2:1_SPACING
*
CPU_2TO1
?
FSB_DATA2DSTB
*
FSB_DATA FSB_DSTB
FSB_ADDR2ADDR
FSB_ADDRFSB_ADDR
*
=100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF
=100_OHM_DIFF =100_OHM_DIFF
* Y
SATA_100D
=STANDARD=STANDARD
=55_OHM_SE=55_OHM_SE=55_OHM_SE
Y*
IDE_55S
MEM_CMD2MEM
MEM_CMD
*
MEM_DQS
FSB_COMMON
*
=2:1_SPACING
?
=100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF
=100_OHM_DIFF =100_OHM_DIFF
DMI_100D
Y*
=100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF
=100_OHM_DIFF =100_OHM_DIFF
PCIE_100D
* Y
10 MIL
*
CLK_SLOW
?
20 MIL
*
CLK_MED
?
SMB
*
=3:1_SPACING
?
MEM_CMD
*
MEM_CTRL2MEM
MEM_CTRL
=1.5:1_SPACING
MEM_DATA2DATA
* ?
MEM_DATA2MEM =3:1_SPACING
* ?
MEM_DQS2MEM
*
=3:1_SPACING
?
MEM_2OTHER
MEM_CLK
**
MEM_2OTHER
MEM_CTRL
* *
MEM_DQS
MEM_DQS2MEM
*
MEM_DATA
*
FSB_ADSTB
FSB_ADDR
FSB_ADDR2ADSTB
20 MIL
*
SATA
?
=90_OHM_DIFF=90_OHM_DIFF
=90_OHM_DIFF=90_OHM_DIFF=90_OHM_DIFF
USB2_90D
* Y
=STANDARD=STANDARD
=55_OHM_SE
Y
=55_OHM_SE
*
=55_OHM_SE
FSB_55S
20 MIL
*
CLK_PCIE
?
MEM_CMD2MEM
*
=3:1_SPACING
?
25 MIL
*
CLK_FSB
?
=70_OHM_DIFF
Y*
=70_OHM_DIFF =70_OHM_DIFF
=70_OHM_DIFF
MEM_70D
=70_OHM_DIFF
=STANDARD=STANDARD
Y
=55_OHM_SE
*
=55_OHM_SE =55_OHM_SE
CPU_55S
=55_OHM_SE =55_OHM_SE
CLK_MED_55S
* Y
=55_OHM_SE
=STANDARD =STANDARD
=100_OHM_DIFFCLK_PCIE_100D =100_OHM_DIFF =100_OHM_DIFF
=100_OHM_DIFF =100_OHM_DIFF
* Y
=100_OHM_DIFF
CLK_FSB_100D
=100_OHM_DIFF =100_OHM_DIFF
=100_OHM_DIFF =100_OHM_DIFF
* Y
*
SPI
=1.8:1_SPACING
?
MEM_CMD2CMD
*
=1.5:1_SPACING
?
*
MEM_DQS2MEM
MEM_DQS MEM_DQS
MEM_CMD
*
MEM_CMD2MEM
MEM_CLK
MEM_DATA2DATA
MEM_DATAMEM_DATA
**
MEM_CMD
MEM_CMD2MEM
MEM_DATA
*
MEM_CLK
MEM_CLK2MEM
MEM_CMD
*
MEM_CLK2MEM
MEM_CTRL
MEM_CLK
*
MEM_CLK2MEM
MEM_CLKMEM_CLK
MEM_DQS
MEM_DQS2MEM
*
MEM_CLK
MEM_DQS
MEM_DQS2MEM
*
MEM_CTRL
*
MEM_DQS2MEM
MEM_DQS MEM_CMD
*
MEM_CLK
MEM_CLK2MEM
MEM_DQS
*
MEM_DATA
MEM_DATA2MEM
MEM_CTRL
*
MEM_DATA2MEM
MEM_DATA
MEM_CLK
MEM_DATA2MEM
MEM_DATA
*
MEM_CMD
MEM_DATA2MEM
MEM_DATA
*
MEM_DQS
*
MEM_CMD
MEM_CMD2MEM
MEM_CTRL
*
MEM_CMD MEM_CMD
MEM_CMD2CMD
MEM_DQS
MEM_CTRL
*
MEM_CTRL2MEM
MEM_DATA
MEM_CTRL2MEM
*
MEM_CTRL
MEM_CLK2MEM
MEM_CLK
*
MEM_DATA
25 MIL
*
CPU_VCCSENSE
?
CPU_ITP
*
=2:1_SPACING
?
FSB_DATA
*
FSB_DATA
FSB_DATA2DATA
FSB_ADDR2ADSTB
*
=3:1_SPACING
?
*
FSB_ADDR2ADDR
=2:1_SPACING
?
*
=3:1_SPACING
FSB_ADDR
?
84 87
06004051-7164
Napa Platform Constraints
SYNC_MASTER=(MASTER)
SYNC_DATE=(MASTER)
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTH
ALLOW ROUTE
ON LAYER?
LAYER
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
LINE-TO-LINE SPACING
LAYER
SPACING_RULE_SET
WEIGHT
TABLE_SPACING_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
LINE-TO-LINE SPACING
LAYER
SPACING_RULE_SET
WEIGHT
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
MINIMUM LINE WIDTH
ALLOW ROUTE
ON LAYER?
LAYER
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
MINIMUM LINE WIDTH
ALLOW ROUTE
ON LAYER?
LAYER
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_RULE_ITEM
LINE-TO-LINE SPACING
LAYER
SPACING_RULE_SET
WEIGHT
TABLE_SPACING_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
LINE-TO-LINE SPACING
LAYER
SPACING_RULE_SET
WEIGHT
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTH
ALLOW ROUTE
ON LAYER?
LAYER
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
AREA_TYPE
SPACING_RULE_SET
NET_SPACING_TYPE1 NET_SPACING_TYPE2
TABLE_SPACING_ASSIGNMENT_HEAD
LINE-TO-LINE SPACING
LAYER
SPACING_RULE_SET
WEIGHT
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
Video Signal Constraints
SOURCE: ATI Layout Guide, Rev 0.5 (DSG-216MOBRADEON-05), Sections 7 & 8.1.2.
note
DQ/DQM/DQS lines are 40-ohm single-ended impedence.
CTRL lines are 55-ohm single-ended impedence.
LVDS and TMDS signals are 100-ohm +/- 10% differential impedence.
LVDS and TMDS pairs should be kept at least 25 mils apart.
Ground shields can be used around each pair if spacing cannot be met.
Ground shields recommended around VGA signals.
VGA should be routed as close to 75-ohms single-ended impedence as possible.
SOURCE: ATI Layout Guide, Rev 0.5 (DSG-216MOBRADEON-05), Sections 7 & 8.1.2.
NOTE: Layout Guide does not specify LVDS/TMDS spacing to other traces other than "do not run close"
High-Speed I/O Interface Constraints
PCI Bus Constraints
NOTE: CLK lines are specified in Layout Guide as 40-ohm single-ended. We treat as 75-ohm differential.
GDDR3 (Frame Buffer) Memory Bus Constraints
ADDR/CTRL lines should route 35-ohms to T, then 55-ohms to each VRAM device.
NOTE: Layout Guide does not specify LVDS/TMDS spacing to other traces other than "do not run close"
VGA signals should be kept at least 15 mils from other traces.
?
25 MIL
TMDS_PAIR2PAIR
*
?
25 MIL
LVDS_PAIR2PAIR
*
FB_55S
=55_OHM_SE
*
=55_OHM_SE
=STANDARD =STANDARD
=55_OHM_SE
Y
=55_OHM_SE=35_OHM_SE
Y*
=STANDARD =STANDARD
=35_55_OHM_SEFB_35S_TO_55S
=100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF
=100_OHM_DIFF
Y*
TMDS_100D
=100_OHM_DIFF
*
ENET
=3:1_SPACING
?
*
FW
=3:1_SPACING
?
VGA
*
15 MIL
?
TMDS
*
=3:1_SPACING
?
LVDS
=3:1_SPACING
* ?
VGA_75S
=75_OHM_SE=75_OHM_SE=75_OHM_SE
=STANDARD
Y*
=STANDARD
Y
=40_OHM_SE =40_OHM_SE
=STANDARD=STANDARD
*
=40_OHM_SE
FB_40S
*
=2.5:1_SPACING
FB_CLK
?
TMDS
*
TMDS_PAIR2PAIR
TMDS
=100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF
=100_OHM_DIFF
* Y
LVDS_100D
=100_OHM_DIFF
* Y
=75_OHM_DIFF =75_OHM_DIFF =75_OHM_DIFF
=75_OHM_DIFF =75_OHM_DIFF
FB_75D
LVDS
LVDS_PAIR2PAIR
*
LVDS
=2:1_SPACING
PCI
* ?
Y
=55_OHM_SE
=STANDARD=STANDARD
=55_OHM_SE
*
=55_OHM_SE
PCI_55S
=2.5:1_SPACING
FB_ADCTRL
* ?
FB_DATA
*
=2.5:1_SPACING
?
FW_110D
=110_OHM_DIFF=110_OHM_DIFF
=110_OHM_DIFF=110_OHM_DIFF=110_OHM_DIFF
Y*
Y*
=100_OHM_DIFF=100_OHM_DIFF
=100_OHM_DIFF=100_OHM_DIFF=100_OHM_DIFF
ENET_100D
85 87
06004051-7164
More System Constraints
SYNC_MASTER=(MASTER)
SYNC_DATE=(MASTER)
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTH
ALLOW ROUTE
ON LAYER?
LAYER
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTH
ALLOW ROUTE
ON LAYER?
LAYER
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
MINIMUM LINE WIDTH
ALLOW ROUTE
ON LAYER?
LAYER
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
MINIMUM LINE WIDTH
ALLOW ROUTE
ON LAYER?
LAYER
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
LINE-TO-LINE SPACING
LAYER
SPACING_RULE_SET
WEIGHT
TABLE_SPACING_RULE_HEAD
AREA_TYPE
SPACING_RULE_SET
NET_SPACING_TYPE1 NET_SPACING_TYPE2
TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
OVERRIDEOVERRIDE OVERRIDE OVERRIDE
TABLE_SPACING_RULE_OVERRIDE
OVERRIDEOVERRIDE OVERRIDE OVERRIDE
TABLE_SPACING_RULE_OVERRIDE
LINE-TO-LINE SPACING
LAYER
SPACING_RULE_SET
WEIGHT
TABLE_SPACING_RULE_HEAD
OVERRIDEOVERRIDE OVERRIDE OVERRIDE
TABLE_SPACING_RULE_OVERRIDE
OVERRIDEOVERRIDE OVERRIDE OVERRIDE
TABLE_SPACING_RULE_OVERRIDE
OVERRIDEOVERRIDE OVERRIDE OVERRIDE
TABLE_SPACING_RULE_OVERRIDE
LINE-TO-LINE SPACING
LAYER
SPACING_RULE_SET
WEIGHT
TABLE_SPACING_RULE_HEAD
OVERRIDEOVERRIDE OVERRIDE OVERRIDE
TABLE_SPACING_RULE_OVERRIDE
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
LINE-TO-LINE SPACING
LAYER
SPACING_RULE_SET
WEIGHT
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
LINE-TO-LINE SPACING
LAYER
SPACING_RULE_SET
WEIGHT
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
LINE-TO-LINE SPACING
LAYER
SPACING_RULE_SET
WEIGHT
TABLE_SPACING_RULE_HEAD
OVERRIDEOVERRIDE OVERRIDE OVERRIDE
TABLE_SPACING_RULE_OVERRIDE
OVERRIDEOVERRIDE OVERRIDE OVERRIDE
TABLE_SPACING_RULE_OVERRIDE
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_ASSIGNMENT_ITEM
OVERRIDEOVERRIDE OVERRIDE OVERRIDE
TABLE_SPACING_RULE_OVERRIDE
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_PHYSICAL_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_PHYSICAL_RULE_ITEM
OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_ITEM
AREA_TYPE
SPACING_RULE_SET
NET_SPACING_TYPE1 NET_SPACING_TYPE2
TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_ITEM
LINE-TO-LINE SPACING
LAYER
SPACING_RULE_SET
WEIGHT
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
MINIMUM LINE WIDTH
ALLOW ROUTE
ON LAYER?
LAYER
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
MINIMUM LINE WIDTH
ALLOW ROUTE
ON LAYER?
LAYER
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_ASSIGNMENT_ITEM
TABLE_PHYSICAL_ASSIGNMENT_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTH
ALLOW ROUTE
ON LAYER?
LAYER
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
MINIMUM LINE WIDTH
ALLOW ROUTE
ON LAYER?
LAYER
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTH
ALLOW ROUTE
ON LAYER?
LAYER
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
MINIMUM LINE WIDTH
ALLOW ROUTE
ON LAYER?
LAYER
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTH
ALLOW ROUTE
ON LAYER?
LAYER
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTH
ALLOW ROUTE
ON LAYER?
LAYER
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTH
ALLOW ROUTE
ON LAYER?
LAYER
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_BOARD_INFO
VERSION
ALLEGRO
(MIL or MM)
BOARD UNITS
BOARD LAYERS
BOARD AREAS
LINE-TO-LINE SPACING
LAYER
SPACING_RULE_SET
WEIGHT
TABLE_SPACING_RULE_HEAD
MINIMUM LINE WIDTH
ALLOW ROUTE
ON LAYER?
LAYER
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE
TABLE_PHYSICAL_RULE_ITEM
OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE
TABLE_PHYSICAL_RULE_ITEM
AREA_TYPE
SPACING_RULE_SET
NET_SPACING_TYPE1 NET_SPACING_TYPE2
TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
AREA_TYPE
SPACING_RULE_SET
NET_SPACING_TYPE1 NET_SPACING_TYPE2
TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
PHYSICAL_RULE_SET
AREA_TYPE
NET_PHYSICAL_TYPE
TABLE_PHYSICAL_ASSIGNMENT_HEAD
OVERRIDEOVERRIDE OVERRIDE OVERRIDE
TABLE_SPACING_RULE_OVERRIDE
MINIMUM LINE WIDTH
ALLOW ROUTE
ON LAYER?
LAYER
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
MINIMUM LINE WIDTH
ALLOW ROUTE
ON LAYER?
LAYER
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTH
ALLOW ROUTE
ON LAYER?
LAYER
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
M9 Board-Specific Spacing & Physical Constraints
Rules for "Topology #3" for FSB signals, Napa DG tables 4-7 & 4-12.
Allow 0.1 MM on blind-to-buried via dogbones (layers 2 & 11)
Unsupported rule
"Stale" physical / spacing types
Y
TOP,BOTTOM
45_OHM_SE
0.150 MM 0.150 MM
FSB_ADSTB
*
=2:1_SPACING
?
*
FSB_COMMON
*
FSB_ANALOG
ENET
**
ENETCONN
*
0.100 MM
MEM_70D
*
MEM_85D
0.100 MM
TOP,BOTTOM
Y
50_OHM_SE
0.124 MM 0.124 MM
NO_TYPE,BGA
15.2
MM
TOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,ISL8,ISL9,ISL10,ISL11,BOTTOM
TOP,BOTTOM
Y
35_OHM_SE
0.230 MM 0.230 MM
* *
STANDARDFB_PP1V8
30 MM
* Y
0 MM 0 MM
=55_OHM_SE =55_OHM_SE
DEFAULT
12.7 MM
Y
=DEFAULT
*
STANDARD
=DEFAULT =DEFAULT
=DEFAULT
=STANDARD
Y*
110_OHM_DIFF
0.330 MM 0.330 MM
0.077 MM 0.077 MM
0.125 MM
85_OHM_DIFF
=STANDARD
Y*
0.101 MM
0.125 MM
0.101 MM
TOP,BOTTOM
85_OHM_DIFF
Y
0.125 MM 0.125 MM
0.125 MM 0.125 MM
100_OHM_DIFF
=STANDARD
Y*
0.080 MM
0.200 MM 0.200 MM
0.080 MM
Y
TOP,BOTTOM
100_OHM_DIFF
0.099 MM 0.099 MM
0.200 MM 0.200 MM
Y
=STANDARD
*
0.149 MM 0.149 MM
0.125 MM 0.125 MM
70_OHM_DIFF
TOP,BOTTOM
Y
0.185 MM 0.185 MM
0.125 MM 0.125 MM
70_OHM_DIFF
Y
0.115 MM 0.111 MM
0.125 MM 0.125 MM
=STANDARD
*
80_OHM_DIFF
TOP,BOTTOM
Y
80_OHM_DIFF
0.140 MM 0.140 MM
0.125 MM 0.125 MM
TOP,BOTTOM
110_OHM_DIFF
Y
0.089 MM 0.089 MM
0.330 MM 0.330 MM
0.100 MM
40_OHM_SE
* Y
=STANDARD
=STANDARD =STANDARD
0.131 MM
TOP,BOTTOM
Y
0.185 MM
40_OHM_SE
0.185 MM
*
TMDS_100D
TMDS
*
TMDS_100D
TMDSCONN
TOP,BOTTOM
0.100 MM
Y
55_OHM_SE
0.100 MM
*
BGA
CLK_MED
BGA_P2MM
CLK_SLOW
*
BGA
BGA_P2MM
ISL2,ISL11
0.1 MM
1.8:1_SPACING
?
FSB_DSTB BGA_P3MMFSB_DSTB
BGA
FB_CLK
BGA_P2MM
BGA
*
ISL2,ISL11
0.1 MM
2:1_SPACING
?
0.1 MM
ISL2,ISL11
1.5:1_SPACING
?
ISL2,ISL11
0.1 MM
3:1_SPACING
?
*
0.076 MM0.076 MM
=STANDARD=STANDARD
=STANDARD55_OHM_SE
Y
**
BGA
BGA_P1MM
ISL2,ISL11
0.1 MM
2.5:1_SPACING
?
0.100 MM
MEM_45S
*
* Y
=STANDARD =STANDARD
0.165 MM 0.165 MM
35_OHM_SE =STANDARD
TMDS
**
TMDSCONN
VGA
*
VGA_75S
BGA
CLK_FSB
*
BGA_P2MM
BGA_P2MMCLK_PCIE
BGA
*
MEM_CLK
BGA_P2MM
BGA
*
TOP,BOTTOM
Y
27P4_OHM_SE
0.335 MM0.335 MM
Y
75_OHM_DIFF
0.161 MM 0.161 MM
TOP,BOTTOM
0.125 MM 0.125 MM
=STANDARD
*
90_OHM_DIFF
0.102 MM 0.102 MM
0.220 MM 0.220 MM
Y
TOP,BOTTOM
Y
90_OHM_DIFF
0.130 MM
0.220 MM 0.220 MM
0.130 MM
=STANDARD
* Y
=STANDARD
=STANDARD
0.076 MM0.076 MM
75_OHM_SE
* Y
=STANDARD
=STANDARD
50_OHM_SE
0.090 MM
=STANDARD
0.090 MM
FSB_ADDR2ADSTB
*
=2:1_SPACING
?
LVDS
*
LVDS_100D
0.105 MM 0.105 MM
45_OHM_SE
* Y
=STANDARD =STANDARD
=STANDARD
0.1 MM
ISL2,ISL11
4:1_SPACING
?
FSB_ADDR
*
=2:1_SPACING
?
=STANDARD
*
FSB_ADDR2ADDR
?
?
ISL2,ISL11
0.1 MM
CLK_SLOW
?
LVDS_PAIR2PAIR
ISL2,ISL11
0.1 MM
?
0.1 MM
ISL2,ISL11
CPU_VCCSENSE
?
DMI 0.1 MM
ISL2,ISL11
?
0.1 MM
ISL2,ISL11
CPU_COMP
?
ISL2,ISL11
0.1 MM
CPU_GTLREF
?
TMDS_PAIR2PAIR
0.1 MM
ISL2,ISL11
?
VGA
ISL2,ISL11
0.1 MM
?
0.1 MM
ISL2,ISL11
CLK_FSB
?
ISL2,ISL11
0.1 MM
CLK_PCIE
?
ISL2,ISL11
0.1 MM
PCIE
?
MEM_2OTHER
0.1 MM
ISL2,ISL11
?
0.1 MM
ISL2,ISL11
CLK_MED
?
SATA
0.1 MM
ISL2,ISL11
?
2:1_SPACING
0.2 MM
*
?*
1.5:1_SPACING
0.15 MM
?
0.18 MM
*
1.8:1_SPACING
?*
0.25 MM
2.5:1_SPACING
?*
4:1_SPACING
0.4 MM
?*
3:1_SPACING
0.3 MM
?
DEFAULT
*
0.1 MM
?
=DEFAULTSTANDARD
*
?
BGA_P1MM
*
=DEFAULT
?
=DEFAULT
*
BGA_P3MM
?*
BGA_P2MM =DEFAULT
?
=2:1_SPACING
FSB_DATA
*
?
=2:1_SPACING
*
FSB_DSTB
?*
=2:1_SPACING
FSB_DATA2DSTB
?
=STANDARD
FSB_DATA2DATA
*
?*
MEM_2OTHER
0.5 MM
?*
PCI_2PCI
0.1 MM
*
PCI PCI
PCI_2PCI
MEM_PP1V8_S3
**
STANDARD
* *
GND
STANDARD
**
I2C SMB
* *
FSB_COMMON
FSB_P2MM
=STANDARD
Y
75_OHM_DIFF
0.131 MM 0.131 MM
0.125 MM 0.125 MM
*
=STANDARD
0.165 MM
=STANDARD
=STANDARD
Y*
35_55_OHM_SE
0.076 MM
0.100 MM
35_55_OHM_SE
TOP,BOTTOM
0.230 MM
Y
* Y
=STANDARD
27P4_OHM_SE
0.240 MM
=STANDARD
=STANDARD
0.240 MM
86 87
06004051-7164
M9 Spacing & Physical Constraints
SYNC_MASTER=(MASTER)
SYNC_DATE=(MASTER)
I2C
FSB_P2MM
MEM_PP1V8_S3
FB_PP1V8
PCI_55S
PCI
FSB_ANALOG
GND
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
ELECTRICAL_CONSTRAINT_SET
PHYSICAL
NET_TYPE
SPACING
I70
I71
I72
I73
051-7164 06004
8787
M57 NET PROPERTIES
SYNC_DATE=(MASTER)
SYNC_MASTER=(MASTER)
ITPRESET_L
CPU_ITPCPU_55S
CPU_VID<6..0>
CPU_2TO1
CPU_55S
CPU_VID<6..0>
CPU_2TO1
CPU_55S
CPU_VCCSENSE_P
THERM
CPU_VCCSENSE
CPU_27P4S
SB_ACZ_BITCLK
AUDIO
AUDIO_55S
ACZ_BITCLK
AUDIO
AUDIO_55S
CLK_SLOW
CLK_SLOW_55S
SPI
SPI_55S
FSB_DPWR_L
FSB_COMMON
FSB_55S
FSB_REQ_L<4..0>
FSB_ADDR
FSB_55S
CPU_STPCLK_L
CPU_55S
VGA
VGA_75S
LVDS
LVDS_100D
TMDS
TMDS_100D
PCIE
PCIE_100D
TMDS_CLK_P
TMDSTMDS
FSB_BNR_L
FSB_COMMON
FSB_55S
FSB_HITM_L
FSB_COMMON
FSB_55S
SB_ACZ_SYNC
AUDIO
AUDIO_55S
TMDS_CLK_N
TMDSTMDS
ACZ_SYNC
AUDIO
AUDIO_55S
ACZ_SDATAIN<0>
AUDIO
AUDIO_55S
SB_ACZ_SDATAOUT
AUDIO
AUDIO_55S
ACZ_SDATAOUT
AUDIO
AUDIO_55S
ACZ_RST_L
AUDIO
AUDIO_55S
SB_ACZ_RST_L
AUDIO
AUDIO_55S
CLK_MED
CLK_MED_55S
CLK_PCIE
CLK_PCIE_100D
IDE
IDE_55S
FSB_HIT_L
FSB_COMMON
FSB_55S
CPU_THERMTRIP_L
CPU_2TO1
CPU_55S
FSB_IERR_L
CPU_55S
DMI
DMI_100D
FB_DATA
FB_40S
FB_ADCTRL
FB_35S_TO_55S
FB_ADCTRL
FB_55S
CPU_INIT_L
CPU_55S
CPU_SMI_L
CPU_55S
MEM_DATA
MEM_55S
MEM_CTRL
MEM_45S
MEM_CLK MEM_70D
MEM_CMD MEM_55S
FSB_ADS_L
FSB_COMMON
FSB_55S
FSB_BREQ0_L
FSB_COMMON
FSB_55S
XDP_BPM_L<5..0>
CPU_ITPCPU_55S
CPU_XDP_CLK_P
CPU_ITP
CLK_FSB_100D
CPU_COMP<0>
CPU_COMP
CPU_27P4S
IMVP6_VSEN_N
CPU_VCCSENSE
CPU_27P4S
CPU_VCCSENSE_N
THERM
CPU_VCCSENSE
CPU_27P4S
FSB_A_L<31..3>
FSB_ADDR
FSB_55S
FSB_FERR_L
CPU_55S
IMVP_DPRSLPVR
CPU_2TO1
CPU_55S
CPU_PWRGD
CPU_55S
CPU_NMI
CPU_55S
CPU_A20M_L
CPU_55S
CPU_DPSLP_L
CPU_55S
CPU_IGNNE_L
CPU_55S
PM_DPRSLPVR
CPU_2TO1
CPU_55S
CPU_GTLREF
CPU_GTLREF
CPU_55S
CPU_COMP<3>
CPU_COMP
CPU_55S
CPU_COMP<2>
CPU_COMP
CPU_27P4S
FSB_DSTBN_L<3..0>
FSB_DSTB
FSB_55S
FSB_DINV_L<3..0>
FSB_DATA
FSB_55S
FSB_DSTBP_L<3..0>
FSB_DSTB
FSB_55S
FSB_DBSY_L
FSB_COMMON
FSB_55S
FSB_CPURST_L
FSB_COMMON
FSB_55S
FSB_TRDY_L
FSB_COMMON
FSB_55S
CLK_FSB
CLK_FSB_100D
FW
FW_110D
USB2
USB2_90D
FSB_RS_L<2..0>
FSB_COMMON
FSB_55S
FSB_DRDY_L
FSB_COMMON
FSB_55S
FSB_D_L<63..0>
FSB_DATA
FSB_55S
FSB_ADSTB_L<3..0>
FSB_ADSTB
FSB_55S
CPU_INTR
CPU_55S
IMVP6_VSEN_P
CPU_VCCSENSE
CPU_27P4S
CPU_XDP_CLK_N
CPU_ITP
CLK_FSB_100D
SMB
SMB_55S
CPU_COMP<1>
CPU_COMP
CPU_55S
ENET
ENET_100D
SATA
SATA_100D
FB_CLK FB_75D
MEM_DQS MEM_85D
FSB_LOCK_L
FSB_COMMON
FSB_55S
TMDS_CLK_F_N
TMDSCONNTMDSCONN
TMDS_CLK_F_P
TMDSCONNTMDSCONN
TMDS_DATA_P<5..3>
TMDSTMDS
TMDS_DATA_P<2..0>
TMDSTMDS
TMDS_DATA_N<5..3>
TMDSTMDS
TMDS_DATA_N<2..0>
TMDSTMDS
TMDS_DATA_F_P<5..3>
TMDSCONNTMDSCONN
TMDS_DATA_F_P<2..0>
TMDSCONNTMDSCONN
TMDS_DATA_F_N<5..3>
TMDSCONNTMDSCONN
TMDS_DATA_F_N<2..0>
TMDSCONNTMDSCONN
FSB_BPRI_L
FSB_COMMON
FSB_55S
FSB_DEFER_L
FSB_COMMON
FSB_55S
12D6 12C6
12B4
12B4
12B4
12B6
12D4
7C4
7C4
7C4
7C4
80D1
80D6
80D1
80D6
12B4
34D5
12C4
61C8
7C3
7C3
7C3
12C4
7C3
12C4
34D5
80B8
80D8
80B8
80D8
80B6
80D1
80B6
80D1
87B6
87B6
48B3
12B4
12A4
21C4
80B8
12C4
12B4
80C8
48B3
48B3
48B3
48B3
12B4
12C4
12C4
34D3
7D8
21C4
21C4
23C3
7B4
7B4
7B4
12B4
11B5
12B4
7B4
7D8
34D3
12B4
80D1
80D1
80A8
80C8
80A8
80C8
80B5
80C6
80B5
80C6
9C2
9C2
61B1
21C7
7B3
7D8
7C8
79C7
7D6
7D6
79C7
21C7
21C7
21C7
21C7
7D6
21C4
21C4
7D6
7D6
11B3
33C4
61A1
7C8
61C7
7B3
21C4
21C4
7B3
21C4
14B7
7B3
7B3
7B3
7D6
7D6
12A4
12A4
7D6
7B3
7C8
21C4
33C4
7D6
80C6
80B6
79C7
79C7
79C7
79C7
80B3
80B5
80B3
80B5
12C4
12B4
11B3
8B7
8B7
8B6
21C6
5C1
5A4
5A7
5C4
78C3
5B7
5B7
21C6
78C3
5C1
5C1
21C6
5C1
5C1
21C6
5B7
7D6
7D6
7C8
5B7
5B7
7C6
11B3
7B3
61A3
8B6
5B7
5C4
5B4
7C8
7C8
5B4
7C8
5B4
7B4
7B3
7B3
5B7
5B7
5B7
5B7
5A4
7D6
7D6
5B7
5B7
5B7
7C8
61A3
11B3
7B3
5A7
80A5
80B5
78C3
78C3
78C3
78C3
80A6
80B3
80A6
80B3
7D6
7D6
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