ANALOG DEVICES AD5582, AD5583 Service Manual

Quad, Parallel Input, Voltage Output,

44

VOD

–

+

33

A1

32

A0

31

DB11

30

DB10

29

DB9

28

DB8

26

DB7

25

DB6

24

DB5

23

DB4

21

DB3

20

DB2

19

DB1

18

DB0

34

CS

35

R/W

14

DV

DD

17

MSB

16

RS

15

LDAC

I
N
T
E
R
F
A
C
E

OE

CONTROL

LOGIC

22

DGND127DGND236DGND340V

REFHD

39

V

REFLD

41

V

REFHC

42

V

REFLC

45

V

SS2

46

V

DD2

D

O

IN

REG

D

I

47

VOC

3

V

DD1

4

V

SS1

5

VOA

2

VOB

11

R1

12

RCT

13

R2

20k

20k

1

AGND1

48

AGND2

DAC
REG

ADDR

DECODE

38

V

DD3

37

V

SS3

4 4

AD5582

–

+

10

V

REFLA

9

V

REFHA

7

V

REFLB

8

V

REFHB

a

12-/10-Bit Digital-to-Analog Converters

FEATURES
12-Bit Linearity and Monotonic AD5582
10-Bit Linearity and Monotonic AD5583
Wide Operating Range: Single 5 V to 15 V or

Dual 5 V Supply
Unipolar or Bipolar Operation
Double Buffered Registers Enable Independent or

Simultaneous Multichannel Update
4 Independent Rail-to-Rail Reference Inputs
20 mA High Current Output Drive
Parallel Interface
Data Readback Capability
5 s Settling Time
Built-In Matching Resistor Simplifies

Negative Reference
Unconditionally Stable Under Any Capacitive Loading
Compact Footprint: TSSOP-48
Extended Temperature Range: 40C to 125C

APPLICATIONS
Process Control Equipment
Closed-Loop Servo Control
Data Acquisition Systems
Digitally Controlled Calibration
Optical Network Control Loops
4 m to 20 mA Current Transmitter

AD5582/AD5583

AD5582 FUNCTIONAL BLOCK DIAGRAM

GENERAL DESCRIPTION

The AD5582/AD5583 family of quad, 12-/10-bit, voltage output
digital-to-analog converters is designed to operate from a single
5 V to 15 V or dual ± 5 V supply. It offers the user ease of use in
single- or dual-supply systems. Built using an advance BiCMOS
process, this high performance DAC is dynamically stable, capable
of high current drive, and in small form factor.

The applied external reference V
put voltage ranges from V
of full-scale outputs. For multiplying and wide dynamic appli­cations, ac reference inputs can be as high as |V

SS

built-in precision trimmed resistors
configured easily to provide four-

A doubled-buffered parallel interface offers a fast settling time.
A common level sensitive load DAC strobe (LDAC) input allows
additional simultaneous update of all DAC outputs. An external
asynchronous reset (RS) forces all registers to the zero code state
when the MSB = 0 or to midscale when the MSB = 1.

Both parts are offered in the same pinout and package to allow
users to select the appropriate resolution for a given application
without PCB layout changes.

REV. A

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.

determines the full-scale out-

REF

to VDD, resulting in a wide selection

are available and can be

DD

– VSS|. Two

quadrant multiplications.

ADR421

REF

R1

R2

RCT

–

+

2.5V

DIGITAL CIRCUITRY OMITTED FOR CLARITY

V

REFHA

V

REFHB

V

REFHC

V

REFHD

V

REFLA

V

REFLB

V

REFLC

V

REFLD

DAC A

DAC B

DAC C

DAC D

2.5V

2.5V

2.5V

2.5V

AD5582/AD5583

2.5V

Figure 1. Using Built-In Matching Resistors
to Generate a Negative Voltage Reference

The AD5582 is well suited for DAC8412 replacement in medium
voltage applications in new designs, as well as any other general
purpose multichannel 10- to 12-bit applications.

The AD5582/AD5583 are specified over the extended industrial
(–40∞C to +125∞C) temperature range and offered in a thin and
compact 1.1 mm TSSOP-48 package.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2003 Analog Devices, Inc. All rights reserved.

AD5582/AD5583–SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

(VDD = +5 V, VSS = –5 V, DVDD = +5 V  10%, V
–40C < TA < +125C, unless otherwise noted.)

= +2.5 V, V

REFH

= –2.5 V,

REFL

Parameter Symbol Condition Min Typ1Max Unit

STATIC PERFORMANCE

Resolution

Relative Accuracy

2

3

N AD5582 12 Bits

AD5583 10 Bits

INL –1 +1 LSB
Differential Nonlinearity3DNL Monotonic –1 LSB
Zero-Scale Error V

ZSE

Data = 000H for AD5582 –2 +2 LSB
and AD5583

Gain Error V

Gain Error V
Full-Scale Tempco

4

GE

V

GE

GE

TCV

FS

Data = 0xFFFH for AD5582 –2 +2 LSB
Data = 0x3FFH for AD5583 –4 +4 LSB
VDD = 2.7 V to 4.5 V –4 +4 LSB

1.5 ppm/∞C

REFERENCE INPUT

V

Input Range V

REFH

Input Range

V

REFL

5

Input Resistance R

Input Capacitance

4

REF Input Current I

V

C

REF

REFH

REFL

REF

REF

REF Multiplying Bandwidth BW

REF

Data = 555H (Minimum R

)12 20 kW

REF

for AD5582 and 155H for AD5583

Data = 555H for AD5582 500 mA
Code = Full Scale 1.3 MHz

V

+ 0.5 V

REFL

V

SS

V

V

DD

REFH

– 0.5 V

80 pF

1

R1–R2 Matching R1/R2 AD5582 ± 0.025 %

AD5583 ± 0.100 %

ANALOG OUTPUT

Output Current

Output Current

Capacitive Load

6

6

4, 7

I

OUT

I

OUT

C

Data = 800H for AD5582 and ± 2mA
200

for AD5583, V

H

OUT

£ 2 mV

Data = 800H for AD5582 and

for AD5583, V

200

H

£ ± 15 mV –20 mA

V

OUT

L

No Oscillation Note 7 pF

£ |–8 mV| +20 mA

OUT

LOGIC INPUTS

Logic Input Low Voltage V

Logic Input High Voltage V

Input Leakage Current I
Input Capacitance

4

Output Voltage High V
Output Voltage Low V

IL

IH

IL

C

IL

OH

OL

DVDD = 5 V ± 10% 0.8 V

= 3 V ± 10% 0.4 V

DV

DD

DVDD = 5 V ± 10% 2.4 V
DV

= 3 V ± 10% 2.1 V

DD

0.01 1 mA

5pF
IOH = –0.8 mA 2.4 V
IOL = 1.2 mA, TA = 85∞C, 0.4 V

= 0.6 mA, DVDD = 3 V

I

OL

I

= 1.0 mA, TA = 125∞C, 0.4 V

OL

IOL = 0.5 mA, DVDD = 3 V

AC CHARACTERISTICS

Output Slew Rate SR Data = Zero Scale to Full Scale 2 V/ms

to Zero Scale
To ± 0.1% of Full Scale 5 ms

to 800H to 7FF

H

for AD5582 and 1FF

to 200

H

H

H

100 nV-s

Settling Time

8

t

S

DAC Glitch Q Code 7FF

to 1FFH for AD5583

Digital Feedthrough V

OUT/tCS

Data = Midscale, CS Toggles at 5 nV-s
f = 16 MHz

Analog Crosstalk V

Output Noise e

OUT/VREFVREF

N

= 1.5 V dc + 1 V p-p, –80 dB

Data = 000

, f = 100 kHz

H

f = 1 kHz 33 nV/÷Hz

REV. A–2–

AD5582/AD5583

Parameter Symbol Condition Min Typ

1

Max Unit

SUPPLY CHARACTERISTICS

Single-Supply Voltage Range V
Dual-Supply Voltage Range V

Digital Logic Supply DV
Positive Supply Current

6

Negative Supply Current I
Power Dissipation P
Power Supply Sensitivity P

NOTES

1

Typical specifications represent average readings measured at 25∞C.

2

DAC Output Equation: V
AD5582 = 12 bits, AD5583 = 10 bits. One LSB step voltage = (V

3

The first two codes (000H, 001H) of the AD5583 and the first four codes (000H, 001H, 002H, 003H) of the AD5582 are excluded from the linearity error measurement
in single-supply operation.

4

These parameters are guaranteed by design and not subject to production testing.

5

Dual-supply operation, V

6

Short circuit output and supply currents are 24 mA and 25 mA, respectively.

7

Part is stable under any capacitive loading conditions.

8

The settling time specification does not apply for negative-going transitions within the last 3 LSBs of ground in single-supply operation.

Specifications subject to change without notice.

= V

OUT

REFL

= VSS, exclude the lowest eight codes for the AD5582 and two codes for the AD5583 for INL and DNL errors.

REFL

+ [(V

DD

DD/VSS

I

DD

SS

DISS

SS

REFH

DD

– V

ELECTRICAL CHARACTERISTICS

VSS = 0 V 3 18 V
VDD = +2.7 V to +6.5 V, –9 +9 V

= –6.5 V to –2.7 V

V

SS

2.7 8 V
VIL = 0 V, No Load 1.7 3 mA
VIL = 0 V, No Load 1.5 3 mA
VIL = 0 V, No Load 16 30 mW
VDD = ± 5% 30 ppm/V

)  D/2N], where D = data loaded in corresponding DAC Register A, B, C, D, and N equals the number of bits;

REFL

– V

REFH

)/4096 V and (V

REFL

REFH

– V

)/1024 V for AD5582 and AD5583, respectively.

REFL

(VDD = 15 V, VSS = 0 V, DVDD = 5 V  10%, V

= 10 V, V

REFH

REFL

= 0 V,

–40C < TA < +125C, unless otherwise noted.)

Parameter Symbol Condition Min Typ1Max Unit

STATIC PERFORMANCE

Resolution

Relative Accuracy
Differential Nonlinearity
Zero-Scale Error V

2

3

N AD5582 12 Bits

AD5583 10 Bits

INL –1 +1 LSB

3

DNL Monotonic –1 LSB

ZSE

Data = 000H for AD5582 –2 +2 LSB
and AD5583

Gain Error V

Full-Scale Tempco

4

GE

V

GE

TCV

FS

Data = 0xFFFH for AD5582 –2 +2 LSB
Data = 0x3FFH for AD5583 –4 +4 LSB

1.5 ppm/∞C

REFERENCE INPUT

V

Input Range V

REFH

V

Input Range

REFL

5

Input Resistance R

Input Capacitance

4

REF Input Current I

V

C

REF

REFH

REFL

REF

REF

REF Multiplying Bandwidth BW

REF

Data = 555H (Minimum R

)12 20 kW

REF

for AD5582 and 155H for AD5583

Data = 555H for AD5582 1000 mA
Code = Full Scale 1.3 MHz

V

+ 0.5 V

REFL

V

SS

V

V

DD

REFH

– 0.5 V

80 pF

1

R1–R2 Matching R1/R2 AD5582 ± 0.025 %

AD5583 ± 0.100 %

ANALOG OUTPUT

Output Current

Output Current

Capacitive Load

6

6

4, 7

I

OUT

I

OUT

C

Data = 800H for AD5582 and 2 mA

for AD5583, V

200

H

OUT

£ 2 mV

Data = 800H for AD5582 and
200

for AD5583, V

H

£ 15 mV –20 mA

V

OUT

L

No Oscillation Note 7 pF

£ |–8 mV| +20 mA

OUT

REV. A

–3–

AD5582/AD5583

ELECTRICAL CHARACTERISTICS

(continued)

Parameter Symbol Condition Min Typ1Max Unit

LOGIC INPUTS/OUTPUTS

Logic Input Low Voltage V

Logic Input High Voltage V

Input Leakage Current I
Input Capacitance

4

Output Voltage High V
Output Voltage Low V

IL

IH

IL

C

IL

OH

OL

V

OL

= 3 V ± 10% 0.4 V

DV

DD

2.4 V

= 3 V ± 10% 2.1 V

DV

DD

IOH = –0.8 mA 2.4 V
IOL = 1.2 mA, TA = 85C, 0.4 V

= 0.6 mA, DVDD = 3 V

I

OL

IOL = 1.0 mA, TA = 125C, 0.4 V

0.8 V

mA
pF

IOL = 0.5 mA, DVDD = 3 V

AC CHARACTERISTICS

Output Slew Rate SR Data = Zero Scale to Full Scale 2 V/ms

to Zero Scale
To ± 0.1% of Full Scale 14 ms

to 800H to 7FFH for 100 nV-s

AD5582 and 1FF

H

for AD5583

1FF

H

to 200H to

H

Data = Midscale, CS Toggles at 5 nV-s

Settling Time

8

t

S

DAC Glitch Q Code 7FF

Digital Feedthrough V

OUT/tCS

f = 16 MHz
V

Analog Crosstalk V

Output Noise e

OUT/VREF

N

= 1.5 V dc + 1 V p-p, –80 dB

REF

Data = 000

, f = 100 kHz

H

f = 1 kHz 33 nV/÷Hz

SUPPLY CHARACTERISTICS

Single-Supply Voltage Range V
Dual-Supply Voltage Range V

Digital Logic Supply DV
Positive Supply Current

6

Power Dissipation P

DD

DD/VSS

I

DD

DISS

DD

VSS = 0 V 3 16.5 V
VDD = +2.7 V to +6.5 V, –6.5 +6.5 V

= –6.5 V to –2.7 V

V

SS

2.7 6.5 V
VIL = 0 V, No Load 2.3 3.5 mA
VIL = 0 V, No Load 34.5 52.5 mW

Power Supply Sensitivity PSS VDD = ± 5% 30 ppm/V

NOTES

1

Typical specifications represent average readings measured at 25∞C.

2

DAC Output Equation: V
bits; AD5582 = 12 bits, AD5583 = 10 bits. One LSB step voltage = (V

3

The first two codes (000H, 001H) of the AD5583 and the first four codes (000H, 001H, 002H, 003H) of the AD5582 are excluded from the linearity error measurement
in single-supply operation.

4

These parameters are guaranteed by design and not subject to production testing.

5

Dual-supply operation, V

6

Short circuit output and supply currents are 24 mA and 25 mA, respectively.

7

Part is stable under any capacitive loading conditions.

8

The settling time specification does not apply for negative-going transitions within the last 3 LSBs of ground in single-supply operation.

Specifications subject to change without notice.

= V

OUT

REFL

+ [(V

REFL

= VSS, exclude the lowest eight codes for the AD5582 and two codes for the AD5583 for INL and DNL errors.

REFH

– V

)  D/2N], where D = data in decimal loaded in corresponding DAC Register A, B, C, D, and N equals the number of

REFL

REFH

– V

)/4096 V and = (V

REFL

REFH

– V

)/1024 V for AD5582 and AD5583, respectively.

REFL

REV. A–4–

AD5582/AD5583

TIMING CHARACTERISTICS

(VDD = 15 V or 5 V, VSS = 0 V, DVDD = 5 V  10%, V
unless otherwise noted.)

= 10 V, V

REFH

= 0 V, –40C < TA < +125C,

REFL

Parameter Symbol Condition Min Typ Max Unit

INTERFACE TIMING*

Chip Select Write Pulse Width t
Chip Select Read Pulse Width t
Write Setup t
Write Hold t
Address Setup t
Address Hold t
Load Setup t
Load Hold t
Write Data Setup t
Write Data Hold t
Load Data Pulse Width t
Reset Pulse Width t
Read Data Hold t
Read Data Setup t
Data to Hi-Z t
Chip Select to Data t
Chip Select Repetitive Pulse Width t
Load Setup in Double Buffer Mode t
Load Data Hold t

*All input control signals are specified with tR = tF = 2 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V.
Specifications subject to change without notice.

WCS

RCS

WS

WH

AS

AH

LS

LH

WDS

WDH

LDW

RESET

RDH

RDS

DZ

CSD

CSP

LDS

LDH

CL = 10 pF 100 ns
CL = 10 pF 100 ns

20 ns
130 ns
35 ns
0ns
35 ns
0ns
0ns
0ns
35 ns
0ns
20 ns
20 ns
0ns
0ns

10 ns
20 ns
0ns

TIMING CHARACTERISTICS

(VDD = 15 V or 5 V, VSS = 0 V, DVDD = 3 V  10%, V
unless otherwise noted.)

= 10 V, V

REFH

= 0 V, –40C < TA < +125C,

REFL

Parameter Symbol Condition Min Typ Max Unit

INTERFACE TIMING*

Chip Select Write Pulse Width t
Chip Select Read Pulse Width t
Write Setup t
Write Hold t
Address Setup t
Address Hold t
Load Setup t
Load Hold t
Write Data Setup t
Write Data Hold t
Load Data Pulse Width t
Reset Pulse Width t
Read Data Hold t
Read Data Setup t
Data to Hi-Z t
Chip Select to Data t
Chip Select Repetitive Pulse Width t
Load Setup in Double Buffer Mode t
Load Data Hold t

*All input control signals are specified with tR = tF = 2 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V.
Specifications subject to change without notice.

WCS

RCS

WS

WH

AS

AH

LS

LH

WDS

WDH

LDW

RESET

RDH

RDS

DZ

CSD

CSP

LDS

LDH

CL = 10 pF 80 100 ns
CL = 10 pF 80 100 ns

35 ns
130 ns
50 ns
0ns
50 ns
0ns
0ns
0ns
50 ns
0ns
35 ns
35 ns
0ns
0ns

20 ns
35 ns
0ns

REV. A

–5–

AD5582/AD5583

ABSOLUTE MAXIMUM RATINGS*

VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +18 V

to GND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +18 V

V

DD

V

to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –9 V

SS

to V

V

DD

to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +18 V

V

REF–

to V

V

REFH

. . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +18 V

REF+

. . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +18 V

REFL

DVDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 V

Logic Inputs to GND . . . . . . . . . . . V

to GND . . . . . . . . . . . . . . . . . VSS – 0.3 V, VDD + 0.3 V

V

OUT

I

Short Circuit to GND . . . . . . . . . . . . . . . . . . . . . . 24 mA

OUT

Thermal Resistance Junction to Ambient, 

– 0.3 V, VDD + 0.3 V

SS

. . . . . . 115∞C/W

JA

ORDERING GUIDE

Thermal Resistance Junction to Case, JC . . . . . . . . . . 42∞C/W

Maximum Junction Temperature (T

Package Power Dissipation = (T

Max) . . . . . . . . . . 150∞C

J

Max – TA)/

J

JA

Operating Temperature Range . . . . . . . . . . –40∞C to +125∞C

Storage Temperature Range . . . . . . . . . . . . –65∞C to +150∞C

Lead Temperature

RV-48 (Soldering, 60 secs) . . . . . . . . . . . . . . . . . . . . 300∞C

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

1

Resolution Temperature Package Package Container Top

Model (Bits) Range Description Option Quantity Marking

AD5582YRV-REEL112 –40∞C to +125∞CTSSOP-48 RV-48 2500 AD5582Y
AD5583YRV-REEL 10 –40∞C to +125∞CTSSOP-48 RV-48 2500 AD5583Y
AD5582YRV

1

12 –40∞C to +125∞CTSSOP-48 RV-48 39 AD5582Y

AD5583YRV 10 –40∞C to +125∞CTSSOP-48 RV-48 39 AD5583Y

NOTES

1

The AD5582 contains 4116 transistors. The die size measures 108 mil  144 mil.

2

First row marking is shown in the table above. Second row marking contains date code in YYWW format. Third row marking contains the lot number.

2

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD5582/AD5583 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

REV. A–6–