DACPORT Low Cost, Complete
BIT1
(MSB)
BIT8
(LSB)
GND
CS CE
CONTROL
INPUTS
DIGITAL INPUT DATA (BUS)
+
V
CC
l2L
CONTROL
LOGIC
l
2
L LATCHES
8-BIT VOLTAGE-SWITCHING
D-TO-A CONVERTER
MSB
LSB
OUTPUT
AMP
CONTROL
AMP
BAND-GAP
REFERENCE
GND
V
OUT
V
OUT
SENSE A
V
OUT
SENSE B
AD557
a
FEATURES
Complete 8-Bit DAC
Voltage Output—0 V to 2.56 V
Internal Precision Band-Gap Reference
Single-Supply Operation: 5 V (ⴞ10%)
Full Microprocessor Interface
Fast: 1 s Voltage Settling to ⴞ1/2 LSB
Low Power: 75 mW
No User Trims Required
Guaranteed Monotonic Over Temperature
MIN
to T
MAX
2
L), an extremely
All Errors Specified T
Small 16-Lead DIP or 20-Lead PLCC Package
Low Cost
PRODUCT DESCRIPTION
The AD557 DACPORT® is a complete voltage-output 8-bit
digital-to-analog converter, including output amplifier, full
microprocessor interface and precision voltage reference on a
single monolithic chip. No external components or trims are
required to interface, with full accuracy, an 8-bit data bus to an
analog system.
The low cost and versatility of the AD557 DACPORT are the
result of continued development in monolithic bipolar technologies.
The complete microprocessor interface and control logic is
implemented with integrated injection logic (I
dense and low-power logic structure that is process-compatible
with linear bipolar fabrication. The internal precision voltage
reference is the patented low-voltage band-gap circuit which
permits full-accuracy performance on a single 5 V power supply.
Thin-film silicon-chromium resistors provide the stability required
for guaranteed monotonic operation over the entire operating
temperature range, while laser-wafer trimming of these thin-film
resistors permits absolute calibration at the factory to within
± 2.5 LSB; thus, no user-trims for gain or offset are required. A
new circuit design provides voltage settling to ±1/2 LSB for a
full-scale step in 800 ns.
The AD557 is available in two package configurations. The
AD557JN is packaged in a 16-lead plastic, 0.3"-wide DIP. For
surface mount applications, the AD557JP is packaged in a
20-lead JEDEC-standard PLCC. Both versions are specified
over the operating temperature range of 0°C to 70°C.
DACPORT is a registered trademark of Analog Devices, Inc.
*Covered by U.S. Patent Nos. 3,887,863; 3,685,045; 4,323,795; other
patents pending.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
P-Compatible 8-Bit DAC
AD557*
FUNCTIONAL BLOCK DIAGRAM
PRODUCT HIGHLIGHTS
1. The 8-bit I2L input register and fully microprocessorcompatible control logic allow the AD557 to be directly
connected to 8- or 16-bit data buses and operated with standard control signals. The latch may be disabled for direct
DAC interfacing.
2. The laser-trimmed on-chip SiCr thin-film resistors are
calibrated for absolute accuracy and linearity at the factory.
Therefore, no user trims are necessary for full rated accuracy
over the operating temperature range.
3. The inclusion of a precision low-voltage band-gap reference
eliminates the need to specify and apply a separate reference
source.
4. The AD557 is designed and specified to operate from a
single 4.5 V to 5.5 V power supply.
5. Low digital input currents, 100 µA max, minimize bus loading.
Input thresholds are TTL/ low voltage CMOS compatible.
6. The single-chip, low power I
ently more reliable than hybrid multichip or conventional
single-chip bipolar designs.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703 © Analog Devices, Inc., 2001
2
L design of the AD557 is inher-
AD557–SPECIFICATIONS
(@ TA = 25ⴗC, VCC = 5 V unless otherwise noted)
Model Min Typ Max Unit
RESOLUTION 8 Bits
RELATIVE ACCURACY
0°C to 70°C ± 1/2 1 LSB
OUTPUT
ABSOLUTE MAXIMUM RATINGS*
VCC to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to 18 V
Digital Inputs (Pins 1–10) . . . . . . . . . . . . . . . . . . . 0 V to 7.0 V
. . . . . . . . . . . . . . . . . . . . . . . Indefinite Short to Ground
V
OUT
Ranges 0 to 2.56 V
Current Source 5 mA
Sink Internal Passive
Pull-Down to Ground
OUTPUT SETTLING TIME
FULL-SCALE ACCURACY
3
4
0.8 1.5 µs
2
@ 25°C ± 1.5 ±2.5 LSB
T
MIN
to T
MAX
± 2.5 ±4.0 LSB
ZERO ERROR
@ 25°C ± 1 LSB
T
to T
MIN
MAX
MONOTONICITY
T
to T
MIN
Guaranteed But Not Tested
MAX
5
± 3 LSB
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450 mW
Storage Temperature Range
N/P (Plastic) Packages . . . . . . . . . . . . . . . . –25°C to +100°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . 300°C
Thermal Resistance
Junction to Ambient/Junction to Case
N/P (Plastic) Packages . . . . . . . . . . . . . . . . . .140/55°C/W
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
DIGITAL INPUTS
T
to T
MIN
Input Current ⴞ100 µA
MAX
Data Inputs, Voltage
Bit On—Logic “1” 2.0 V
Bit On—Logic “0” 0 0.8 V
Control Inputs, Voltage
On—Logic “1” 2.0 V
(LSB) BIT 8
On—Logic “0” 0 0.8 V
Input Capacitance 4 pF
TIMING
6
tW Strobe Pulsewidth 225 ns
T
to T
MIN
MIN
MIN
to T
to T
MAX
MAX
MAX
tDH Data Hold Time 10 ns
T
tDS Data Setup Time 225 ns
T
300 ns
10 ns
300 ns
(MSB) BIT 1
POWER SUPPLY
Operating Voltage Range (VCC)
2.56 Volt Range 4.5 5.5 V
Current (ICC)1525mA
Rejection Ratio 0.03 %/%
POWER DISSIPATION, VCC = 5 V 75 125 mW
OPERATING TEMPERATURE RANGE 0 70 °C
NOTES
1
Relative Accuracy is defined as the deviation of the code transition points from the
ideal transfer point on a straight line from the offset to the full scale of the device.
See “Measuring Offset Error” on the AD558 data sheet.
2
Passive pull-down resistance is 2 kΩ.
3
Settling time is specified for a positive-going full-scale step to ± 1/2 LSB. Negativegoing steps to zero are slower, but can be improved with an external pull-down.
4
The full-scale output voltage is 2.55 V and is guaranteed with a 5 V supply.
5
A monotonic converter has a maximum differential linearity error of ± 1 LSB.
6
See Figure 7.
Specifications shown in boldface are tested on all production units at electrical test.
Specifications subject to change without notice.
ORDERING GUIDE
BIT 6
BIT 5
BIT 4
BIT 3
NC = NO CONNECT
Momentary Short to V
PIN CONFIGURATIONS
DIP
16
V
OUT
15
V
OUT
14
V
OUT
13
GND
12
GNDBIT 4
+V
11
CC
10
CS
9
CE
BIT 7
BIT 6
BIT 5
BIT 3
BIT 2
1
2
3
AD557
4
TOP VIEW
(Not to Scale)
5
6
7
8
PLCC
SENSE A
OUT
OUT
V
NC
20 19123
PIN 1
IDENTIFIER
13
CE
NC
V
18
17
16
15
14
CS
NC
4
5
6
7
8
BIT 7
BIT 8 (LSB)
AD557
TOP VIEW
(Not to Scale)
91011 12
BIT 2
(MSB) BIT 1
SENSE A
SENSE B
V
SENSE B
OUT
GND
NC
GND
+V
CC
CC
Temperature Package Package
Model Range Description Option
AD557JN 0°C to 70°C Plastic DIP N-16
AD557JP 0°C to 70°C Plastic Leaded Chip Carrier P-20A
–2–
REV. B
AD557
CIRCUIT DESCRIPTION
The AD557 consists of four major functional blocks fabricated
on a single monolithic chip (see Figure 1). The main D/A converter section uses eight equally weighted laser-trimmed current
sources switched into a silicon-chromium thin-film R/2R resistor
ladder network to give a direct but unbuffered 0 mV to 400 mV
output range. The transistors that form the DAC switches are
PNPs; this allows direct positive-voltage logic interface and a
zero-based output range.
DIGITAL INPUT DATA (BUS)
BIT1
(MSB)
8-BIT VOLTAGE-SWITCHING
D-TO-A CONVERTER
AMP
l2L LATCHES
BIT8
(LSB)
+
V
CC
GND
OUTPUT
AMP
V
V
OUT
OUT
GND
V
OUT
SENSE A
SENSE B
BAND-GAP
REFERENCE
CONTROL
INPUTS
CE
CS
l2L
CONTROL
LOGIC
CONTROL
Figure 1. Functional Block Diagram
The high-speed output buffer amplifier is operated in the noninverting mode with gain determined by the user-connections
at the output range select pin. The gain-setting application
resistors are thin film laser trimmed to match and track the
DAC resistors and to assure precise initial calibration of the output range, 0 V to 2.56 V. The amplifier output stage is an
NPN transistor with passive pull-down for zero-based output
capability with a single power supply.
The internal precision voltage reference is of the patented
band-gap type. This design produces a reference voltage of
1.2 V and thus, unlike 6.3 V temperature-compensated Zeners,
may be operated from a single, low-voltage logic power supply.
The microprocessor interface logic consists of an 8-bit data
latch and control circuitry. Low power, small geometry and high
speed are advantages of the I
2
L is bipolar process compatible so that the performance of the
I
2
L design as applied to this section.
analog sections need not be compromised to provide on-chip
logic capabilities. The control logic allows the latches to be
operated from a decoded microprocessor address and write signal. If the application does not involve a µP or data bus, wiring
CS and CE to ground renders the latches “transparent” for
direct DAC access.
Digital Input Code Output
Binary Hexadecimal Decimal Voltage
0000 0000 00 0 0
0000 0001 01 1 0.010 V
0000 0010 02 2 0.020 V
0000 1111 0F 15 0.150 V
0001 0000 10 16 0.160 V
0111 1111 7F 127 1.270 V
1000 0000 80 128 1.280 V
1100 0000 C0 192 1.920 V
1111 1111 FF 255 2.55 V
CONNECTING THE AD557
The AD557 has been configured for low cost and ease of application. All reference, output amplifier and logic connections are
made internally. In addition, all calibration trims are performed
at the factory assuring specified accuracy without user trims.
The only connection decision to be made by the user is whether
the output range desired is unipolar or bipolar. Clean circuit
board layout is facilitated by isolating all digital bit inputs on
one side of the package; analog outputs are on the opposite side.
UNIPOLAR 0 V TO 2.56 V OUTPUT RANGE
Figure 2 shows the configuration for the 0 V to 2.56 V fullscale output range. Because of its precise factory calibration, the
AD557 is intended to be operated without user trims for gain
and offset; therefore, no provisions have been made for such user
trims. If a small increase in scale is required, however, it may be
accomplished by slightly altering the effective gain of the output
buffer. A resistor in series with V
SENSE will increase the
OUT
output range. Note that decreasing the scale by putting a resistor
in series with GND will not work properly due to the codedependent currents in GND. Adjusting offset by injecting dc at
GND is not recommended for the same reason.
OUTPUT
AMP
16
V
OUT
V
SENSE A
15
OUT
14
V
SENSE B
OUT
GND
13
Figure 2. 0 V to 2.56 V Output Range
BIPOLAR –1.28 V TO +1.28 V OUTPUT RANGE
The AD557 was designed for operation from a single power
supply and is thus capable of providing only a unipolar 0 V to
2.56 V output range. If a negative supply is available, bipolar
output ranges may be achieved by suitable output offsetting and
scaling. Figure 3 shows how a ± 1.28 V output range may be
achieved when a –5 V power supply is available. The offset is
provided by the AD589 precision 1.2 V reference which will
operate from a 5 V supply. The AD711 output amplifier can
provide the necessary ±1.28 V output swing from ±5 V supplies.
Coding is complementary offset binary.
5k⍀
+5V
AD711
1.5k⍀
–5V
INPUT CODE
00000000
10000000
11111111
0.01F
0.01F
V
OUT
+1.28V
0V
–1.27V
V
O
+1.28 TO
–1.27
AD557
V
IN
AD589
0.01F
V
= 0V TO 2.56V
OUT
BIPOLAR
OFFSET
ADJUST
–1.2V
4.7k⍀
–5V
5k⍀
500⍀
4.53k⍀
Figure 3. Bipolar Operation of AD557 from ±5 V Supplies
REV. B
–3–
AD557
APPLICATIONS
Grounding and Bypassing
All precision converter products require careful application of
good grounding practices to maintain full rated performance.
Because the AD557 is intended for application in microcomputer systems where digital noise is prevalent, special care must
be taken to assure that its inherent precision is realized.
The AD557 has two ground (common) pins; this minimizes
ground drops and noise in the analog signal path. Figure 4
shows how the ground connections should be made.
It is often advisable to maintain separate analog and digital
grounds throughout a complete system, tying them common in
one place only. If the common tie-point is remote and accidental disconnection of that one common tie-point occurs due to
card removal with power on, a large differential voltage between
the two commons could develop. To protect devices that interface to both digital and analog parts of the system, such as the
AD557, it is recommended that common ground tie-points
should be provided at each such device. If only one system
ground can be connected directly to the AD557, it is recommended that analog common be selected.
OUTPUT
AMP
V
OUT
16
V
SENSE A
OUT
15
SENSE B
V
OUT
14
GND
13
12
GND
11
0.1F
+V
CC
R
L
TO SYSTEM GND
TO SYSTEM GND
(SEE TEXT)
TO SYSTEM V
CC
Figure 4. Recommended Grounding and Bypassing
Using a “False” Ground
Many applications, such as disk drives, require servo control
voltages that swing on either side of a “false” ground. This
ground is usually created by dividing the 12 V supply equally
and calling the midpoint voltage “ground.”
Figure 5 shows an easy and inexpensive way to implement this.
The AD586 is used to provide a stable 5 V reference from the
system’s 12 V supply. The op amp shown likewise operates from
a single (12 V) supply available in the system. The resulting output at the V
of 5 V. AD557 input code vs. V
node is ± 2.5 V around the “false” ground point
OUT
AD557
100k⍀
100k⍀
is shown in Figure 6.
OUT
200k⍀
1/4 LM324
100k⍀
“FALSE”
GROUND
6
AD586
5V
4
V
OUT
12V
2
V
IN
Figure 5. Level Shifting the AD557 Output Around a
“False” Ground
Timing and Control
The AD557 has data input latches that simplify interface to 8and 16-bit data buses. These latches are controlled by Chip
Enable (CE) and Chip Select (CS) inputs. CE and CS are internally “NORed” so that the latches transmit input data to the
DAC section when both CE and CS are at Logic “0.” If the
application does not involve a data bus, a “00” condition allows
for direct operation of the DAC. When either CE or CS go to
Logic “1,” the input data is latched into the registers and held
until both CE and CS return to “0.” (Unused CE or CS inputs
should be tied to ground.) The truth table is given in Table I.
The logic function is also shown in Figure 6.
V
OUT
7.5
5.0
2.5
00H 80H FFH
AD557 INPUT CODE
Figure 6. AD557 Input Code vs. Level Shifted Output in a
“False” Ground Configuration
Table I. AD557 Control Logic Truth Table
Input Data CE CS DAC Data Condition
0 0 0 0 “Transparent”
1 0 0 1 “Transparent”
0 g 0 0 Latching
1 g 0 1 Latching
00g 0 Latching
10g 1 Latching
X 1 X Previous Data Latched
X X 1 Previous Data Latched
NOTES
X = Does not matter
g
= Logic Threshold at Positive-Going Transition
Latch
In a level-triggered latch such as that used in the AD557, there
is an interaction between the data setup and hold times and
the width of the enable pulse. In an effort to reduce the time
required to test all possible combinations in production, the
AD557 is tested with t
T
MIN
and T
MAX
, with t
= tW = 225 ns at 25°C and 300 ns at
DS
= 10 ns at all temperatures. Failure to
DH
comply with these specifications may result in data not being
latched properly.
Figure 7 shows the timing for the data and control signals, CE
and CS are identical in timing as well as in function.
t
DH
DATA
0.8V
INPUTS
CS OR CE
V OUTPUT
0.8V
DAC
t
= STROBE PULSEWIDTH = 225ns min
W
t
= DATA HOLD TIME = 10ns min
DH
t
= DATA SETUP TIME = 225ns min
DS
t
= DAC SETTLING TIME TO ⴞ 1/2 LSB
SETTLING
t
DS
t
W
t
SETTLING
2.0V
2.0V
1/2 LSB
Figure 7. AD557 Timing
REV. B–4–
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
N-16 (Plastic) Package
0.87 (22.1) MAX
0.25
0.31
(6.35)
(7.87)
AD557
0.18
(4.57)
0.018
(0.46)
0.045 ⴞ 0.003
(1.143 ⴞ 0.076)
0.020
(0.51)
MAX
0.033
(0.84)
0.1
(2.54)
P-20A (PLCC) Package
0.02 (0.51)
MAX
0.390 ⴞ 0.005
(9.906 ⴞ 0.125)
0.353 ⴞ 0.003
(8.966 ⴞ 0.076)
NO.1 PIN
IDENTIFIER
TOP
VIEW
0.050
(1.27)
SQ
SQ
0.035
(0.59)
0.125
(3.18) MIN
0.173 ⴞ 0.008
(4.385 ⴞ 0.185)
0.060 (1.53)
MIN
0.011
(0.28)
0.3
(7.62)
0.105 ⴞ 0.015
(2.665 ⴞ 0.375)
0.020 (0.51) MIN
0.035 ⴞ 0.01
(0.89 ⴞ 0.25)
0.029 ⴞ 0.003
(0.737 ⴞ 0.076)
0.017 ⴞ 0.004
(0.432 ⴞ 0.101)
0.025 (0.64) MIN
0.18
(4.57)
MAX
REV. B
–5–
AD557–Revision History
Location Page
Data sheet changed from REV. A to REV. B.
Changes to MONOTONICITY section of spec. page . . . . . . . . . 2
C00512a–0–1/01 (rev. B)
–6–
PRINTED IN U.S.A.
REV. B
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