Analog Devices AD53040 b Datasheet

Ultrahigh Speed Pin Driver

a

FEATURES
500 MHz Driver Operation
Driver Inhibit Function
100 ps Edge Matching
Guaranteed Industry Specifications

50 ⍀ Output Impedance
>1.5 V/ns Slew Rate

Variable Output Voltages for ECL, TTL and CMOS
High Speed Differential Inputs for Maximum Flexibility
Ultrasmall 20-Lead SOP Package with Built-In Heat Sink

APPLICATIONS
Automatic Test Equipment

Semiconductor Test Systems

Board Test Systems
Instrumentation and Characterization Equipment

PRODUCT DESCRIPTION

The AD53040 is a complete high speed pin driver designed for
use in digital or mixed-signal test systems. Combining a high
speed monolithic process with a unique surface mount package,
this product attains superb electrical performance while preserv­ing optimum packaging densities and long-term reliability in an
ultrasmall 20-lead, SOP package with built-in heat sink.

Featuring unity gain programmable output levels of –3 V to
+8 V, with output swing capability of less than 100 mV to 9 V,
the AD53040 is designed to stimulate ECL, TTL and CMOS
logic families. The 500 MHz data rate capacity and matched
output impedance allows for real-time stimulation of these
digital logic families. To test I/O devices, the pin driver can
be switched into a high impedance state (Inhibit Mode), electri­cally removing the driver from the path. The pin driver leakage
current inhibit is typically 100 nA and output charge transfer
entering inhibit is typically less than 20 pC.

with Inhibit Mode

AD53040

FUNCTIONAL BLOCK DIAGRAM

V

V

CCVEE

CC

V

H

DATA

DATA

INH

INH

V

L

DRIVER

AD53040

GND

GND GND GND GND

The AD53040 transition from HI/LO or to inhibit is controlled
through the data and inhibit inputs. The input circuitry uses
high speed differential inputs with a common-mode range of

±3 V. This allows for direct interface to precision differential

ECL timing or the simplicity of stimulating the pin driver from a
single ended TTL or CMOS logic source. The analog logic HI/LO

inputs are equally easy to interface. Typically requiring 10 µA of

bias current, the AD53040 can be directly coupled to the
output of a digital-to-analog converter.

The AD53040 is available in a 20-lead, SOP package with a
built-in heat sink and is specified to operate over the ambient

commercial temperature range of –25°C to +85°C.

50V

1.0mA/K

V

EE

39nF 39nF

V

HDCPL

V

OUT

V

LDCPL

TV

CC

THERM

REV. B

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 1999

AD53040–SPECIFICATIONS

(All specifications are at TJ = +85ⴗC ⴞ 5ⴗC, +VS = +12 V ⴞ 3%, –VS = –7 V ⴞ
3% unless otherwise noted. All temperature coefficients are measured at TJ = +75ⴗC–95ⴗC). (A 39 nF capacitor must be connected between
VCC and V

Parameter Min Typ Max Units Test Conditions

DIFFERENTIAL INPUT CHARACTERISTICS

Input Swing (Data to DATA, INH to INH) ECL 2 Volts

Max (DATA, DATA) to Min (INH, INH)
Max (INH, INH) to Min (Data, DATA) 2 Volts
Bias Current ±10 µAV

REFERENCE INPUTS

Bias Currents –50 +50 µAV

OUTPUT CHARACTERISTICS

Logic High Range –2 +8 Volts DATA = H, VH = –2 V to +8 V

Logic Low Range –3 +5 Volts DATA = L, V
Amplitude (V

Absolute Accuracy

V
V
V
V

Offset TC, V

Output Resistance 45 47 49 Ω DATA = H, V

Output Leakage –1.0 +1.0 µAV

Dynamic Current Limit 150 mA C

Static Current Limit ±65 mA Output to –3 V, V

PSRR, Drive Mode 35 dB VS = V

DYNAMIC PERFORMANCE, DRIVE

(VH and VL)

Propagation Delay Time 1.5 ns Measured at 50%, V

Propagation Delay TC 2 ps/°C Measured at 50%, V

Delay Matching, Edge to Edge 100 ps Measured at 50%, V

Rise and Fall Time

Rise and Fall Time TC

Overshoot, Undershoot and Preshoot ±(1% +50 mV) % of Step + mV a. V

Settling Time

and between VEE and V

HDCPL

and VL) 0.1 9 Volts VL = –0.05 V, VH = +0.05 V and

H

Offset –100 +100 mV DATA = H, VH = –2 V to +8 V, VL = –3 V

H

Gain + Linearity Error ±0.3 ±5% of V

H

Offset –100 +100 mV DATA = L, VL = –3 V to +5 V, VH = +6 V

L

Gain + Linearity Error ±0.3 ±5% of V

L

or V

H

L

1 V Swing 0.8 ns Measured 20%–80%, V
3 V Swing 1.7 ns Measured 10%–90%, V
5 V Swing 2.4 ns Measured 10%–90%, V

1 V Swing ±1 ps/°C Measured 20%–80%, V
3 V Swing ±2 ps/°C Measured 10%–90%, V
5 V Swing ±3 ps/°C Measured 10%–90%, V

to 15 mV 40 ns V

to 4 mV 8 µsV

Delay Change vs. Pulsewidth 50 ps V

LDCPL

.)

= –2 V, 0.0 V

IN

, VH = 5 V

L

V

= –3 V (VH = –2 V to +6 V)

L

V

= –1 V (VH = +6 V to +8 V)

L

V

= –2 V, VH = +7 V

L

+ mV DATA = H, VH = –2 V to +8 V, VL = –3 V

H

+ mV DATA = L, VL = –3 V to +5 V, VH = +6 V

0.5 mV/°CV

L

, VH = 0 V, +5 V and –3 V, 0 V

L

= 30 mA

I

OUT

= –3 V to +8 V

OUT

= 39 nF, VH = +7 V, VL = –2 V

BYP

DATA = H and Output to +8 V, V
V

= –3 V, DATA = L

L

V

= –400 mV

L

V

= –400 mV

L

V

= –400 mV

L

, VH = 0.0 V, 1.0 V

L

b. V

, VH = 0.0 V, 3.0 V

L

, VH = 0.0 V, 5.0 V

c. V

L

= 0 V, VH = 0.5 V

L

= 0 V, VH = 0.5 V

L

= 0 V, VH = 2 V,

L

= –3 V to +5 V, VH = +6 V

L

= +3 V, VL = 0 V,

H

= +8 V, VL = –1 V,

H

± 3%

S

= +400 mV,

H

= +400 mV,

H

= +400 mV,

H

L

L

L

L

L

L

= +6 V,

H

= 0 V, VH = 1 V
= 0 V, VH = 3 V
= 0 V, VH = 5 V

= 0 V, VH = 1 V
= 0 V, VH = 3 V
= 0 V, VH = 5 V

Pulsewidth = 2.5 ns/7.5 ns, 30 ns/100 ns

–2–

REV. B

AD53040

WARNING!

ESD SENSITIVE DEVICE

Parameter Min Typ Max Units Test Conditions

DYNAMIC PERFORMANCE, DRIVE

(VH and VL) (Continued)

Minimum Pulsewidth

3 V Swing 1.7 ns 4.0 ns Input, 10%/90% Output,

V

= 0 V, VH = 3 V

5 V Swing 2.6 ns 6.0 ns Input, 10%/90% Output,

Toggle Rate 500 MHz V

DYNAMIC PERFORMANCE, INHIBIT

Delay Time, Active to Inhibit 2 5 ns Measured at 50%, VH = +2 V,

Delay Time, Inhibit to Active 2 5 ns Measured at 50%, V

I/O Spike <200 mV, p-p V
Output Capacitance 5 pF Driver Inhibited

POWER SUPPLIES

Total Supply Range 19 V
Positive Supply +12 V
Negative Supply –7 V
Positive Supply Current 75 mA
Negative Supply Current 75 mA
Total Power Dissipation 1.15 1.43 W

Temperature Sensor Gain Factor 1.0 µA/K R

NOTES
Connecting or shorting the decoupling capacitors to ground will result in the destruction of the device.

Specifications subject to change without notice.

L

= 0 V, VH = 5 V

V

L

= –1.8 V, VH = –0.8 V,

L

V

> 600 mV p-p

OUT

V

= –2 V

L

V

= –2 V

L

= 0 V, VL = 0 V

H

= 10 K, V

LOAD

SOURCE

= +2 V,

H

= +12 V

ABSOLUTE MAXIMUM RATINGS

1

Power Supply Voltage

+V

to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +13 V

S

to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –8 V

–V

S

+V

to –VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +20 V

S

Inputs

DATA, DATA, INH, INH . . . . . . . . . . . . . . . . +5 V, –3 V

DATA to DATA, INH to INH . . . . . . . . . . . . . . . . . . ±3 V

, VL to GND . . . . . . . . . . . . . . . . . . . . . . . . . +9 V, –4 V

V

H

to VL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +11 V, 0 V

V

H

Outputs

V

Short Circuit Duration . . . . . . . . . . . . . . . .Indefinite

OUT

V

Range in Inhibit Mode

OUT

V
V

. . . . . Do Not Connect Except for Capacitor to V

HDCPL

. . . . . Do Not Connect Except for Capacitor to V

LDCPL

THERM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +13 V, 0 V

Environmental

Operating Temperature (Junction) . . . . . . . . . . . . . .+175°C

Storage Temperature . . . . . . . . . . . . . . . . –65°C to +150°C

Lead Temperature (Soldering, 10 sec)

3

. . . . . . . . . . +260°C

NOTES

1

Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Absolute maximum limits apply
individually, not in combination. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.

2

Output short circuit protection is guaranteed as long as proper heat sinking is

employed to ensure compliance with the operating temperature limits.

3

To ensure lead coplanarity (±0.002 inches) and solderability, handling with bare

hands should be avoided and the device should be stored in environments at 24°C
± 5°C (75°F ± 10°F) with relative humidity not to exceed 65%.

2

ORDERING GUIDE

CC

EE

Package Quantity Per Package

Model Description Shipping Container Option

AD53040KRP 20-Lead Power SOIC Tube, 38 Pieces RP-20

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD53040 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

Shipment Method,

REV. B

–3–

AD53040

PIN FUNCTION DESCRIPTIONS

Pin Pin
Name Number Pin Functional Description

V

CC

1, 2 Positive Power Supply. Both pins

should be connected to minimize in­ductance and allow maximum speed of
operation. V

should be decoupled to

CC

GND with a low inductance 0.1 µF

capacitor.

V

EE

8, 9 Negative Power Supply. Both pins

should be connected to keep the induc­tance down and allow maximum speed
of operation. V

should be decoupled

EE

to GND with a low inductance 0.1 µF

capacitor.

GND 4, 6, 14,

16, 17 Device Ground. These pins should be

connected to the circuit board’s ground
plane at the pins.

V

L

15 Analog Input that sets the voltage level

of a Logic 0 of the driver. Determines
the driver output for DATA > DATA.

V

H

18 Analog input that sets the voltage level

of a Logic 1 of the driver. Determines
the driver output for DATA > DATA.

V

OUT

5 The Driver Output. The nominal out-

put impedance is 50 Ω.

V

HDCPL

3 Internal supply decoupling for the

output stage. This pin is connected

through a 39 nF minimum

to V

CC

capacitors.

V

LDCPL

7 Internal supply decoupling for the

output stage. This pin is connected
to V

through a 39 nF minimum

EE

capacitors.

INH, INH 10, 11 ECL compatible input that control the

high impedance state of the driver.
When INH > INH, the driver goes into
a high impedance state.

DATA, 13, 12 ECL compatible inputs that determines
DATA the high and low state of the driver.

Driver output is high for DATA >
DATA.

TV

CC

19 Temperature Sensor Start-Up Pin. This

pin should be connected to V

CC

.

THERM 20 Temperature Sensor Output Pin. A

resistor (10K) should be connected
between THERM and V

. The ap-

CC

proximate die temperature can be de­termined by measuring the current
through the resistor. The typical scale

factor is 1 µA/K.

PIN CONFIGURATION

V

HDCPL

V

LDCPL

V
V

GND

V

OUT

GND

V
V

INH

CC

CC

EE

EE

1
2
3
4
5
6
7
8
9

10

AD53040

TOP VIEW

(Not to Scale)

COPPER
SLUG UP

20
19
18
17
16
15
14
13
12
11

THERM
TV

CC

V

H

GND
GND
V

L

GND
DATA

DATA

INH

Table I. Pin Driver Truth Table

Output

DATA DATA INH INH State

0101V
1001V

L

H

0110Hi-Z
1010Hi-Z

Table II. Package Thermal Characteristics

Air Flow, FM ␪JC, ⴗC/W ␪JA, ⴗC/W

0450
50 4 49
400 4 34

–4–

REV. B

AD53040

p

APPLICATION INFORMATION
Power Supply Distribution, Bypassing and Sequencing

The AD53040 draws substantial transient currents from its
power supplies when switching between states and careful design
of the power distribution and bypassing is key to obtaining speci­fied performance. Supplies should be distributed using broad,
low inductance traces or (preferably) planes in a multilayered
board with a dedicated ground-plane layer. All of the device’s
power supply pins should be used to minimize the internal in­ductance presented by the part’s bond wires. Each supply must

be bypassed to ground with at least one 0.1 µF capacitor; chip-

style capacitors are preferable as they minimize inductance. One

or more 10 µF (or greater) Tantalum capacitors per board are

also advisable to provide additional local energy storage.

The AD53040’s current-limit circuitry also requires external
bypass capacitors. Figure 1 shows a simplified schematic of the
positive current-limit circuit. Excessive collector current in out-

put transistor Q49 creates a voltage drop across the 10 Ω resis-

tor, which turns on PNP transistor Q48. Q48 diverts the rising­edge slew current, shutting down the current mirror and remov­ing the output stage’s base drive. The V

pin should be

HDCPL

bypassed to the positive supply with a 0.039 µF capacitor, while

the V

pin (not shown) requires a similar capacitor to the

LDCPL

negative supply- these capacitors ensure that the AD53040
doesn’t current limit during normal output transitions up the its
full 9 V rated step size. Both capacitors must have minimum­length connections to the AD53040. Here again, chip capacitors
are ideal.

VPOS

10V610%

V

HDCPL

V

H

RISING-EDGE SLEW

CONTROL CURRENT

LEVEL-SHIFTED

LOGIC DRIVE

Q48

VNEG

Q49

Several points about the current-limit circuitry should be noted.
First, the limiting currents are not tightly controlled, as they are
functions of both absolute transistor V

and junction tem-

BES

perature; higher dc output current is available at lower junction
temperatures. Second, it is essential to connect the V
capacitor to the positive supply (and the V

LDCPL

HDCPL

capacitor to
the negative supply)—failure to do so causes considerable ther­mal stress in the current-limiting resistor(s) during normal sup­ply sequencing and may ultimately cause them to fail, rendering
the part nonfunctional. Finally, the AD53040 may appear to
function normally for small output steps (less than 3 V or so) if
one or both of these capacitors is absent, but it will exhibit
excessive rise or fall times for steps of larger amplitude.

The AD53040 does not require special power-supply sequencing.
However, good design practice dictates that digital and analog
control signals not be applied to the part before the supplies are
stable. Violating this guideline will not normally destroy the
part, but the active inputs can draw considerable current until
the main supplies are applied.

Digital Input Range Restrictions

Total range amongst all digital signals (DATA, DATA, INH,
and INH) has to be less than or equal to 2 V to meet specified
timing. The device will function above 2 V with reduced perfor­mance up to the absolute maximum limit. This performance
degradation might not be noticed in all modes of operation. Of
all the six possible transitions (V
INH v V

, VL v INH and INH v VL), there may be only one

H

v VL, VL v VH, VH v INH,

H

that would show a degradation, usually in delay time. Taken to
the extreme, the driver may fail to achieve a proper output volt­age, output impedance or may fail to fully inhibit.

An example of a scenario that would not work for the AD53040
is if the part is driven using 5 V single-ended CMOS. One pin of
each differential input would be tied to a +2.5 V reference level
and the logic voltages would be applied to the other. This would

meet the Absolute Maximum Rating of ±3 V because the max
differential is ±2.5 V. It is however possible, for example for

0.0 V to be applied to the INH input and +5 V to be applied to
the DATA input. This 5 V difference far exceeds the 2.0 V
limitation given above. Even using 3 V CMOS or TTL the
difference between logic high and logic low is greater than or
equal to 3 V which will not properly work. The only solution is
to use resistive dividers or equivalent to reduce the voltage levels.

OUT

Q50

Figure 1. Simplified Schematic of the AD53040 Output
Stage and Positive Current Limit Circuitry

REV. B

–5–

5.12V

550mV

/DIV

–380mV

66.25ns 500

Figure 2. 5 V Output Swing

s/DIV 71.25ns

AD53040

DATA

J1

SMB

50V

R6
50V

C12

0.01mF

INH

J2

SMB

50V

R5
50V

C13

0.01mF

NOTE:

1. 50V TERMINATION TO BE AS CLOSE TO RECEIVER
AS POSSIBLE. (END OF TRACE MARKED BY *). THROUGH
SMA CONNECTS BETWEEN MC10EL16 OUTPUTS AND DUT.

2. NO VIAS ALLOWED ON VOUT LINE.

3. SMA ON V

IMPEDANCE MATCH.

4. ONE DIMENSION OF BOARD TO BE 4-1/2 INCHES.

5. DUT PACKAGE IS TO BE CENTERED ON BOARD.

6. ALL RESISTORS AND NONELECTROLYTIC CAPS ARE

0805-SIZE SURFACE MOUNT.

7. SEE DATA SHEET FOR HIDDEN POWER AND GROUND PINS
ON LOGIC GATES.

V

LOW

V

50V

C14

0.1mF

C15

0.1mF

J4

J5

P1

DB15

SMB

J3

SMB

J6

SMB

SMB

1
9
2
10
3
11
4
12
5
13
6
14
7
15
8

50V

50V

50V

+

C4
1mFC71mFC61mF

JP1

1

TP

JP2

1

TP

JP3

1

TP

U1

MC10EL16

1

8

2

7

3

2
3

6

5

–5.2V

–2V

U2

MC10EL16

6
–5.2V

–2V

R4
50VR350V

R1
50VR250V

C21

0.1mF

1

8

7

5

C22

0.1mF
GND

+V

–V

S

S

0.1mF

C1

HIGH

C5
1mF

8. ALL 100nF BYPASS CAPACITORS TO BE LOCATED CLOSE

TO PACKAGE.

9. PCB IS TO BE 4-LAYER WITH POWER GND ( ) AND –2V AS

INNER PLANES.

C2

0.1mF

THERM

TV

CC

TH
VH
VL

AD53040

DATA

INH

PWR

GND

V

LOW

–2V
V

HIGH

–V

S

THERM

–5.2V

+V

S

C8

0.1mF

TO BE MOUNTED ON ITS SIDE FOR BEST

OUT

+V

S

C19

0.1mF

R7

50V

+V

–V

S

S

V

C9

0.1mF

EE

C16

0.039mF

IL+

IL–

C10

0.1mF

G2H

G2L

V

OUT

–5.2V

C17

0.039mF

C3

0.1mF

C11

0.1mF

HQG1

U3

–V

S

50V

J8

SIDESMB

J7

SIDESMB

GND

TEST_LD

V

OUT

C18
5pF

V

CC

Figure 3. Evaluation Board Schematic

–6–

REV. B

OUTLINE DIMENSIONS

SEATING
PLANE

0.0118 (0.30)

0.0040 (0.10)

0.0201 (0.51)

0.0130 (0.33)

0.1043 (2.65)

0.0926 (2.35)

0.0500
(1.27)

BSC

STANDOFF

0.0500 (1.27)

0.0057 (0.40)

8°
0°

0.0295 (0.75)

0.0098 (0.25)

x 45°

0.5118 (13.00)

0.4961 (12.60)

0.4193 (10.65)

0.3937 (10.00)

0.2992 (7.60)

0.2914 (7.40)

PIN 1

0.3340 (8.61)

0.3287 (8.35)

0.1890 (4.80)

0.1791 (4.55)

20

1

11

10

HEAT

SINK

Dimensions shown in inches and (mm).

20-Lead Thermally Enhanced Small Outline Package (PSOP)

(RP-20)

AD53040

C3003b–0–11/99

REV. B

PRINTED IN U.S.A.

–7–