Spartan-6 FPGA
Power Management
User Guide
UG394 (v1.1) September 4, 2012
Notice of Disclaimer
The information disclosed to you hereunder (the “Materials”) is provided solely for the selection and use of Xilinx products. To the maximum
extent permitted by applicable law: (1) Materials are made available "AS IS" and with all faults, Xilinx hereby DISCLAIMS ALL
WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether
in contract or tort, including negligence, or under any other theory of liability) for any loss or damage of any kind or nature related to, arising
under, or in connection with, the Materials (including your use of the Materials), including for any direct, indirect, special, incidental, or
consequential loss or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any action
brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same.
Xilinx assumes no obligation to correct any errors contained in the Materials or to notify you of updates to the Materials or to product
specifications. You may not reproduce, modify, distribute, or publicly display the Materials without prior written consent. Certain products are
subject to the terms and conditions of the Limited Warranties which can be viewed at http://www.xilinx.com/warranty.htm
subject to warranty and support terms contained in a license issued to you by Xilinx. Xilinx products are not designed or intended to be
fail-safe or for use in any application requiring fail-safe performance; you assume sole risk and liability for use of Xilinx products in Critical
Applications: http://www.xilinx.com/warranty.htm#critapps
© Copyright 2010–2012 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Zynq, Vivado, and other designated brands
included herein are trademarks of Xilinx in the United States and other countries. All other trademarks are the property of their respective
owners.
.
; IP cores may be
Revision History
The following table shows the revision history for this document.
Date Version Revision
05/18/10 1.0 Initial Xilinx release.
09/04/12 1.1 • Updated Additional Documentation section.
•In Chapter 1, deleted first and last paragraphs from Differential I/O Standards.
Eliminated statements pertaining to differential drivers and receivers disabled in
suspend mode. Reinforced the directive that the SUSPEND pin must be tied to GND
when the suspend feature is disabled by adding “or High” to second paragraph of
SUSPEND Pin. Changed “X” to “0” in first row of Tab le 1- 5. Changed the AWAKE
output pin power supply to V
Pin Behavior when Suspend Feature is Enabled. Added “for Recommended
Operating Conditions” to data sheet power levels referenced in FPGA Voltage
Requirements During Suspend Mode.
•In Chapter 2, changed “used” to “being programmed” in description section, last row,
of Ta bl e 2 -1 . Added V
±5%” specification from first paragraph in VCCAUX Specifications and third
“
CCAUX
paragraph of VCCO.
•In Chapter 3, removed “approximately one speed grade slower (~15%)” from first
paragraph in Introduction. Added a UG382 reference to Designing Using the
Lower-Power Spartan-6 LX Devices. Added V
paragraphs to Lower-Power Spartan-6 LX Device Specifications.
•In Chapter 5, removed “50%” specification from second paragraph in Saving Power.
Also remove last sentence referencing techniques for past FPGA families from last
paragraph in ISE Design Suite Power Optimization.
power rail on bank 1 in third paragraph of AWAK E
CCO
setting restriction paragraphs to VCCAUX. Removed
and IODELAY2 specification
CCAUX
Spartan-6 FPGA Power Management www.xilinx.com UG394 (v1.1) September 4, 2012
Table of Contents
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Preface: About This Guide
Guide Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Additional Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Additional Support Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Chapter 1: Power Management With Suspend Mode
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Differences from Extended Spartan-3A Family. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Multi-Pin Wake-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Suspend Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Suspend Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Design Steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Entering Suspend Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Exiting Suspend Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
PROGRAM_B Programming Pin Always Overrides Suspend Mode . . . . . . . . . . . . . 14
Enable the Suspend Feature and Glitch Filtering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
User Constraints File Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Bitstream Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Define the Multi-Pin Wake-Up Feature and Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Define the I/O Behavior During Suspend Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Single-Ended I/O Standards. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Differential I/O Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
SUSPEND Attribute. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
UCF Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Design Maintained during Suspend Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Design Requirements to Maintain Application Data . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Suspend Mode Wake-Up Timing Controls. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Wake-Up Timing Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Switch Outputs from Suspend to Normal Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Release Write Protect on Clocked Primitives. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Dedicated Configuration Pins Unaffected During Suspend Mode. . . . . . . . . . . . 19
JTAG Operations Allowed During Suspend Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
SUSPEND Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
SUSPEND Input Glitch Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
SUSPEND_SYNC Primitive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
AWAKE Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
General Behavior (Suspend Feature Disabled) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
AWAKE Pin Behavior when Suspend Feature is Enabled . . . . . . . . . . . . . . . . . . . . . . 21
Controlling Wake-Up from an External Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Synchronizing Wake-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Spartan-6 FPGA Power Management www.xilinx.com 3
UG394 (v1.1) September 4, 2012
Post-Configuration CRC Limitations When Using Suspend Mode. . . . . . . . . . . . 22
FPGA Voltage Requirements During Suspend Mode . . . . . . . . . . . . . . . . . . . . . . . . 24
Memory Controller Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Chapter 2: Voltage Supplies
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
VCCINT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
VCCAUX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Setting the VCCAUX Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
VCCAUX Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
VCCO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
VREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Board Design and Signal Integrity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Simultaneously Switching Outputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Power Distribution System Design and Decoupling/Bypass Capacitors . . . . . . . . . . 28
Chapter 3: Lower-Power Spartan-6 LX Devices
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Designing Using the Lower-Power Spartan-6 LX Devices . . . . . . . . . . . . . . . . . . . . 29
Lower-Power Spartan-6 LX Device Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Chapter 4: Power-On and Power-Down Behavior Including Hibernate
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Supply Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Ramp Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Hot Swap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Configuration Data Retention and Brown Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
GTP Transceiver Power-Up and Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Hibernate Power Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Forcing FPGA to Quiescent Current Levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Entering Hibernate State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Turn Off VCCO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Exiting Hibernate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Chapter 5: Power Estimation
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Voltage Regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Saving Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Saving Clock Routing Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
ISE Design Suite Power Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
4 www.xilinx.com Spartan-6 FPGA Power Management
UG394 (v1.1) September 4, 2012
About This Guide
This document provides information on the various hardware methods of power
management in Spartan-6 FPGAs, primarily focusing on the suspend mode. Other power
management topics include the lower-power Spartan-6 LX devices (-1L) and the
programmable V
provided on the power rails, including hot swap and hibernate (power-off) options.
Guide Contents
This user guide contains the following chapters:
• Chapter 1, Power Management With Suspend Mode
• Chapter 2, Voltage Supplies
• Chapter 3, Lower-Power Spartan-6 LX Devices
• Chapter 4, Power-On and Power-Down Behavior Including Hibernate
• Chapter 5, Power Estimation
level available in all Spartan-6 devices. In addition, more detail is
CCAUX
Preface
Additional Documentation
These documents are available for download at
http://www.xilinx.com/support/documentation/spartan-6.htm
• Spartan-6 Family Overview
This overview outlines the features and product selection of the Spartan-6 family.
• Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
This data sheet contains the DC and switching characteristic specifications for the
Spartan-6 family.
• Spartan-6 FPGA Packaging and Pinout Specifications
This specification includes the tables for device/package combinations and maximum
I/Os, pin definitions, pinout tables, pinout diagrams, mechanical drawings, and
thermal specifications.
• Spartan-6 FPGA Configuration User Guide
This all-encompassing configuration guide includes chapters on configuration
interfaces (serial and parallel), multi-bitstream management, bitstream encryption,
boundary-scan and JTAG configuration, and reconfiguration techniques.
• Spartan-6 FPGA SelectIO Resources User Guide
This guide describes the SelectIO™ resources available in all Spartan-6 devices.
.
Spartan-6 FPGA Power Management www.xilinx.com 5
UG394 (v1.1) September 4, 2012
Running H/F 3
•Spartan-6 FPGA Clocking Resources User Guide
This guide describes the clocking resources available in all Spartan-6 devices,
including the DCMs and PLLs.
• Spartan-6 FPGA Block RAM Resources User Guide
This guide describes the Spartan-6 device block RAM capabilities.
• Spartan-6 FPGA Configurable Logic Blocks User Guide
This guide describes the capabilities of the configurable logic blocks (CLBs) available
in all Spartan-6 devices.
• Spartan-6 FPGA GTP Transceivers User Guide
This guide describes the GTP transceivers available in the Spartan-6 LXT FPGAs.
• Spartan-6 FPGA DSP48A1 Slice User Guide
This guide describes the architecture of the DSP48A1 slice in Spartan-6 FPGAs and
provides configuration examples.
• Spartan-6 FPGA Memory Controller User Guide
This guide describes the Spartan-6 FPGA memory controller block, a dedicated
embedded multi-port memory controller that greatly simplifies interfacing
Spartan-6 FPGAs to the most popular memory standards.
• Spartan-6 FPGA PCB Design and Pin Planning Guide
This guide provides information on PCB design for Spartan-6 devices, with a focus on
strategies for making design decisions at the PCB and interface level.
These documents provide additional background:
• WP298
At 40 and 45 nm process nodes, power has become the primary factor for FPGA
selection. Spartan-6 FPGAs offer lower power, simpler power systems and PCB
complexity, better reliability, and lower system cost. This white paper details how
Xilinx designed for this new reality in Spartan-6 (45 nm) and Virtex®-6 (40 nm) FPGA
families, achieving dramatic power reductions over previous generation devices.
• WP370
Xilinx delivers the first automated, fine-grain clock-gating solution that can reduce
dynamic power by up to 30% for Spartan-6 FPGA designs.
• WP396
White Paper
This white paper describes how Spartan-6 FPGAs address the needs of high-volume
systems. The ability to connect efficiently and inexpensively to commodity memories,
high-performance chip-to-chip interface capability, and innovative power down
modes are just a few of the problems solved by high-performance, low-power, and
low-cost Spartan-6 FPGAs.
, Power Consumption at 40 nm and 45 nm, White Paper
, Reducing Switching Power with Intelligent Clock Gating, White Paper
, High-Volume Spartan-6 FPGAs: Performance and Power Leadership by Design,
Additional Support Resources
To search the database of silicon and software questions and answers or to create a
technical support case in WebCase, see the Xilinx website at:
http://www.xilinx.com/support
6 www.xilinx.com Spartan-6 FPGA Power Management
.
UG394 (v1.1) September 4, 2012
Chapter 1
Power Management With Suspend Mode
Introduction
Some applications require the lowest possible system cost or highest performance, and
other applications require the lowest possible standby power. Spartan®-6 FPGAs offer
low-power options to balance these cost and performance trade-offs.
The Spartan-6 family offers the suspend mode, an advanced static power-management
feature, which reduces FPGA power consumption while retaining the FPGA's
configuration data and maintaining the design. The device can quickly enter and exit
suspend mode as required in an application.
Differences from Extended Spartan-3A Family
The suspend mode in Spartan-6 FPGAs is a superset of the suspend feature in the
Extended Spartan-3A FPGAs. Two new enhancements include multi-pin wake-up and
suspend synchronization.
Multi-Pin Wake-up
The multi-pin wake-up feature allows the FPGA to monitor for a wake-up signal on up to
eight pins. In the Extended Spartan-3A family, monitoring was limited to the SUSPEND
pin itself. Multi-pin wake-up also allows a number of independent sources to trigger the
FPGA to return to the normal application.
Suspend Synchronization
The Spartan-6 FPGA primitive, SUSPEND_SYNC, enables the synchronization of the
suspend action with the application design. In the Extended Spartan-3A family, the
suspend mode activation begins immediately upon asserting the SUSPEND pin. The
Spartan-6 FPGA SUSPEND_SYNC primitive allows the application design to
acknowledge a suspend request, thereby allowing the application to finish necessary
functions prior to entering the suspend mode.
Spartan-6 FPGA Power Management www.xilinx.com 7
UG394 (v1.1) September 4, 2012
Chapter 1: Power Management With Suspend Mode
Suspend Features
The significant features and benefits of the suspend mode:
• Quickly and easily puts the FPGA into a static condition, eliminating most active
current.
• Reduces quiescent current by 40% or more.
• Retains FPGA configuration data and the state of the FPGA application during
suspend mode.
• Fast, programmable FPGA wake-up time from suspend mode.
• Individual control on each user-I/O pin to define pin behavior while in suspend
mode.
• Activated externally by the system using a single dedicated control pin (SUSPEND).
• Indicates the present suspend mode status using the AWAKE pin.
• Awakens an FPGA in suspend mode using any of eight SUSPEND control pins (SCP).
• SUSPEND_SYNC primitive to acknowledge a ready state prior to entering suspend
mode.
Design Steps
To use the suspend feature:
• Enable the Suspend Feature and Glitch Filtering, page 14
• Define the Multi-Pin Wake-Up Feature and Pins, page 15
• Define the I/O Behavior During Suspend Mode, page 15
• Implement steps to maintain application data during suspend mode
(SUSPEND_SYNC) (see Design Requirements to Maintain Application Data, page 17)
• Define the Suspend Mode Wake-Up Timing Controls, page 17
• Define the AWAKE Pin Behavior when Suspend Feature is Enabled, page 21
Entering Suspend Mode
Figure 1-1 is a block diagram of the FPGA entering suspend mode. Figure 1-2, page 10
shows example waveforms.
8 www.xilinx.com Spartan-6 FPGA Power Management
UG394 (v1.1) September 4, 2012
X-Ref Target - Figure 1-1
Entering Suspend Mode
FPGA Application Logic
SUSPEND
FPGA
Inputs
Glitch Filter
Writable Clocked Primitives
Flip-Flops
Latches
SUSPEND_SYNC
SREQ SACK
SRL
LUT RAM
Block RAM
Block FPGA
Inputs
Write-Protect Writable
Clocked Primitives
Apply SUSPEND Attribute
to FPGA Outputs
SUSPEND
Attribute
SUSPEND
Attribute
FPGA
Outputs
AWAK
E
Suspend Enable
ENABLE_SUSPEND
Filter Select
ENABLE_SUSPEND
SUSPEND_SYNC
Instantiated
UG394_c1_01_020310
Figure 1-1: Entering Suspend Mode
The FPGA can only enter suspend mode if enabled in the configuration bitstream (see
Enable the Suspend Feature and Glitch Filtering, page 14). The SUSPEND pin must be Low
during power up and configuration. Once enabled through the bitstream, and the
SUSPEND_SYNC primitive is not present in the design, when the SUSPEND pin is
asserted, the FPGA unconditionally and quickly enters suspend mode.
If the SUSPEND_SYNC primitive is present in the design, the FPGA does not enter
suspend mode until the suspend-acknowledge signal (SACK) is asserted. After the
SUSPEND pin is asserted, the SREQ port of the SUSPEND_SYNC primitive transitions
High. This can be used in the design to initiate any functions that must be completed prior
to the FPGA entering suspend mode. When these functions are complete, drive the SACK
port High.
After the FPGA enters suspend mode, all nonessential FPGA functions are shut down to
minimize power dissipation. The FPGA retains all configuration data while in suspend
mode. After entering suspend mode, all writable clocked primitives are write-protected
against spurious write operations, and all FPGA inputs and interconnects are shut down.
This allows the design state to be held static during suspend mode. If a specific design state
must be maintained, see Design Requirements to Maintain Application Data, page 17.
Spartan-6 FPGA Power Management www.xilinx.com 9
UG394 (v1.1) September 4, 2012
Chapter 1: Power Management With Suspend Mode
ug394_c1_02_042910
Blocked
t
SUSPEND_DISABLE
t
AWAKE_GWE
t
AWAKE_GTS
SUSPEND Input
AWAKE Output
Flip-Flops, Block RAM,
Distributed RAM
FPGA Outputs
FPGA Inputs,
Interconnect
Write Protected
Defined by SUSPEND Attribute
1
2
3
4
5
6
7
8
10
9
Entering Suspend Mode Exiting Suspend Mode
sw_gts_cycle
sw_gwe_cycle
t
SUSPEND_ENABLE
t
SUSPENDLOW_AWAKE
t
SUSPEND_GTS
t
SUSPENDHIGH_AWAKE
t
SUSPEND_GWE
Each FPGA output pin or bidirectional I/O pin assumes its defined suspend mode
behavior, which is described as part of the FPGA design using a SUSPEND attribute.
The AWAKE pin goes Low, indicating that the FPGA is in suspend mode. The DONE pin
remains High while the FPGA is in suspend mode because the FPGA configuration data is
not lost.
X-Ref Target - Figure 1-2
Figure 1-2: Suspend Mode Waveforms (Entering and Exiting)
This section details the waveform notes in Figure 1-2.
Entering Suspend in Figure 1-2
1. An external signal drives the FPGA's SUSPEND pin High, unconditionally forcing the
FPGA into the power-saving suspend mode (if SUSPEND_SYNC is not used). When
10 www.xilinx.com Spartan-6 FPGA Power Management
SUSPEND_SYNC is used, this phase does not complete until the SACK port of the
SUSPEND_SYNC primitive is asserted. Data values are captured for I/O pins with a
SUSPEND attribute set to DRIVE_LAST_VALUE; however, this value is not presented
until Step 4.
2. In response to the SUSPEND input going High or SACK assertion on the
SUSPEND_SYNC primitive, and after a delay of t
protects and preserves the states of all clocked primitives. The states of all flip-flops,
block RAM, distributed RAM (LUT RAM), shift registers (SRL), and I/O latches are
preserved during suspend mode.
SUSPEND_GWE
, the FPGA write
UG394 (v1.1) September 4, 2012
Entering Suspend Mode
3. After a delay of t
SUSPENDHIGH_AWAKE
, the FPGA drives the AWAKE output Low to
indicate that it is entering suspend mode.
4. After a delay of t
SUSPEND_GTS
, the FPGA switches the normal behavior of all outputs
over to the suspend mode behavior defined by the SUSPEND attribute assigned to
each I/O. See Define the I/O Behavior During Suspend Mode, page 15.
5. After a delay of t
SUSPEND_DISABLE
, FPGA inputs are blocked and the interconnect shut
off (High) to prevent any internal switching activity.
Exiting Suspend in Figure 1-2
6. The system drives the FPGA's SUSPEND input Low, causing the FPGA to exit suspend
mode. If using multi-pin wake-up mode, the system first drives the FPGA's SUSPEND
input LOW, then drives any of the enabled multi-pin wake-up pins High, causing the
FPGA to exit suspend mode.
7. The FPGA releases the inputs and interconnect after a delay of t
SUSPEND_ENABLE
allowing signals to propagate internally. There is no danger of corrupting the internal
state because all clocked primitives are still write protected.
8. After a delay of t
SUSPENDLOW_AWAKE
or t
SCP_AWAKE
, the FPGA asserts the AWAKE
signal with the bitstream option drive_awake:yes. If the option is drive_awake:no,
then the FPGA releases AWAKE to become an open-drain output. In this case, an
external pull-up resistor is required or an external signal must drive AWAKE High
before the FPGA continues to awaken. All subsequent timing is measured from when
the AWAKE output transitions High. If multiple FPGAs are waking up and need to be
synchronized, set drive_awake:no in each and then use an external pull-up resistor to
synchronize the AWAKE pins. If other devices are waking up and the FPGA(s) need to
wait, set drive_awake:no and use an external signal to control the AWAKE pin and
drive it High once the rest of the system is ready.
9. After a delay of t
AWAK E_ GTS
, the FPGA switches output behavior from the specified
SUSPEND attribute to the function specified in the FPGA application. The timing of
this switch-over is controlled by the suspend/wake sw_gts_cycle bitstream
generation setting, which defines when the FPGA's internal global three-state (GTS)
control is released. After the specified number of clock cycles, the outputs are active
according to the normal FPGA application. By default, the outputs are enabled four
clock cycles after AWAKE goes High. The outputs are generally released before the
clocked primitives to allow signals to propagate out of the FPGA.
10. After a delay of t
AWAK E_ GWE
, the writable, clocked primitives are released according
to the suspend/wake sw_gwe_cycle bitstream generator setting, which defines when
the FPGA's internal global write enable (GWE) control is asserted. After the specified
cycle, it is again possible to write to flip-flops, block RAM, distributed RAM (LUT
RAM), shift registers (SRL), and I/O latches. By default, the clocked primitives are
released five clock cycles after AWAKE transitions High. The write-protect lock should
be held until after outputs are enabled.
,
Spartan-6 FPGA Power Management www.xilinx.com 11
UG394 (v1.1) September 4, 2012
Chapter 1: Power Management With Suspend Mode
Exiting Suspend Mode
There are four possible ways to exit suspend mode in a powered system:
• Drive the SUSPEND input Low, exiting suspend mode.
• If multi-pin wake-up mode is enabled, drive the SUSPEND input Low and then assert
any one of the user enabled SCP pins.
• Pulse the PROGRAM_B input Low to reset the FPGA and cause the FPGA to
reprogram.
• Power cycle the FPGA, causing the FPGA to reprogram.
The block diagram in Figure 1-3 shows how to exit suspend mode using the SUSPEND
pin.
When SUSPEND transitions Low, the FPGA automatically re-enables all inputs and
interconnects after a delay of t
SUSPEND must first transition Low, then when any of the user enabled SCP pins for
multi-pin wake up mode transition High, the FPGA re-enables all inputs and interconnects
after a delay of t
When enabled in the FPGA bitstream, all flip-flops are optionally globally set or reset
according to the FPGA design description. By default, the flip-flops are not globally set or
reset, which preserves the state of the FPGA application from the beginning of suspend
mode.
SUSPEND_ENABLE
SUSPEND_ENABLE
.
. If using multi-pin wake-up mode,
The remaining wake-up process depends on two user-programmable timers which define
when FPGA outputs are re-enabled and when the write-protect lock is released from all
writable clocked primitives. These timers begin after the AWAKE pin is High. The
wake-up timing clock source is also programmable.
12 www.xilinx.com Spartan-6 FPGA Power Management
UG394 (v1.1) September 4, 2012
Loading...