Xilinx Spartan-6 FPGA PCB Design and Pin Planning Guide

Spartan-6 FPGA
PCB Design and
Pin Planning Guide

UG393 (v1.1) April 29, 2010

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© 2009–2010 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx
in the United States and other countries. All other trademarks are the property of their respective owners.

Revision History

The following table shows the revision history for this document.

Date Version Revision

09/21/09 1.0 Initial Xilinx release.

04/29/10 1.1 Changed guide title and added Chapter 6 and Appendix A. Replaced

Ta bl e 2 -1 .

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Table of Contents

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Preface: About This Guide

Guide Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Additional Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Additional Support Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Chapter 1: PCB Technology Basics

PCB Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Traces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Planes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Vias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Pads and Antipads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Lands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Transmission Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Return Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Chapter 2: Power Distribution System

PCB Decoupling Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Recommended Capacitors per Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Required PCB Capacitor Quantities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Capacitor Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

PCB Bulk Capacitors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

PCB High-Frequency Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Capacitor Consolidation Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

PCB Capacitor Placement and Mounting Techniques . . . . . . . . . . . . . . . . . . . . . . . . . . 17

PCB Bulk Capacitors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

0805 Ceramic Capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

0402 Ceramic Capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Basic PDS Principles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Noise Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Role of Inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Capacitor Parasitic Inductance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

PCB Current Path Inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Capacitor Mounting Inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Plane Inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

FPGA Mounting Inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

PCB Stackup and Layer Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Capacitor Effective Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Capacitor Anti-Resonance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Capacitor Placement Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

V

Stabilization Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

REF

Power Supply Consolidation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Unconnected V

Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

CCO

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Simulation Methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

PDS Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Noise Magnitude Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Noise Spectrum Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Optimum Decoupling Network Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Troubleshooting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Possibility 1: Excessive Noise from Other Devices on the PCB . . . . . . . . . . . . . . . . . . 37

Possibility 2: Parasitic Inductance of Planes, Vias, or Connecting Traces . . . . . . . . . . 37

Possibility 3: I/O Signals in PCB are Stronger Than Necessary . . . . . . . . . . . . . . . . . . 38

Possibility 4: I/O Signal Return Current Traveling in Sub-Optimal Paths . . . . . . . . . 38

Chapter 3: SelectIO Signaling

Interface Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Single-Ended versus Differential Interfaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

SDR versus DDR Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Single-Ended Signaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Modes and Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Input Thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Chapter 4: PCB Materials and Traces

How Fast is Fast? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Dielectric Losses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Relative Permittivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Loss Tangent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Skin Effect and Resistive Losses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Choosing the Substrate Material . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Traces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Trace Geometry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Trace Characteristic Impedance Design for High-Speed Transceivers . . . . . . . . . . . . 43

Trace Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Plane Splits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Return Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Simulating Lossy Transmission Lines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Cable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Skew Between Conductors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Chapter 5: Design of Transitions for High-Speed Signals

Excess Capacitance and Inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Time Domain Reflectometry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

BGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

SMT Pads. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Differential Vias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

P/N Crossover Vias. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

SMA Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Backplane Connectors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Microstrip/Stripline Bends . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

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Chapter 6: I/O Pin and Clock Planning

Configuration Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Configuration Pin Planning Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Multi-function Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Configuration Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Memory Controller Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

MCB Pin Planning Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

MCB Clocking Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

GTP Transceivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

GTP Transceiver Pin Planning Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

GTP Transceiver Clocking Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

PCI Express . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Other GTP Transceiver Based Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Global and I/O Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

GCLK Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

BUFIO2 I/O Clock Buffer Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Overview of BUFIO2 Resource Usage per Interface Type . . . . . . . . . . . . . . . . . . . . . . . 66

Bidirectional I/O. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Serializing Interfaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Pin Planning Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Single-Ended SerDes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Differential SerDes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Power Management—Using Suspend/Awake. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

I/O Standards and I/O Banking Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Simultaneous Switching Output (SSO) Management . . . . . . . . . . . . . . . . . . . . . . . . 67

Running Design Rule Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Density Migration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Appendix A: Recommended PCB Design Rules

Recommended PCB Design Rules for QFP Packages . . . . . . . . . . . . . . . . . . . . . . . . . 69

Recommended PCB Design Rules for BGA and CSP Packages . . . . . . . . . . . . . . . 70

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About This Guide

This guide provides information on PCB design for Spartan®-6 devices, with a focus on
strategies for making design decisions at the PCB and interface level.

Guide Contents

This guide contains the following chapters:

• Chapter 1, PCB Technology Basics, discusses the basics of current PCB technology
focusing on physical structures and common assumptions.

• Chapter 2, Power Distribution System, covers the power distribution system for
Spartan-6 FPGAs, including all details of decoupling capacitor selection, use of
voltage regulators and PCB geometries, simulation and measurement.

• Chapter 3, SelectIO Signaling, contains information on the choice of SelectIO™
standards, I/O topographies, and termination strategies as well as information on
simulation and measurement techniques.

• Chapter 4, PCB Materials and Traces, provides some guidelines on managing signal
attenuation to obtain optimal performance for high-frequency applications.

• Chapter 5, Design of Transitions for High-Speed Signals, addresses the interface at
either end of a transmission line. The provided analyses and examples can greatly
accelerate the specific design.

Preface

Additional Documentation

The following documents are also available for downloaded at

http://www.xilinx.com/support/documentation/spartan-6.htm

• Spartan-6 Family Overview

This overview outlines the features and product selection of the Spartan-6 family.

• Spartan-6 FPGA Data Sheet: DC and Switching Characteristics

This data sheet contains the DC and switching characteristic specifications for the
Spartan-6 family.

• Spartan-6 FPGA Packaging and Pinout Specifications

This specification includes the tables for device/package combinations and maximum
I/Os, pin definitions, pinout tables, pinout diagrams, mechanical drawings, and
thermal specifications.

• Spartan-6 FPGA Configuration User Guide

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.

Preface: About This Guide

• Spartan-6 FPGA SelectIO Resources User Guide

•Spartan-6 FPGA Clocking Resources User Guide

• Spartan-6 FPGA Configurable Logic Block User Guide

• Spartan-6 FPGA Block RAM Resources User Guide

• Spartan-6 FPGA DSP48A1 Slice User Guide

• Spartan-6 FPGA Memory Controller User Guide

This all-encompassing configuration guide includes chapters on configuration
interfaces (serial and parallel), multi-bitstream management, bitstream encryption,
boundary-scan and JTAG configuration, and reconfiguration techniques.

This guide describes the SelectIO™ resources available in all Spartan-6 devices.

This guide describes the clocking resources available in all Spartan-6 devices,
including the DCMs and PLLs.

This guide describes the capabilities of the configurable logic blocks (CLBs) available
in all Spartan-6 devices.

This guide describes the Spartan-6 device block RAM capabilities.

This guide describes the architecture of the DSP48A1 slice in Spartan-6 FPGAs and
provides configuration examples.

This guide describes the Spartan-6 FPGA memory controller block, a dedicated
embedded multi-port memory controller that greatly simplifies interfacing Spartan-6
FPGAs to the most popular memory standards.

• Spartan-6 FPGA GTP Transceiver User Guide

This guide describes the GTP transceivers available in the Spartan-6 LXT FPGAs.

Additional Support Resources

To search the Answer Database of silicon, software, and IP questions and answers, or to
create a technical support WebCase, see the Xilinx website at:

http://www.xilinx.com/support/mysupport.htm

.

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PCB Technology Basics

Printed circuit boards (PCBs) are electrical systems, with electrical properties as
complicated as the discrete components and devices mounted to them. The PCB designer
has complete control over many aspects of the PCB; however, current technology places
constraints and limits on the geometries and resulting electrical properties. The following
information is provided as a guide to the freedoms, limitations, and techniques for PCB
designs using FPGAs.

This chapter contains the following sections:

• PCB Structures

• Transmission Lines

• Return Currents

PCB Structures

Chapter 1

Tr ac e s

Planes

PCB technology has not changed significantly in the last few decades. An insulator
substrate material (usually FR4, an epoxy/glass composite) with copper plating on both
sides has portions of copper etched away to form conductive paths. Layers of plated and
etched substrates are glued together in a stack with additional insulator substrates
between the etched substrates. Holes are drilled through the stack. Conductive plating is
applied to these holes, selectively forming conductive connections between the etched
copper of different layers.

While there are advancements in PCB technology, such as material properties, the number
of stacked layers used, geometries, and drilling techniques (allowing holes that penetrate
only a portion of the stackup), the basic structures of PCBs have not changed. The
structures formed through the PCB technology are abstracted to a set of physical/electrical
structures: traces, planes (or planelets), vias, and pads.

A trace is a physical strip of metal (usually copper) making an electrical connection
between two or more points on an X-Y coordinate of a PCB. The trace carries signals
between these points.

A plane is an uninterrupted area of metal covering the entire PCB layer. A planelet, a
variation of a plane, is an uninterrupted area of metal covering only a portion of a PCB
layer. Typically, a number of planelets exist in one PCB layer. Planes and planelets
distribute power to a number of points on a PCB. They are very important in the

Spartan-6 FPGA PCB Design and Pin Planning www.xilinx.com 9
UG393 (v1.1) April 29, 2010

Chapter 1: PCB Technology Basics

transmission of signals along traces because they are the return current transmission
medium.

Vias

A via is a piece of metal making an electrical connection between two or more points in the
Z space of a PCB. Vias carry signals or power between layers of a PCB. In current plated­through-hole (PTH) technology, a via is formed by plating the inner surface of a hole
drilled through the PCB. In current microvia technology (also known as High Density
Interconnect or HDI), a via is formed with a laser by ablating the substrate material and
deforming the conductive plating. These microvias cannot penetrate more than one or two
layers, however, they can be stacked or stair-stepped to form vias traversing the full board
thickness.

Pads and Antipads

Because PTH vias are conductive over the whole length of the via, a method is needed to
selectively make electrical connections to traces, planes, and planelets of the various layers
of a PCB. This is the function of pads and antipads.

Pads are small areas of copper in prescribed shapes. Antipads are small areas in prescribed
shapes where copper is removed. Pads are used both with vias and as exposed outer-layer
copper for mounting of surface-mount components. Antipads are used mainly with vias.

For traces, pads are used to make the electrical connection between the via and the trace or
plane shape on a given layer. For a via to make a solid connection to a trace on a PCB layer,
a pad must be present for mechanical stability. The size of the pad must meet drill
tolerance/registration restrictions.

Antipads are used in planes. Because plane and planelet copper is otherwise
uninterrupted, any via traveling through the copper makes an electrical connection to it.
Where vias are not intended to make an electrical connection to the planes or planelets
passed through, an antipad removes copper in the area of the layer where the via
penetrates.

Lands

For the purposes of soldering surface mount components, pads on outer layers are
typically referred to as lands or solder lands. Making electrical connections to these lands
usually requires vias. Due to manufacturing constraints of PTH technology, it is rarely
possible to place a via inside the area of the land. Instead, this technology uses a short
section of trace connecting to a surface pad. The minimum length of the connecting trace is
determined by minimum dimension specifications from the PCB manufacturer. Microvia
technology is not constrained, and vias can be placed directly in the area of a solder land.

Dimensions

The major factors defining the dimensions of the PCB are PCB manufacturing limits, FPGA
package geometries, and system compliance. Other factors such as Design For
Manufacturing (DFM) and reliability impose further limits, but because these are
application specific, they are not documented in this user guide.

The dimensions of the FPGA package, in combination with PCB manufacturing limits,
define most of the geometric aspects of the PCB structures described in this section (PCB

Structures), both directly and indirectly. This significantly constrains the PCB designer. The

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UG393 (v1.1) April 29, 2010

Transmission Lines

package pin or ball pitch (1.0 mm for FG packages) defines the land pad layout. The
minimum surface feature sizes of current PCB technology define the via arrangement in
the area under the device. Minimum via diameters and keep-out areas around those vias are
defined by the PCB manufacturer. These diameters limit the amount of space available
in-between vias for routing of signals in and out of the via array underneath the device.
These diameters define the maximum trace width in these breakout traces. PCB
manufacturing limits constrain the minimum trace width and minimum spacing.

The total number of PCB layers necessary to accommodate an FPGA is defined by the
number of signal layers and the number of plane layers.

• The number of signal layers is defined by the number of I/O signal traces routed in
and out of an FPGA package (usually following the total User I/O count of the
package for array packages).

• The number of plane layers is defined by the number of power and ground plane
layers necessary to bring power to the FPGA and to provide references and isolation
for signal layers.

PCBs for larger FPGAs can range from 4 to 22 layers.

System compliance often defines the total thickness of the board. Along with the number
of board layers, this defines the maximum layer thickness, and therefore, the spacing in the
Z direction of signal and plane layers to other signal and plane layers. Z-direction spacing
of signal trace layers to other signal trace layers affects crosstalk. Z-direction spacing of
signal trace layers to reference plane layers affects signal trace impedance. Z-direction
spacing of plane layers to other plane layers affects power system parasitic inductance.

Z-direction spacing of signal trace layers to reference plane layers (defined by total board
thickness and number of board layers) is a defining factor in trace impedance.Trace width
(defined by FPGA package ball pitch and PCB via manufacturing constraints) is another
factor in trace impedance. A designer often has little control over trace impedance in area
of the via array beneath the FPGA. When traces escape the via array, their width can
change to the width of the target impedance (usually 50Ω single-ended).

Decoupling capacitor placement and discrete termination resistor placement are other
areas of trade-off optimization. DFM constraints often define a keep-out area around the
perimeter of the FPGA (device footprint) where no discrete components can be placed. The
purpose of the keep-out area is to allow room for assembly and rework where necessary.
For this reason, the area just outside the keep-out area is one where components compete
for placement. It is up to the PCB designer to determine the high priority components.
Decoupling capacitor placement constraints are described in Chapter 2, Power

Distribution System. Termination resistor placement constraints must be determined

through signal integrity simulation, using IBIS or SPICE.

Transmission Lines

The combination of a signal trace and a reference plane forms a transmission line. All I/O
signals in a PCB system travel through transmission lines.

For single-ended I/O interfaces, both the signal trace and the reference plane are necessary
to transmit a signal from one place to another on the PCB. For differential I/O interfaces,
the transmission line is formed by the combination of two traces and a reference plane.
While the presence of a reference plane is not strictly necessary in the case of differential
signals, it is necessary for practical implementation of differential traces in PCBs.

Good signal integrity in a PCB system is dependent on having transmission lines with
controlled impedance. Impedance is determined by the geometry of the traces and the

Spartan-6 FPGA PCB Design and Pin Planning www.xilinx.com 11
UG393 (v1.1) April 29, 2010

Chapter 1: PCB Technology Basics

dielectric constant of the material in the space around the signal trace and between the
signal trace and the reference plane.

The dielectric constant of the material in the vicinity of the trace and reference plane is a
property of the PCB laminate materials, and in the case of surface traces, a property of the
air or fluid surrounding the board. PCB laminate is typically a variant of FR4, though it can
also be an exotic material.

While the dielectric constant of the laminate varies from board to board, it is fairly constant
within one board. Therefore, the relative impedance of transmission lines in a PCB is
defined most strongly by the trace geometries and tolerances. Impedance variance can
occur based on the presence or absence of glass in a local portion of the laminate weave,
but this rarely poses issues except in high-speed (>6 Gb/s) interfaces.

Return Currents

An often neglected aspect of transmission lines and their signal integrity is return current.
It is incorrect to assume that a signal trace by itself forms a transmission line. Currents
flowing in a signal trace have an equal and opposite complimentary current flowing in the
reference plane beneath them. The relationship of the trace voltage and trace current to
reference plane voltage and reference plane current defines the characteristic impedance of
the transmission line formed by the trace and reference plane. While interruption of
reference plane continuity beneath a trace is not as dramatic in effect as severing the signal
trace, the performance of the transmission line and any devices sharing the reference plane
is affected.

It is important to pay attention to reference plane continuity and return current paths.
Interruptions of reference plane continuity, such as holes, slots, or isolation splits, cause
significant impedance discontinuities in the signal traces. They can also be a significant
source of crosstalk and contributor to Power Distribution System (PDS) noise. The
importance of return current paths cannot be underestimated.

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UG393 (v1.1) April 29, 2010

Power Distribution System

This chapter documents the power distribution system (PDS) for Spartan®-6 FPGAs,
including decoupling capacitor selection, placement, and PCB geometries. A simple
decoupling method is provided for each device in the Spartan-6 family. Basic PDS design
principles are covered, as well as simulation and analysis methods. This chapter contains
the following sections:

• PCB Decoupling Capacitors

• Basic PDS Principles

• Simulation Methods

• PDS Measurements

• Troubleshooting

PCB Decoupling Capacitors

Chapter 2

Recommended Capacitors per Device

A simple PCB-decoupling network for each Spartan-6 device is listed in Tab le 2 -1 .

Decoupling methods other than those presented in Ta bl e 2- 1 can be used, but the
decoupling network should be designed to meet or exceed the performance of the simple
decoupling networks presented here. The impedance of the alternate network must be less
than or equal to that of the recommended network across frequencies from 100 KHz to
500 MHz.

Because device capacitance requirements vary with CLB and I/O utilization, PCB
decoupling guidelines are provided on a per-device basis. V
are listed as the quantity per device, while V
I/O bank. Device performance at full utilization is equivalent across all devices when
using these recommended networks.

and V

capacitors are listed as the quantity per

CCO

CCINT

CCAUX

capacitors

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UG393 (v1.1) April 29, 2010

Chapter 2: Power Distribution System

Required PCB Capacitor Quantities

Tab le 2 -1 lists the PCB decoupling capacitor guidelines per VCC supply rail.

CCO

(1)

V

CCO

Bank 2

in µF

V

CCO

Bank 3

in µF

V

CCO

Bank 4

in µF

V

CCO

Bank 5

in µF

Tot al

Table 2-1: Required PCB Capacitor Quantities per Device

V

Bank 1

in µF

Package

Device
(XC6S)

V

V

CCINT

in µF

100 4.7 0.47 100 4.7 0.47 100 4.7 0.47 100 4.7 0.47 100 4.7 0.47 100 4.7 0.47 100 4.7 0.47 100 4.7 0.47

V

CCAUX

in µF

CCO

Bank 0

in µF

TQG144LX4 051073012012012012 28

TQG144LX9 112073012012012012 26

CPG196LX4 051113112112112112 27

CPG196LX9 112113112112112112 25

CPG196LX16 124 11 3112 112 11211 2 28

CSG225LX4 051124123123123123 37

CSG225LX9 012124123123123123 34

CSG225LX16 124 12 4123 12 3123 123 38

CSG324LX9 112135123124123124 39

CSG324LX16 124 13 6124 12 4134 124 46

CSG324LX25 137 13 6124 12 4134 124 50

CSG324 LX25T 1 3 7 1 2 5 1 1 1 1 2 4 1 3 4 1 2 4 44

(2)

CSG324LX45 2612136 12 3124 13 4124 58

CSG324 LX45T 2 6 12 1 2 5 1 1 1 1 2 4 1 3 4 1 2 4 53

FT(G)256LX9 112125123124123124 38

FT(G)256LX16 12412 5 123 12 4123 12 4 41

FT(G)256LX25 13712 5 123 12 4123 12 4 45

CSG484LX45 2612148 12 3148 12 4147

71

CSG484 LX45T 2 6 12 1 4 7 1 2 3 1 4 7 1 2 4 1 4 7 69

CSG484LX75 31020148124148124148 86

CSG484 LX75T 3 10 20 1 4 7 1 2 3 1 4 7 1 2 4 1 4 7

82

CSG484 LX100 4 13 27 1 4 9 1 2 4 1 4 8 1 3 5 1 4 8 100

CSG484 LX100T 4 13 27 1 4 7 1 2 3 1 4 7 1 2 4 1 4 7 93

CSG484 LX150 7 20 40 1 4 9 1 2 4 1 4 8 1 3 5 1 4 8 123

CSG484 LX150T 7 20 40 1 4 7 1 2 3 1 4 7 1 2 4 1 4 7 11 6

FG(G)484LX25 13 7137 124 13413 613 4 55

FG(G)484 LX25T 1 3 7 1 3 6 1 2 3 1 3 4 1 3 6 1 3 4

53

FG(G)484LX45 261214812 3 136 14 7146 72

FG(G)484 LX45T 2 6 12 1 4 7 1 2 3 1 3 6 1 3 6 1 3 6 68

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UG393 (v1.1) April 29, 2010

PCB Decoupling Capacitors

CCO

(1)

(Continued)

V

CCO

Bank 2

in µF

V

CCO

Bank 3

in µF

V

CCO

Bank 4

in µF

V

CCO

Bank 5

in µF

Tot al

Table 2-1: Required PCB Capacitor Quantities per Device

V

Bank 1

in µF

Package

Device
(XC6S)

V

V

CCINT

in µF

100 4.7 0.47 100 4.7 0.47 100 4.7 0.47 100 4.7 0.47 100 4.7 0.47 100 4.7 0.47 100 4.7 0.47 100 4.7 0.47

V

CCAUX

in µF

CCO

Bank 0

in µF

FG(G)484LX75 31020149135136147146 89

FG(G)484 LX75T 3 10 20 1 4 7 1 2 3 1 3 6 1 3 6 1 3 6 81

FG(G)484 LX100 4 13 27 1 4 8 1 3 5 1 3 6 1 4 6 1 4 6 98

FG(G)484 LX100T 4 13 27 1 4 7 1 2 3 1 3 6 1 3 6 1 3 6 92

FG(G)484 LX150 7 20 40 1 4 8 1 3 5 1 3 6 1 4 6 1 4 6 121

FG(G)484 LX150T 7 20 40 1 4 7 1 2 3 1 3 6 1 3 6 1 3 6 115

FG(G)676LX45 261215913 5 136 14 6148 78

FG(G)676 LX75 3 10 20 2 6 12 1 4 6 1 4 6 1 4 7 1 4 7 1 2 4 1 2 4 113

FG(G)676 LX75T 3 10 20 1 5 10 1 3 6 1 2 4 1 3 6 1 3 5 1 2 4 1 2 4 99

FG(G)676 LX100 4 13 27 2 6 12 1 4 6 1 4 6 1 4 7 1 4 7 1 2 4 1 2 4 124

FG(G)676 LX100T 4 13 27 1 5 10 1 3 5 1 2 4 1 3 5 1 3 5 1 2 3 1 2 4 107

FG(G)676 LX150 7 20 40 2 6 12 1 4 6 1 4 6 1 4 7 1 4 7 1 2 4 1 2 4 147

(2)

FG(G)676 LX150T 7 20 40 1 5 10 1 3 5 1 2 4 1 3 5 1 3 5 1 2 3 1 2 4 130

FG(G)900 LX100T 4 13 27 2 6 13 1 4 6 1 4 7 1 4 7 1 5 8 1 2 4 1 2 4 128

FG(G)900 LX150 7 20 40 2 7 15 1 5 9 1 4 7 1 5 9 1 5 8 1 2 4 1 2 4 161

FG(G)900 LX150T 7 20 40 2 7 14 1 5 8 1 4 7 1 5 8 1 5 8 1 2 4 1 2 4 158

Notes:

1. PCB Capacitor specifications are listed in Tab le 2- 2.

2. Total includes all capacitors for all supplies, accounting for the number of I/O banks in the device.

Spartan-6 FPGA PCB Design and Pin Planning www.xilinx.com 15
UG393 (v1.1) April 29, 2010

Chapter 2: Power Distribution System

Capacitor Specifications

The electrical characteristics of the capacitors in Tab le 2 -1 are described in this section.
Characteristics of the PCB bulk and high-frequency capacitors are specified in Ta bl e 2 -2 ,
followed by guidelines on acceptable substitutions. The equivalent series resistance (ESR)
ranges specified for these capacitors can be over-ridden. However, this requires analysis of
the resulting power distribution system impedance to ensure that no resonant impedance
spikes result.

Table 2-2: PCB Capacitor Specifications

Ideal

Val ue

100 µF C > 100 µF 1210

4.7 µF C > 4.7 µF 0805

0.47 µF C > 0.47 µF

PCB Capacitor Substitution Rules:

1. Values can be larger than specified.

2. Body size can be smaller than specified.

3. ESR must be within the specified range.

4. Voltage rating can be higher than specified.

Val ue

Range

(1)

Body

(2)

Size

0204 or

0402

Typ e

2-Terminal
Ceramic
X7R or X5R

2-Terminal
Ceramic
X7R or X5R

2-Terminal
Ceramic
X7R or X5R

PCB Bulk Capacitors

The purpose of the bulk capacitors is to cover the low-frequency range between where the
voltage regulator stops working (~100 KHz) and where the high-frequency capacitors start
working (~2 MHz). As specified in Ta bl e 2 -1 , all FPGA supplies require bulk capacitors.

The bulk capacitors in Tab le 2 -1 and Ta bl e 2- 2 are not necessarily in addition to the voltage
regulator output capacitors required by the regulator manufacturer, provided there is no
inductor, ferrite bead, choke, or other filter between the FPGA and the bulk capacitors.
However, if the FPGA bulk and regulator output requirements are merged, the total
capacitance of this network must not be less than the total bulk specified in Ta bl e 2- 1 and

Tab le 2 -2, and must comply with the regulator manufacturer’s output capacitor

requirements.

ESL

Maximum

5nH 10mΩ <ESR<60mΩ 6.3V GRM32ER60J107ME20L

2nH 10mΩ <ESR<60mΩ 6.3V

1.5 nH 10 mΩ <ESR<60mΩ 6.3V

ESR Range

(3)

Volt ag e

Rating

(4)

Suggested

Part Number

The bulk PCB capacitors specified in Ta ble 2 -1 are ceramic capacitors from Murata, a
capacitor manufacturer. This capacitor was selected for its value, size, and low-cost. It is
also RoHS compliant. If another manufacturer’s capacitors or another type of capacitor
(e.g., tantalum or high-performance electrolytic) meet the specifications listed in Tab le 2 -2 ,
substitution is acceptable.

PCB High-Frequency Capacitors

There are two high-frequency capacitor values in Tab le 2 -2 : the 4.7 µF capacitor in an 0805
package and the 0.47 µF capacitor in an 0402 or 0204 package. Substitutions can be made
for some characteristics, but not others; see the notes attached to Tab le 2 -2 for details.

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Capacitor Consolidation Rules

Sometimes a number of I/O banks are powered from the same voltage (e.g., 1.8V) and the
recommended guidelines call for multiple bulk capacitors. This is also the case for V
and V
fewer (larger value) bulk capacitors provided the electrical characteristics of the
consolidated capacitors (ESR and ESL) are equal to the electrical characteristics of the
parallel combination of the recommended capacitors.

in the larger devices. These many smaller capacitors can be consolidated into

CCAUX

PCB Decoupling Capacitors

CCINT

For most consolidations of V

CCO

, V

CCINT

, and V

CCAUX

capacitors, large bulk capacitors
(ceramic, tantalum, or high-performance electrolytic) with sufficiently low ESL and ESR
are readily available. High-frequency capacitors cannot be consolidated as the usefulness
of high-frequency capacitors depends on the number of PCB vias accessed.

Example

This example is of an FPGA with a single interface spanning three I/O banks, all powered
from the same voltage. The required PCB capacitor table (Tabl e 2- 1) calls for one 100 µF
capacitor per bank. These three capacitors can be consolidated into one capacitor since
three 100 µF capacitors can be covered by one 330 µF capacitor. The following is then true:

• The ESL of the combination must be one-third of the specified capacitor. Three

capacitors at 5 nH are equivalent to one capacitor at 1.7 nH. This implies that a 330 µF
capacitor is acceptable provided its ESL is less than 1.7 nH.

• The ESR of the combination must be one-third of the specified capacitor. Three

capacitors each in the range of 10 mΩ to 60 mΩ are equivalent to one capacitor in the
range of 3.3 mΩ to 20 mΩ. A 330 µF capacitor is acceptable provided its ESL is in this
range.

• Three 100 µF capacitors with 3 nH ESL and 20 mΩ ESR are replaced by one 330 µF

capacitor with a 0.5 nH ESL and a 15 mΩ ESR.

PCB Capacitor Placement and Mounting Techniques

Placement and mounting restrictions presented in this section are unique to each capacitor
type listed in the Capacitor Specifications section.

PCB Bulk Capacitors

Bulk capacitors can be large and difficult to place very close to the FPGA. Fortunately, this
is not a problem because the low-frequency energy covered by bulk capacitors is not as
sensitive to capacitor location. Bulk capacitors can be placed almost anywhere on the PCB,
but the best placement is as close as possible to the FPGA. Capacitor mounting should
follow normal PCB layout practices, tending toward short and wide shapes connecting to
power planes with multiple vias.

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UG393 (v1.1) April 29, 2010

Chapter 2: Power Distribution System

0805 Land Pattern

End Vias

Long Traces

(A)

UG393_c2_01_091809

(B)

0805 Land Pattern

End Vias

Not Recommended.

Connecting Trace is Too Long

1.27 mm
(50 mils)

0.61mm
(24 mils)

1.07 mm
(42 mils)

0.61mm
(24 mils)

(C)

0805 Land Pattern

Side Vias

1.12 mm
(44 mils)

0.61 mm
(24 mils)

0.61mm
(24 mils)

(D)

0805 Land Pattern

Double Side Vias

0.61mm
(24 mils)

0.61 mm
(24 mils)

1.12 mm
(44 mils)

0805 Ceramic Capacitor

The 4.7 µF 0805 capacitor covers the middle frequency range. Placement has some impact
on its performance. The capacitor should be placed as close as possible to the FPGA. Any
placement within two inches of the device’s outer edge is acceptable.

The capacitor mounting (solder lands, traces, and vias) should be optimized for low
inductance. Vias should be butted directly against the pads. Vias can be located at the ends
of the pads (see Figure 2-1B), but are more optimally located at the sides of the pads (see

Figure 2-1C). Via placement at the sides of the pads decreases the mounting’s overall

parasitic inductance by increasing the mutual inductive coupling of one via to the other.
Dual vias can be placed on both sides of the pads (see Figure 2-1D) for even lower parasitic
inductance, but with diminishing returns.

X-Ref Target - Figure 2-1

18 www.xilinx.com Spartan-6 FPGA PCB Design and Pin Planning

Figure 2-1: Example 0805 Capacitor Land and Mounting Geometries

UG393 (v1.1) April 29, 2010

PCB Decoupling Capacitors

0402 Ceramic Capacitor

The 0.47 µF 0402 capacitor covers the high-middle frequency range. Placement and
mounting are critical for these capacitors.

The capacitor should be mounted as close to the FPGA as possible (achieves the least
parasitic inductance possible).

For PCBs with a total thickness of < 1.575 mm (62 mils), the best placement location is on
the PCB backside, within the device footprint (in the empty cross with an absence of vias).
V

and GND vias corresponding to the supply of interest should be identified in the via

CC

array. Where space is available, 0402 mounting pads should be added and connected to
these vias.

For PCBs with a total thickness > 1.575 mm (62 mils), the best placement location could be
on the PCB top surface. The depth of the V
factor: if the V
surface is optimal; if the V

plane is in the PCB stackup’s top half, capacitor placement on the top PCB

CC

plane is in the PCB stackup’s bottom half, capacitor

CC

placement on the bottom PCB surface is optimal.

Any 0402 capacitors placed outside the device footprint (whether on the top or bottom
surface) should be within 0.5 inch of the device’s outer edge.

The capacitor mounting (solder lands, traces, and vias) must be optimized for low
inductance. Vias should be butted against the pads with no trace length in-between. These
vias should be at the sides of the pads if at all possible (see Figure 2-2C). Via placement at
the sides of the pads decreases the mounting’s parasitic inductance by increasing the
mutual inductive coupling of one via to the other. Dual vias can be placed on both sides of
the pads (see Figure 2-2D) for even lower parasitic inductance, but with diminishing
returns.

plane of interest in the PCB stackup is the key

CC

Many manufacturing rules prevent mounting any device within 0.1 inch of the FPGA on
the PCB top surface. Manufacturing rules can also prevent capacitor placement on the PCB
backside within the device footprint, whether because backside mounting is prohibited or
geometries necessary to fit mounting pads in the tight spaces between vias are too small
for reliable soldering. These rules decrease the available options for capacitor placement
but do not preclude meeting the Xilinx placement recommendations. Discuss any specific
concerns with a PCB fabrication, assembly, and/or quality department.

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UG393 (v1.1) April 29, 2010

Chapter 2: Power Distribution System

0402 Land Pattern

End Vias

Long Traces

(A) (C)(B) (D)

UG393_c2_02_091809

0402 Land Pattern

End Vias

0.381 mm
(15 mils)

0.635 mm
(25 mils)

1.07 mm
(42 mils)

0.61mm
(24 mils)

0402 Land Pattern

Double Side Vias

0.762 mm
(30 mils)

0.381 mm
(15 mils)

0.61mm
(24 mils)

0402 Land Pattern

Side Vias

0.762 mm
(30 mils)

0.381 mm
(15 mils)

0.61mm
(24 mils)

Not Recommended.

Connecting Trace is Too Long

X-Ref Target - Figure 2-2

Basic PDS Principles

Figure 2-2: Example 0402 Capacitor Land and Mounting Geometries

Noise Limits

The purpose of the PDS and the properties of its components are discussed in this section.
The important aspects of capacitor placement, capacitor mounting, PCB geometry, and
PCB stackup recommendations are also described.

In the same way that devices in a system have a requirement for the amount of current
consumed by the power system, there is also a requirement for the cleanliness of the
power. This cleanliness requirement specifies a maximum amount of noise present on the
power supply, often referred to as ripple voltage (V
all Spartan-6 FPGAs, require that V
V

value. This means that the peak-to-peak V

CC

nominal V
power supplies: V

. In this document the term VCC is used generically for the following FPGA

CC

CCINT

, V

CCO

supplies not fluctuate more than ±5% of the nominal

CC

RIPPLE

, V

CCAUX

, and V

REF

exactly the nominal value provided in the data sheet. If not, then V

). Most digital devices, including

RIPPLE

must be no more than 10% of the

. This assumes that nominal VCC is

must be adjusted

RIPPLE

to a value correspondingly less than 10%.

The power consumed by a digital device varies over time and this variance occurs on all
frequency scales, creating a need for a wide-band PDS to maintain voltage stability.

• Low-frequency variance of power consumption is usually the result of devices or

large portions of devices being enabled or disabled. This variance occurs in time
frames from milliseconds to days.

• High-frequency variance of power consumption is the result of individual switching

events inside a device. This occurs on the scale of the clock frequency and the first few
harmonics of the clock frequency up to about 1 GHz.

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UG393 (v1.1) April 29, 2010

Basic PDS Principles

+

FPGA

L

REGULATOR

L

DECOUPLING

C

DECOUPLING

Voltage

Regulator

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Because the voltage level of VCC for a device is fixed, changing power demands are
manifested as changing current demand. The PDS must accommodate these variances of
current draw with as little change as possible in the power-supply voltage.

When the current draw in a device changes, the PDS cannot respond to that change
instantaneously. As a consequence, the voltage at the device changes for a brief period
before the PDS responds. Two main causes for this PDS lag correspond to the two major
PDS components: the voltage regulator and decoupling capacitors.

The first major component of the PDS is the voltage regulator. The voltage regulator
observes its output voltage and adjusts the amount of current it is supplying to keep the
output voltage constant. Most common voltage regulators make this adjustment in
milliseconds to microseconds. Voltage regulators effectively maintain the output voltage
for events at all frequencies from DC to a few hundred kHz, depending on the regulator
(some are effective at regulating in the low MHz). For transient events that occur at
frequencies above this range, there is a time lag before the voltage regulator responds to
the new current demand level.

For example, if the device’s current demand increases in a few hundred picoseconds, the
voltage at the device sags by some amount until the voltage regulator can adjust to the
new, higher level of required current. This lag can last from microseconds to milliseconds.
A second component is needed to substitute for the regulator during this time, preventing
the voltage from sagging.

This second major PDS component is the decoupling capacitor (also known as a bypass
capacitor). The decoupling capacitor works as the device’s local energy storage. The
capacitor cannot provide DC power because it stores only a small amount of energy
(voltage regulator provides DC power). This local energy storage should respond very
quickly to changing current demands. The capacitors effectively maintain power-supply
voltage at frequencies from hundreds of kHz to hundreds of MHz (in the milliseconds to
nanoseconds range). Decoupling capacitors are not useful for events occurring above or
below this range.

For example, if current demand in the device increases in a few picoseconds, the voltage at
the device sags by some amount until the capacitors can supply extra charge to the device.
If current demand in the device maintains this new level for many milliseconds, the
voltage-regulator circuit, operating in parallel with the decoupling capacitors, replaces the
capacitors by changing its output to supply this new level of current.

Figure 2-3 shows the major PDS components: the voltage regulator, the decoupling

capacitors, and the active device being powered (FPGA).

X-Ref Target - Figure 2-3

Spartan-6 FPGA PCB Design and Pin Planning www.xilinx.com 21
UG393 (v1.1) April 29, 2010

Figure 2-3: Simplified PDS Circuit

Chapter 2: Power Distribution System

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TRANSIENT

FPGA

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Z

P

(f)

V

RIPPLE

+

−

+

V

Figure 2-4 shows a simplified PDS circuit with all reactive components represented by a

frequency-dependent resistor.

X-Ref Target - Figure 2-4

Role of Inductance

Inductance is the property of the capacitors and the PCB current paths that slows down
changes in current flow. Inductance is the reason why capacitors cannot respond
instantaneously to transient currents or to changes that occur at frequencies higher than
their effective range.

Figure 2-4: Further Simplified PDS Circuit

Inductance can be thought of as the momentum of charge. Charge moving through a
conductor represents some amount of current. If the level of current changes, the charge
moves at a different rate. Because momentum (stored magnetic-field energy) is associated
with this charge, some amount of time and energy is required to slow down or speed up
the charge flow. The greater the inductance, the greater the resistance to change, and the
longer the time required for the current level to change. A voltage develops across the
inductance as this change occurs.

The PDS, made up of a regulator and multiple stages of decoupling capacitors,
accommodates the device current demand and responds to current transients as quickly as
possible. When these current demands are not met, the voltage across the device's power
supply changes. This is observed as noise. Inductance in the current path of the capacitors
should be minimized, because it retards the ability of decoupling capacitors to quickly
respond to changing current demands.

Inductances occur between the FPGA device and capacitors and between the capacitors
and the voltage regulator (see Figure 2-3). These inductances occur as parasitics in the
capacitors and in all PCB current paths. It is important that each of these parasitics be
minimized.

Capacitor Parasitic Inductance

The capacitance value is often considered the bypass capacitors’s most important
characteristic. In power system applications, the parasitic inductance (ESL) has the same or
greater importance. Capacitor package dimensions (body size) determine the amount of
parasitic inductance. Physically small capacitors usually have lower parasitic inductance
than physically large capacitors.

22 www.xilinx.com Spartan-6 FPGA PCB Design and Pin Planning

UG393 (v1.1) April 29, 2010