SP701 Evaluaon Board
User Guide
UG1319 (v1.0) July 12, 2019
Revision History
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Revision History
Section
07/12/2019 Version 1.0
Initial release. N/A
Revision Summary
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SP701 Board User Guide 2
Table of Contents
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Revision History...............................................................................................................2
Chapter 1: Introduction.............................................................................................. 4
Overview.......................................................................................................................................4
Additional Resources.................................................................................................................. 5
Block Diagram..............................................................................................................................5
Board Features............................................................................................................................ 6
Board Specifications....................................................................................................................7
Chapter 2: Board Setup and Configuration......................................................9
Electrostatic Discharge Caution.................................................................................................9
Board Components..................................................................................................................... 9
Default Switch and Jumper Settings....................................................................................... 12
Spartan-7 Device Configuration.............................................................................................. 13
Chapter 3: Board Component Descriptions................................................... 15
Overview.....................................................................................................................................15
Component Descriptions......................................................................................................... 15
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SP701 Board User Guide 3
Appendix A: VITA 57.1 FMC Connector Pinouts............................................44
Appendix B: Xilinx Design Constraints............................................................. 45
Overview.....................................................................................................................................45
Appendix C: Regulatory and Compliance Information........................... 46
CE Information...........................................................................................................................46
Compliance Markings............................................................................................................... 47
Appendix D: Additional Resources and Legal Notices.............................48
Xilinx Resources.........................................................................................................................48
Documentation Navigator and Design Hubs.........................................................................48
References..................................................................................................................................49
Please Read: Important Legal Notices................................................................................... 50
Introduction
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Overview
Chapter 1: Introduction
Chapter 1
The SP701 evaluaon board is based on the XC7S100FGGA676 device, a member of the Xilinx
7 series FPGA family. It is opmized for low cost, low power, and high I/O performance. It comes
with advanced high-performance FPGA logic based on real6-input look up table (LUT), 36 Kb
dual-port block RAM, support for DDR3L interface up to 1866 Mb/s, XADC with 12-bit
1 MSPA ADC with on-chip thermal and supply sensors, and powerful clock management les
(CMTs). The board is designed for high-performance and lower power with a 28 nm, 1V core
voltage process. For lower power, it has a 0.9V core voltage opon.
Table 1: XC7S100 Resources
Spartan®-7 FPGA
Resources
Logic Resources Part Number XCS7100
Logic Cells 102,400
Slices 16,000
CLB Flip-flops 128,000
Memory Resources Max. Distributed RAM (Kb) 1,100
Block RAM/FIFO w/EEC (36 Kb each) 120
Total Block RAM (Kb) 4,320
Clock Resources Clock Mgmt. Tiles (1 MMCM + 1 PLL) 8
I/O Resources Max. Single-Ended I/O Pins 400
Max. Differential I/O Pins 192
Embedded Hard IP
Resources
Speed Grades Commercial Temp (C) -1, -2
DSP Slices 160
Analog Mixed Signal (AMS)/XADC 1
Configuration AES/HMAC Blocks 1
Industrial Temp (I) -1, -2, -1L
Expanded Temp (Q) -1
Component Features
®
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SP701 Board User Guide 4
Package Body Area (mm) Ball Pitch (mm) Available User I/O:
3.3V SelectIO™
technology HR I/O
FGGA676 27 x 27 1.0 400
The following table lists the models for this board. See the SP701 evaluaon board product page
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for details.
Table 2: Models of SP701 Boards
Kit Description
EK-S7-SP701-G Xilinx Spartan-7 FPGA SP701 Evaluation Kit
EK-S7-SP701-G-J Xilinx Spartan-7 FPGA SP701 Evaluation Kit, Japan Specific
Additional Resources
See Appendix D: Addional Resources and Legal Noces for references to documents, les, and
resources relevant to the SP701 evaluaon board.
Chapter 1: Introduction
Block Diagram
The following gure shows the various components of the SP701 Evaluaon Board.
Figure 1: SP701 Evaluation Board Block Diagram
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SP701 Board User Guide 5
Board Features
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The SP701 evaluaon board features are listed here. Detailed informaon for each feature is
provided in Chapter 3: Board Component Descripons.
• XC7S100-2FGGA676 package
• Form factor: 6.00 in (152.4 mm) square, 0.08844 in (88.44 mils) thick
• Conguraon:
○ Quad SPI (QSPI) 1 Gb
○ Direct QSPI ash program header
○ USB-to-JTAG bridge
• DDR3L SDRAM memory:
○ 256Mx16 4 Gb DDR3-1866
Chapter 1: Introduction
• 32 Kb I2C EEPROM for hardware ID storage accessible by FPGA and System Controller
• Clocks:
○ I2C programmable SYSCLK oscillator 33.33 MHz
• VITA 57.1 FMC-LPC connector:
○ 34 dierenal pairs or 68 single-ended LA[00-33] bus
• 2x 10/100/1000 Tri-Speed Ethernet PHY
• Mobile industry processor interface (MIPI) features:
○ MIPI-CSI Camera Serial Interface (for PCAM 5C from Digilent)
○ MIPI-DSI Display Serial Interface
• HDMI output (1.4 specicaon support)
• USB-UART interface:
○ FT4232H JTAG/3xUART
• System Controller (MSP430)
• I2C Bus
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SP701 Board User Guide 6
• 6x Pmod rt-angle receptacle (Digilent Pmod IF 1.2.0 specicaon support)
• General purpose I/O (GPIO):
○ 8x LED (GPIO_LED[0:7]) (acve-High)
○ 5x pushbuon switch, geographical, GPIO_SW_[N,E,S,W,C] (acve-High)
○ 1x pushbuon switch, CPU_RESET (acve-High)
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○ 2x 8-pole DIP switch, GPIO_DIP_SW_B[0:15] (acve-High)
• Operaonal Switches:
○ Power On-O slide switch
○ PROG_B pushbuon switch (acve-Low)
○ 4-pole conguraon mode DIP switch M[0:2]_0_SW, INIT_B_0 (acve-Low)
• Operaonal Status LEDs:
○ Done
○ Power On
○ PG (Power Good)
• Power System:
Chapter 1: Introduction
○ V
○ I2C telemetry on 12V input and V
0.90V or 1.00V (I2C selectable)
ccint
Board Specifications
Dimensions
• Height: 6.00 in (152.4 mm)
• Width: 6.00 in (152.4 mm)
• Thickness: 0.08844 in (88.44 mils)
Note: A 3D model of this board is not available.
See the SP701 board website documentaon tab (Board Files check box) for the XDC lisng and
board schemacs (0381874).
Environmental
ccint
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SP701 Board User Guide 7
• Temperature
○ Operang: 0°C to +45°C
○ Storage: –25°C to +60°C
• Humidity
○ 10% to 90% non-condensing
Operating Voltage
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Chapter 1: Introduction
• +12V
DC
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SP701 Board User Guide 8
Chapter 2
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Board Setup and Configuration
Electrostatic Discharge Caution
CAUTION! ESD can damage electronic components when they are improperly handled, and can result in total or
intermient failures. Always follow ESD-prevenon procedures when removing and replacing components.
To prevent ESD damage:
• Use an ESD wrist or ankle strap and ensure that it makes skin contact. Connect the equipment
end of the strap to an unpainted metal surface on the chassis.
• Avoid touching the adapter against your clothing. The wrist strap protects components from
ESD on the body only.
• Handle the adapter by its bracket or edges only. Avoid touching the printed circuit board or
the connectors.
• Put the adapter down only on an anstac surface such as the bag supplied in your kit.
• If you are returning the adapter to Xilinx® Product Support, place it back in its anstac bag
immediately.
Board Components
The following gure shows the SP701 board component locaons. Each numbered component is
keyed to the table in Board Component Locaon.
IMPORTANT! The following gure is for visual reference only and might not reect the current revision of the
board. There could be mulple revisions of this board. The specic details concerning the dierences between
revisions are not captured in this document. This document is not intended to be a reference design guide and the
informaon herein should not be used as such. Always refer to the schemac, layout, and XDC les of the specic
SP701 version of interest for such details.
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SP701 Board User Guide 9
Chapter 2: Board Setup and Configuration
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Figure 2: SP701 Evaluation Board Components
Round callout references a component
00
on the front side of the board
14
16
7
4
Square callout references a component
00
on the back side of the board
18
27
17
5
15
21
26
34
28
3
1
22
12
20
2
31
13
19
30
8 9
33
29
32
6
25
10 11
35
23
24
X22622-070119
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SP701 Board User Guide 10
Chapter 2: Board Setup and Configuration
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Board Component Location
The following table idenes the components, references the respecve schemac (0381874)
page numbers, and links to a detailed funconal descripon of the components and board
features in Chapter 3: Board Component Descripons.
Table 3: Board Component Locations
Schematic
Callout Feature [#] = Bottom Notes
1 Spartan-7 XC7S100 FPGA (U1) XC7S100-2FGGA676C
2 1Gb QSPI Flash 4-bit [U3] Micron MT25QL01GBBB8ESF-0SIT 4
3 Direct QSPI Flash Program Header (J37) 2X5 1.27 mm
pitch male header
4 DDR3L Component Memory (U12) Micron MT41K256M16TW 7
5 IIC EEPROM [U27] ST Microelectronics M24C32-WDW6 8
6 I2C Programmable Clock, LVDS [U45] Silicon Labs SI570BAB000875DG
7 FMC LPC Connector J21 Samtec ASP-134603-01 15-16
8 10/100/1000 Mb/s Tri-speed Ethernet PHY (RGMII)
with RJ45, SGMII mode only (U14), (J9)
9 10/100/1000 Mb/s Tri-speed Ethernet PHY (RGMII)
with RJ45, SGMII mode only (U16), (J11)
10 MIPI-CSI Camera Serial Interface (J8) TE Connectivity 1-1734248-5 8
11 MIPI-DSI Display Serial Interface (J20) Hirose FH34SJ-34S-0.5SH 11
12 HDMI Video Output (U18), (J13) Analog Devices ADV7511KSTZ, Molex
13 USB UART Interface, USB bridge (U6) with micro-AB
USB connector (J5), and 2x7 2 mm keyed program
cable connector (J3)
14 System Controller MSP430 (U25) TI MSP430F5342IRGZ 19
15 System Controller MSP430 4-pole GPIO DIP switch
(SW2)
16 System Controller MSP430 reset pushbutton (SW3,
active-Low)
17 I2C Bus Switch (U23)
I2C_MSP430 Bus Port Expander (U24)
18 PMOD Interface 6x 2x6 Rt-Angle receptacles (J14-J19) Sullins PPPC062LJBN-RC 17
19 User 8x LEDs, Green, active-High (D6-D13) Lumex SML-LX0603GW-TR 21
20 User 6x pushbutton, active-High (SW4-SW9) E-Switch TL3301EF100QG 21
21 User 2x 8-pole DIP switch, 1.27 mm pitch, active-High
(SW10, SW12)
22 FPGA Program pushbutton, (SW1), active-Low Omron B3U-1000P 3
23 Power Input Connector, 2x6 (J30) Molex-39-30-1060 23
24 Power On/Off Slide Switch (SW11) C&K 1101M2S3AQE2 23
25 SP701 Board Power System, MPS (top and bottom) Monolithic Power Systems (MPS) 24-26
Samtec FTSH-105-01-F-DV 3
(default 33.3333 MHz)
TI DP83867IRPAP with Wurth
7499111221A RJ45 (with magnetics)
TI DP83867IRPAP with Wurth
7499111221A RJ45 (with magnetics)
47151-1001
FTDI FT4232HQ_QFN64, Hirose ZX62DAB-5P8(30), Molex 87832-1420
Wurth 416131160804 19
Panasonic EVQ-11L07K 19
TI TCA9548A
TI TCA6416A
Wurth 416131160808 21
Page
Number
8
9
10
12,13
3, 5
19
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SP701 Board User Guide 11
Chapter 2: Board Setup and Configuration
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Table 3: Board Component Locations (cont'd)
Callout Feature [#] = Bottom Notes
26 Configuration options, FPGA U1 configuration mode
4-pole DIP switch, (SW13)
27 XADC/SYSMON 2x10 shrouded/keyed
Header (J24)
28 Encryption Key Battery Backup Circuit
Battery retainer [B1]
29 System Controller MSP430 2x7 0.1"
JTAG Header (J22)
30 Ethernet 1x4 0.1" JTAG header (J10) Sullins PBC36DAAN 9
Wurth 416131160804 3
Samtec TST-110-01-G-D 22
Keystone 2998 3
Tyco 5103308-2 19
Default Switch and Jumper Settings
Schematic
Page
Number
Jumpers
Default jumper sengs are listed in the following table. The table also references the respecve
schemac (0381874) page numbers.
Table 4: Default Jumper Settings
Schematic
Callout Jumper Type Function Default
31 J38 2-pin male header USB JTAG enable Jumper ON 5
32 J2 2-pin male header FPGA U1 CFGBVS_0 Jumper OFF 3
33 J6 2-pin male header FT4232 U6 SUSPEND Jumper OFF 5
34 J23 3-pin male header FPGA U1 XADC_VCC Select 2-3 22
34 J25 3-pin male header REF3012 U29 Vin Select 1-2 22
34 J26 3-pin male header FPGA U1 XADC_VREFP Select 1-2 22
34 J27 2-pin male header GND-to-J28/L12 Jumper ON 22
34 J28 2-pin male header J28/L12-to-XADC_GND Jumper OFF 22
35 J35 2-pin male header Power System Inhibit Jumper OFF 23
Page
Number
Switches
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SP701 Board User Guide 12
Default switch sengs are listed in the following table. The table also references the respecve
schemac (0381874) page numbers.
Chapter 2: Board Setup and Configuration
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Table 5: Default Switch Settings
Callout Switch Type Function Default
15 SW2 5-pole DIP MSP430 U25 GPIO OFF, OFF, OFF, OFF,
21 SW10 8-pole FPGA U1 GPIO All OFF 21
21 SW12 8-pole FPGA U1 GPIO All OFF 21
FPGA U1 Configuration:
Switch OFF = 1 = High; ON = 0 = Low
Mode = SW13[4:2] = Mode[2:0]
26 SW13 4-pole DIP
JTAG: SW13[4:2] = OFF, ON, OFF =
Mode[101]
MASTER SPI: SW13[4:2] = ON, ON, OFF =
Mode[001]
SW13[1] = INIT_B, OFF = OPEN, ON = 0 =
Low
OFF
OFF, ON, OFF=101
OFF
Schematic
Page
Number
19
3
Spartan-7 Device Configuration
The SP701 board supports two of the 7 series FPGA conguraon modes:
• Master SPI ash memory using the onboard QSPI ash memory
• JTAG
○ J5 micro-AB USB-JTAG interface connector
- USB A-to-micro-B PC to SP701 cable connecon
○ J3 2x7 2 mm keyed JTAG pod at cable header
- Plaorm cable USB II/Parallel cable IV type connecon
Each conguraon interface corresponds to one or more conguraon modes and bus widths as
listed in the following table.
The mode switches M2, M1, and M0 are on SW13 posions 4, 3, and 2, respecvely.
Table 6: SP701 Board FPGA Configuration Modes
Configuration Mode SW13 Switch Settings M[2:0]
Master SPI 001
JTAG (default) 101
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SP701 Board User Guide 13
See Table 5, callout 26 SW13 for more informaon on the switch posion.
Chapter 2: Board Setup and Configuration
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JTAG
Vivado® design tools, Xilinx® SDK, or third-party tools can establish a JTAG connecon to the
Spartan-7 device through the FTDI FT4232 USB-to-JTAG/USB UART device (U6) connected to
the micro-USB connector (J5).
To use the JTAG pod cable with the FTDI used for the UART only on J5, remove the jumper from
J38 when using the PC4/USB cable for JTAG.
To use the FPGA programming tools to detect the JTAG chain and program the FPGA, connect
the PC4/USB JTAG pod at cable to the 2x7 2 mm keyed shrouded connector J3.
Quad SPI
To boot from the QSPI nonvolale conguraon memory, use the following procedure:
1. Store a valid Spartan-7 boot image in the SPI ash device. See the 7 Series FPGAs
Conguraon User Guide (UG470) for informaon on programming the SPI.
2. Set the boot mode pins SW13 [4:2] MODE[2:0] as indicated in the table in Spartan-7 Device
Conguraon for Master SPI.
3. Power-cycle the SP701 board. SW13 is callout 30 in Board Components.
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SP701 Board User Guide 14
Chapter 3
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Board Component Descriptions
Overview
This chapter provides a detailed funconal descripon of the components and features of the
SP701 board. Board Component Locaon idenes the components, references the respecve
schemac page numbers, and links to the corresponding detailed funconal descripon in this
chapter. Component locaons are shown in Board Components.
Component Descriptions
Spartan-7 XC7S100 FPGA
[Figure 2, callout 1]
A Spartan-7 XC7S100-2FGGA676C FPGA is installed on the SP701 evaluaon board. The
Spartan-7 family is opmized for low cost, lowest power, and high I/O performance.
For further informaon on Spartan-7 FPGAs, see 7 Series FPGAs Data Sheet: Overview (DS180).
Encryption Key Battery Backup Circuit
The XC7S100 FPGA U1 implements bitstream encrypon key technology. The SP701 board
provides the encrypon key backup baery circuit shown in the following gure.
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SP701 Board User Guide 15
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