SP623
Spartan-6 FPGA
GTP Transceiver
Characterization Board
User Guide
UG751 (v1.0) May 22, 2010
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Revision History
The following table shows the revision history for this document.
Date Version Revision
05/22/10 1.0 Initial Xilinx release.
SP623 Board User Guide www.xilinx.com UG751 (v1.0) May 22, 2010
Table of Contents
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Preface: About This Guide
Guide Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Typographical. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Online Document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Chapter 1: SP623 Board Features and Operation
SP623 Board Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Board Power and Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Onboard Power Regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
GTP Transceiver Power Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
FPGA Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
PROG Push Button . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
DONE LED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
INIT LED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
System ACE Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
System ACE Controller Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Configuration Address DIP Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
JTAG Isolation Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
200 MHz 2.5V LVDS Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
SuperClock-2 Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
User SMA Global Clock Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
User LEDs (Active High) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
User DIP Switches (Active High). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
User Push Buttons (Active High) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
User Test I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
GTP Transceiver Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
GTP Transceiver Clock Input SMAs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
USB to UART Bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
FMC HPC Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2
I
C Bus Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Appendix A: Default Jumper Positions
Appendix B: VITA 57.1 FMC HPC Connector Pinout
Appendix C: SP623 Master UCF Listing
Appendix D: References
SP623 Board User Guide www.xilinx.com 3
UG751 (v1.0) May 22, 2010
4 www.xilinx.com SP623 Board User Guide
UG751 (v1.0) May 22, 2010
About This Guide
This document describes the basic setup, features, and operation of the SP623
Spartan-6® FPGA GTP transceiver characterization board. The SP623 board provides the
hardware environment for characterizing and evaluating the GTP transceivers available
on the Spartan-6 XC6SLX150T-3FGG676 FPGA.
Guide Contents
This user guide contains the following chapters and appendices:
• Chapter 1, SP623 Board Features and Operation describes the components, features,
and operation of the SP623 Spartan-6 FPGA GTP transceiver characterization board.
• Appendix A, Default Jumper Positions lists the jumpers that must be installed on the
board for proper operation.
• Appendix B, VITA 57.1 FMC HPC Connector Pinout provides a pinout reference for
the FPGA mezzanine card (FMC) connector.
• Appendix C, SP623 Master UCF Listing provides a listing of the SP623 master user
constraints file (UCF).
• Appendix D, References provides a list of references and links to related
documentation.
Preface
Conventions
Typographical
To find additional documentation, see the Xilinx website at:
http://www.xilinx.com/support/documentation/index.htm
To search the Answer Database of silicon, software, and IP questions and answers, or to
create a technical support WebCase, see the Xilinx website at:
http://www.xilinx.com/support
This document uses the following conventions. An example illustrates each convention.
The following typographical conventions are used in this document:
.
.
SP623 Board User Guide www.xilinx.com 5
UG751 (v1.0) May 22, 2010
Preface: About This Guide
Courier font
Convention Meaning or Use Example
Messages, prompts, and
program files that the system
displays
speed grade: - 100
Courier bold
Helvetica bold
Italic font
Online Document
The following conventions are used in this document:
Convention Meaning or Use Example
Blue text
Literal commands that you enter
in a syntactical statement
Commands that you select from
a menu
Keyboard shortcuts Ctrl+C
Variables in a syntax statement
for which you must supply
values
References to other manuals
Emphasis in text
Cross-reference link to a location
in the current document
ngdbuild design_name
File → Open
ngdbuild design_name
See the Command Line Tools User
Guide for more information.
If a wire is drawn so that it
overlaps the pin of a symbol, the
two nets are not connected.
See the section “Additional
Resources” for details.
Refer to “Title Formats” in
Chapter 1 for details.
Blue, underlined text
Hyperlink to a website (URL)
Go to http://www.xilinx.com
for the latest speed files.
6 www.xilinx.com SP623 Board User Guide
UG751 (v1.0) May 22, 2010
Chapter 1
SP623 Board Features and Operation
This chapter describes the components, features, and operation of the
SP623 Spartan®-6 FPGA GTP transceiver characterization board. The SP623 board
provides the hardware environment for characterizing and evaluating the GTP
transceivers available on the Spartan-6 XC6SLX150T-3FGG676 FPGA.
SP623 Board Features
• Spartan-6 XC6SLX150T-3FGG676 FPGA
• On-board power supplies for all necessary voltages
• Power supply jacks for optional use of external power supplies
• JTAG configuration port for use with Platform Cable USB or Parallel Cable III/IV
cables
•System ACE™ controller
• Power module supporting all Spartan-6 FPGA GTP transceiver power requirements
• A fixed, 200 MHz 2.5V LVDS oscillator wired to global clock inputs
• One pair of global clock inputs with SMA connectors
• SuperClock-2 module supporting multiple frequencies
• 16 pairs of SMA connectors for the GTP transceivers
• 8 pairs of SMA connectors for GTP transceiver clock inputs
•Power status LEDs
• General purpose DIP switches, LEDs, push buttons, and test I/O
• Two VITA 57.1 FMC HPC connectors
• USB to UART bridge
2
•I
C Bus
The SP623 board block diagram is shown in Figure 1-1.
Caution!
standard ESD prevention measures when handling the board.
SP623 Board User Guide www.xilinx.com 7
UG751 (v1.0) May 22, 2010
The SP623 board can be damaged by electrostatic discharge (ESD). Follow
Chapter 1: SP623 Board Features and Operation
UG751_c1_01_050410
Spartan-6 FPGA
XC6SLX150T-3FGG676
Power In 12V
FMC Interface
FMC1 and FMC2
ANSI/VITA 57.1-2008 v1.1
USB to UART
Bridge
System ACE
Controller
I2C Bus Management
GTP Transceiver
Power Module
FPGA Power Source
On-board Regulation:
VCCINT 1.2V @ 20 Amps
VCCO 2.5V @ 20 Amps
VCCAUX 2.5V @ 20 Amps
Auxiliary Power
On-board Regulation:
5.0V @ 8 Amps
3.3V @ 20 Amps
2.5V @ 20 Amps
GTP Dual 123
Transceiver and
Clock SMAs
GTP Dual 101
Transceiver and
Clock SMAs
User GPIO
Push Buttons,
DIP Switches,
and LEDs
200 MHz LVDS Clock,
User SMA Clocks
SuperClock-2 Module
GTP Dual 245
Transceiver and
Clock SMAs
GTP Dual 267
Transceiver and
Clock SMAs
X-Ref Target - Figure 1-1
Detailed Description
Figure 1-1: SP623 Board Block Diagram
Figure 1-2 shows the SP623 board described in this user guide. Each numbered feature that
is referenced in Figure 1-2 is described in the sections that follow.
Note:
board.
The image in Figure 1-2 is for reference only and might not reflect the current revision of the
8 www.xilinx.com SP623 Board User Guide
UG751 (v1.0) May 22, 2010
X-Ref Target - Figure 1-2
UG751_c1_02_041310
1a 19 6
1e 1520a 20b 16 14 13
1c
4 5 937
8
1d 1d
1e
1b
1g
1f
1f
2
1f
1h
11
1l
10
12
17
18
18
21
1a Main power switch (SW1) 8 Configuration address DIP switch (SW3)
1b 12V mini-fit connector (J122) 9 JTAG isolation jumpers (J22, J23, J195, J196)
1c 12V ATX connector (J141) 10 200 MHz 2.5V LVDS oscillator (U7)
1d Power regulation jumpers (J30, J31, J33, J102, J104,J105) 11 SuperClock-2 module
1e Regulation inhibit (J14, J19) 12 User SMA global clock inputs (J167, J168)
1f External power supply jacks 13 User LEDs, active-High (DS10 - DS17)
1g TI PMBus connector (J6) 14 User DIP switches, active-High (SW1 - SW8)
1h GTP transceiver power supply module 15 User push buttons, active-High (SW4, SW6)
1i MGTAVCCPLL isolation jumper (J3) 16 User test I/O (J44)
2 FPGA configuration connector (J1) 17 GTP transceiver pins
3 PROG push button, active-Low (SW5) 18 GTP transceiver clock input SMAs
4 DONE LED (DS6) 19 USB to UART bridge (U26)
5 INIT LED (DS20) 20a FMC1 (J112)
6 System ACE controller (U25) 20b FMC2 (J113)
7 System ACE reset, active-Low (SW2) 21 I2C bus management (U14)
Detailed Description
Figure 1-2: Detailed Description of SP623 Board Components
SP623 Board User Guide www.xilinx.com 9
UG751 (v1.0) May 22, 2010
Chapter 1: SP623 Board Features and Operation
Power Management
Numbers 1a through 1i refer to the callouts in Figure 1-2:
1a: Main power switch (SW1)
1b: 12V mini-fit connector (J122)
1c: 12V ATX connector (J141)
1d: Power regulation jumpers (J30, J31, J33, J102, J104, J105)
1e: Regulation inhibit (J14, J19)
1f: External power supply jacks (J5, J98, J173, J174, J175, J177, J178, J189, J220, J223, J227,
J234)
1g: TI PMBus cable connector (J6)
1h: GTP power supply module
1i: MGTAVCCPLL isolation jumper (J3)
Board Power and Switch
The SP623 board is powered through J122 using the 12V AC adapter included with the
board. J122 is a 6-pin (2 x 3) right angle Mini-Fit type connector.
Power can also be provided through:
• Connector J141 which accepts an ATX hard disk 4-pin power plug
• Jack J234 which can be used to connect to a bench-top power supply
Caution!
The ATX 6-pin connector has a different pinout than J122. Connecting an ATX 6-pin connector
into J122 will damage the SP623 board and void the board warranty.
Caution! Do NOT apply power to J122 and connectors J141 and/or J234 at the same time.
Doing so will damage the SP623 board.
The SP623 board power is turned on or off by switch SW1. When the switch is in the ON
position, power is applied to the board and a green LED (DS36) illuminates.
Do NOT plug a PC ATX power supply 6-pin connector into J122 on the SP623 board.
10 www.xilinx.com SP623 Board User Guide
UG751 (v1.0) May 22, 2010
Onboard Power Regulation
External Supply Jacks
VCCINT
VCCAUX
VCCO
VCC2V5
UG751_c1_03_041510
VCC3V3
VCC5
Power Supply
Switching Module PTD08A020W
1.2V at 20A max
J223 J227
J175
J173
J178 J189
J174
J98
Power Controller 1
UCD9240PFC U8
U10
Switching Module PTD08A020W
2.5V at 20A max U12
Switching Module PTD08A020W
2.5V at 20A max
PTV12010WAD DC-DC Converter
5.0V at 8A max
MGTAVTT
Power Controller 2
UCD9240PFC
GTP Transceiver
Power Module
U19
U23
Switching Module PTD08A020W
3.3V at 20A max U22
U15
Switching Module PTD08A020W
2.5V at 20A max U13
12V PWR IN
J122 or J141
or J234
MGTAVCC
Figure 1-3 shows the on-board power supply architecture.
Detailed Description
X-Ref Target - Figure 1-3
Note:
Power regulation jumpers are not shown in Figure 1-3.
SP623 Board User Guide www.xilinx.com 11
Figure 1-3: SP623 Board Power Supply Block Diagram
The SP623 board uses power regulators and PMBus compliant digital PWM system
controllers from Texas Instruments to supply the core and auxiliary voltages listed in
Tab le 1-1 . The board can also be configured to use external bench power supply for each
voltage. See Using External Power Sources.
UG751 (v1.0) May 22, 2010
Chapter 1: SP623 Board Features and Operation
Table 1-1: Onboard Power System Devices
Device
Core voltage controller and regulators
UCD9240PFC U8 PMBus compliant digital PWM system
PTD08A020W U10 Adjustable switching regulator
PTD08A020W U12 Adjustable switching regulator
PTD08A020W U13 Adjustable switching regulator
Auxiliary voltage controller and regulators
UCD9240PFC U19 PMBus compliant digital PWM system
PTD08A020W U23 Adjustable switching regulator
PTD08A020W U22 Adjustable switching regulator
5V auxiliary power
Reference
Designator
Description
controller (address = 52)
20A, 0.6V to 3.6V
20A, 0.6Vto 3.6V
20A, 0.6V to 3.6V
controller (address = 53)
20A, 0.6V to 3.6V
20A, 0.6V to 3.6V
Power Rail
Net Name
VCCINT 1.2V J102 J223
VCCAUX 2.5V J104 J227
VCCO 2.5V J105 J98
VCC2V5 2.5V J31 J175
VCC3V3 3.3V J30 J174
Typical
Voltag e
Power
Regulation
Jumper
External
Supply
Jack
PTV12010WAD U15 Adjustable switching regulator
8A, 1.2V to 5.5V
Using External Power Sources
The maximum output current rating for each power regulator is listed in Tab le 1-1 . If a
design exceeds this value on any power rail, power for that rail must be supplied through
the external power jack using a supply capable of providing the required current.
Each power rail has a corresponding jack and jumper that is used to supply voltage to the
rail using an external power supply. The jack, jumper, and regulator for each power rail is
listed in Ta bl e 1-1 .
Caution!
power rail through its corresponding supply jack.
The power regulation jumper must be removed before applying external power to the
Disabling Onboard Power
Voltage regulators U10, U12, U13, U22, and U23 are disabled by installing a jumper across
pins 2–3 of header J14. Voltage regulator U15 is disabled by installing a jumper across pins
2–3 of header J19.
Default Jumper Positions
A list of shunts and shorting plugs and their required positions for normal board operation
is provided in Appendix A, Default Jumper Positions.
VCC5 5.0V J33 J173
12 www.xilinx.com SP623 Board User Guide
UG751 (v1.0) May 22, 2010
Detailed Description
UG751_c1_04_041510
Monitoring Voltage and Current
Voltage and current monitoring and control are available for selected power rails through
Texas Instruments' Fusion Digital Power graphical user interface (GUI). Both onboard TI
power controllers are wired to the same PMBus. The PMBus connector, J6, is provided for
use with the TI USB Interface Adapter PMBus pod and associated TI GUI.
References
More information about the power system components used by the SP623 board are
available from the Texas Instruments digital power website at:
http://www.ti.com/ww/en/analog/digital-power/index.html
GTP Transceiver Power Module
The GTP transceiver power module supplies MGTAVCC and MGTAVTT voltages to the
FPGA GTP transceivers. Two power modules are provided with the SP623 board. Either of
the power modules can be plugged into connectors J34 and J179 in the outlined and labeled
power module location shown in Figure 1-4.
X-Ref Target - Figure 1-4
Figure 1-4: Mounting Location, GTP Transceiver Power Module
Tab le 1- 2 describes the nominal voltage values for the MGTAVCC and MGTAVTT power
rails. It also lists the maximum current ratings for each rail supplied by either module
included with the SP623 board.
Table 1-2: GTP Transceiver Power Module
Maximum Current Rating Regulation Jumper
Power Supply
Rail Net Name
MGTAVCC 1.2V 16A 8A JP1 N/A J178
MGTAVTT 1.2V 12A 6A JP2 N/A J189
Typical
Voltag e
Linear
Technology
Module
Texas
Instruments
Module
Linear
Technology
Module
Texas
Instruments
Module
External
Supply
Jack
The GTP transceiver power rails also have corresponding input voltage jacks to supply
each voltage independently from a bench-top power supply (See External Supply Jack
column in Ta bl e 1 -2 ). To supply power externally to one or both rails when the
SP623 Board User Guide www.xilinx.com 13
UG751 (v1.0) May 22, 2010
Chapter 1: SP623 Board Features and Operation
UG751_c1_05_041910
J178J3J189
J5
MGTAVTT
GTP Power
Supply Module
MGTAVCC
MGTAVCCPLL
12V DC
VCC5
VCC3V3
External Supply Jacks
Linear Technology Module is installed, place jumpers on JP1 and/or JP2 across pins 2–3
(OFF position).
Note:
external supply to its corresponding supply jack.
The power regulation jumper must be placed in the OFF position before connecting an
The Texas Instruments module does not have voltage regulation jumpers and must be
removed from the board before providing external power to the GTP transceiver rails.
MGTAVCCPLL Rail
The GTP transceiver power module also supplies the MGTAVCCPLL rail through the J3
shorting plug (Figure 1-5). This jumper connects MGTAVCC and MGTAVCCPLL rails by
default. The MGTAVCCPLL rail can also be supplied from an external 1.2V (nominal)
power supply by removing the J3 shorting plug and then connecting the power supply
output to J5.
X-Ref Target - Figure 1-5
FPGA Configuration
[Figure 1-2, callout 2]
The FPGA is configured in JTAG mode only using one of the following options:
•Platform Cable USB
•Parallel Cable IV
• Parallel Cable III
• System ACE controller
Detailed information on the System ACE controller is available in
DS080
, System ACE CompactFlash Solution.
The FPGA is configured through one of the aforementioned cables by connecting the cable
to the download cable connector, J1.
The FPGA is configured through the System ACE controller by setting the 3-bit
configuration address DIP switches (SW3) to select one of eight bitstreams stored on a
CompactFlash memory card (see Configuration Address DIP Switches, page 16).
Note:
cable is used, causing no disruption in the JTAG chain.
The System ACE controller is bypassed when the flying wire leads or the Parallel Cable IV
Figure 1-5: MGTAVCCPLL Isolation Jumper
14 www.xilinx.com SP623 Board User Guide
UG751 (v1.0) May 22, 2010
X-Ref Target - Figure 1-6
J1
Detailed Description
The JTAG chain of the board is illustrated in Figure 1-6 (the four System ACE interface
isolation jumpers described in JTAG Isolation Jumpers are not shown). Shorting pins 1–2
on header J162 automatically bypasses the FMC modules and the GTP transceiver power
supply module in the chain.
U20
PWR Module
JTAG Cable
Connector
FPGA
TDO
TDI
U1 U25
System ACE Controller
CFGTDI
CFGTDO
JTAG
BUFF/DRVR
3.3V2.5V
TSTTDO
TSTTDI
J162
Figure 1-6: JTAG Chain
J35
J36
J37
TDI
TDO
FMC1
TDI
TDO
FMC2
TDI
TDO
UG751_c1_06_041510
PROG Push Button
[Figure 1-2, callout 3]
Pressing the PROG push button (SW5) grounds the active-Low program pin of the FPGA.
DONE LED
[Figure 1-2, callout 4]
The DONE LED (DS6) indicates the status of the DONE pin of the FPGA. When the DONE
pin is high, DS6 lights indicating the FPGA is successfully configured.
INIT LED
[Figure 1-2, callout 5]
The INIT LED (DS20) lights during FPGA initialization.
SP623 Board User Guide www.xilinx.com 15
UG751 (v1.0) May 22, 2010
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