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This document describes the basic setup, features, and operation of the SP623
Spartan-6® FPGA GTP transceiver characterization board. The SP623 board provides the
hardware environment for characterizing and evaluating the GTP transceivers available
on the Spartan-6 XC6SLX150T-3FGG676 FPGA.
Guide Contents
This user guide contains the following chapters and appendices:
•Chapter 1, SP623 Board Features and Operation describes the components, features,
and operation of the SP623 Spartan-6 FPGA GTP transceiver characterization board.
•Appendix A, Default Jumper Positions lists the jumpers that must be installed on the
board for proper operation.
•Appendix B, VITA 57.1 FMC HPC Connector Pinout provides a pinout reference for
the FPGA mezzanine card (FMC) connector.
•Appendix C, SP623 Master UCF Listing provides a listing of the SP623 master user
constraints file (UCF).
•Appendix D, References provides a list of references and links to related
documentation.
Preface
Conventions
Typographical
To find additional documentation, see the Xilinx website at:
To search the Answer Database of silicon, software, and IP questions and answers, or to
create a technical support WebCase, see the Xilinx website at:
http://www.xilinx.com/support
This document uses the following conventions. An example illustrates each convention.
The following typographical conventions are used in this document:
.
.
SP623 Board User Guidewww.xilinx.com5
UG751 (v1.0) May 22, 2010
Preface: About This Guide
Courier font
ConventionMeaning or UseExample
Messages, prompts, and
program files that the system
displays
speed grade: - 100
Courier bold
Helvetica bold
Italic font
Online Document
The following conventions are used in this document:
ConventionMeaning or UseExample
Blue text
Literal commands that you enter
in a syntactical statement
Commands that you select from
a menu
Keyboard shortcutsCtrl+C
Variables in a syntax statement
for which you must supply
values
References to other manuals
Emphasis in text
Cross-reference link to a location
in the current document
ngdbuild design_name
File → Open
ngdbuild design_name
See the Command Line Tools User
Guide for more information.
If a wire is drawn so that it
overlaps the pin of a symbol, the
two nets are not connected.
See the section “Additional
Resources” for details.
Refer to “Title Formats” in
Chapter 1 for details.
Blue, underlined text
Hyperlink to a website (URL)
Go to http://www.xilinx.com
for the latest speed files.
6www.xilinx.comSP623 Board User Guide
UG751 (v1.0) May 22, 2010
Chapter 1
SP623 Board Features and Operation
This chapter describes the components, features, and operation of the
SP623 Spartan®-6 FPGA GTP transceiver characterization board. The SP623 board
provides the hardware environment for characterizing and evaluating the GTP
transceivers available on the Spartan-6 XC6SLX150T-3FGG676 FPGA.
SP623 Board Features
•Spartan-6 XC6SLX150T-3FGG676 FPGA
•On-board power supplies for all necessary voltages
•Power supply jacks for optional use of external power supplies
•JTAG configuration port for use with Platform Cable USB or Parallel Cable III/IV
cables
•System ACE™ controller
•Power module supporting all Spartan-6 FPGA GTP transceiver power requirements
•A fixed, 200 MHz 2.5V LVDS oscillator wired to global clock inputs
•One pair of global clock inputs with SMA connectors
The SP623 board is powered through J122 using the 12V AC adapter included with the
board. J122 is a 6-pin (2 x 3) right angle Mini-Fit type connector.
Power can also be provided through:
•Connector J141 which accepts an ATX hard disk 4-pin power plug
•Jack J234 which can be used to connect to a bench-top power supply
Caution!
The ATX 6-pin connector has a different pinout than J122. Connecting an ATX 6-pin connector
into J122 will damage the SP623 board and void the board warranty.
Caution! Do NOT apply power to J122 and connectors J141 and/or J234 at the same time.
Doing so will damage the SP623 board.
The SP623 board power is turned on or off by switch SW1. When the switch is in the ON
position, power is applied to the board and a green LED (DS36) illuminates.
Do NOT plug a PC ATX power supply 6-pin connector into J122 on the SP623 board.
10www.xilinx.comSP623 Board User Guide
UG751 (v1.0) May 22, 2010
Onboard Power Regulation
External Supply Jacks
VCCINT
VCCAUX
VCCO
VCC2V5
UG751_c1_03_041510
VCC3V3
VCC5
Power Supply
Switching Module PTD08A020W
1.2V at 20A max
J223J227
J175
J173
J178 J189
J174
J98
Power Controller 1
UCD9240PFCU8
U10
Switching Module PTD08A020W
2.5V at 20A maxU12
Switching Module PTD08A020W
2.5V at 20A max
PTV12010WAD DC-DC Converter
5.0V at 8A max
MGTAVTT
Power Controller 2
UCD9240PFC
GTP Transceiver
Power Module
U19
U23
Switching Module PTD08A020W
3.3V at 20A maxU22
U15
Switching Module PTD08A020W
2.5V at 20A maxU13
12V PWR IN
J122 or J141
or J234
MGTAVCC
Figure 1-3 shows the on-board power supply architecture.
Detailed Description
X-Ref Target - Figure 1-3
Note:
Power regulation jumpers are not shown in Figure 1-3.
SP623 Board User Guidewww.xilinx.com11
Figure 1-3: SP623 Board Power Supply Block Diagram
The SP623 board uses power regulators and PMBus compliant digital PWM system
controllers from Texas Instruments to supply the core and auxiliary voltages listed in
Tab le 1-1 . The board can also be configured to use external bench power supply for each
voltage. See Using External Power Sources.
UG751 (v1.0) May 22, 2010
Chapter 1: SP623 Board Features and Operation
Table 1-1: Onboard Power System Devices
Device
Core voltage controller and regulators
UCD9240PFCU8PMBus compliant digital PWM system
PTD08A020WU10Adjustable switching regulator
PTD08A020WU12Adjustable switching regulator
PTD08A020WU13Adjustable switching regulator
Auxiliary voltage controller and regulators
UCD9240PFCU19PMBus compliant digital PWM system
PTD08A020WU23Adjustable switching regulator
PTD08A020WU22Adjustable switching regulator
5V auxiliary power
Reference
Designator
Description
controller (address = 52)
20A, 0.6V to 3.6V
20A, 0.6Vto 3.6V
20A, 0.6V to 3.6V
controller (address = 53)
20A, 0.6V to 3.6V
20A, 0.6V to 3.6V
Power Rail
Net Name
VCCINT1.2VJ102J223
VCCAUX2.5VJ104J227
VCCO2.5VJ105J98
VCC2V52.5VJ31J175
VCC3V33.3VJ30J174
Typical
Voltag e
Power
Regulation
Jumper
External
Supply
Jack
PTV12010WADU15Adjustable switching regulator
8A, 1.2V to 5.5V
Using External Power Sources
The maximum output current rating for each power regulator is listed in Tab le 1-1 . If a
design exceeds this value on any power rail, power for that rail must be supplied through
the external power jack using a supply capable of providing the required current.
Each power rail has a corresponding jack and jumper that is used to supply voltage to the
rail using an external power supply. The jack, jumper, and regulator for each power rail is
listed in Ta bl e 1-1 .
Caution!
power rail through its corresponding supply jack.
The power regulation jumper must be removed before applying external power to the
Disabling Onboard Power
Voltage regulators U10, U12, U13, U22, and U23 are disabled by installing a jumper across
pins 2–3 of header J14. Voltage regulator U15 is disabled by installing a jumper across pins
2–3 of header J19.
Default Jumper Positions
A list of shunts and shorting plugs and their required positions for normal board operation
is provided in Appendix A, Default Jumper Positions.
VCC55.0VJ33J173
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UG751 (v1.0) May 22, 2010
Detailed Description
UG751_c1_04_041510
Monitoring Voltage and Current
Voltage and current monitoring and control are available for selected power rails through
Texas Instruments' Fusion Digital Power graphical user interface (GUI). Both onboard TI
power controllers are wired to the same PMBus. The PMBus connector, J6, is provided for
use with the TI USB Interface Adapter PMBus pod and associated TI GUI.
References
More information about the power system components used by the SP623 board are
available from the Texas Instruments digital power website at:
The GTP transceiver power module supplies MGTAVCC and MGTAVTT voltages to the
FPGA GTP transceivers. Two power modules are provided with the SP623 board. Either of
the power modules can be plugged into connectors J34 and J179 in the outlined and labeled
power module location shown in Figure 1-4.
X-Ref Target - Figure 1-4
Figure 1-4: Mounting Location, GTP Transceiver Power Module
Tab le 1- 2 describes the nominal voltage values for the MGTAVCC and MGTAVTT power
rails. It also lists the maximum current ratings for each rail supplied by either module
included with the SP623 board.
Table 1-2: GTP Transceiver Power Module
Maximum Current RatingRegulation Jumper
Power Supply
Rail Net Name
MGTAVCC1.2V16A8AJP1N/AJ178
MGTAVTT1.2V12A6AJP2N/AJ189
Typical
Voltag e
Linear
Technology
Module
Texas
Instruments
Module
Linear
Technology
Module
Texas
Instruments
Module
External
Supply
Jack
The GTP transceiver power rails also have corresponding input voltage jacks to supply
each voltage independently from a bench-top power supply (See External Supply Jack
column in Ta bl e 1 -2 ). To supply power externally to one or both rails when the
SP623 Board User Guidewww.xilinx.com13
UG751 (v1.0) May 22, 2010
Chapter 1: SP623 Board Features and Operation
UG751_c1_05_041910
J178J3J189
J5
MGTAVTT
GTP Power
Supply Module
MGTAVCC
MGTAVCCPLL
12V DC
VCC5
VCC3V3
External Supply Jacks
Linear Technology Module is installed, place jumpers on JP1 and/or JP2 across pins 2–3
(OFF position).
Note:
external supply to its corresponding supply jack.
The power regulation jumper must be placed in the OFF position before connecting an
The Texas Instruments module does not have voltage regulation jumpers and must be
removed from the board before providing external power to the GTP transceiver rails.
MGTAVCCPLL Rail
The GTP transceiver power module also supplies the MGTAVCCPLL rail through the J3
shorting plug (Figure 1-5). This jumper connects MGTAVCC and MGTAVCCPLL rails by
default. The MGTAVCCPLL rail can also be supplied from an external 1.2V (nominal)
power supply by removing the J3 shorting plug and then connecting the power supply
output to J5.
X-Ref Target - Figure 1-5
FPGA Configuration
[Figure 1-2, callout 2]
The FPGA is configured in JTAG mode only using one of the following options:
•Platform Cable USB
•Parallel Cable IV
•Parallel Cable III
•System ACE controller
Detailed information on the System ACE controller is available in
DS080
, System ACE CompactFlash Solution.
The FPGA is configured through one of the aforementioned cables by connecting the cable
to the download cable connector, J1.
The FPGA is configured through the System ACE controller by setting the 3-bit
configuration address DIP switches (SW3) to select one of eight bitstreams stored on a
CompactFlash memory card (see Configuration Address DIP Switches, page 16).
Note:
cable is used, causing no disruption in the JTAG chain.
The System ACE controller is bypassed when the flying wire leads or the Parallel Cable IV
Figure 1-5: MGTAVCCPLL Isolation Jumper
14www.xilinx.comSP623 Board User Guide
UG751 (v1.0) May 22, 2010
X-Ref Target - Figure 1-6
J1
Detailed Description
The JTAG chain of the board is illustrated in Figure 1-6 (the four System ACE interface
isolation jumpers described in JTAG Isolation Jumpers are not shown). Shorting pins 1–2
on header J162 automatically bypasses the FMC modules and the GTP transceiver power
supply module in the chain.
U20
PWR Module
JTAG Cable
Connector
FPGA
TDO
TDI
U1U25
System ACE Controller
CFGTDI
CFGTDO
JTAG
BUFF/DRVR
3.3V2.5V
TSTTDO
TSTTDI
J162
Figure 1-6: JTAG Chain
J35
J36
J37
TDI
TDO
FMC1
TDI
TDO
FMC2
TDI
TDO
UG751_c1_06_041510
PROG Push Button
[Figure 1-2, callout 3]
Pressing the PROG push button (SW5) grounds the active-Low program pin of the FPGA.
DONE LED
[Figure 1-2, callout 4]
The DONE LED (DS6) indicates the status of the DONE pin of the FPGA. When the DONE
pin is high, DS6 lights indicating the FPGA is successfully configured.
INIT LED
[Figure 1-2, callout 5]
The INIT LED (DS20) lights during FPGA initialization.
SP623 Board User Guidewww.xilinx.com15
UG751 (v1.0) May 22, 2010
Chapter 1: SP623 Board Features and Operation
System ACE Controller
[Figure 1-2, callout 6]
The onboard System ACE controller (U25) allows storage of multiple configuration files on
a CompactFlash card. These configuration files can be used to program the FPGA. The
CompactFlash card connects to the CompactFlash card connector (U24) located directly
below the System ACE controller on the back-side of the board.
System ACE Controller Reset
[Figure 1-2, callout 7]
Pressing push button SW2 (RESET) resets the System ACE controller. Reset is an
active-Low input.
Configuration Address DIP Switches
[Figure 1-2, callout 8]
DIP switch SW3 selects one of the eight configuration bitstream addresses in the
CompactFlash memory card. The switch settings for selecting each address are identified
in Tab le 1- 3.
Table 1-3: SW3 DIP Switch Configuration
AddressADR2ADR1ADR0
0O
1OOC
2OCO
3OCC
4COO
5COC
6CCO
7CCC
Notes:
1. O indicates the open switch position (logic 0).
2. C indicates the closed switch position (logic 1).
JTAG Isolation Jumpers
[Figure 1-2, callout 9]
The group of four 2-pin headers shown in Figure 1-7 provide the option to isolate the
FPGA JTAG interface from the System ACE controller by removing the shunts from all
four headers. The FPGA JTAG interface can also be driven directly from these headers by
attaching the flying wire JTAG cable to pin 2 of each header. Figure 1-7 shows a more
detailed representation of the isolation jumpers as part of the broader JTAG chain in
Figure 1-6.
(1)
OO
(2)
16www.xilinx.comSP623 Board User Guide
UG751 (v1.0) May 22, 2010
X-Ref Target - Figure 1-7
UG751_c1_07_050110
J196
J195
J23
J22
System ACE
Controller
CFGTCK
CFGTDI
CFGTDO
CFGTMS
U25
TCK
TDO
TDI
TMS
FPGA
U1
Figure 1-7: JTAG Isolation Jumpers
Tab le 1- 4 indicates the FPGA pin name associated with each jumper.
Table 1-4: JTAG Isolation Jumpers
Reference DesignatorFPGA Pin Name
J22TMS
Detailed Description
J23TDI
J195TDO
J196TCK
200 MHz 2.5V LVDS Oscillator
[Figure 1-2, callout 10]
The SP623 board has one 2.5V LVDS differential 200 MHz oscillator (U7) connected to the
FPGA global clock inputs. Ta bl e 1 -5 lists the FPGA pin connections to the LVDS oscillator.
The 200 MHz differential clock is enabled by placing two shunts (P, N) across J188 header
pins 1
–3 and 2–4 (LVDS).
Table 1-5: LVDS Oscillator Global Clock Connections
FPGA PinNet NameU7 Pin
V23IO_LVDS_CLK_P4
W24IO_LVDS_CLK_N5
SuperClock-2 Module
[Figure 1-2, callout 11]
The SuperClock-2 module connects to the clock module interface connector (J32) and
provides a programmable, low-noise clock source for the SP623 board. The clock module
SP623 Board User Guidewww.xilinx.com17
UG751 (v1.0) May 22, 2010
maps to FPGA I/O by way of 24 control pins, 3 LVDS pairs, 1 regional clock pair, and 1
reset pin. Ta bl e 1- 6 shows the FPGA I/O mapping for the SuperClock-2 module interface.
The SP623 board also supplies VCC5, VCC3V3, VCC2V5, and VCCO input power to the
clock module interface.
Chapter 1: SP623 Board Features and Operation
Table 1-6: SuperClock-2 FPGA I/O Mapping
FPGA PinNet NameJ32 Pin
F12CM_LVDS1_P1
E12CM_LVDS1_N3
V12CM_LVDS2_P9
W12CM_LVDS2_N11
G12CM_LVDS3_P17
F11CM_LVDS3_N19
U25CM_GCLK_P25
U26CM_GCLK_N27
U20CM_CTRL_061
U19CM_CTRL_163
AA24CM_CTRL_265
AA23CM_CTRL_367
T20CM_CTRL_469
T19CM_CTRL_571
U22CM_CTRL_673
U21CM_CTRL_775
AE26CM_CTRL_877
AE25CM_CTRL_979
Y26CM_CTRL_1081
Y24CM_CTRL_1183
AC26CM_CTRL_1285
AC25CM_CTRL_1387
AB26CM_CTRL_1489
AB24CM_CTRL_1591
AD26CM_CTRL_1693
AD24CM_CTRL_1795
AA26CM_CTRL_1897
AA25CM_CTRL_1999
W26CM_CTRL_20101
W25CM_CTRL_21103
V24CM_CTRL_22105
T23CM_CTRL_23107
T22CM_RST66
18www.xilinx.comSP623 Board User Guide
UG751 (v1.0) May 22, 2010
User SMA Global Clock Inputs
[Figure 1-2, callout 12]
The SP623 board provides two single-ended clock input SMAs that can be used for
connecting to an external function generator. These clock inputs can alternatively be used
as a differential pair. The FPGA clock pins are connected to the SMAs as shown in
Tab le 1- 7.
Detailed Description
Note:
used.
Table 1-7: SMA Clock Input Connections
Jumpers should NOT be installed on AFX SEL headers J99 and J100 if these clock inputs are
FPGA PinNet NameSMA Connector
R25SMA_CLK_PJ167
R26SMA_CLK_NJ168
User LEDs (Active High)
[Figure 1-2, callout 13]
DS10 through DS17 are eight active-High LEDs that are connected to user I/O on the
FPGA as shown in Ta bl e 1 -8 . These LEDs can be used to indicate status, or any other
purpose determined by the user.
Table 1-8: User LEDs
FPGA PinNet Name
L21LED1DS17
L20LED2DS16
M23LED3DS15
Reference
Designator
M21LED4DS14
N26LED5DS13
N25LED6DS12
L26LED7DS11
L25LED8DS10
User DIP Switches (Active High)
[Figure 1-2, callout 14]
DIP switch SW7 provides a set of eight active-High switches that connect to user I/O on
the FPGA, as shown in Tab le 1- 9. These pins can be used to set control pins, or other
functions determined by the user.
SP623 Board User Guidewww.xilinx.com19
UG751 (v1.0) May 22, 2010
Chapter 1: SP623 Board Features and Operation
Table 1-9: User DIP Switches
FPGA PinNet Name
J26SW1
J25SW2
K26SW3
K24SW4
G26SW5
G25SW6
H26SW7
H24SW8
User Push Buttons (Active High)
[Figure 1-2, callout 15]
SW5 and SW6 are active-High user push buttons that are connected to user I/O pins on the
FPGA, as identified in Ta bl e 1 -1 0. These switches can be used for any purpose determined
by the user.
Table 1-10: User Push Buttons
Reference
Designator
SW7
User Test I/O
[Figure 1-2, callout 16]
A standard 2 x 6, 100-mil pitch header (J44) brings out 6 FPGA I/O for test purposes.
Tab le 1-11 lists these pins.
Table 1-11: User Test I/O
FPGA PinNet Name
M26PB_SW1SW6
M24PB_SW2SW4
FPGA PinNet NameJ44 Pin
U1IO_L40N_M3DQ7_3_U12
U2IO_L40P_M3DQ6_3_U24
V1IO_L39N_M3LDQSN_3_V16
V3IO_L39P_M3LDQS_3_V38
AA13IO_L36N_2_AA1310
AB13IO_L36P_2_AB1312
Reference
Designator
20www.xilinx.comSP623 Board User Guide
UG751 (v1.0) May 22, 2010
X-Ref Target - Figure 1-8
UG751_c1_07_052210
267 ClocksDual 267Dual 123
245 ClocksDual 245Dual 101
123 Clocks
101 Clocks
Detailed Description
GTP Transceiver Pins
[Figure 1-2, callout 17]
All FPGA GTP transceiver pins are connected to differential SMA connector pairs. The
GTP transceivers are grouped into four sets of two (referred to as Duals) which share two
differential reference clock pin-pairs (Figure 1-8). The transceiver pins and their
corresponding SMA connector are identified in Tab le 1 -1 2.
Figure 1-8: GTP Transceiver and Reference Clock SMA Locations
Table 1-12: GTP Transceiver Pins
FGPA PinNet NameSMA ConnectorTrace Length (Mils)
D7101_RX0_PJ514,253
C7101_RX0_NJ524,253
B6101_TX0_PJ533,634
A6101_TX0_NJ543,633
D9101_RX1_PJ553,861
C9101_RX1_NJ563,861
SP623 Board User Guidewww.xilinx.com21
UG751 (v1.0) May 22, 2010
Chapter 1: SP623 Board Features and Operation
Table 1-12: GTP Transceiver Pins (Cont’d)
FGPA PinNet NameSMA ConnectorTrace Length (Mils)
B8101_TX1_PJ572,503
A8101_TX1_NJ582,502
D17123_RX0_PJ683,531
C17123_RX0_NJ693,531
B18123_TX0_PJ673,340
A18123_TX0_NJ663,340
D19123_RX1_PJ653,665
C19123_RX1_NJ643,664
B20123_TX1_PJ632,939
A20123_TX1_NJ622,941
AC8245_RX0_PJ484,316
AD8245_RX0_NJ734,315
AE7245_TX0_PJ743,616
AF7245_TX0_NJ753,615
AC10245_RX1_PJ763,865
AD10245_RX1_NJ773,865
AE9245_TX1_PJ782,563
AF9245_TX1_NJ792,562
AC18267_RX0_PJ843,328
AD18267_RX0_NJ853,327
AE19267_TX0_PJ863,719
AF19267_TX0_NJ873,718
AC20267_RX1_PJ883,952
AD20267_RX1_NJ893,952
AE21267_TX1_PJ903,238
AF21267_TX1_NJ913,239
22www.xilinx.comSP623 Board User Guide
UG751 (v1.0) May 22, 2010
GTP Transceiver Clock Input SMAs
[Figure 1-2, callout 18]
The SP623 board provides differential SMA connectors that can be used for connecting an
external function generator to all GTP transceiver reference clock inputs of the FPGA. The
FPGA reference clock pins are connected to the SMA connectors as shown in Tab le 1 -1 3.
Table 1-13: GTP Transceiver Clock Inputs to the FPGA
FPGA PinNet NameSMA Connector
B10101_REFCLK0_PJ59
A10101_REFCLK0_NJ60
D11101_REFCLK1_PJ49
C11101_REFCLK1_NJ50
D15123_REFCLK0_PJ70
C15123_REFCLK0_NJ61
B16123_REFCLK1_PJ72
A16123_REFCLK1_NJ71
Detailed Description
AE11245_REFCLK0_PJ80
AF11245_REFCLK0_NJ81
AC12245_REFCLK1_PJ82
AD12245_REFCLK1_NJ83
AC16267_REFCLK0_PJ92
AD16267_REFCLK0_NJ93
AE17267_REFCLK1_PJ94
AF17267_REFCLK1_NJ95
USB to UART Bridge
[Figure 1-2, callout 19]
Communications between the SP623 board and a host computer are through a USB Mini-B
cable connected to J9. Control is provided by U26, a USB to UART bridge (Silicon
Laboratories CP2103). Tab le 1-1 4 lists the pin assignments and signals for the USB
connector J9.
Table 1-14: USB Mini-B Connector Pin Assignments and Signals
J9 PinSignal NameDescription
1VBUS+5V from host system (not used)
2USB_DATA_N Bidirectional differential serial data (N-side)
3USB_DATA_PBidirectional differential serial data (P-side)
4GROUNDSignal ground
SP623 Board User Guidewww.xilinx.com23
UG751 (v1.0) May 22, 2010
Chapter 1: SP623 Board Features and Operation
The CP2103 supports an IO voltage range of 1.8V to 2.5V on the SP623 board. The
connections between the FPGA and CP2103 should use the LVCMOS25 IO standard.
UART IP (for example, Xilinx® XPS UART Lite) must be implemented in the FPGA fabric.
The FPGA supports the USB to UART bridge using four signal pins:
•Transmit (TX)
•Receive (RX)
•Request to Send (RTS)
•Clear to Send (CTS).
Connections of these signals between the FPGA and the CP2103 at U26 are listed in
Tab le 1-1 5.
Table 1-15: FPGA to U26 (CP2103 USB to UART Bridge) Connections
FPGA PinFPGA FunctionNet NameU26 PinU26 Function
L23RTS, outputUSB_CTS22CTS, input
L23CTS, inputUSB_RTS23RTS, output
N20TX, data outUSB_RX24RXD, data in
N19RX, data inUSB_TX25TXD, data out
The bridge device also provides as many as 4 GPIO signals that can be defined by the user
for status and control information (Ta bl e 1 -1 6).
Table 1-16: CP2103 USB to UART Bridge User GPIO
FPGA PinNet NameU26 Pin
P22USB_GPIO019
P21USB_GPIO118
N22USB_GPIO217
N21USB_GPIO316
A royalty-free software driver named Virtual COM Port (VCP) is available from Silicon
Laboratories. This driver permits the CP2103 USB to UART bridge to appear as a COM
port to the host computer communications application software (for example,
HyperTermimal or TeraTerm). The VCP driver must be installed on the host computer
prior to establishing communications with the SP623 board.
FMC HPC Connectors
[Figure 1-2, callouts 20a, and 20b]
The SP623 board features two high pin count (HPC) connectors as defined by the VITA
57.1.1 FMC specification. Each FMC HPC connector is a 10 x 40 position socket that is fully
populated with 400 pins. See Appendix B, VITA 57.1 FMC HPC Connector Pinout for a
cross-reference of signal names to pin coordinates.
The FMC1 HPC connector at J112 on the SP623 board provides connectivity for:
•58 differential user-defined pairs:
•34 LA pairs
•24 HA pairs
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Detailed Description
•3 differential clocks
The FMC2 HPC connector at J113 on the SP623 board provides connectivity for:
•57 differential user-defined pairs:
•34 LA pairs
•23 HA pairs
•2 differential clocks
Note:
(non-adjustable). The 2.5V rail cannot be turned off. The VITA 57.1 FMC interfaces on the SP623
board are compatible with 2.5V mezzanine cards capable of supporting 2.5V V
The V
voltage for the FMC HPC connectors on the SP623 board is fixed at 2.5V
ADJ
.
ADJ
The connections for the FMC1 and FMC2 connectors are identified in Tab le 1 -17 and
Tab le 1-1 8, respectively.
Table 1-17: Vita 57.1 FMC1 HPC Connections at J112
FPGA PinNet NameFMC Pin
T3FMC1_CLK0_M2C_PH4
T1FMC1_CLK0_M2C_NH5
B14FMC1_CLK1_M2C_PG2
A14FMC1_CLK1_M2C_NG3
V4FMC1_CLK2_M2C_PK4
W3FMC1_CLK2_M2C_NK5
R2FMC1_HA00_CC_PF4
R1FMC1_HA00_CC_NF5
M4FMC1_HA01_CC_PE2
N3FMC1_HA01_CC_NE3
N2FMC1_HA02_PK7
N1FMC1_HA02_NK8
M3FMC1_HA03_PJ6
M1FMC1_HA03_NJ7
L2FMC1_HA04_PF7
L1FMC1_HA04_NF8
K3FMC1_HA05_PE6
K1FMC1_HA05_NE7
J2FMC1_HA06_PK10
J1FMC1_HA06_NK11
H3FMC1_HA07_PJ9
H1FMC1_HA07_NJ10
G2FMC1_HA08_PF10
G1FMC1_HA08_NF11
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Chapter 1: SP623 Board Features and Operation
Table 1-17: Vita 57.1 FMC1 HPC Connections at J112 (Cont’d)
FPGA PinNet NameFMC Pin
F3FMC1_HA09_PE9
F1FMC1_HA09_NE10
E2FMC1_HA10_PK13
E1FMC1_HA10_NK14
D3FMC1_HA11_PJ12
D1FMC1_HA11_NJ13
J4FMC1_HA12_PF13
J3FMC1_HA12_NF14
L9FMC1_HA13_PE12
L8FMC1_HA13_NE13
L4FMC1_HA14_PJ15
L3FMC1_HA14_NJ16
M8FMC1_HA15_PF16
M6FMC1_HA15_NF17
K5FMC1_HA16_PE15
J5FMC1_HA16_NE16
L7FMC1_HA17_CC_PK16
L6FMC1_HA17_CC_NK17
B2FMC1_HA18_PJ18
B1FMC1_HA18_NJ19
L10FMC1_HA19_PF19
K10FMC1_HA19_NF20
G4FMC1_HA20_PE18
G3FMC1_HA20_NE19
J9FMC1_HA21_PK19
J7FMC1_HA21_NK20
C2FMC1_HA22_PJ21
C1FMC1_HA22_NJ22
K9FMC1_HA23_PK22
K8FMC1_HA23_NK23
U14.13FMC1_I2C_SCL
U14.12FMC1_I2C_SDA
(1)
(1)
C30
C31
E13FMC1_LA00_CC_PG6
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Table 1-17: Vita 57.1 FMC1 HPC Connections at J112 (Cont’d)
FPGA PinNet NameFMC Pin
D13FMC1_LA00_CC_NG7
C13FMC1_LA01_CC_PD8
A13FMC1_LA01_CC_ND9
H9FMC1_LA02_PH7
G9FMC1_LA02_NH8
A3FMC1_LA03_PG9
A2FMC1_LA03_NG10
F9FMC1_LA04_PH10
E8FMC1_LA04_NH11
D5FMC1_LA05_PD11
C5FMC1_LA05_ND12
H7FMC1_LA06_PC10
Detailed Description
G7FMC1_LA06_NC11
H10FMC1_LA07_PH13
G10FMC1_LA07_NH14
B4FMC1_LA08_PG12
A4FMC1_LA08_NG13
F10FMC1_LA09_PD14
E10FMC1_LA09_ND15
B5FMC1_LA10_PC14
A5FMC1_LA10_NC15
H8FMC1_LA11_PH16
G8FMC1_LA11_NH17
J11FMC1_LA12_PG15
G11FMC1_LA12_NG16
H12FMC1_LA13_PD17
G13FMC1_LA13_ND18
K12FMC1_LA14_PC18
J12FMC1_LA14_NC19
F7FMC1_LA15_PH19
F6FMC1_LA15_NH20
J15FMC1_LA16_PG18
H15FMC1_LA16_NG19
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Chapter 1: SP623 Board Features and Operation
Table 1-17: Vita 57.1 FMC1 HPC Connections at J112 (Cont’d)
FPGA PinNet NameFMC Pin
B12FMC1_LA17_CC_PD20
A12FMC1_LA17_CC_ND21
J16FMC1_LA18_CC_PC22
J17FMC1_LA18_CC_NC23
F16FMC1_LA19_PH22
E16FMC1_LA19_NH23
C3FMC1_LA20_PG21
B3FMC1_LA20_NG22
G15FMC1_LA21_PH25
F15FMC1_LA21_NH26
F18FMC1_LA22_PG24
E18FMC1_LA22_NG25
G16FMC1_LA23_PD23
F17FMC1_LA23_ND24
F20FMC1_LA24_PH28
E20FMC1_LA24_NH29
H17FMC1_LA25_PG27
G17FMC1_LA25_NG28
C21FMC1_LA26_PD26
B21FMC1_LA26_ND27
G6FMC1_LA27_PC26
F5FMC1_LA27_NC27
H18FMC1_LA28_PH31
H19FMC1_LA28_NH32
B22FMC1_LA29_PG30
A22FMC1_LA29_NG31
G19FMC1_LA30_PH34
F19FMC1_LA30_NH35
B23FMC1_LA31_PG33
A23FMC1_LA31_NG34
D21FMC1_LA32_PH37
D22FMC1_LA32_NH38
E6FMC1_LA33_PG36
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Table 1-17: Vita 57.1 FMC1 HPC Connections at J112 (Cont’d)
FPGA PinNet NameFMC Pin
E5FMC1_LA33_NG37
E3FMC1_PRSNT_M2CH2
U20.13FMC1_TCK_BUF
J36.1FMC1_TDI
J36.3FMC1_TDO
U20.16TMS_BUF
Notes:
1. This signal is not directly connected to the FPGA. The value in the
leftmost column represents the device and pin the signal is
connected to. For example, U14.13 = U14 pin 13.
(1)
(1)
(1)
(1)
D29
D30
D31
D33
Table 1-18: Vita 57.1 FMC2 HPC Connections at J113
FPGA PinNet NameFMC Pin
Detailed Description
U23FMC2_CLK0_M2C_PH4
U24FMC2_CLK0_M2C_NH5
AD14FMC2_CLK1_M2C_PG2
AF14FMC2_CLK1_M2C_NG3
R7FMC2_HA00_CC_PF4
R6FMC2_HA00_CC_NF5
U4FMC2_HA02_PK7
U3FMC2_HA02_NK8
V5FMC2_HA03_PJ6
W5FMC2_HA03_NJ7
U9FMC2_HA04_PF7
U8FMC2_HA04_NF8
U7FMC2_HA05_PE6
T6FMC2_HA05_NE7
AB3FMC2_HA06_PK10
AB1FMC2_HA06_NK11
AD3FMC2_HA07_PJ9
AD1FMC2_HA07_NJ10
AC2FMC2_HA08_PF10
AC1FMC2_HA08_NF11
AE2FMC2_HA09_PE9
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Chapter 1: SP623 Board Features and Operation
Table 1-18: Vita 57.1 FMC2 HPC Connections at J113 (Cont’d)
FPGA PinNet NameFMC Pin
AE1FMC2_HA09_NE10
AA2FMC2_HA10_PK13
AA1FMC2_HA10_NK14
Y3FMC2_HA11_PJ12
Y1FMC2_HA11_NJ13
W2FMC2_HA12_PF13
W1FMC2_HA12_NF14
R10FMC2_HA13_PE12
T9FMC2_HA13_NE13
P3FMC2_HA14_PJ15
P1FMC2_HA14_NJ16
N6FMC2_HA15_PF16
P6FMC2_HA15_NF17
P5FMC2_HA16_PE15
R5FMC2_HA16_NE16
N8FMC2_HA17_CC_PK16
N7FMC2_HA17_CC_NK17
R4FMC2_HA18_PJ18
R3FMC2_HA18_NJ19
R9FMC2_HA19_PF19
P8FMC2_HA19_NF20
N5FMC2_HA20_PE18
N4FMC2_HA20_NE19
P10FMC2_HA21_PK19
N9FMC2_HA21_NK20
M10FMC2_HA22_PJ21
M9FMC2_HA22_NJ22
Y6FMC2_HA23_PK22
Y5FMC2_HA23_NK23
U14.13FMC2_I2C_SCL
U14.12FMC2_I2C_SDA
(1)
(1)
C30
C31
AB14FMC2_LA00_CC_PG6
AC14FMC2_LA00_CC_NG7
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Table 1-18: Vita 57.1 FMC2 HPC Connections at J113 (Cont’d)
FPGA PinNet NameFMC Pin
AE13FMC2_LA01_CC_PD8
AF13FMC2_LA01_CC_ND9
V18FMC2_LA02_PH7
W19FMC2_LA02_NH8
W17FMC2_LA03_PG9
W18FMC2_LA03_NG10
AA21FMC2_LA04_PH10
AB21FMC2_LA04_NH11
Y17FMC2_LA05_PD11
AA17FMC2_LA05_ND12
U15FMC2_LA06_PC10
V16FMC2_LA06_NC11
Detailed Description
AA19FMC2_LA07_PH13
AB19FMC2_LA07_NH14
W16FMC2_LA08_PG12
Y16FMC2_LA08_NG13
AA18FMC2_LA09_PD14
AB17FMC2_LA09_ND15
Y15FMC2_LA10_PC14
AA16FMC2_LA10_NC15
V14FMC2_LA11_PH16
V15FMC2_LA11_NH17
U13FMC2_LA12_PG15
V13FMC2_LA12_NG16
AA15FMC2_LA13_PD17
AB15FMC2_LA13_ND18
Y21FMC2_LA14_PC18
AA22FMC2_LA14_NC19
Y12FMC2_LA15_PH19
AA12FMC2_LA15_NH20
W14FMC2_LA16_PG18
Y13FMC2_LA16_NG19
AE15FMC2_LA17_CC_PD20
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Chapter 1: SP623 Board Features and Operation
Table 1-18: Vita 57.1 FMC2 HPC Connections at J113 (Cont’d)
FPGA PinNet NameFMC Pin
AF15FMC2_LA17_CC_ND21
AD23FMC2_LA18_CC_PC22
AF23FMC2_LA18_CC_NC23
Y11FMC2_LA19_PH22
AA11FMC2_LA19_NH23
V11FMC2_LA20_PG21
V10FMC2_LA20_NG22
AA9FMC2_LA21_PH25
AB9FMC2_LA21_NH26
AA10FMC2_LA22_PG24
AB11FMC2_LA22_NG25
AD6FMC2_LA23_PD23
AF6FMC2_LA23_ND24
W20FMC2_LA24_PH28
Y20FMC2_LA24_NH29
W10FMC2_LA25_PG27
W9FMC2_LA25_NG28
AE5FMC2_LA26_PD26
AF5FMC2_LA26_ND27
Y9FMC2_LA27_PC26
AA8FMC2_LA27_NC27
AB7FMC2_LA28_PH31
AC6FMC2_LA28_NH32
AB22FMC2_LA29_PG30
AC22FMC2_LA29_NG31
AC5FMC2_LA30_PH34
AD5FMC2_LA30_NH35
W8FMC2_LA31_PG33
W7FMC2_LA31_NG34
AD4FMC2_LA32_PH37
AF4FMC2_LA32_NH38
AA7FMC2_LA33_PG36
AA6FMC2_LA33_NG37
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Table 1-18: Vita 57.1 FMC2 HPC Connections at J113 (Cont’d)
FPGA PinNet NameFMC Pin
AC3FMC2_PRSNT_M2CH2
U20.13FMC2_TCK_BUF
J36.1FMC2_TDI
J36.3FMC2_TDO
U20.16TMS_BUF
Notes:
1. This signal is not directly connected to the FPGA. The value in the
leftmost column represents the device and pin the signal is
connected to. For example, U14.13 = U14 pin 13.
(1)
(1)
(1)
(1)
D29
D30
D31
D33
Table 1-19: Power Supply Voltages for the HPC Connector
Detailed Description
Volt ag e
Supply
V
ADJ
3P3V
AUX
Volt a g e Ran g e
3P3V3.3V43±5%1,000 µF
12P0V12V21±5%1,000 µF
I2C Bus Management
[Figure 1-2, callout 21]
2
The I
C bus is controlled through U14, a four-channel I2C-bus multiplexer (Texas
Instruments PCA9544A). The FPGA communicates with the multiplexer through I
and clock signals mapped to FPGA pins J24 and J23, respectively. The I
PCA9544A device is 0x70. The bus hosts four components:
•SuperClock-2 module
•GTP Transceiver power supply module
•FMC1
•FMC2
2
An I
C component can be accessed by selecting the appropriate channel through the
control register of the MUX as shown in Ta bl e 1- 20 .
Allowable
Number
of Pins
Maximum
Amps
Toleranc e
Maximum
Capacitive Load
Fixed 2.5V44±5%1,000 µF
3.3V10.020±5%150 µF
2
C idcode for the
2
C data
Table 1-20: I2C Channel Assignments
U27
Channel
2
C Component
I
0SuperClock-2 module
1GTP transceiver power supply module
2FMC1
3FMC2
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Chapter 1: SP623 Board Features and Operation
34www.xilinx.comSP623 Board User Guide
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Appendix A
Default Jumper Positions
Tab le A- 1 shows the 23 standard (black) shunts that must be installed on the board for
proper operation. There are an additional six (red) shorting plugs that must be installed to
enable the output of on-board, regulated power and to connect the MGTAVCCPLL and
MGTAVCC rails. These shunts and shorting plugs must always be installed except where
specifically noted in this user guide. Refer to PCB Assembly Drawing 0431556 for the
default placement of all on-board jumpers and their respective connectors, as located on
the board.
Figure B-1 provides a cross-reference of signal names to pin coordinates for the VITA 57.1
FMC HPC connector.
X-Ref Target - Figure B-1
SP623 Board User Guidewww.xilinx.com37
UG751 (v1.0) May 22, 2010
Figure B-1: FMC HPC Connector Pinout
Appendix B: VITA 57.1 FMC HPC Connector Pinout
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SP623 Master UCF Listing
The SP623 master user constraints file (UCF) template provides for designs targeting the
SP623 Spartan-6 FPGA GTP transceiver characterization board. Net names in the
constraints listed below correlate with net names on the SP623 board schematic. Users
must identify the appropriate pins and replace the net names below with net names in the
user RTL. See the Constraints Guide
Users can refer to the UCF files generated by tools such as Memory Interface Generator
(MIG) for memory interfaces and Base System Builder (BSB) for more detailed I/O
standards information required for each particular interface. The FMC connectors J112 and
J113 are connected to 2.5V V
cco
customer-specific circuitry, the FMC bank I/O standards must be uniquely defined by each
customer.
SP623 Master UCF Listing:
NET "101_REFCLK0_N"LOC = "A10";
NET "101_REFCLK0_P"LOC = "B10";
NET "101_REFCLK1_N"LOC = "C11";
NET "101_REFCLK1_P"LOC = "D11";
NET "101_RX0_N"LOC = "C7";
NET "101_RX0_P"LOC = "D7";
NET "101_RX1_N"LOC = "C9";
NET "101_RX1_P"LOC = "D9";
NET "101_TX0_N"LOC = "A6";
NET "101_TX0_P"LOC = "B6";
NET "101_TX1_N"LOC = "A8";
NET "101_TX1_P"LOC = "B8";
NET "123_REFCLK0_N"LOC = "C15";
NET "123_REFCLK0_P"LOC = "D15";
NET "123_REFCLK1_N"LOC = "A16";
NET "123_REFCLK1_P"LOC = "B16";
NET "123_RX0_N"LOC = "C17";
NET "123_RX0_P"LOC = "D17";
NET "123_RX1_N"LOC = "C19";
NET "123_RX1_P"LOC = "D19";
NET "123_TX0_N"LOC = "A18";
NET "123_TX0_P"LOC = "B18";
NET "123_TX1_N"LOC = "A20";
NET "123_TX1_P"LOC = "B20";
NET "245_REFCLK0_N"LOC = "AF11";
NET "245_REFCLK0_P"LOC = "AE11";
NET "245_REFCLK1_N"LOC = "AD12";
NET "245_REFCLK1_P"LOC = "AC12";
NET "245_RX0_N"LOC = "AD8";
NET "245_RX0_P"LOC = "AC8";
NET "245_RX1_N"LOC = "AD10";
for more information.
banks. Because each user’s FMC card implements
Appendix C
SP623 Board User Guidewww.xilinx.com39
UG751 (v1.0) May 22, 2010
Appendix C: SP623 Master UCF Listing
NET "245_RX1_P"LOC = "AC10";
NET "245_TX0_N"LOC = "AF7";
NET "245_TX0_P"LOC = "AE7";
NET "245_TX1_N"LOC = "AF9";
NET "245_TX1_P"LOC = "AE9";
NET "267_REFCLK0_N"LOC = "AD16";
NET "267_REFCLK0_P"LOC = "AC16";
NET "267_REFCLK1_N"LOC = "AF17";
NET "267_REFCLK1_P"LOC = "AE17";
NET "267_RX0_N"LOC = "AD18";
NET "267_RX0_P"LOC = "AC18";
NET "267_RX1_N"LOC = "AD20";
NET "267_RX1_P"LOC = "AC20";
NET "267_TX0_N"LOC = "AF19";
NET "267_TX0_P"LOC = "AE19";
NET "267_TX1_N"LOC = "AF21";
NET "267_TX1_P"LOC = "AE21";
NET "AWAKE_1"LOC = "AC23";
NET "CCLK_2"LOC = "AE24";
NET "CM_CTRL_0"LOC = "U20";
NET "CM_CTRL_1"LOC = "U19";
NET "CM_CTRL_10"LOC = "Y26";
NET "CM_CTRL_11"LOC = "Y24";
NET "CM_CTRL_12"LOC = "AC26";
NET "CM_CTRL_13"LOC = "AC25";
NET "CM_CTRL_14"LOC = "AB26";
NET "CM_CTRL_15"LOC = "AB24";
NET "CM_CTRL_16"LOC = "AD26";
NET "CM_CTRL_17"LOC = "AD24";
NET "CM_CTRL_18"LOC = "AA26";
NET "CM_CTRL_19"LOC = "AA25";
NET "CM_CTRL_2"LOC = "AA24";
NET "CM_CTRL_20"LOC = "W26";
NET "CM_CTRL_21"LOC = "W25";
NET "CM_CTRL_22"LOC = "V24";
NET "CM_CTRL_23"LOC = "T23";
NET "CM_CTRL_3"LOC = "AA23";
NET "CM_CTRL_4"LOC = "T20";
NET "CM_CTRL_5"LOC = "T19";
NET "CM_CTRL_6"LOC = "U22";
NET "CM_CTRL_7"LOC = "U21";
NET "CM_CTRL_8"LOC = "AE26";
NET "CM_CTRL_9"LOC = "AE25";
NET "CM_GCLK_N"LOC = "U26";
NET "CM_GCLK_P"LOC = "U25";
NET "CM_LVDS1_N"LOC = "E12";
NET "CM_LVDS1_P"LOC = "F12";
NET "CM_LVDS2_N"LOC = "W12";
NET "CM_LVDS2_P"LOC = "V12";
NET "CM_LVDS3_N"LOC = "F11";
NET "CM_LVDS3_P"LOC = "G12";
NET "CM_RST"LOC = "T22";
NET "CMPCS_B_2"LOC = "Y19";
NET "CSO_B_2"LOC = "AF3";
NET "DOUT_BUSY_1"LOC = "AC24";
NET "DUT_I2C_SCL"LOC = "J23";
NET "DUT_I2C_SDA"LOC = "J24";
NET "DUT_PMB_ALERT"LOC = "E24";
NET "DUT_PMB_CLK"LOC = "L19";
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NET "DUT_PMB_CTRL"LOC = "E23";
NET "DUT_PMB_DATA"LOC = "K20";
NET "DUT_SPI_CS"LOC = "B26";
NET "DUT_SPI_D"LOC = "C26";
NET "DUT_SPI_Q"LOC = "B25";
NET "DUT_SPI_SCK"LOC = "C25";
NET "FMC1_CLK0_M2C_N"LOC = "T1";
NET "FMC1_CLK0_M2C_P"LOC = "T3";
NET "FMC1_CLK1_M2C_N"LOC = "A14";
NET "FMC1_CLK1_M2C_P"LOC = "B14";
NET "FMC1_CLK2_M2C_N"LOC = "W3";
NET "FMC1_CLK2_M2C_P"LOC = "V4";
NET "FMC1_HA00_CC_N"LOC = "R1";
NET "FMC1_HA00_CC_P"LOC = "R2";
NET "FMC1_HA01_CC_N"LOC = "N3";
NET "FMC1_HA01_CC_P"LOC = "M4";
NET "FMC1_HA02_N"LOC = "N1";
NET "FMC1_HA02_P"LOC = "N2";
NET "FMC1_HA03_N"LOC = "M1";
NET "FMC1_HA03_P"LOC = "M3";
NET "FMC1_HA04_N"LOC = "L1";
NET "FMC1_HA04_P"LOC = "L2";
NET "FMC1_HA05_N"LOC = "K1";
NET "FMC1_HA05_P"LOC = "K3";
NET "FMC1_HA06_N"LOC = "J1";
NET "FMC1_HA06_P"LOC = "J2";
NET "FMC1_HA07_N"LOC = "H1";
NET "FMC1_HA07_P"LOC = "H3";
NET "FMC1_HA08_N"LOC = "G1";
NET "FMC1_HA08_P"LOC = "G2";
NET "FMC1_HA09_N"LOC = "F1";
NET "FMC1_HA09_P"LOC = "F3";
NET "FMC1_HA10_N"LOC = "E1";
NET "FMC1_HA10_P"LOC = "E2";
NET "FMC1_HA11_N"LOC = "D1";
NET "FMC1_HA11_P"LOC = "D3";
NET "FMC1_HA12_N"LOC = "J3";
NET "FMC1_HA12_P"LOC = "J4";
NET "FMC1_HA13_N"LOC = "L8";
NET "FMC1_HA13_P"LOC = "L9";
NET "FMC1_HA14_N"LOC = "L3";
NET "FMC1_HA14_P"LOC = "L4";
NET "FMC1_HA15_N"LOC = "M6";
NET "FMC1_HA15_P"LOC = "M8";
NET "FMC1_HA16_N"LOC = "J5";
NET "FMC1_HA16_P"LOC = "K5";
NET "FMC1_HA17_CC_N"LOC = "L6";
NET "FMC1_HA17_CC_P"LOC = "L7";
NET "FMC1_HA18_N"LOC = "B1";
NET "FMC1_HA18_P"LOC = "B2";
NET "FMC1_HA19_N"LOC = "K10";
NET "FMC1_HA19_P"LOC = "L10";
NET "FMC1_HA20_N"LOC = "G3";
NET "FMC1_HA20_P"LOC = "G4";
NET "FMC1_HA21_N"LOC = "J7";
NET "FMC1_HA21_P"LOC = "J9";
NET "FMC1_HA22_N"LOC = "C1";
NET "FMC1_HA22_P"LOC = "C2";
NET "FMC1_HA23_N"LOC = "K8";
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NET "FMC1_HA23_P"LOC = "K9";
NET "FMC1_LA00_CC_N"LOC = "D13";
NET "FMC1_LA00_CC_P"LOC = "E13";
NET "FMC1_LA01_CC_N"LOC = "A13";
NET "FMC1_LA01_CC_P"LOC = "C13";
NET "FMC1_LA02_N"LOC = "G9";
NET "FMC1_LA02_P"LOC = "H9";
NET "FMC1_LA03_N"LOC = "A2";
NET "FMC1_LA03_P"LOC = "A3";
NET "FMC1_LA04_N"LOC = "E8";
NET "FMC1_LA04_P"LOC = "F9";
NET "FMC1_LA05_N"LOC = "C5";
NET "FMC1_LA05_P"LOC = "D5";
NET "FMC1_LA06_N"LOC = "G7";
NET "FMC1_LA06_P"LOC = "H7";
NET "FMC1_LA07_N"LOC = "G10";
NET "FMC1_LA07_P"LOC = "H10";
NET "FMC1_LA08_N"LOC = "A4";
NET "FMC1_LA08_P"LOC = "B4";
NET "FMC1_LA09_N"LOC = "E10";
NET "FMC1_LA09_P"LOC = "F10";
NET "FMC1_LA10_N"LOC = "A5";
NET "FMC1_LA10_P"LOC = "B5";
NET "FMC1_LA11_N"LOC = "G8";
NET "FMC1_LA11_P"LOC = "H8";
NET "FMC1_LA12_N"LOC = "G11";
NET "FMC1_LA12_P"LOC = "J11";
NET "FMC1_LA13_N"LOC = "G13";
NET "FMC1_LA13_P"LOC = "H12";
NET "FMC1_LA14_N"LOC = "J12";
NET "FMC1_LA14_P"LOC = "K12";
NET "FMC1_LA15_N"LOC = "F6";
NET "FMC1_LA15_P"LOC = "F7";
NET "FMC1_LA16_N"LOC = "H15";
NET "FMC1_LA16_P"LOC = "J15";
NET "FMC1_LA17_CC_N"LOC = "A12";
NET "FMC1_LA17_CC_P"LOC = "B12";
NET "FMC1_LA18_CC_N"LOC = "J17";
NET "FMC1_LA18_CC_P"LOC = "J16";
NET "FMC1_LA19_N"LOC = "E16";
NET "FMC1_LA19_P"LOC = "F16";
NET "FMC1_LA20_N"LOC = "B3";
NET "FMC1_LA20_P"LOC = "C3";
NET "FMC1_LA21_N"LOC = "F15";
NET "FMC1_LA21_P"LOC = "G15";
NET "FMC1_LA22_N"LOC = "E18";
NET "FMC1_LA22_P"LOC = "F18";
NET "FMC1_LA23_N"LOC = "F17";
NET "FMC1_LA23_P"LOC = "G16";
NET "FMC1_LA24_N"LOC = "E20";
NET "FMC1_LA24_P"LOC = "F20";
NET "FMC1_LA25_N"LOC = "G17";
NET "FMC1_LA25_P"LOC = "H17";
NET "FMC1_LA26_N"LOC = "B21";
NET "FMC1_LA26_P"LOC = "C21";
NET "FMC1_LA27_N"LOC = "F5";
NET "FMC1_LA27_P"LOC = "G6";
NET "FMC1_LA28_N"LOC = "H19";
NET "FMC1_LA28_P"LOC = "H18";
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NET "FMC1_LA29_N"LOC = "A22";
NET "FMC1_LA29_P"LOC = "B22";
NET "FMC1_LA30_N"LOC = "F19";
NET "FMC1_LA30_P"LOC = "G19";
NET "FMC1_LA31_N"LOC = "A23";
NET "FMC1_LA31_P"LOC = "B23";
NET "FMC1_LA32_N"LOC = "D22";
NET "FMC1_LA32_P"LOC = "D21";
NET "FMC1_LA33_N"LOC = "E5";
NET "FMC1_LA33_P"LOC = "E6";
NET "FMC1_PRSNT_M2C"LOC = "E3";
NET "FMC2_CLK0_M2C_N"LOC = "U24";
NET "FMC2_CLK0_M2C_P"LOC = "U23";
NET "FMC2_CLK1_M2C_N"LOC = "AF14";
NET "FMC2_CLK1_M2C_P"LOC = "AD14";
NET "FMC2_HA00_CC_N"LOC = "R6";
NET "FMC2_HA00_CC_P"LOC = "R7";
NET "FMC2_HA02_N"LOC = "U3";
NET "FMC2_HA02_P"LOC = "U4";
NET "FMC2_HA03_N"LOC = "W5";
NET "FMC2_HA03_P"LOC = "V5";
NET "FMC2_HA04_N"LOC = "U8";
NET "FMC2_HA04_P"LOC = "U9";
NET "FMC2_HA05_N"LOC = "T6";
NET "FMC2_HA05_P"LOC = "U7";
NET "FMC2_HA06_N"LOC = "AB1";
NET "FMC2_HA06_P"LOC = "AB3";
NET "FMC2_HA07_N"LOC = "AD1";
NET "FMC2_HA07_P"LOC = "AD3";
NET "FMC2_HA08_N"LOC = "AC1";
NET "FMC2_HA08_P"LOC = "AC2";
NET "FMC2_HA09_N"LOC = "AE1";
NET "FMC2_HA09_P"LOC = "AE2";
NET "FMC2_HA10_N"LOC = "AA1";
NET "FMC2_HA10_P"LOC = "AA2";
NET "FMC2_HA11_N"LOC = "Y1";
NET "FMC2_HA11_P"LOC = "Y3";
NET "FMC2_HA12_N"LOC = "W1";
NET "FMC2_HA12_P"LOC = "W2";
NET "FMC2_HA13_N"LOC = "T9";
NET "FMC2_HA13_P"LOC = "R10";
NET "FMC2_HA14_N"LOC = "P1";
NET "FMC2_HA14_P"LOC = "P3";
NET "FMC2_HA15_N"LOC = "P6";
NET "FMC2_HA15_P"LOC = "N6";
NET "FMC2_HA16_N"LOC = "R5";
NET "FMC2_HA16_P"LOC = "P5";
NET "FMC2_HA17_CC_N"LOC = "N7";
NET "FMC2_HA17_CC_P"LOC = "N8";
NET "FMC2_HA18_N"LOC = "R3";
NET "FMC2_HA18_P"LOC = "R4";
NET "FMC2_HA19_N"LOC = "P8";
NET "FMC2_HA19_P"LOC = "R9";
NET "FMC2_HA20_N"LOC = "N4";
NET "FMC2_HA20_P"LOC = "N5";
NET "FMC2_HA21_N"LOC = "N9";
NET "FMC2_HA21_P"LOC = "P10";
NET "FMC2_HA22_N"LOC = "M9";
NET "FMC2_HA22_P"LOC = "M10";
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NET "FMC2_HA23_N"LOC = "Y5";
NET "FMC2_HA23_P"LOC = "Y6";
NET "FMC2_LA00_CC_N"LOC = "AC14";
NET "FMC2_LA00_CC_P"LOC = "AB14";
NET "FMC2_LA01_CC_N"LOC = "AF13";
NET "FMC2_LA01_CC_P"LOC = "AE13";
NET "FMC2_LA02_N"LOC = "W19";
NET "FMC2_LA02_P"LOC = "V18";
NET "FMC2_LA03_N"LOC = "W18";
NET "FMC2_LA03_P"LOC = "W17";
NET "FMC2_LA04_N"LOC = "AB21";
NET "FMC2_LA04_P"LOC = "AA21";
NET "FMC2_LA05_N"LOC = "AA17";
NET "FMC2_LA05_P"LOC = "Y17";
NET "FMC2_LA06_N"LOC = "V16";
NET "FMC2_LA06_P"LOC = "U15";
NET "FMC2_LA07_N"LOC = "AB19";
NET "FMC2_LA07_P"LOC = "AA19";
NET "FMC2_LA08_N"LOC = "Y16";
NET "FMC2_LA08_P"LOC = "W16";
NET "FMC2_LA09_N"LOC = "AB17";
NET "FMC2_LA09_P"LOC = "AA18";
NET "FMC2_LA10_N"LOC = "AA16";
NET "FMC2_LA10_P"LOC = "Y15";
NET "FMC2_LA11_N"LOC = "V15";
NET "FMC2_LA11_P"LOC = "V14";
NET "FMC2_LA12_N"LOC = "V13";
NET "FMC2_LA12_P"LOC = "U13";
NET "FMC2_LA13_N"LOC = "AB15";
NET "FMC2_LA13_P"LOC = "AA15";
NET "FMC2_LA14_N"LOC = "AA22";
NET "FMC2_LA14_P"LOC = "Y21";
NET "FMC2_LA15_N"LOC = "AA12";
NET "FMC2_LA15_P"LOC = "Y12";
NET "FMC2_LA16_N"LOC = "Y13";
NET "FMC2_LA16_P"LOC = "W14";
NET "FMC2_LA17_CC_N"LOC = "AF15";
NET "FMC2_LA17_CC_P"LOC = "AE15";
NET "FMC2_LA18_CC_N"LOC = "AF23";
NET "FMC2_LA18_CC_P"LOC = "AD23";
NET "FMC2_LA19_N"LOC = "AA11";
NET "FMC2_LA19_P"LOC = "Y11";
NET "FMC2_LA20_N"LOC = "V10";
NET "FMC2_LA20_P"LOC = "V11";
NET "FMC2_LA21_N"LOC = "AB9";
NET "FMC2_LA21_P"LOC = "AA9";
NET "FMC2_LA22_N"LOC = "AB11";
NET "FMC2_LA22_P"LOC = "AA10";
NET "FMC2_LA23_N"LOC = "AF6";
NET "FMC2_LA23_P"LOC = "AD6";
NET "FMC2_LA24_N"LOC = "Y20";
NET "FMC2_LA24_P"LOC = "W20";
NET "FMC2_LA25_N"LOC = "W9";
NET "FMC2_LA25_P"LOC = "W10";
NET "FMC2_LA26_N"LOC = "AF5";
NET "FMC2_LA26_P"LOC = "AE5";
NET "FMC2_LA27_N"LOC = "AA8";
NET "FMC2_LA27_P"LOC = "Y9";
NET "FMC2_LA28_N"LOC = "AC6";
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NET "FMC2_LA28_P"LOC = "AB7";
NET "FMC2_LA29_N"LOC = "AC22";
NET "FMC2_LA29_P"LOC = "AB22";
NET "FMC2_LA30_N"LOC = "AD5";
NET "FMC2_LA30_P"LOC = "AC5";
NET "FMC2_LA31_N"LOC = "W7";
NET "FMC2_LA31_P"LOC = "W8";
NET "FMC2_LA32_N"LOC = "AF4";
NET "FMC2_LA32_P"LOC = "AD4";
NET "FMC2_LA33_N"LOC = "AA6";
NET "FMC2_LA33_P"LOC = "AA7";
NET "FMC2_PRSNT_M2C"LOC = "AC3";
NET "HSWAPEN_0"LOC = "A1";
NET "INIT_B_2"LOC = "AE3";
NET "IO_L36N_2_AA13"LOC = "AA13";
NET "IO_L36P_2_AB13"LOC = "AB13";
NET "IO_L39N_M3LDQSN_3_V1 "LOC = "V1";
NET "IO_L39P_M3LDQS_3_V3"LOC = "V3";
NET "IO_L40N_M3DQ7_3_U1"LOC = "U1";
NET "IO_L40P_M3DQ6_3_U2"LOC = "U2";
NET "IO_LVDS_CLK_N"LOC = "W24";
NET "IO_LVDS_CLK_P"LOC = "V23";
NET "LED1"LOC = "L21";
NET "LED2"LOC = "L20";
NET "LED3"LOC = "M23";
NET "LED4"LOC = "M21";
NET "LED5"LOC = "N26";
NET "LED6"LOC = "N25";
NET "LED7"LOC = "L26";
NET "LED8"LOC = "L25";
NET "M0_CMPMISO_2"LOC = "AF24";
NET "M1_2"LOC = "AD22";
NET "PB_SW1"LOC = "M26";
NET "PB_SW2"LOC = "M24";
NET "RFUSE"LOC = "V19";
NET "SMA_CLK_N"LOC = "R26";
NET "SMA_CLK_P"LOC = "R25";
NET "SW1"LOC = "J26";
NET "SW2"LOC = "J25";
NET "SW3"LOC = "K26";
NET "SW4"LOC = "K24";
NET "SW5"LOC = "G26";
NET "SW6"LOC = "G25";
NET "SW7"LOC = "H26";
NET "SW8"LOC = "H24";
NET "USB_CTS"LOC = "L23";
NET "USB_GPIO0"LOC = "P22";
NET "USB_GPIO1"LOC = "P21";
NET "USB_GPIO2"LOC = "N22";
NET "USB_GPIO3"LOC = "N21";
NET "USB_RTS"LOC = "L24";
NET "USB_RX"LOC = "N20";
NET "USB_TX"LOC = "N19";
NET "VFS"LOC = "W22";
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Appendix C: SP623 Master UCF Listing
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References
Additional information relevant to Spartan®-6 devices, the SP623 Spartan-6 FPGA GTP
transceiver characterization board, and intellectual property is available in the documents
listed here:
Appendix D
•DS162
•UG380
•UG385
•UG381
•UG388
•DS080
•UG386
•DS606
•DS614
•HW-CLK-101-SCLK2 SuperClock-2 Module User Guide
To find additional documentation, see the Xilinx website at: