XILINX SP601 User Manual

SP601 Hardware User Guide

UG518 (v1.7) September 26, 2012

© Copyright 2009–2012 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. All other trademarks are the property of their respective owners.

DISCLAIMER

The information disclosed to you hereunder (the “Materials”) is provided solely for the selection and use of Xilinx products. To the maximum extent permitted by applicable law: (1) Materials are made available “AS IS” and with all faults, Xilinx hereby DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including negligence, or under any other theory of liability) for any loss or damage of any kind or nature related to, arising under, or in connection with, the Materials (including your use of the Materials), including for any direct, indirect, special, incidental, or consequential loss or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any action brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same. Xilinx assumes no obligation to correct any errors contained in the Materials, or to advise you of any corrections or update. You may not reproduce, modify, distribute, or publicly display the Materials without prior written consent. Certain products are subject to the terms and conditions of the Limited Warranties which can be viewed at http://www.xilinx.com/warranty.htm support terms contained in a license issued to you by Xilinx. Xilinx products are not designed or intended to be fail-safe or for use in any application requiring fail-safe performance; you assume sole risk and liability for use of Xilinx products in Critical Applications:

http://www.xilinx.com/warranty.htm#critapps

; IP cores may be subject to warranty and

Revision History

The following table shows the revision history for this document.

Date Version Revision

07/15/09 1.0 Initial Xilinx release.

08/19/09 1.1 • Added Appendix B, VITA 57.1 FMC LPC Connector Pinout.

• Updated Figure 1-17.

• Updated Tab le 1- 4, Ta bl e 1 -19 , and Tab le 1 -2 2.

• Added introductory paragraph to Appendix C, SP601 Master UCF.

• Miscellaneous typographical edits and new user guide template.

05/17/10 1.2 • Updated Figure 1-1, Figure 1-2, Figure 1-14, Figure 1-18, Tab le 1- 9, Ta bl e 1 -1,

Ta bl e 1 -11 , and Tab le 1-1 6.

•Added Figure 1-7, Figure 1-8, and Ta bl e 1 -13 .

• Updated 9. VITA 57.1 FMC-LPC Connector, page 25, Appendix B, VITA 57.1 FMC

LPC Connector Pinout, and Appendix C, SP601 Master UCF.

06/16/10 1.3 Reversed order of 15. Configuration Options and 16. Power Management. Updated 1.

Spartan-6 XC6SLX16-2CSG324 FPGA and 2. 128 MB DDR2 Component Memory. Added Ta bl e 1 -2 6 . Added UG394 References.

09/24/10 1.4 Added Power System Test Points, including Ta b le 1 -2 5.

02/16/11 1.5 Added note and revised header description to indicate the I/Os support LVCMOS25

signaling on page 34. Revised oscillator manufacturer information from Epson to SiTime on page page 23 and page 51.

07/18/11 1.6 Corrected wording from “PPM frequency jitter” to “PPM frequency stability” in section

Oscillator (Differential), page 23. Added Table 1-15, page 27.

09/26/12 1.7 Added Regulatory and Compliance Information, page 53.

, Spartan-6 FPGA Power Management User Guide to Appendix D,

SP601 Hardware User Guide www.xilinx.com UG518 (v1.7) September 26, 2012

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Preface: About This Guide

Guide Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Additional Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Additional Support Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Chapter 1: SP601 Evaluation Board

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Additional Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Related Xilinx Documents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

1. Spartan-6 XC6SLX16-2CSG324 FPGA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

I/O Voltage Rails . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2. 128 MB DDR2 Component Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3. SPI x4 Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

4. Linear Flash BPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

5. 10/100/1000 Tri-Speed Ethernet PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

6. USB-to-UART Bridge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

7. IIC Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

8-Kb NV Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

8. Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Oscillator (Differential) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Oscillator Socket (Single-Ended, 2.5V or 3.3V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

SMA Connectors (Differential) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

9. VITA 57.1 FMC-LPC Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

10. Status LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

11. FPGA Awake LED and Suspend Jumper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

12. FPGA INIT and DONE LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

13. User I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

14. FPGA_PROG_B Pushbutton Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

15. Configuration Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

JTAG Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

16. Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

AC Adapter and 5V Input Power Jack/Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Onboard Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Power System Test Points. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

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UG518 (v1.7) September 26, 2012

Appendix A: Default Jumper and Switch Settings

Appendix B: VITA 57.1 FMC LPC Connector Pinout

Appendix C: SP601 Master UCF

Appendix D: References

Appendix E: Regulatory and Compliance Information

Directives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Electromagnetic Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Safety . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

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UG518 (v1.7) September 26, 2012

About This Guide

This manual accompanies the Spartan®-6 FPGA SP601 Evaluation Board and contains information about the SP601 hardware and software tools.

Guide Contents

This manual contains the following chapters:

• Chapter 1, SP601 Evaluation Board, provides an overview of the SP601 evaluation board and details the components and features of the SP601 board.

• Appendix A, Default Jumper and Switch Settings.

• Appendix B, VITA 57.1 FMC LPC Connector Pinout.

• Appendix C, SP601 Master UCF.

• Appendix D, References.

Preface

Additional Documentation

The following documents are available for download at

http://www.xilinx.com/products/spartan6

• Spartan-6 Family Overview

This overview outlines the features and product selection of the Spartan-6 family.

• Spartan-6 FPGA Data Sheet: DC and Switching Characteristics

This data sheet contains the DC and switching characteristic specifications for the Spartan-6 family.

• Spartan-6 FPGA Packaging and Pinout Specifications

This specification includes the tables for device/package combinations and maximum I/Os, pin definitions, pinout tables, pinout diagrams, mechanical drawings, and thermal specifications.

• Spartan-6 FPGA Configuration User Guide

This all-encompassing configuration guide includes chapters on configuration interfaces (serial and parallel), multi-bitstream management, bitstream encryption, boundary-scan and JTAG configuration, and reconfiguration techniques.

• Spartan-6 FPGA SelectIO Resources User Guide

This guide describes the SelectIO™ resources available in all Spartan-6 devices.

•Spartan-6 FPGA Clocking Resources User Guide

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UG518 (v1.7) September 26, 2012

Preface: About This Guide

This guide describes the clocking resources available in all Spartan-6 devices, including the DCMs and PLLs.

• Spartan-6 FPGA Block RAM Resources User Guide

This guide describes the Spartan-6 device block RAM capabilities.

• Spartan-6 FPGA DSP48A1 Slice User Guide

This guide describes the architecture of the DSP48A1 slice in Spartan-6 FPGAs and provides configuration examples.

• Spartan-6 FPGA Memory Controller User Guide

This guide describes the Spartan-6 FPGA memory controller block, a dedicated embedded multi-port memory controller that greatly simplifies interfacing Spartan-6 FPGAs to the most popular memory standards.

• Spartan-6 FPGA PCB Designer’s Guide

This guide provides information on PCB design for Spartan-6 devices, with a focus on strategies for making design decisions at the PCB and interface level.

Additional Support Resources

To search the database of silicon and software questions and answers or to create a technical support case in WebCase, see the Xilinx website at:

http://www.xilinx.com/support

6 www.xilinx.com SP601 Hardware User Guide

UG518 (v1.7) September 26, 2012

SP601 Evaluation Board

Overview

The SP601 board enables hardware and software developers to create or evaluate designs targeting the Spartan®-6 XC6SLX16-2CSG324 FPGA.

The SP601 provides board features for evaluating the Spartan-6 family that are common to most entry-level development environments. Some commonly used features include a DDR2 memory controller, a parallel linear flash, a tri-mode Ethernet PHY, general-purpose I/O (GPIO), and a UART. Additional functionality can be added through the VITA 57.1.1 expansion connector. Features, page 8 provides a general listing of the board features with details provided in Detailed Description, page 10.

Additional Information

Additional information and support material is located at:

Chapter 1

• http://www.xilinx.com/sp601

This information includes:

• Current version of this user guide in PDF format

• Example design files for demonstration of Spartan-6 FPGA features and technology

• Demonstration hardware and software configuration files for the SP601 linear and SPI memory devices

• Reference Design Files

• Schematics in PDF format and DxDesigner schematic format

• Bill of materials (BOM)

• Printed-circuit board (PCB) layout in Allegro PCB format

• Gerber files for the PCB (Many free or shareware Gerber file viewers are available on the internet for viewing and printing these files.)

• Additional documentation, errata, frequently asked questions, and the latest news

For information about the Spartan-6 family of FPGA devices, including product highlights, data sheets, user guides, and application notes, see the Spartan-6 FPGA website at

http://www.xilinx.com/support/documentation/spartan-6.htm

SP601 Hardware User Guide www.xilinx.com 7

UG518 (v1.7) September 26, 2012

Chapter 1: SP601 Evaluation Board

Features

The SP601 board provides the following features (see Figure 1-2 and Tab le 1 -1):

• 1. Spartan-6 XC6SLX16-2CSG324 FPGA

• 2. 128 MB DDR2 Component Memory

• 3. SPI x4 Flash

• 4. Linear Flash BPI

• 5. 10/100/1000 Tri-Speed Ethernet PHY

• 7. IIC Bus

• 8Kb NV memory

• External access 2-pin header

• VITA 57.1 FMC-LPC connector

• 8. Clock Generation

• Oscillator (Differential)

• Oscillator Socket (Single-Ended, 2.5V or 3.3V)

• SMA Connectors (Differential)

• 9. VITA 57.1 FMC-LPC Connector

• 10. Status LEDs

•FPGA_AWAKE

•INIT

•DONE

• 13. User I/O

• User LEDs

•User DIP switch

• User pushbuttons

• GPIO male pin header

• 14. FPGA_PROG_B Pushbutton Switch

• 15. Configuration Options

• 3. SPI x4 Flash (both onboard and off-board)

• 4. Linear Flash BPI

• JTAG Configuration

• 16. Power Management

• AC Adapter and 5V Input Power Jack/Switch

• Onboard Power Supplies

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UG518 (v1.7) September 26, 2012

X-Ref Target - Figure 1-1

Detailed Description

Figure 1-2 shows a board photo with numbered features corresponding to Tab le 1 -1 and

the section headings in this document.

X-Ref Target - Figure 1-2

The numbered features in Figure 1-2 correlate to the features and notes listed in Ta bl e 1 -1 .

Table 1-1: SP601 Features

Number Feature Notes

Figure 1-2: SP601 Board Photo

1 Spartan-6 FPGA XC6SLX16-2CSG324

2 DDR2 Component Elpida EDE1116ACBG 1 Gb

3 SPI x4 Flash and Headers SPI select and External Headers 8

4 Linear Flash BPI StrataFlash 8-bit (J3 device), 3 pins

DDR2 SDRAM

shared w/ SPI x4

Schematic

Page

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UG518 (v1.7) September 26, 2012

Table 1-1: SP601 Features (Cont’d)

Detailed Description

Number Feature Notes

5 10/100/1000 Ethernet PHY GMII Marvell Alaska PHY 7

6 RS232 UART (USB Bridge) Uses CP2103 Serial-to-USB connection 10

7 IIC Goes to Header and VITA 57.1 FMC 10

8 Clock, socket, SMA Differential, Single-Ended, Differential 9

9 VITA 57.1 FMC-LPC

connector

10 LEDs Ethernet PHY Status 7

11 LED, Header FPGA Awake LED, Suspend Header 8

12 LEDs FPGA INIT, DONE 9

LED User I/O (active-High) 9

DIP Switch User I/O (active-High) 9

Pushbutton User I/O, CPU_RESET (active-High) 9

12-pin (8 I/O) Header 6 pins x 2 male header with 8 I/Os

14 Pushbutton FPGA_PROG_B 9

LVDS signals, clocks, PRSNT 6

(active-High)

Schematic

Page

15 USB JTAG Cypress USB to JTAG download cable

logic

16 Onboard Power Power Management 11,12,13

1. Spartan-6 XC6SLX16-2CSG324 FPGA

A Xilinx Spartan-6 XC6SLX16-2CSG324 FPGA is installed on the SP601 Evaluation Board.

References

See the Spartan-6 FPGA Data Sheet. [Ref 1]

Configuration

The SP601 supports configuration in the following modes:

•Master SPI x4

• Master SPI x4 with off-board device

•BPI

•JTAG (using the included USB-A to Mini-B cable)

For details on configuring the FPGA, see 15. Configuration Options.

The Mode DIP switch SW2 is set to M[1:0] = 01 Master SPI default.

14, 15

References

See the Spartan-6 FPGA Configuration User Guide for more information. [Ref 2]

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UG518 (v1.7) September 26, 2012

Chapter 1: SP601 Evaluation Board

I/O Voltage Rails

There are four available banks on the LX16-CSG324 device. Banks 0, 1, and 2 are connected for 2.5V I/O. Bank 3 is used for the 1.8V DDR2 component memory interface of Spartan-6 FPGA’s hard memory controller. The voltage applied to the FPGA I/O banks used by the SP601 board is summarized in Tab le 1 -2 .

Table 1-2: I/O Voltage Rail of FPGA Banks

FPGA Bank I/O Voltage Rail

References

See the Spartan-6 FPGA documentation for more information at

http://www.xilinx.com/support/documentation/

02.5V

12.5V

22.5V

31.8V

spartan-6.htm.

2. 128 MB DDR2 Component Memory

There are 128 MB of DDR2 memory available on the SP601 board. A 1-Gb Elpida EDE1116ACBG (84-ball) DDR2 memory component is accessible through Bank 3 of the LX16 device. The Spartan-6 FPGA hard memory controller is used for data transfer across the DDR2 memory interface’s 16-bit data path using SSTL18 signaling. The SP601 board supports the “standard” VCCINT setting of 1.20V ± 5%. This setting provides the standard memory controller block (MCB) performance of 625 Mb/s for DDR2 memory in a -2 speed grade device. Signal integrity is maintained through DDR2 resistor terminations and memory on-die terminations (ODT), as shown in Ta bl e 1 - 3 and Ta bl e 1 -4 .

Table 1-3: Termination Resistor Requirements

Signal Name Board Termination On-Die Termination

DDR2_A[14:0] 49.9Ω to V

DDR2_BA[2:0] 49.9Ω to V

DDR2_RAS_N 49.9Ω to V

DDR2_CAS_N 49.9Ω to V

DDR2_WE_N 49.9Ω to V

DDR2_CS_N 100Ω to GND

DDR2_CKE 4.7KΩ to GND

DDR2_ODT 4.7KΩ to GND

DDR2_DQ[15:0] ODT

DDR2_UDQS[P,N], DDR2_LDQS[P,N]

DDR2_UDM, DDR2_LDM ODT

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ODT

Table 1-3: Termination Resistor Requirements (Cont’d)

Signal Name Board Termination On-Die Termination

Detailed Description

DDR2_CK[P,N]

Notes:

1. Nominal value of VTT for DDR2 interface is 0.9V.

100Ω differential at memory

component

Table 1-4: FPGA On-Chip (OCT) Termination External Resistor Requirements

FPGA U1 Pin FPGA Pin Number Board Connection for OCT

ZIO L6 No Connect

RZQ C2 100Ω to GROUND

Tab le 1 -5 shows the connections and pin numbers for the DDR2 Component Memory.

Table 1-5: DDR2 Component Memory Connections

FPGA U1

Schematic Net Name

Pin Number Pin Name

Memory U2

J7 DDR2_A0 M8 A0

J6 DDR2_A1 M3 A1

H5 DDR2_A2 M7 A2

L7 DDR2_A3 N2 A3

F3 DDR2_A4 N8 A4

H4 DDR2_A5 N3 A5

H3 DDR2_A6 N7 A6

H6 DDR2_A7 P2 A7

D2 DDR2_A8 P8 A8

D1 DDR2_A9 P3 A9

F4 DDR2_A10 M2 A10

D3 DDR2_A11 P7 A11

G6 DDR2_A12 R2 A12

L2 DDR2_DQ0 G8 DQ0

L1 DDR2_DQ1 G2 DQ1

K2 DDR2_DQ2 H7 DQ2

K1 DDR2_DQ3 H3 DQ3

H2 DDR2_DQ4 H1 DQ4

H1 DDR2_DQ5 H9 DQ5

J3 DDR2_DQ6 F1 DQ6

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Chapter 1: SP601 Evaluation Board

Table 1-5: DDR2 Component Memory Connections (Cont’d)

FPGA U1

J1 DDR2_DQ7 F9 DQ7

M3 DDR2_DQ8 C8 DQ8

M1 DDR2_DQ9 C2 DQ9

N2 DDR2_DQ10 D7 DQ10

N1 DDR2_DQ11 D3 DQ11

T2 DDR2_DQ12 D1 DQ12

T1 DDR2_DQ13 D9 DQ13

U2 DDR2_DQ14 B1 DQ14

U1 DDR2_DQ15 B9 DQ15

F2 DDR2_BA0 L2 BA0

F1 DDR2_BA1 L3 BA1

E1 DDR2_BA2 L1 BA2

Schematic Net Name

Pin Number Pin Name

Memory U2

E3 DDR2_WE_B K3 WE

L5 DDR2_RAS_B K7 RAS

K5 DDR2_CAS_B L7 CAS

K6 DDR2_ODT K9 ODT

G3 DDR2_CLK_P J8 CK

G1 DDR2_CLK_N K8 CK

H7 DDR2_CKE K2 CKE

L4 DDR2_LDQS_P F7 LDQS

L3 DDR2_LDQS_N E8 LDQS

P2 DDR2_UDQS_P B7 UDQS

P1 DDR2_UDQS_N A8 UDQS

K3 DDR2_LDM F3 LDM

K4 DDR2_UDM B3 UDM

References

See the Elpida DDR2 SDRAM Specifications for more information. [Ref 11]

Also, see the

Spartan-6 FPGA Memory Controller User Guide. [Ref 3]

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3. SPI x4 Flash

SPI Prog

FPGA_D1_MISO2

J12

FPGA_D2_MISO3

FPGA_PROG_B

FPGA_MOSI_CSI_B_MISO0

SPI_CS_B

FPGA_CCLK

FPGA_D0_DIN_MISO_MISO1

UG518_04_040910

GND

VCC3V3

Silkscreen

TMS

TDI

TDO

TCK

GND

3V3

HDR_1X9

The Xilinx Spartan-6 FPGA hosts a SPI interface which is accessible to the Xilinx iMPACT configuration tool. The SPI memory device operates at 3.0V; the Spartan-6 FPGA I/Os are

3.3V tolerant and provide electrically compatible logic levels to directly access the SPI flash

through a 2.5V bank. The XC6SLX16-2CSG324 is a master device when accessing an external SPI flash memory device.

The SP601 SPI interface has two parallel connected configuration options (see Figure 1-4): an SPI X4 (Winbond W25Q64VSFIG) 64-Mb flash memory device and a flash programming header (J12). J12 supports a user-defined SPI mezzanine board. The SPI configuration source is selected via SPI select jumper J15. For details on configuring the FPGA, see 15. Configuration Options.

X-Ref Target - Figure 1-3

Detailed Description

Figure 1-3: J12 SPI Flash Programming Header

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Chapter 1: SP601 Evaluation Board

FPGA SPI INTERFACE

U17

J12

SPI X4 FLASH

MEMORY

WINBOND

W25Q64VSFIG

SPI PROGRAM

HEADER

SPI SELECT

JUMPER

ON = SPI X4 U17 OFF = SPI EXT. J12

SPIX4_CS_B

DIN,DOUT,CCLK

SPI_CS_B

J15

UG518_07_070809

X-Ref Target - Figure 1-4

Figure 1-4: SPI Flash Interface Topology

Table 1-6: SPI x4 Memory Connections

FPGA U1

V2 FPGA_PROG_B 1

V14 FPGA_D2_MISO3 1 IO3_HOLD_B 2

T14 FPGA_D1_MISO2_R 9 IO2_WP_B 3

V3 SPI_CS_B 4 TMS

T13 FPGA_MOSI_CSI_B_MISO0 15 DIN 5 TDI

R13 FPGA_D0_DIN_MISO_MISO1 8 IO1_DOUT 6 TDO

R15 FPGA_CCLK 16 CLK 7 TCK

Schematic Net Name

SPI MEM U17 SPI HDR J12

Pin # Pin Name

Number

8GND

9 VCC3V3

J15.2 SPIX4_CS_B 7 CS_B

References

Pin Name

16 www.xilinx.com SP601 Hardware User Guide

See the Winbond Serial Flash Memory Data Sheet for more information. [Ref 12]

See the XPS Serial Peripheral Interface Data Sheet for more information. [Ref 4]

UG518 (v1.7) September 26, 2012

4. Linear Flash BPI

An 8-bit (16 MB) Numonyx linear flash memory (TE28F128J3D-75) (J3D type) is used to provide non-volatile bitstream, code, and data storage. The J3D devices operate at 3.0V; the Spartan-6 FPGA I/Os are 3.3V tolerant and provide electrically compatible logic levels to directly access the linear flash BPI through a 2.5V bank. For details on configuring the FPGA, see 15. Configuration Options.

X-Ref Target - Figure 1-5

Detailed Description

U1 U10

FPGA

BPI FLASH

INTERFACE

ADDR, DATA, CTRL

Figure 1-5: Linear Flash BPI Interface

Table 1-7: BPI Memory Connections

FPGA U1 Pin Schematic Net Name

K18 FLASH_A0 32 A0

K17 FLASH_A1 28 A1

J18 FLASH_A2 27 A2

J16 FLASH_A3 26 A3

G18 FLASH_A4 25 A4

G16 FLASH_A5 24 A5

NUMONYX TYPE J3vD

T28F128J3D-75

UG518_09_070809

BPI Memory U10

Pin Number Pin Name

H16 FLASH_A6 23 A6

H15 FLASH_A7 22 A7

H14 FLASH_A8 20 A8

H13 FLASH_A9 19 A9

F18 FLASH_A10 18 A10

F17 FLASH_A11 17 A11

K13 FLASH_A12 13 A12

K12 FLASH_A13 12 A13

E18 FLASH_A14 11 A14

E16 FLASH_A15 10 A15

G13 FLASH_A16 8 A16

SP601 Hardware User Guide www.xilinx.com 17

UG518 (v1.7) September 26, 2012

+ 37 hidden pages

XILINX SP601 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Revision History

Table of Contents

About This Guide

Guide Contents

Additional Documentation

Additional Support Resources

SP601 Evaluation Board

Overview

Additional Information

Features

Related Xilinx Documents

Block Diagram

Detailed Description

1. Spartan-6 XC6SLX16-2CSG324 FPGA

2. 128 MB DDR2 Component Memory

3. SPI x4 Flash

4. Linear Flash BPI