Xilinx MP3 NG Application Note

XAPP169 (v1.0) November 24, 1999 www.xilinx.com 1

1-800-255-7778

Summary This application note illustrates the use of Xilinx Spartan-II FPGA and an IDT RC32364 RISC

controller in a handheld, consumer electronics platform. Specifically the target application is an
MP3 audio player with advanced user interface features.

In this application the Spartan device is used to implement the complex system level glue logic
required to interface and manage the memory and I/O devices. The RC32364 implements the
MP3 decoding functions, the graphical user interface, and various device control functions.

Introduction While the design is targeted at solving a specific problem, decoding and playing compressed

audio streams, it illustrates solutions to a number of general technical issues. These include:

• Supporting a graphical user interface in an embedded system.

• Implementing cost-effective interfaces to LCD displays, touch screens, USB, IRDA, and
CompactFlash in an embedded system.

• Error handling when using NAND FLASH memory.

• Controlling SDRAM memory.

MP3
Background

MP3 Market

The MP3 player market emerged in late 1998, when Diamond Multimedia shipped its Rio MP3
audio player. While there is considerable diversity in opinions about the potential size of this
market, market analysts all agree that the opportunity is significant and will experience rapid
growth in the short term. Like any new market, the feature set of MP3 players is likely to change
as more users buy them. Key dynamics in this market include:

• Copy Protection. While the Secure Digital Music Initiative (SDMI) promises to make a
wider variety of music available in MP3 format, there is considerable technical uncertainty
about implementation timetables.

• Non-MP3 Formats. While MP3 is the dominant format for music available on the Internet,
other large players are pushing other formats tailored to their business agendas.

• Extended Features. At $150 to $250 an MP3 player is a relatively expensive consumer
electronics purchase. The dominant component of that price is the FLASH memory that
these devices use. This cost component is more or less the same for all vendors, and
constrains price point differentiation. One way to increase the perceived value of an MP3
player, and therefore get a competitive advantage, is to add value added features tailored to
the target market.

Due to these market dynamics, including the potential for rapid changes in feature
requirements, the best approach is a flexible high-performance system. This flexibility
manifests itself in two forms. The first is the use of a high-performance processor, which
supports the addition of additional soft features without the need to resort to optimized
assembly language. The second is the use of a low-cost, high-density FPGA to provide flexible
I/O support for the processor.

MP3 NG: A Next Generation Consumer
Platform

XAPP169 (v1.0) November 24, 1999 Application Note

R

Applicat i o n N o te : Sp a r tan-II

2 www.xilinx.com XAPP169 (v1.0) November 24, 1999

1-800-255-7778

MP3 NG: A Next Generation Consumer Platform

R

MP3 Technology

MP3 refers to the MPEG Layer 3 audio compression scheme that was defined as part of the
International Standards Organization (ISO) Moving Picture Experts Group (MPEG) audio/video
coding standard. MPEG-I defined three encoding schemes, referred to as Layer 1, Layer 2, and
Layer 3. Each of these schemes uses increasing sophisticated encoding techniques and gives
correspondingly better audio quality at a given bit rate. The three layers are hierarchical, in that
a Layer 3 decoder can decode Layer 1, 2, and 3 bitstreams; a Layer 2 decoder can decode
Layer 2, and 1 bitstreams; and a Layer 1 decoder can only decode Layer 1 bitstreams. Each of
the layers support decoding audio sampled at 48, 44.1, or 32 kHz. MPEG 2 uses the same
family of codecs but extends it by adding support for 24, 22.05, or 16 kHz sampling rates as well
as more audio channels for surround sound and multilingual applications.

All Layers use the same basic structure. The coding scheme can be described as "perceptual
noise shaping" or "perceptual subband / transform coding". The encoder analyzes the spectral
components of the audio signal by calculating a filterbank (transform) and applies a psycho­acoustic model to estimate the just noticeable noise-level. In its quantization and coding stage,
the encoder tries to allocate the available number of data bits in a way to meet both the bitrate
and masking requirements. In plain English, the algorithm exploits the fact that loud sounds
mask out the listener’s ability to perceive quieter sounds in the same frequency range. The
encoder uses this property to remove information from the signal that would not be heard
anyway.

Like all of the MPEG compression technologies, the algorithms are designed so that the
decoder is much less complex. Its only task is to synthesize an audio signal out of the coded
spectral components. All Layers use the same analysis filter bank (polyphase with 32 sub­bands). Layer 3 adds a MDCT transform to increase the frequency resolution.

All layers use the same header information in their bitstream to support the hierarchical
structure of the standard.

Solution
Overview

A key design objective for this application was the creation of a solution with the lowest possible
cost, while at the same time providing support for value added features. These features include
the ability to store contact information and record memos and other functions commonly found
in Personal Digital Assistants (PDAs).

Figure 1 gives an overview of the design. The key features of which are:

• 128 x 128 pixel graphical touch screen.

• USB interface for download music and network connectivity.

• IRDA compliant infrared interface for exchanging data with other units.

• 32 MB of on board FLASH storage.

• CompactFlash interface for storage expansion using CompactFlash cards or MicroDrive

hard drives.

All of this is driven by a high-performance IDT RC32364 32-bit RISC processor and interfaced
using a next generation Spartan-II FPGA. Before the functions implemented in the Spartan
device and the software function running on the RC32364 are examined, the following gives an
overview of the Application Specific Standard Products (ASSPs) that are included in the
design.

MP3 NG: A Next Generation Consumer Platform

XAPP169 (v1.0) November 24, 1999 www.xilinx.com 3

1-800-255-7778

R

IDT RC32364 RISController™

The processor chosen for this design is the IDT RC32364. The features of this device that are
leveraged in this application are:

• Paged memory management unit.

• High-performance, 175 dhrystone MIPs at 133 MHz.

• Integer Multiply ACcumulate (MAC) support, 67M MACs/second at 133 MHz.

• Separate, line lockable, instruction (8 KB) and data (2 KB) caches.

• Power saving features including active power management and a power-down operating

mode.

• On-chip In Circuit Emulation (ICE) interface to provide access to internal CPU state
(registers, cache) and for debug control (breakpoints, single step, insert instructions into
pipeline).

Figure 2 shows the block diagram for this device. The complete data sheet for the RC32364

can be found at the following URL:

http://www.idt.com/docs/79RC32364_DS_32100.pdf

The RC32364’s MMU consists of address translation logic and a Translation Lookaside Buffer
(TLB) capable of supporting demand paged virtual memory. In addition, it includes several
features that are valuable in an embedded application such as variable sized pages and
lockable TLB entries. Figure 3 illustrates the virtual to physical address translation performed
by the RC32364.

RC32364

RISC

CPU

Addr/Data

Control

32
21

Xilinx

Spartan II

FPGA

CS4343

Audio

DAC

MT48LC1M16A1

SDRAM

KM29U64000T

FLASH

USBN9602

USB

Interface

8

Control

9

Control

11

Data

16

8

Serial Audio

3

Control Port

2

MAX1108
2 Channel

ADC

Serial Data

3

Serial Data

7

SED1758
LCD Row

Driver

Serial Data

2

SED1743

LCD Column

Driver

128 x 128

LCD Panel

&

4 Wire T ouch

Membrane

128

128

R

L

To Stereo

Headphone

Jack

IRMS6100

IRDA

Transceiver

3

Address

11

Control17

CompactFlash

Interface

Control

3

IRQ

Figure 1: MP3 NG System Block Diagram

4 www.xilinx.com XAPP169 (v1.0) November 24, 1999

1-800-255-7778

MP3 NG: A Next Generation Consumer Platform

R

The variable page size lets each mapping independently represent memory regions that can
range from 4 KB to 16 MB. This feature lets the system designer adjust the address mapping
granularity for different memory regions.

Locking TLB entries excludes entries from being recommended for replacement when there is
an address miss. This lets the system designer have mappings for critical regions of code and
or data locked into the TLB for predictable real time performance.

System Co ntrol

Coprocessor (CPO)

2kB D-Cache, 2-set,

Clock

Enhanced JTAG (ICE Interface)

TLB

MMU

lockable, write-back/write-through

Generation

Unit

RC32364 B u s Inter face U n it

8kB

I-Cache,

lockable

2-set,

RISCore32300 Internal Bus Interface

RISCore 400 0 Co m pat ible

w/

RISCore 323 00

TM

Extended MIPS 32
Integer CPU Core

Figure 2: RC32364 Block Diagram

(

Courtesy IDT)

28 11 0

20 12

2931

VPN

Offset

3239

ASID

8

Virtual Address with 1M (220) 4-Kbyt e pages

23

0

8 24

Offset

39

Virtual Address with 256 (28)16-Mbyte pages

8 bits = 256 pages

20 bits = 1M

12

ASID

8

28 293132

VPN

24

Virtual-to­physical transla­tion in TLB

Bits 31, 30 and 29 of the
virtual address select user, super­visor, or kernel address spaces.

Offset passed
unchanged to
physical memory

Virtual-to-physical-

translation in TLB

TLB

TLB

31 0

PFN

Offset

32-bit Physical Address

Offset pa ssed
unchanged to physical
memory.

Figure 3: RC32364 Address Translation

(Courtesy IDT)

MP3 NG: A Next Generation Consumer Platform

XAPP169 (v1.0) November 24, 1999 www.xilinx.com 5

1-800-255-7778

R

The RC32364 interfaces to the system through a 32-bit multiplexed address/data bus. The bus
offers a rich set of signals to control transfers of which only a subset was required for this
application. Figure 4 shows the timing for read transactions on this bus.

MasterClock

AD(31:0)

Addr

Data Inpu t

Addr(3:2)

ALE

DataEn*

Ack*

Last*

Rd*

CIP*

I/D*

DT/R*

Wr*

Addr

Data In put

Width(1:0)

Figure 4: RC32364 Read Timing

(Courtesy IDT)

6 www.xilinx.com XAPP169 (v1.0) November 24, 1999

1-800-255-7778

MP3 NG: A Next Generation Consumer Platform

R

Crystal CS4343
Stereo DAC

The Digital-to-Analog Converter chosen for this design is the Crystal CS4343 from Cirrus
Logic. This device features:

• 1.8V to 3.3V operation.

• 24-bit conversion at up to 96 kHz.

• Digital volume control.

• Digital bass and treble boost.

• Built-in headphone amplifier capable of delivering 5 mW into a 16

Ω load.

Figure 5 shows the block diagram for this device.

The CS4343 provides three interfaces: the analog stereo headphone interface, the serial port
used to transfer digital audio data streams, and the control port used to configure the device.

The control port is an industry standard I

2

C slave interface. I2C is a multidrop, 2-wire, serial
interface consisting of a clock (SCL) and data (SDA) and operating at up to 100 kHz. (See

Figure 7 Control Port Timing.) The control port is used to configure device features such as

volume, muting, equalization, power management, and the operating mode of the serial port.

Figure 1 on page 3 gives an overview of control port timing. A detailed description of I

2

C

operation can be found in the I

2

C specification as described in the references.

LK/DEM

SDATA

DIF1/SDA

MCLK

VA_HP

HP

SERIAL

PORT

DE-

CONTROL PORT

∆Σ

DAC

RST

LRCK

DIF0/SCL

VA

VD_IO

DIGITAL

VOLUME

CONTROL

BASS/TREBLE

BOOST

COMPRESSION

LIMITING

∆Σ

DAC

DIGITAL
FILTERS

ANALOG

FILTER

ANALOG

FILTER

GND FILT+ REF_GND

ANALOG
VOLUME

CONTROL

HEAD-

PHONE

AMPLIFIER

ANALOG
VOLUME

CONTROL

HP

EMPHASIS

VQ_HP

Figure 5: CS4343 Block Diagram

(Courtesy Cirrus Logic)

MP3 NG: A Next Generation Consumer Platform

XAPP169 (v1.0) November 24, 1999 www.xilinx.com 7

1-800-255-7778

R

The serial port can be configured for several operating modes. The mode of operation chosen
for this application is referred to in the CS4343 documentation as "Serial Audio Format 2".

Figure 7 gives an overview of serial port timing when in this mode.

t

buf

t

hdst

t

hdst

t

low

t

r

t

f

t

hdd

t

high

t

sud

t

sust

t

susp

Stop Start

Start

Stop

Repeated

SDA

SCL

t

irs

RST

Figure 6: Control Port Timing

(Courtesy Cirrus Logic)

Figure 7: Serial Port Timing

(Courtesy Cirrus Logic)

LRCK

SCLK

Left Channel

Right Channel

SDATA

6543210987

15 14 13 12 11 10

6543210987

15 14 13 12 11 10

8 www.xilinx.com XAPP169 (v1.0) November 24, 1999

1-800-255-7778

MP3 NG: A Next Generation Consumer Platform

R

Samsung
FLASH Memory

The FLASH memory chosen for this design is the KM29U64000T 8M x 8 device from Samsung
Semiconductor. This device is based on NAND FLASH technology and is popular in MP3 player
applications due to its high density and low cost per bit.

Figure 8 shows the block diagram for this device. The complete data sheet for the

KM29U64000T can be found at the following URL:

http://www.usa.samsungsemi.com/products/prodspec/flash/km29u64000(i)t.pdf

Unfortunately this device also has two characteristics that present significant system level
design challenges. The first of these is the narrow, highly multiplexed interface that is used to
access the device. The KM29U64000T interfaces to the system through an 8-bit wide port that
is used for both address and data. Figure 9 illustrates the read timing for this device.

The second and most challenging issue relates to data integrity, which is an issue common to
most devices using NAND technology. There are two aspects to this, the first of which is the fact
that devices when shipped may have memory blocks that may not be used due to data errors.
The data sheet for the device has a parameter called N

VB

that is the number valid blocks that

the device contains. The value of N

VB

varies from device to device and is specified to have a
minimum of 1014, a maximum of 1024, and typically 1020. While the first block is guaranteed
to be good, bad blocks can occur at any other location within the memory array . Invalid blocks
are marked at the factory by storing a "0" value at location "0" in either the first or second block
of the page. The system level impact of this is that it must keep track of which blocks are good
within the device and that this results in a non-contiguous memory map.

The second issue is that while the device is guaranteed to provide at least the minimum number
of valid blocks over its operational lifetime these devices may experience failures in additional
blocks throughout their life. In order to ensure system integrity some form of error detection and
correction must be implemented.

The discussion of the FLASH memory interface will discuss how these issues were addressed
in this design.

X-Buffers

Y-Gating

64M + 2M Bit

Command

2nd half Page Register & S/A

NAND Flash

ARRAY

(512 + 16)Byte x 16384

Y-Gating

1st half Page Register & S/A

I/O Buffers & Latches

Latches
& Decoders

Y-Buffers
Latches
& Decoders

Register

Control Logic

& High Voltage

Generator

Global Buffers

Output

Driver

A9 - A22

A0 - A7

Command

CE
RE
WE

CLE ALE WP

I/0 0
I/0 7

VCCQ
V

SS

A8

Figure 8: KM29U64000T Block Diagram

(Courtesy Samsung Semiconductor)

MP3 NG: A Next Generation Consumer Platform

XAPP169 (v1.0) November 24, 1999 www.xilinx.com 9

1-800-255-7778

R

Micron SDRAM
Memory

The SDRAM memory chosen for this design is the MT48LC1M16A1S - 512K x 16 x 2 bank
device from Micron Semiconductor. This device is available in speed grades from 125 to 166
MHz operating over an LVTTL synchronous interface. Figure 10 shows the block diagram for
this device. Figure 11 shows the MT48LC1M16A1 read timing of the device. The complete data
sheet for the MT48LC1M16 can be found at the following URL:

http://www.micron.com/mti/msp/pdf/datasheets/16MSDRAMx16.pdf

CE

CLE

R/B

I/O0 - 7

WE

ALE

RE

Busy

00h or 01h

A0 ~ A 7

A9 ~ A 16

A17 ~ A 22

Dout N Dout N+1 Dout N+2

Dout N+3 Dout 527

Column
Address

Page(Row)
Address

tWB

tAR2

tR

tRC

tRHZ

tRR

tCHZ

tCEH

tRB

tCRY

tWC

»

»»

Figure 9: KM29U64000T Read Timing

(Courtesy Samsung Semiconductor)