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Compal confidential |
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Liverpool 10AR/10ARG |
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KSWAE LA-4971P Schematics Document |
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Mobile AMD S1G2 S1G3/ |
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RS780MN & RS780MC & RX781 & RS880 / |
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SB700 & SB710 |
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2009-04-22 Rev. 1.0 |
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Security Classification |
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Compal Secret Data |
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Compal Electronics, Inc. |
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Issued Date |
2008-09-25 |
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Deciphered Date |
2009-09-25 |
Title |
Cover Sheet |
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THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL |
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AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D |
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Custom |
LA-4971P |
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1.0 |
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DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS |
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MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. |
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Date: |
Wednesday, April 22, 2009 |
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A |
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E |
Compal Confidential |
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AM DS 1G2 CPU |
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The rma lSe nso r |
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Fan Con |
trol |
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Mod |
elN |
ame :KS WA E/ KTW AE |
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File |
Nam |
e: LA-497 1P |
ATI |
M92 |
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uFCPGA-638 Package |
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ADM1032ARMZ |
page 6 |
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APL5607KI-TRG |
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page 4 |
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with VRAM |
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Grif |
inP latf orm |
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Hyp erT ran spo rtL |
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page 4,5,6,7 |
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1 |
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ink 2.6GH z |
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16X 16 |
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200 pin DD RI-SO -DIM MX 2 |
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VG AM XM Con n |
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ATI |
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Page 19 |
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BANK 0, 1, 2, 3 |
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page 8,9 |
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RS780MN |
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Mem |
ory BUS (DD RI) |
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Dua |
lCh ann el |
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CR T |
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RS780MC |
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1.8V DD RI667 /80 0MH Z |
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page 16 |
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RX781 |
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LCD |
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Con n. |
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RS880 |
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page 17 |
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HD MI CEC Con troler |
HD MI Con n. |
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EC SMBUS |
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R5F211A4SP |
page 18 |
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page 18 |
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2 |
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PCIe 4x |
1.5V 2.5GHz(250MB/s) |
page 10,11,12,13,14 |
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A-Link |
Exp res sI |
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4X PCI -E |
Rig htU SB Con |
n |
Int.Cam era |
Blu eto oth |
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ATI |
USB Port 0,1 |
page 32 |
USBPort 9 page 32 |
USBPort 6 page 32 |
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RTL |
810 3EL |
LAN |
10/ 100 M |
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PCI eMi niC |
ard WLA |
N |
NEW |
Car d |
USB |
5V 480MHz |
SB700 |
USB 5x |
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USB port 11 |
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SB710 |
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PCIe port 3 |
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page 26 |
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PCIe Port 2 |
page 27 |
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page 27 |
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5V 480MHz |
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PCIe port 0 |
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RJ4 5 |
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eSA |
TA |
SATA |
5V 1.5GHz(150MB/s) |
WLA |
N |
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Fing erP rint er |
RTS 515 9E 3IN1 |
3IN1 |
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USBPort 8 |
page 27 |
USBPort 7 page 27 |
USBPort 4 page 29 |
page 29 |
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page 26 |
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USB port 2 |
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USB |
5V 480MHz |
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SATA port 2 |
page 25 |
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PCI BUS 3.3V 33 MHz |
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SATA |
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SAT AH DD 1 |
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SATA port 0 page 25 |
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5V 1.5GHz(150MB/s) |
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3 |
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Car dBu sC ont roler |
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SATA |
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SAT AO DD |
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Clo ckG |
ene rato |
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USB |
/B |
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OZ601 |
page 28 |
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page 20,21,22,23,24 |
5V 1.5GHz(150MB/s) |
SATA port 3 page 25 |
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SLG8SP626VTR page 15 |
page 32 |
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LPC BUS 3.3V 33 MHz |
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RTC |
CKT . |
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Pow |
er/ B |
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HD Audio |
3.3V 24.576MHz/48Mhz |
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page 37 |
page 35 |
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Deb |
ugP ort |
ENE |
KB9 |
26 D3 |
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page 33 |
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page 34 |
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Pow |
erO n/O fCK T. |
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SW /B |
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MD C1 .5 |
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HD AC ode c |
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page 35 |
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page 35 |
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page 33 |
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ALC272 |
page 30 |
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Gs ens or |
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Tou ch Pad |
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Int.KBD |
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SPI RO M |
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DC /DC |
Inte rfac eC KT. |
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page 35 |
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page 35 |
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page 33 |
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page 33 |
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page 36 |
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RJ1 1 |
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AM PLI FIE R |
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MIC |
CO NN |
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Int.MIC |
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HP CO NN |
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Vol ume Con trol |
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page 33 |
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TPA6017 |
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page 31 |
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page 31 |
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page 31 |
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page 31 |
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page 31 |
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Pow |
erC |
ircu itD C/D C |
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page 37,38,39,40 |
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4 |
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41,42,43,44 |
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SPK CO NN |
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page 31 |
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Security Classification |
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Compal Secret Data |
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Compal Electronics, Inc. |
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||||
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|||
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Issued Date |
2008-09-25 |
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Deciphered Date |
2009-09-25 |
Title |
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Block Diagram |
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|||
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THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL |
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||||||
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AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D |
Size |
Document Number |
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Rev |
|||||
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Custom |
LA-4971P |
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1.0 |
||||||
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DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS |
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MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. |
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Date: |
Wednesday, April 22, 2009 |
Sheet |
2 |
of |
45 |
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A |
B |
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C |
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D |
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E |
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A |
B |
C |
D |
E |
1
2
3
4
Voltage Rails
O : ON
X : OFF
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+5VS |
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power |
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+3VS |
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+2.5VS |
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plane |
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+1.8VS |
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+1.5VS |
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+B |
+5VALW |
+1.8V |
+1.1VS |
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+VGA_CORE |
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+3VL |
+3VALW |
+0.9V |
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+1.2V_HT |
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+5VL |
+1.2VALW |
+0.9V |
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State |
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+CPU_CORE_NB |
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+RTCVCC |
+3V_LAN |
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+CPU_CORE_0 |
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+CPU_CORE_1 |
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S0 |
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O |
O |
O |
O |
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S1 |
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O |
O |
O |
O |
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S3 |
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O |
O |
O |
X |
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S5 S4/AC |
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O |
O |
X |
X |
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S5 S4/ Battery only |
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O |
X |
X |
X |
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S5 S4/AC & Battery |
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X |
X |
X |
X |
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don't exist |
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I2C / SMBUS ADDRESSING |
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DEVICE |
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HEX |
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ADDRESS |
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DDR SO-DIMM 0 |
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A0 |
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1 0 1 0 0 0 0 0 |
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DDR SO-DIMM 1 |
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A4 |
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1 0 1 0 0 1 0 0 |
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CLOCK GENERATOR (EXT.) |
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D2 |
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1 1 0 1 0 0 1 0 |
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EC SM Bus1 address |
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Device |
HEX |
Address |
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Smart Battery |
16H |
0001 011X b |
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HDMI-CEC |
34H |
0011 010X b |
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EC KB926D2 |
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EC SM Bus2 address |
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Device |
HEX |
Address |
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ADI1032-1 CPU |
98H |
1001 100X b |
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ADI1032-2 VGA |
9AH |
1001 101X b |
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EC KB926D2 |
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Ext. VGA/B
CS/B
Symbol Note : |
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: Digital Ground |
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Platform |
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Item |
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CPU |
NB |
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VGA |
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SB |
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Comment |
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GM@ |
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S1G2 |
RS780MC |
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NA |
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SB700 |
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PUMA@ |
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GM@ |
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S1G2 |
RS780MN |
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NA |
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SB700 |
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: Analog Ground |
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PM@+GPM@ |
S1G2 |
RS780MN |
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MXM |
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SB700 |
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PM@+PM1@ |
S1G2 |
RX781 |
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MXM |
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SB700 |
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||||||||
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@ : just reserve , no build |
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1 |
|||||||||||||
DEBUG@ : reserve for debug. |
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Platform |
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Item |
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CPU |
NB |
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VGA |
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SB |
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Comment |
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GM@ |
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S1G3 |
RS880MC |
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NA |
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SB710 |
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L Layout Notes |
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TIGRIS@ |
GM@ |
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S1G3 |
RS880M |
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NA |
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SB710 |
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||||||||||||||||||||||
|
UMA@: means for RS780M. |
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PM@+GPM@ |
S1G3 |
RS880M |
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MXM |
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SB710 |
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PM@+PM1@ |
S1G3 |
RX881 |
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MXM |
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SB710 |
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BTO (Build-To-Order) |
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Option Table |
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|||||
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Function |
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Express card / PCMCIA |
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BLUE TOOTH |
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RJ11 |
SSD |
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SATA ODD |
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WiFi |
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G- sensor |
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3 in 1 card reader |
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||||||||||
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Description |
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( E / A ) |
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( B ) |
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( R ) |
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( S ) |
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( H ) |
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Explain |
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16" |
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17" |
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Half - size |
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First |
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Second |
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RTS5159 |
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BTO |
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EXPCARD@ / PCMCIA@ |
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BT@ |
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MDC@ |
SSD@ |
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16inch@ |
17inch@ |
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WLAN@ |
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WIMAX@ |
G@ + G_1st@ |
G@ + G_2nd@ |
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CARD@ |
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Function |
|
FingerPrinter |
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CAMERA & MIC |
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HDMI |
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LVDS wireset |
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DC-IN |
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CHIPSET |
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2 |
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Description |
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( F ) |
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(X) |
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(Y) |
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|||||||||||
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Explain |
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CAMERA |
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MIC |
|
AMD(UMA) |
|
ATI VGA/B |
|
COMMON |
|
Cost down |
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BTO |
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FP@ |
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CAM@ |
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MIC@ |
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IHDMI@ |
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HDMI@ |
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H@ |
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LVDSSET@ |
16inch_45@ |
17inch_45@ |
PUMA@ |
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TIGRIS@ |
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SMBUS Control Table |
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SOURCE |
INVERTER |
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BATT |
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HDMI |
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CPU |
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SODIMM |
CLK |
WLAN |
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LCD |
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HDMI |
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NEW |
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MXM |
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THERMAL |
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DDC |
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DDC |
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Thermal |
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CEC |
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GEN |
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CARD |
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I / II |
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ROM |
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ROM |
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Sensor |
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SENSOR |
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EC_SMB_CK1 |
|
KB926 |
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V |
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V |
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EC_SMB_DA1 |
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EC_SMB_CK2 |
|
KB926 |
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V |
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V |
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EC_SMB_DA2 |
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I2C_CLK |
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RS780M |
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V |
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|||||||
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I2C_DATA |
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3 |
||||||
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DDC_CLK0 |
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RS780M |
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V |
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||||||||
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DDC_DATA0 |
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DDC_CLK1 |
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RS780M |
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|||||||
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DDC_DATA1 |
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||||||||
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SCL0 |
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SB700 |
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V |
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V |
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V |
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||||||||
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SDA0 |
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SCL1 |
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SB700 |
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V |
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SDA1 |
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SCL2 |
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SB700 |
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SDA2 |
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SCL3 |
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SB700 |
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SDA3 |
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4 |
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Security Classification |
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Compal Secret Data |
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Compal Electronics, Inc. |
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Issued Date |
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2008-09-25 |
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Deciphered Date |
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2009-09-25 |
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Title |
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Notes List |
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THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL |
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AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D |
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LA-4971P |
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1.0 |
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DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS |
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MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. |
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Date: |
Wednesday, April 22, 2009 |
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Sheet 3 of 45 |
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A |
B |
C |
D |
E |
A |
B |
C |
D |
E |
< C1, C2 and C7 must be replaced to 10-uF for Caspian compatibility > |
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+1.2V_HT |
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VLDT CAP. |
Near CPU Socket |
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250 mil |
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1 |
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1 |
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1 |
1 |
1 |
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1 |
PUMA@ |
TIGRIS@ |
PUMA@ |
TIGRIS@ |
C3 |
C4 |
C5 |
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C6 |
C1 |
C1 |
C2 |
C2 |
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4.7U_0805_10V4Z |
10U_0805_10V6K |
4.7U_0805_10V4Z |
10U_0805_10V6K |
0.22U_0603_16V4Z |
0.22U_0603_16V4Z |
180P_0402_50V8J |
180P_0402_50V8J |
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2 |
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2 |
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2 |
2 |
2 |
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2 |
1 |
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1 |
10 H_CADIP[0..15] |
H_CADIP[0..15] |
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H_CADOP[0..15] |
H_CADOP[0..15] |
10 |
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10 |
H_CADIN[0..15] |
H_CADIN[0..15] |
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H_CADON[0..15] |
H_CADON[0..15] |
10 |
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+1.2V_HT |
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JCPUA |
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PUMA@ |
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C7 |
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D1 |
VLDT_A0 HT LINK |
VLDT_B0 |
AE2 |
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+VLDT_B |
1 |
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2 4.7U_0805_10V4Z |
< VLDT_A & VLDT_B : HyperTransport I/O ring power > |
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VLDT=500mA |
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D2 |
VLDT_A1 |
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VLDT_B1 |
AE3 |
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D3 |
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AE4 |
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D4 |
VLDT_A2 |
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VLDT_B2 |
AE5 |
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TIGRIS@ |
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VLDT_A3 |
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VLDT_B3 |
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C7 |
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H_CADIP0 |
E3 |
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AD1 |
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H_CADOP0 |
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10U_0805_10V6K |
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H_CADIN0 |
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E2 |
L0_CADIN_H0 |
L0_CADOUT_H0 |
AC1 |
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H_CADON0 |
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H_CADIP1 |
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E1 |
L0_CADIN_L0 |
L0_CADOUT_L0 |
AC2 |
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H_CADOP1 |
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H_CADIN1 |
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F1 |
L0_CADIN_H1 |
L0_CADOUT_H1 |
AC3 |
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H_CADON1 |
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H_CADIP2 |
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G3 |
L0_CADIN_L1 |
L0_CADOUT_L1 |
AB1 |
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H_CADOP2 |
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H_CADIN2 |
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G2 |
L0_CADIN_H2 |
L0_CADOUT_H2 |
AA1 |
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H_CADON2 |
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H_CADIP3 |
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G1 |
L0_CADIN_L2 |
L0_CADOUT_L2 |
AA2 |
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H_CADOP3 |
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H_CADIN3 |
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H1 |
L0_CADIN_H3 |
L0_CADOUT_H3 |
AA3 |
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H_CADON3 |
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2 |
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H_CADIP4 |
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J1 |
L0_CADIN_L3 |
L0_CADOUT_L3 |
W2 |
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H_CADOP4 |
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2 |
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H_CADIN4 |
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K1 |
L0_CADIN_H4 |
L0_CADOUT_H4 |
W3 |
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H_CADON4 |
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H_CADIP5 |
L3 |
L0_CADIN_L4 |
L0_CADOUT_L4 |
V1 |
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H_CADOP5 |
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H_CADIN5 |
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L2 |
L0_CADIN_H5 |
L0_CADOUT_H5 |
U1 |
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H_CADON5 |
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H_CADIP6 |
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L1 |
L0_CADIN_L5 |
L0_CADOUT_L5 |
U2 |
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H_CADOP6 |
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H_CADIN6 |
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M1 |
L0_CADIN_H6 |
L0_CADOUT_H6 |
U3 |
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H_CADON6 |
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H_CADIP7 |
N3 |
L0_CADIN_L6 |
L0_CADOUT_L6 |
T1 |
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H_CADOP7 |
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H_CADIN7 |
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N2 |
L0_CADIN_H7 |
L0_CADOUT_H7 |
R1 |
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H_CADON7 |
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H_CADIP8 |
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E5 |
L0_CADIN_L7 |
L0_CADOUT_L7 |
AD4 |
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H_CADOP8 |
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H_CADIN8 |
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F5 |
L0_CADIN_H8 |
L0_CADOUT_H8 |
AD3 |
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H_CADON8 |
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< From NB > |
H_CADIP9 |
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F3 |
L0_CADIN_L8 |
L0_CADOUT_L8 |
AD5 |
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H_CADOP9 |
< To NB > |
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H_CADIN9 |
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F4 |
L0_CADIN_H9 |
L0_CADOUT_H9 |
AC5 |
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H_CADON9 |
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H_CADIP10 |
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G5 |
L0_CADIN_L9 |
L0_CADOUT_L9 |
AB4 |
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H_CADOP10 |
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H_CADIN10 |
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H5 |
L0_CADIN_H10 |
L0_CADOUT_H10 |
AB3 |
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H_CADON10 |
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H_CADIP11 |
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H3 |
L0_CADIN_L10 |
L0_CADOUT_L10 |
AB5 |
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H_CADOP11 |
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H_CADIN11 |
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H4 |
L0_CADIN_H11 |
L0_CADOUT_H11 |
AA5 |
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H_CADON11 |
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H_CADIP12 |
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K3 |
L0_CADIN_L11 |
L0_CADOUT_L11 |
Y5 |
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H_CADOP12 |
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H_CADIN12 |
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K4 |
L0_CADIN_H12 |
L0_CADOUT_H12 |
W5 |
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H_CADON12 |
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H_CADIP13 |
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L5 |
L0_CADIN_L12 |
L0_CADOUT_L12 |
V4 |
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H_CADOP13 |
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H_CADIN13 |
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M5 |
L0_CADIN_H13 |
L0_CADOUT_H13 |
V3 |
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H_CADON13 |
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H_CADIP14 |
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M3 |
L0_CADIN_L13 |
L0_CADOUT_L13 |
V5 |
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H_CADOP14 |
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H_CADIN14 |
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M4 |
L0_CADIN_H14 |
L0_CADOUT_H14 |
U5 |
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H_CADON14 |
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H_CADIP15 |
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N5 |
L0_CADIN_L14 |
L0_CADOUT_L14 |
T4 |
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H_CADOP15 |
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H_CADIN15 |
P5 |
L0_CADIN_H15 |
L0_CADOUT_H15 |
T3 |
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H_CADON15 |
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J3 |
L0_CADIN_L15 |
L0_CADOUT_L15 |
Y1 |
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10 |
H_CLKIP0 |
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J2 |
L0_CLKIN_H0 |
L0_CLKOUT_H0 |
W1 |
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H_CLKOP0 |
10 |
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10 |
H_CLKIN0 |
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J5 |
L0_CLKIN_L0 |
L0_CLKOUT_L0 |
Y4 |
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H_CLKON0 |
10 |
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10 |
H_CLKIP1 |
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K5 |
L0_CLKIN_H1 |
L0_CLKOUT_H1 |
Y3 |
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H_CLKOP1 |
10 |
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10 |
H_CLKIN1 |
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N1 |
L0_CLKIN_L1 |
L0_CLKOUT_L1 |
R2 |
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H_CLKON1 |
10 |
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10 |
H_CTLIP0 |
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P1 |
L0_CTLIN_H0 |
L0_CTLOUT_H0 |
R3 |
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H_CTLOP0 |
10 |
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3 |
10 |
H_CTLIN0 |
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P3 |
L0_CTLIN_L0 |
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L0_CTLOUT_L0 |
T5 |
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H_CTLON0 |
10 |
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3 |
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10 |
H_CTLIP1 |
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P4 |
L0_CTLIN_H1 |
L0_CTLOUT_H1 |
R5 |
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H_CTLOP1 |
10 |
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10 |
H_CTLIN1 |
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L0_CTLIN_L1 |
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L0_CTLOUT_L1 |
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H_CTLON1 |
10 |
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@FOX_PZ63823-284S-41F_638P
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< FAN Control Circuit : Vout = 1.6 x Vset > |
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+5VS |
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1A |
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1 |
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D1 |
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2 |
@ |
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+FAN1 |
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C183 |
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1SS355_SOD323-2 |
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+3VS |
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1 |
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2 |
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JFAN |
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+FAN1 |
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C192 |
10U_0805_10V4Z |
1 |
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1 |
1 |
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10U_0805_10V4Z |
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1 |
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2 |
2 |
2 |
1 |
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3 |
3 |
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2 |
U6 |
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D2 |
C9 |
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R12 |
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1 |
EN |
GND |
8 |
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@ |
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@ |
4 |
GND |
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2 |
7 |
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BAS16_SOT23-3 |
1000P_0402_25V8J |
5 |
10K_0402_5% |
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3 |
VIN |
GND |
6 |
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2 |
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1 |
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GND |
2 |
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4 < From EC > 34 EN_DFAN1 |
VOUT |
GND |
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@ACES_85204-0300N_3P |
< To EC > |
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4 |
VSET |
GND |
5 |
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FAN_SPEED1 34 |
4 |
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2 |
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APL5607KI-TRG_SO8 |
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C8 |
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@ |
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0.01U_0402_25V7K |
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1 |
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Security Classification |
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Compal Secret Data |
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Compal Electronics, Inc. |
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|||||
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|||
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Issued Date |
2008-09-25 |
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Deciphered Date |
2009-09-25 |
Title |
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|
AMD CPU S1G2 HT I/F |
|
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|
|||||
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|
|
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL |
|
|
|
|
|
||||||||
|
|
|
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D |
Size |
Document Number |
|
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|
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|
Rev |
|||||
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Custom |
|
LA-4971P |
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1.0 |
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DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS |
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MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. |
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Date: |
Wednesday, April 22, 2009 |
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Sheet |
4 |
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45 |
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A |
B |
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C |
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D |
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E |
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A |
B |
C |
D |
E |
1
2
3
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< DDR2 VREF is 0.5 ratio > |
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< PLACE CLOSE TO PROCESSOR WITHIN 1.5 INCH > |
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< Processor DDR2 Memory Interface > |
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+1.8V |
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DDR_A_CLK0 |
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DDR_B_CLK0 |
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2 |
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1 |
C10 |
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1 |
C14 |
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R1 |
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1.5P_0402_50V9C |
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1.5P_0402_50V9C |
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JCPUC |
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1K_0402_1% |
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DDR_A_CLK#0 |
2 |
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DDR_B_CLK#0 |
2 |
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8 DDR_B_D[63..0] |
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DDR_B_D0 |
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MEM:DATA |
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DDR_A_D0 |
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DDR_A_D[63..0] |
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1 |
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< From/To SO_DIMMB > |
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C11 |
MB_DATA0 |
MA_DATA0 |
G12 |
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+MCH_REF |
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DDR_B_D1 |
A11 |
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F12 |
DDR_A_D1 |
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< From/To SO_DIMMA > |
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DDR_B_D2 |
A14 |
MB_DATA1 |
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MA_DATA1 |
H14 |
DDR_A_D2 |
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2 |
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1 |
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1 |
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DDR_A_CLK1 |
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DDR_B_CLK1 |
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DDR_B_D3 |
B14 |
MB_DATA2 |
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MA_DATA2 |
G14 |
DDR_A_D3 |
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R2 |
C12 |
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C13 |
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1 |
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1 |
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DDR_B_D4 |
G11 |
MB_DATA3 |
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MA_DATA3 |
H11 |
DDR_A_D4 |
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MB_DATA4 |
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MA_DATA4 |
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C11 |
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C15 |
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DDR_B_D5 |
E11 |
MB_DATA5 |
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MA_DATA5 |
H12 |
DDR_A_D5 |
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1K_0402_1% |
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0.1U_0402_16V7K |
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1000P_0402_25V8J |
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DDR_B_D6 |
D12 |
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C13 |
DDR_A_D6 |
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1 |
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1 |
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2 |
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2 |
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1.5P_0402_50V9C |
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1.5P_0402_50V9C |
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DDR_B_D7 |
A13 |
MB_DATA6 |
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MA_DATA6 |
E13 |
DDR_A_D7 |
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DDR_A_CLK#1 |
2 |
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DDR_B_CLK#1 |
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DDR_B_D8 |
A15 |
MB_DATA7 |
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MA_DATA7 |
H15 |
DDR_A_D8 |
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DDR_B_D9 |
A16 |
MB_DATA8 |
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MA_DATA8 |
E15 |
DDR_A_D9 |
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DDR_B_D10 |
A19 |
MB_DATA9 |
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MA_DATA9 |
E17 |
DDR_A_D10 |
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DDR_B_D11 |
A20 |
MB_DATA10 |
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MA_DATA10 |
H17 |
DDR_A_D11 |
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DDR_B_D12 |
C14 |
MB_DATA11 |
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MA_DATA11 |
E14 |
DDR_A_D12 |
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DDR_B_D13 |
D14 |
MB_DATA12 |
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MA_DATA12 |
F14 |
DDR_A_D13 |
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DDR_B_D14 |
C18 |
MB_DATA13 |
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MA_DATA13 |
C17 |
DDR_A_D14 |
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DDR_B_D15 |
D18 |
MB_DATA14 |
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MA_DATA14 |
G17 |
DDR_A_D15 |
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DDR_B_D16 |
D20 |
MB_DATA15 |
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MA_DATA15 |
G18 |
DDR_A_D16 |
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DDR_B_D17 |
A21 |
MB_DATA16 |
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MA_DATA16 |
C19 |
DDR_A_D17 |
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DDR_B_D18 |
D24 |
MB_DATA17 |
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MA_DATA17 |
D22 |
DDR_A_D18 |
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DDR_B_D19 |
C25 |
MB_DATA18 |
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MA_DATA18 |
E20 |
DDR_A_D19 |
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DDR_B_D20 |
B20 |
MB_DATA19 |
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MA_DATA19 |
E18 |
DDR_A_D20 |
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DDR_B_D21 |
C20 |
MB_DATA20 |
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MA_DATA20 |
F18 |
DDR_A_D21 |
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DDR_B_D22 |
B24 |
MB_DATA21 |
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MA_DATA21 |
B22 |
DDR_A_D22 |
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DDR_B_D23 |
C24 |
MB_DATA22 |
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MA_DATA22 |
C23 |
DDR_A_D23 |
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DDR_B_D24 |
E23 |
MB_DATA23 |
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MA_DATA23 |
F20 |
DDR_A_D24 |
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DDR_B_D25 |
E24 |
MB_DATA24 |
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MA_DATA24 |
F22 |
DDR_A_D25 |
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DDR_B_D26 |
G25 |
MB_DATA25 |
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MA_DATA25 |
H24 |
DDR_A_D26 |
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DDR_B_D27 |
G26 |
MB_DATA26 |
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MA_DATA26 |
J19 |
DDR_A_D27 |
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DDR_B_D28 |
C26 |
MB_DATA27 |
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MA_DATA27 |
E21 |
DDR_A_D28 |
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DDR_B_D29 |
D26 |
MB_DATA28 |
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MA_DATA28 |
E22 |
DDR_A_D29 |
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DDR_B_D30 |
G23 |
MB_DATA29 |
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MA_DATA29 |
H20 |
DDR_A_D30 |
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DDR_B_D31 |
G24 |
MB_DATA30 |
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MA_DATA30 |
H22 |
DDR_A_D31 |
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+0.9V |
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+0.9V |
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DDR_B_D32 |
AA24 |
MB_DATA31 |
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MA_DATA31 |
Y24 |
DDR_A_D32 |
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JCPUB |
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DDR_B_D33 |
AA23 |
MB_DATA32 |
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MA_DATA32 |
AB24 |
DDR_A_D33 |
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DDR_B_D34 |
AD24 |
MB_DATA33 |
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MA_DATA33 |
AB22 |
DDR_A_D34 |
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D10 |
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W10 |
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DDR_B_D35 |
AE24 |
MB_DATA34 |
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MA_DATA34 |
AA21 |
DDR_A_D35 |
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C10 |
VTT1 |
MEM:CMD/CTRL/CLK VTT5 |
AC10 |
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< VTT regulator voltage > |
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DDR_B_D36 |
AA26 |
MB_DATA35 |
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MA_DATA35 |
W22 |
DDR_A_D36 |
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Place them close to CPU within 1" |
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B10 |
VTT2 |
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VTT6 |
AB10 |
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DDR_B_D37 |
AA25 |
MB_DATA36 |
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MA_DATA36 |
W21 |
DDR_A_D37 |
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AD10 |
VTT3 |
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VTT7 |
AA10 |
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DDR_B_D38 |
AD26 |
MB_DATA37 |
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MA_DATA37 |
Y22 |
DDR_A_D38 |
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2 |
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VTT4 |
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VTT8 |
A10 |
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DDR_B_D39 |
AE25 |
MB_DATA38 |
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MA_DATA38 |
AA22 |
DDR_A_D39 |
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R4 |
1 |
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2 |
39.2_0402_1% |
MEM_P |
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AF10 |
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VTT9 |
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DDR_B_D40 |
AC22 |
MB_DATA39 |
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MA_DATA39 |
Y20 |
DDR_A_D40 |
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MEMZP |
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MB_DATA40 |
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MA_DATA40 |
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+1.8V |
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R3 |
1 |
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2 |
39.2_0402_1% |
MEM_N |
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AE10 |
MEMZN |
VTT_SENSE |
Y10 |
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VTT_SENSE |
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PAD |
T1 |
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DDR_B_D41 |
AD22 |
MB_DATA41 |
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MA_DATA41 |
AA20 |
DDR_A_D41 |
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DDR_B_D42 |
AE20 |
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AA18 |
DDR_A_D42 |
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T2 |
PAD |
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H16 |
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W17 |
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+MCH_REF |
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DDR_B_D43 |
AF20 |
MB_DATA42 |
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MA_DATA42 |
AB18 |
DDR_A_D43 |
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RSVD_M1 |
MEMVREF |
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DDR_B_D44 |
AF24 |
MB_DATA43 |
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MA_DATA43 |
AB21 |
DDR_A_D44 |
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9 DDR_A_ODT0 |
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DDR_A_ODT0 |
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T19 |
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B18 |
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PAD |
T3 |
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DDR_B_D45 |
AF23 |
MB_DATA44 |
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MA_DATA44 |
AD21 |
DDR_A_D45 |
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||||||||
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< To SO_DIMMA > |
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DDR_A_ODT1 |
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V22 |
MA0_ODT0 |
RSVD_M2 |
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DDR_B_D46 |
AC20 |
MB_DATA45 |
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MA_DATA45 |
AD19 |
DDR_A_D46 |
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9 DDR_A_ODT1 |
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U21 |
MA0_ODT1 |
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W26 |
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DDR_B_ODT0 |
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DDR_B_ODT0 8 |
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DDR_B_D47 |
AD20 |
MB_DATA46 |
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MA_DATA46 |
Y18 |
DDR_A_D47 |
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V19 |
MA1_ODT0 |
MB0_ODT0 |
W23 |
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DDR_B_ODT1 |
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< To SO_DIMMB > |
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DDR_B_D48 |
AD18 |
MB_DATA47 |
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MA_DATA47 |
AD17 |
DDR_A_D48 |
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MA1_ODT1 |
MB0_ODT1 |
Y26 |
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DDR_B_ODT1 |
8 |
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DDR_B_D49 |
AE18 |
MB_DATA48 |
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MA_DATA48 |
W16 |
DDR_A_D49 |
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9 DDR_CS0_DIMMA# |
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DDR_CS0_DIMMA# |
T20 |
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MB1_ODT0 |
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DDR_B_D50 |
AC14 |
MB_DATA49 |
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MA_DATA49 |
W14 |
DDR_A_D50 |
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|||||||||||||
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< To SO_DIMMA > |
|
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DDR_CS1_DIMMA# |
U19 |
MA0_CS_L0 |
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V26 |
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DDR_CS0_DIMMB# |
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DDR_B_D51 |
AD14 |
MB_DATA50 |
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MA_DATA50 |
Y14 |
DDR_A_D51 |
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||||||||||||||||||
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9 DDR_CS1_DIMMA# |
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U20 |
MA0_CS_L1 |
MB0_CS_L0 |
W25 |
|
DDR_CS1_DIMMB# |
|
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|
DDR_CS0_DIMMB# 8 |
< To SO_DIMMB > |
|
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DDR_B_D52 |
AF19 |
MB_DATA51 |
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MA_DATA51 |
Y17 |
DDR_A_D52 |
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V20 |
MA1_CS_L0 |
MB0_CS_L1 |
U22 |
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DDR_CS1_DIMMB# 8 |
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DDR_B_D53 |
AC18 |
MB_DATA52 |
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MA_DATA52 |
AB17 |
DDR_A_D53 |
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|||||||||||
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MA1_CS_L1 |
MB1_CS_L0 |
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DDR_B_D54 |
AF16 |
MB_DATA53 |
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MA_DATA53 |
AB15 |
DDR_A_D54 |
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||||||
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9 DDR_CKE0_DIMMA |
|
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|
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DDR_CKE0_DIMMA |
J22 |
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J25 |
|
DDR_CKE0_DIMMB |
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|
DDR_CKE0_DIMMB 8 |
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DDR_B_D55 |
AF15 |
MB_DATA54 |
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MA_DATA54 |
AD15 |
DDR_A_D55 |
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|||||||||||||||
|
|
< To SO_DIMMA > |
|
|
|
|
|
DDR_CKE1_DIMMA |
J20 |
MA_CKE0 |
MB_CKE0 |
H26 |
|
DDR_CKE1_DIMMB |
|
|
|
< To SO_DIMMB > |
|
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|
|
DDR_B_D56 |
AF13 |
MB_DATA55 |
|
|
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MA_DATA55 |
AB13 |
DDR_A_D56 |
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|||||||||||||||||||||||||
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|
|
9 DDR_CKE1_DIMMA |
|
|
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|
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MA_CKE1 |
MB_CKE1 |
|
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|
DDR_CKE1_DIMMB 8 |
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DDR_B_D57 |
AC12 |
MB_DATA56 |
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MA_DATA56 |
AD13 |
DDR_A_D57 |
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|||||||||||||||||||||
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N19 |
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P22 |
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DDR_B_D58 |
AB11 |
MB_DATA57 |
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MA_DATA57 |
Y12 |
DDR_A_D58 |
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||
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N20 |
MA_CLK_H0 |
MB_CLK_H0 |
R22 |
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DDR_B_D59 |
Y11 |
MB_DATA58 |
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|
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MA_DATA58 |
W11 |
DDR_A_D59 |
|
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||||||
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|
|
9 DDR_A_CLK0 |
|
|
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|
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|
|
DDR_A_CLK0 |
|
E16 |
MA_CLK_L0 |
MB_CLK_L0 |
A17 |
|
DDR_B_CLK0 |
|
|
|
DDR_B_CLK0 8 |
|
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DDR_B_D60 |
AE14 |
MB_DATA59 |
|
|
|
MA_DATA59 |
AB14 |
DDR_A_D60 |
|
|
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|
|||||||||||||||
|
|
< To SO_DIMMA > |
|
|
|
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|
|
DDR_A_CLK#0 |
|
F16 |
MA_CLK_H1 |
MB_CLK_H1 |
A18 |
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DDR_B_CLK#0 |
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< To SO_DIMMB > |
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DDR_B_D61 |
AF14 |
MB_DATA60 |
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MA_DATA60 |
AA14 |
DDR_A_D61 |
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9 DDR_A_CLK#0 |
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DDR_A_CLK1 |
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Y16 |
MA_CLK_L1 |
MB_CLK_L1 |
AF18 |
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DDR_B_CLK1 |
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DDR_B_CLK#0 8 |
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DDR_B_D62 |
AF11 |
MB_DATA61 |
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MA_DATA61 |
AB12 |
DDR_A_D62 |
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9 DDR_A_CLK1 |
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DDR_A_CLK#1 |
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AA16 |
MA_CLK_H2 |
MB_CLK_H2 |
AF17 |
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DDR_B_CLK#1 |
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DDR_B_CLK1 8 |
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DDR_B_D63 |
AD11 |
MB_DATA62 |
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MA_DATA62 |
AA12 |
DDR_A_D63 |
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9 DDR_A_CLK#1 |
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P19 |
MA_CLK_L2 |
MB_CLK_L2 |
R26 |
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DDR_B_CLK#1 |
8 |
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8 DDR_B_DM[7..0] |
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MB_DATA63 |
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MA_DATA63 |
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DDR_A_DM[7..0] |
9 |
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P20 |
MA_CLK_H3 |
MB_CLK_H3 |
R25 |
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DDR_B_DM0 |
A12 |
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E12 |
DDR_A_DM0 |
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< To SO_DIMMA > |
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9 DDR_A_MA[15..0] |
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MA_CLK_L3 |
MB_CLK_L3 |
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DDR_B_MA[15..0] 8 |
< To SO_DIMMB > |
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< To SO_DIMMB > |
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DDR_B_DM1 |
B16 |
MB_DM0 |
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MA_DM0 |
C15 |
DDR_A_DM1 |
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< To SO_DIMMA > |
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MB_DM1 |
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MA_DM1 |
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DDR_A_MA0 |
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N21 |
MA_ADD0 |
MB_ADD0 |
P24 |
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DDR_B_MA0 |
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DDR_B_DM2 |
A22 |
MB_DM2 |
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MA_DM2 |
E19 |
DDR_A_DM2 |
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DDR_A_MA1 |
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M20 |
N24 |
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DDR_B_MA1 |
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DDR_B_DM3 |
E25 |
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F24 |
DDR_A_DM3 |
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DDR_A_MA2 |
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N22 |
MA_ADD1 |
MB_ADD1 |
P26 |
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DDR_B_MA2 |
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DDR_B_DM4 |
AB26 |
MB_DM3 |
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MA_DM3 |
AC24 |
DDR_A_DM4 |
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DDR_A_MA3 |
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M19 |
MA_ADD2 |
MB_ADD2 |
N23 |
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DDR_B_MA3 |
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DDR_B_DM5 |
AE22 |
MB_DM4 |
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MA_DM4 |
Y19 |
DDR_A_DM5 |
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3 |
|||||||||
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DDR_A_MA4 |
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M22 |
MA_ADD3 |
MB_ADD3 |
N26 |
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DDR_B_MA4 |
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DDR_B_DM6 |
AC16 |
MB_DM5 |
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MA_DM5 |
AB16 |
DDR_A_DM6 |
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DDR_A_MA5 |
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L20 |
MA_ADD4 |
MB_ADD4 |
L23 |
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DDR_B_MA5 |
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DDR_B_DM7 |
AD12 |
MB_DM6 |
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MA_DM6 |
Y13 |
DDR_A_DM7 |
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|||||||||
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DDR_A_MA6 |
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M24 |
MA_ADD5 |
MB_ADD5 |
N25 |
|
DDR_B_MA6 |
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MB_DM7 |
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MA_DM7 |
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|||||||||
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|
DDR_A_MA7 |
|
L21 |
MA_ADD6 |
MB_ADD6 |
L24 |
|
DDR_B_MA7 |
|
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|
DDR_B_DQS0 |
C12 |
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G13 |
DDR_A_DQS0 |
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||||||||
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|
DDR_A_MA8 |
|
L19 |
MA_ADD7 |
MB_ADD7 |
M26 |
|
DDR_B_MA8 |
|
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|
8 DDR_B_DQS0 |
|
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|
|
DDR_B_DQS#0 |
B12 |
MB_DQS_H0 |
|
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|
MA_DQS_H0 |
H13 |
DDR_A_DQS#0 |
|
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|
DDR_A_DQS0 9 |
|
|
||||||||||||||
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|
DDR_A_MA9 |
|
K22 |
MA_ADD8 |
MB_ADD8 |
K26 |
|
DDR_B_MA9 |
|
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|
8 DDR_B_DQS#0 |
|
|
|
|
DDR_B_DQS1 |
D16 |
MB_DQS_L0 |
|
|
|
MA_DQS_L0 |
G16 |
DDR_A_DQS1 |
|
|
|
DDR_A_DQS#0 9 |
|
|||||||||||||||
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|
DDR_A_MA10 |
|
R21 |
MA_ADD9 |
MB_ADD9 |
T26 |
|
DDR_B_MA10 |
|
|
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|
|
8 DDR_B_DQS1 |
|
|
|
|
DDR_B_DQS#1 |
C16 |
MB_DQS_H1 |
|
|
|
MA_DQS_H1 |
G15 |
DDR_A_DQS#1 |
|
|
|
DDR_A_DQS1 9 |
|
|
||||||||||||||
|
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|
|
DDR_A_MA11 |
|
L22 |
MA_ADD10 |
MB_ADD10 |
L26 |
|
DDR_B_MA11 |
|
|
|
|
|
|
|
|
|
|
|
8 DDR_B_DQS#1 |
|
|
|
|
DDR_B_DQS2 |
A24 |
MB_DQS_L1 |
|
|
|
MA_DQS_L1 |
C22 |
DDR_A_DQS2 |
|
|
|
DDR_A_DQS#1 9 |
|
|||||||||||||||
|
|
|
|
|
|
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|
|
|
|
|
|
|
|
|
|
DDR_A_MA12 |
|
K20 |
MA_ADD11 |
MB_ADD11 |
L25 |
|
DDR_B_MA12 |
|
|
|
|
|
|
|
|
|
|
|
8 DDR_B_DQS2 |
|
|
|
|
DDR_B_DQS#2 |
A23 |
MB_DQS_H2 |
|
|
|
MA_DQS_H2 |
C21 |
DDR_A_DQS#2 |
|
|
|
DDR_A_DQS2 9 |
|
|
||||||||||||||
|
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|
DDR_A_MA13 |
|
V24 |
MA_ADD12 |
MB_ADD12 |
W24 |
|
DDR_B_MA13 |
|
|
|
|
|
|
|
|
|
|
|
8 DDR_B_DQS#2 |
|
|
|
|
DDR_B_DQS3 |
F26 |
MB_DQS_L2 |
|
|
|
MA_DQS_L2 |
G22 |
DDR_A_DQS3 |
|
|
|
DDR_A_DQS#2 9 |
|
|||||||||||||||
|
|
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|
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|
|
|
|
|
|
DDR_A_MA14 |
|
K24 |
MA_ADD13 |
MB_ADD13 |
J23 |
|
DDR_B_MA14 |
|
|
|
|
|
|
|
|
|
|
|
8 DDR_B_DQS3 |
|
|
|
|
DDR_B_DQS#3 |
E26 |
MB_DQS_H3 |
|
|
|
MA_DQS_H3 |
G21 |
DDR_A_DQS#3 |
|
|
|
DDR_A_DQS3 9 |
|
|
||||||||||||||
|
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|
|
DDR_A_MA15 |
|
K19 |
MA_ADD14 |
MB_ADD14 |
J24 |
|
DDR_B_MA15 |
|
|
|
|
|
|
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|
|
|
8 DDR_B_DQS#3 |
|
|
|
|
DDR_B_DQS4 |
AC25 |
MB_DQS_L3 |
|
|
|
MA_DQS_L3 |
AD23 |
DDR_A_DQS4 |
|
|
|
DDR_A_DQS#3 9 |
|
|||||||||||||||
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|
MA_ADD15 |
MB_ADD15 |
|
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|
8 DDR_B_DQS4 |
|
|
|
|
DDR_B_DQS#4 |
AC26 |
MB_DQS_H4 |
|
|
|
MA_DQS_H4 |
AC23 |
DDR_A_DQS#4 |
|
|
|
DDR_A_DQS4 9 |
|
|
|||||||||||
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|
DDR_A_BS#0 |
|
R20 |
|
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|
R24 |
|
DDR_B_BS#0 |
|
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|
8 DDR_B_DQS#4 |
|
|
|
|
DDR_B_DQS5 |
AF21 |
MB_DQS_L4 |
|
|
|
MA_DQS_L4 |
AB19 |
DDR_A_DQS5 |
|
|
|
DDR_A_DQS#4 9 |
|
||||||||||||
|
|
< To SO_DIMMA > |
|
9 DDR_A_BS#0 |
|
|
|
|
|
|
|
DDR_A_BS#1 |
|
R23 |
MA_BANK0 |
MB_BANK0 |
U26 |
|
DDR_B_BS#1 |
|
|
|
DDR_B_BS#0 8 |
< To SO_DIMMB > |
|
8 DDR_B_DQS5 |
|
|
|
|
DDR_B_DQS#5 |
AF22 |
MB_DQS_H5 |
|
|
|
MA_DQS_H5 |
AB20 |
DDR_A_DQS#5 |
|
|
|
DDR_A_DQS5 9 |
|
|
||||||||||||||||||||||||
|
|
|
9 DDR_A_BS#1 |
|
|
|
|
|
|
|
DDR_A_BS#2 |
|
J21 |
MA_BANK1 |
MB_BANK1 |
J26 |
|
DDR_B_BS#2 |
|
|
|
DDR_B_BS#1 |
8 |
|
8 DDR_B_DQS#5 |
|
|
|
|
DDR_B_DQS6 |
AE16 |
MB_DQS_L5 |
|
|
|
MA_DQS_L5 |
Y15 |
DDR_A_DQS6 |
|
|
|
DDR_A_DQS#5 |
9 |
|
|||||||||||||||||||||||||
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|
9 DDR_A_BS#2 |
|
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|
MA_BANK2 |
MB_BANK2 |
|
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|
DDR_B_BS#2 |
8 |
|
|
|
8 DDR_B_DQS6 |
|
|
|
|
DDR_B_DQS#6 |
AD16 |
MB_DQS_H6 |
|
|
|
MA_DQS_H6 |
W15 |
DDR_A_DQS#6 |
|
|
|
DDR_A_DQS6 9 |
|
|
|||||||||||||||
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|
DDR_A_RAS# |
|
R19 |
|
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|
U25 |
|
DDR_B_RAS# |
|
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|
8 DDR_B_DQS#6 |
|
|
|
|
DDR_B_DQS7 |
AF12 |
MB_DQS_L6 |
|
|
|
MA_DQS_L6 |
W12 |
DDR_A_DQS7 |
|
|
|
DDR_A_DQS#6 9 |
|
||||||||||||
|
|
< To SO_DIMMA > |
|
9 DDR_A_RAS# |
|
|
|
|
|
|
|
DDR_A_CAS# |
|
T22 |
MA_RAS_L |
MB_RAS_L |
U24 |
|
DDR_B_CAS# |
|
|
|
DDR_B_RAS# 8 |
< To SO_DIMMB > |
|
8 DDR_B_DQS7 |
|
|
|
|
DDR_B_DQS#7 |
AE12 |
MB_DQS_H7 |
|
|
|
MA_DQS_H7 |
W13 |
DDR_A_DQS#7 |
|
|
|
DDR_A_DQS7 9 |
|
|
||||||||||||||||||||||||
|
|
|
9 DDR_A_CAS# |
|
|
|
|
|
|
|
DDR_A_WE# |
|
T24 |
MA_CAS_L |
MB_CAS_L |
U23 |
|
DDR_B_WE# |
|
|
|
DDR_B_CAS# 8 |
|
8 DDR_B_DQS#7 |
|
|
|
|
|
|
MB_DQS_L7 |
|
|
|
MA_DQS_L7 |
|
|
|
|
|
|
DDR_A_DQS#7 |
9 |
|
|||||||||||||||||||||||||
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|
|
9 DDR_A_WE# |
|
|
|
|
|
|
|
|
MA_WE_L |
MB_WE_L |
|
|
|
|
DDR_B_WE# |
8 |
|
|
|
< From/To SO_DIMMB > |
|
|
|
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|
< From/To SO_DIMMA > |
|
|||||||||||||||||||||||||||
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@ |
FOX_PZ63823-284S-41F_638P |
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@ |
FOX_PZ63823-284S-41F_638P |
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Security Classification |
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Compal Secret Data |
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Compal Electronics, Inc. |
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Issued Date |
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2008-09-25 |
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Deciphered Date |
2009-09-25 |
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Title |
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AMD CPU S1G2 DDRII I/F |
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THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL |
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AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D |
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Size |
Document Number |
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Rev |
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Custom |
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LA-4971P |
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1.0 |
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DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS |
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MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. |
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Date: |
Wednesday, April 22, 2009 |
Sheet |
5 |
of |
45 |
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A |
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B |
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C |
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D |
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E |
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A |
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+CPU_CORE_0 |
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< Close to CPU > |
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R487 |
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1 |
2 |
10_0402_5% |
CPU_VDD0_RUN_FB_H |
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R486 |
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1 |
2 |
10_0402_5% |
CPU_VDD0_RUN_FB_L |
+CPU_CORE_1 |
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Un-Mount R489 For Caspian |
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R489 |
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PUMA@ |
1 |
2 |
10_0402_5% |
CPU_VDD1_RUN_FB_H |
1 |
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R488 |
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PUMA@ |
1 |
2 |
10_0402_5% |
CPU_VDD1_RUN_FB_L |
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Change R488 to 10K For Caspian |
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< 200-MHz PLL Reference Clock >
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C20 |
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15 CLK_CPU_BCLK |
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1 |
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2 |
3900P_0402_50V7K |
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CPU_CLKIN_SC_P |
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1 |
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R8 |
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169_0402_1% |
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2 |
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C21 |
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15 CLK_CPU_BCLK# |
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1 |
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2 |
3900P_0402_50V7K |
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CPU_CLKIN_SC_N |
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Address:100_1100 Place close to CPU wihtin 1.5"
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< Filtered PLL Supply Voltage > |
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2 |
+2.5VS |
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+2.5VDDA |
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L1 |
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2 FBM_L11_201209_300L_0805 |
VDDA=300mA |
+2.5VDDA |
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1 |
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1 |
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1 |
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1 |
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C17 |
C18 |
C19 |
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@ |
+ C16 |
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4.7U_0805_10V4Z |
3300P_0402_50V7K |
0.22U_0603_16V4Z |
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100U_D2_6.3VM |
2 |
2 |
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2 |
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< Serial VID Interface clock & data > |
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+1.8VS |
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0718 AMD --> 1K ohm |
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R22 |
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2 |
1 |
1K_0402_5% |
CPU_SVC |
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R23 |
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2 |
1 |
1K_0402_5% |
CPU_SVD |
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+1.8VS |
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3 |
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2 |
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R15 |
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300_0402_5% |
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1 |
LDT_RST# |
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20 |
LDT_RST# |
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1 |
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C22 |
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@ |
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0.01U_0402_25V7K |
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2 |
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+1.8VS |
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+1.8VS |
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2 |
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2 |
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R21 |
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R36 |
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300_0402_5% |
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300_0402_5% |
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1 |
H_PWRGD |
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1 |
20,43 |
H_PWRGD |
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11,20 |
LDT_STOP# |
LDT_STOP# |
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1 |
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C23 |
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C25 |
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@ |
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0.1U_0402_16V7K |
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0.01U_0402_25V7K |
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2 |
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2 |
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+1.8VS |
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4 |
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2 |
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R30 |
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300_0402_5% |
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PUMA@ |
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1 |
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R27 |
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11,20 |
CPU_LDT_REQ# |
CPU_LDT_REQ# |
1 |
2 |
0_0402_5% |
CPU_LDT_REQ_R# |
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C24 |
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Un-Mount R27 For Caspian |
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0.01U_0402_25V7K |
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2 |
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A |
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B |
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C |
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E |
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JCPUD |
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< Differential feedback for VDDNB > |
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+2.5VDDA |
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Close to CPU |
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F8 |
VDDA1 |
KEY1 |
M11 |
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+VDDNB |
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F9 |
VDDA2 |
KEY2 |
W18 |
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R484 |
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CPU_CLKIN_SC_P |
A9 |
CLKIN_H |
SVC |
A6 |
CPU_SVC |
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CPU_SVC |
43 |
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2 |
1 |
10_0402_5% |
CPU_VDDNB_RUN_FB_H |
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CPU_CLKIN_SC_N |
A8 |
A4 |
CPU_SVD |
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< Serial VID Interface clock & data > |
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CLKIN_L |
SVD |
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CPU_SVD |
43 |
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R485 |
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LDT_RST# |
B7 |
RESET_L |
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2 |
1 |
10_0402_5% |
CPU_VDDNB_RUN_FB_L |
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H_PWRGD |
A7 |
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LDT_STOP# |
F10 |
PWROK |
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AF6 |
CPU_THERMTRIP#_R |
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< Thermal Sensor Trip output > |
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CPU_LDT_REQ_R# |
C6 |
LDTSTOP_L THERMTRIP_L |
AC7 |
CPU_PROCHOT#_1.8 |
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< HTC-active state indication or command > |
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LDTREQ_L |
PROCHOT_L |
AA8 |
2 |
1 R42 |
+1.8V |
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MEMHOT_L |
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< Sideband-Temperature Sensor Interface Clock & Data> |
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AF4 |
SIC |
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300_0402_5% |
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< Sideband-Temperature Sensor Interface interrupt > |
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AF5 |
SID |
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W7 |
THERMDC_CPU |
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1 |
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AE6 |
ALERT_L |
THERMDC |
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W8 |
THERMDA_CPU |
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< Thermal diode cathode & anode > |
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< Compensation Resistor to VSS > |
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R13 |
1 |
2 44.2_0402_1% |
CPU_HTREF0 |
R6 |
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THERMDA |
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HT_REF0 |
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< Compensation Resistor to VLDT > |
+1.2V_HT |
R14 |
1 |
2 44.2_0402_1% |
CPU_HTREF1 |
P6 |
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HT_REF1 |
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+1.8V sense no support |
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CPU_VDD0_RUN_FB_H |
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43 CPU_VDD0_RUN_FB_H |
F6 |
VDD0_FB_H |
VDDIO_FB_H |
W9 |
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PAD |
T22 |
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< Differential feedback for VDDIO > |
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43 CPU_VDD0_RUN_FB_L |
CPU_VDD0_RUN_FB_L |
E6 |
VDD0_FB_L |
VDDIO_FB_L |
Y9 |
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PAD |
T21 |
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< VDDIO : DDR SDRAM I/O ring power supply> |
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43 CPU_VDD1_RUN_FB_H |
CPU_VDD1_RUN_FB_H |
Y6 |
VDD1_FB_H |
VDDNB_FB_H |
H6 |
CPU_VDDNB_RUN_FB_H |
CPU_VDDNB_RUN_FB_H |
43 |
< Differential feedback for VDDNB > |
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43 CPU_VDD1_RUN_FB_L |
CPU_VDD1_RUN_FB_L |
AB6 |
VDD1_FB_L |
VDDNB_FB_L |
G6 |
CPU_VDDNB_RUN_FB_L |
CPU_VDDNB_RUN_FB_L |
43 |
< Northbridge power supply > |
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< Debug ready > |
T9 |
PAD |
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G10 |
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DBRDY |
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CPU_DBREQ# |
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AA9 |
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E10 |
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< Debug request > |
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T10 PAD |
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TMS |
DBREQ_L |
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||||||||||
< JTAG debug port > |
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AC9 |
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T11 PAD |
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TCK |
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AD9 |
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AE9 |
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T12 PAD |
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TRST_L |
TDO |
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PAD |
T20 |
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AF9 |
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T19 |
PAD |
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TDI |
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CPU_TEST23_TSTUPD |
AD7 |
TEST23 |
TEST28_H |
J7 |
CPU_TEST28_H_PLLCHRZ_P |
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PAD |
T5 |
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route as differential |
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H8 |
CPU_TEST28_L_PLLCHRZ_N |
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as short as possible |
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H10 |
TEST18 |
TEST28_L |
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PAD |
T6 |
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testpoint under package |
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G9 |
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D7 |
CPU_TEST17_BP3 |
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PAD |
T7 |
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TEST19 |
TEST17 |
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E7 |
CPU_TEST16_BP2 |
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CPU_TEST25_H_BYPASSCLK_H |
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TEST16 |
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PAD |
T8 |
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E9 |
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F7 |
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CPU_TEST25_L_BYPASSCLK_L |
E8 |
TEST25_H |
TEST15 |
C7 |
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CPU_TEST21_SCANEN |
AB8 |
TEST25_L |
TEST14 |
C3 |
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@R32 |
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TEST21 |
TEST7 |
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CPU_TEST20_SCANCLK2 |
AF7 |
K8 |
CPU_TEST10_ANALOGOUT 2 |
1 |
300_0402_5% +1.2V_HT |
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TEST20 |
TEST10 |
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CPU_TEST24_SCANCLK1 |
AE7 |
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AE8 |
TEST24 |
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C4 |
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Add R32 at PVT |
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TEST22 |
TEST8 |
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AC8 |
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TEST12 |
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AF8 |
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TEST27 |
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TEST29_H |
C9 |
CPU_TEST29_H_FBCLKOUT_P |
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PAD |
T13 |
2 |
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1 |
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2 R25 |
C2 |
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C8 |
CPU_TEST29_L_FBCLKOUT_N |
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0_0402_5% |
AA6 |
TEST9 |
TEST29_L |
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PAD |
T14 |
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TEST6 |
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A3 |
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H18 |
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RSVD1 |
RSVD10 |
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A5 |
H19 |
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RSVD2 |
RSVD9 |
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B3 |
AA7 |
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RSVD3 |
RSVD8 |
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B5 |
D5 |
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RSVD4 |
RSVD7 |
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C1 |
C5 |
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RSVD5 |
RSVD6 |
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||||
@FOX_PZ63823-284S-41F_638P
Add R497 and R498 at PVT |
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+1.8V |
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R497 |
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R498 |
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TIGRIS@ |
1 |
2 |
510_0402_5% |
CPU_TEST25_H_BYPASSCLK_H |
@ |
1 |
2 510_0402_5% |
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R499 |
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R500 |
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@ |
1 |
2 |
510_0402_5% |
CPU_TEST25_L_BYPASSCLK_TIGRIS@L |
1 |
2 510_0402_5% |
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||||||
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@D12 |
|
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< To power circuitry> |
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R10 |
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1 |
2 |
CH751H-40PT_SOD323-2 |
ENTRIP2 |
38,40 |
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3 |
||
+1.8V |
1 |
2 |
10K_0402_5% |
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< HDT Connector > |
|
|||||
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@D20 |
|
|
< To power circuitry> |
|
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|||
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1 |
2 |
R5 |
|
2 |
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1 |
2 |
CH751H-40PT_SOD323-2 |
EN0 |
37,40 |
|
|
< R41 Close to CPU > |
< R494 Close to CPU > |
|
|
JP3 |
|
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|||||||||
|
300_0402_5% |
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||||
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B |
Q3 |
|
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CPU_DBREQ# |
|
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1 |
2 |
|
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||
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D16 |
|
|
< To SB700 ACPI block> |
|
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|
R494 |
|
3 |
4 |
|
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E |
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5 |
6 |
|
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|||||
|
CPU_THERMTRIP#_R |
|
1 |
1 |
2 |
CH751H-40PT_SOD323-2 |
|
|
|
|
|
R41 |
1 |
2 300_0402_5% |
@ 1 |
2 |
0_0402_5% |
|
|
|
|||||||||||
|
|
3 |
H_THERMTRIP# |
21 |
+1.8V |
|
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|||||||||||||||||||||
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C |
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7 |
8 |
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|||||
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|
MMBT3904_NL_SOT23-3 |
|
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|
|
T23 PAD |
@ |
R40 |
1 |
2 |
220_0402_5% |
|
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|
9 |
10 |
|
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||||||
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11 |
12 |
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|||||||||||
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@ |
R39 |
1 |
2 |
220_0402_5% |
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13 |
14 |
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|||||||
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@ |
R38 |
1 |
2 |
220_0402_5% |
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||||
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15 |
16 |
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|||||||
|
|
R9 |
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|
+1.8V |
@ |
R37 |
1 |
2 |
220_0402_5% |
|
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||||||
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17 |
18 |
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|||||||||||
+1.8V |
1 |
2 300_0402_5% |
|
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||||||
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T24 |
PAD |
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|
19 |
20 |
|
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|
|||||
|
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|
|
|
< To SB700 CPU block> |
|
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|||||||
|
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@ |
R11 |
|
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|
|
+1.8V |
|
21 |
22 |
|
LDT_RST# |
||
|
CPU_PROCHOT#_1.8 |
|
1 |
|
2 |
0_0402_5% |
|
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23 |
24 |
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||||
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|
|
H_PROCHOT# 20 |
|
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26 |
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|
|
@ SAMTEC_ASP-68200-07 |
|
|||
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|
|
NOTE: HDT TERMINATION IS REQUIRED FOR REV. Ax SILICON ONLY. |
|||||||||
Add R29 and R31 at PVT |
|
|
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|
|
+3VS |
|
|
|
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|
|
< Thermal Sensor > |
|
|
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|
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||||||||
|
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|
U2 |
|
|
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|
|
< From EC > |
|
|||||||
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|
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TIGRIS@ |
|
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|
|
1 |
VDD |
SCLK |
8 |
EC_SMB_CK2 |
|
EC_SMB_CK2 |
19,34,35 |
||
|
|
R31 |
|
CPU_TEST20_SCANCLK2 |
|
|
|
|
|
|
|
1 |
|
|
|
THERMDA_CPU |
|
|
|
|
EC_SMB_DA2 |
|
|
|
|
||||||
2 |
1 |
300_0402_5% |
|
|
|
|
|
|
C26 |
|
|
|
|
2 |
D+ |
SDATA |
7 |
|
EC_SMB_DA2 19,34,35 |
||||||||||||
|
|
TIGRIS@ |
|
|
|
|
|
|
|
|
|
|
|
0.1U_0402_16V7K |
|
1 |
2 |
C27 |
THERMDC_CPU |
3 |
D- |
ALERT# |
6 |
|
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|
4 |
||
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2 |
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||||||||||||
|
|
R29 |
|
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|
|
2200P_0402_50V7K |
|
|
|
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|
|
||
1 |
2 |
300_0402_5% |
CPU_TEST23_TSTUPD |
|
|
|
|
|
|
|
|
< noise filter cap |
> |
|
|
4 |
THERM# |
GND |
5 |
|
|
|
|
|
|
||||||
|
|
R26 |
|
|
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|
|
|
|
|
ADM1032ARM-1 ZREEL_MSOP8 |
|
|
|
|
|
||||
2 |
1 |
300_0402_5% |
CPU_TEST21_SCANEN |
|
|
|
|
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|
|
|
Compal Electronics, Inc. |
|
||||||||||
|
|
|
|
|
|
|
|
Security Classification |
|
|
|
Compal Secret Data |
|
|
|
|
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|||||||||
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||||
|
|
R28 |
|
|
|
|
|
|
Issued Date |
|
2008-09-25 |
Deciphered Date |
|
2009-09-25 |
|
|
|
Title |
|
|
|
|
|
|
|
|
|
||||
1 |
2 |
300_0402_5% |
CPU_TEST24_SCANCLK1 |
|
|
|
|
|
|
|
|
|
|
|
|
|
AMD CPU S1G2 CTRL |
|
|
||||||||||||
|
|
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|
||||||||||||||
|
|
|
|
|
|
|
|
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL |
|
|
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|
|
||||||||||||||||
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AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D |
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Custom |
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LA-4971P |
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1.0 |
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DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS |
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MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. |
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Date: |
Wednesday, April 22, 2009 |
Sheet |
6 |
of |
45 |
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B |
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C |
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D |
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E |
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A |
B |
C |
D |
E |
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+CPU_CORE_0 JCPUE |
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+CPU_CORE_1 |
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VDD decoupling : +CPU_CORE |
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G4 |
VDD0_1 |
VDD1_1 |
P8 |
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+CPU_CORE_0 |
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H2 |
VDD0_2 |
VDD1_2 |
P10 |
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+CPU_CORE_0 |
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+CPU_CORE_0 |
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J9 |
R4 |
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J11 |
VDD0_3 |
VDD1_3 |
R7 |
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VDD0_4 |
VDD1_4 |
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J13 |
VDD0_5 |
VDD1_5 |
R9 |
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1 |
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1 |
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1 |
1 |
C33 |
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1 |
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1 |
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1 |
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1 |
C42 |
J15 |
VDD0_6 |
VDD1_6 |
R11 |
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+ |
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C32 |
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C34 |
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C35 |
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C40 |
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C41 |
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K6 |
VDD0_7 |
VDD1_7 |
T2 |
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C30 |
C28 |
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K10 |
T6 |
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22U_0805_6.3V6M |
22U_0805_6.3V6M |
22U_0805_6.3V6M |
22U_0805_6.3V6M |
0.22U_0603_16V4Z |
0.01U_0402_25V7K |
180P_0402_50V8J |
K12 |
VDD0_8 |
VDD1_8 |
T8 |
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2 |
330U_X_2VM_R6M |
2 |
330U_X_2VM_R6M |
2 |
2 |
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2 |
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2 |
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2 |
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2 |
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2 |
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K14 |
VDD0_9 |
VDD1_9 |
T10 |
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L4 |
VDD0_10 |
VDD1_10 |
T12 |
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Near CPU Socket |
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Under CPU Socket |
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Under CPU Socket |
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VDD0_11 |
VDD1_11 |
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L7 |
VDD0_12 |
VDD1_12 |
T14 |
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1 |
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L9 |
VDD0_13 |
VDD1_13 |
U7 |
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L11 |
U9 |
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L13 |
VDD0_14 |
VDD1_14 |
U11 |
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+CPU_CORE_1 |
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+CPU_CORE_1 |
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+CPU_CORE_1 |
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VDD0_15 |
VDD1_15 |
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L15 |
U13 |
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M2 |
VDD0_16 |
VDD1_16 |
U15 |
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VDD0_17 |
VDD1_17 |
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M6 |
VDD0_18 |
VDD1_18 |
V6 |
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1 |
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1 |
1 |
C37 |
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1 |
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C45 |
M8 |
VDD0_19 |
VDD1_19 |
V8 |
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+ |
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C36 |
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C38 |
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C39 |
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C43 |
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C44 |
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M10 |
VDD0_20 |
VDD1_20 |
V10 |
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C31 |
C29 |
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N7 |
V12 |
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22U_0805_6.3V6M |
22U_0805_6.3V6M |
22U_0805_6.3V6M |
22U_0805_6.3V6M |
0.22U_0603_16V4Z |
0.01U_0402_25V7K |
180P_0402_50V8J |
N9 |
VDD0_21 |
VDD1_21 |
V14 |
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2 |
330U_X_2VM_R6M |
2 |
330U_X_2VM_R6M |
2 |
2 |
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2 |
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+VDDNB |
N11 |
VDD0_22 |
VDD1_22 |
W4 |
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VDD0_23 |
VDD1_23 |
Y2 |
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VDD1_24 |
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Near CPU Socket |
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Under CPU Socket |
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Under CPU Socket |
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K16 |
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AC4 |
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VDDNB_1 |
VDD1_25 |
+1.8V |
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M16 |
AD2 |
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P16 |
VDDNB_2 |
VDD1_26 |
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VDDNB_3 |
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Y25 |
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T16 |
VDDNB_4 |
VDDIO27 |
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+1.8V |
V16 |
V25 |
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VDDIO decoupling : DDR SDRAM I/O ring power |
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VDDNB_5 |
VDDIO26 |
V23 |
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H25 |
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VDDIO25 |
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VDDIO1 |
VDDIO24 |
V21 |
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+1.8V |
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J17 |
V18 |
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K18 |
VDDIO2 |
VDDIO23 |
U17 |
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VDDIO3 |
VDDIO22 |
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K21 |
VDDIO4 |
VDDIO21 |
T25 |
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C46 |
1 |
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C50 |
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K23 |
VDDIO5 |
VDDIO20 |
T23 |
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C47 |
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C48 |
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C49 |
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C51 |
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K25 |
VDDIO6 |
VDDIO19 |
T21 |
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L17 |
T18 |
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VDDIO7 |
VDDIO18 |
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22U_0805_6.3V6M |
22U_0805_6.3V6M |
0.22U_0603_16V4Z |
0.22U_0603_16V4Z |
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180P_0402_50V8J |
180P_0402_50V8J |
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M18 |
R17 |
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2 |
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M21 |
VDDIO8 |
VDDIO17 |
P25 |
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Under CPU Socket |
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M23 |
VDDIO9 |
VDDIO16 |
P23 |
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VDDIO10 |
VDDIO15 |
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M25 |
VDDIO11 |
VDDIO14 |
P21 |
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+1.8V |
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N17 |
VDDIO12 |
VDDIO13 |
P18 |
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@ |
FOX_PZ63823-284SAthlon-41F 638P64 S1 Processor Socket |
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C55 |
C56 |
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C57 |
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C58 |
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JCPUF |
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2 |
0.22U_0603_16V4Z |
0.22U_0603_16V4Z |
0.22U_0603_16V4Z |
0.22U_0603_16V4Z |
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AA4 |
VSS1 |
VSS66 |
J6 |
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2 |
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AA11 |
J8 |
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VSS2 |
VSS67 |
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Between CPU Socket and DIMM |
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AA13 |
J10 |
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VSS3 |
VSS68 |
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AA15 |
VSS4 |
VSS69 |
J12 |
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AA17 |
J14 |
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VSS5 |
VSS70 |
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+1.8V |
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AA19 |
J16 |
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VSS6 |
VSS71 |
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AB2 |
J18 |
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VSS7 |
VSS72 |
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AB7 |
K2 |
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VSS8 |
VSS73 |
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1 |
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1 |
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AB9 |
K7 |
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VSS9 |
VSS74 |
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C60 |
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C61 |
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AB23 |
K9 |
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VSS10 |
VSS75 |
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AB25 |
K11 |
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VSS11 |
VSS76 |
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2 |
0.01U_0402_25V7K |
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0.01U_0402_25V7K |
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AC11 |
K13 |
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2 |
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AC13 |
VSS12 |
VSS77 |
K15 |
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Between CPU Socket and DIMM |
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VSS13 |
VSS78 |
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AC15 |
VSS14 |
VSS79 |
K17 |
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AC17 |
VSS15 |
VSS80 |
L6 |
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AC19 |
VSS16 |
VSS81 |
L8 |
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AC21 |
VSS17 |
VSS82 |
L10 |
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+1.8V |
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AD6 |
L12 |
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180PF Qt'y follow the distance between CPU socket and DIMM0. <2.5inch> |
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AD8 |
VSS18 |
VSS83 |
L14 |
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AD25 |
VSS19 |
VSS84 |
L16 |
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VSS20 |
VSS85 |
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1 |
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1 |
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1 |
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1 |
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AE11 |
VSS21 |
VSS86 |
L18 |
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C62 |
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AE13 |
M7 |
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C63 |
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C64 |
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C65 |
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VSS22 |
VSS87 |
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AE15 |
M9 |
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VSS23 |
VSS88 |
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180P_0402_50V8J |
180P_0402_50V8J |
180P_0402_50V8J |
180P_0402_50V8J |
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AE17 |
AC6 |
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2 |
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VSS24 |
VSS89 |
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2 |
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2 |
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2 |
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AE19 |
M17 |
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Between CPU Socket and DIMM |
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AE21 |
VSS25 |
VSS90 |
N4 |
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VSS26 |
VSS91 |
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AE23 |
N8 |
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VSS27 |
VSS92 |
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B4 |
N10 |
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+1.8V |
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Change to B2 size |
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B6 |
VSS28 |
VSS93 |
N16 |
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3 |
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B8 |
VSS29 |
VSS94 |
N18 |
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1 |
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B9 |
VSS30 |
VSS95 |
P2 |
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VSS31 |
VSS96 |
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1 |
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1 |
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1 |
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1 |
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+ |
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B11 |
VSS32 |
VSS97 |
P7 |
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C74 |
C75 |
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C76 |
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C77 |
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@ |
C78 |
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B13 |
P9 |
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220U_B2_4VM_R45M |
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B15 |
VSS33 |
VSS98 |
P11 |
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4.7U_0805_10V4Z |
4.7U_0805_10V4Z |
4.7U_0805_10V4Z |
4.7U_0805_10V4Z |
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VSS34 |
VSS99 |
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B17 |
P17 |
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2 |
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2 |
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2 |
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2 |
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2 |
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B19 |
VSS35 |
VSS100 |
R8 |
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Between CPU Socket and DIMM |
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B21 |
VSS36 |
VSS101 |
R10 |
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VSS37 |
VSS102 |
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B23 |
VSS38 |
VSS103 |
R16 |
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B25 |
VSS39 |
VSS104 |
R18 |
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D6 |
VSS40 |
VSS105 |
T7 |
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+0.9V |
VTT decoupling. |
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D8 |
VSS41 |
VSS106 |
T9 |
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D9 |
VSS42 |
VSS107 |
T11 |
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D11 |
VSS43 |
VSS108 |
T13 |
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D13 |
T15 |
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VSS44 |
VSS109 |
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1 |
1 |
C67 |
1 |
C68 |
1 |
C69 |
1 |
C70 |
1 |
C71 |
1 |
C72 |
1 |
C73 |
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D15 |
VSS45 |
VSS110 |
T17 |
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C66 |
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D17 |
VSS46 |
VSS111 |
U4 |
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D19 |
U6 |
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VSS47 |
VSS112 |
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|
4.7U_0805_10V4Z |
4.7U_0805_10V4Z |
0.22U_0603_16V4Z |
0.22U_0603_16V4Z |
1000P_0402_25V8J |
1000P_0402_25V8J |
180P_0402_50V8J |
180P_0402_50V8J |
+0.9V |
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D21 |
U8 |
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2 |
2 |
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2 |
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2 |
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2 |
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2 |
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2 |
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2 |
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1. Near Power Supply |
D23 |
VSS48 |
VSS113 |
U10 |
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Near CPU Socket Right side |
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1 2. Change to B2 size |
D25 |
VSS49 |
VSS114 |
U12 |
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VSS50 |
VSS115 |
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+0.9V |
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+ |
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E4 |
VSS51 |
VSS116 |
U14 |
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C59 |
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F2 |
U16 |
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220U_B2_4VM_R45M |
F11 |
VSS52 |
VSS117 |
U18 |
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VSS53 |
VSS118 |
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1 |
1 |
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1 |
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1 |
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1 |
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1 |
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1 |
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1 |
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2 |
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F13 |
VSS54 |
VSS119 |
V2 |
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C79 |
C80 |
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C81 |
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C82 |
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C83 |
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C84 |
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C85 |
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C86 |
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F15 |
V7 |
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|
4.7U_0805_10V4Z |
4.7U_0805_10V4Z |
0.22U_0603_16V4Z |
0.22U_0603_16V4Z |
1000P_0402_25V8J |
1000P_0402_25V8J |
180P_0402_50V8J |
180P_0402_50V8J |
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F17 |
VSS55 |
VSS120 |
V9 |
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F19 |
VSS56 |
VSS121 |
V11 |
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2 |
2 |
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2 |
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2 |
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2 |
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2 |
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2 |
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2 |
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VSS57 |
VSS122 |
|
||
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Near CPU Socket Left side |
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F21 |
VSS58 |
VSS123 |
V13 |
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F23 |
VSS59 |
VSS124 |
V15 |
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F25 |
VSS60 |
VSS125 |
V17 |
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4 |
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H7 |
VSS61 |
VSS126 |
W6 |
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H9 |
Y21 |
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H21 |
VSS62 |
VSS127 |
Y23 |
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+VDDNB decoupling : Northbridge power |
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VSS63 |
VSS128 |
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H23 |
VSS64 |
VSS129 |
N6 |
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+VDDNB |
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J4 |
VSS65 |
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@ FOX_PZ63823-284SAthlon-41F 638P64 S1 Processor Socket |
||||
|
1 |
|
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1 |
|
|
1 TIGRIS@ |
|
Security Classification |
|
Compal Secret Data |
|
|
|
Compal Electronics, Inc. |
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|
|||||||||
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C52 |
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C53 |
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C54 |
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|||
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22U_0805_6.3V6M |
|
|
22U_0805_6.3V6M |
|
|
22U_0805_6.3V6M |
|
Issued Date |
2008-09-25 |
|
Deciphered Date |
2009-09-25 |
Title |
AMD CPU S1G2 PWR & GND |
|
|
||||||
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|||||||||||||
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2 |
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2 |
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2 |
|
|
|
|
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL |
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||||
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|
|
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D |
Size |
Document Number |
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Rev |
|||||
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|
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS |
Custom |
LA-4971P |
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|
1.0 |
|||||
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||||||
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|
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. |
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||||
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|
Date: |
Wednesday, April 22, 2009 |
Sheet |
7 |
of |
45 |
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A |
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B |
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C |
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D |
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E |
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1
2
3
4
|
A |
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B |
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C |
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D |
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E |
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+1.8V |
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|
|
+1.8V |
|
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|
< EMI require > |
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|
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< EMI require > |
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||||
|
0.1U_0402_16V7K |
1 |
2 C160 |
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|
C155 2 |
1 |
0.1U_0402_16V7K |
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+1.8V |
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|||
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+0.9V |
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||
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JDDRH |
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RP8 |
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9 |
+V_DDR_MCH_REF |
|
|
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1 |
VREF |
VSS |
2 |
DDR_B_D4 |
|
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|
|
DDR_B_MA4 |
1 |
8 |
C105 |
2 |
1 |
0.1U_0402_16V7K |
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1 |
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3 |
VSS |
DQ4 |
4 |
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DDR_B_MA2 |
2 |
7 |
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DDR_B_D0 |
|
5 |
DQ0 |
DQ5 |
6 |
DDR_B_D5 |
|
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|
|
DDR_B_MA0 |
3 |
6 |
C106 |
2 |
1 0.1U_0402_16V7K |
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||
1 |
C104 |
DDR_B_D1 |
|
7 |
8 |
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DDR_B_RAS# |
4 |
5 |
|
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1 |
|||
|
1000P_0402_25V8J |
|
|
|
9 |
DQ1 |
VSS |
10 |
DDR_B_DM0 |
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2 |
DDR_B_DQS#0 |
11 |
VSS |
DM0 |
12 |
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|
47_0804_8P4R_5% |
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|||
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|
DDR_B_DQS0 |
13 |
DQS0# |
VSS |
14 |
DDR_B_D6 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||
|
|
|
|
|
15 |
DQS0 |
DQ6 |
16 |
DDR_B_D7 |
|
|
|
|
|
|
|
RP9 |
|
|
|
|
|
|
|
|
|
DDR_B_D2 |
|
17 |
VSS |
DQ7 |
18 |
|
|
|
|
|
|
DDR_B_MA14 |
1 |
8 |
C108 |
2 |
1 |
0.1U_0402_16V7K |
|
|
|
|
|
|
DDR_B_D3 |
|
19 |
DQ2 |
VSS |
20 |
DDR_B_D12 |
|
|
|
|
|
DDR_B_MA11 |
2 |
7 |
|
|
|
|
|
|
|
|
|
|
|
|
|
21 |
DQ3 |
DQ12 |
22 |
DDR_B_D13 |
|
|
|
|
|
DDR_B_MA7 |
3 |
6 |
C107 |
2 |
1 |
0.1U_0402_16V7K |
|
|
|
|
|
DDR_B_D8 |
|
23 |
VSS |
DQ13 |
24 |
|
|
|
|
|
|
DDR_B_MA6 |
4 |
5 |
|
|
|
|
|
|
|
|
|
|
DDR_B_D9 |
|
25 |
DQ8 |
VSS |
26 |
DDR_B_DM1 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
27 |
DQ9 |
DM1 |
28 |
|
|
|
|
|
|
|
47_0804_8P4R_5% |
|
|
|
|
|
|
|
|
|
|
DDR_B_DQS#1 |
29 |
VSS |
VSS |
30 |
|
|
|
DDR_B_CLK0 5 |
|
|
|
|
|
|
|
|
|
|
|
|||
|
|
DDR_B_DQS1 |
31 |
DQS1# |
CK0 |
32 |
|
|
|
|
|
|
RP10 |
|
|
|
|
|
|
|
||||
|
|
|
|
|
33 |
DQS1 |
CK0# |
34 |
|
|
|
DDR_B_CLK#0 |
5 |
|
DDR_CKE0_DIMMB 8 |
1 |
C109 |
2 |
1 |
0.1U_0402_16V7K |
|
|
|
|
|
|
DDR_B_D10 |
|
35 |
VSS |
VSS |
36 |
DDR_B_D14 |
|
|
|
|
|
DDR_B_BS#2 |
7 |
2 |
|
|
|
|
|
|
|
|
|
|
DDR_B_D11 |
|
37 |
DQ10 |
DQ14 |
38 |
DDR_B_D15 |
|
|
|
|
|
DDR_B_MA15 |
6 |
3 |
C110 |
2 |
1 |
0.1U_0402_16V7K |
|
|
|
|
|
|
|
|
|
39 |
DQ11 |
DQ15 |
40 |
|
|
|
|
|
|
DDR_CKE1_DIMMB 5 |
4 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
VSS |
VSS |
|
|
|
|
|
|
|
|
|
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|
|
|
|
|
|
|
|
|
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|
|
|
|
|
47_0804_8P4R_5% |
|
|
|
|
|
|
|
|
|
|
DDR_B_D16 |
|
41 |
VSS |
VSS |
42 |
DDR_B_D20 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
43 |
44 |
|
|
|
|
|
|
|
RP11 |
|
|
|
|
|
|
|
|||||
|
|
DDR_B_D17 |
|
45 |
DQ16 |
DQ20 |
46 |
DDR_B_D21 |
|
|
|
|
|
DDR_B_MA3 |
8 |
1 |
C111 |
2 |
1 |
0.1U_0402_16V7K |
|
|
|
|
|
|
|
|
|
47 |
DQ17 |
DQ21 |
48 |
|
|
|
|
|
|
DDR_B_MA8 |
7 |
2 |
|
|
|
|
|
|
|
|
|
DDR_B_DQS#2 |
49 |
VSS |
VSS |
50 |
|
|
|
|
|
|
DDR_B_MA12 |
6 |
3 |
C112 |
2 |
1 |
0.1U_0402_16V7K |
|
|
|
||
|
|
DDR_B_DQS2 |
51 |
DQS2# |
NC |
52 |
DDR_B_DM2 |
|
|
|
|
|
DDR_B_MA9 |
5 |
4 |
|
|
|
|
|
|
|
||
|
|
|
|
|
53 |
DQS2 |
DM2 |
54 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
VSS |
VSS |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||
|
|
DDR_B_D18 |
|
55 |
56 |
DDR_B_D22 |
|
|
|
|
|
|
47_0804_8P4R_5% |
|
|
|
|
|
|
|
||||
|
|
DDR_B_D19 |
|
57 |
DQ18 |
DQ22 |
58 |
DDR_B_D23 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
59 |
DQ19 |
DQ23 |
60 |
|
|
|
|
|
|
|
|
RP12 |
|
|
|
|
|
|
|
|
|
DDR_B_D24 |
|
61 |
VSS |
VSS |
62 |
DDR_B_D28 |
|
|
|
|
|
DDR_B_BS#0 |
8 |
1 |
C114 |
2 |
1 |
0.1U_0402_16V7K |
|
|
|
|
|
|
DDR_B_D25 |
|
63 |
DQ24 |
DQ28 |
64 |
DDR_B_D29 |
|
|
|
|
|
DDR_B_MA10 |
7 |
2 |
|
|
|
|
|
|
|
|
|
|
|
|
|
65 |
DQ25 |
DQ29 |
66 |
|
|
|
|
|
|
DDR_B_MA1 |
6 |
3 |
C113 |
2 |
1 0.1U_0402_16V7K |
|
|
|
|
2 |
|
DDR_B_DM3 |
|
67 |
VSS |
VSS |
68 |
DDR_B_DQS#3 |
|
|
|
|
DDR_B_MA5 |
5 |
4 |
|
|
|
|
|
|
2 |
||
|
|
|
|
|
69 |
DM3 |
DQS3# |
70 |
DDR_B_DQS3 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
71 |
NC |
DQS3 |
72 |
|
|
|
|
|
|
|
47_0804_8P4R_5% |
|
|
|
|
|
|
|
|
|
|
DDR_B_D26 |
|
73 |
VSS |
VSS |
74 |
DDR_B_D30 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
DDR_B_D27 |
|
75 |
DQ26 |
DQ30 |
76 |
DDR_B_D31 |
|
|
|
|
|
|
|
RP13 |
|
|
|
|
|
|
|
|
|
|
|
|
|
77 |
DQ27 |
DQ31 |
78 |
|
|
|
|
|
|
DDR_CS1_DIMMB# 8 |
1 |
C116 |
2 |
1 |
0.1U_0402_16V7K |
|
|
|
|
|
5 DDR_CKE0_DIMMB |
DDR_CKE0_DIMMB |
79 |
VSS |
VSS |
80 |
DDR_CKE1_DIMMB |
DDR_CKE1_DIMMB 5 |
DDR_B_ODT1 |
7 |
2 |
|
|
|
|
|
|
|
||||||
|
|
|
|
81 |
CKE0 |
NC/CKE1 |
82 |
|
|
|
DDR_B_CAS# |
6 |
3 |
C115 |
2 |
1 |
0.1U_0402_16V7K |
|
|
|
||||
|
|
|
|
|
83 |
VDD |
VDD |
84 |
DDR_B_MA15 |
|
|
|
|
DDR_B_WE# |
5 |
4 |
|
|
|
|
|
|
|
|
|
|
DDR_B_BS#2 |
85 |
NC |
NC/A15 |
86 |
DDR_B_MA14 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||
|
5 DDR_B_BS#2 |
BA2 |
NC/A14 |
|
|
|
|
|
47_0804_8P4R_5% |
|
|
|
|
|
|
|
||||||||
|
|
DDR_B_MA12 |
87 |
VDD |
VDD |
88 |
DDR_B_MA11 |
|
|
|
|
|
|
|
|
|
|
|
|
|||||
|
|
89 |
90 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||||||
|
|
DDR_B_MA9 |
|
91 |
A12 |
A11 |
92 |
DDR_B_MA7 |
|
|
|
|
|
|
|
RP14 |
|
|
|
|
|
|
|
|
|
|
DDR_B_MA8 |
|
93 |
A9 |
A7 |
94 |
DDR_B_MA6 |
|
|
|
|
|
DDR_B_BS#1 |
1 |
8 |
C118 |
2 |
1 |
0.1U_0402_16V7K |
|
|
|
|
|
|
|
|
|
95 |
A8 |
A6 |
96 |
|
|
|
|
|
|
DDR_CS0_DIMMB# 2 |
7 |
|
|
|
|
|
|
|
|
|
|
DDR_B_MA5 |
|
97 |
VDD |
VDD |
98 |
DDR_B_MA4 |
|
|
|
|
|
DDR_B_MA13 |
3 |
6 |
C117 |
2 |
1 |
0.1U_0402_16V7K |
|
|
|
|
|
|
DDR_B_MA3 |
|
99 |
A5 |
A4 |
100 |
DDR_B_MA2 |
|
|
|
|
|
DDR_B_ODT0 |
4 |
5 |
|
|
|
|
|
|
|
|
|
|
DDR_B_MA1 |
|
101 |
A3 |
A2 |
102 |
DDR_B_MA0 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
103 |
A1 |
A0 |
104 |
|
|
|
|
|
|
|
47_0804_8P4R_5% |
|
|
|
|
|
|
|
|
|
|
DDR_B_MA10 |
105 |
VDD |
VDD |
106 |
DDR_B_BS#1 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||
|
|
A10/AP |
BA1 |
|
DDR_B_BS#1 |
5 |
|
|
|
|
|
|
|
|
|
|
|
|||||||
|
5 DDR_B_BS#0 |
DDR_B_BS#0 |
107 |
BA0 |
RAS# |
108 |
DDR_B_RAS# |
|
DDR_B_RAS# |
5 |
|
|
|
|
|
|
|
|
|
|
|
|||
|
5 DDR_B_WE# |
DDR_B_WE# |
|
109 |
WE# |
S0# |
110 |
DDR_CS0_DIMMB# |
DDR_CS0_DIMMB# |
5 |
|
|
|
|
|
|
|
|
|
|
||||
|
|
DDR_B_CAS# |
111 |
VDD |
VDD |
112 |
DDR_B_ODT0 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||
|
5 DDR_B_CAS# |
113 |
CAS# |
ODT0 |
114 |
|
DDR_B_ODT0 |
5 |
|
|
|
|
|
|
|
|
|
|
|
|||||
|
5 DDR_CS1_DIMMB# |
DDR_CS1_DIMMB# |
115 |
NC/S1# |
NC/A13 |
116 |
DDR_B_MA13 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||
|
|
DDR_B_ODT1 |
117 |
VDD |
VDD |
118 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||
|
5 DDR_B_ODT1 |
119 |
NC/ODT1 |
NC |
120 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||
|
|
DDR_B_D32 |
|
121 |
VSS |
VSS |
122 |
DDR_B_D36 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
123 |
124 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||||
|
|
DDR_B_D33 |
|
125 |
DQ32 |
DQ36 |
126 |
DDR_B_D37 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
127 |
DQ33 |
DQ37 |
128 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
DDR_B_DQS#4 |
VSS |
VSS |
DDR_B_DM4 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||
|
|
129 |
130 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||||
3 |
|
DDR_B_DQS4 |
131 |
DQS4# |
DM4 |
132 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
3 |
||
|
|
|
|
|
133 |
DQS4 |
VSS |
134 |
DDR_B_D38 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
DDR_B_D34 |
|
135 |
VSS |
DQ38 |
136 |
DDR_B_D39 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
DDR_B_D35 |
|
137 |
DQ34 |
DQ39 |
138 |
|
|
|
|
|
|
|
|
|
DDR_B_D[0..63] |
|
|
|
||||
|
|
|
|
|
139 |
DQ35 |
VSS |
140 |
DDR_B_D44 |
|
|
|
|
|
|
|
|
|
|
|
|
DDR_B_D[0..63] |
5 |
|
|
|
DDR_B_D40 |
|
141 |
VSS |
DQ44 |
142 |
DDR_B_D45 |
|
|
|
|
|
|
|
|
DDR_B_DM[0..7] |
DDR_B_DM[0..7] |
5 |
|
||||
|
|
|
DQ40 |
DQ45 |
|
|
|
|
|
|
|
|
|
|||||||||||
|
|
DDR_B_D41 |
|
143 |
DQ41 |
VSS |
144 |
|
|
|
|
|
|
|
|
|
DDR_B_DQS[0..7] |
|
|
|
||||
|
|
|
|
|
145 |
146 |
DDR_B_DQS#5 |
|
|
|
|
|
|
|
DDR_B_DQS[0..7] |
|
5 |
|||||||
|
|
DDR_B_DM5 |
|
147 |
VSS |
DQS5# |
148 |
DDR_B_DQS5 |
|
|
|
|
|
|
|
|
|
|
|
|
||||
|
|
|
|
|
149 |
DM5 |
DQS5 |
150 |
|
|
|
|
|
|
|
|
|
DDR_B_MA[0..15] |
DDR_B_MA[0..15] |
5 |
||||
|
|
DDR_B_D42 |
|
VSS |
VSS |
DDR_B_D46 |
|
|
|
|
|
|
|
|
||||||||||
|
|
|
151 |
DQ42 |
DQ46 |
152 |
|
|
|
|
|
|
|
|
DDR_B_DQS#[0..7] |
|
|
|
||||||
|
|
DDR_B_D43 |
|
153 |
154 |
DDR_B_D47 |
|
|
|
|
|
|
|
|
DDR_B_DQS#[0..7] |
5 |
||||||||
|
|
|
|
|
155 |
DQ43 |
DQ47 |
156 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|||
|
|
DDR_B_D48 |
|
VSS |
VSS |
DDR_B_D52 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||
|
|
|
157 |
158 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||||
|
|
DDR_B_D49 |
|
159 |
DQ48 |
DQ52 |
160 |
DDR_B_D53 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
161 |
DQ49 |
DQ53 |
162 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
VSS |
VSS |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||
|
|
|
|
|
163 |
NC,TEST |
CK1 |
164 |
|
|
|
DDR_B_CLK1 |
5 |
|
|
|
|
|
|
|
|
|
|
|
|
|
DDR_B_DQS#6 |
165 |
VSS |
CK1# |
166 |
|
|
|
DDR_B_CLK#1 5 |
|
|
|
|
|
|
|
|
|
|
|
|||
|
|
167 |
168 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||||||
|
|
DDR_B_DQS6 |
169 |
DQS6# |
VSS |
170 |
DDR_B_DM6 |
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171 |
DQS6 |
DM6 |
172 |
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DDR_B_D50 |
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VSS |
VSS |
DDR_B_D54 |
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173 |
174 |
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DDR_B_D51 |
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175 |
DQ50 |
DQ54 |
176 |
DDR_B_D55 |
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177 |
DQ51 |
DQ55 |
178 |
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DDR_B_D56 |
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VSS |
VSS |
DDR_B_D60 |
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179 |
180 |
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DDR_B_D57 |
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181 |
DQ56 |
DQ60 |
182 |
DDR_B_D61 |
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183 |
DQ57 |
DQ61 |
184 |
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VSS |
VSS |
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DDR_B_DM7 |
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185 |
186 |
DDR_B_DQS#7 |
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187 |
DM7 |
DQS7# |
188 |
DDR_B_DQS7 |
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DDR_B_D58 |
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189 |
VSS |
DQS7 |
190 |
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DDR_B_D59 |
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191 |
DQ58 |
VSS |
192 |
DDR_B_D62 |
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4 |
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193 |
DQ59 |
DQ62 |
194 |
DDR_B_D63 |
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4 |
9,15,21,27 SMB_CK_DAT0 |
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195 |
VSS |
DQ63 |
196 |
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SDA |
VSS |
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9,15,21,27 SMB_CK_CLK0 |
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197 |
SCL |
SAO |
198 |
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+3VS |
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+3VS |
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199 |
VDDSPD |
SA1 |
200 |
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1 |
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201 |
VSS |
VSS |
202 |
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C119 |
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@FOX_AS0A426-N8RN-7F_200P |
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0.1U_0402_16V7K |
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2 |
|
DIMM0 STD H:9.2mm (Bot) |
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Security Classification |
Compal Secret Data |
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Compal Electronics, Inc. |
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|||||
Issued Date |
2008-09-25 |
Deciphered Date |
2009-09-25 |
Title |
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DDRII SO-DIMM 0 |
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THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL |
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AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D |
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Size |
Document Number |
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Rev |
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Custom |
LA-4971P |
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1.0 |
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DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS |
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MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. |
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Date: |
Wednesday, April 22, 2009 |
Sheet |
8 |
of |
45 |
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A |
B |
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C |
D |
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E |
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1
2
3
4
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A |
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B |
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C |
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D |
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+1.8V |
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2 |
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R43 |
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1K_0402_1% |
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1 |
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+V_DDR_MCH_REF |
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8 +V_DDR_MCH_REF |
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1 |
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1 |
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2 |
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C96 |
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R44 |
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C95 |
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DDR_A_D[0..63] |
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1K_0402_1% |
2 |
0.1U_0402_16V7K |
2 |
1000P_0402_25V8J |
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DDR_A_D[0..63] 5 |
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1 |
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< EMI require > |
+1.8V |
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+1.8V < EMI require > |
DDR_A_DM[0..7] |
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DDR_A_DM[0..7] 5 |
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0.1U_0402_16V7K 1 |
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2 C193 |
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JDDRL |
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C161 2 |
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1 0.1U_0402_16V7K |
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DDR_A_DQS[0..7] |
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DDR_A_DQS[0..7] 5 |
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1 |
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2 |
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DDR_A_MA[0..15] |
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DDR_A_MA[0..15] 5 |
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VREF |
VSS |
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DDR_A_D4 |
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3 |
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4 |
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VSS |
DQ4 |
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DDR_A_DQS#[0..7] |
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DDR_A_D0 |
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5 |
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6 |
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DDR_A_D5 |
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DQ0 |
DQ5 |
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DDR_A_DQS#[0..7] 5 |
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DDR_A_D1 |
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7 |
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8 |
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DQ1 |
VSS |
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DDR_A_DM0 |
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9 |
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10 |
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DDR_A_DQS#0 |
11 |
VSS |
DM0 |
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12 |
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DQS0# |
VSS |
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DDR_A_DQS0 |
13 |
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14 |
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DDR_A_D6 |
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DQS0 |
DQ6 |
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15 |
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16 |
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DDR_A_D7 |
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DDR_A_D2 |
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VSS |
DQ7 |
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17 |
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18 |
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DQ2 |
VSS |
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DDR_A_D3 |
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19 |
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20 |
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DDR_A_D12 |
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DQ3 |
DQ12 |
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21 |
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22 |
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DDR_A_D13 |
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DDR_A_D8 |
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VSS |
DQ13 |
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23 |
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24 |
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DQ8 |
VSS |
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DDR_A_D9 |
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25 |
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26 |
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DDR_A_DM1 |
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DQ9 |
DM1 |
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27 |
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28 |
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DDR_A_DQS#1 |
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VSS |
VSS |
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+0.9V |
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29 |
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30 |
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DDR_A_CLK0 5 |
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DQS1# |
CK0 |
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DDR_A_DQS1 |
31 |
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32 |
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RP1 |
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DDR_A_CLK#0 5 |
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DQS1 |
CK0# |
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DDR_A_MA6 |
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33 |
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34 |
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1 |
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8 |
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VSS |
VSS |
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DDR_A_D10 |
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35 |
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36 |
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DDR_A_D14 |
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DDR_A_MA14 |
2 |
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7 |
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DDR_A_D11 |
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37 |
DQ10 |
DQ14 |
|
38 |
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DDR_A_D15 |
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DDR_A_MA7 |
3 |
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6 |
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DQ11 |
DQ15 |
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39 |
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40 |
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DDR_A_MA11 |
4 |
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5 |
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||||||
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VSS |
VSS |
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47_0804_8P4R_5% |
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|
41 |
VSS |
VSS |
42 |
|
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RP2 |
|
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DDR_A_D16 |
43 |
44 |
DDR_A_D20 |
|
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DDR_CKE0_DIMMA |
8 |
1 |
||
|
DDR_A_D17 |
45 |
DQ16 |
DQ20 |
46 |
DDR_A_D21 |
|
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DDR_A_BS#2 |
7 |
2 |
|
|
47 |
DQ17 |
DQ21 |
48 |
|
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DDR_CKE1_DIMMA |
6 |
3 |
|
DDR_A_DQS#2 |
49 |
VSS |
VSS |
50 |
|
|
|
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DDR_A_MA15 |
5 |
4 |
|
DDR_A_DQS2 |
51 |
DQS2# |
NC |
52 |
DDR_A_DM2 |
|
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|
53 |
DQS2 |
DM2 |
54 |
|
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47_0804_8P4R_5% |
|
|
DDR_A_D18 |
55 |
VSS |
VSS |
56 |
DDR_A_D22 |
|
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|
|
RP3 |
|
|
DDR_A_D19 |
57 |
DQ18 |
DQ22 |
58 |
DDR_A_D23 |
|
|
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DDR_A_BS#1 |
1 |
8 |
|
|
59 |
DQ19 |
DQ23 |
60 |
|
|
|
|
DDR_A_MA2 |
2 |
7 |
|
DDR_A_D24 |
61 |
VSS |
VSS |
62 |
DDR_A_D28 |
|
|
|
DDR_A_MA0 |
3 |
6 |
|
DDR_A_D25 |
63 |
DQ24 |
DQ28 |
64 |
DDR_A_D29 |
|
|
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DDR_A_MA4 |
4 |
5 |
|
|
65 |
DQ25 |
DQ29 |
66 |
|
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|
DDR_A_DM3 |
VSS |
VSS |
DDR_A_DQS#3 |
|
|
|
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|
|
||
|
67 |
68 |
|
|
|
|
47_0804_8P4R_5% |
|||||
|
|
69 |
DM3 |
DQS3# |
70 |
DDR_A_DQS3 |
|
|
|
|
RP4 |
|
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|
71 |
NC |
DQS3 |
72 |
|
|
|
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DDR_A_MA5 |
8 |
1 |
|
DDR_A_D26 |
73 |
VSS |
VSS |
74 |
DDR_A_D30 |
|
|
|
DDR_A_MA8 |
7 |
2 |
|
DDR_A_D27 |
75 |
DQ26 |
DQ30 |
76 |
DDR_A_D31 |
|
|
|
DDR_A_MA9 |
6 |
3 |
|
|
77 |
DQ27 |
DQ31 |
78 |
|
|
|
|
DDR_A_MA12 |
5 |
4 |
|
DDR_CKE0_DIMMA |
79 |
VSS |
VSS |
80 |
DDR_CKE1_DIMMA |
|
|
|
|
|
|
5 DDR_CKE0_DIMMA |
CKE0 |
NC/CKE1 |
DDR_CKE1_DIMMA |
5 |
|
47_0804_8P4R_5% |
||||||
|
|
81 |
VDD |
VDD |
82 |
|
|
|
|
|
||
|
|
83 |
84 |
DDR_A_MA15 |
|
|
|
|
RP5 |
|
||
5 DDR_A_BS#2 |
DDR_A_BS#2 |
85 |
NC |
NC/A15 |
86 |
DDR_A_MA14 |
|
|
|
DDR_A_BS#0 |
8 |
1 |
|
87 |
BA2 |
NC/A14 |
88 |
|
|
|
|
DDR_A_MA10 |
7 |
2 |
|
|
DDR_A_MA12 |
89 |
VDD |
VDD |
90 |
DDR_A_MA11 |
|
|
|
DDR_A_MA3 |
6 |
3 |
|
DDR_A_MA9 |
91 |
A12 |
A11 |
92 |
DDR_A_MA7 |
|
|
|
DDR_A_MA1 |
5 |
4 |
|
DDR_A_MA8 |
93 |
A9 |
A7 |
94 |
DDR_A_MA6 |
|
|
|
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|
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|
95 |
A8 |
A6 |
96 |
|
|
|
|
|
47_0804_8P4R_5% |
|
|
DDR_A_MA5 |
97 |
VDD |
VDD |
98 |
DDR_A_MA4 |
|
|
|
|
RP6 |
|
|
DDR_A_MA3 |
99 |
A5 |
A4 |
100 |
DDR_A_MA2 |
|
|
|
DDR_A_ODT1 |
8 |
1 |
|
DDR_A_MA1 |
101 |
A3 |
A2 |
102 |
DDR_A_MA0 |
|
|
|
DDR_CS1_DIMMA# |
7 |
2 |
|
|
103 |
A1 |
A0 |
104 |
|
|
|
|
DDR_A_CAS# |
6 |
3 |
|
DDR_A_MA10 |
105 |
VDD |
VDD |
106 |
DDR_A_BS#1 |
|
|
|
DDR_A_WE# |
5 |
4 |
|
A10/AP |
BA1 |
DDR_A_BS#1 5 |
|
||||||||
5 DDR_A_BS#0 |
DDR_A_BS#0 |
107 |
BA0 |
RAS# |
108 |
DDR_A_RAS# |
DDR_A_RAS# 5 |
|
|
|
|
|
5 DDR_A_WE# |
DDR_A_WE# |
109 |
WE# |
S0# |
110 |
DDR_CS0_DIMMA# |
DDR_CS0_DIMMA# |
5 |
|
47_0804_8P4R_5% |
||
|
|
111 |
VDD |
VDD |
112 |
|
|
|
|
|
RP7 |
|
5 DDR_A_CAS# |
DDR_A_CAS# |
113 |
114 |
DDR_A_ODT0 |
DDR_A_ODT0 |
5 |
|
DDR_A_MA13 |
1 |
8 |
||
DDR_CS1_DIMMA# |
115 |
CAS# |
ODT0 |
116 |
DDR_A_MA13 |
|
DDR_A_ODT0 |
2 |
7 |
|||
5 DDR_CS1_DIMMA# |
|
117 |
NC/S1# |
NC/A13 |
118 |
|
|
|
|
DDR_A_RAS# |
3 |
6 |
|
DDR_A_ODT1 |
119 |
VDD |
VDD |
120 |
|
|
|
|
DDR_CS0_DIMMA# |
4 |
5 |
5 DDR_A_ODT1 |
NC/ODT1 |
NC |
|
|
|
|
||||||
|
|
121 |
VSS |
VSS |
122 |
|
|
|
|
|
|
|
|
DDR_A_D32 |
123 |
124 |
DDR_A_D36 |
|
|
|
|
47_0804_8P4R_5% |
|||
|
DDR_A_D33 |
125 |
DQ32 |
DQ36 |
126 |
DDR_A_D37 |
|
|
|
|
|
|
|
|
127 |
DQ33 |
DQ37 |
128 |
|
|
|
|
|
|
|
|
DDR_A_DQS#4 |
VSS |
VSS |
DDR_A_DM4 |
|
|
|
|
|
|
||
|
129 |
130 |
|
|
|
|
|
|
||||
|
DDR_A_DQS4 |
131 |
DQS4# |
DM4 |
132 |
|
|
|
|
|
|
|
|
|
133 |
DQS4 |
VSS |
134 |
DDR_A_D38 |
|
|
|
|
|
|
|
DDR_A_D34 |
135 |
VSS |
DQ38 |
136 |
DDR_A_D39 |
|
|
|
|
|
|
|
DDR_A_D35 |
137 |
DQ34 |
DQ39 |
138 |
|
|
|
|
|
|
|
|
|
139 |
DQ35 |
VSS |
140 |
DDR_A_D44 |
|
|
|
|
|
|
|
DDR_A_D40 |
141 |
VSS |
DQ44 |
142 |
DDR_A_D45 |
|
|
|
|
|
|
|
DDR_A_D41 |
143 |
DQ40 |
DQ45 |
144 |
|
|
|
|
|
|
|
|
|
145 |
DQ41 |
VSS |
146 |
DDR_A_DQS#5 |
|
|
|
|
|
|
|
DDR_A_DM5 |
147 |
VSS |
DQS5# |
148 |
DDR_A_DQS5 |
|
|
|
|
|
|
|
|
149 |
DM5 |
DQS5 |
150 |
|
|
|
|
|
|
|
|
DDR_A_D42 |
VSS |
VSS |
DDR_A_D46 |
|
|
|
|
|
|
||
|
151 |
152 |
|
|
|
|
|
|
||||
|
DDR_A_D43 |
153 |
DQ42 |
DQ46 |
154 |
DDR_A_D47 |
|
|
|
|
|
|
|
|
155 |
DQ43 |
DQ47 |
156 |
|
|
|
|
|
|
|
|
DDR_A_D48 |
VSS |
VSS |
DDR_A_D52 |
|
|
|
|
|
|
||
|
157 |
158 |
|
|
|
|
|
|
||||
|
DDR_A_D49 |
159 |
DQ48 |
DQ52 |
160 |
DDR_A_D53 |
|
|
|
|
|
|
|
|
161 |
DQ49 |
DQ53 |
162 |
|
|
|
|
|
|
|
|
|
VSS |
VSS |
|
|
|
|
|
|
|
||
|
|
163 |
NC,TEST |
CK1 |
164 |
|
DDR_A_CLK1 |
5 |
|
|
|
|
|
DDR_A_DQS#6 |
165 |
VSS |
CK1# |
166 |
|
DDR_A_CLK#1 |
5 |
|
|
|
|
|
167 |
168 |
|
|
|
|
|
|||||
|
DDR_A_DQS6 |
169 |
DQS6# |
VSS |
170 |
DDR_A_DM6 |
|
|
|
|
|
|
|
|
171 |
DQS6 |
DM6 |
172 |
|
|
|
|
|
|
|
|
|
VSS |
VSS |
|
|
|
|
|
|
|
||
|
DDR_A_D50 |
173 |
174 |
DDR_A_D54 |
|
|
|
|
|
|
||
|
DDR_A_D51 |
175 |
DQ50 |
DQ54 |
176 |
DDR_A_D55 |
|
|
|
|
|
|
|
|
177 |
DQ51 |
DQ55 |
178 |
|
|
|
|
|
|
|
|
DDR_A_D56 |
VSS |
VSS |
DDR_A_D60 |
|
|
|
|
|
|
||
|
179 |
180 |
|
|
|
|
|
|
||||
|
DDR_A_D57 |
181 |
DQ56 |
DQ60 |
182 |
DDR_A_D61 |
|
|
|
|
|
|
|
|
183 |
DQ57 |
DQ61 |
184 |
|
|
|
|
|
|
|
|
DDR_A_DM7 |
VSS |
VSS |
DDR_A_DQS#7 |
|
|
|
|
|
|
||
|
185 |
186 |
|
|
|
|
|
|
||||
|
|
187 |
DM7 |
DQS7# |
188 |
DDR_A_DQS7 |
|
|
|
|
|
|
|
DDR_A_D58 |
189 |
VSS |
DQS7 |
190 |
|
|
|
|
|
|
|
|
DDR_A_D59 |
191 |
DQ58 |
VSS |
192 |
DDR_A_D62 |
|
|
|
|
|
|
|
|
193 |
DQ59 |
DQ62 |
194 |
DDR_A_D63 |
|
|
|
|
|
|
8,15,21,27 SMB_CK_DAT0 |
|
195 |
VSS |
DQ63 |
196 |
|
|
|
|
|
|
|
|
SDA |
VSS |
|
|
|
|
|
|
|
|||
8,15,21,27 SMB_CK_CLK0 |
|
197 |
SCL |
SAO |
198 |
Security Classification |
|
|
Compal Secret Data |
|
|
|
|
+3VS |
199 |
VDDSPD |
SA1 |
200 |
|
|
|
|
|
|
|
|
203 |
204 |
|
|
2008-09-25 |
|
2009-09-25 |
|
||||
|
1 |
VSS |
VSS |
Issued Date |
|
Deciphered Date |
|
|||||
|
C103 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
@FOX_AS0A426-M4R-TR_200P |
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL |
|||
|
|
|
2 |
0.1U_0402_16V7K |
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D |
|||
|
|
|
|
DIMM0 STD H:5.2mm (Bot) |
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. |
|||
|
|
|
|
|
|
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS |
||
A |
|
|
|
B |
|
C |
|
D |
|
|
|
|
|
||||
E
1
+1.8V
C87 1 
2 0.1U_0402_16V7K
C88 1 
2 0.1U_0402_16V7K
C90 1 
2 0.1U_0402_16V7K
C89 1 
2 0.1U_0402_16V7K
2
C91 1 
2 0.1U_0402_16V7K
C92 1 
2 0.1U_0402_16V7K
C93 1 
2 0.1U_0402_16V7K
C94 1 
2 0.1U_0402_16V7K
C98 1 
2 0.1U_0402_16V7K
C97 1 
2 0.1U_0402_16V7K
C100 1 
2 0.1U_0402_16V7K
C99 1 
2 0.1U_0402_16V7K
C102 |
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0.1U_0402_16V7K |
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C101 |
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0.1U_0402_16V7K |
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Title |
Compal Electronics, Inc. |
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DDRII SO-DIMM 1 |
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Size |
Document Number |
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Rev |
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Custom |
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LA-4971P |
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1.0 |
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Date: |
Wednesday, April 22, 2009 |
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Sheet 9 of |
45 |
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U3B GM : RS780MN & RS780MC, PM : RX781 |
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PCIE_GTX_C_MRX_P[0..15] |
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PCIE_GTX_C_MRX_P[0..15] |
19 |
Polarity inversion |
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PCIE_GTX_C_MRX_N0 |
D4 |
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GFX_RX0P |
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GFX_TX0P |
A5 |
PCIE_MTX_GRX_P0 PM@ |
C120 |
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0.1U_0402_16V7K |
PCIE_MTX_C_GRX_N0 |
Polarity inversion |
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PCIE_MTX_C_GRX_P[0.. |
15] |
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PCIE_MTX_C_GRX_P[0..15] |
19 |
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PCIE_GTX_C_MRX_N[0..15] |
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PCIE_GTX_C_MRX_P0 |
C4 |
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GFX_RX0N |
PART 2 OF 6 |
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GFX_TX0N |
B5 |
PCIE_MTX_GRX_N0 PM@ |
C121 |
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0.1U_0402_16V7K |
PCIE_MTX_C_GRX_P0 |
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PCIE_MTX_C_GRX_N[0.. |
15] |
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PCIE_GTX_C_MRX_N[0..15] |
19 |
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PCIE_GTX_C_MRX_P1 |
A3 |
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GFX_RX1P |
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GFX_TX1P |
A4 |
PCIE_MTX_GRX_P1 PM@ |
C122 |
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0.1U_0402_16V7K |
PCIE_MTX_C_GRX_N1 |
Polarity inversion |
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PCIE_MTX_C_GRX_N[0..15] |
19 |
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PCIE_GTX_C_MRX_N1 |
B3 |
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GFX_RX1N |
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GFX_TX1N |
B4 |
PCIE_MTX_GRX_N1 PM@ |
C123 |
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0.1U_0402_16V7K |
PCIE_MTX_C_GRX_P1 |
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Polarity inversion |
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PCIE_GTX_C_MRX_N2 |
C2 |
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C3 |
PCIE_MTX_GRX_P2 PM@ |
C124 |
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0.1U_0402_16V7K |
PCIE_MTX_C_GRX_P2 |
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GFX_RX2P |
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GFX_TX2P |
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PCIE_GTX_C_MRX_P2 |
C1 |
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B2 |
PCIE_MTX_GRX_N2 PM@ |
C125 |
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0.1U_0402_16V7K |
PCIE_MTX_C_GRX_N2 |
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GFX_RX2N |
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GFX_TX2N |
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PCIE_MTX_GRX_P3 PM@ |
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Polarity inversion |
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PCIE_GTX_C_MRX_N3 |
E5 |
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D1 |
C126 |
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0.1U_0402_16V7K |
PCIE_MTX_C_GRX_N3 |
Polarity inversion |
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GFX_RX3P |
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GFX_TX3P |
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PCIE_GTX_C_MRX_P3 |
F5 |
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D2 |
PCIE_MTX_GRX_N3 PM@ |
C127 |
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0.1U_0402_16V7K |
PCIE_MTX_C_GRX_P3 |
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GFX_RX3N |
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GFX_TX3N |
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PCIE_MTX_GRX_P4 |
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Polarity inversion |
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PCIE_GTX_C_MRX_N4 |
G5 |
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E2 |
PM@ |
C128 |
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0.1U_0402_16V7K |
PCIE_MTX_C_GRX_P4 |
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GFX_RX4P |
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GFX_TX4P |
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PCIE_GTX_C_MRX_P4 |
G6 |
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GFX_RX4N |
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GFX_TX4N |
E1 |
PCIE_MTX_GRX_N4 PM@ |
C129 |
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0.1U_0402_16V7K |
PCIE_MTX_C_GRX_N4 |
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PCIE_MTX_GRX_P5 PM@ |
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PCIE_MTX_C_GRX_P5 |
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Polarity inversion |
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PCIE_GTX_C_MRX_N5 |
H5 |
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F4 |
C130 |
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0.1U_0402_16V7K |
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GFX_RX5P |
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GFX_TX5P |
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PCIE_GTX_C_MRX_P5 |
H6 |
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F3 |
PCIE_MTX_GRX_N5 PM@ |
C131 |
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0.1U_0402_16V7K |
PCIE_MTX_C_GRX_N5 |
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PCIE_GTX_C_MRX_P6 |
J6 |
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GFX_RX5N |
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GFX_TX5N |
F1 |
PCIE_MTX_GRX_P6 PM@ |
C132 |
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0.1U_0402_16V7K |
PCIE_MTX_C_GRX_P6 |
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GFX_RX6P |
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GFX_TX6P |
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PCIE_GTX_C_MRX_N6 |
J5 |
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F2 |
PCIE_MTX_GRX_N6 |
PM@ |
C133 |
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0.1U_0402_16V7K |
PCIE_MTX_C_GRX_N6 |
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GFX_RX6N |
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GFX_TX6N |
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< From MXM VGA board > |
Polarity inversion |
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PCIE_GTX_C_MRX_N7 |
J7 |
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H4 |
PCIE_MTX_GRX_P7 PM@ |
C134 |
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0.1U_0402_16V7K |
PCIE_MTX_C_GRX_P7 |
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< To MXM VGA board > |
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GFX_RX7P |
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GFX_TX7P |
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PCIE_GTX_C_MRX_P7 |
J8 |
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H3 |
PCIE_MTX_GRX_N7 PM@ |
C135 |
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0.1U_0402_16V7K |
PCIE_MTX_C_GRX_N7 |
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GFX_RX7N |
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GFX_TX7N |
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PCIE_MTX_GRX_P8 PM@ |
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PCIE_MTX_C_GRX_P8 |
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Polarity inversion |
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PCIE_GTX_C_MRX_N8 |
L5 |
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H1 |
C136 |
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0.1U_0402_16V7K |
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GFX_RX8P |
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GFX_TX8P |
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PCIE_GTX_C_MRX_P8 |
L6 |
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H2 |
PCIE_MTX_GRX_N8 PM@ |
C137 |
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0.1U_0402_16V7K |
PCIE_MTX_C_GRX_N8 |
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GFX_RX8N |
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GFX_TX8N |
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PCIE_MTX_GRX_P9 |
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PCIE_MTX_C_GRX_P9 |
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Polarity inversion |
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PCIE_GTX_C_MRX_N9 |
M8 |
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J2 |
PM@ |
C138 |
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0.1U_0402_16V7K |
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GFX_RX9P |
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GFX_TX9P |
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PCIE_GTX_C_MRX_P9 |
L8 |
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J1 |
PCIE_MTX_GRX_N9 PM@ |
C139 |
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0.1U_0402_16V7K |
PCIE_MTX_C_GRX_N9 |
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Polarity inversion |
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PCIE_GTX_C_MRX_N10 |
P7 |
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GFX_RX9N |
GFX |
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GFX_TX9N |
K4 |
PCIE_MTX_GRX_P10 PM@ |
C140 |
1 |
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2 |
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0.1U_0402_16V7K |
PCIE_MTX_C_GRX_P10 |
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GFX_RX10P |
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GFX_TX10P |
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PCIE_GTX_C_MRX_P10 |
M7 |
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K3 |
PCIE_MTX_GRX_N10 PM@ |
C141 |
1 |
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2 |
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0.1U_0402_16V7K |
PCIE_MTX_C_GRX_N10 |
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GFX_RX10N |
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GFX_TX10N |
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PCIE_MTX_GRX_P11 |
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PCIE_MTX_C_GRX_P11 |
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Polarity inversion |
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PCIE_GTX_C_MRX_N11 |
P5 |
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K1 |
PM@ |
C142 |
1 |
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2 |
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0.1U_0402_16V7K |
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GFX_RX11P |
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GFX_TX11P |
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PCIE_GTX_C_MRX_P11 |
M5 |
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GFX_RX11N |
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GFX_TX11N |
K2 |
PCIE_MTX_GRX_N11 PM@ |
C143 |
1 |
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2 |
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0.1U_0402_16V7K |
PCIE_MTX_C_GRX_N11 |
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Polarity inversion |
|
PCIE_GTX_C_MRX_N12 |
R8 |
|
GFX_RX12P |
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GFX_TX12P |
M4 |
PCIE_MTX_GRX_P12 PM@ |
C144 |
1 |
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2 |
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0.1U_0402_16V7K |
PCIE_MTX_C_GRX_N12 |
Polarity inversion |
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PCIE_GTX_C_MRX_P12 |
P8 |
|
I/F |
|
M3 |
PCIE_MTX_GRX_N12 PM@ |
C145 |
1 |
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2 |
|
0.1U_0402_16V7K |
PCIE_MTX_C_GRX_P12 |
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GFX_RX12N |
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GFX_TX12N |
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PCIE_MTX_GRX_P13 PM@ |
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Polarity inversion |
|
PCIE_GTX_C_MRX_N13 |
R6 |
|
M1 |
C146 |
1 |
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2 |
|
0.1U_0402_16V7K |
PCIE_MTX_C_GRX_P13 |
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GFX_RX13P |
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GFX_TX13P |
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|
PCIE_GTX_C_MRX_P13 |
R5 |
|
|
M2 |
PCIE_MTX_GRX_N13 PM@ |
C147 |
1 |
|
2 |
|
0.1U_0402_16V7K |
PCIE_MTX_C_GRX_N13 |
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|
Polarity inversion |
|
PCIE_GTX_C_MRX_N14 |
P4 |
|
GFX_RX13N |
PCIE |
|
GFX_TX13N |
N2 |
PCIE_MTX_GRX_P14 |
PM@ |
C148 |
1 |
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|
2 |
|
0.1U_0402_16V7K |
PCIE_MTX_C_GRX_N14 |
Polarity inversion |
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GFX_RX14P |
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GFX_TX14P |
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PCIE_GTX_C_MRX_P14 |
P3 |
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N1 |
PCIE_MTX_GRX_N14 PM@ |
C149 |
1 |
|
2 |
|
0.1U_0402_16V7K |
PCIE_MTX_C_GRX_P14 |
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GFX_RX14N |
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GFX_TX14N |
|
PCIE_MTX_GRX_P15 PM@ |
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|
Polarity inversion |
|
PCIE_GTX_C_MRX_N15 |
T4 |
|
|
P1 |
C150 |
1 |
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|
2 |
|
0.1U_0402_16V7K |
PCIE_MTX_C_GRX_P15 |
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GFX_RX15P |
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GFX_TX15P |
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|
PCIE_GTX_C_MRX_P15 |
T3 |
|
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|
P2 |
PCIE_MTX_GRX_N15 |
PM@ |
C151 |
1 |
|
2 |
|
0.1U_0402_16V7K |
PCIE_MTX_C_GRX_N15 |
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|
27 PCIE_PTX_C_IRX_P0 |
|
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|
|
AE3 |
|
GFX_RX15N |
|
|
GFX_TX15N |
AC1 |
PCIE_ITX_PRX_P0 |
|
|
C152 |
|
1 |
|
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0.1U_0402_16V7K |
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PCIE_ITX_C_PRX_P0 27 |
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2 |
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GPP_RX0P |
|
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GPP_TX0P |
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|||||||||||
|
|
< To New Card > |
|
27 PCIE_PTX_C_IRX_N0 |
|
|
|
|
|
AD4 |
|
GPP_RX0N |
|
|
GPP_TX0N |
AC2 |
PCIE_ITX_PRX_N0 |
|
|
C153 |
1 |
|
2 |
|
0.1U_0402_16V7K |
|
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|
|
|
PCIE_ITX_C_PRX_N0 |
27 |
< To New Card > |
|
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|
||||||||||||||||||||||||||
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AE2 |
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AB4 |
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AD3 |
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GPP_RX1P |
|
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GPP_TX1P |
AB3 |
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GPP_RX1N |
|
|
GPP_TX1N |
|
PCIE_ITX_PRX_P2 |
WLAN@ C156 |
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0.1U_0402_16V7K |
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||||||||||
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|
< To WLAN > |
|
|
27 PCIE_PTX_C_IRX_P2 |
|
|
|
|
|
AD1 |
|
GPP_RX2P |
|
|
GPP_TX2P |
AA2 |
|
1 |
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2 |
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|
PCIE_ITX_C_PRX_P2 |
27 |
< To WLAN > |
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27 PCIE_PTX_C_IRX_N2 |
|
|
|
|
|
AD2 |
|
GPP_RX2N |
PCIE I/F GPP |
GPP_TX2N |
AA1 |
PCIE_ITX_PRX_N2 |
WLAN@ C157 |
|
1 |
|
|
2 |
|
0.1U_0402_16V7K |
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PCIE_ITX_C_PRX_N2 27 |
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26 PCIE_PTX_C_IRX_P3 |
|
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|
V5 |
|
GPP_RX3P |
|
|
GPP_TX3P |
Y1 |
PCIE_ITX_PRX_P3 |
|
|
C158 |
|
1 |
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|
2 |
|
0.1U_0402_16V7K |
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PCIE_ITX_C_PRX_P3 26 |
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|
< To LAN > |
|
|
26 PCIE_PTX_C_IRX_N3 |
|
|
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|
|
W6 |
|
GPP_RX3N |
|
|
GPP_TX3N |
Y2 |
PCIE_ITX_PRX_N3 |
|
|
C159 |
1 |
|
2 |
|
0.1U_0402_16V7K |
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PCIE_ITX_C_PRX_N3 |
26 |
< To LAN > |
|
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|||||||||||||||||||||||
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U5 |
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Y4 |
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U6 |
|
GPP_RX4P |
|
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GPP_TX4P |
Y3 |
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U8 |
|
GPP_RX4N |
|
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GPP_TX4N |
V1 |
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U7 |
|
GPP_RX5P |
|
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GPP_TX5P |
V2 |
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20 |
SB_RX0P |
|
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|
AA8 |
|
GPP_RX5N |
|
|
GPP_TX5N |
AD7 |
SB_TX0P_C |
|
|
C162 |
1 |
|
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0.1U_0402_16V7K |
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SB_TX0P 20 |
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SB_RX0P |
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SB_TX0P |
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2 |
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20 |
SB_RX0N |
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Y8 |
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SB_RX0N |
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SB_TX0N |
AE7 |
SB_TX0N_C |
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C163 |
1 |
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2 |
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0.1U_0402_16V7K |
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SB_TX0N 20 |
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20 |
SB_RX1P |
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AA7 |
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SB_RX1P |
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SB_TX1P |
AE6 |
SB_TX1P_C |
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C164 |
1 |
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2 |
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0.1U_0402_16V7K |
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SB_TX1P 20 |
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< From SB700 : x4 PCIE A-link > |
20 |
SB_RX1N |
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Y7 |
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SB_RX1N |
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SB_TX1N |
AD6 |
SB_TX1N_C |
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C165 |
1 |
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2 |
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0.1U_0402_16V7K |
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SB_TX1N 20 |
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< To SB700 : x4 PCEI A-link> |
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20 |
SB_RX2P |
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AA5 |
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SB_RX2P |
PCIE I/F SB |
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SB_TX2P |
AB6 |
SB_TX2P_C |
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C166 |
1 |
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2 |
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0.1U_0402_16V7K |
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SB_TX2P 20 |
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20 |
SB_RX2N |
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AA6 |
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SB_RX2N |
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SB_TX2N |
AC6 |
SB_TX2N_C |
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C168 |
1 |
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2 |
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0.1U_0402_16V7K |
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SB_TX2N 20 |
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20 |
SB_RX3P |
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W5 |
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SB_RX3P |
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SB_TX3P |
AD5 |
SB_TX3P_C |
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C169 |
1 |
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2 |
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0.1U_0402_16V7K |
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SB_TX3P 20 |
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20 |
SB_RX3N |
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Y5 |
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SB_RX3N |
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SB_TX3N |
AE5 |
SB_TX3N_C |
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C167 |
1 |
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2 |
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0.1U_0402_16V7K |
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SB_TX3N 20 |
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PCIE_CALRP |
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R55 |
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1.27K_0402_1% |
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< TX Impedance Calibration. Connect to GND > |
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AC8 |
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1 |
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2 |
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PCE_CALRP(PCE_BCALRP) |
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AB8 |
PCIE_CALRN |
|
R56 |
1 |
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2 |
2K_0402_1% |
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+1.1VS |
|
< RX Impedance Calibration. Connect to VDDPCIE > |
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RS780MCR3@ |
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PCE_CALRN(PCE_BCALRN) |
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RS780M_FCBGA528 |
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U3A |
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RS780M Display Port Support (muxed on GFX) |
|
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||||||||||||
|
|
H_CADOP[0..15] |
|
|
H_CADOP[0..15] |
4 |
|
|
|
H_CADOP0 |
Y25 |
|
HT_RXCAD0P |
|
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HT_TXCAD0P |
D24 |
H_CADIP0 |
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H_CADIP[0..15] |
|
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H_CADIP[0..15] |
4 |
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H_CADON[0..15] |
|
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|
H_CADON0 |
Y24 |
|
HT_RXCAD0N |
PART 1 OF 6 |
|
HT_TXCAD0N |
D25 |
H_CADIN0 |
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H_CADIN[0..15] |
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H_CADON[0..15] |
4 |
|
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|
H_CADOP1 |
V22 |
|
|
E24 |
H_CADIP1 |
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|
H_CADIN[0..15] |
4 |
|
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|
DP0 |
|
GFX_TX0,TX1,TX2 and TX3 |
|
AUX0 and HPD0 |
|
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|||||||||||||||||||||||||||||
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H_CADON1 |
V23 |
|
HT_RXCAD1P |
|
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HT_TXCAD1P |
E25 |
H_CADIN1 |
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HT_RXCAD1N |
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HT_TXCAD1N |
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H_CADOP2 |
V25 |
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F24 |
H_CADIP2 |
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H_CADON2 |
V24 |
|
HT_RXCAD2P |
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HT_TXCAD2P |
F25 |
H_CADIN2 |
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DP1 |
|
GFX_TX4,TX5,TX6 and TX7 |
|
AUX1 and HPD1 |
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H_CADOP3 |
U24 |
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HT_RXCAD2N |
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HT_TXCAD2N |
F23 |
H_CADIP3 |
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H_CADON3 |
U25 |
|
HT_RXCAD3P |
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HT_TXCAD3P |
F22 |
H_CADIN3 |
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H_CADOP4 |
T25 |
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HT_RXCAD3N |
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HT_TXCAD3N |
H23 |
H_CADIP4 |
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H_CADON4 |
T24 |
|
HT_RXCAD4P |
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HT_TXCAD4P |
H22 |
H_CADIN4 |
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H_CADOP5 |
P22 |
|
HT_RXCAD4N |
|
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HT_TXCAD4N |
J25 |
H_CADIP5 |
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H_CADON5 |
P23 |
|
HT_RXCAD5P |
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HT_TXCAD5P |
J24 |
H_CADIN5 |
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|||||||
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|
H_CADOP6 |
P25 |
|
HT_RXCAD5N |
I/F |
|
HT_TXCAD5N |
K24 |
H_CADIP6 |
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H_CADON6 |
P24 |
|
HT_RXCAD6P |
|
HT_TXCAD6P |
K25 |
H_CADIN6 |
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|
< If integrated GFX is used, some PCIE pairs are used as HDMI signal pairs > |
|
|
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|||||||||||||||||||
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HT_RXCAD6N |
|
HT_TXCAD6N |
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||||||||||||||||||||||||
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H_CADOP7 |
N24 |
|
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K23 |
H_CADIP7 |
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||||||||||
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|
HT_RXCAD7P |
CPU |
|
HT_TXCAD7P |
|
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|||||||||||
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H_CADON7 |
N25 |
|
|
K22 |
H_CADIN7 |
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|
PCIE_MTX_GRX_P0 IHDMI@ R74 1 |
2 |
0_0402_5% |
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HDMI_TXD2+ |
18,19 |
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HT_RXCAD7N |
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HT_TXCAD7N |
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< From S1G2 CPU : x16 HT> |
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< To S1G2 CPU : x16 HT> |
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PCIE_MTX_GRX_N0 IHDMI@ R75 |
1 |
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2 |
0_0402_5% |
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HDMI_TXD2- |
18,19 |
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H_CADOP8 |
AC24 |
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F21 |
H_CADIP8 |
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PCIE_MTX_GRX_P1 IHDMI@ R76 1 |
2 |
0_0402_5% |
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HT_RXCAD8P |
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HT_TXCAD8P |
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HDMI_TXD1+ |
18,19 |
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H_CADON8 |
AC25 |
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G21 |
H_CADIN8 |
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PCIE_MTX_GRX_N1 IHDMI@ R81 1 |
2 |
0_0402_5% |
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HDMI_TXD1- |
18,19 |
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H_CADOP9 |
AB25 |
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HT_RXCAD8N |
TRANSPORT |
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HT_TXCAD8N |
G20 |
H_CADIP9 |
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HT_RXCAD14N |
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H_CADON14 |
U21 |
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HT_TXCAD14N |
P21 |
H_CADIN14 |
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H_CADON9 |
AB24 |
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HT_RXCAD9P |
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HT_TXCAD9P |
H21 |
H_CADIN9 |
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PCIE_MTX_GRX_P2 IHDMI@ R82 1 |
2 |
0_0402_5% |
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HDMI_TXD0+ |
18,19 |
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H_CADOP10 |
AA24 |
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HT_RXCAD9N |
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HT_TXCAD9N |
J20 |
H_CADIP10 |
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PCIE_MTX_GRX_N2 IHDMI@ R83 1 |
2 |
0_0402_5% |
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H_CADON10 |
AA25 |
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HT_RXCAD10P |
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HT_TXCAD10P |
J21 |
H_CADIN10 |
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PCIE_MTX_GRX_P3 IHDMI@ R84 1 |
2 |
0_0402_5% |
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HDMI_TXD0- |
18,19 |
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H_CADOP11 |
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HT_RXCAD10N |
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HT_TXCAD10N |
J18 |
H_CADIP11 |
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PCIE_MTX_GRX_N3 IHDMI@ R85 1 |
2 |
0_0402_5% |
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HDMI_CLK0+ |
18,19 |
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Y22 |
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HT_RXCAD11P |
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HT_TXCAD11P |
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HDMI_CLK0- |
18,19 |
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H_CADON11 |
Y23 |
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HT_RXCAD11N |
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HT_TXCAD11N |
K17 |
H_CADIN11 |
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H_CADOP12 |
W21 |
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L19 |
H_CADIP12 |
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H_CADON12 |
W20 |
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HT_RXCAD12P |
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HT_TXCAD12P |
J19 |
H_CADIN12 |
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H_CADOP13 |
V21 |
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HT_RXCAD12N |
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HT_TXCAD12N |
M19 |
H_CADIP13 |
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H_CADON13 |
V20 |
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HT_RXCAD13P |
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HT_TXCAD13P |
L18 |
H_CADIN13 |
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H_CADOP14 |
U20 |
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HT_RXCAD13N |
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HT_TXCAD13N |
M21 |
H_CADIP14 |
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HT_RXCAD14P |
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HT_TXCAD14P |
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H_CADOP15 |
U19 |
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HT_RXCAD15P |
HYPER |
HT_TXCAD15P |
P18 |
H_CADIP15 |
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H_CADON15 |
U18 |
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M18 |
H_CADIN15 |
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4 |
H_CLKON1 |
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AA22 |
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HT_RXCLK1N |
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HT_TXCLK1N |
L20 |
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H_CLKIN1 |
4 |
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HT_RXCAD15N |
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HT_TXCAD15N |
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4 |
H_CLKOP0 |
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T22 |
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HT_RXCLK0P |
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HT_TXCLK0P |
H24 |
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H_CLKIP0 |
4 |
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4 |
H_CLKON0 |
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T23 |
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HT_RXCLK0N |
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HT_TXCLK0N |
H25 |
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H_CLKIN0 |
4 |
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AB23 |
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L21 |
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4 |
H_CLKOP1 |
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HT_RXCLK1P |
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HT_TXCLK1P |
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H_CLKIP1 |
4 |
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4 |
H_CTLOP0 |
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H_CTLOP0 |
M22 |
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HT_RXCTL0P |
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HT_TXCTL0P |
M24 |
H_CTLIP0 |
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H_CTLIP0 |
4 |
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H_CTLON0 |
M23 |
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M25 |
H_CTLIN0 |
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4 |
H_CTLON0 |
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HT_RXCTL0N |
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HT_TXCTL0N |
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H_CTLIN0 |
4 |
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H_CTLOP1 |
R21 |
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P19 |
H_CTLIP1 |
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4 |
H_CTLOP1 |
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HT_RXCTL1P |
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HT_TXCTL1P |
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H_CTLIP1 |
4 |
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H_CTLON1 |
R20 |
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R18 |
H_CTLIN1 |
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4 |
H_CTLON1 |
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HT_RXCTL1N |
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HT_TXCTL1N |
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H_CTLIN1 |
4 |
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301_0402_1%1 |
2 |
R57 |
HT_RXCALP |
C23 |
HT_RXCALP |
HT_TXCALP |
B24 |
HT_TXCALP |
R58 |
1 |
2 |
301_0402_1% |
< Transmitter Calibration Resistor to HT_TXCALN > |
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HT_RXCALN |
A24 |
B25 |
HT_TXCALN |
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HT_RXCALN |
HT_TXCALN |
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0718 Place within 1" |
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RS780MCR3@RS780M_FCBGA528 |
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0718 Place within 1" |
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layout 1:2 |
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NEED CHECK R57 & R58 WITH AMD |
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layout 1:2 |
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/ |
Security Classification |
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Compal Secret Data |
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Compal Electronics, Inc. |
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Issued Date |
2008-09-25 |
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Deciphered Date |
2009-09-25 |
Title |
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RS780M&RX781-HT/PCIE |
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THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL |
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AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D |
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Document Number |
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Rev |
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Custom |
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LA-4971P |
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1.0 |
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DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS |
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MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. |
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Date: |
Wednesday, April 22, 2009 |
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Sheet |
10 |
of |
45 |
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A |
B |
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C |
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D |
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E |
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1
2
3
4
1
2
3
4
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A |
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B |
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C |
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D |
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E |
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AVDD=100mA |
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U3C |
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+AVDD1 |
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F12 |
AVDD1(NC) |
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TXOUT_L0P(NC) |
A22 |
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UMA_LCD_TXOUT0_A0+ 17 |
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+AVDD2 |
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E12 |
AVDD2(NC) |
PART 3 OF 6 |
TXOUT_L0N(NC) |
B22 |
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UMA_LCD_TXOUT0_A017 |
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F14 |
A21 |
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G15 |
AVDDDI(NC) |
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TXOUT_L1P(NC) |
B21 |
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UMA_LCD_TXOUT0_A1+ 17 |
< LVDS dual channel : channel 1 > |
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+AVDDQ |
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H15 |
AVSSDI(NC) |
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TXOUT_L1N(NC) |
B20 |
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UMA_LCD_TXOUT0_A1- |
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H14 |
AVDDQ(NC) |
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TXOUT_L2P(NC) |
A20 |
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UMA_LCD_TXOUT0_A2+ 17 |
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AVSSQ(NC) |
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TXOUT_L2N(DBG_GPIO0) |
A19 |
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UMA_LCD_TXOUT0_A2- |
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E17 |
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TXOUT_L3P(NC) |
B19 |
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C_Pr(DFT_GPIO5) |
CRT/TVOUT |
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TXOUT_L3N(DBG_GPIO2) |
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F19 |
BLUEb(NC) |
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TXOUT_U3N(NC) |
D19 |
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F17 |
Y(DFT_GPIO2) |
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F15 |
COMP_Pb(DFT_GPIO4) |
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TXOUT_U0P(NC) |
B18 |
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UMA_LCD_TZOUT0_B0+ 17 |
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UMA_CRT_R |
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TXOUT_U0N(NC) |
A18 |
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UMA_LCD_TZOUT0_B0- |
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16 |
UMA_CRT_R |
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G17 |
RED(DFT_GPIO0) |
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TXOUT_U1P(PCIE_RESET_GPIO3) |
B17 |
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UMA_LCD_TZOUT0_B1+ 17 |
< LVDS dual channel : channel 2 > |
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UMA_CRT_G |
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E18 |
REDb(NC) |
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TXOUT_U1N(PCIE_RESET_GPIO2) |
D20 |
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UMA_LCD_TZOUT0_B1- |
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16 |
UMA_CRT_G |
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F18 |
GREEN(DFT_GPIO1) |
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TXOUT_U2P(NC) |
D21 |
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UMA_LCD_TZOUT0_B2+ |
17 |
1 |
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UMA_CRT_B |
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E19 |
GREENb(NC) |
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TXOUT_U2N(NC) |
D18 |
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UMA_LCD_TZOUT0_B2- |
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16 |
UMA_CRT_B |
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BLUE(DFT_GPIO3) |
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14,16 UMA_CRT_HSYNC |
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UMA_CRT_HSYNC |
A11 |
DAC_HSYNC(PWM_GPIO4) |
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TXCLK_LP(DBG_GPIO1) |
B16 |
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UMA_LCD_TXCLK_ACLK+ 17 |
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14,16 UMA_CRT_VSYNC |
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UMA_CRT_VSYNC |
B11 |
DAC_VSYNC(PWM_GPIO6) |
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TXCLK_LN(DBG_GPIO3) |
A16 |
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UMA_LCD_TXCLK_ACLK17 |
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F8 |
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D16 |
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16 UMA_CRT_CLK |
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E8 |
DAC_SCL(PCE_RCALRN) |
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TXCLK_UP(PCIE_RESET_GPIO4) |
D17 |
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UMA_LCD_TZCLK_BCLK+ 17 |
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16 UMA_CRT_DATA |
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GPM@R65 |
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715_0402_1% |
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G14 |
DAC_SDA(PCE_TCALRN) |
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TXCLK_UN(PCIE_RESET_GPIO1) |
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UMA_LCD_TZCLK_BCLK- |
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DAC_RSET(PWM_GPIO1) |
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+VDDLTP18 |
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< DAC internal reference to set full scale DAC current > |
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GM@ |
R65 |
1 |
2 715_0402_1% |
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VDDLTP18(NC) |
A13 |
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+NB_PLLVDD |
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A12 |
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B13 |
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+NB_PLLVDD |
PLLVDD(NC) |
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VSSLTP18(NC) |
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+NB_HTPVDD |
D14 |
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+NB_HTPVDD |
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PLLVDD18(NC) |
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+VDDLT18 |
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B12 |
PLLVSS(NC) |
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LVTM |
VDDLT18_1(NC) |
A15 |
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PWR |
VDDLT18_2(NC) |
B15 |
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+VDDA18HTPLL |
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H17 |
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A14 |
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VDDA18HTPLL |
VDDLT33_1(NC) |
B14 |
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+VDDA18PCIEPLL |
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D7 |
VDDA18PCIEPLL1 |
VDDLT33_2(NC) |
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E7 |
VDDA18PCIEPLL2 |
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VSSLT1(VSS) |
C14 |
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VSSLT2(VSS) |
D15 |
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R67 1 |
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2 |
0_0402_5% NB_RESET# |
D8 |
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PLL |
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C16 |
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+1.1VS |
14,19,20,26,27,33,34 |
PLT_RST# |
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NB_PWRGD |
A10 |
SYSRESETb |
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VSSLT3(VSS) |
C18 |
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21 NB_PWRGD |
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C10 |
POWERGOOD |
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VSSLT4(VSS) |
C20 |
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6,20 |
LDT_STOP# |
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C12 |
LDTSTOPb |
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VSSLT5(VSS) |
E20 |
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6,20 |
CPU_LDT_REQ# |
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ALLOW_LDTSTOP |
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VSSLT6(VSS) |
C22 |
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R71 |
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C25 |
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PM |
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VSSLT7(VSS) |
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4.7K_0402_5% |
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15 |
CLK_NBHT |
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C24 |
HT_REFCLKP |
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15 |
CLK_NBHT# |
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HT_REFCLKN |
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1 1 |
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E11 |
CLOCKs |
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15 NB_OSC_14.318M |
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U1 |
REFCLK_P/OSCIN(OSCIN) |
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E9 |
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GM@ |
R73 2 |
1 |
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< LVDS digital power enable > |
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GPP_REFCLKP |
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100K_0402_5% |
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F11 |
REFCLK_N(PWM_GPIO3) |
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LVDS_DIGON(PCE_TCALRP) |
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UMA_ENVDD |
17 |
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LVDS_BLON(PCE_RCALRP) |
F7 |
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GM@ |
R79 1 |
2 |
0_0402_5% |
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UMA_ENBKL |
34 |
< LVDS backlight enable > |
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15 NBGFX_CLK |
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T2 |
GFX_REFCLKP |
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LVDS_ENA_BL(PWM_GPIO2) |
G12 |
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R72 |
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T1 |
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2 |
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15 NBGFX_CLK# |
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4.7K_0402_5% |
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GFX_REFCLKN |
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PAD T17 |
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GPM@R73 |
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100K_0402_5% |
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U2 |
GPP_REFCLKN |
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15 CLK_SBLINK_BCLK |
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V4 |
GPPSB_REFCLKP(SB_REFCLKP) |
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V3 |
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15 CLK_SBLINK_BCLK# |
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GPPSB_REFCLKN(SB_REFCLKN) |
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GPM@R78 |
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0_0402_5% |
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B9 |
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17 UMA_LCD_DDC_CLK |
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I2C_CLK |
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A9 |
MIS. |
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D9 |
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GM@ |
R78 1 |
2 |
0_0402_5% |
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< HDMI hot-plug detection > |
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17 |
UMA_LCD_DDC_DAT |
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B8 |
I2C_DATA |
TMDS_HPD(NC) |
D10 |
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HPD |
18,19,21 |
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18 |
HDMIDAT_UMA |
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A8 |
DDC_DATA0/AUX0N(NC) |
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HPD(NC) |
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18 |
HDMICLK_UMA |
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DDC_CLK0/AUX0P(NC) |
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< Strap option pin or gate side-port memory IO > |
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B7 |
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D12 |
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SUS_STAT# |
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14,21 |
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A7 |
DDC_CLK1/AUX1P(NC) |
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SUS_STAT#(PWM_GPIO5) |
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DDC_DATA1/AUX1N(NC) |
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THERMALDIODE_P |
AE8 |
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+3VS |
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@ |
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R88 |
2 |
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1 10K_0402_5% |
B10 |
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AD8 |
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G11 |
STRP_DATA |
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THERMALDIODE_N |
D13 |
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R80 1 |
2 1.8K_0402_5% |
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Strap pin |
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C8 |
RSVD |
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TESTMODE |
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14 |
AUX_CAL |
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AUX_CAL(NC) |
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RS780MCR3@ RS780M_FCBGA528
< Dedicated power for the DAC which can affect display quality > |
|
< Dedicated power for the DAC which can affect display quality > |
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|
|
+1.8VS |
R371 1 |
2 |
300_0402_5% NB_PWRGD |
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|||||||
GPM@ |
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L2 |
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GPM@ |
L4 |
PM1@ |
C172 |
PM1@ |
C198 |
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+3VS |
|
0_0603_5% |
|
+1.8VS |
0_0603_5% |
|
0_0603_5% |
|
0_0402_5% |
|
RS780 use 140 ohm, check RS880 use what value |
|
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|||||
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PM1@ |
C170 |
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L2 |
0_0603_5% |
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L4 |
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GM@ 1 |
2 |
BLM18PG121SN1D_0603 |
+AVDD1 |
GM@ |
0_0603_5% |
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+AVDD2 |
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GM@ |
R62 1 |
2 |
140_0402_1% UMA_CRT_R |
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3 |
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1 |
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1 |
1 |
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C170 |
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C172 |
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C198 |
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GM@ |
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GM@ |
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GM@ |
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GM@ |
R63 1 |
2 |
150_0402_1% UMA_CRT_G |
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2.2U_0603_6.3V4Z |
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2.2U_0603_6.3V4Z |
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0.1U_0402_16V7K |
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2 |
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2 |
2 |
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GM@ |
R64 1 |
2 |
150_0402_1% UMA_CRT_B |
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|||||
< DAC Bandgap Reference Voltage > |
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< 1.8V power for system PLLs > |
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|
< Power for integrated DVI/HDMI PLL macro > |
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||||
GPM@ |
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L6 |
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+1.8VS |
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0_0603_5% |
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GPM@ |
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L7 |
PM1@ |
C176 |
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GPM@ |
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L3 |
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PM1@ |
C171 |
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PM1@ |
C175 |
+1.8VS |
|
0_0603_5% |
|
0_0603_5% |
+1.8VS |
|
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0_0603_5% |
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0_0603_5% |
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||||
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L6 |
0_0603_5% |
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||
GM@ 1 |
2 |
BLM18PG121SN1D_0603 |
+AVDDQ |
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L7 |
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+NB_HTPVDD |
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L3 |
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+VDDLTP18 |
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1 |
GM@ 1 |
2 |
BLM18PG121SN1D_0603 |
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GM@ 2 |
|
1 BLM18PG121SN1D_0603 |
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C175 |
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1 |
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1 |
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GM@ |
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C176 |
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C171 |
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2.2U_0603_6.3V4Z |
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GM@ |
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GM@ |
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2 |
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2.2U_0603_6.3V4Z |
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2.2U_0603_6.3V4Z |
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||||
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2 |
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2 |
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< IO power for HyperTransport PLL > |
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|
< 1.1V Power for system PLLs > |
|
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|
|
< 1.8V IO power for the integrated DVI/HDMI interface > |
|
|
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|
|||||
+1.8VS |
|
+VDDA18HTPLL |
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GPM@ |
|
L9 |
PM1@ |
C178 |
|
|
GPM@L5 |
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|
PM1@ |
|
C173 |
|
|
L10 1 |
2 BLM18PG121SN1D_0603 |
|
+1.1VS |
|
0_0603_5% |
|
0_0603_5% |
+1.8VS |
|
0_0603_5% |
|
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|
0_0402_5% |
|
|||
|
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1 |
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C179 |
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L9 |
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+NB_PLLVDD |
GM@ |
L5 |
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GM@ 1 |
2 |
BLM18PG121SN1D_0603 |
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2 |
1 |
BLM18PG121SN1D_0603 |
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|
+VDDLT18 |
|||
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2.2U_0603_6.3V4Z |
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1 |
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1 |
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1 |
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2 |
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C178 |
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C174 |
C173 |
4 |
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||||||
< 1.8V IO power for PCI-E PLLs > |
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GM@ |
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GM@ |
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GM@ |
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+1.8VS |
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2 |
2.2U_0603_6.3V4Z |
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2 |
4.7U_0805_10V4Z |
2 |
0.1U_0402_16V7K |
||||
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+VDDA18PCIEPLL |
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L11 1 |
2 BLM18PG121SN1D_0603 |
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1 |
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Compal Electronics, Inc. |
|
|||||
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C180 |
|
/ Security Classification |
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Compal Secret Data |
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|||||||
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||||
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|
2.2U_0603_6.3V4Z |
Issued Date |
2008-09-25 |
Deciphered Date |
2009-09-25 |
|
Title |
|
|
|
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|
|
||||
|
|
2 |
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|
|
RS780 VEDIO/CLK GEN |
|
||||||||
|
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|
|
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL |
|
|
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|
|||||||||||
|
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|
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D |
Size |
Document Number |
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|
Rev |
||||||||
|
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Custom |
|
LA-4971P |
|
|
1.0 |
||||||||||
|
|
|
|
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS |
|
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|||||||||||
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|||||||||
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|
|
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. |
|
Date: |
Wednesday, April 22, 2009 |
Sheet |
11 |
of |
45 |
||||||||
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||||||||
A |
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B |
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C |
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D |
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E |
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2 |
1 |
B |
B |
U3D
|
|
|
PAR 4 OF 6 |
|
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|
AB12 |
MEM_A0(NC) |
|
MEM_DQ0/DVO_VSYNC(NC) |
AA18 |
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AE16 |
|
AA20 |
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||
|
V11 |
MEM_A1(NC) |
|
MEM_DQ1/DVO_HSYNC(NC) |
AA19 |
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|
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AE15 |
MEM_A2(NC) |
|
MEM_DQ2/DVO_DE(NC) |
Y19 |
|
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AA12 |
MEM_A3(NC) |
|
MEM_DQ3/DVO_D0(NC) |
V17 |
|
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AB16 |
MEM_A4(NC) |
|
MEM_DQ4(NC) |
AA17 |
|
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AB14 |
MEM_A5(NC) |
|
MEM_DQ5/DVO_D1(NC) |
AA15 |
|
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AD14 |
MEM_A6(NC) |
|
MEM_DQ6/DVO_D2(NC) |
Y15 |
|
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AD13 |
MEM_A7(NC) |
|
MEM_DQ7/DVO_D4(NC) |
AC20 |
|
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|
|
AD15 |
MEM_A8(NC) |
I/F |
MEM_DQ8/DVO_D3(NC) |
AD19 |
|
|
|
|
|
AC16 |
MEM_A9(NC) |
MEM_DQ9/DVO_D5(NC) |
AE22 |
|
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|
|
AE13 |
MEM_A10(NC) |
MEM_DQ10/DVO_D6(NC) |
AC18 |
|
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|
|
|
AC14 |
MEM_A11(NC) |
MEM_DQ11/DVO_D7(NC) |
AB20 |
|
|
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|
|
Y14 |
MEM_A12(NC) |
|
MEM_DQ12(NC) |
AD22 |
|
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MEM_A13(NC) |
|
MEM_DQ13/DVO_D9(NC) |
|
|
|
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|
|
Y12 |
MEM_RASb(NC)MEM/DVO_ |
MEM_DQS1P(NC) |
AE21 |
|
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|
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|
|
MEM_DQ14/DVO_D10(NC) |
AC22 |
|
|
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|
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AD16 |
MEM_BA0(NC) |
|
MEM_DQ15/DVO_D11(NC) |
AD21 |
|
|
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|
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AE17 |
MEM_BA1(NC) |
|
|
|
|
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|
|
AD17 |
MEM_BA2(NC) |
|
MEM_DQS0P/DVO_IDCKP(NC) |
Y17 |
|
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|
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W18 |
|
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||
|
W12 |
|
|
MEM_DQS0N/DVO_IDCKN(NC) |
AD20 |
|
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MEM_CASb(NC) |
MEM_DQS1N(NC) |
|
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|
AD18 |
|
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|||
|
MEM_WEb(NC) |
SBD_ |
|
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|
|
|
AB13 |
|
W17 |
|
|
|
|
||
|
AB18 |
MEM_CSb(NC) |
MEM_DM0(NC) |
AE19 |
|
|
|
|
|
|
V14 |
MEM_CKE(NC) |
MEM_DM1/DVO_D8(NC) |
|
|
|
|
|
|
|
|
MEM_ODT(NC) |
|
IOPLLVDD18(NC) |
AE23 |
|
|
+1.8VS |
|
|
V15 |
|
|
AE24 |
|
|
|||
|
W14 |
MEM_CKP(NC) |
|
IOPLLVDD(NC) |
|
|
|
+1.1VS |
|
|
MEM_CKN(NC) |
|
|
|
|
|
|
|
|
|
|
|
IOPLLVSS(NC) |
AD23 |
|
|
|
|
|
|
AE12 |
MEM_COMPP(NC) |
|
|
|
|
|
|
|
|
AD12 |
|
AE18 |
|
|
|
|
||
|
|
MEM_COMPN(NC) |
MEM_VREF(NC) |
|
|
|
|
|
|
RS780MCR3@ |
RS780M_FCBGA528 |
|
|
|
|
|
|
||
A |
A |
|
/ Security Classification |
|
Compal Secret Data |
|
|
Compal Electronics, Inc. |
|
|
||||||
|
|
|
|
|
|
|
|
|
|
|
||||
|
Issued Date |
2008-09-25 |
|
Deciphered Date |
2009-09-25 |
Title |
|
|
|
|
|
|
|
|
|
|
|
|
|
RS780M&RX781 SIDE PORT |
|
|
|||||||
|
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL |
|
|
|
||||||||||
|
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D |
Size |
Document Number |
|
|
|
|
|
Rev |
|||||
|
Custom |
|
LA-4971P |
|
|
|
1.0 |
|||||||
|
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS |
|
|
|
|
|||||||||
|
|
|
|
|
|
|
||||||||
|
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. |
|
|
|
|
|
|
|
|
|||||
|
|
|
|
|
|
|
Date: |
Wednesday, April 22, 2009 |
|
Sheet |
12 |
of |
45 |
|
2 |
|
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1 |
|
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|
|
|
|
A |
B |
C |
D |
E |
|
|
2A |
L16 0_0805_5% |
|
|
< Digital IO power for HyperTransport interface > |
||
+1.1VS |
2 |
1 |
|
|
|
|
|
|
|
|
|
1 |
1 |
1 |
1 |
|
1 |
|
|
|
C209 |
C206 |
|
C207 |
C208 |
C210 |
|
|
|
4.7U_0805_10V4Z |
0.1U_0402_16V7K |
|
0.1U_0402_16V7K |
0.1U_0402_16V7K |
0.1U_0402_16V7K |
|
|
|
2 |
2 |
2 |
2 |
|
2 |
|
2A |
L18 0_0805_5% |
|
|
< IO power for HyperTransport receive interface > |
||
2 |
1 |
|
|
|
|
|
|
|
|
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1 |
1 |
1 |
|
1 |
|
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C215 |
C214 |
|
C216 |
C217 |
C218 |
1 |
|
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|
|
|
10U_0805_10V4Z |
0.1U_0402_16V7K |
|
0.1U_0402_16V7K |
0.1U_0402_16V7K |
0.1U_0402_16V7K |
|
|
|
2 |
2 |
2 |
|
2 |
|
|
2A |
L19 0_0805_5% |
|
|
< IO power for HyperTransport transmit interface > |
||
+1.2V_HT |
2 |
1 |
|
|
|
|
|
|
|
|
|
1 |
1 |
1 |
1 |
|
1 |
|
|
|
C225 |
C226 |
|
C227 |
C228 |
C229 |
|
|
|
4.7U_0805_10V4Z |
0.1U_0402_16V7K |
|
0.1U_0402_16V7K |
0.1U_0402_16V7K |
0.1U_0402_16V7K |
|
|
|
2 |
2 |
2 |
2 |
|
2 |
|
2A |
|
L22 |
0_0805_5% |
|
|
< 1.8V IO power for PCI-E graphics, SB, and GPP interfaces > |
|||
+1.8VS |
2 |
1 |
|
|
|
|
|
|
||
|
|
|
1 |
1 |
|
|
1 |
1 |
1 |
1 |
|
|
|
C235 |
|
C246 |
|
C236 |
C237 |
C238 |
C239 |
|
|
|
4.7U_0805_10V4Z |
4.7U_0805_10V4Z |
0.1U_0402_16V7K |
0.1U_0402_16V7K |
0.1U_0402_16V7K |
0.1U_0402_16V7K |
||
|
|
|
2 |
2 |
|
|
2 |
2 |
2 |
2 |
2 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
< 1.8V IO transform power > |
|
||
+1.8VS |
|
|
|
|
|
|
< 1.8V power for side-port memory interface > |
|
||
|
1 |
|
|
|
|
|
|
|||
|
C251 |
|
+1.8VS |
GM@ L89 |
1 |
2 |
0_0603_5% |
|
|
|
|
|
|
|
|
|
|
|
1 |
|
|
|
1U_0402_6.3V4Z |
|
|
|
|
|
C252 |
|
|
|
|
2 |
|
|
GPM@L89 |
|
|
0_0603_5% GM@ |
|
|
|
|
|
|
|
|
|
|
|
1U_0402_6.3V4Z |
|
|
|
|
|
|
|
|
|
|
2 |
|
|
|
|
|
|
|
|
|
PM1@ |
C252 |
|
|
|
|
|
|
|
|
|
|
0_0402_5% |
|
|
3
4
A |
B |
|
|
U3E |
|
|
|
|
< Main IO power for PCI-E graphics, SB, and GPP interfaces > |
|
|
|
|
|
|
|
|
|
|
||||||||||||||||
|
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|
|
+VDDHT |
J17 |
VDDHT_1 |
PART 5/6 |
VDDPCIE_1 |
A6 |
+VDDA11PCIE |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
FBMA-L11-201209-221LMA30T_0805 1 |
2 L17 |
+1.1VS |
||||||||
|
K16 |
VDDHT_2 |
VDDPCIE_2 |
B6 |
VDDA_12=2.5A |
C220 |
|
C219 |
|
C222 |
|
C221 |
|
|
|
C224 |
|
C223 |
|
|
|
C211 |
|
C212 |
|
|
|
|
|
|
|
||
|
M16 |
VDDHT_3 |
|
|
VDDPCIE_3 |
D6 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||||||||
|
L16 |
|
|
|
|
C6 |
|
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|
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|
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|
|
P16 |
VDDHT_4 |
|
|
VDDPCIE_4 |
E6 |
|
|
1 |
|
1 |
|
1 |
|
1 |
|
|
|
2 |
|
2 |
|
|
|
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|
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|
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|
|
VDDHT_5 |
|
|
VDDPCIE_5 |
|
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|
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|
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|
||||||||
|
R16 |
VDDHT_6 |
|
|
VDDPCIE_6 |
F6 |
|
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|
|
T16 |
VDDHT_7 |
|
|
VDDPCIE_7 |
G7 |
|
|
|
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|
|
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|
|
|
|
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|
|
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|
|
|
+VDDHTRX |
|
|
|
|
VDDPCIE_8 |
H8 |
|
04021U 6.3V4Z |
2 |
04021U 6.3V4Z |
2 |
04021U 6.3V4Z |
2 |
04021U 6.3V4Z |
2 |
|
|
|
1 |
|
1 |
|
|
080510U 10V4Z |
|
080510U 10V4Z |
|
|
|
|
|
|
|
H18 |
VDDHTRX_1 |
|
|
J9 |
|
|
|
04020.1U16V7K |
04020.1U16V7K |
|
|
|
|
|
|
|
|
|
|
||||||||||||||
+VDDHTTX |
AE25 |
|
|
VDDPCIE_16 |
U9 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||||||||
|
G19 |
VDDHTRX_2 |
|
|
VDDPCIE_10 |
K9 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
F20 |
VDDHTRX_3 |
|
|
VDDPCIE_11 |
M9 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
E21 |
VDDHTRX_4 |
|
|
VDDPCIE_12 |
L9 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
D22 |
VDDHTRX_5 |
|
|
VDDPCIE_13 |
P9 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
B23 |
VDDHTRX_6 |
|
|
VDDPCIE_14 |
R9 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
A23 |
VDDHTRX_7 |
|
|
VDDPCIE_15 |
T9 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
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|
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|
|
|
|
|
|
|
|
V9 |
|
|
|
|
|
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|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AD24 |
VDDHTTX_1 |
|
|
VDDPCIE_17 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
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|
|
|
|
VDDHTTX_2 |
|
|
|
|
|
|
|
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|
|
|
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|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AC23 |
VDDHTTX_3 |
|
|
VDDC_1 |
K12 |
|
|
|
|
|
|
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AB22 |
VDDHTTX_4 |
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VDDC_2 |
J14 |
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+NB_CORE |
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AA21 |
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U16 |
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Y20 |
VDDHTTX_5 |
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VDDC_3 |
J11 |
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VDDHTTX_6 |
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VDDC_4 |
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W19 |
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POWER |
K15 |
< Core power > |
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VDD_CORE:GM=5A/PM=10A |
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PJP9 |
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+VDDA18PCIE |
J10 |
VDDHTTX_7 |
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VDDC_5 |
P11 |
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C247 |
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C240 |
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C241 |
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C242 |
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C243 |
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C230 |
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C231 |
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C244 |
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C232 |
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C233 |
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C245 |
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470U_D2E_2.5VM_R9M |
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VDDC_12 |
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V18 |
VDDHTTX_8 |
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VDDC_6 |
M12 |
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2 |
1 |
+1.1VS |
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U17 |
VDDHTTX_9 |
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VDDC_7 |
L14 |
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T17 |
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L11 |
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PAD-OPEN 4x4m |
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R17 |
VDDHTTX_10 |
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VDDC_8 |
M13 |
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VDDHTTX_11 |
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VDDC_9 |
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P17 |
VDDHTTX_12 |
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VDDC_10 |
M15 |
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1 |
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M17 |
VDDHTTX_13 |
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VDDC_11 |
N12 |
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2 |
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2 |
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2 |
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2 |
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2 |
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2 |
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2 |
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2 |
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2 |
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1 |
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1 |
+ |
C234 |
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N14 |
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T10 |
VDDA18PCIE_1 |
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VDDC_13 |
U12 |
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04020.1U16V7K |
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04020.1U16V7K |
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04020.1U16V7K |
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04020.1U16V7K |
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04020.1U16V7K |
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04020.1U16V7K |
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04020.1U16V7K |
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04020.1U16V7K |
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04020.1U16V7K |
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080510U10V4Z |
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080510U10V4Z |
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VDDA18PCIE_8 |
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VDDC_20 |
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1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
2 |
2 |
2 |
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P10 |
VDDA18PCIE_2 |
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VDDC_14 |
P13 |
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K10 |
VDDA18PCIE_3 |
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VDDC_15 |
P14 |
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DVT change to B size |
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M10 |
VDDA18PCIE_4 |
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VDDC_16 |
R12 |
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L10 |
VDDA18PCIE_5 |
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VDDC_17 |
R15 |
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W9 |
VDDA18PCIE_6 |
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VDDC_18 |
T11 |
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H9 |
VDDA18PCIE_7 |
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VDDC_19 |
T15 |
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R10 |
VDDA18PCIE_9 |
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VDDC_21 |
T14 |
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Y9 |
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J16 |
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VDDA18PCIE_10 |
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VDDC_22 |
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AA9 |
VDDA18PCIE_11 |
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AB9 |
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AE10 |
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VDDA18PCIE_12 |
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VDD_MEM1(NC) |
< Isolated power for side-port memory interface > |
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AD9 |
VDDA18PCIE_13 |
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VDD_MEM2(NC) |
AA11 |
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AE9 |
VDDA18PCIE_14 |
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VDD_MEM3(NC) |
Y11 |
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U10 |
VDDA18PCIE_15 |
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VDD_MEM4(NC) |
AD10 |
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VDD_MEM5(NC) |
AB10 |
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F9 |
VDD18_1 |
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VDD_MEM6(NC) |
AC10 |
< 3.3V IO power > |
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G9 |
VDD18_2 |
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AE11 |
VDD18_MEM1(NC) |
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VDD33_1(NC) |
H11 |
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+3VS |
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AD11 |
VDD18_MEM2(NC) |
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VDD33_2(NC) |
H12 |
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1 |
C250 |
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1 |
C253 |
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RS780MCR3@ |
RS780M_FCBGA528 |
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GM@ |
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GM@ |
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2 |
0.1U_0402_16V4Z |
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2 |
0.1U_0402_16V4Z |
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U3F |
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A25 |
VSSAHT1 |
PART 6/6 |
VSSAPCIE1 |
A2 |
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D23 |
VSSAHT2 |
VSSAPCIE2 |
B1 |
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E22 |
VSSAHT3 |
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VSSAPCIE3 |
D3 |
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G22 |
VSSAHT4 |
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VSSAPCIE4 |
D5 |
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G24 |
VSSAHT5 |
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VSSAPCIE5 |
E4 |
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G25 |
VSSAHT6 |
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VSSAPCIE6 |
G1 |
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H19 |
VSSAHT7 |
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VSSAPCIE7 |
G2 |
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J22 |
VSSAHT8 |
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VSSAPCIE8 |
G4 |
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L17 |
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H7 |
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VSSAHT9 |
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VSSAPCIE9 |
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L22 |
VSSAHT10 |
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VSSAPCIE10 |
J4 |
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L24 |
VSSAHT11 |
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VSSAPCIE11 |
R7 |
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L25 |
VSSAHT12 |
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VSSAPCIE12 |
L1 |
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M20 |
VSSAHT13 |
|
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VSSAPCIE13 |
L2 |
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N22 |
VSSAHT14 |
|
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VSSAPCIE14 |
L4 |
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P20 |
VSSAHT15 |
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VSSAPCIE15 |
L7 |
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R19 |
VSSAHT16 |
|
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VSSAPCIE16 |
M6 |
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R22 |
VSSAHT17 |
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VSSAPCIE17 |
N4 |
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R24 |
VSSAHT18 |
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VSSAPCIE18 |
P6 |
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R25 |
VSSAHT19 |
|
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VSSAPCIE19 |
R1 |
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H20 |
VSSAHT20 |
|
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VSSAPCIE20 |
R2 |
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U22 |
VSSAHT21 |
|
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VSSAPCIE21 |
R4 |
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V19 |
VSSAHT22 |
GROUND |
VSSAPCIE22 |
V7 |
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N13 |
VSS13 |
VSSAPCIE31 |
Y6 |
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||
|
W22 |
VSSAHT23 |
|
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VSSAPCIE23 |
U4 |
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W24 |
VSSAHT24 |
|
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VSSAPCIE24 |
V8 |
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W25 |
VSSAHT25 |
|
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VSSAPCIE25 |
V6 |
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Y21 |
VSSAHT26 |
|
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VSSAPCIE26 |
W1 |
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AD25 |
VSSAHT27 |
|
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VSSAPCIE27 |
W2 |
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VSSAPCIE28 |
W4 |
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L12 |
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W7 |
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VSS11 |
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VSSAPCIE29 |
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M14 |
VSS12 |
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VSSAPCIE30 |
W8 |
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P12 |
VSS14 |
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VSSAPCIE32 |
AA4 |
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P15 |
VSS15 |
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VSSAPCIE33 |
AB5 |
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R11 |
VSS16 |
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VSSAPCIE34 |
AB1 |
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R14 |
VSS17 |
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VSSAPCIE35 |
AB7 |
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T12 |
VSS18 |
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VSSAPCIE36 |
AC3 |
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U14 |
VSS19 |
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VSSAPCIE37 |
AC4 |
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U11 |
VSS20 |
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VSSAPCIE38 |
AE1 |
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U15 |
VSS21 |
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VSSAPCIE39 |
AE4 |
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V12 |
VSS22 |
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VSSAPCIE40 |
AB2 |
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W11 |
VSS23 |
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W15 |
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VSS24 |
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AC12 |
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AE14 |
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VSS25 |
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VSS1 |
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AA14 |
VSS26 |
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VSS2 |
D11 |
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Y18 |
VSS27 |
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VSS3 |
G8 |
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AB11 |
VSS28 |
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VSS4 |
E14 |
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AB15 |
VSS29 |
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VSS5 |
E15 |
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AB17 |
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J15 |
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VSS30 |
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VSS6 |
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AB19 |
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J12 |
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VSS31 |
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VSS7 |
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AE20 |
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K14 |
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VSS32 |
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VSS8 |
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AB21 |
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M11 |
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VSS33 |
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VSS9 |
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K11 |
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L15 |
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VSS34 |
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VSS10 |
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RS780M_FCBGA528 |
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RS780MCR3@ |
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/ Security Classification |
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Compal Secret Data |
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Compal Electronics, Inc. |
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||||
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|||
Issued Date |
2008-09-25 |
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Deciphered Date |
2009-09-25 |
Title |
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RS780M&RX781 PWR/GND |
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|||||
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL |
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||||||||
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D |
Size |
Document Number |
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Rev |
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Custom |
LA-4971P |
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1.0 |
||||||
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS |
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||||||
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. |
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Date: |
Wednesday, April 22, 2009 |
Sheet |
13 |
of |
45 |
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C |
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D |
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E |
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1
2
3
4
A |
B |
C |
D |
E |
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< RS780 DFT_GPIO5 mux at CRT_VSYNC pull High to 3K > |
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< DFT_GPIO5:STRAP_DEBUG_BUS_GPIO_ENABLEb > |
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SI2: Change to 3K pull high |
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Enables the Test Debug Bus using GPIO. |
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R101 |
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1 : Enable (RX780, RS780) |
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11,16 UMA_CRT_VSYNC |
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2 |
1 |
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3K_0402_5% |
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+3VS |
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0 : Disable (RX780, RS780) |
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1 |
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R102 |
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PIN: RS740-->RS780_AUX_CAL; RX780-->NB_TV_C; RS780--> VSYNC# |
1 |
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@ 2 |
1 |
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3K_0402_5% |
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< RS780 use register to control PCI-E configure > |
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< DFT_GPIO[4:2] : STRAP_PCIE_GPP_CFG[2:0] > |
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These pin straps are used to configure PCI-E GPP mode. |
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000 : 00001 |
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001 : 00010 |
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010 : 01011 |
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011 : 00100 |
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100 : 01010 |
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101 : 01100 |
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111 : 01011 |
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< RS780 DFT_GPIO1 > |
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< DFT_GPIO1 : LOAD_EEPROM_STRAPS > |
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Selects Loading of STRAPS from EPROM |
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R104 |
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11 AUX_CAL |
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@ 1 |
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2 |
150_0402_1% |
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1 : Bypass the loading of EEPROM straps and use Hardware Default Values |
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2 |
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0 : I2C Master can load strap values from EEPROM if connected, or use default values if not connected |
2 |
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D4 |
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RS740/RX780: DFT_GPIO1 RS780:SUS_STAT |
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@ |
2 |
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1 CH751H-40PT_SOD323-2 |
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||||||||||
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11,21 SUS_STAT# |
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PLT_RST# 11,19,20,26,27,33,34 |
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< RS780 use HSYNC to enable SIDE PORT (internal pull high) > |
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< DFT_GPIO0: STRAP_DEBUG_BUS_PCIE_ENABLEb > |
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||||||||||||||||||
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RX780: Enables the Test Debug Bus using PCIE bus |
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R125 |
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1 : Disable ( Can still be enabled using nbcfg register access ) |
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||
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11,16 UMA_CRT_HSYNC |
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2 |
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1 |
3K_0402_5% |
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+3VS |
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0 : Enable |
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RS780: Enables Side port memory ( RS780 use HSYNC#) |
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1. Disable (RS780) |
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0 : Enable (RS780) |
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3 |
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3 |
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4 |
4 |
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/ |
Security Classification |
|
Compal Secret Data |
|
|
|
Compal Electronics, Inc. |
|
|
||||
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|||||
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|
Issued Date |
2008-09-25 |
|
Deciphered Date |
2009-09-25 |
Title |
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|
RS780M&RX781 STRAPS |
|
|
|||||
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|
|
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL |
|
|
|
|
||||||||
|
|
|
|
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D |
Size |
Document Number |
|
|
|
|
Rev |
|||||
|
|
|
|
Custom |
LA-4971P |
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1.0 |
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DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS |
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MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. |
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Date: |
Wednesday, April 22, 2009 |
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14 |
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45 |
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A |
B |
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C |
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D |
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E |
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