Texas Instruments CD74HCT7046AM96, CD74HCT7046AM, CD74HCT7046AE, CD74HC7046AM96, CD74HC7046AM Datasheet

CD74HC7046A,

[ /Title
(CD74
HC704
6A,
CD74
HCT70
46A)
/Sub­ject
(Phase­Locked
Loop

Data sheet acquired from Harris Semiconductor
SCHS218

February 1998

Features

• Center Frequency of 18MHz (Typ) at VCC = 5V,
Minimum Center Frequency of 12MHz at V

• Choice of Two Phase Comparators

- Exclusive-OR

- Edge-Triggered JK Flip-Flop

• Excellent VCO Frequency Linearity

• VCO-Inhibit Control for ON/OFF Keying and for Low
Standby Power Consumption

• Minimal Frequency Drift

• Zero Voltage Offset Due to Op-Amp Buffer

• Operating Power-Supply Voltage Range

- VCO Section . . . . . . . . . . . . . . . . . . . . . . . . . . 3V to 6V

- Digital Section . . . . . . . . . . . . . . . . . . . . . . . . 2V to 6V

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range . . . -55

• Balanced Propagation Delay and Transition Times

• Significant Power Reduction Compared to LSTTL
Logic ICs

• HC Types

- 2V to 6V Operation

- High Noise Immunity: N

at VCC = 5V

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

V

= 0.8V (Max), VIH = 2V (Min)

IL

- CMOS Input Compatibility, I

= 30%, NIH = 30% of V

IL

≤ 1µA at VOL, V

l

CC = 4.5V

o

C to 125oC

OH

CD74HCT7046A

Phase-Locked Loop

with VCO and Lock Detector

Description

The Harris CD74HC7046A and CD74HCT7046A high-speed
silicon-gate CMOS devices, specified in compliance with
JEDEC Standard No. 7A, are phase-locked-loop (PLL)
circuits that contain a linear voltage-controlled oscillator
(VCO), two-phase comparators (PC1, PC2), and a lock
detector. A signal input and a comparator input are common
to each comparator. The lock detector gives a HIGH level at
pin 1 (LD) when the PLL is locked. The lock detector
capacitor must be connected between pin 15 (C
8 (Gnd). For a frequency range of 100kHz to 10MHz, the
lock detector capacitor should be 1000pF to 10pF,
respectively.

The signal input can be directly coupled to large voltage
signals, or indirectly coupled (with a series capacitor) to
small voltage signals. A self-bias input circuit keeps small
voltage signals within the linear region of the input amplifiers.
With a passive low-pass filter, the 7046A forms a second­order loop PLL. The excellent VCO linearity is achieved by
the use of linear op-amp techniques.

Ordering Information

TEMP. RANGE

CC

PART NUMBER

CD74HC7046AE -55 to 125 16 Ld PDIP E16.3
CD74HCT7046AE -55 to 125 16 Ld PDIP E16.3
CD74HC7046AM -55 to 125 16 Ld SOIC M16.15
CD74HCT7046AM -55 to 125 16 Ld SOIC M16.15

NOTES:

1. When ordering, use the entire partnumber. Add the suffix 96 to
obtain the variant in the tape and reel.

2. Wafer and die for this part number is available which meets all
electrical specifications. Please contact your local sales office or
Harris customer service for ordering information.

(oC) PACKAGE PKG. NO.

) and pin

LD

Applications

• FM Modulation and Demodulation

• Frequency Synthesis and Multiplication

• Frequency Discrimination

• Tone Decoding

• Data Synchronization and Conditioning

• Voltage-to-Frequency Conversion

• Motor-Speed Control

• Related Literature

- AN8823, CMOS Phase-Locked-Loop Application
Using the CD74HC/HCT7046A and
CD74HC/HCT7046A

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright

© Harris Corporation 1998

1

File Number 1920.1

CD74HC7046A, CD74HCT7046A

Pinout

CD74HC7046A, CD74HCT7046A

(PDIP, SOIC)

TOP VIEW

PC1
COMP

VCO

LD

OUT

OUT

INH
C1
C1

GND

1
2
3

IN

4
5
6

A

7

B

8

674314

C1

A

C1

C1

16
15
14
13
12
11
10

9

B

VCO

V
C
SIG
PC2
R
R
DEM
VCO

OUT

CC
LD

2
1

IN

OUT

OUT

IN

COMP

Functional Diagram

2
15
13
1

4

10

OUT

PC1
C

LD

PC2
LD

VCO

DEM

2

OUT

OUT

OUT

OUT

C1
C1

INH

3

IN

14

IN

A
B

11

R

1

12

R

2

IN

φ

6
7

VCO
9
5

PC1

COMP

SIG

VCO

SIG

IN

IN

R2

R1

R5

V

REF

R2

12

R1

11

OUT

10

DEM

+

-

-

+

VCO

-

+

INH
59

VCO

IN

LOCK DETECTOR

CC

V

V

CC

D

CP

D

CP

UP

Q

Q

R

D

Q

DOWN

Q

R

D

1.5K

150Ω

PC2

OUT

V

CC

GND

p

n

LOCK
DETECTOR

1

OUTPUT

15

C
LOCK
DETECTOR
CAPACITOR

13

LD

R3

C2

FIGURE 1. LOGIC DIAGRAM

2

CD74HC7046A, CD74HCT7046A

Pin Descriptions

PIN NO. SYMBOL NAME AND FUNCTION

1 LD Lock Detector Output (Active High)
2 PC1
3 COMP
4 VCO
5 INH Inhibit Input
6C1
7C1
8 Gnd Ground (0V)

9 VCO
10 DEM
11 R
12 R
13 PC2
14 SIG
15 C
16 V

CC

Phase Comparator 1 Output

OUT

Comparator Input

IN

VCO Output

OUT

Capacitor C1 Connection A

A

Capacitor C1 Connection B

B

VCO Input

IN

Demodulator Output

OUT

Resistor R1 Connection

1

Resistor R2 Connection

2

Phase Comparator 2 Output

OUT

Signal Input

IN

Lock Detector Capacitor Input

LD

Positive Supply Voltage

General Description

VCO

The VCO requires one external capacitor C1 (between C1
and C1B) and one external resistor R1 (between R1 and
Gnd) or two external resistors R1 and R2 (between R1 and
Gnd, and R2 and Gnd). Resistor R1 and capacitor C1 deter­mine the frequency range of the VCO. Resistor R2 enables
the VCO to have a frequency offset if required. See logic dia­gram, Figure 1.

The high input impedance of the VCO simplifies the design
of low-pass filters by giving the designer a wide choice of
resistor/capacitor ranges. In order not to load the low-pass
filter, a demodulator output of the VCO input voltage is pro­vided at pin 10 (DEM
niques where the DEM
lower than the VCO input voltage, here the DEM
equals that of the VCO input. If DEM
resistor (R
unused, DEM
(VCO
input (COMP

) should be connected from DEM

S

OUT

) can be connected directly to the comparator

OUT

), or connected via a frequency-divider. The

IN

VCO output signal has a guaranteed duty factor of 50%. A
LOW level at the inhibit input (INH) enables the VCO, while a
HIGH level disables the VCO to minimize standby power
consumption.

Phase Comparators

The signal input (SIG
biasing amplifier at pin 14, provided that the signal swing is
between the standard HC family input logic levels, Capaci­tive coupling is required for signals with smaller swings.

). In contrast to conventional tech-

OUT

voltage is one threshold voltage

OUT

is used, a load

OUT

OUT

OUT

to Gnd; if

voltage

should be left open. The VCO output

) can be directly coupled to the self-

IN

Phase Comparator 1 (PC1)

This is an Exclusive-OR network. The signal and comparator
input frequencies (f

) must have a 50% duty factor to obtain

i

the maximum locking range. The transfer characteristic of
PC1, assuming ripple (f

V

DEMOUT

=(VCC/π)(φ

is the demodulator output at pin 10; V

= 2fi) is suppressed, is:

r

SIGIN

- φ

COMPIN

) where V

DEMOUT=VPC1OUT

(via low-pass filter).
The average output voltage from PC1, fed to the VCO input

via the low-pass filter and seen at the demodulator output at
pin 10 (V

DEMOUT

of signals (SIG
shown in Figure 2. The average of V

), is the resultant of the phase differences

) and the comparator input (COMPIN)as

IN

is equal to 1/2 V

DEM

when there is no signal or noise at SIGIN, and with this input
the VCO oscillates at the center frequency (f
forms for the PC1 loop locked at f

The frequency capture range (2f

shown in Figure 3.

o

) is defined as the fre-

c

). Typical wave-

o

quency range of input signals on which the PLL will lock if it
was initially out-of-lock. The frequency lock range (2f
defined as the frequency range of input signals on which the
loop will stay locked if it was initially in lock. The capture
range is smaller or equal to the lock range.

With PC1, the capture range depends on the low-pass filter
characteristics and can be made as large as the lock range.
This configuration retains lock behavior even with very noisy
input signals. Typical of this type of phase comparator is that
it can lock to input frequencies close to the harmonics of the
VCO center frequency.

A

Phase Comparator 2 (PC2)

This is a positive edge-triggered phase and frequency detec­tor. When the PLL is using this comparator, the loop is con­trolled by positive signal transitions and the duty factors of
SIGIN and COMP

are not important. PC2 comprises two

IN

D-type flip-flops, control-gating and a three-state output
stage. The circuit functions as an up-down counter (Figure

1) where SIG

causes an up-count and COMPINa down-

IN

count. The transfer function of PC2, assuming ripple (f
is suppressed, is:

V

DEMOUT

is the demodulator output at pin 10; V

=(VCC/4π)(φ

SIGN

- φ

COMPIN

) where V

DEMOUT=VPC2OUT

(via low-pass filter).
The average output voltage from PC2, fed to the VCO via the

low-pass filter and seen at the demodulator output at pin 10
(V

DEMOUT

SIG
for the PC2 loop locked at f

When the frequencies of SIG
the phase of SIG
driver at PC2
the phase differences (φ

), is the resultant of the phase differences of

and COMPINas shown in Figure 4. Typical waveforms

IN

leads that of COMPIN, the p-type output

IN

is held “ON” for a time corresponding to

OUT

are shown in Figure 5.

o

and COMPINare equal but

IN

DEMOUT

). When the phase of SIG

lags that of COMPIN, the n-type driver is held “ON”.
When the frequency of SIG

is higher than that of COMPIN,

IN

the p-type output driver is held “ON” for most of the input sig­nal cycle time, and for the remainder of the cycle both n-type
and p-type drivers are “OFF” (three-state). If the SIG

DEMOUT

CC

)is

L

r=fi

DEMOUT

IN

fre-

IN

)

3

CD74HC7046A, CD74HCT7046A

quency is lower than the COMP

frequency, then it is the n-

IN

type driver that is held “ON” for most of the cycle. Subse­quently, the voltage at the capacitor (C2) of the low-pass filter
connected to PC2

varies until the signal and comparator

OUT

inputs are equal in both phase and frequency . At this stable
point the voltage on C2 remains constant as the PC2 output is
in three-state and the VCO input at pin 9 is a high impedance.

Thus, for PC2, no phase difference exists between SIG

IN

and COMPINover the full frequency range of the VCO.
Moreover, the power dissipation due to the low-pass filter is
reduced because both p-type and n-type drivers are “OFF”
for most of the signal input cycle. It should be noted that the
PLL lock range for this type of phase comparator is equal to
the capture range and is independent of the low-pass filter.
With no signal present at SIG

, the VCO adjusts, via PC2,

IN

to its lowest frequency.

Lock Detector Theory of Operation

Detection of a locked condition is accomplished by a NOR
gate and an envelope detector as shown in Figure 6. When
the PLL is in Lock, the output of the NOR gate is High and
the lock detector output (Pin 1) is at a constant high level. As
the loop tracks the signal on Pin 14 (signal in), the NOR gate
outputs pulses whose widths represent the phase differ­ences between the VCO and the input signal. The time
between pulses will be approximately equal to the time con­stant of the VCO center frequency. During the rise time of
the pulse, the diode across the 1.5kΩ resistor is forward

biased and the time constant in the path that charges the
lock detector capacitor is T = (150Ω x C

LD

).

During the fall time of the pulse the capacitor discharges
through the 1.5kΩ and the 150Ω resistors and the channel
resistance of the n-device of the NOR gate to ground
(T = (1.5kΩ + 150Ω + Rn-channel) x C

LD

).

The waveform preset at the capacitor resembles a sawtooth
as shown in Figure 7. The lock detector capacitor value is
determined by the VCO center frequency. The typical range
of capacitor for a frequency of 10MHz is about 10pF and for
a frequency of 100kHz is about 1000pF. The chart in Figure
8 can be used to select the proper lock detector capacitor
value. As long as the loop remains locked and tracking, the
level of the sawtooth will not go below the switching thresh­old of the Schmitt-trigger inverter. If the loop breaks lock, the
width of the error pulse will be wide enough to allow the saw­tooth waveform to go below threshold and a level change at
the output of the Schmitt trigger will indicate a loss of lock,
as shown in Figure 9. The lock detector capacitor also acts
to filter out small glitches that can occur when the loop is
either seeking or losing lock.

Note: When using phase comparator 1, the detector will only
indicate a lock condition on the fundamental frequency and
not on the harmonics, which PC1 will also lock on. If a detec­tion of lock is needed over the harmonic locking range of
PC1, then the lock detector output must be OR-ed with the
output of PC1.

V

CC

V

DEMOUT (AV)

1/2 V

CC

0

o

0

FIGURE 2. PHASE COMPARATOR 1: AVERAGE OUTPUT

VOLTAGE vs INPUT PHASE DIFFERENCE:
V

DEMOUT

PIN

); φ

= V

DEMOUT

PC1OUT

= (φ

o

90

= (VCC/π) (φ

- φ

SIGIN

φ

DEMOUT

COMPIN

SIGIN

)

- φ

COM-

180

SIG

IN

COMP

IN

VCO

OUT

PC1

OUT

VCO

IN

o

FIGURE 3. TYPICAL WAVEFORMS FOR PLL USING PHASE

COMPARATOR 1, LOOP LOCKED AT f

V

CC

GND

o

4

V

DEMOUT (AV)

1/2 V

CD74HC7046A, CD74HCT7046A

V

CC

SIG

IN

COMP

IN

VCO

OUT

V

CC

PC2

VCO

OUT

HIGH IMPEDANCE OFF - STATE

IN

CC

GND

0

-360

o

o

φ

0

DEMOUT

FIGURE 4. PHASE COMPARATOR 2: AVERAGE OUTPUT

VOLTAGE vs INPUT PHASE DIFFERENCE:
V

DEMOUT

PIN

); φ

= V

DEMOUT

COMP

PC2OUT

= (φ

SIG

IN

IN

= (VCC/π) (φ

- φ

SIGIN

UP
FF

DN

FF

- φ

SIGIN

COMPIN

7046 LOCK DETECTOR CIRCUITRY

COM-

)

PHASE DIFFERENCE

o

360

1.5kΩ 150Ω

PIN 15

PCP

OUT

FIGURE 5. TYPICAL WAVEFORMS FOR PLL USING PHASE

COMPARATOR 2, LOOP LOCKED AT f

PIN 1

LOCK DETECTOR
OUTPUT

C

LD

LOCK DETECTOR
CAPACITOR

o

FIGURE 6. CD74HC/HCT7046A LOCK DETECTOR CIRCUIT

1.5kΩ 150Ω

PIN 15

LOCK

DETECTOR

CAPACITOR

PIN 1

C

LD

V

DETECTOR

CAP

LOCK

OUTPUT

V

TH

FIGURE 7. WAVEFORM PRESENT AT LOCK DETECTOR CAPACITOR WHEN IN LOCK

5

CD74HC7046A, CD74HCT7046A

10M

1M

100K

10K

1K

100

10

LOCK DETECTOR CAPACITOR VALUE (pF)

10 100 1K 10K 100K 1M 10M 100M

f, VCO CENTER FREQUENCY (HZ)

FIGURE 8. LOCK DETECTOR CAPACITOR SELECTION CHART

LOSS OF LOCK

1.5kΩ 150Ω

PIN 15

LOCK

DETECTOR

CAPACITOR

PIN 1

C

LD

LOCK

DETECTOR

OUTPUT

V

CAP

V

TH

FIGURE 9. WAVEFORM PRESENT AT LOCK DETECTOR CAPACITOR WHEN UNLOCKED

6

CD74HC7046A, CD74HCT7046A

Absolute Maximum Ratings Thermal Information

DC Supply Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V

DC Input Diode Current, I

IK

For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Diode Current, I

OK

For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Source or Sink Current per Output Pin, I

O

For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA

DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA

Operating Conditions

Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC

Supply Voltage Range, V

HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V

HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V

DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to V

Input Rise and Fall Time

2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)

4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)

6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

3. θJA is measured with the component mounted on an evaluation PC board in free air.

CC

Thermal Resistance (Typical, Note 3) θJA (oC/W)

PDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160

Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . 150oC

Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC

Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC

(SOIC - Lead Tips Only)

CC

DC Electrical Specifications

PARAMETER SYMBOL
HC TYPES
VCO SECTION

INH High Level Input
Voltage

INH Low Level Input
Voltage

VCO

High Level

OUT

Output Voltage
CMOS Loads

VCO

High Level

OUT

Output Voltage
TTL Loads

VCO

OUT

Low Level
Output Voltage
CMOS Loads

VCO

OUT

Low Level
Output Voltage
TTL Loads

C1A, C1B Low Level
Output Voltage
(Test Purposes Only)

V

IH

V

IL

V

OH

V

OL

V

OL

TEST

CONDITIONS

(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

I

V

CC

(V)

o

C -40oC TO 85oC -55oCTO125oC

25

UNITSV

- - 3 2.1 - - 2.1 - 2.1 - V

4.5 3.15 - - 3.15 - 3.15 - V
6 4.2 - - 4.2 - 4.2 - V

- - 3 - - 0.9 - 0.9 - 0.9 V

4.5 - - 1.35 - 1.35 - 1.35 V
6 - - 1.8 - 1.8 - 1.8 V

VIHor VIL-0.02 3 2.9 - - 2.9 - 2.9 - V

-0.02 4.5 4.4 - - 4.4 - 4.4 - V

-0.02 6 5.9 - - 5.9 - 5.9 - V

- - ---- - - - V

-4 4.5 3.98 - - 3.84 - 3.7 - V

-5.2 6 5.48 - - 5.34 - 5.2 - V

VIHor VIL0.02 2 - - 0.1 - 0.1 - 0.1 V

0.02 4.5 - - 0.1 - 0.1 - 0.1 V

0.02 6 - - 0.1 - 0.1 - 0.1 V

- - ---- - - - V
4 4.5 - - 0.26 - 0.33 - 0.4 V

5.2 6 - - 0.26 - 0.33 - 0.4 V

VIL or

V

OL

4 4.5 - - 0.40 - 0.47 - 0.54 V

5.2 6 - - 0.40 - 0.47 - 0.54 V

7