Siemens SAB-C515-1R24M, SAB-C515-1RM, SAB-C515-L24M, SAB-C515-LM, SAF-C515-1R24M Datasheet

Microcomputer Components

8-Bit CMOS Microcontroller

C515

Data Sheet 08.97

C515 Data Sheet
Revision History: Current Version: 1997-08-01

Previous Version: none (Original Version)
Page

(in previous
Version)

Page
(in current
Version)

Subjects (major changes since last revision)

Edition 1997-08-01
Published by Siemens AG,

Bereich Halbleiter, Marketing­Kommunikation, Balanstraße 73,
81541 München

©

Siemens AG 1997.

All Rights Reserved.

Attention please!

As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes
and circuits implemented within components or assemblies.

The information describes the type of component and shall not be considered as assured characteristics.
Terms of delivery and rights to change design reserved.
For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or the Siemens Companies

and Representatives worldwide (see address list).
Due to technical requirements components may contain dangerous substances. For information on the types in question please contact

your nearest Siemens Office, Semiconductor Group.
Siemens AG is an approved CECC manufacturer.

Packing

Please use the recycling operators known to you. We can also help you – get in touch with your nearest sales office. By agreement we
will take packing material back, if it is sorted. You must bear the costs of transport.

For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs in­curred.

Components used in life-support devices or systems must be expressly authorized for such purpose!

Critical components
written approval of the Semiconductor Group of Siemens AG.

1 A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the

failure of that life-support device or system, or to affect its safety or effectiveness of that device or system.

2 Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain hu-

man life. If they fail, it is reasonable to assume that the health of the user may be endangered.

1

of the Semiconductor Group of Siemens AG, may only be used in life-support devices or systems

2

with the express

8-Bit CMOS Microcontroller

Advance Information

Data Sheet

Full upward compatibility with SAB 80C515

•

Up to 24 MHz external operating frequency

•

– 500ns instruction cycle at 24 MHz operation
8K byte on-chip ROM (with optional ROM protection)

•

– alternatively up to 64K byte external program memory
Up to 64K byte external data memory

•

256 byte on-chip RAM

•

Six 8-bit parallel I/O ports

•

One input port for analog/digital input

•

Full duplex serial interface (USART)

•

– 4 operating modes, fixed or variable baud rates
Three 16-bit timer/counters

•

– Timer 0 / 1 (C501 compatible)
– Timer 2 for 16-bit reload, compare, or capture functions

C515

(more features on next page)

Power
Saving
Modes

8-Bit

A/D

Converter

On-Chip Emulation Support Module

Digital

Input

Watchdog

Port6Port 5 Port 4

I/O I/OAnalog/

Timer

T2

T0

T1

RAM

256 x 8

CPU

ROM

K8x8

USART

Port 0

Port 1

Port 2

Port 3

I/O

I/O

I/O

I/O

MCA03198

Figure 1
C515 Functional Units

Semiconductor Group 3 1997-08-01

Features (cont’d):

•

8-bit A/D converter
– 8 multiplexed analog inputs
– Programmable reference voltages

•

16-bit watchdog timer

•

Power saving modes
– Idle mode
– Slow down mode (can be combined with idle mode)
– Software power-down mode

•

12 interrupt sources (7 external, 5 internal) selectable at four priority levels

•

On-chip emulation support logic (Enhanced Hooks Technology

•

ALE switch-off capability

•

P-MQFP-80-1 package

•

Temperature Ranges : SAB-C515

SAF-C515
SAH-C515

T

= 0 to 70 ° C

A

T

= -40 to 85 ° C

A

T

= -40 to 110 ° C (max. operating frequency: 16 MHz)

A

TM

)

C515

The C515 is an upward compatible version of the SAB 80C515A 8-bit microcontroller which
additionally provides ALE switch-off capability, on-chip emulation support, ROM protection, and
slow down mode capability. With a maximum external clock rate of 24 MHz it achieves a 500 ns
instruction cycle time (1

Ordering Information
Type Ordering Code Package Description

SAB-C515-1RM
SAB-C515-1R24M

SAF-C515-1RM Q67127-DXXXX P-MQFP-80-1 with mask programmable ROM (16 MHz)

SAF-C515-1R24M Q67127-DXXXX P-MQFP-80-1 with mask programmable ROM (24 MHz)

SAB-C515-LM
SAB-C515-L24M

SAF-C515-LM Q67127-C1031 P-MQFP-80-1 for external memory (16 MHz)

µ

s at 12 MHz). The C515 is mounted in a P-MQFP-80 package.

(8-Bit CMOS microcontroller)

Q67127-DXXXX
Q67127-DXXXX

Q67127-C1030
Q67127-C1032

P-MQFP-80-1
P-MQFP-80-1

P-MQFP-80-1
P-MQFP-80-1

with mask programmable ROM (16 MHz)
with mask programmable ROM (24 MHz)

ext. temp. – 40 ˚C to 85 ˚C

ext. temp. – 40 ˚C to 85 ˚C
for external memory (16 MHz)

for external memory (24 MHz

ext. temp. – 40 ˚C to 85 ˚C

SAF-C515-L24M Q67127-C1081 P-MQFP-80-1 for external memory (24 MHz)

ext. temp. – 40 ˚C to 85 ˚C

Note: Versions for extended temperature ranges – 40 ˚C to 110 ˚C (SAH-C515C-LM and SAH-

C515-1RM) are available on request. The ordering number of ROM types (DXXXX
extensions) is defined after program release (verification) of the customer.

Semiconductor Group 4 1997-08-01

C515

XTAL1
XTAL2

ALE
PSEN
EA

RESET
PE

V

AREF

V

AGND

V

C515

V

SSCC

Port 0
8 Bit Digital I/O

1Port

8 Bit Digital I/O
Port 2

8 Bit Digital I/O
Port 3

8 Bit Digital I/O

4Port

8 Bit Digital I/O
Port 5

8 Bit Digital I/O

6Port
8 Bit Analog/
Digital Input

MCL03199

Figure 2
Logic Symbol

Additional Literature

For further information about the C515 the following literature is available:

Title Ordering Number

C515 8-Bit CMOS Microcontroller User’s Manual B158-H7049-X-X-7600
C500 Microcontroller Family

B158-H6987-X-X-7600

Architecture and Instruction Set User’s Manual
C500 Microcontroller Family - Pocket Guide B158-H6986-X-X-7600

Semiconductor Group 5 1997-08-01

P0.7/AD7

P0.6/AD6

P5.7

P0.5/AD5

P0.4/AD4

P0.3/AD3

P0.2/AD2

P0.1/AD1

P0.0/AD0EAALE

N.C.

N.C.

PSEN

N.C.

P2.7/A15

P2.6/A14

P2.5/A13

P2.4/A12

P2.3/A11

4142434445464748495051525354555657585960

C515

P5.6
P5.5
P5.4
P5.3
P5.2
P5.1
P5.0
N.C.

V

CC

N.C.
N.C.
P4.0

P4.1

P4.2

PE
P4.3
P4.4
P4.5
P4.6
P4.7

62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80

12

345

4061
39
38
37
36
35
34
33
32

C515

31
30
29
28
27
26
25
24
23
22
21

6

7

8

9

10

11

12

13 14 15

16

17

18

19

20

P2.2/A10
P2.1/A9
P2.0/A8
XTAL1
XTAL2
N.C.

V

SS

V

CC

N.C.
P1.0/INT3/CC0
P1.1/INT4/CC1
P1.2/INT5/CC2
P1.3/INT6/CC3
P1.4/INT2
P1.5/T2EX
P1.6/CLKOUT
P1.7/T2
N.C.
P3.7/RD
P3.6/WR

AREF

N.C.

V

RESET

AGND

V

P6.7/AIN7

P6.5/AIN5

P6.6/AIN6

P6.3/AIN3

P6.4/AIN4

P6.2/AIN2

N.C.

N.C.

P6.0/AIN0

P6.1/AIN1

P3.1/TXD

P3.0/RXD

Figure 3
C515 Pin Configuration (P-MQFP-80 Package, Top View)

P3.4/T0

P3.2/INT0

P3.5/T1

P3.3/INT1

MCP03200

Semiconductor Group 6 1997-08-01

Table 1
Pin Definitions and Functions

C515

Symbol Pin Number

(P-MQFP-80)

RESET

1I

VAREF 3 –
VAGND 4 –
P6.0-P6.7 12-5 I

*) I = Input

O = Output

I/O*) Function

RESET

A low level on this pin for the duration of two machine
cycles while the oscillator is running resets the C515. A
small internal pullup resistor permits power-on reset
using only a capacitor connected to V

Reference voltage for the A/D converter
Reference ground for the A/D converter
Port 6

is an 8-bit unidirectional input port to the A/D converter.
Port pins can be used for digital input, if voltage levels
simultaneously meet the specifications for high/low input
voltages and for the eight multiplexed analog inputs.

SS

.

Semiconductor Group 7 1997-08-01

Table 1
Pin Definitions and Functions (cont’d)

C515

Symbol Pin Number

(P-MQFP-80)

P3.0-P3.7 15-22

15

16

17

18

19
20
21

22

I/O*) Function

I/O Port 3

is an 8-bit quasi-bidirectional I/O port with internal pullup
resistors. Port 3 pins that have 1's written to them are
pulled high by the internal pullup resistors, and in that
state can be used as inputs. As inputs, port 3 pins being
externally pulled low will source current ( I
characteristics) because of the internal pullup resistors.
Port 3 also contains the interrupt, timer, serial port and
external memory strobe pins that are used by various
options. The output latch corresponding to a secondary
function must be programmed to a one (1) for that
function to operate. The secondary functions are
assigned to the pins of port 3 as follows:
P3.0 / RxD Receiver data input (asynch.) or data

P3.1 / TxD Transmitter data output (asynch.) or

P3.2 / INT0

P3.3 / INT1 External interrupt 1 input /

P3.4 / T0 Timer 0 counter input
P3.5 / T1 Timer 1 counter input
P3.6 / WR

P3.7 / RD RD control output; enables the

, in the DC

IL

input/output (synch.) of serial interface

clock output (synch.) of serial interface
External interrupt 0 input /
timer 0 gate control input

timer 1 gate control input

WR control output; latches the data byte
from port 0 into the external data
memory

external data memory

*) I = Input

O = Output

Semiconductor Group 8 1997-08-01

Table 1
Pin Definitions and Functions (cont’d)

C515

Symbol Pin Number

(P-MQFP-80)

P1.0 - P1.7 31-24

31

30

29

28

27
26

25
24

I/O*) Function

I/O Port 1

is an 8-bit quasi-bidirectional I/O port with internal pullup
resistors. Port 1 pins that have 1's written to them are
pulled high by the internal pullup resistors, and in that
state can be used as inputs. As inputs, port 1 pins being
externally pulled low will source current ( I
characteristics) because of the internal pullup resistors.
The port is used for the low-order address byte during
program verification. Port 1 also contains the interrupt,
timer, clock, capture and compare pins that are used by
various options. The output latch corresponding to a
secondary function must be programmed to a one (1) for
that function to operate (except when used for the
compare functions). The secondary functions are
assigned to the port 1 pins as follows :
P1.0 / INT3 /

P1.1 / INT4 /CC1 Interrupt 4 input /

P1.2 / INT5 /CC2 Interrupt 5 input /

P1.3 / INT6 /CC3 Interrupt 6 input /

P1.4 / INT2
P1.5 / T2EX Timer 2 external reload /

P1.6 / CLKOUT System clock output
P1.7 / T2 Counter 2 input

CC0 Interrupt 3 input /

compare 0 output /
capture 0 input

compare 1 output /
capture 1 input

compare 2 output /
capture 2 input

compare 3 output /
capture 3 input
Interrupt 2 input

trigger input

, in the DC

IL

V

SS

V

CC

34 –
33, 69 –

Ground (0 V)
Supply voltage

during normal, idle, and power-down operation.

*) I = Input

O = Output

Semiconductor Group 9 1997-08-01

Table 1
Pin Definitions and Functions (cont’d)

C515

Symbol Pin Number

(P-MQFP-80)

XTAL2 36 –

XTAL1 37 – XTAL1

P2.0-P2.7 38-45 I/O Port 2

I/O*) Function

XTAL2

Input to the inverting oscillator amplifier and input to the
internal clock generator circuits.
To drive the device from an external clock source,
XTAL2 should be driven, while XTAL1 is left
unconnected.
times as well as rise/fall times specified in the AC
characteristics must be observed.

Output of the inverting oscillator amplifier.

is an 8-bit quasi-bidirectional I/O port with internal pullup
resistors. Port 2 pins that have 1's written to them are
pulled high by the internal pullup resistors, and in that
state can be used as inputs. As inputs, port 2 pins being
externally pulled low will source current (I
characteristics) because of the internal pullup resistors.
Port 2 emits the high-order address byte during fetches
from external program memory and during accesses to
external data memory that use 16-bit addresses
(MOVX @DPTR). In this application it uses strong
internal pullup resistors when issuing 1's. During
accesses to external data memory that use 8-bit
addresses (MOVX @Ri), port 2 issues the contents of
the P2 special function register.

Minimum and maximum high and low

, in the DC

IL

PSEN

ALE 48 O The Address Latch enable

*) I = Input

O = Output

Semiconductor Group 10 1997-08-01

47 O The Program Store Enable

output is a control signal that enables the external
program memory to the bus during external fetch
operations. It is activated every six oscillator periods,
except during external data memory accesses. The
signal remains high during internal program execution.

output is used for latching the address into external
memory during normal operation. It is activated every six
oscillator periods, except during an external data
memory access.

Table 1
Pin Definitions and Functions (cont’d)

C515

Symbol Pin Number

I/O*) Function

(P-MQFP-80)

EA 49 I External Access Enable

When held high, the C515 executes instructions from
the internal ROM (C515-1R) as long as the program
counter is less than 2000H. When held low, the C515
fetches all instructions from ext. program memory. For
the C515-L this pin must be tied low.

P0.0-P0.7 52-59 I/O Port 0

is an 8-bit open-drain bidirectional I/O port. Port 0 pins
that have 1's written to them float, and in that state can
be used as high-impedance inputs. Port 0 is also the
multiplexed low-order address and data bus during
accesses to external program and data memory. In this
application it uses strong internal pullup resistors when
issuing 1's. Port 0 also outputs the code bytes during
program verification in the C515-1R. External pullup
resistors are required during program verification.

P5.ß-P5.7 67-60 I/O Port 5

is an 8-bit quasi-bidirectional I/O port with internal pullup
resistors. Port 5 pins that have 1's written to them are
pulled high by the internal pullup resistors, and in that
state can be used as inputs. As inputs, port 5 pins being
externally pulled low will source current (I
characteristics) because of the internal pullup resistors.

, in the DC

IL

P4.0-P4.7 72-74,

76-80

I/O Port 4

is an 8-bit quasi-bidirectional I/O port with internal pull­up resistors. Port 4 pins that have 1’s written to them are
pulled high by the internal pull-up resistors, and in that
state can be used as inputs. As inputs, port 4 pins being
externally pulled low will source current (I

, in the DC

IL

characteristics) because of the internal pull-up resistors.

PE

75 I Power saving mode enable

A low level on this pin allows the software to enter the
power saving modes (idle mode and power down
mode). When PE is held at high level it is impossible to
enter the power saving modes. When left unconnected
this pin is pulled high by a weak internal pull-up resistor.

*) I = Input

O = Output

Semiconductor Group 11 1997-08-01

Table 1
Pin Definitions and Functions (cont’d)

C515

Symbol Pin Number

(P-MQFP-80)

N.C. 2, 13, 14, 23,

32, 35, 46, 50,
51, 68, 70, 71

*) I = Input

O = Output

I/O*) Function

– Not connected

These pins of the P-MQFP-80 package must not be
connected.

Semiconductor Group 12 1997-08-01

XTAL1
XTAL2

ALE

C515

OSC & Timing

RAM ROM

256 x 8

8K x 8

C515

PSEN
EA
PE
RESET

V

AREF

V

AGND

CPU

Programmable

Watchdog Timer

Timer 0

Timer 1

Timer 2

USART

Baud Rate Generator

Interrupt Unit

Programmable

Reference Voltages

8-Bit

A/D Converter

Emulation

Support

Logic

Port 0

Port 1

Port 2

Port 3

Port 4

Port 5

Port 0
8 Bit Digital I/O

Port 1
8 Bit Digital I/O

Port 2
8 Bit Digital I/O

Port 3
8 Bit Digital I/O

Port 4
8 Bit Digital I/O

Port 5
8 Bit Digital I/O

Port 6

S & H

Analog

MUX

Port 6

MCB03201

8 Bit Digital I/O

Digital Input

Figure 4
Block Diagram of the C515C

Semiconductor Group 13 1997-08-01

C515

CPU

The C515 is efficient both as a controller and as an arithmetic processor. It has extensive facilities
for binary and BCD arithmetic and excels in its bit-handling capabilities. Efficient use of program
memory results from an instruction set consisting of 44 % one-byte, 41 % two-byte, and 15% three­byte instructions. With a 6 MHz crystal, 58% of the instructions are executed in 1.0µs (10 MHz: 600).

Special Function Register PSW (Address D0H) Reset Value : 00H

Bit No. MSB LSB

H

D7

CY AC

H

D6

H

D5

F0

H

D4

RS1 RS0 OV F1 PD0

Bit Function

CY Carry Flag

Used by arithmetic instruction.

AC Auxiliary Carry Flag

Used by instructions which execute BCD operations.
F0 General Purpose Flag
RS1

RS0

Register Bank select control bits

These bits are used to select one of the four register banks.

RS1 RS0 Function

0 0 Bank 0 selected, data address 00H-07
0 1 Bank 1 selected, data address 08H-0F
1 0 Bank 2 selected, data address 10H-17
1 1 Bank 3 selected, data address 18H-1F

H

D3

H

D2

H

D1

H

D0

H

PSW

H

H

H

H

OV Overflow Flag

Used by arithmetic instruction.
F1 General Purpose Flag
P Parity Flag

Set/cleared by hardware after each instruction to indicate an odd/even

number of "one" bits in the accumulator, i.e. even parity.

Semiconductor Group 14 1997-08-01

Memory Organization

The C515 CPU manipulates data and operands in the following four address spaces:

– up to 64 Kbyte of internal/external program memory
– up to 64 Kbyte of external data memory
– 256 bytes of internal data memory
– a 128 byte special function register area

Figure 5 illustrates the memory address spaces of the C515.

C515

External

Internal

"Code Space"

FFFF

2000

External
(EA = 0)1)=(EA

H

H

1FFF

0000

FFFF

H

External

Indirect

Address

FF

H

Internal

RAM

80

H

H

0000

H

"Data Space" "Internal Data Space"

H

Internal

RAM

Direct

Address

Special

Function

Register

7F

H

00

H

FF

H

80

H

MCD03202

Figure 5
C515 Memory Map

Semiconductor Group 15 1997-08-01

C515

Reset and System Clock

The reset input is an active low input at pin RESET. Since the reset is synchronized internally, the
RESET pin must be held low for at least two machine cycles (24 oscillator periods) while the
oscillator is running. A pullup resistor is internally connected to VCC to allow a power-up reset with
an external capacitor only. An automatic reset can be obtained when VCC is applied by connecting
the RESET pin to VSS via a capacitor. Figure 6 shows the possible reset circuitries.

b)a)

&

+

Figure 6
Reset Circuitries

RESET

C515

RESET

C515

c)

+

RESET

C515

MCS03203

Semiconductor Group 16 1997-08-01

C515

Figure 7 shows the recommended oscillator circuitries for crystal and external clock operation.

Crystal Oscillator Mode Driving from External Source

C

XTAL1

1-24 MHz

C

XTAL2 XTAL2

C

Crystal Mode :

= 20 pF±10 pF (incl. stray capacitance)

Figure 7
Recommended Oscillator Circuitries

N.C.

External Oscillator
Signal

XTAL1

MCS03204

Semiconductor Group 17 1997-08-01