Nokia 2190 Service Manual sysmod
Programmes After Market Services (PAMS)
Technical Documentation
NHB–3 Series Transceiver
Chapter 4
SYSTEM MODULE
PAMS
Technical Documentation
CHAPTER 4 – SYSTEM MODULE
CONTENTS
System Module DB6 4–4
Baseband Block 4–4
Introduction 4–4
Technical Summary 4–4
Interconnection Diagram 4–5
Technical Specifications 4–5
Control Signals 4–6
Connector to UIF Module 4–9
System Connector X100 4–10
Internal Signals and Connections 4–11
Functional Description 4–13
Clocking Scheme Diagram 4–13
Circuit Description 4–13
Reset and Power Control Diagram 4–14
Watchdog System Diagram 4–15
Power Distribution Diagram 4–16
CTRLU 4–17
PWRU 4–21
Introduction 4–21
Block Description 4–22
DSPU 4–24
Introduction 4–24
Technical Description 4–26
Block Description 4–27
AUDIO 4–28
Introduction 4–28
Technical Specification 4–28
Block Description 4–29
ASIC 4–31
Introduction 4–31
Technical Specification 4–31
Block Description 4–33
RFI 4–36
Introduction 4–36
Technical Specification 4–36
Block Description 4–37
Definitions and Abbreviations 4–38
NHB–3
System Module DB6
Page No
Original 26/97
Page 4–2
PAMS
Technical Documentation
RF Blocks 4–39
Technical Summary 4–39
Technical Specification 4–39
Power Distribution Diagram 4–39
Functional Description 4–41
RF Characteristics 4–42
Transmitter 4–44
Synthesizer 4–45
Block Diagram of Receiver Section 4–46
Connections between RX and TX (Version: 6.0 Edit: 88) 4–47
Block Diagram 4–48
Block Diagram of System Section 4–49
Circuit Diagram of CTRLU Section 4–50
Circuit Diagram of PWRU Section 4–51
Circuit Diagram of DSPU Section 4–52
Circuit Diagram of Audio Section 4–53
Circuit Diagram of ASIC Section 4–54
Circuit Diagram of RFI Section 4–55
Circuit Diagram of Receiver Section 4–56
Circuit Diagram of Transmitter Section 4–57
Component Layout Diagram of DB6 side 1 4–58
Component Layout Diagram of DB6 side 2 4–59
Parts List of DB6 (EDMS Issue: 3.1) 4–60
NHB–3
System Module DB6
Original 26/97
Page 4–3
PAMS
Technical Documentation
System Module DB6
Baseband Block
Introduction
The baseband block is designed for a handportable phone, that operates in the
DCS1900 system. The purpose of the baseband module is to control the phone
and process audio signals to and from the RF block. The module also controls
the user interface.
Technical Summary
All functional baseband blocks are mounted on a single 6–layer printed circuit
board. This board contains also RF parts. The chassis of the radio unit has
separating walls for baseband and RF. All components of the baseband section
are surface mountable. They are soldered using reflow. The connections to accessories are taken through the bottom connector of the radio unit. The connections to the User Interface module (UIF) are fed through a flex connector.
There is no physical connector between the RF and baseband sections.
NHB–3
System Module DB6
List of submodules:
CTRLU Control Unit for the phone
PWRU Power supply
DSPU Digital Signal Processing block
AUDIO Audio coding
ASIC D2CA GSM/PCN ASIC
RFI RF – baseband interface
The blocks above are only functional blocks and therefore have no type or material codes.
Original 26/97
Page 4–4
PAMS
Technical Documentation
Interconnection Diagram
NHB–3
System Module DB6
UIF–module
mic
ear
sio
AUDIO
xearxmic
System
connector
dbus
FLASH
LOAD
RFI
12 bit parallel +
32K x 16
SRAM
sio
DSP
ext
sio
mem
PSL+
CHRGR
M2 BUS
Interface
A14:0,
D15:0
A5:0,
D15:0
sio
8 x control
ASIC
A4:0
A19:16
D7:0
A19:0,D7:0
ext mem
io
io
io
MCU
A12:0,D7:0
E2PROM
8K X 8
RF
UIF–module
UIM CARD
READER
LCD
DRIVER
A17:0,D7:0
1024K x 8
FLASH
LCD
LCD
A14:0,D7:0
32K x 8
SRAM
sio
Technical Specifications
Modes of Operation
There are four different operation modes
– active mode
– idle mode
– power off mode
– local mode
In the active state all circuits are powered and part of the module may be in idle
mode.
The module is usually in the idle mode when there is no call and the phone is in
SERV. In the idle mode circuits are reset, powered down and clocks are
stopped or the frequency reduced. All the clocks except the main clock from
VCTCXO can be stopped in that mode. Whether the UIM clock is stopped or
not depends on the network and UIM card type.
Original 26/97
Page 4–5
PAMS
Technical Documentation
In power off mode only the circuits needed for power up are powered. This
means that only power up block inside the PSL+ is powered. The power key on
the flex is pulled up with a pull up resistor inside the PSL+.
The local mode is used for alignment and testing.
Supply Voltages and Power Consumption
Pin/Conn. Symbol Notes
VBATT/sys VBATT • min/typ/max 5.3 /6.0 /8.6 V sw limit
• min/typ/max 4.5 /6.0 /8.9±0.3 V hw limit
• min/typ/max 4.5 /6.0 /7.3±0.3 V hw limit
during a call
VA1 • min/typ/max 4.5 / 4.65 /4.8 V Imax = 40 mA
VA2 • min/typ/max 4.5 / 4.65 /4.8 V Imax = 80 mA
VL1 • min/typ/max 4.5 / 4.65 /4.8 V Imax = 150 mA
NHB–3
System Module DB6
14/sys VF • min/typ/max 11.4 /12 /12.6 V Flash
8,16/sys VCHAR • min/typ/max 10 /12 /13.5 V Charger voltage,
Control Signals
Pin/Con Symbol Notes
5/sys M2BUS • min/max 0 /0.7 V Input low level
6/sys HOOK_RXD2 • Connected to MCU A/D input
VL2 • min/typ/max 4.5 / 4.65 /4.8 V Imax = 150 mA
VREF • min/typ/max 4.55 / 4.65 /4.75 V Imax = 5 mA
programming voltage
when Isink<730 mA
• min/typ/max 730 /800 /870 mA Charger cur–
rent, when Uin<10 V
• min/max 3.0 /4.8 V Input high level
• min/typ/max 0 /0.2 /0.35 V Output low level
• min/typ/max 3.6 /4.65 /4.8V Output high level
• min/typ/max 4.1 /4.65 /4.8 V (not in use)
• min/typ/max 3.0 /3.45 /4.0 V Headset
adapter and plug are connected
• min/typ/max 1.9 /2.35 /2.9 V Hook off in
compact HF
• min/typ/max 0 /0.5 /0.7 V Hook on in
compact HF
Original 26/97
Page 4–6
PAMS
Technical Documentation
Pin/Con Symbol Notes
6/sys HOOK_RXD2 • Flash loading data
7/sys PHFS TXD2 • Power control for PHF–1
15/sys DCLK • DBUS clock 512 kHz
NHB–3
System Module DB6
• min/typ/max 0 /0.2 /0.7 V Input low level
• min/typ/max 3.6 /4.65 /4.8 V Input high level
• min/typ/max 0 /0.2 /0.7 V Output low,
power off
• min/typ/max 3.6 /4.65 /4.8 V Output high,
power on
• Flash loading acknowledgedata
• min/typ/max 0 /0.2 /0.7 V Output low level
• min/typ/max 3.6 /4.65/4.8 V Output high level
• min/typ/max 3.6 /4.65 /4.8 V State ”1”
• min/typ/max 0 /0.2 /0.7 V State ”0”
11/sys DSYNC • DBUS sync 8 kHz
• min/typ/max 3.6 /4.65 /4.8 V State ”1”
• min/typ/max 0 /0.2 /0.7 V State ”0”
4/sys TDA • DBUS transmitted data from HP
• min/typ/max 3.6/4.65/4.8 V State ”1”,
1mA load
• min/typ/max 0 /0.2 /0.7 V State ”0”
12/sys RDA • DBUS received data to HP
min/typ/max 3.6/4.65/4.8 V State ”1”
• min/typ/max 0 /0.2 /0.7 V State ”0”
13/sys BENA • typ 0 V Headset power off
• min/typ 4.4 /4.6 V Headset power on
4/UIF BACKLIGHT • Display and keyboard illumination control
• min/max 0 /0.7 V Output low, backlights off
• min/typ/max 4.5 /4.65 / 4.8 V Output high,
backlights on
5–8/UIF UIF(0:3) • Keyboard row lines read. Display data
lines write.
• min/max 0 /0.7 V Output/Input low
• min/max 4.5 /4.8 V Output/Input high
9/UIF UIF4 • Keyboard row read. Write strobe for
Original 26/97
LCD driver
• min/max 0 /0.7 V Output/Input low
• min/max 4.5 /4.8 V Output/Input high
Page 4–7
PAMS
Technical Documentation
Pin/Con Symbol Notes
10/UIF UIF5 • Keyboard row read. LCD driver register select
11/UIF UIF6 • Enable strobe for LCD driver
12/UIF MIC ENA • min/max 0 /0.7 V Output low,
13–16/ COL(0:3) • Keyboard columns
UIF • min/max 0 /0.7 V Output low
17/UIF CALL LED • min/max 0 /0.7 V Output low, call led off
NHB–3
System Module DB6
• min/max 0 /0.7 V Output/Input low
• min/max 4.5 /4.8 V Output/Input high
• min/max 0 /0.7 V Output/Input low
• min/max 4.5 /4.8 V Output/Input high
microphone bias on
• Floating, microphone off
• min/max 4.5 /4.8 V Output high
• min/typ/max 4.5/ 4.65/ 4.8 V Output high,
call led on
22/UIF BUZZER • PWM output from MCU
• min/max 0 /0.7 V Output low, buzzer off
• min/typ/max 4.5/ 4.65/ 4.8 V Output high,
buzzer on
23/UIF XPWRON • min/typ/max 0 /0 /0.7 V Input low,
power on/off
• typ 4.65 V Floating when inactive.
A pull–up in PSL+
25/UIF UIMCLK • Clock for UIM card
• min/typ/max 3.6 /4.65 /4.8 V State ”1”
• min/typ/max 0 /0.2 /0.7 V State ”0”
• min/max 1 MHz /5 MHz UIM card
clock frequency
26/UIF UIMRESET • Reset for UIM card
• min/typ/max 4.5/ 4.65/ 4.8 V Output high
• min/max 0 /0.7 V Output low
27/UIF VUIM • min/typ/max 4.5/ 4.65/ 4.8 V UIM card reader
supply voltage
• max 10 mA UIM card supply current at
any frequency
• max 100 µA UIM card supply current in
idle state at 1 MHz and 25°C
28/UIF UIMDATA • Data for UIM card In/Out
Original 26/97
• min/typ/max 3.6 /4.65 /4.8 V State ”1”
• min/typ/max 0 /0.2 /0.7 V State ”0”
Page 4–8
PAMS
Technical Documentation
Pin/Con Symbol Notes
BTYPE/ BTYPE • A pullup in phone. 47 kΩ resistor series with
sys 100 kΩ resistor and transitor C–E paraller
NHB–3
System Module DB6
connection
• min/typ/max 0.88 /0.98 /1.09 V
400mAh/15kΩ (pull resistor in the battery pack)
• min/typ/max 1.02 /1.13 /1.25 V 500 mA/18kΩ
• min/typ/max 1.86 /2.02 /2.20 V 950 mA/47kΩ
battery don‘t be in accessorylist
• min/typ/max 2.03 /2.20 /2.37 V,
1100 mAh/56 kΩ
• min/typ/max 2.22 /2.39 /2.58 V,
1200 mAh/68 kΩ battery don‘t be in access.list
• min/typ/max 2.58 /2.76 /2.95 V,
1500 mAh/100 kΩ
• min/typ/max 3.30 /3.48 /3.66 V,
Lithium/270 kΩ,battery don‘t be in access.list
• min/typ/max 1.02 /1.13 /1.25 V,
Vibra 500 mAh/18 kΩ
BTEMP/ TBAT • A 100 kΩ pull–up resistor in HP
sys • typ 3.49 V , at – 5 C
Connector to UIF Module
Signal name Pin Notes
VL1 1 Logic supply voltage 4.65V
GND 2 Ground
VBATT 3,30 Battery voltage
BACKLIGHT 4 Backlights on/off
UIF(0:3) 5–8 Lines for keyboard read and LCD–controller
• typ 2.97 V , at +5 C,Battery temperature
cold limit
• typ 2.86 V , at +7 C
• typ 1.23 V , at +40 C
• typ 0.97 V , at +48 C, Battery temperature
hot limit
• Vibra Battery control. PWM output from
MCU. DC separated.
data
UIF4 9 Line for keyboard read and LCD–controller
Original 26/97
read/write strobe
Page 4–9
PAMS
Technical Documentation
Signal name Pin Notes
UIF5 10 Line for keyboard read and LCD–controller
UIF6 11 LCD–controller enable strobe
MIC_ENA 12 Microphone bias enable
COL(0:3) 13–16 Lines for keyboard write
CALL_LED 17 Call led enable
MICP 18 Microphone (positive node)
MICN 19 Microphone (negative node)
EARP 20 Earpiece (negative node)
EARN 21 Earpiece (positive node)
BUZZER 22 PWM signal buzzer control
XPWRNON 23 Power key (active low)
NHB–3
System Module DB6
data/instruction register selection
VA1 24 Analog supply voltage 4.65V
UIMCLK 25 Clock for UIM data
UIMRESET 26 Reset for UIM
VUIM 27 UIM voltage supply
UIMDATA 28 Serial data for UIM
GND 29 Analog ground. Connected directly to digital
System Connector X100
Signal name pin Notes
GND 1,9 Digital ground.
MIC_JCONN 2 External audio input from accessories or
AGND 3 Analog ground for accessories.
ground on the PCB.
handsfree microphone. Multiplexed with
junction box connection indication. 16.8k
pull down in HP
Connected directly to digital ground on
the PCB.
TDA 4 Transmitted DBUS–data to the accessories
M2BUS 5 Serial bidirectional data and control between
Original 26/97
the handphone and accessories.
Page 4–10
PAMS
Technical Documentation
Signal name Pin Notes
HOOK_RXD2 6 HOOK–indication. The phone has a 100k
PHFS_TXD2 7 Hands–free device power on/off. Data to flash
VCHAR 8,16 Battery charging voltage.
EAR_HFPWR 10 External audio output to accessories or
DSYNC 11 DBUS–data bit sync clock.
RDA 12 DBUS received data from the accessories.
BENA 13 Power supply to headset adapter.
VF 14 Programming voltage for flash from Flash box.
NHB–3
System Module DB6
pull–up resistor. Data to flash from flash
programmer.
programming device.
handsfree speaker. 100kW pull–down in HP to
turn on the junction box.
DCLK 15 DBUS–data clock.
GND BGND Ground
TBAT BTEMP Battery temperature and vibrabattery control
BTYPE BTYPE Battery type
VBATT B+ Battery voltage
VCHAR DC+ Battery charging voltage
VCHAR CH+ Battery charging voltage
GND GND Charging ground, also phone ground
Internal Signals and Connections
Signals between RF and ASIC
Signal Name Function Notes
SCLK Synthesizer clock ASIC–>RF
SDATA Synthesizer data ASIC–>RF
SENA1 Synthesizer enable, UHF and ASIC–>RF
RXPWR RX supply voltage ON/OFF ASIC–>RF
SYNTHPWR Synthesizer supply voltage ON/OFF ASIC–>RF
TXPWR TX supply voltage ON/OFF ASIC–>RF
TXP Transmitter power control enable ASIC–>RF
Original 26/97
VHF PLL enable
Page 4–11
PAMS
Technical Documentation
Signal Name Function Notes
TXL Transmitter low power enable, ASIC–>RF
RFC 26 MHz clock to ASIC CLKIN RF –> ASIC
Signals between RF and RFI
Signal Name Functions Notes
AFC Automatic frequency control voltage RFI –> RF
TXC TX transmit power control voltage, RFI –> RF
TXQP,TXQN differential TX quadrature signal RFI –> RF
TXIP,TXIN differential TX inphase signal RFI –> RF
PDATA0 front end AGC control RFI –> RF
NHB–3
System Module DB6
”0” = low power, ”1” = normal power
AGC control in receiving
RXQ RX quadrature signal RF –> RFI
RXI RX inphase signal RF –> RFI
Signals between RF and CTRLU
Signals name Function Notes
TRF RF temperature RF –> CTRLU
Original 26/97
Page 4–12
PAMS
Technical Documentation
Functional Description
Clocking Scheme Diagram
DSP Clock
60.2 MHz
differential sine
wave
ear
mouth
OSCIL–
LATOR
RFI Clock 13 MHz
Sleep Mode:
135.4kHz
DBUSCLK 512kHz
enable
RFI
NHB–3
System Module DB6
RF System Clock
26 MHz
VCTCXO
AUDIO
CODEC
Codec Sync Clock
8 kHz
DBUSCLK 512kHz
DBUSSYNC 8kHz
DSP
Circuit Description
Most of the clocks are generated from the 26 MHz VCTCXO frequency by the
ASIC:
– 26 MHz clock for the MCU. MCU‘s internal clock frequency is half
of that (13 MHz).
DBUSSYNC 8kHz
Codec Main Clock
and data Transfer
clock
512kHz
ASIC
UIMCLK
3.25 / 1.625
MHz
MCU
Clock
26 MHz
MCU
Original 26/97
– 13 MHz for the RFI. The ASIC also generates 135.4 kHz sleep
mode clock for the RFI.
– 3.25 MHz clock for UIM. When there is no data transfer between
the UIM card and the HP the clock can be reduced to 1.625 MHz.
Some UIM cards also allows the clock to be stopped in that mode.
– 512 kHz main clock for the codec and for the data transfer between the DSP and the codec.
Page 4–13
PAMS
Technical Documentation
– 8 kHz syncronisation clock for data transfer between the DSP and
the codec.
– 512 kHz clock and 8 kHz sync. clock for the DBUS data transfer.
The DSP has its own crystal oscillator which can be turned off and on by the
ASIC. The DSP uses differential sinusoidal clock. The frequency is 60.2 MHz.
The MCU generates 8 kHz clock to the codec for the control data transfer.
In the idle mode all the clocks can be stopped except 26 MHz main clock com-
ing from the VCTCXO.
Reset and Power Control Diagram
NHB–3
System Module DB6
RFI
PSL+
VL1
XRES reset in
XPWRON
XPwrOff
Circuit Description
There are three different ways to switch power on:
reset in
DSP
approx 2Hz
Reset Out
Reset Out
ASIC
Vcc
Reset in
MCU
UIMRESET
resetreg
XPWRON
– Power key pressing grounds the XPWRON line. The PSL+ detects
that and switches the power on.
Original 26/97
– Charger detection on PSL+ detects that charger is connected and
switches power on.
Page 4–14
PAMS
Technical Documentation
– PSL+ will switch power on when the battery is connected. After
that the MCU will detect if power key is pressed or charger connected. If not the power will be switched off.
All devices are powered up at the same time by the PSL+. It supplies the reset
to the ASIC at power up. The ASIC starts the clocks to the DSP and the MCU.
After about 20us the ASIC releases the resets to MCU, RFI and DSP. MCU
and RFI reset is released after 256 13 MHz clock cycles. DSP reset release
time from DSP clock activation can be selected from 0 to 255 13MHz clock
cycles. In our case it is 255. UIM reset release time is according to DSC1900
UIM specifications.
To turn off power for the phone, the user presses the PWR key. The MCU detects this. The MCU cuts off any ongoing call, exits all tasks, acts inoperative to
the user and leaves the PSL+ watchdog without resets. After power–down
delay, the PSL+ cuts off the supply from all circuitry.
If charging is on the phone stays on but it looks to the user like it is powered off
(lights are off and the display is blank) except the charging indicator stays on.
NHB–3
System Module DB6
Watchdog System Diagram
PSL
reset
DSP
5
POWER
4
ASIC
1
2
3
reset
4
Original 26/97
MCU
XPWROFF
Page 4–15
PAMS
Technical Documentation
Circuit Description
Normal operation:
1. MCU tests DSP
2. MCU updates ASIC watchdog timer (> 2Hz)
3. MCU pulses the XPWROFF input on the PSL+ (about 2Hz)
Failed operation:
4. ASIC resets MCU and DSP after about 0.5 s failure
5. PSL+ switches power off about1.5 s after the previous XPWROFF pulse
Power Distribution Diagram
PSL+
VBATT
VL1
VL2
NHB–3
System Module DB6
VCHAR
FLASH
BOX
VF
VL2
32Kx1
6
SRAM
VA1
PCM
CODE
C
VA1
VA2
VREF
VL1
DSP
VL2
VA2 VL1
RFI
VL1
VL2
ASIC
VREFVL1
MCU
MCU
VBATT VREF
VA1
LCD Driver
VL1
VL1
E2PROM
8K x 8
RF
UIF–module
UIF–module
VBATT
VL1
VF
512K x
8
FLASH
LCD
LCD
VL1
32K x
8
SRAM
Circuit Description
PSL+ control supply voltages. VL1 and VL2 are supply voltages to the logic circuits. VA1 and VA2 are supply voltages to the audio circuits. VREF is A/D converter and RF reference voltage. VBATT is fed directly to the circuits which
need higher operation voltage and more current like RF transmitter and UIF
backlight. VF is flash programming voltage, which is fed from flash box.
PSL+ output voltages are active, when PSL+ is in power on state.
Original 26/97
Page 4–16
PAMS
Technical Documentation
CTRLU
Introduction
The Control block contains a microcomputer unit (MCU) and three memory circuits (FLASH, SRAM, EEPROM), a 20–bit address bus and an 8–bit data bus.
Main Features of the CTRLU Block
MCU functions:
– system control
– communication control
– user interface functions
– authentication
– RF monitoring
– power up/down control
– accessory monitoring
– battery monitoring and charging control
– self–test and production testing
– flash loading
NHB–3
System Module DB6
External Signals and Connections, Inputs
Signal name Signal description From
VL1 Power supply voltage for CTRLU block PWRU
VREF Reference voltage for MCU AD–converter PWRU
VBATDET Battery voltage detection PWRU
VC Charger voltage monitoring PWRU
EROMSELX Chip select for the EEPROM memory ASIC
ROMSELX Chip select for the FLASH memory ASIC
RAMSELX Chip select for the SRAM memory ASIC
RESETX Reset signal for MCU ASIC
NMI Non–maskable interrupt request ASIC
MCUCLK Main clock for MCU ASIC
IRQX Interrupt request ASIC
PCMCDO Audio codec control data receiving AUDIO
TRF RF–module temperature detection RF
VF Programming voltage for flash memory system con.
HOOK_RXD2 The use of handsfree monitoring. Flash system con.
Original 26/97
programming data input on the production
line.
Page 4–17
PAMS
Technical Documentation
Signal name Signal description From
TBAT Battery temperature detection and system con.
vibrabattery control
BTYPE Battery size identification system con.
JCONN Junction box connection identification AUDIO
ROMAD18 Rom address 18, (paging) ASIC
External Signals and Connections, Outputs
Signal name Signal description To
XPWROFF Power off control, PSL+ watchdog reset PWRU
PWM Charger on/off control PWRU
WSTROBEX MCU write strobe ASIC
RSTROBEX MCU read strobe ASIC
NHB–3
System Module DB6
MCUAD(19:0) 20–bit MCU address bus ASIC
MBUSDET MBUS activity detection ASIC
PCMCLK Clock for audio codec control data AUDIO
transfer
PCMCDI Audio codec control data transmitting AUDIO
XSELPCMC Chip select for audio codec AUDIO
PHFS_TXD2 Power on/off control for HF device. system con.
Verification output of the programmed data
of FLASH during programming.
CALL_LED ’Incoming’ call indicator light control UIF conn.
BACKLIGHT LCD and display backlight on/off control UIF conn.
BUZZER Buzzer signal UIF conn.
VOLTUM Software charging voltage limit PWRU
BATDET Detect battery removing and give to ASIC ASIC
warning, ASIC drive UIM card down
External Signals and Connections, Bidirectional
Signal name Signal description To/From
MCUDA(7:0) MCU‘s 8–bit data bus ASIC
M2BUS Asynchronous serial data bus system conn.
Original 26/97
Page 4–18
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Technical Documentation
Block Description
MCU – Memories:
The MCU has a 20 bits wide address bus A(19:0) and an 8–bit data
bus with memories. The address bits A(19:16) are used for chip select decoding. The decoding is done in the D2CA ASIC. The ASIC
can address two 4 Mbit (or smaller) or one 8 Mbit flash memories.
Hitachi HD647536 processor has 60kbyte internal ROM and 2kbyte
RAM memories. One wait state is used in flash memory access.
Flash programming
In flash programming a special flash programming box and a PC is
needed. Loading is done through the bottom connector of HP; multiplexed with HOOK_RXD2 and PHFS_TXD2 line. First MCU goes to
minimum mode (MBUS command from PC or if MBUS is connected
to MIC_JCONN line in power up). Then the flash software is loaded
from PC to flash loading box. When the loading is complete flash
loading to HP can be started by MBUS command from PC to the
MCU. After that the MCU asks the test box to start flash loading to
HP. The box supplies 12 V programming voltage for flash and starts
to send 250 bytes data blocks to the MCU via HOOK_RXD2 line.
The baud rate is 406 kbit/s. The MCU calculates the check sum,
sends acknowledge via PHFS_TXD2 line and sends the data to
flash. When all the data is loaded the HP makes reset and tells the
flash loading box if the loading was succeeded or not. Only PSL+,
ASIC and MCU must be active during the loading.
NHB–3
System Module DB6
CTRLU – PWRU
MCU controls the watchdog timer in PSL+. It sends a positive pulse
at approximately 2 Hz to XPWROFF pin of the PSL+ to keep the
power on. If MCU fails to deliver this pulse, the PSL+ will remove
power from the system. MCU also controls the charger on/off switching in the PWRU block. When power off is requested or MCU leaves
PSL+ watchdog without reset. After the watchdog time has elapsed
PSL+ cuts off the supply voltages from the phone.
CTRLU – ASIC
MCU and ASIC have a common 8–bit data bus and a 9–bit address
bus. Bits A(4:0) are used for normal addressing whereas bits
A(19:16) are decoded in ASIC to chip select inputs for CTRLU memories. ASIC controls the main clock, main reset and interrupts to
MCU. The internal clock of MCU is half the MCUCLK clock speed.
RESETX resets everything in MCU except the contents of the RAM.
IRQX is a general purpose interrupt request line from ASIC. After
IRQX request the interrupt register of the ASIC is read to find out the
reason for interrupt. NMI interrupt is used only to wake up MCU from
software standby mode.
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CTRLU – DSPU
MCU and DSP communicate through ASIC. ASIC has an MCU mailbox and a DSP mailbox. MCU writes data to DSP mailbox where
DSP can only read the incoming data. In MCU mailbox the data
transfer direction is the opposite. When power is switched on the
MCU loads data from the flash memory to DSP‘s external memory
through this mailbox.
CTRLU – AUDIO
CTRLU control audio selections MIC/XMIC, EAR/XEAR and those
lines gains. Also CTRLU control tone, ring and dtmf generator.
When MCU drive the chip select signal XSELPCMC low, MCU writes
or reads control data to or from the speech codec registers at the
rate defined by PCMCLK. PCMCDI is an output data line from MCU
to codec and PCMCDO is an input data line from codec to MCU.
CTRLU – RF/BATTERY Monitoring
NHB–3
System Module DB6
MCU has internal 8 channel 10 bit AD converter. Following signals
are used to monitor battery, charging, accessories and RF:
BTYPE battery size
TBAT battery temperature (used also for vibrabattery control)
VBATDET battery voltage
VC charging voltage
TRF RF temperature
CTRLU – UIF
UIM card, keyboard and display interface goes through ASIC.
BUZZER, BACKLIGHT and CALL_LED are controlled directly from
MCU.
CTRLU – ACCESSORIES
M2BUS is used to control external accessories. This interface can
also be used for factory testing and maintenance purposes.
PHFS_TXD2 is used to turn power on to HF accessories.
JCONN is used to indicate that junction box is connected. DC level
come from system connector line MIC_JCONN. Phone can also enter minimum mode when M2BUS is connected to MIC_JCONN line.
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TBAT is used to control vibrabattery. (Used also for battery temperature measurement.)
HOOK indicates accessories hook state. Line is connected to MCU
A/D–input.
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Technical Documentation
JCONN is used to indicate that junction box is connected. DC level
comes from system connector line MIC_JCONN. Phone can also. .
enter minimum mode when M2BUS is connected to MIC_JCONN
line. Line is connected to MCU A/D–input.
Main Components
Hitachi H8/536:
H8/536 is a CMOS microcontroller unit (MCU) comprising a CPU
core and on–chip supporting modules with 16–bit architecture. The
data bus to outside world has 8 bits.
1024k*8bit FLASH memory:
150 ns. maximum read access time (MCU need 1 wait state)
contains the main program code for the MCU; part of the DSP pro-
gram code is also located on FLASH
ASIC can address two 4Mbit memories or one 8Mbit memory.
NHB–3
System Module DB6
32k*8bit SRAM memory:
100 ns. maximum read access time
8k*8bit paraller EEPROM memory:
150 ns. maximum read access time
contains user defined information
there is a register bit on the ASIC which must be set before the write
operation to the EEPROM.
PWRU
Introduction
The power block creates the supply voltages for the baseband block and contains the charging electronics.
External Signals and Connections, Inputs
Signal name Signal description From
XPWRON PWR on switch UIF
XPWROFF Power off control CTRLU
VBATT Battery voltage system conn.
PWM Charger on/off control CTRLU
VCHAR Charging voltage system conn.
VOLTLIM Software charger voltage limit CTRLU
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External Signals and Connections, Outputs
Signal name Signal description To
XRES Master reset ASIC
VL1 Logic supply voltage. Max 150 mA CTRLU,ASIC,
VL2 Logic supply voltage. Max 150 mA DSPU,ASIC
VA1 Analog supply voltage. Max 40 mA AUDIO,UIF
VA2 Analog supply voltage. Max 80 mA RFI
VREF Reference voltage 4.65 V±2% Max 5 mA CTRLU,RFI
VBATDET Switched VBATT divided by 2 CTRLU
VC Attenuated VCHAR CTRLU
CHRDET Charger detection ASIC
NHB–3
System Module DB6
RFI,UIF,DSPU
Block Description
The PSL+ IC produces the following supply voltages:
2 * VL 150mA for logic
VA1 40mA for audios
VA2 80mA for RFI
VREF 5mA reference
In addition, it has internal watchdog, voltage detection and charger detection
functions. The watchdog will cut off output voltages if it is not reset once in every 1.5 (+/– 0.75) second. The voltage detector resets the phone if the battery
voltage falls below 4.7 V (+/–0.2V). The charger detection starts the phone if it
is in power–off state when the charging voltage is applied.
The charging electronics is controlled by the MCU. When the charging voltage
is applied to the phone and the phone is powered up, the MCU detects it and
starts controlling charging. If MCU detects too high charging voltage (over 14
volts) or current (over 78 A/D bit difference between VC and VBATDET) it will
cut off the charging. The phone will accept charging voltages from 5 to 14 volts.
If the phone is in power–off state, the PSL+ will detect the charging voltage and
turn on the phone. If the battery voltage is high enough the reset will be released and the MCU will start controlling charging. If the battery voltage is too
low the phone stays in reset state and the charging control circuitry will pass
charging current to the battery. When the battery voltage has reached 5.25 V
(+/– 0.2 V) the reset will be removed and the MCU starts controlling charging.
MCU controls the charging with pulse width modulation output. Charging voltage is limited by hardware in normal operation to 8.9 V and during a call to
7.6 V.
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