Nokia 2180 Service Manual ch5pinps
Programme’s After Market Services
NHD–4 Series Transceivers
Chapter 5
Schematics/Layouts &
Pinouts
Original 11/97
NHD–4
PAMS
Schematics/Layouts & Pinouts
Technical Documentation
CONTENTS
Pinouts
BASEBAND FILTER
IF + FM DETECTOR 5–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2 x SYNTH 5–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CDAGCR 5–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MCU 5–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MCU memory Flash EEPROM, SRAM 5–6. . . . . . . . . . . . . . . . . . . . . . . . .
DSP memory 5–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PSL + N500 6–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CDAGCT4 5–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CDCONT5 5–9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CDRFI 5–10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Page No
CDSB 4.5 5–11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AUDIO CODEC 5–13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DSP 5–14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Schematics / Layouts (GR1_17a)
Figure 1. NHD–4 Block Diagram 5–15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 2. Power Supply 5–16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 3. MCU 5–17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 4. DSP 5–18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 5. CDMA Asic 5–19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 6. CDRFI 5–20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 7. Audio 5–21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 8. I/O 5–22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 9. MCU Memory 5–23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 10. DSP Memory 5–24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 11. RX 5–25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 12. TX 5–26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 13. Synth 5–27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 14. RF Block 5–28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 15. RFSW 5–29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 16. Control 5–30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 17. Component Layout –Top 5–31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 18. Component Layout – Bottom 5–32. . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 19. Component Values – Top 5–33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 20. Component Values – Bottom 5–34. . . . . . . . . . . . . . . . . . . . . . . . . . .
Page 5–2
Original 11/97
PAMS
NHD–4
Technical Documentation
BASEBAND FILTER (N2) IF + FM DETECTOR (D1)
BASEBAND FILTER N2
NC
NC
AVDD
AVSS
NC
NC
11
12
13
14
15
N2
16
17
18
19
20
Q_A33
Q_AAFI
AGND
I_AAFI
IF AMP+FM DETECTOR D1
I_A33
10
9
NC
CAL
8
DVDD
7
MC
6
DVSS
5
PD
4
XPD
3
NC
2
Q_PFO
1
1 Capacitor Input (I–channel)
2 RXI Output (I–channel)
3 RX_FIL_CAL CALlibration start
4 Digital VDD
5 9.8304 MHz Master Clock
6 Digital VSS
7 Connected to Ground
8 Power Down, Active low
9 No Connection (Grounded)
10 RXQ Output (Q–channel)
Schematics/Layouts & Pinouts
11 Capacitor Input (Q–channel)
12 No Connection (Grounded)
13 Input (Q–channel)
14 No Connection (Grounded)
15 Analog VDD
16 Analog signal GrouND for external stabilation
17 Analog VSS
18 No Connection (Grounded)
19 No Connection (Grounded)
20 Input (I–channel)
AF OUT
QUAD
IF OUT
RSSI
NC
NC
GND
MIX IN
8
9
7
10
6
11
5
12
D1
4
13
14
3
15
2
16
1
2 x SYNTH (N300)
FAST
CPPF
CPP
VDD1
VDD2
PRI
DGND
FXTAL
PDN
NC
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
N300
13
12
11
NC
A0N
VCC
CPA
AGND
AUX
ISET
E
DATA
CLK
9 Demodulate signal output
10 Phase shift signal input of FM demodulator
11 Output terminal of IF AMP
12 Output is DC vs Signal level (RSSI)
13 No Connection
14 No Connection
15 GND
16 1st IF signal input
FIL IN
FIL OUT
DEC
IF IN
VCC
MIX OUT
OSC OUT
OSC IN
1 Local oscillator input
2 Local oscillator output
3 Mix output
4 Power supply
5 2nd IF input
6 Decoupling for bias
7 INVERTER AMP output
8 INVERTER AMP input
1 Control input to speed–up main synth
2 Principal synth speed–up charge–pump output
3 Principal synth normal charge–pump output
4 Digital power supply 1
5 Digital power supply 2
6 1 GHz principal synth RF divider input
7 Digital ground
8 Common reference freq input from chrystal ascillator
9 Principal synth power–on input
10 No Connection
11 Serial clock input
12 Serial data input
13 RX_LE Programming bus enable input (active LOW)
14 Regulator pin to set the charge–pump currents
15 Auxiliary synth frequency input
16 Analog ground
17 180MHz Auxiliary synth charge–pump output
18 Supply for charge–pump and DAC circuits
19 Auxiliary synth power–on input
20 No Connection
Original 11/97
Page 5–3
NHD–4
PAMS
Schematics/Layouts & Pinouts
CDAGCR (N1)
C
IF
E
LNA_BP
VCC1
VCC5
GND5
VC
9
10
11
12
13
14
15
VCN
4LON
4LO
VCC8
GND8
GND6
IREF
ICTL
16
17
18
19
20
21
22
23
24
N1
25262728293031
I
Q
SEL1
VCC6
SEL0
GND7
8
7
6
5
4
3
2
1
32
VCC7
VCC4
N4
GND1
IFN
GND2
VCC2
VCC3
GND3
GND4
1 GROUND (Return for CCGA stage 3)
2 GROUND (Return for CCGA stage 2)
3 DC power for CCGA stage 2
4 DC power for CCGA stage 1
5 GROUND (Return for CCGA stage 1)
6 180° IF Input
7 GROUND (Return for LNA)
8 Emitters of QC’s
Technical Documentation
17 Bypass for CCGA’s conrtol line
18 180° Clock Input
19 0° Clock Input
20 DC power for LO circuitry
21 GROUND (Return for LO circuitry)
22 GROUND (Return for DeMod circuitry)
23 Input control current reference
24 Input control current
9 Collector’s of Q1
10 Sets bias current for the internal LNA (short=6.2mA)
11 Emitters of Q1 (Internal LNA)
12 Bypass for LNA’s bias line
13 DC power for LNA
14 DC power for gain control
15 GROUND (Return for Gain control)
16 Bypass for CCGA’s conrtol line
25 DC Power for DeMod circuitry
26 Baseband 90° output
27 Baseband 0° output
28 Set high for –14 dB change in total gain
29 Set high for –7 dB change in total gain
30 GROUND (Return for Outputs Buffers)
31 DC power for Output Buffers
32 DC power for CCGA stage 3
Page 5–4
Original 11/97
PAMS
NHD–4
Technical Documentation
MCU (D706)
1 No Connection
2 No Connection
3 MCUREAD : Goes Low to indicate that the
CPU is reading external address
4 MCU_WR : Goes Low to indicate that the
CPU is writing external address
5 Power VL1
6 Ground
7 Ground
8 Connected to VL1
9 Connected to VL1
10 XSYS_RESET : A low input causes chip to reset
11 MCU Non Maskable Interrupt
12 Ground
13–20 MCUDA An 8–bit input/output port
21–28 MCUAD An 8–bit input/output port
29 Ground
30–41 MCUAD An 8–bit input/output port
41 MCUDA
42 Power VL1
43 XPWROFF 8–bit Timer Clock input? ? ? ?
44 TEMP1–EN Power Amp temperature
45 TEMP2_EN VCTCXO temperature
47 CALL LED On when phone is ringing / silent alarm
46 No Connection
48 CODEC_CLK
49 CODEC_DO MCU data write to Codec
50 CODEC_DI MCU data read from Codec
51 Ground
52 VBATDET
53 VCHRGMON
54 HOOK_RXD2 Accessory &
55 BTEMP Battery temparature monitoring
56 RFTEMP 1 for PA , 2 for VCTCXO
57 BTYPE Battery type and size
58 RSSI Amps received signal strenght indicator
59 JCONN External audio input from accescories or external
handsfree microphone
60 VREF
Schematics/Layouts & Pinouts
STBY
MD1
MD2
RES
NMI
Vss
D0
D1
D2
D3
D4
D5
D6
D7
7
8
9
10
11
12
13
14
15
16
17
18
19
20
A0
A1
A2
A3
A4
A5
A6
A7
Vss
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
414243444546474849
FTI1
TMCI
Vcc
A19
FTI2
NC
MCU
50
FTOA1
FTOB3/FTCI3
FTOB2/FTCI2
FTOP1/FTCI1
515354
AN1
AN0
AVss
AN2
61 BACKLIGHT Keypad backlight on
62 XCODEC_CS Codec chip select
63 PHFS_TXD2 Power Hans Free / Flash data
64 HOOK_RXD2 Accessory on/off / Flash data
65 Vibra battery controlling
66 MBUS OUT Prosessor monitores outsend data
67 MBUSDET Mbus monitoring during sleepmode
68 No Connection
69 MCU_CLK Clock 15.36 MHz
70 No Connection
71 Ground
72 No Connection
73 No Connection
74 VAHS provides power to Headset
75 5VOFF to 4.7V Regulator (D500)
76 VCHRGPWR controls charging current
77 MCU_INTO
78 No Connection
79 VOLTLIM for future use based on charging
80 XMCU_AS
MD0
RD
NC
WR
Vcc
2
3
4
5
6
55525657585960
AN7
AN6
AN5
AN4
AN3
1
NC
AVcc
AS
80
TMO
79
IRQ1
78
IRQ0
77
WAIT
76
BREQ
75
BACK
74
E
73
NC
72
Vss
71
XTAL
70
EXTAL
69
Vref
68
RXD1
67
TXD1
66
PW3
65
PW2
64
PW1
63
FTOA3
62
FTOA2
61
Original 11/97
Page 5–5
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