Nokia 2180 Service Manual ch4sysps

Programme’s After Market Services

NHD–4 Series Transceivers

Chapter 4

System Module

Original 11/97

NHD–4 System Module

Technical Documentation

CONTENTS

Baseband Block Connections 4–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Internal Signals and Connections 4–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Power Block 4–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MCU Block 4–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MCU Memory Block 4–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DSP Block 4–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DSP memory Block 4–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CDSB ASIC Block 4–9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CDRFI Block 4–11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

AUDIO Block 4–12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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External Signals and Connections 4–12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

User Interface Connector 4–12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Baseband Functional Description 4–14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Power Supply 4–14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MCU Block 4–15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DSP Block 4–15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CDRFI 4–15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Audio Block 4–16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Transmitter Functional Description 4–16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Introduction 4–17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TX Gain Limiting 4–17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CDMA TX Gain Control 4–17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

AMPS TX Gain Control 4–19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TX PA Bias Control (Dynamic TXB) 4–20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Temperature Compensation 4–20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Circuit Description 4–20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CDAGCT IC (N100) 4–20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

AT–109 Variable Attenuator (V106) 4–21. . . . . . . . . . . . . . . . . . . . . . . . . . .

3rd Stage Amplifier (V112) 4–21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Receiver Functional Description 4–24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Introduction 4–24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Antenna and Coaxial Cable (W400) 4–24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Duplexor (Z102) 4–24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

RF LNA Switches and SWAGC/RX_CAL Control Lines 4–24. . . . . . . . . .

LNA and RX SAW Filter 4–25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Mixer (T1) 4–26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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1st IF AMP (V9) and the Diode Switch (V10) 4–26. . . . . . . . . . . . . . . . . . .

AMPS Receiver 4–27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Crystal Filter (Z3) 4–27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CDMA Receiver 4–28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CDMA IF SAW Filter (Z2) 4–28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Synthesizer Functional Description 4–30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Introduction 4–30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PLL IC (N300) 4–30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

The VCTCXO Clock (G300) 4–30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

The UHF Synthesizer 4–30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

The VHF Synthesizer 4–31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

AGC Functional Description 4–32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Signal Descriptions 4–32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

15.36 MHz 4–32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

System Module

DC Voltage Supplies 4–34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Parts List GR1_17A 4–37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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Baseband Block Connections

Below is a list of the functional blocks of the baseband architecture:

– Power Supply Charging Logic Device (PSL+3) – Microcomputer Unit (MCU) – MCU External Memory –

Electrically Eraseable Programmable Read Only Memory (EEPROM) Static Random Access Memory (SRAM)

Flash Memory – Digital Signal Processor (DSP) – DSP External Memory –

Static Random Access Memory (SRAM) – CDSB ASIC – CDMA RF to BB Interface (CDRFI)

System Module

– Audio Coder/Decoder (CODEC)

Internal Signals and Connections

Power Block

Table 1. Power Block Connections

Signal Name T ype Notes

XPWRON IN PWR on switch XPWROFF IN Power off control VBATT IN Battery voltage VCHAR IN Charging voltage VOLTLIM IN Voltage Limiting of charging while call is in prog-

ress. 5VOFF IN voltage reg control –ON / OFF VCHRGPWM IN PWM for controlling battery charging. XPWR_

RESET

OUT Master reset

VL1 OUT Logic supply voltage 1. VL2 OUT Logic supply voltage 2. VL3 OUT Logic supply voltage 3. VA1 OUT Analog supply voltage 1. VA2 OUT Analog supply voltage 2. VREF OUT Reference voltage VL5VOLT OUT Logic supply voltage for MBUS

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NHD–4 System Module

Table 1. Power Block Connections (continued)

NotesTypeSignal Name

Technical Documentation

VLCD OUT Voltage for LCD on UIF VBATDET OUT Switched VBATT VC OUT Attenuated VCHRGMON CHRG_INT OUT Signal to indicate a Charger has been connected

to Phone.

MCU Block

Table 2. MCU Block Connections

Signal Name T ype Notes

MCU_CLK IN Clk into MCU XSYS_RESET IN MCU Reset

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MCUAD(19:0) OUT MCU Address Bus MCUDA(7:0) I/O MCU Data Bus XMCU_AS OUT MCU Address Strobe XMCU_RD OUT MCU Read XMCU_WR OUT MCU Write MCU_NMI IN MCU Non Maskable Interupt MCU_INT0 IN MCU Maskable Interupt 1 CODEC_DI OUT Audio codec control data CODEC_CLK OUT Codec Clock XCODEC_CS OUT Audio codec chip select CODEC_DO IN Audio codec control data CALL_LED OUT UIF CALL_LED enable BACK_LIGHT OUT UIF BACK_LIGHT enable PHFS_TXD2 OUT Hands Free speaker Mute Control HOOK_RXD2 OUT Hook Recieved data VIB_CONT OUT Vibrator Control MBUS_OUT OUT MBUS data output VAHS_EN OUT Headset voltage enable VOLTLIM OUT Voltage Limiting 5VOFF OUT voltage reg control VCHRGPWM OUT Control PWM XPWROFF OUT Watchdog signal TEMP1_EN OUT RFTEMP1 TEMP2_EN OUT RFTEMP2 VBATDET IN A/D input for battery voltage level

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Table 2. MCU Block Connections (continued)

NotesTypeSignal Name

System Module

VCHRGMON IN A/D input for monitoring of charging voltage HOOK_RXD2 IN A/D input – Hook indicator (Phone on or off Hook) BTEMP IN A/D input for monitoring Battery temp. RFTEMP IN A/D input for monitoring RFTEMP 1 and 2 temp. BTYPE IN A/D input for monitoring Battery type. RSSI IN A/D input for monitoring RSSI. JCONN IN A/D input for monitoring Accessory type. MBUS_DET IN MBUS data input.

MCU Memory Block

Table 3. MCU Memory Block Connections

Signal Name T ype Notes

MCUAD IN MCU Address Bus MCUDA I/O MCU Data Bus XMCU_RD IN MCU Read used as Output Enable XMCU_WR IN MCU Write used as Read/Write select XFLASH_CS IN Flash Chip Select XSRAM_CS IN SRAM Chip Select XROM_CS IN EEPROM Chip Select

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DSP Block

Table 4. DSP Block Connections

Signal Name T ype Notes

DSP_CLK IN DSP Clock XSYS_RESET IN DSP Reset DSP_INT0 IN DSP Maskable Interupt 0 DSP_INT1 IN DSP Maskable Interupt 1 DSPAD(15:0) OUT DSP Address Bus DSPDA(15:0) I/O DSP Data Bus DSP_RXW OUT DSP Read / Write Select XDSP_STRB OUT DSP Master Strobe for Memory Access XDSP_DS OUT DSP Data Strobe for Memory Access Codec_FS IN Frame Sync

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Codec_MCLK IN Codec CLK PCMOUT IN Data from Codec PCMIN OUT Data to Codec DSP_SYNC I/O Frame Sync DSP_MCLK I/O CLK DBUS_IN IN Data to DSP. DBUS_OUT OUT Data from DSP.

DSP memory Block

Table 5. DSP Memory Block Connections

Signal Name T ype Notes

DSPAD(15:0) IN DSP Address Bus DSPDA(15:0) I/O DSP Data Bus DSP_RXW IN DSP Read / Write Select XDSP_STRB IN DSP Master Strobe

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CDSB ASIC Block

Table 6. CDSB ASIC Block Connections

Signal Name T ype Notes

XPWR_

IN Master reset FROM PSL+ 3

RESET XSYS_RESET OUT System Reset OSC_OUT IN 32KHz Clk input OSC_IN IN 32KHz Clk input CDRFI_SI OUT CDRFI Serial Data In CDRFI_SO IN CDRFI Serial Data Out CDRFI_SEN OUT CDRFI Serial data ENABLE CDRFI_SCLK OUT CDRFI Serial data CLocK CDRFI_9.8M OUT CDRFI 9.8 MHz clock

System Module

15.36M_IN IN 15.36MHz Clk IN

9.83M_IN IN 9.83MHz Clk IN TXD(7:0) I/O CDRFI TX Data CDRFI_RWSEL OUT CDRFI Read/Write SELect CDRFI_IQSEL OUT CDRFI Tx IQ SELECT RXQ IN CDRFI RX Quadrature–phase data RXI IN CDRFI RX In–phase data DAFOUT IN CDRFI DAF INput GATE OUT CDRFI VCO_EN OUT CDRFI DSP_CLK OUT 7.68 MHz Clk to DSP DSP_INT0 OUT DSP Maskable Interupt 0 DSP_INT1 OUT DSP Maskable Interupt 1 DSPAD IN DSP Address Bus DSPDA I/O DSP Data Bus DSP_RXW IN DSP Read / Write Select XDSP_STRB IN DSP Master Strobe XDSP_DS IN DSP Data Strobe DSP_SYNC OUT Frame Sync DSP_MCLK OUT CLK Codec_FS OUT Frame Sync Codec_MCLK OUT CLK MCU_CLK OUT 15.36 MHz Clk to MCU MCUAD(19:0) IN MCU Address Bus

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Table 6. CDSB ASIC Block Connections (continued)

NotesTypeSignal Name

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MCUDA I/O MCU Data Bus XMCU_AS IN MCU Address Strobe XMCU_RD IN MCU Read Enable XMCU_WR IN MCU Write used as Read/Write select MCU_NMI OUT MCU Non Maskable Interupt MCU_INT0 OUT MCU Maskable Interupt 1 MBUS_DET IN MBUS data input. CHRG_INT IN Signal to indicate a Charger has been connected to

Phone. XFLASH_CS OUT Flash Chip Select XSRAM_CS OUT SRAM Chip Select XROM_CS OUT EEPROM Chip Select LCD_COL I/O LCD and COL/RO lines to UIF CDATTEN OUT SW AGC to RF RF_LIMADJ IN RF_SCLK OUT Serial Data Clk RF_SDATA OUT Serial Data RF_RX_LE OUT Latch Enable for Serial Data RF_TXB OUT Tx Power Bias RF_TXREF OUT REF Level for TXIP comparator RF_AFC OUT VCTCXO control voltage RF_AGCREF OUT Sets RXI & RXQ levels RF_TXGAIN OUT Offsets TX gain to RX gain RF_TXSLP OUT Correction of TX gain slope RF_RXSLP OUT Correction of RX gain slope RF_TXC OUT Limit maximum TX gain RF_TXPUNC OUT RF_VCO_EN OUT RF_RFE0 OUT RFEN0 RF_RFE1 OUT RFEN1 RF_RFE2 OUT RFEN2 RF_RFE3 OUT FAST RF_RFE4 OUT RX_FIL_CAL RF_RFE5 OUT SEL0

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Table 6. CDSB ASIC Block Connections (continued)

RF_RFE6 OUT SEL1 RF_RFE7 OUT RF Control Line

CDRFI Block

Table 7. CDRFI Block Connections

Signal Name T ype Notes

XSYS_RESET IN XRESET SDI IN Serial Data In SDO OUT Serial Data Out SENABLE IN Serial data ENABLE

System Module

NotesTypeSignal Name

SCLK IN Serial data CLocK

9.8M IN 9.8 MHz clock VCLKIN IN VCLocK INput VCLKOUT OUT VCLocK OUTput CLKIN IN CLocK INput CLKOUT OUT CLocK OUTput TXI+ OUT TX signal In–phase (+) TXI– OUT TX signal In–phase (–) TXQ+ OUT TX signal Quadrature–phase (+) TXQ– OUT TX signal Quadrature–phase (–) TXD(7:0) I/O TX Data R/WSEL IN Read/Write SELect IQSELECT IN Tx IQ SELECT RXQ IN RX signal Quadrature–phase RXI IN RX signal In–phase RXQ(5:0) OUT RX Quadrature–phase data RXI(5:0) OUT RX In–phase data TXAGC1 OUT TX AGC control RXAGC1 OUT RX AGC control ANATX OUT ANAlog mode TX signal ANARX+DAF IN ANAlog mode RX + DAF signal DAFOUT OUT DAF OUTput GATE IN TBA VCO_EN IN TBA

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AUDIO Block

Table 8. Audio Block Connections

Signal Name T ype Notes

VA2 IN Analog supply voltage 1. Max 80 mA. PCMIN IN Received audio in PCM–format CODEC_FS IN frame sync CODEC_MCLK IN codec main clock CODEC_DIN IN Audio codec control data CODEC_CLK IN Clock for audio codec control data transfer XCODEC_CS IN Audio codec chip select HFMIC IN External microphone MICN, MICP IN Differential microphone signal PCMOUT OUT Transmitted audio in PCM–format

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CODEC_DO OUT Audio codec control data MIC_EN OUT Microphone enable EXTEAR OUT External received audio EARN, EARP OUT Internal received audio

External Signals and Connections

Table 9. List of Connectors

Connector Name Notes

User Interface Connector 30 pin ZIF for Flex System Connector Acc., Charging, Test connector .

User Interface Connector

Table 10. UIF Connector

Signal Name Pin / Conn. Notes

VL1 1 Logic supply voltage GND 2, 29 Ground VBAT 3, 30 Battery voltage BACKLIGHT 4 Backlights on/off UIF(0:6) 5 – 11 Lines for keyboard write and LCD–controller

control MIC_EN 12 Microphone bias enable COL(0:3) 13 – 16 Lines for keyboard read CALL_LED 17 Call led enable MICP 18 Microphone (positive node)

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Table 10. UIF Connector (continued)

NotesPin / Conn.Signal Name

MICN 19 Microphone (negative node) EARN 20 Earpiece (negative node) EARP 21 Earpiece (positive node) BUZZER 22 Buzzer control ONKEYX 23 Power key VA1 24 Analog supply voltage VL5VOLT 26 LCD supply voltage NC 25,27,28 NO CONNECT

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Baseband Functional Description

Below is a list of the functional blocks of the baseband architecture:

– Power Supply – Microcomputer Unit (MCU)

External Memory –

Electrically Eraseable Programmable Read Only Memory (EEPROM) Static Random Access Memory (SRAM) Flash Memory

MBUS

– Digital Signal Processor (DSP)

External Memory –Static Random Access Memory (SRAM) DBUS Multipath Analyzyer

– Audio Coder/Decoder (CODEC) – CDSB ASIC

Sleep Clock Oscillator (32 KHz)

– CDMA RF to BB Interface (CDRFI)

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Technical Documentation

Power Supply

The PSL+3 – IC produces the supply voltages:

It also has internal watchdog, voltage detection and charger detection functions. The watchdog will cut the output voltages if it is not resetted once in about 6 seconds. The voltage detector resets the phone if the battery voltage falls below 4.0 V. The charger detection starts the phone if it is in power–off when the charging voltage is applied.

The charging electronics is controlled by the MCU. When the charging voltage is applied to the phone while the phone is powered up, the MCU detects it and starts controlling the charging.

If the phone is in power–off, the PSL+3 will detect the charging voltage and start the phone. If the battery voltage is high enough the reset will be released and the MCU will start controlling the charging. If the battery voltage is too low the phone is in reset and charging control circuitry will pass the charging current to the battery. When the battery voltage has reached 4 V the reset will be removed and the MCU starts controlling the charging. This all is invisible to the user.

– RF Interface

3 * VL 150 mA for logic VA1 40 mA not used at this time VA2 80 mA for AUDIO VREF 5 mA reference

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MCU Block

The MCU block controls the user interface, link layer, upper layer protocols, some physical layer tasks, and accessories not linked to data services. It also executes service and diagnostics commands and manages the battery.

DSP Block

The DSPU provides control and signal processing for AMPS and CDMA modes of operation.

– Control and general functions:

– communication with MCU / PC–Locals – mode control of ASIC hardware – RF control – DBUS communication

– AMPS mode speech processing:

– audio signal filtering – acoustic echo cancellation

– AMPS mode modem functions:

– ST (Signalling Tone) signal generation – SAT (Supervisory Audio Tone) signal detection and regeneration – WBD (Wide Band Data) sending – Handoff control

– CDMA mode speech processing:

– Vocoder (Voice Coder) encoding and decoding – acoustic echo cancellation

– CDMA mode control:

– PN (Pseudo Noise) signal acquisition and monitoring – soft & hard handoffs – ASIC Rake Receiver demodulator control – received data rate determination – Multiplex Sublayer (LM) routing of data to MCU or Voice

Coder

– Loopback and Markov Service Options

System Module

CDRFI

CDRFI is a monolitic CMOS high speed CODEC designed for use in CDMA (Code Division Multiple Access) Digital Cellular Telephone applications. It provides AD conversion of the in–phase and quadrature signals in receive path and generation of the in–phase and quadrature signals in transmit path. The CODEC interfaces with digital chip(s) via two parallel interface (separate interfaces for AD and DA signal converters) and one serial interface (for the control DA converters).

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Audio Block

The block consists of audio codec with some peripheral components. The codec includes microphone and earpiece amplifier and all the necessary switches for routing. The controlling of the codec is done by the MCU. The PCM–data comes from and goes to DSPs.

The code converts analog voice to digital samples that can be processed by the DSP. It also accepts DSP processed speech, converts it to analog and transmits the output to the handset or hands free speaker. The codec communicates linear coded data with the DSP over a dedicated serial port. The master clock of the codec is synchronized with the RF VCTCXO and generated by the CDSB ASIC. Codec set up and DTMF tone generation are controlled by the microprocessor via a second serial port.

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Transmitter Functional Description

The transmitter stages are as follows:

 The CDAGCT ASIC  The Variable Attenuator  Two SAW filters  Three BJT driver amplifiers  The GaAs FET power amplifier  The Detector circuit  The Isolator  The Duplexer

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Introduction

NHD–4 uses the same transmitter to up convert, amplify and filter the analog AMPS and the digital CDMA signals. The key differences between analog and digital transmission are the Power Amplifier (PA) bias levels , attenuation levels of the variable attenuator, and operation of the RF transmitter ASIC (CDAGCT). It is important to keep in mind that the AMPS and CDMA signals are significantly different. The AMPS signal is distinct FM modulated carrier with a channel bandwidth of 30 kHz. CDMA modulation is spread spectrum. A CDMA signal is 1.23 MHz wide and appears noise–like.

Aside from this introduction, the Functional Description describes the various signals entering and exiting the NHD–4 transmitter circuit, as well as the DC voltage supplies that bias it.

TX Gain Limiting

TX Limiting is a control feature for CDMA TX operation. In some conditions the AGC loop of the phone may call upon the transmitter to provide more output power than is recommended for healthy operation. The TX Limiting circuit places a ceiling or limit on the output power of the CDMA transmitter. Transmitting above the limit might put the CLY–10 PA (V113) out of its linear range of operation.

System Module

In CDMA operation the TXI_REF PDM stays fixed at a tuned voltage level. This tuned level corresponds to the TX output power limit. The tuned TXI_REF PDM line will be approximately 1.0 V. The detector voltage, TXI, directly reflects the output power of the TX PA chain (V110–V113). For maximum CDMA output power TXI is approximately 1.0 V DC at Pin 2. For minimum CDMA output power TXI is about 2.26 V.

When TXI equals TXI_REF, the LIM_ADJ line goes logic low to approximately 0.0 V. A way to test CDMA TX Limiting Control is to probe the LIM_ADJ line with an oscilloscope and maximize the gain of the transmitter. When the TX output power reaches the limit the LIM_ADJ line will toggle continuously, appearing as a square wave 3.2 Vpp (read at R840) with an approximate frequency of 400 Hz.

CDMA TX Gain Control

A fundamental requirement for proper CDMA system operation is that received signal power levels reaching the digital demodulators remain constant. This is true for both the mobile unit and the base station. The mobile unit must dynamically adjust the gain of its receiver to ensure that the down converted baseband I & Q signal levels delivered to the CDSB ASIC are always constant. The mobile must also dynamically adjust its transmit output power so that the base station always receives the same signal strength. The amount of gain needed at the mobile unit receiver is used to determine how much gain to provide the mobile unit transmitter, thus they are linked in a loop.

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