Nokia 2170 Service Manual sysmod

Programme’s After Market Services

NHP–4 Series Transceivers

Chapter 4

System Module

Issue 1 04/99

NHP–4 System Module

Technical Documentation

Baseband Block 4–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Baseband Block Connections 4–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Internal Signals and Connections 4–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Functional Description 4–13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Power Management 4–14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MCU BLOCK 4–16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DSP Block 4–18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Digital ASIC Clock 4–20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CDRFI 4–21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Audio Block 4–22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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RF Block Introduction 4–23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Transmitter 4–23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Functional Description 4–23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Circuit Description 4–27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Receiver 4–33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Functional Description 4–33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Synthesizer 4–38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

The VCTCXO Clock (G100) 4–38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

The Fujitsu Dual PLL Frequency Synthesizer IC (N101) 4–38. . . . . . . . . . . .

The 2 GHz UHF Channel Selector (LO_PRX, LO_PTX) 4–39. . . . . . . . . . . .

The 416.2 MHz TX VHF LO (LO_TIF) 4–39. . . . . . . . . . . . . . . . . . . . . . . . . . . .

The 256.2 MHz RX VHF LO (LO_RIF)/ 4–40. . . . . . . . . . . . . . . . . . . . . . . . . . .

Motorola MC145162D PLL IC (CLOCKS, N102) 4–40. . . . . . . . . . . . . . . . . . .

Parts List GR2 4–42. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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List Of Figures

Figure 1 Baseband – Interconnections 4–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 2 4–14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 3 Memory Map 4–17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 4 DSP memory configuration w/ 64k external SRAM 4–19. . . . . . . . . .

RF/BB Block Diagram 4–A1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Power Supply 4–A2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MCU 4–A3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MCU Memory 4–A4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DSP 4–A5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DSP Memory 4–A6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

RF Block 4–A7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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Receiver 4–A8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Transmitter 4–A9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Synthesiser 4–A10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input / Output 4–A11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Clocks 4–A12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Power 4–A13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Component Layout – Top 4–A14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Component Layout – Bottom 4–A15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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Baseband Block

Baseband architecture refers to all those technology elements in the phone design which do not include the RF functions. This document describes in overview, the HD891 baseband architecture. Primarily the focus of this document will be to highlight those aspects of the baseband architecture which are unique to the CDMA project.

DSP

DBUS Interface Multipath Analyzer Message Injection IS 125

MIC

EAR

sio

ext mem

sio

PCM CODEC

A15:0, D7:0

64K x 16 SRAM

ASIC

CDRFI

System Module

SYN

C O N T

REC R O L

XMIT/MOD

DUP

UIF–module

LCD

Switche r Charge

FLASH

r LOAD

MBUS Interfac e

Charger Control

sio

ext mem

MCU

Figure 1 Baseband – Interconnections

Baseband Block Connections

Below is a list of the functional blocks of the baseband architecture:

– Microcontroller Unit (MCU) – MCU External Memory –

Electrically Eraseable Programmable Read Only Memory (EEPROM) Static Random Access Memory (SRAM) Flash Memory

A19:0,D7:0

sio

16k x 8

Serial

PROM

1M x 8 32K x 8

FLASH SRAM

LCD Driver

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– Digital Signal Processor (DSP) – DSP External Memory –

Static Random Access Memory (SRAM) – CDSB ASIC – CDMA RF to BB Interface (CDRFI) – Audio Coder/Decoder (CODEC)

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Technical Documentation

Internal Signals and Connections

Power Block

Table 1. Power Block Connections

Signal Name T ype Notes T o/From

XPWRON IN Power on switch UIF WATCHDOG IN Watchdog reset pulse MCU VBATTERY IN Battery voltage Sys. conn. CHAR+ IN Charger Voltage Sys. conn. CHAR– IN Charger Return GND CHAR_PWM IN PWM for controlling battery charging MCU XPWR_RESET OUT Master reset, Power–on Reset ASIC 3VA OUT Analog 3.15V supply CODEC

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3VD OUT 3.15V power supply for baseband 5VD OUT 4.8V supply for MBUS and XEAR Differential Circuit

(Switched)

VAHS OUT 4.8V supply for XEAR Differential Circuit (Switched),

and power for the Headset Accessory

LCD_PWR OUT 4.8V supply with series diode and resistor for LCD

(LCD can’t use 4.8V) BATT_ADC OUT Battery voltage input to ADC MCU CHAR_ADC OUT Charger voltage input to ADC MCU CHAR_INT OUT Signal to indicate a Charger has been connected to

Phone.

UIF

Opamp (N708) and System Connector

UIF

ASIC

MCU Block

Table 2. MCU Block Connections

Signal Name T ype Notes T o/From

MCU_CLK IN 15.36 MHz Clk into MCU ASIC XSYS_RESET IN MCU Reset from ASIC ASIC MCUAD(19:0) OUT MCU 20 bit Address Bus Mem, ASIC MCUDA(7:0) I/O MCU 8 bit Data Bus Mem, ASIC XMCU_AS OUT MCU Address Strobe ASIC XMCU_RD OUT MCU Read used as Output Enable Mem, ASIC XMCU_WR OUT MCU Write used as Read/Write select Mem, ASIC MCU_NMI IN MCU Non Maskable Interupt ASIC MCU_INT0 IN MCU Maskable Interupt 1 ASIC CODEC_DI OUT CODEC_CLK OUT

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Audio codec control data MCU

Clock for audio codec control data transfer MCU

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Table 2. MCU Block Connections (continued)

XCODEC_CS OUT CODEC_DO IN

Audio codec chip select MCU

Audio codec control data MCU

System Module

To/FromNotesTypeSignal Name

CALL_LED OUT UIF CALL_LED enable UIF BACK_LIGHT OUT UIF BACK_LIGHT enable UIF PHFS_TXD2 OUT Hands Free speaker Mute Control and Trans-

Sys. conn. mitted data from Flash during Flash Programming.

HOOK_RXD2 OUT Recieved data during Flash Programming. Sys. conn. VIB_CONT OUT Vibrator Control for quit alarm Sys. conn. MBUS_OUT OUT MBUS data output Sys. conn. VAHS_EN OUT Headset voltage enable Sys. conn. CHAR_PWM OUT Control PWM for charging batteries. PWR WATCHDOG OUT Watchdog signal used to reset watchdog cir-

PWR cuit

TEMP1_EN OUT Control signal to pick RFTEMP1 for A/D read MCU TEMP2_EN OUT Control signal to pick RFTEMP2 for A/D read MCU BATT_ADC IN A/D input for battery voltage level PWR CHAR_ADC IN A/D input for monitoring of charging voltage PWR HOOK_RXD2 IN A/D input – Hook indicator (Phone on or off

Sys. conn. Hook)

BTEMP IN A/D input for monitoring Battery temp. Sys. conn. RFTEMP IN A/D input for monitoring RFTEMP 1 and 2

RF temp.

BTYPE IN A/D input for monitoring Battery type. Sys.conn. RSSI IN A/D input for monitoring RSSI. RF JCONN IN A/D input for monitoring Accessory type. Sys. conn. MBUS_DET IN MBUS data input. Sys. conn

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MCU Memory Block

Table 3. MCU Memory Block Connections

Signal Name T ype Notes T o/From

MCUAD(19:0) IN MCU 20 bit Address Bus MCU MCUDA(7:0) I/O MCU 8 bit Data Bus MCU XMCU_RD IN MCU Read used as Output Enable MCU XMCU_WR IN MCU Write used as Read/Write select MCU XFLASH_CS IN Flash Chip Select ASIC XSRAM_CS IN SRAM Chip Select ASIC VF IN 12 volt line for Flash programming Sys. conn.

DSP Block

Table 4. DSP Block Connections

Signal Name T ype Notes T o/From

DSP_CLK IN 15.36 MHz Clk into DSP ASIC XSYS_RESET IN DSP Reset from ASIC ASIC DSP_INT0 IN DSP Maskable Interupt 0 ASIC DSP_INT1 IN DSP Maskable Interupt 1 ASIC DSPAD(15:0) OUT DSP 16 bit Address Bus Mem, ASIC DSPDA(15:0) I/O DSP 16 bit Data Bus Mem, ASIC DSP_RXW OUT DSP Read / Write Select Mem, ASIC IO_STRB OUT DSP Master Strobe for Memory Access Mem, ASIC Codec_FS IN Frame Sync for aligning Codec audio data

ASIC 8KHz

Codec_MCLK IN CLK for moving Codec audio data ASIC PCMOUT IN Audio Data from Codec CODEC PCMIN OUT Audio Data to Codec CODEC DSP_SYNC I/O Frame Sync for aligning data in and out of

DSP. Used by MP, MI, IS125 and Data Acc.

DSP_MCLK I/O CLK for moving data in and out of DSP. Used

by MP, MI, IS125 and Data Acc.

ASIC,

Sys. conn.

ASIC,

Sys. conn.

DBUS_IN IN Data to DSP. Sys. conn. DBUS_OUT OUT Data from DSP. Sys. conn.

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System Module

DSP memory Block

Table 5. DSP Memory Block Connections

Signal Name T ype Notes T o/From

DSPAD(15:0) IN DSP 16 bit Address Bus DSP DSPDA(15:0) I/O DSP 16 bit Data Bus DSP DSP_RXW IN DSP Read / Write Select DSP XDSP_CS IN DSP SRAM Chip Select for Memory Access

CDSB ASIC Block

Table 6. CDSB ASIC Block Connections

Signal Name T ype Notes T o/From

XPWR_RESET

IN Master reset from 3V switching power supply PWR

XSYS_RESET OUT System Reset to MCU, DSP, CDRFI MCU, DSP,

CDRFI

OSC_OUT OUT 32KHz Clk output ASIC OSC_IN IN 32KHz Clk input ASIC OSC_EN IN Osc. enable ASIC OSC_SEL IN Select clock or Backup ASIC CDRFI_SI OUT CDRFI Serial Data In CDRFI CDRFI_SO IN CDRFI Serial Data Out CDRFI CDRFI_SEN OUT CDRFI Serial data ENABLE CDRFI CDRFI_SCLK OUT CDRFI Serial data CLocK CDRFI CDRFI_9.8M OUT CDRFI 9.8 MHz clock CDRFI

15.36M_IN IN 15.36MHz Clk IN CDRFI

9.83M_IN IN 9.83MHz Clk IN CDRFI TXD(7:0) I/O CDRFI TX Data bits 0–7 CDRFI CDRFI_RWSELOUT CDRFI Read/Write SELect CDRFI

CDRFI_IQSEL OUT CDRFI Tx IQ SELECT bit in digital mode, ad-

CDRFI dress select bit in analog mode.

RXQ(4:0) IN CDRFI RX Quadrature–phase data bits 0–4 CDRFI RXI(4:0) IN CDRFI RX In–phase data bits 0–4 CDRFI DAFOUT IN CDRFI DAF INput –NOT

USED HD891–

IFclk IN Namps Support –NOT

USED HD891–

Noxw IN Namps Support –NOT

USED HD891–

GATE OUT CDRFI CDRFI

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Table 6. CDSB ASIC Block Connections (continued)

Technical Documentation

To/FromNotesTypeSignal Name

DSP_CLK OUT 15.36 MHz Clk to DSP DSP DSP_INT0 OUT DSP Maskable Interupt 0 DSP DSP_INT1 OUT DSP Maskable Interupt 1 DSP DSPAD(15:0) IN DSP 16 bit Address Bus (15,14,8–0) DSP DSPDA(7:0) I/O DSP 8 bit Data Bus DSP DSP_RXW IN DSP Read / Write Select DSP IO_STRB IN DSP Master Strobe for Memory Access DSP XDSP_IS IN DSP Data Strobe DSP

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DSP_SYNC OUT Frame Sync for aligning data in and out of

Sys. conn. DSP. Used by MP, MI, IS125 and Data Acc.

DSP_MCLK OUT CLK for moving data in and out of DSP. Used

Sys. conn. by MP, MI, IS125 and Data Acc.

DBUS_IN IN Signal used as an interupt for DBUS activity Sys. conn. Codec_FS OUT Frame Sync for aligning Codec audio data

8KHz

DSP,

CODEC

Codec_MCLK OUT CLK for moving audio Codec data DSP,

CODEC

MCU_CLK OUT 15.36 MHz Clk to MCU MCU MCUAD(19:0) IN MCU 20 bit Address Bus (19–16,5–0) MCU MCUDA(7:0) I/O MCU 8 bit Data Bus MCU XMCU_AS IN MCU Address Strobe MCU XMCU_RD IN MCU Read used as Output Enable MCU XMCU_WR IN MCU Write used as Read/Write select MCU MCU_NMI OUT MCU Non Maskable Interupt MCU MCU_INT0 OUT MCU Maskable Interupt 1 MCU MBUS_DET IN MBUS data input. Sys. conn CHAR_INT IN Signal to indicate a Charger has been con-

PWR nected to Phone.

XFLASH_CS OUT Flash Chip Select MCU Mem. XSRAM_CS OUT SRAM Chip Select MCU Mem. XROM_CS OUT EEPROM Chip Select –NOT

MCU Mem. USED HD891–

LCD_COL I/O LCD and COL/RO lines to UIF UIF CDATTEN OUT SW AGC to RF RF RF_LIMADJ IN RF RF_SCLK OUT Serial Data Clk RF

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Table 6. CDSB ASIC Block Connections (continued)

System Module

RF_SDAT A OUT Serial Data RF RF_RX_LE OUT Latch Enable for Serial Data RF RF_TXB OUT Tx Power Bias

RF 8bit PDM – 3.84Mhz

RF_TXREF OUT REF Level for TXIP comparator

RF 8bit PDM – 1.92Mhz

RF_AFC OUT VCTCXO control voltage

RF 8bit PDM – 3.840Mhz

RF_AGCREF OUT AUXAGC RF RF_TXGAIN OUT Offsets TX gain to RX gain –NOT

RF USED HD891– 7bit PDM – 4.9152Mhz

RF_TXSLP OUT Correction of TX gain slope –NOT

RF USED HD891– 7bit PDM – 1.92Mhz

To/FromNotesTypeSignal Name

RF_RXSLP OUT Correction of RX gain slope –NOT

RF USED HD891– 7bit PDM – 1.92Mhz

RF_TXC OUT Limit maximum TX gain NOT

RF USED HD891 8bit PDM – 4.9152Mhz

RF_PDM1 OUT PDM NOT

USED HD891

RF_PDM2 OUT PDM NOT

USED HD891

RF_TXPUNC OUT Enables the PA RF RF_VCO_EN OUT Same as RF RESET to CDCONT RF RF_RFE0 OUT RF Control Line RFEN0 RF RF_RFE1 OUT RF Control Line RFEN1 RF RF_RFE2 OUT RF Control Line RFEN2 RF RF_RFE3 OUT RF Control Line FAST RF RF_RFE4 OUT RF Control Line RX_FIL_CAL RF RF_RFE5 OUT RF Control Line SEL0 RF RF_RFE6 OUT RF Control Line SEL1 –NOT

RF USED HD891–

RF_RFE7 OUT RF Control Line RX_CAL NC

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CDRFI Block

Table 7. CDRFI Block Connections

Signal Name T ype Notes T o/From

XSYS_RESET IN XRESET When set = 0, reset registers

ASIC to default values.

SDI IN Serial Data In ASIC SDO OUT Serial Data Out ASIC SENABLE IN Serial data ENABLE ASIC SCLK IN Serial data CLocK ASIC

9.8M IN 9.8 MHz clock ASIC VCLKIN IN VCLocK recovery INput RF VCLKOUT OUT VCLocK recovery OUTput ASIC CLKIN IN CLocK recovery INput RF

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CLKOUT OUT CLocK recovery OUTput ASIC TXI+ OUT TX signal In–phase (+) RF TXI– OUT TX signal In–phase (–) RF TXQ+ OUT TX signal Quadrature–phase (+) RF TXQ– OUT TX signal Quadrature–phase (–) RF TXD(7:0) I/O TX Data bits 0–7 ASIC R/WSEL IN Read/Write SELect ASIC IQSELECT IN Tx IQ SELECT bit in digital mode,

ASIC address select bit in analog mode.

RXQ IN RX signal Quadrature–phase RF RXI IN RX signal In–phase RF RXQ(5:0) OUT RX Quadrature–phase data bits 0–5 ASIC RXI(5:0) OUT RX In–phase data bits 0–5 ASIC TXAGC1 OUT TX AGC control RF RXAGC1 OUT RX AGC control RF ANATX OUT ANAlog mode TX signal –NOT USED

RF HD891–

ANARX+DAF IN ANAlog mode RX + DAF signal –NOT USED

RF HD891–

DAFOUT OUT DAF OUTput –NOT USED HD891– ASIC GATE IN Controls TX output ASIC VCO_EN IN Disables the Clock squaring circuits ASIC TEST IN TEST input (if not used, must be on VSS)

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System Module

AUDIO Block

Table 8. Audio Block Connections

Signal Name T ype Notes T o/From

3VA PCMIN CODEC_FS CODEC_MCLK CODEC_DIN CODEC_CLK

XCODEC_CS XMIC_JCONN MICN, MICP PCMOUT CODEC_DO MIC_ENX XEAR_HFJPWR EARN, EARP

OUT OUT OUT OUT OUT

Analog supply voltage, Max 80 mA. PWR

Received audio serial data DSP

8kHz frame sync ASIC

512kHz codec audio data clock ASIC

Audio codec control data MCU

IN IN

Clock for audio codec control data transfer Audio codec chip select MCU

External microphone Sys. conn.

Differential microphone signal UIF conn

Transmitted serial audio data input DSP Audio codec control data output MCU Microphone enable UIF External received audio Sys. conn. Internal received audio UIF

MCU

Functional Description

Below is a list of the functional blocks of the baseband architecture:

– Power Management – Microcontroller Unit (MCU)

External Memory –

Electrically Eraseable Programmable Read Only Memory (EE-

PROM)

Static Random Access Memory (SRAM) Flash Memory

MBUS

– Digital Signal Processor (DSP)

External Memory –

Static Random Access Memory (SRAM) DBUS Multipath Analyzyer

– Audio Coder/Decoder (CODEC) – CDSB ASIC

Sleep Clock Oscillator (32 KHz)

– CDMA RF to BB Interface (CDRFI) – RF Interface

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Power Management

This section covers the power management system of the HD891 transceiver. The power management software is the same as HD881 with some minor updates, however, the power supply section is completely new. A highly efficient and low noise DC–DC converter is used for most of the baseband power, and the PSL logic is replaced using a few comparators. The charging circuit is also new.

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Technical Documentation

General

The HD891 power management section consists of charging, power–on, watchdog, & reset circuits, and voltage regulators. The main 3V baseband supply is generated by a buck mode dc–dc converter. Power off quiescent current drain is 250uA while power on sleep mode current is 2mA.

Power Distribution

Power distribution to the rest of the phone is very simple. Baseband uses the 3.15V 3VD output from the dc–dc converter. RF uses VBAT (from VBATTERY) as a supply. UI and MBUS use the 4.8V supply (5VD). The UI also uses VBATTERY for the LEDs and buzzer.

Figure 2

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Charging Switch/Regulator

The charging switch/regulator acts to connect the charger input to the battery with minimal losses. To prevent overcharging the output voltage is limited to 8.4V (+/–0.25V) when CHAR_PWM is high or 5.4V when CHAR_PWM is low (startup). Maximum current is 1000mA. The input is protected against transients by a varistor. Maximum dc input voltage range is –5V to +16V.

Charging is controlled by the CHAR_PWM signal. When it is high, charging is on. If the battery voltage is less than 5.4V charging is on regardless of the CHAR_PWM state. Charging can only occur if the charging voltage is greater than the battery voltage.

If there is no battery the charger will provide 8.5V working voltage to the phone. The software should detect a no–battery condition and display a warning in the UI. If desired, it may be possible to operate the phone in standby, as long as the total phone current is less than 280mA.

Battery Monitor

System Module

A comparator continuously measures the battery voltage. When battery voltage rises above 5.2V the phone will power on (watchdog reset). When battery voltage falls below 5.0V the phone powers off. The 200mV hysteresis prevents oscillation.

Charger Detection

When the charger input voltage rises above 5.0V and battery voltage is above 5.2V the phone is powered on (watchdog reset). If battery voltage is lower than 5.4V the charger automatically turns on to provide a pre–charge. And then once the battery voltage reaches 5.2V the battery monitor turns on the phone.

When a charger is connected and the phone is on, the CHAR_INT signal will go high. It is possible that when the battery falls below 5.4V a false CHAR_INT may occur even without a charger connected. This should not be a problem because the software should have already powered down the phone.

Watchdog

The watchdog timer is reset on power up or when the WATCHDOG input is toggled. The minimum pulse width for either input is 10ms. Minimum watchdog timeout is 9 seconds. If the MCU does not reset the timer by toggling WATCHDOG (falling edge triggered) within the timeout period the 3VD output (& software) will power down.

Note: It is best to hold WATCHDOG low so a power down itself does not reset the timer!

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DC–DC Converter, Regulators, Reset

Technical Documentation

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The main 3VD supply for baseband is regulated by a DC–DC converter. It offers 90% efficiency in normal mode and 80% during sleep. The free–run operating frequency is 250kHz, but locks to either 307kHz (CDMA) or 340kHz (AMPS) of the PWR_CLK input signal (Note: HD891 will operate in CDMA mode only). The PLL lock time is 10ms. To put the DC–DC converter into sleep mode the shutdown pin and PWR_CLK should be held low.

The 5V supply to the LCD and MBUS is from a 4.8V LDO linear regulator.

Note: The LCD may be changed to a 3V version!

Table 9. Regulator Specifications

Output Voltage Current Noise

3VD 3.15V +/–0.10V 500mA 5mVpp 50mV n/a 100mV, 5ms 5VD 4.8V +/–0.2V 50mA 5mVpp 50mV 1ms 100mV, 5ms

1. Using a resistive load at 1/2 rated current.

2. From zero to rated current load.

Regulation

Risetime Transient

The XPWR_RESET line is released about 150ms after the 3VD output has risen beyond 2.5V.

MCU BLOCK

The MCU block controls the user interface, link layer, upper layer protocols, some physical layer tasks, and accessories not linked to data services. It also executes service and diagnostics commands and manages the battery.

The block includes a Hitachi HD647534 processor ( 32K internal ROM, 2K internal SRAM ) with access to a 1M x 8 FLASH, 32K x 8 SRAM, and 16K x 8 EEPROM. Clock and sleep control, system decode, software timers, and other system support are incorporated into CDSB ASIC. MCU input clock will be sourced by a 15.36 MHz clock from the ASIC. The period of an MCU state is equal to the 15.36 MHz clock divided by two. A low power software standby mode is invoked whenever processing lulls. The MCU communicates with CDSB ASIC over a byte wide parallel data bus.

MCU memory pages 2 and 4 can be changed based on bits set in the CDSB ASIC. Page 2 maybe set for EEPROM select or FLASH select. Default is EEPROM. Page 4 maybe set for SRAM select or FLASH select. Default is FLASH.

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Technical Documentation

External Memory

External memory accessed by the MCU:

 1M x 8bit FLASH memory

– 150 ns maximum read access time – contains the main program code for the MCU ; in the beginning

– Not all the FLASH is used, ONLY 40000 and up is available.

 32k x 8bit SRAM memory

– 150 ns maximum read access time

 16k x 8bit EEPROM memory (Serial)

Memory Map

PAGE 0:

H0 0000 H0 0200

Vector tables

on chip

32K bytes

the DSP program code locates also in FLASH

PAGE 0:

H0 F680

on chip

RAM

2K bytes

ROM

H0 FE80

registers

384 bytes

System Module

PAGE 1:

ASIC

PAGE 2:

EEPROM/

FLASH

PAGE 3:

SRAM

PAGE 4:

FLASH/ SRAM

PAGE 5:

PAGE 6,7:

FLASH FLASH

PAGE 8,9,A,B: PAGE C,D,E,F:

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FLASH FLASH

Figure 3 Memory Map

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NHP–4 System Module

MBUS

MBUS interface will be implemented via serial port on the MCU. Protocol will be DCT MBUS compatible.

DSP Block

The DSP block functions include speech processing, time critical physical layer tasks, and multiplex sublayer tasks. The block consists of a TI LEAD processor clocked by the 15.36 Mhz system clock. An internal upconverter and PLL mechanism in the DSP will allow machine cycle rates up to 50 MHz. We will be using a x 3 option, the ASIC will provide the 15.36 MHz clock to the DSP. This will be advantageous in that a duty cycle closer to 50% could be guaranteed without relying on the output of the VCTCXO which has the possibility of a much wider variation. A low power sleep mode can invoked whenever processing allows. A 64kx16 SRAM will be incorporated.

The DSP must communicate with the MCU and the CDSB ASIC. MCU communication is directed through the CDSB ASIC to manage sleep and interrupt timing. The mailbox function inside the ASIC provides the ”gateway” for communications between the two processors. The digital ASIC interface is memory mapped I/O consisting of byte wide parallel data, address lines, and access control lines.

PAMS

Technical Documentation

The DBUS and the Multipath Analyzer/Message Injection are outputs/input of the DSP. Only one of these comm. links may be used at a time.

The DSPU (Digital Signal Processing Unit) block is in charge of the channel and speech coding according to the IS–96–B specifications for 8kbit VOCODERS, and IS–3972 for 13kbit VOCODERS. The block consists of a TMS320C5xx DSP and external RAMs. The DSP chip contains 28kword internal mask ROM and 5k word internal and 32k word external RAM. The 64K word external RAM is loaded with code stored in the MCU flash ROM.

The DSPU provides control and signal processing for CDMA modes of operation. – Control and general functions:

– communication with MCU / PC–Locals – mode control of ASIC hardware – RF control – DBUS communication

– CDMA mode speech processing:

– Vocoder (Voice Coder) encoding and decoding – acoustic echo cancellation

– CDMA mode control:

– PN (Pseudo Noise) signal acquisition and monitoring – soft & hard handoffs – ASIC Rake Receiver demodulator control – received data rate determination – Multiplex Sublayer (LM) routing of data to MCU or Voice Coder – Loopback and Markov Service Options

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Nokia 2170 Service Manual sysmod

System Module

Contents

List Of Figures

Baseband Block

Baseband Block Connections

Internal Signals and Connections

Power Block

MCU Block

MCU Memory Block

DSP Block

DSP memory Block

CDSB ASIC Block

CDRFI Block

AUDIO Block

Functional Description

Power Management

General

Power Distribution

Charging Switch/Regulator

Battery Monitor

Charger Detection

Watchdog

MCU BLOCK

External Memory

Memory Map

MBUS

DSP Block