Nokia 2160 Service Manual system

SYSTEM MODULE GR4/GP4

NHC–4

11/97JR
Technical Documentation

Contents

System Module GR4 8–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Technical Summary 8–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

External and Internal Connectors 8–5. . . . . . . . . . . . . . . . . . . . .

Bottom Connector X100 8–5. . . . . . . . . . . . . . . . . . . . . . . . . .

UIF Module Connector X196 8–7. . . . . . . . . . . . . . . . . . . . . .

Baseband Block 8–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

List of Submodules 8–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Modes of Operation 8–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Analog Control Channel Mode (ACC) 8–8. . . . . . . . . . . . . . .

Out of Range Mode (OOR) 8–8. . . . . . . . . . . . . . . . . . . . . . . .

Analog Voice Channel Mode (AVCH) 8–9. . . . . . . . . . . . . . .

Digital Control Channel Mode (DCC) 8–9. . . . . . . . . . . . . . .

Digital Traffic Channel Mode 8–9. . . . . . . . . . . . . . . . . . . . . .

Supply voltages and power consumption 8–9. . . . . . . . . . . . . .

Audio Control Signals 8–10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Current Consumption 8–10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Clocking Schemes 8–11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Reset and Power Control 8–12. . . . . . . . . . . . . . . . . . . . . . . . . . . .

Watchdog System 8–13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CTRLU 8–14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Introduction 8–14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input Signals of CTRLU 8–14. . . . . . . . . . . . . . . . . . . . . . . . . . .

Outputs Signals of CTRLU 8–15. . . . . . . . . . . . . . . . . . . . . . . .

Bidirectional Signal of CTRLU 8–16. . . . . . . . . . . . . . . . . . . . .

Block Description of CTRLU 8–16. . . . . . . . . . . . . . . . . . . . . . .

Behaviour in Different Modes 8–17. . . . . . . . . . . . . . . . . . . . . .

Main Components 8–18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PWRU 8–19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input Signals of PWRU 8–19. . . . . . . . . . . . . . . . . . . . . . . . . . .

Output Signals of PWRU 8–19. . . . . . . . . . . . . . . . . . . . . . . . . .

Block Description of PWRU 8–19. . . . . . . . . . . . . . . . . . . . . . .

Main Components of PWRU 8–20. . . . . . . . . . . . . . . . . . . . . .

DSPU 8–21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input Signal of DSPU 8–22. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output signal of DSPU 8–22. . . . . . . . . . . . . . . . . . . . . . . . . . .

Bidirectional signal of DSPU 8–22. . . . . . . . . . . . . . . . . . . . . . .

Block Description of DSPU 8–22. . . . . . . . . . . . . . . . . . . . . . . .

Modes of Operation 8–24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Main Components of DSPU 8–24. . . . . . . . . . . . . . . . . . . . . . .

AUDIO 8–25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input signal of AUDIO 8–25. . . . . . . . . . . . . . . . . . . . . . . . . . . .

8–1

Copyright  Nokia Mobile Phones

SYSTEM MODULE GR4/GP4

NHC–4

11/97JR
Technical Documentation

Copyright  Nokia Mobile Phones

Output signal of AUDIO 8–25. . . . . . . . . . . . . . . . . . . . . . . . . . .

Block Description of AUDIO 8–26. . . . . . . . . . . . . . . . . . . . . . .

Main Componets of AUDIO 8–26. . . . . . . . . . . . . . . . . . . . . . .

ASIC 8–27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input Signals of ASIC 8–27. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output signals of ASIC 8–28. . . . . . . . . . . . . . . . . . . . . . . . . . .

Bidirectional signals of ASIC 8–29. . . . . . . . . . . . . . . . . . . . . .

Block Description of ASIC 8–29. . . . . . . . . . . . . . . . . . . . . . . . .

Main Components of ASIC 8–29. . . . . . . . . . . . . . . . . . . . . . . .

RFI 8–30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Inputs signals of RFI 8–30. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output signals of RFI 8–31. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Bidirectional of RFI 8–31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Main Components of RFI 8–31. . . . . . . . . . . . . . . . . . . . . . . . .

RF Module Block 8–32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

List of Functional Blocks 8–32. . . . . . . . . . . . . . . . . . . . . . . . . . . .

Constructions and Connections 8–32. . . . . . . . . . . . . . . . . . . . . .

RF Frequency Plan 8–32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Functional Description 8–33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Receiver 8–33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Frequency Synthesizers 8–33. . . . . . . . . . . . . . . . . . . . . . . . . .

Transmitter 8–34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Modes of Operation 8–35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Analog control channel mode 8–35. . . . . . . . . . . . . . . . . . . . . .

Analog out of range mode and extended stby mode 8–35. .

Analog voice channel mode 8–35. . . . . . . . . . . . . . . . . . . . . . .

Digital traffic channel mode 8–35. . . . . . . . . . . . . . . . . . . . . . .

Software Compensations 8–35. . . . . . . . . . . . . . . . . . . . . . . . . . . .

Power Levels (TXC) vs. Temperature 8–35. . . . . . . . . . . . . . .

Power Levels (TXC) vs. channel 8–35. . . . . . . . . . . . . . . . . . .

Power Levels vs. Battery Voltage 8–36. . . . . . . . . . . . . . . . . .

Power Up/Down ramps 8–36. . . . . . . . . . . . . . . . . . . . . . . . . . .

Digital Mode RSSI 8–36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

RF Characteristics 8–36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Receiver 8–36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Duplex Filter 8–36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Pre–amplifier 8–36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

RX Interstage Filter 8–36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

First mixer 8–36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

First IF amplifier 8–36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

First IF filter 8–37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2nd first IF amplifier 8–37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Receiver IF circuit, RX part of CRFRT (digital mode) 8–37.

Second IF filter 8–37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8–2

SYSTEM MODULE GR4/GP4

NHC–4

11/97JR
Technical Documentation

Copyright  Nokia Mobile Phones

FM IF circuit (analog mode) 8–37. . . . . . . . . . . . . . . . . . . . . . .

Transmitter 8–37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Modulator Circuit, TX part of CRFRT 8–37. . . . . . . . . . . . . . .

Unconversion mixer 8–37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TX buffers 8–38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TX interstage filter 8–38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Power amplifier 8–38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Power control circuitry 8–38. . . . . . . . . . . . . . . . . . . . . . . . . . . .

Synthesizers 8–38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Reference oscillator 8–38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

YHF synthesizer 8–38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

UHF synthesizer 8–39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

UHF buffers 8–39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PLL circuit 8–39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Baseband Block Diagram 8–40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

RF Block Diagram 8–41. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

RF Block Interconnection Diagram (GP4) (Version 5.63 ; edit 120) 8–42. . . .

Baseband Power Distribution Diagram 8–43. . . . . . . . . . . . . . . . . .

RF Power Disribution Diagram 8–44. . . . . . . . . . . . . . . . . . . . . . . . .

Parts List of GR4 EDMS Issue: 6.7 Code: 0200674 8–45. . . . .

Parts List of GP4 EDMS Issue: 7.0 Code: 0200900 8–57. . . . .

Parts List of GP4 (EFR) EDMS Issue: 3.0 Code: 0201114 8–68

8–3

Schematic Diagrams: GR4, GP4

Block Diagram 8A–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

GR4: Block Diagram of System Blocks (V. 4.24 Edit: 185) layout 12 8A–2. . .
GR4: Circuit Diagram of CTRLU Section (V. 5.01 Edit: 167) layout 13 8A–3.
GR4: Circuit Diagram of PWRU Section (V. 5.01 Edit: 114) layout 13 8A–4. .
GR4: Circuit Diagram of DSPU Section (V. 5.01 Edit: 157) layout 13 8A–5. .

GR4: Circuit Diagram of Audio Section (V. 5.01 Edit: 79) layout 13 8A–6. . . .

GR4: Circuit Diagram of ASIC Section (V. 5.01 Edit: 182) layout 13 8A–7. . .

GR4: Circuit Diagram of RFI Section (V. 5.01 Edit: 117) layout 13 8A–8. . . . .

GR4: Circuit Diagram of Receiver Section (V. 5.01 Edit: 166) layout 13 8A–9
GR4: Circuit Dgrm of Synthesizer Section (V.5.01 Edit:110) layout 13 8A–10.
GR4: C. D. of Transmitter and Mod. Sect. (V.5.01 Edit:404) layout 13 8A–11.
GP4: Block Diagram of System Blocks (V. 5.63 Edit: 205) layout 06 8A–12. .
GP4: Circuit Diagram of CTRLU Section (V. 5.63 Edit: 188) layout 06 8A–13
GP4: Circuit Diagram of PWRU Section (V. 5.63 Edit: 131) layout 06 8A–14.
GP4: Circuit Diagram of DSPU Section (V. 5.63 Edit: 171) layout 06 8A–15. .
GP4: Circuit Diagram of Audio Section (V. 5.63 Edit: 93) layout 06 8A–16. . .
GP4: Circuit Diagram of ASIC Section (V. 5.63 Edit: 202) layout 06 8A–17. .

GP4: Circuit Diagram of RFI Section (V. 5.63 Edit: 132) layout 06 8A–18. . . .

GP4: Circuit Diagram of Receiver Section (V. 5.63 Edit: 194) layout 06 8A–19
GP4: Circuit Dgrm of Synthesizer Section (V.5.63 Edit:131) layout 06 8A–20

SYSTEM MODULE GR4/GP4

NHC–4

11/97JR
Technical Documentation

Copyright  Nokia Mobile Phones

GP4: C. D. of Transmitter and Mod. Sect. (V.5.63 Edit:431) layout 06 8A–21.
GP4: Block Diagram of System Blocks (V. 8.61 Edit: 206) layout 06 8A–22. .
GP4: Circuit Diagram of CTRLU Section (V. 8.61 Edit: 189) layout 06 8A–23
GP4: Circuit Diagram of PWRU Section (V. 8.61 Edit: 132) layout 06 8A–24.
GP4: Circuit Diagram of DSPU Section (V. 8.61 Edit: 173) layout 06 8A–25. .
GP4: Circuit Diagram of Audio Section (V. 8.61 Edit: 94) layout 06 8A–26. . .
GP4: Circuit Diagram of ASIC Section (V. 8.61 Edit: 283) layout 06 8A–27. .

GP4: Circuit Diagram of RFI Section (V. 8.61 Edit: 133) layout 06 8A–28. . . .

GP4: Circuit Diagram of Receiver Section (V. 8.61 Edit: 195) layout 06 8A–29

GP4: C. D. of Synthesizer Section (V. 8.61 Edit: 132) layout 06 8A–30. . . . . .

GP4: C. D. of Transmitter and Mod. Sect. (V.8.61 Edit:432) layout 06 8A–31.

Layout Diagram of GR4 side 1 (version 13) 8A–32. . . . . . . . . . . . . .

Layout Diagram of GR4 side 2 (version 13) 8A–33. . . . . . . . . . . . . .

Layout Diagram of GP4 side 1 (version 06) 8A–34. . . . . . . . . . . . . .

Layout Diagram of GP4 side 2 (version 06) 8A–35. . . . . . . . . . . . . .

Layout Diagram of GP4 side 1 (EFR 8.61 version 06) 8A–36. . . . .

Layout Diagram of GP4 side 2 (EFR 8.61 version 06) 8A–37. . . . .

8–4

SYSTEM MODULE GR4/GP4

NHC–4

11/97JR
Technical Documentation

System Module GR4

Technical Summary

All functional blocks of the baseband are mounted on a single multi layer

printed circuit board. This board contains also RF–parts. The chassis of the ra-

dio unit contains separating walls for baseband and RF. All components of the

baseband are surface mountable. They are soldered using reflow. The connec-

tions to accessories are fed through the bottom connector of the radio unit. The

connections to User Interface –module (UIF) are fed through a flex foil connec-

tor. There is no physical connector between RF and baseband.

External and Internal Connectors

The system module has two connector, external bottom connector and internal

UIF module connector.

8–5

Copyright  Nokia Mobile Phones

Antenna
connector

2

1

16

System connector

Bottom Connector X100

System Connector

Pin: Name: Description:

1, 9 LGND Digital ground. Separated with a choke from

4

Battery connector

3

2

1

4

Charging connector

X100

9

18

3

2

30

1

1

X196

UIF module connector

D0000323

PCB–gound

2 XMIC_JCONN External audio input from accessories or

handsfree microphone.
3 AGND Analog ground.
4 TDA DBUS transmitted data.

SYSTEM MODULE GR4/GP4

NHC–4

11/97JR
Technical Documentation

Copyright  Nokia Mobile Phones

8–6

5 M2BUS Serial bidirectional data and control between

the handportable and accessories.
6 HOOK/RXD2 HOOK indication. The phone has a 100 kΩ

pull–up resistor.
7 PHFS/TXD2 Handsfree device power on/off, data to flash

programming device.
8, 16 VCHAR Battery charging voltage.
10 XEAR_HFJPWR External audio output to accessories or

handsfree speaker.
11 DSYNC DBUS frame sync DBUSCLKEN
12 RDA DBUS received data
13 BENA Booster enable, TX–timing control (open drain,

TX–power is on when BENA is low)
14 VF Programming voltage for FLASH.
15 DCLK DBUS data clock. DBUSCLK

Battery Connector

Pin: Name: Description:
1 VBAT Battery voltage

2 BSI Battery size identification
3 BTEMP Battery temperature sense
4 GND Ground

Charging Connector

Pin: Name: Description:
1 VCHAR Battery charging voltage

2 GND Ground
3 VCHAR Battery charging voltage
4 GND Ground

Antenna Connector

Pin: Name: Description:
1 RF EXT External antenna signal

2 GND Ground

SYSTEM MODULE GR4/GP4

NHC–4

UIF Module Connector X196

Pin: Name: Description:
1 VL1 Logic supply voltage 4.65 V

2,17,20 GND Ground
3,30 VBAT Battery voltage
4 KEYLIGHT Backlights on/off
5–11 UIF(0;6) Lines for keyboard write and LCD–

12 UIF7 LCD lights on/off
13–16 COL(0;3) Lines for keyboard read
18 MICP Microphone (positive node)
19 MICN Microphone (negative node)
20 EARP Earpiece (positive node)

11/97JR
Technical Documentation

controller control

8–7

Copyright  Nokia Mobile Phones

21 EARN Earpiece (negative node)
23 VA2 Analog supply voltage 4.65 V
24 ONKEYX Power key (active low)
26 MIC_EN Microphone bias enable (open drain,

active low)
29 BUZZER Buzzer control

SYSTEM MODULE GR4/GP4

NHC–4

Baseband Block

Baseband block is designed for a handportable phone, that operates in DAMPS
system. The purpose of the baseband module is to control the phone and pro­cess audio signals to and from RF. The module also controls the user interface.

List of Submodules

CTRLU Control Unit for the phone
PWRU Power supply
DSPU Digital Signal Processing block
AUDIO Audio coding
ASIC UDSA2 – asic
RFI RF – baseband interface
These blocks are only functional blocks and therefore have no type nor material

codes.

11/97JR
Technical Documentation

8–8

Copyright  Nokia Mobile Phones

Modes of Operation

There are the following operating modes in the phone: Analog control channel,
Analog speech channel, Digital control channel, Digital traffic channel and out–
of–range.

Analog Control Channel Mode (ACC)

Radio unit is ready for reception on analog control channel. Most of the time
only RX–modem of UDSA2–asic and clock for it are operational. All other cir­cuitry is powered down. Sometimes UDSA2 detects incoming data and wakes
up the MCU to read it. MCU determines whether the data is meant for that par­ticular phone or not. If the call is detected, the phone moves to analog voice
channel or digital traffic channel mode depending on the orders by the base
station. Occasionally the phone communicates with the base station and then
the phone must be powered up.

Out of Range Mode (OOR)

All circuitry is powered down except a timer in UDSA2. After the timer has
elapsed the phone tries to establish the connection to base station. If it
succeeds, the phone goes to analog control channel mode. If the connection
can not be established the phone will stay in out of range mode, start the count­er in ASIC and power down all other circuitry.

SYSTEM MODULE GR4/GP4

NHC–4

11/97JR
Technical Documentation

Analog Voice Channel Mode (AVCH)

The phone is capable for analog receiving and transmitting. All circuitry is pow­ered up except digital rx parts. MCU is in charge of the signalling between the
phone and the base station.

Whenever possible the circuits are put to sleep or standby.

Digital Control Channel Mode (DCC)

On digital control channel (DCC) DSPU receives the paging information from
the Paging channel (PCH) or Broadcasting channel (BCCH). DSPU sends mes­sages to MCU for processing them.

Phone is in sleep between pagings.
From DCC phone may be commanded to analog control channel or to analog

or digital traffic channel

Digital Traffic Channel Mode

8–9

Copyright  Nokia Mobile Phones

The phone is capable for receiving and transmitting on digital traffic channel. All
circuitry is powered up, except FM detector.

On digital trafic channel DSPU processes speech signal in 20 ms time slots.
DSPU performs the speech and channel functions in time shared fashion and
sleeps whenever possible. Rx and tx are powered on and off according to the
slot timing. MCU is waken up mainly by DSPU, when there is signalling in­formation for the CS.

Supply voltages and power consumption

Line symbol Minimum Typ/nom Maximum Unit/notes
VBAT 5.3 V 6.0 V 9.0 V

VCHAR 11.0 V 13.0 V
VA1 4.5 V 4.65 V 4.8 V Imax = 40 mA
VA2 4.5 V 4.65 V 4.8 V Imax = 80 mA
VL1 4.5 V 4.65 V 4.8 V Imax = 150 mA
VL2 4.5 V 4.65 V 4.8 V Imax = 150 mA
VREF 4.6 V 4.65 V 4.8 V Imax = 5 mA
VF 11.4 V 12 V 12.6 V

SYSTEM MODULE GR4/GP4

NHC–4

Audio Control Signals

The nominal values correspond ±2.9 kHz peak deviation.
Line symbol Minimum Typ./nom. Maximum

MICP, MICN 106.1 mV
EARP, EARN 43.7 V
EXTEAR

• min d.c. level 2.0 V 158 mV
XMIC

• min d.c. level 2.0 V 11 kΩ pull–down
resistor in HP 71 mV

Current Consumption

State VL1/mA VL2/mA VA1/mA VA2/mA

11/97JR
Technical Documentation

rms

8–10

Copyright  Nokia Mobile Phones

rms

rms

rms

1.384 V

600 mV

1026 mV

rms

rms

rms

NOSERV 12 1.2 <50 µA <50 µA
SERV Ana 18 1 13 µA 140 µA
Analog call 43 50 8.4 11
Digital call 43 63 4.6 11

VL1 = MCU, SRAM, FLASH, ASIC, RFI, EEPROM, UI
VL2 = DSP1, DSP–rams
VA1 = RFI
VA2 = AUDIO codec, UI

SYSTEM MODULE GR4/GP4

NHC–4

Clocking Schemes

MCU 1x clock: 4.86 / 9.72 MHz

MCU

DSP Clock: 9.72 MHz

DSP

38.88 MIPS

PLL

2x, 4x

11/97JR
Technical Documentation

RFI Clock: 9.72 MHz

MCU CCR bit 1

programmed
frequency
MCU CCR

bit 0

DIV2

DSP CCR
bit 2

EN

RFI2

ENEN

Copyright  Nokia Mobile Phones

RF 2nd IF freq: 9.72 /4 = 2.43 MHz

RFI2 clock 106kHz

DSP
CCR
bit 3

DSP
CCR
bit 14

EN

DIV

91.7

DIV2

8–11

VCTCXO

ASIC System Clock

AUDIO
CODEC

DBUS

Data clock

512 kHz (d–mode)

518.4 kHz (a–mode)

8.0 kHz (d–mode)

8.1 kHz (a–mode)

Sync clock

Data clock
512 kHz

Sync clock

8.0/64 kHz

MCU CCR bit 2, DSP CCR bit 0

EN

DSP CCR
bit12

EN

DSP CCR bit 11

frequency

DIV

18.75
DIV

1200

RF System Clock:

19.44 low level
sine wave

UDSA2

UDSA2 uses an unbuffered clock from the VCTCXO. MCU can select its clock
frequency: 4.86 MHz, 9.72 or 19.44 MHz (default 9.72 MHz). DSP uses internal
4X PLL for generating the 38.88 MHz. Audio codec uses different clocks in A–
and D–mode. VCTCXO oscillator is running all the time.

All of the clock outputs can be disabled/enabled. DSP controls the DSP clock
and MCU clock is controlled by MCU. If DSP is in sleep mode, MCU can wake

SYSTEM MODULE GR4/GP4

NHC–4

it up by sending a PIO–message. MCU and DSP clocks are also controlled by
the sleep clock.

Reset and Power Control

reset in

DSP

11/97JR
Technical Documentation

RFI

reset in

ASIC

RFI Reset Out

DSP Reset Out
MCU Reset Out

resetreg

Vcc
Reset in

resetreg

8–12

Copyright  Nokia Mobile Phones

LCD

Reset in

PSL+

VL1

XRES reset in

XPWRON

XPwrOff

approx 0.5s

The supply power is switched on by PWR key on keyboard. All devices are
powered up at the same time by PSL+.

PSL+ supplies the reset to ASIC at power up. ASIC starts the clocks to DSP
and MCU. After 100 ms delay the PSL+ release the reset to ASIC, and ASIC
releases the resets to all circuitry. Power up reset resets MCU , RFI and DSP.

For powering of the phone, the user pushes PWR–key. MCU detects that it is
pushed. After that the MCU cuts the eventual ongoing call, exits all tasks, acts
dead to the user and leaves PSL+ watchdog without resets. After power–down
delay PSL+ cuts the supply voltage from all the circuitry.

XPWRON

MCU

SYSTEM MODULE GR4/GP4

NHC–4

Watchdog System

PSL

11/97JR
Technical Documentation

reset

DSP

1

5

POWER

3

8–13

Copyright  Nokia Mobile Phones

4

ASIC

4

2

reset

XPWROFF

Normal operation:

1 MCU tests DSP
2 MCU updates ASIC watchdog timer (> 2 Hz)
3 MCU pulses the XPWROFF input on the PSL+

Failed operation:

4 SIC resets MCU and DSPs (After about 0.5 sec failure)
5 PSL+ switches the power off (After 0.750 ms failure)

MCU

(about 2 Hz)

SYSTEM MODULE GR4/GP4

NHC–4

CTRLU

Introduction

The Control block provides a mastercomputer unit (MCU) and it’s environment.
The environment consists of three memory circuits (FLASH, SRAM, EEPROM),
20 bit address bus and 8 bit data bus.EEPROM uses serial communication.

MCU functions:
– system control
– communication control
– user interface
– authentication
– RF monitoring
– power up/down control
– accessory monitoring

11/97JR
Technical Documentation

8–14

Copyright  Nokia Mobile Phones

– battery monitoring
– self–test and production testing
– charging control

Input Signals of CTRLU

Signal name Signal description From
VL1 Power supply voltage for CTRLU block PWRU

VREF Reference voltage for MCU A/D converter PWRU
VBATDET Battery voltage detection PWRU
VC Charger voltage monitoring PWRU
ROMSELX Chip select for the FLASH memory ASIC
RAMSELX Chip select for the SRAM memory ASIC
RESETX Reset signal for MCU ASIC
NMI Non–maskable interrupt request ASIC
MCUCLK Main clock for MCU ASIC
IRQX Interrupt request ASIC
MBUSOUT Transmitted M2BUS–data from M2BUS– ASIC

circuitry of ASIC
PCMCDO Audio codec control data receiving AUDIO
RSSI Received signal level indicator RF
TRF RF module temperature detection RF

SYSTEM MODULE GR4/GP4

NHC–4

TXF Transmitter on/off error control RF
VF Programming voltage for flash memory System conn.
JCONN Indicates if phone is connected to car System conn.

RXD2_HOOK The use of handsfree monitoring System conn.

BTEMP Battery temperature detection Battery conn.

BSI Battery size identification Battery conn.

Outputs Signals of CTRLU

Signal name Signal description To

11/97JR
Technical Documentation

Copyright  Nokia Mobile Phones

installation bracket. When phone is

connected to car installation bracket, this

signal has about 2 V d.c. level, otherwise

d.c. level is 0 V.

Flash programming data input on the

production line

Vibrator battery control signal

8–15

XPWROFF Power off control, PSL+ watchdog reset PWRU
PWM Charger on/off control PWRU
MCUASX MCU address strobe ASIC
WSTROBEX MCU write strobe ASIC
RSTROBEX MCU read strobe ASIC
MCUAD(19;0) 20–bit MCU address bus ASIC
MBUSDET MBUS activity detection ASIC
TXD Transmitted M2BUS–data to M2BUS– ASIC

circuitry of ASIC.
PCMCLK Clock for audio codec control data AUDIO

transfer
PCMCDI Audio codec control data transmitting AUDIO
XSELPCMC Chip select for audio codec AUDIO
TXD2_PHFS Power on/off control for HF device System conn.

Verification output of the programmed

data of flash on the production line
UIF8 Call–led control Uif conn.
BUZZER Buzzer signal to earphone Uif conn.

SYSTEM MODULE GR4/GP4

NHC–4

Bidirectional Signal of CTRLU

Signal name Signal description To/From
MCUDA(7;0) MCU’s 8 bit data bus ASIC,memories

M2BUS Asyncronous serial data bus System conn.

Block Description of CTRLU

MCU – Memories

MCU has a 20 bits wide address bus A(19:0) and an 8–bit data bus with memo­ries. The address bits A(19:16) are used for chip select decoding. The decod­ing is done in UDSA2–asic.

On the Hitachi HD647534 internal memory map there is the following:

00000 – 07FFF 32k bytes internal ROM
0F680 – 0FE7F 2k bytes internal RAM

11/97JR
Technical Documentation

8–16

Copyright  Nokia Mobile Phones

0FE80 – 0FFFF 384 bytes registers

External memory map is the following:

08000 – 0FFFF 32k bytes RAM
30000 – 300FF 256 bytes ASIC
80000 – BFFFF 256k bytes FlashROM

CTRLU – PWRU

MCU controls the watchdog timer in PSL+. It sends a positive pulse at approxi­mately 2 Hz to XPWROFF pin of the PSL+ to keep the power on. If MCU fails to
deliver this pulse, the PSL+ will remove power from the system. MCU controls
also the charger on/off switching in the PWRU block. When power off is re­quested MCU leaves PSL+ watchdog without reset. After the watchdog has
elapsed PSL+ cuts off the supply voltages from the phone.

CTRLU – ASIC

MCU and ASIC have a common 8 bit data bus and a 9 bit address bus. A(5:0)
are used for normal addressing whereas bits A(19:16) are decoded in ASIC to
chip select inputs for CTRLU memories. ASIC controls the main clock, main re­set and interrupts to MCU. The internal clock of MCU is half the MCUCLK clock
speed. RESETX resets everything in MCU except the contents of the RAM.
IRQX is general purpose interrupt request line from ASIC. After IRQX request
the interrupt register of asic is read to find out the reason for interrupt. NMI–in­terrupt is used only to wake up MCU from software standby mode.

CTRLU – DSPU

MCU and DSP communicate through ASIC. ASIC has MCU mailbox and DSP–
mailbox. MCU writes data to MCU mailbox where DSP can only read the in­coming data. In DSP–mailbox data transfer direction is opposite.

SYSTEM MODULE GR4/GP4

NHC–4

11/97JR
Technical Documentation

Copyright  Nokia Mobile Phones

8–17

CTRLU – AUDIO

When the the chip select signal XSELPCMC goes low, MCU writes or reads
control data from AUDIO at the rate defined PCMCLK. PCMCDI is output data
line from MCU to codec and PCMCDO is input data line from codec to MCU.

CTRLU – BATTERY – Monitoring

MCU monitors battery functions with 3 channels (BTEMP, BSI,VBATDET) of an
8 channel A/D converter.

CTRLU – RF – Monitoring

MCU monitors RF functions with two channels (RSSI and TRF) of an 8 chan­nel AD converter and one digital I/O–pin (TXI).

CTRLU – Keyboard and LCD Driver Interface

MCU and User Interface communication is controlled through ASIC.

CTRLU – ACCESSORIES

M2BUS is used to control external accessories. This interface can be used also
to factory testing and service and maintenance purposes.

Behaviour in Different Modes

Analog Control Channel Modes

While on analog control channel the MCU and the peripherals are in standby.
From time to time the MCU must poll the states of the control lines from the ac­cessories.

The UDSA2 gives an interrupt to MCU if RX–modem detects data on channel.
The MCU then wakes up and starts controlling the receiving. If the data was not
for that phone the MCU will go to standby. Otherwise it will continue to control
the phone and start establishing the call.

Another alternative to wake up the processor is that the user pushes any button
on the keyboard. After that the asic will give an interrupt and the MCU starts to
control the phone.

Out–of–Range Mode

In out–of–range mode the MCU is in standby most of the time. During that time
the input clock is also stopped to save power. ASIC wakes up the MCU from
time to time to control the search for control channels and to reset the PSL+
watchdog. MCU use OOR signal to cut off the voltages from receiver to save
power in out of range mode.

Analog Voice Channel Mode

During analog voice channel operation the MCU is in charge of the operation of
the phone. The MCU is sleeping always when it is possible.

SYSTEM MODULE GR4/GP4

NHC–4

Digital Traffic Channel Mode

During digital traffic channel operation the MCU is in charge of the operation of
the phone. The MCU is sleeping always when it is possible.

Digital Control Channel Mode

While on analog control channel MCU and the peripherals are in standby. From
time to time the MCU must poll the states of the control lines from the accesso­ries.

DSPU perioidically wakes up to receive the paging information from PCH or
BCCH. DSPU wakes up the MCU if message is for the phone. MCU processes
the messages and controls the phone accordingly. If message was not for the
phone, then DSPU goes back to standby.

Another alternative to wake up the processor is that the user pushes any button
on the keyboard. After that the asic will give an interrupt and the MCU starts to
control the phone.

Main Components

11/97JR
Technical Documentation

8–18

Copyright  Nokia Mobile Phones

• Hitachi H8/534

– H8/534 is a CMOS microcomputer unit (MCU) comprising a CPU core and

on–chip supporting modules with 16 bit architecture. The data bus to outside
world has 8 bits.

• 512k*8 bit FLASH memory
– 150 ns maximum read access time
– contains the main program code for the MCU; in the beginning the DSP pro-

gram code locates also in FLASH

• 32k*8bit SRAM memory
– 100 ns maximum read access time

• 8k*8bit EEPROM memory
– serial communication
– contains user defined information

SYSTEM MODULE GR4/GP4

NHC–4

PWRU

The power block makes the supply voltages for the baseband and includes also
the charging electronics.

Input Signals of PWRU

Signal name Signal description From
XPWRON PWR on switch UIF

XPWROFF Power off control CTRLU
VBATT Battery voltage System conn.
PWM Charger on/off control CTRLU
VCHAR Charging voltage System conn.

Output Signals of PWRU

11/97JR
Technical Documentation

8–19

Copyright  Nokia Mobile Phones

Signal name Signal description To
XRES Master reset ASIC

VL1 Logic supply voltage 1. Max 150 mA. CTRLU,ASIC,

VL2 Logic supply voltage 2. Max 150 mA. DSPU
VA1 Analog supply voltage 1. Max 40 mA. RFI
VA2 Analog supply voltage 2. Max 80 mA. AUDIO,UIF
VREF Reference voltage 4.65V ±2%. Max. 5mA. CTRLU,ASIC,

VBATDET Switched VBATT divided by 2 CTRLU
VC Attenuated VCHAR CTRLU

Block Description of PWRU

PSL+ has an internal watchdog, voltage detection and charger detection func­tions. The watchdog will cut the output voltages if it is not resetted once in
about 0.5 seconds. The voltage detector resets the phone if the battery voltage
falls below 4.5 V.

RFI,UIF

RF

The charging electronics is controlled by the MCU. When the charging voltage
is applied to the phone while the phone is powered up, the MCU detects it and
starts controlling the charging.

If the phone is in power–off, the PSL+ will detect the charging voltage and start
the phone. If the battery voltage is high enough the reset will be released and
the MCU will start controlling the charging. If the battery voltage is too low the
phone is in reset and charging control circuitry will pass the charging current to

SYSTEM MODULE GR4/GP4

NHC–4

the battery. When the battery voltage has reached 4.5 V the reset will be re­moved and the MCU starts controlling the charging. This all is invisible to the
user.

Main Components of PWRU

• PSL+ asic
– Makes the voltages, has power switch, charger and battery detection and

watchdog.

• Transistor BCP69–25 and Schottky STPS340U
– The charging current is passed through these components.

• Transistor BCX51
– VL regulators of PSL+ external output transistors.

11/97JR
Technical Documentation

8–20

Copyright  Nokia Mobile Phones

SYSTEM MODULE GR4/GP4

NHC–4

DSPU

11/97JR
Technical Documentation

Copyright  Nokia Mobile Phones

8–21

The DSPU (Digital Signal Processing Unit) block is in charge of the channel
and speech coding according to the IS–54B (2120 Plus) and IS–136 (2160)
specs. The block consists of a TMS320C541 DSP and slow external RAMs.
The DSP chip contains 28k word internal mask ROM and 4k word internal RAM

The main functions by two main modes of the DSPU block are as follows:
– control and general functions:

– main control of the DSP
– communication with MCU and data adapter module
– RF control

– analog mode speech processing functions:

– pre–emphasis, de–emphasis
– expansion, compression
– analog audio signal filtering
– acoustic echo cancellation (only when the handset is used)

– digital mode speech processing functions:

– VAD (Voice Activity Detection)
– full rateVSELP (Vector Sum Exited Linear Prediction) speech co-

ding

– acoustic echo cancellation (only when the standard HF is used)

– analog mode modem functions:

– ST (Signalling Tone) signal generation
– SAT (Supervisory Audio Tone) signal detection and regeneration
– WBD (Wide Band Data) sending

– digital mode modem functions:

– raised cosine filtering
– channel equalization
– interleaving
– convolutional coding and decoding
– MAHO (Mobile Assisted HandOff) measurements
– AFC (Automatic Frequency Control)
– symbol and frame synchronization
– AGC (Automatic Gain Control)
– DTX (Discontinuous Transmission) control
– CRC generation and checking

SYSTEM MODULE GR4/GP4

NHC–4

Input Signal of DSPU

Signal name Signal description From
VL2 Logic supply voltage 2. Max 150 mA. PWRU

DSPCLK Master clock for DSP ASIC
DSPRSTX Reset for the DSP ASIC
PCMDATRCLK, Differential PCM–data receive clock ASIC

PCMDATRCLKX
PCMOUT Received audio in PCM–format AUDIO
INT0, INT1 Interrupts for DSP ASIC
PCMCO–SYCLKX PCM–data bit sync clock ASIC

Output signal of DSPU

Signal name Signal description To

11/97JR
Technical Documentation

8–22

Copyright  Nokia Mobile Phones

PCMIN Transmitted audio in PCM–format AUDIO
IOX I/O enable. Indicates access to DSP ASIC

RWX Read/WriteX ASIC
DSPAD(17;0) Address bus and control signals ASIC

Bidirectional signal of DSPU

Signal name Signal description To/From
DSPDA(15;0) 16–bit data bus ASIC

Block Description of DSPU

DSP communicates with MCU trough a mailbox in the UDSA2 ASIC. DSP com­municate with the PCM codec with the SIO1 serial bus. DSP controls RFI and
RF through UDSA2.

Analog transmit

Audio signal in analog mode is fed to the PCM codec, where it is routed, ampli­fied and converted by internal A/D converter into 64 kb/s bitstream. The digi­tized speech is processed by the DSP audio modules into 48.6 k samples/s au­dio. The samples are sent to the RFI’s AGC D/A converters. AGC DAC –output
signal is fed to VHF syntheziser to give FM modulation. DSP must also perform
echo cancelling in HF mode.

address space.

SYSTEM MODULE GR4/GP4

NHC–4

11/97JR
Technical Documentation

Copyright  Nokia Mobile Phones

8–23

Analog receive

In analog receive the demodulated analog signal is first A/D converted in RFI at

48.6 k samples/s. The samples are directed trough UDSA2 to DSP. DSP per­forms audio processing and finally transfers the digital audio at 64 kb/s to the
PCM codec, where they are D/A converted. Resulting audio signal is routed
and amplified to the earpiece or external loudspeaker.

Digital transmit

In digital transmit mode DSP processes speech data in 20 ms slots. It performs
VSELP speech coding, CRC generation, convolutional coding and interleaving.
Finally it sends the symbols to the UDSA2 modulator. The UDSA2 modulator
performs the π/4 DQPSK modulation. UDSA2 controls the transmit timing and
at specified intervals sends the I/Q samples at 97.2 k samples/s to RFI for TXI/
Q D/A converters.

Digital receive

In digital receive mode the 2.43 MHz IF signal from RF unit is converted with
RFI/Q A/D converters at sample rate of 48.6 k samples/s. The timing is con­trolled by UDSA2. DSP performs bit detection with equalizer and then convolu­tional decoding and CRC checking. After this the (speech) bits are passed for
VSELP speech decoding. The decoded bits are converted to analog signal in
the PCM codec, routed and fed to the earpiece.

Analog modem functions

Analog modem decoding functions: ST and SAT. but not Wide Band Data
(WBD) are performed by the DSP. All modem transmit functions are performed
by DSP. WBD is received through an external BP filter and decoded (Manches­ter decoding, 3/5 vote and BCH decoding) by the UDSA2 modem. In XSTBY
mode, the 3/5 voting is not used.

Control functions

In all modes except analog control channel mode DSP controls the RF. Control­ling is done physically through UDSA2, where all necessary timing functions
are implemented, and control I/O lines are provided for e.g. syntheziser load­ing, power control etc.

All clocks and timing are generated from the RFC clock, which is amplified in
the ASIC block.

SYSTEM MODULE GR4/GP4

NHC–4

Modes of Operation

DSP goes to sleep by first executing clock stop command to UDSA2 and then
executing IDLE2 instruction. When DSP is in standby, the clock is disabled and
PLL also stopped. DSP is woken up from the sleep by UDSA2 by first starting
the clock and then after a delay issuing an interrupt0/1. No reset is needed.

Analog Control Channel (ACC)

DSP is used to CRC–status checking

Out of Range Mode (OOR)

DSP is used for searching for digital control channels in digital mode. MCU
searches for analog control channels.Synthezisers are controlled by DSP.

Analog Voice Channel Mode (AVCH)

On analog voice channel DSP performs the audio processing, FM modulation,
and signalling except WBD reception. In the HF mode it also performs echo­cancellation and the HF algorithm.

Digital Traffic Channel Mode (DTCH)

11/97JR
Technical Documentation

8–24

Copyright  Nokia Mobile Phones

DSP processes the speech signal in 20 ms slots. RX, TX and MAHO are timed
by the UDSA2 timers. DSP sleeps whenever possible.

Main Components of DSPU

• TI TMS320C541 DSP
– 38.88 MIPS
– 4k RAM/ 28k ROM
– 2 SIOs, 1 timer
– programmable PLL for clocking (4X used: 4*9.72MHz = 38.88MHz)
– 2*32 kb 70 ns external RAM