Nokia 2140 System Module DS9 08
SYSTEM MODULE DS9
NHK–1
9712OJ
Technical Documentation
Contents of System Module DS9
System module DS9 8–2
Introduction 8–2
Technical section 8–2
External and internal connectors 8–2
Internal signals between RF and ASIC 8–5
Internal signals between RF and RFI 8–6
Baseband block 8–7
Interconnection diagram 8–7
Technical specifications 8–7
Functional descriptions 8–8
Names of functional blocks 8–10
RF block 8–26
Functional description 8–26
Block diagram of baseband 8–29
Block diagram of RF 8–30
Power distribution diagram 8–31
Connections between system and RF blocks 8–32
Parts list of DS9 8–33
8–1
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Circuit Diagram of DS9; System Blocks A3/8–1
Circuit Diagram of DS9; CPU and Memories (Version 4.5 edit 65) A3/8–2
Circuit Diagram of DS9; Power Supply IC & Battery Charg. Unit A3/8–3
Circuit Diagram of DS9; Audio Codec IC A3/8–4
Circuit Diagram of DS9; DSP, Clock Generator & Memories A3/8–5
Circuit Diagram of DS9; ASIC IC (Version 4.5 edit 68) A3/8–6
Circuit Diagram of DS9; RFI IC (Version 4.5 edit 40) A3/8–7
Circuit Diagram of DS9; RF Receiver A3/8–8
Circuit Diagram of DS9; RF Receiver (Version 4.3 edit 52) A3/8–9
Circuit Diagram of DS9; RF Transmitter A3/8–10
Circuit Diagram of DS9; RF Transmitter (Version 4.3 edit 94) A3/8–11
Layout Diagrams of DS9 Side 1 A3/8–12
Layout Diagrams of DS9 Side 2 A3/8–13
Layout Diagrams of DS9 Side 1 (Version 13) A3/8–14
Layout Diagrams of DS9 Side 2 (Version 13) A3/8–15
SYSTEM MODULE DS9
NHK–1
System module DS9
Related documentation
Introduction
DS9 is the baseband/RF module NHK–1 cellular tranceiver. The DS9 module
carries out all the system and RF functions of the tranceiver. System module
DS9 is designed for a handportable phone, that operate in PCN system.
Technical section
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Technical Documentation
8–2
Copyright Nokia Mobile Phones
All functional blocks of the system module are mounted on a single multi layer
printed circuit board. The chassis of the radio unit contains separating walls for
baseband and RF. All components of the baseband are surface mountable. The
connections to accessories are fed through the bottom connector of the radio
unit. The connections to user interface –module (UIF) are fed through a flex
connector. There is no physical connector between RF and baseband.
External and internal connectors
The system module has two connector, external bottom connector and internal
UIF module connector.
SYSTEM MODULE DS9
NHK–1
Bottom connector X100
Antenna
connector
2
1
16
System connector
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4
Battery connector
3
2
1
4
Charging connector
X100
9
18
3
30
12
X196
UIF module connector
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1
D0000323
8–3
System connector
Pin: Name: Description:
1, 9 GND Digital ground
2 MIC/JCONN External audio input from accessories or
3 AGND Analog ground for accessories.
4 TDA Transmitted DBUS data to the accessories.
5 M2BUS Serial bidirectional data and control between
6 HOOK/RXD2 HOOK indication. The phone has a 100 kΩ
7 PHFS/TXD2 Handsfree device power on/off, data to flash
8, 16 VCHAR Battery charging voltage.
10 EAR/HFPWR External audio output to accessories or
handsfree microphone. Multiplexed with
junction box connection control signal.
the handportable and accessories.
pull–up resistor.
programming device.
handsfree speaker.
11 DSYNC DBUS data bit sync clock
12 RDA DBUS received data from the accessories
13 NC No connection
14 VF Programming voltage for FLASH.
15 DCLK DBUS data clock
SYSTEM MODULE DS9
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Battery connector
Pin: Name: Description:
1 GND Ground
2 TBAT Battery temperature
3 BTYPE Battery type
4 VBATT Battery voltage
Charging connector
Pin: Name: Description:
1 VCHAR Battery charging voltage
2 GND Ground
3 VCHAR Battery charging voltage
4 GND Ground
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Antenna connector
Pin: Name: Description:
1 RF EXT External antenna signal
2 GND Ground
UIF module connector X196
Pin: Name: Description:
1 VL1 Logic supply voltage 4.65 V
2, 29 GND Ground
3, 30 VBATT Battery voltage
4 BACKLIGHT Backlights on/off
5 – 11 UIF(0;6) Lines for keyboard read and LCD controller
12 MIC ENA Microphone bias enable
13 – 16 COL(0;3) Lines for keyboar read
17 CALL LED Call LED enable
18 MICP Microphone (positive node)
19 MICN Microphone (negative node)
20 EARP Earpiece (negative node)
21 EARN Earpiece (positive node)
22 BUZZER PWM signal buzzer control
SYSTEM MODULE DS9
NHK–1
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23 XPWRON Power key (active low)
24 VA1 Analog supply voltage 4.65 V
25 SIMCLK Clock for SIM data
26 SIMRESET Reset for SIM
27 VSIM SIM voltage supply voltage
28 SIMDATA Serial data for SIM
Internal signals between RF and ASIC
Symbol: Description: Values:
SCLK Synthesizer clock
• load impedance:
• frequency:
SDATA Synthesizer data
• load impedance:
• data rate frequency:
8–5
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10 k
Ω
3.25 MHz
10 k
Ω
3.25 MHz
SENAR RX synthesizer enable
• VHF PLL contr. disabled:
• VHF PLL activated:
• current:
SENAT TX synthesizer enable
• UHF PLL contr. disabled:
• UHF PLL activated:
• current:
RXPWR RX supply voltage on/off
• RX supply voltage on:
• RX supply voltage off:
• current:
SYNTHPWR Supply voltage on/off
• RF regulators on:
• RF regulators off:
• current:
TXPWR TX supply voltage on/off
• TX supply voltage on:
• TX supply volatge off:
• current:
4.5...4.65...4.8 V
0...0.2...0.7 V
50 µA
4.5...4.65...4.8 V
0...0.2...0.7 V
50 µA
4.5...4.65...4.8 V
0...0.2...0.7 V
0.5 mA
4.5...4.65...4.8 V
0...0.2...0.7 V
1.0 mA
4.5...4.65..4.8 V
0...0.2...0.7 V
0.5 mA
TXP TX enable
• transmitter power enable:
• transmitter power disable:
CLKIN 26 MHz clock to ASIC
4.5...4.65...4.8 V
0...0.2...0.7 V
SYSTEM MODULE DS9
NHK–1
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Technical Documentation
Internal signals between RF and RFI
Symbol: Description: Values:
AFC Automatic frequency control voltage
• voltage min/max:
• resolution:
• load impedance (dynamic):
TXC TX transmit power control voltage
• voltage range min/max:
• impedance:
TXQP,TXQN Differential TX quadrature signal
• differential voltage swing:
• d.c. level:
• load impedance:
TXIP,TXIN Differential TX inphase signal
• differential voltage swing:
• d.c. level:
• load impedance:
8–6
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0.35...4.35 V
11 bits
10 k
Ω
0.3...4.2 V
10 k
Ω
1.15...1.2...1.25 V
PP
2.30...2.35...2.40 V
30 k
Ω
1.15...1.2...1.25 V
PP
2.30...2.35...2.40 V
30 k
Ω
PDATA0 Parallel AGC data
• reduced front end gain:
• normal front end gain:
• current:
PDATA1 Parallel AGC data
• AGC 3 dB reduction:
• normal front end gain:
• current:
PDATA2 Parallel AGC data
• AGC 6 dB reduction:
• normal front end gain:
• current:
PDATA3 Parallel AGC data
• AGC 12 dB reduction:
• normal front end gain:
• current:
PDATA4 Parallel AGC data
• AGC 24 dB reduction:
• normal front end gain:
• current:
4.5...4.65...4.8 V
0...0.2...0.7 V
0.1 mA
4.5...4.65...4.8 V
0...0.2...0.7 V
10 µA
4.5...4.65...4.8 V
0...0.2...0.7 V
10 µA
4.5...4.65...4.8 V
0...0.2...0.7 V
10 µA
4.5...4.65...4.8 V
0...0.2...0.7 V
10 µA
PDATA5 Parallel AGC data
• AGC 12 dB reduction:
• normal front end gain:
• current:
4.5...4.65...4.8 V
0...0.2...0.7 V
10 µA
SYSTEM MODULE DS9
NHK–1
RXQ RX quadrature signal
RXI RX inphase signal
Baseband block
The purpose of the baseband module is to control the phone and process audio
signals to and from RF. The module also controls the user interface.
Interconnection diagram
Technical specifications
There are three different operation modes:
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Technical Documentation
• output level:
• source impedance:
• output level:
• source impedance:
8–7
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25 mV
470
25 mV
470
PP
Ω
PP
Ω
– Active mode
– Idle mode
– Power off mode
In the active state all the circuits are supplied with power and part of the mod-
ule might be in idle state.
The module is usually in the idle mode when there is no call. In the idle mode
circuits are reset, powered down and clocks are stopped or the frequency reduced.
In power off mode only the circuits needed for power up are supplied with
power.
SYSTEM MODULE DS9
NHK–1
Functional descriptions
Clocking sceme
DSP Clock
60.2 MHz
differential sine
ear
AUDIO
CODEC
wave
mouth
oscillator
DSP
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Technical Documentation
RFI Clock 13 MHz
Sleep Mode: 135.4kHz
enable
RFI
ASIC
8–8
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RF System Clock
26 MHz
VCTCXO
SIMCLKSIMCLK
Codec Sync Clock
8 kHz
DBUSCLK 512kHz
DBUSSYNC 8kHz
All of the clock outputs can be disabled/enabled. DSP uses differential sinusoidal clock. DSP–clock buffer can be enabled/disabled.
Codec Main Clock and
data Transfer clock
512kHz
3.25 / 1.625
MHz
MCU Clock
26 MHz
MCU
SYSTEM MODULE DS9
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Reset and power control
reset in
DSP
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RFI
Reset Out
Reset Out
ASIC
Vcc
Reset in
resetreg
8–9
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SIMReset
PSL+
VL1
XRES reset in
XPWRON
XPwrOff
approx 2Hz
The supply power is switched on by PWR key on keyboard. All devices are
powered up at the same time by PSL+.
PSL+ supplies the reset to ASIC at power up. ASIC starts the clocks to DSP
and MCU. After some time ASIC releases the resets to all circuitry. Power up
reset resets MCU and RFI. DSP has own, independent reset from the asic.
For powering of the phone, the user pushes PWR–key. MCU detects that it is
pushed. After that the MCU cuts the eventual ongoing call, exits all tasks, acts
dead to the user and leaves PSL+ watchdog without resets. After power–down
delay PSL+ cuts the supply voltage from all the circuitry.
XPWRON
MCU
SYSTEM MODULE DS9
NHK–1
Watchdog system
XPWROFF
PSL
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4
reset
DSP
1
5
2
POWER
3
8–10
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ASIC
4
reset
MCU
Normal operation:
1. MCU tests DSP
2. MCU updates ASIC watchdog timer (> 2Hz)
3. MCU pulses the XPWROFF input on the PSL+ (about 2Hz)
Failed operation:
4. ASIC resets MCU and DSP (after about 0.5 sec failure)
5. PSL+ switches the power off (after 1.5 sec failure)
Names of functional blocks
Name: Function:
CTRLU Control unit for the phone
PWRU Power supply
DSPU Digital signal processing block
AUDIO Audio coding
ASIC EDSA –asic
RFI RF –baseband interface
SYSTEM MODULE DS9
NHK–1
CTRLU
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Technical Documentation
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8–11
The control block provides a microcomputer unit (MCU) and it’s environment.
The environment consists of three memory circuits (FLASH, SRAM, EEPROM),
20 bit address bus and 8 bit data bus.
Main Features of the CTRLU block:
MCU functions:
– system control
– communication control
– user interface
– authentication
– RF monitoring
– power up/down control
– accessory monitoring
– batttery monitoring and charging control
– self–test and production testing
– flash loading
Main components of CTRLU
– Hitachi H8/536
H8/536 is a CMOS microcomputer unit (MCU) comprising a CPU
core and on–chip supporting modules with 16 bit architecture. The
data bus to outside world has 8 bits.
– 512 k x 8 bit FLASH memory
– 100 ns maximum read access time.
– contains the main program code for the MCU; part of the DSP
program code locates also in FLASH.
– In teh product two 256 k x 8 bit FLASH memories will be used
ASIC can address also two 4 Mbit or one 8 Mbit memories.
– 32 k x 8 bit SRAM memory
– 100 ns maximum read access time.
– 8 k x 8 bit EEPROM memory
– 150 ns maximum read access time.
– contains user defined information.
SYSTEM MODULE DS9
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Input signals of CTRLU
Name(from): Description:
VL1(PWRU) Power supply voltage for CTRLU block
VREF(PWRU) Reference voltage for MCU A/D converter
VBATDET(PWRU) Battery voltage detection
VC(PWRU) Charger voltage monitoring
EROMSELX(ASIC) Chip select for the EEPROM memory
ROMSELX(ASIC) Chip select for the FLASH memory
ROM2SELX(ASIC) Chip select for the 2nd FLASH memory
RAMSELX(ASIC) Chip select for the SRAM memory
RESETX(ASIC) Reset signal for MCU
NMI(ASIC) Non–maskable interrupt request
MCUCLK(ASIC) Main clock for MCU
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IRQX(ASIC) Interrup request
PCMCDO(AUDIO) Audio codec control data receiving
TRF(RF) RF module temperature detection
VF(syst.conn.) Programming voltage for FLASH memory
RXD2_HOOK The use of handsfree monitoring
(syst.conn.) FLASH programming data input on the production line
TBAT(batt.conn.) Battery temperature detection
BTYPE(batt.conn.) Battery size identification
JCON(syst.conn.) Junction box connection identification
Output signals of CTRLU
Name(to): Description:
XPWROFF(PWRU) Power off control, PSL+ watchdog reset
PWM(PWRU) Charger on/off control
WSTROBEX(ASIC) MCU write strobe
RSTROBEX(ASIC) MCU read strobe
MCUAD(19:0)(ASIC)20 bit MCU address bus
MBUSDET(ASIC) MBUS activity detection
PCMCLK(AUDIO) Clock for audio cedec control data transfer
PCMCDI(AUDIO) Audio codec control data transmitting
XSELPCMC(AUDIO)Chip select for audio codec
SYSTEM MODULE DS9
NHK–1
TXD2_PHFS Power on/off control for HF device, verification output
(syst.connector) of the programmed data of FLASH during programming
CALL_LED(UIF) Call ’coming’ indicator light control
BACKLIGHT(UIF) LCD and display backlight on/off control
BUZZER(UIF) Buzzer signal
Bidirectional signals of CTRLU
Name(to/from): Description:
MCUDA(7;0)(ASIC) MCU’s 8 bit data bus
M2BUS Asyncronous serial data bus
Block description of CTRLU
– MCU – memories
MCU has a 20 bits wide address bus A(19:0) and an 8–bit data bus
with memories. The address bits A(19:16) are used for chip select
decoding. The decoding is done in EDSA–asic.
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On the Hitachi HD647536 internal memory map there is the following:
• 00000 – 0F67F 62k bytes internal ROM
• 0F680 – 0FE7F 2k bytes internal RAM
• 0FE80 – 0FFFF 384 bytes registers
External memory map is the following:
• 10000 – 17FFF 32k bytes RAM
• 20000 – 21FFF 8k bytes E
• 30000 – 300FF 256 bytes ASIC
• 40000 – 7FFFF 256k bytes FlashROM
• 80000 – BFFFF 256k bytes FlashROM
– CTRLU – PWRU
MCU controls the watchdog timer in PSL+. It sends a positive pulse
at approximately 2 Hz to XPWROFF pin of the PSL+ to keep the
power on. If MCU fails to deliver this pulse, the PSL+ will remove
power from the system. MCU controls also the charger on/off switching in the PWRU block. When power off is requested MCU leaves
PSL+ watchdog without reset. After the watchdog has elapsed PSL+
cuts off the supply voltages from the phone.
2
PROM
SYSTEM MODULE DS9
NHK–1
– CTRLU – ASIC
MCU and ASIC have a common 8 bit data bus and a 9 bit address
bus. A(4:0) are used for normal addressing whereas bits A(19:16)
are decoded in ASIC to chip select inputs for CTRLU memories.
ASIC controls the main clock, main reset and interrupts to MCU. The
internal clock of MCU is half the MCUCLK clock speed. RESETX resets everything in MCU except the contents of the RAM. IRQX is
general purpose interrupt request line from ASIC. After IRQX request
the interrupt register of asic is read to find out the reason for interrupt. NMI–interrupt is used only to wake up MCU from software
standby mode.
– CTRLU – DSPU
MCU and DSP communicate through ASIC. ASIC has MCU–mailbox
and DSP–mailbox. MCU writes data to DSP–mailbox where DSP can
only read the incoming data. In MCU–mailbox data transfer direction
is opposite.
– CTRLU – AUDIO
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When the the chip select signal XSELPCMC goes low, MCU writes
or reads control data to or from the speech codec at the rate defined
by PCMCLK. PCMCDI is output data line from MCU to codec and
PCMCDO is input data line from codec to MCU.
– CTRLU – RF/BATTERY monitoring
MCU monitors RF and battery functions (BTEMP, BSI ,VBATDET,VC
and TRF) with the internal 8 channel 10 bit AD converter.
– CTRLU – keyboard and LCD driver interface
MCU and user interface communication is controlled through ASIC.
– CTRLU – ACCESSORIES
M2BUS is used to control external accessories. This interface can be
used also to factory testing and service and maintenance purposes.
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