Nokia 2110i, 2110 SYSTEM MODULE GR8

SYSTEM MODULE GR8

NHE–4

01/98OJ Technical Documentation

Contents of System Module GR8

System Module GR8 8–3 Introduction 8–3 Technical Section 8–3 WARNINGS 8–3 External and Internal Connectors 8–3 Internal Signals Between RF and ASIC 8–7 Internal Signals Between RF and RFI 8–8 Functional Description of Baseband Block 8–9 Technical Specifications 8–9 Names of Functional Blocks 8–9 Clocking Sceme 8–10 Reset and Power Control 8–11 Watchdog System 8–12 CTRLU 8–13 PWRU 8–19 DSPU 8–21 AUDIO 8–24 ASIC 8–26 RFI 8–31 Functional Description of RF block 8–33 RF Frequency Plan 8–33 Regulators 8–33 Power Distribution 8–34 Current Consumption 8–34 Receiver 8–35 Transmitter 8–39 Synthesizer 8–44 Block Diagram of Baseband 8–48 Power Distribution Diagram of Baseband 8–49 Block Diagram of RF 8–50 Power Distribution Diagram of RF 8–51 Connections between System and RF Blocks 8–52 Connections between RF and TX Blocks 8–53 Circuit Diagram of GR8; System Blocks 8–54 Circuit Diagram of GR8; CPU & Memories 8–55 Circuit Diagram of GR8; Power Supply IC & Batt. Charg. unit 8–56 Circuit Diagram of GR8; DSP, Clock Generator & Memories 8–57 Circuit Diagram of GR8; Audio Codec IC 8–58 Circuit Diagram of GR8; ASIC IC 8–59

8–1

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8–2

Circuit Diagram of GR8; RFI IC 8–60 Circuit Diagram of GR8; RF Receiver and Regulator 8–61 Circuit Diagram of GR8; RF Transmitter 8–62 Layout Diagram of GR8 Side 1 Version 09 8–63 Layout Diagram of GR8 Side 2 Version 09 8–64 Parts List of GR8 EDMS Issue: 6.8 8–65

SYSTEM MODULE GR8

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System Module GR8

Introduction

GR8 is the baseband/RF module NHE–4 cellular tranceiver. The GR8 module carries out all the system and RF functions of the tranceiver. System module GR8 is designed for a handportable phone, that operate in GSM system.

Technical Section

All functional blocks of the system module are mounted on a single multi layer printed circuit board. The chassis of the radio unit has separating walls for baseband and RF. All components of the baseband section are surface mountable. They are soldered using reflow. The connections to accessories are taken through the bottom connector of the radio unit. The connections to the User Interface module (UIF) are fed through a flex connector. There is no physical connector between the RF and baseband sections.

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WARNINGS

The maximum battery voltage during the transmission should not exceed 8.0 V. Higher battery voltages may destroy the power amplifier. This will be quaranteed by hardware based limiting which has maximum value 7.6

External and Internal Connectors

The system module has two connector, external bottom connector and internal UIF module connector.

Battery connector

Antenna connector

X100

Charging connector

0.3 V.

System connector

X196

UIF module connector

D0000323

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Bottom Connector X100

System Connector

Pin: Name: Description: 1, 9 GND Digital ground

2 MIC/JCONN External audio input from accessories or

3 AGND Analog ground for accessories. Connected

4 TDA Transmitted DBUS data to the accessories. 5 M2BUS Serial bidirectional data and control between

6 HOOK/RXD2 HOOK indication. The phone has a 100 kΩ

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handsfree microphone. Multiplexed with junction box connection control signal.

16.8 kΩ pull down in phone.

directly to digital ground on the PCB.

the handportable and accessories.

pull–up resistor. Data to flash from flash programmer.

8–4

7 PHFS/TXD2 Handsfree device power on/off. Data to flash

programming device. 8, 16 VCHAR Battery charging voltage. 10 EAR/HFPWR External audio output to accessories or

handsfree speaker. 100 kΩ pull–down resistor

in phone to turn on the junction box. 11 DSYNC DBUS data bit sync clock. 12 RDA DBUS received data from the accessories. 13 NC Not used. 14 VF Programming voltage for flash. 15 DCLK DBUS data clock.

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Battery Connector

Pin: Name: Description: 1 GND Ground

2 TBAT Battery temperature 3 BTYPE Battery type 4 VBATT Battery voltage

Charging Connector

Pin: Name: Description: 1 VCHAR Battery charging voltage

2 GND Ground 3 VCHAR Battery charging voltage 4 GND Ground

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Antenna Connector

Pin: Name: Description: 1 RF EXT External antenna signal

2 GND Ground

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UIF Module Connector X196

Pin: Name: Description: 1 VL1 Logic supply voltage 4.65 V

2 GND Ground 3, 30 VBATT Battery voltage 4 BACKLIGHT Backlights on/off 5 – 8 UIF(0;3) Lines for keyboard read and LCD controller 9 UIF4 Line for keyboard read and LCD controller

10 UIF5 Line for keyboard read and LCD controller

11 UIF6 LCD controller enable strobe 12 MIC ENA Microphone bias enable

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read/write strobe

data/instruction register selection

8–6

13 – 16 COL(0;3) Lines for keyboard write 17 CALL LED Call LED enable 18 MICP Microphone (positive node) 19 MICN Microphone (negative node) 20 EARP Earpiece (negative node) 21 EARN Earpiece (positive node) 22 BUZZER PWM signal buzzer control 23 XPWRON Power key (active low) 24 VA1 Analog supply voltage 4.65 V 25 SIMCLK Clock for SIM data 26 SIMRESET Reset for SIM 27 VSIM SIM voltage supply voltage 28 SIMDATA Serial data for SIM 29 AGND Analog ground

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Internal Signals Between RF and ASIC

Symbol: Description: Values: SCLK Synthesizer clock

• load impedance:

• frequency:

SDATA Synthesizer data

• load impedance:

• data rate frequency:

SENA1 Synthesizer enable

• PLL contr. disabled:

• PLL activated:

• current:

RXPWR RX supply voltage on/off

• RX supply voltage on:

• RX supply voltage off:

• current:

8–7

10 k

Ω

3.25 MHz

10 k

Ω

3.25 MHz

4.5...4.65...4.8 V

0...0.2...0.7 V 50 µA

4.5...4.65...4.8 V

0...0.2...0.7 V

0.5 mA

SYNTHPWR Supply voltage on/off

• RF regulators on:

• RF regulators off:

• current:

TXPWR TX supply voltage on/off

• TX supply voltage on:

• TX supply voltage off:

• current:

TXP TX enable

• transmitter power enable:

• transmitter power disable:

CLKIN 26 MHz clock to ASIC

4.5...4.65...4.8 V

0...0.2...0.7 V

1.0 mA

4.5...4.65...4.8 V

0...0.2...0.7 V

0.5 mA

4.5...4.65...4.8 V

0...0.2...0.7 V

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Internal Signals Between RF and RFI

Symbol: Description: Values: AFC Automatic frequency control voltage

• voltage min/max:

• resolution:

• load impedance (dynamic):

TXC TX transmit power control voltage

• voltage range min/max:

• impedance:

TXQP,TXQN Differential TX quadrature signal

• differential voltage swing:

• D.C. level:

• load impedance:

TXIP,TXIN Differential TX inphase signal

• differential voltage swing:

• D.C. level:

• load impedance:

8–8

0.35...4.35 V 11 bits 10 k

Ω

0.3...4.2 V 10 k

Ω

1.15...1.2...1.25 V

2.30...2.35...2.40 V 30 k

Ω

1.15...1.2...1.25 V

2.30...2.35...2.40 V 30 k

Ω

PDATA0 Front end AGC control

• reduced front end gain:

• normal front end gain:

• current:

RXQ RX quadrature signal

• output level:

• source impedance:

RXI RX inphase signal

• output level:

• source impedance: 470 Ω

0...0.2...0.7 V

4.5...4.65...4.8 V

0.1 mA

25 mV 470

25 mV

Ω

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Functional Description of Baseband Block

The purpose of the baseband module is to control the phone and process audio signals to and from RF. The module also controls the user interface.

Technical Specifications

There are three different operation modes: – active mode – idle mode – power off mode In the active state all circuits are powered and part of the module may be in idle

mode. The module is usually in the idle mode when there is no call and the phone is in

SERV. In the idle mode circuits are reset, powered down and clocks are stopped or the frequency reduced. All the clocks except the main clock from VCTCXO can be stopped in that mode. Whether the SIM clock is stopped or not depends on the network.

8–9

In power off mode only the circuits needed for power up are powered. This means that only power up block inside the PSL+ is powered. The power key on the flex is pulled up with a pull up resistor inside the PSL+.

Names of Functional Blocks

Name: Function: CTRLU Control unit for phone

PWRU Power supply DSPU Digital signal processing block AUDIO Audio coding ASIC D2CA GSM/PCN system ASIC; several functions RFI RF baseband interface

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Clocking Scheme

DSP Clock

60.2 MHz differential sine wave

OSCILLATOR

ear

mouth

AUDIO CODEC

DSP

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RFI Clock 13 MHz

Sleep Mode: 135.4kHz

enable

RFI

ASIC

8–10

RF System Clock

26 MHz

VCTCXO

SIMCLKSIMCLK

3.25 / 1.625 MHz

Codec Sync Clock

8 kHz

DBUSCLK 512kHz

DBUSSYNC 8kHz

Most of the clocks are generated from the 26 MHz VCTCXO frequency by the ASIC:

– 26 MHz clock for the MCU. MCU‘s internal clock frequency is half of

– 13 MHz for the RFI. The ASIC also generates 135.4 kHz sleep mode clock

– 3.25 MHz clock for SIM. When there is no data transfer between the SIM

– 512 kHz main clock for the codec and for the data transfer between the DSP

MCU Clock

Codec Main Clock and data Transfer clock

512kHz

26 MHz

MCU

that (13 MHz).

for the RFI.

card and the HP the clock can be reduced to 1.625 MHz. Some SIM cards also allows the clock to be stopped in that mode.

and the codec.

– 8 kHz synchronization clock for data transfer between the DSP and the co-

dec.

– 512 kHz clock and 8 kHz sync. clock for the DBUS data transfer.

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The DSP has its own crystal oscillator which can be turned off and on by the ASIC. The DSP uses differential sinusoidal clock. The frequency is 60.2 MHz.

The system ASIC generates 8 kHz clock to the codec for the control data transfer.

In the idle mode all the clocks can be stopped except 26 MHz main clock coming from the VCTCXO.

Reset and Power Control

reset in

DSP

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RFI

Reset Out Reset Out

ASIC

Vcc Reset in

resetreg

8–11

SIMReset

PSL+

VL1

XRES reset in

XPWRON

XPwrOff

approx 2Hz

There are three different ways to switch power on: – Power key pressing grounds the XPWRON line. The PSL+ detects that and

switches the power on.

– Charger detection on PSL+ detects that charger is connected and switches

power on.

– PSL+ will switch power on when the battery is connected. After that the

MCU will detect if power key is pressed or charger connected. If not the power will be switched off.

All devices are powered up at the same time by the PSL+. It supplies the reset to the ASIC at power up. The ASIC starts the clocks to the DSP and the MCU. After 100 ms PSL+ releases the reset to ASIC.

XPWRON

MCU

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ASIC releases MCU and RFI reset after 256 13 MHz clock cycles. DSP reset release time from DSP clock activation can be selected from 0 to 255 13MHz clock cycles. In our case it is 255. SIM reset release time is according to GSM SIM specifications.

To turn power off the user presses the PWR key. The MCU detects this. The MCU cuts off any ongoing call, exits all tasks, acts inoperative to the user and leaves the PSL+ watchdog without resets. After power–down delay, the PSL+ cuts off the supply from all circuitry.

If charging is on the phone stays on but it looks to the user like it is powered off (lights are off and the display is blank) except the charging indicator stays on.

Watchdog System

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reset

DSP

ASIC

POWER

PSL

XPWROFF

reset

MCU

Normal operation:

1. MCU tests DSP

2. MCU updates ASIC watchdog timer (> 2 Hz)

3. MCU pulses the XPWROFF input on the PSL+ (about 2 Hz) Failed operation:

4. ASIC resets MCU and DSP after about 0.5 s failure

5. PSL+ switches power off about 1.5 s after the previous XPWROFF pulse

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CTRLU

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The Control block contains a microcontroller unit (MCU) and three memory circuits (FLASH, SRAM, EEPROM), a 20 bit address bus, an 8 bit data bus and memory circuit control signals.

Main Features of the CTRLU block: MCU functions: – system control – communication control – user interface – authentication – RF monitoring – power up/down control – accessory monitoring – battery monitoring and charging control – self–test and production testing – flash loading

Main Components of CTRLU

– Hitachi H8/536

H8/536 is a CMOS microcontroller unit (MCU) comprising a CPU core and on–chip supporting modules with 16–bit architecture. The data bus to outside world has 8 bits.

– 1024k*8bit FLASH memory

– 150 ns. maximum read access time with 1 wait state – contains the main program code for the MCU; part of the DSP

program code also located on FLASH

– ASIC can address two 4 Mbit memories or one 8 Mbit memory.

– 32 k x 8 bit SRAM memory

– 100 ns. maximum read access time

– 8 k x 8 bit EEPROM memory

– 250 ns. maximum read access time with 1 wait state – contains user defined information. – there is a register bit on the ASIC which must be set before the

write operation to the EEPROM.

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Input Signals of CTRLU

Name(from): Description: VL1(PWRU) Power supply voltage for CTRLU block

VREF(PWRU) Reference voltage for MCU A/D converter VBATDET(PWRU) Battery voltage detection VC(PWRU) Charger voltage monitoring ROMAD18(ASIC) ROM address (paging) EROMSELX(ASIC) Chip select for the EEPROM memory ROMSELX(ASIC) Chip select for the FLASH memory ROM2SELX(ASIC) Chip select for the second FLASH memory RAMSELX(ASIC) Chip select for the SRAM memory RESETX(ASIC) Reset signal for MCU NMI(ASIC) Non–maskable interrupt request

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MCUCLK(ASIC) Main clock for MCU IRQX(ASIC) Interrupt request PCMCDO(AUDIO) Audio codec control data receiving TRF(RF) RF module temperature detection VF(syst.conn.) Programming voltage for FLASH memory RXD2_HOOK The use of handsfree monitoring

(syst.conn.) FLASH programming data input on the production line TBAT(batt.conn.) Battery temperature detection. Vibra cont. for vibrabattery. BTYPE(batt.conn.) Battery size identification MIC_JCONN Junction box connection identification

(sys.conn.)

Output Signals of CTRLU

Name(to): Description: XPWROFF(PWRU) Power off control, PSL+ watchdog reset

PWM(PWRU) Charger on/off control VOLTLIM(PWRU) Voltage limiting; affects to HW voltage limit level WSTROBEX(ASIC) MCU write strobe RSTROBEX(ASIC) MCU read strobe MCUAD(19:0)(ASIC)20 bit MCU address bus MBUSDET(ASIC) MBUS activity detection

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BATDET(ASIC) Battery type and SIM card presence detection PCMCLK(AUDIO) Clock for audio codec control data transfer PCMCDI(AUDIO) Audio codec control data transmitting XSELPCMC(AUDIO)Chip select for audio codec TXD2_PHFS Power on/off control for HF device, verification output

(syst.connector) of the programmed data of FLASH during programming CALL_LED(UIF) ’Incoming’ call indicator light control BACKLIGHT(UIF) LCD and display backlight on/off control BUZZER(UIF) Buzzer signal

Bidirectional Signals of CTRLU

Name(to/from): Description: MCUDA(7;0)(ASIC) MCU’s 8 bit data bus

8–15

M2BUS(sys. conn) Asynchronous serial data bus

Block Description of CTRLU

– MCU – memories

The MCU has a 20 bits wide address bus A(19:0) and an 8 bit data bus with memories. The address bits A(19:16) are used for chip select decoding. The decoding is done in the D2CA ASIC. The ASIC can address two 4 Mbit (or smaller) or one 8 Mbit flash memories. Hitachi HD647536 processor has internal ROM and RAM memories. One wait state is used with external memory access.

On the Hitachi HD647536 internal memory map there is the following:

• 00000 – 001FF Vector tables

• 00200 – 0F67F 62 k bytes internal ROM

• 0F680 – 0FE7F 2 k bytes internal RAM

• 0FE80 – 0FFFF 384 bytes register field

• 10000 – 1FFFF 32 k * 8 bytes RAM

• 20000 – 2FFFF 8 k * 8 bytes EEPROM

• 30000 – 3FFFF 26 * 8 bytes ASIC

• 40000 – 7FFFF 2 Mbit Flash, paged by ASIC page bit to 4 Mbit

• 80000 – FFFFF 4 Mbit Flash

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Chip select generation: Chip select: Page: A19: A18: A17: A16:

RAM X 0001 EEPROM X 0010 ASIC X 0011 FLASH1 (8 Mbit) X 1 X X X

– Flash programming

In flash programming a special flash programming box and a PC is needed. Loading is done through the bottom connector of HP; multiplexed with HOOK and PHFS line. First MCU goes to minimum mode (MBUS command from PC or if MBUS is connected to MIC_JCONN line in power up). Then the flash software is loaded from PC to flash loading box. When the loading is complete flash loading to HP can be started by MBUS command from PC to the MCU. After that the MCU asks the test box to start flash loading to HP. The box supplies 12 V programming voltage for flash and starts to send 250 bytes data blocks to the MCU via HOOK line. The baud rate is 406 kbit/s. The MCU calculates the check sum, sends acknowledge via PHFS line and sends the data to flash. When all the data is loaded the HP makes reset and tells the flash loading box if the loading was succeeded or not. Only PSL+, ASIC and MCU must be active during the loading.

8–16

– CTRLU – PWRU

MCU controls the watchdog timer in PSL+. It sends a positive pulse at approximately 2 Hz to XPWROFF pin of the PSL+ to keep the power on. If MCU fails to deliver this pulse, the PSL+ will remove power from the system. MCU also controls the charger on/off switching in the PWRU block. When power off is requested or MCU leaves PSL+ watchdog without reset. After the watchdog time has elapsed PSL+ cuts off the supply voltages from the phone.

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– CTRLU – ASIC

MCU and ASIC have a common 8–bit data bus and a 9–bit address bus. Bits A(4:0) are used for normal addressing whereas bits A(19:16) are decoded in ASIC to chip select inputs for CTRLU memories. ASIC controls the main clock, main reset and interrupts to MCU. The internal clock of MCU is half the MCUCLK clock speed. RESETX resets everything in MCU except the contents of the RAM. IRQX is a general purpose interrupt request line from ASIC. After IRQX request the interrupt register of the ASIC is read to find out the reason for interrupt. NMI interrupt is used only to wake up MCU from software standby mode.

– CTRLU – DSPU

MCU and DSP communicate through ASIC. ASIC has an MCU mailbox and a DSP mailbox. MCU writes data to DSP mailbox where DSP can only read the incoming data. In MCU mailbox the data transfer direction is the opposite. When power is switched on the MCU loads data from the flash memory to DSP‘s external memory through this mailbox.

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– CTRLU – AUDIO

When the the chip select signal XSELPCMC goes low, MCU writes or reads control data to or from the speech codec registers at the rate defined by PCMCLK. PCMCDI is an output data line from MCU to codec and PCMCDO is an input data line from codec to MCU.

– CTRLU – RF/BATTERY monitoring

MCU has internal 8 channel 10 bit AD converter. Following signals are used to monitor battery, charging and RF:

– BTYPE battery size – TBAT battery temperature (used also for

vibrabattery control) – VBATDET battery voltage – VC charging voltage – TRF RF temperature

– CTRLU – keyboard and LCD driver interface

MCU and user interface communication is controlled through ASIC.

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– CTRLU – ACCESSORIES

M2BUS is used to control external accessories. This interface can also be used for factory testing and maintenance purposes.

There are also some control and indication signals for the accessories:

– PHFS is used to turn power on to HF accessories. – JCONN is used to indicate that junction box is connected. Phone

can also enter minimum mode when M2BUS is connected to

MIC_JCONN line. – HOOK is used to indicate accessories hook state. – TBAT is used to control vibrabattery. (Used also for monitoring

battery temperature.)

8–18

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PWRU

The power block creates the supply voltages for the baseband block and contains the charging electronics.

Main Components of PWRU

– PSL+ ASIC

Generates voltages, contains power on switch, charger and battery voltage detector and watchdog.

– Transistor BCP69–25 and schottky STPS340U

The charging current is passed through these components.

– Transistor BCX51 and BCP69–25

VL regulators of PSL+ external output transistors.

Input Signals of PWRU

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Name(from): Description: XPWRON(UIF) PWR on switch

XPWROFF(CTRLU) Power off control VOLTLIM(CTRLU) Voltage limiting; affects HW voltage limit level VBATT(syst.conn.) Battery voltage PWM(CTRLU) Charger on/off control VCHAR(syst.conn.) Charging voltage

Output Signals of PWRU

Name(from): Description: XRES(ASIC) Master reset

CHRDET(ASIC) Battery charger detection VL1(CTRLU,ASIC, Logic supply voltage, max 150 mA

RFI,UIF) VL2(DSPU) Logic supply voltage, max 150 mA VA1(AUDIO,UIF) Analog supply voltage, max 40 mA VA2(RFI) Analog supply voltage, max 80 mA VREF(CTRLU,RF) Reference voltage 4.65 V ±2 %, max 5 mA VBATDET(CTRLU) Switched VBATT divided by 2 VC(CTRLU) Attenuated VCHAR

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Block Description of PWRU

The PSL+ IC produces the following supply voltages: Name: Description:

VL1, VL2 150 mA for logic VA1 40 mA for audios VA2 80 mA for RFI VREF 5 mA reference In addition, it has internal watchdog, voltage detection and charger detection

functions. The watchdog will cut off output voltages if it is not reset once in every 1.5 (±0.75) second. The voltage detector resets the phone if the battery voltage falls below 4.8 V (±0.2 V). The charger detection starts the phone if it is in power–off state when the charging voltage is applied.

The charging electronics is controlled by the MCU. When the charging voltage is applied to the phone and the phone is powered up, the MCU detects it and starts controlling charging. If MCU detects too high charging voltage (over 14 volts) or current (over 78 A/D bit difference between VC and VBATDET) it will cut off the charging. The phone will accept charging voltages from 5 to 14 volts.

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If the phone is in power–off state, the PSL+ will detect the charging voltage and turn on the phone. If the battery voltage is high enough the reset will be released and the MCU will start controlling charging. If the battery voltage is too low the phone stays in reset state and the charging control circuitry will pass charging current to the battery. When the battery voltage has reached 5.25 V (± 0.2 V) the reset will be removed and the MCU starts controlling charging.

MCU controls the charging with pulse width modulation output. Charging voltage is limited by hardware in normal operation to 8.9 V and during a call to

7.6 V. Battery and charging voltages are calibrated in production; 6V is fed to the bat-

tery and charger pin and the MCU‘s A/D converter values are stored to EEPROM.

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DSPU

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Main interfaces of the DSP: – MCU via ASIC mailbox – ASIC – audio codec – data bus interface (DBUS) for accessories – digital audio interface (DAI) for type approval measurements Main features of the DSP block: – speech processing

– speech coding/decoding

– RPE–LTP–LPC (regular pulse excitation long term

prediction linear predictive coding) – voice activity detection (VAD) for discontinuous transmission

(DTX)

8–21

– comfort noise generation during silence – acoustic echo cancellation

– channel coding and transmission

– block coding (with ASIC) – convolutional coding – interleaving – ciphering (with ASIC) – burst building and writing it to ASIC

– Reception

– reading the A/D conversion results from ASIC – impulse response calculation – matched filtering – bit detection (with Viterbi on ASIC) – deinterleaving of soft decisions – convolutional decoding (with Viterbi) – block decoding (with ASIC)

– Adjacent cell monitoring

– signal strength measurements – neighbor timing measurements – neighbor parameter reception

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– control functions

– RF controls

– frame structure control

– test functions

– functions for RF measurements – debugging functions for product development

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– synthesizer control – power ramp programming – automatic gain control (AGC) – automatic frequency control (AFC)

– control the operations during a TDMA frame (with ASIC) – controlling the multiframe structure – channel configuration control

Main Components of DSPU

– AT&T DSP 1616–S11

– Digital signal processor with 12 kword internal ROM

– Two 32 k * 8 70 ns SRAMs for DSP external memory – 60.2 MHz crystal osc. to generate differential small signal clock for the DSP

Input Signals of DSPU

Name(from): Description: VL2(PWRU) Logic supply voltage, max 150 mA

DSPCLKEN(ASIC) Clock enable for DSP clock oscillator circuit DSP1RSTX(ASIC) Reset for the DSP PCMDATRCLKX PCM data input clock

(ASIC) DBUS data output clock CODEC_CLK PCM data output clock PCMOUT(AUDIO) Received audio in PCM format DBUSCLK DBUS data output clock DBUSSYNC DBUS data bit sync clock RDA DBUS received data INT0, INT1(ASIC) Interrupts for the DSP PCMCOSYCLKX PCM data bit sync clock

(ASIC)

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Output Signals of DSPU

Name(to): Description: PCMIN(AUDIO) Transmitted audio in PCM format

IOX(ASIC) I/O enable, indicates access to DSP address space RWX(ASIC) Read/write X DSPAD(16;9)(ASIC) Address bus and control signals DBUSDET(ASIC) DBUS activity detection

Bidirectional Signals of DSPU

Name(from/to): Description: DSPDA(15;0)(ASIC) 16 bit data bus

Block Description of DSPU

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The Control unit communicates with the DSP circuitry through a mailbox in the D2CA ASIC. The software for the external memories are loaded through this mailbox in start up.

The DSP includes two serial busses. One is used for speech data transfer between the DSP and the codec. The other is used as an external data bus and it is connected to the bottom connector. This bus can be used by data accessories and also as a digital audio interface (DAI) in audio type approval measurements. The clocks (512 kHz main clock and 8 kHz sync. clock) are generated by the ASIC.

In transmit mode the DSP codes the speech and routes the resulting transmit slots to the D2CA. The D2CA ASIC controls timing, and at specified intervals sends these bits to the RFI for DA conversion.

In digital receive mode the RFI AD converts the IF signal from the RF unit under the control of the D2CA. The DSP controls the D2CA and receives the converted bits. After channel and speech decoding, bits are converted into an analog signal in the PCM codec, routed and fed to the earpiece.

The DSP controls the RF through the D2CA ASIC, where all necessary timing functions are implemented, and control I/O lines are provided e.g. for synte loading.

The DSP emulator can be connected to DSP pins TCK, TMS, TDO, TDI, GND and VDD.

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AUDIO

The AUDIO block consists of an audio codec with some peripheral components. The codec contains microphone and earpiece amplifier and all the necessary switches for routing. The codec is controlled by the MCU. The PCM data comes from and goes to the DSP.

Main Components of AUDIO

– Audio codec ST5080

Includes e.g. PCM codec, audio routing switches, microphone and earpiece amplifiers for 2 connections (internal and external devices) and DTMF generator.

Input Signals of AUDIO

Name(from): Description:

01/98OJ Technical Documentation

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VA1(PWRU) Analog supply voltage, max 40 mA PCMIN(DSPU) Received audio in PCM format SYNC(ASIC) 8 kHz frame sync CODEC_CLK(ASIC) 512 kHz codec main clock PCMCDI(CTRLU) Audio codec control data PCMCLK(CTRLU) Clock for audio codec control data transfer XSELPCMC Audio codec chip select

(CTRLU) MIC_JCONN External microphone

(syst.conn.) MICN,MICP(UIF) Differential microphone signal

Output Signals of AUDIO

Name(to): Description: PCMOUT(DSPU) Transmitted audio in PCM format

PCMCDO(CTRLU) Audio codec control data MIC_ENA(UIF) Microphone enable EAR_HFPWR External received audio

(syst.conn.) EARN,EARP(UIF) Internal received audio JCONN(CTRLU) Junction box connected signal (multiplexed with HFMIC)

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