NEC VK19EA, VK18E Schematic
1
2
3
4
5
6
7
8
Intel Chief River
NEC RR3 BLOCK DIAGRAM
15.6"
01
BlOCK DIAGRAM
POWER
A A
CPU
IvyBridge
35W
Channel A
DDR3 SO-DIMM
PAGE 13
Channel B
DDR3 SO-DIMM
B B
2.5" HDD
mSATA
ODD (Tray)
USB Conn. x 4
Left * 2 / Right * 2
C C
8 Mbytes
Touch Pad
D D
PAGE 13
PAGE 18
PAGE 21
PAGE 18
PAGE 16
Flash ROM
K/B
FAN
1
PAGE 23
PAGE 20
PAGE 20
PAGE 24
SPI
DDR3 1600 MT/s 1.5V
DDR3 1600 MT/s 1.5V
PS/2
Package : LQPF128
2
SATA0 6GB /S
SATA1 6GB /S
SATA3 3GB /S
USB3.0
NPC985
EC
PAGE 23
SYSTEM MEMORY
LPC Interface
NCT5577D
Super IO
PAGE 17
UART
Serial Conn.
3
37.5mm X 37.5mm
( rPGA 989 )
PAGE 5~7
5GT/s2.7GT/s
DMI X 4FDI
Mobile Intel
PCH
PantherPoint
HM76
mBGA 989
(25mm X 25mm)
PAGE 8~12
TPM
Conn.
PAGE 16
PAGE 24
Audio Codec
4
Realtek
ALC282
SYSTEM
RESET CIRCUIT
INT DUAL CHANNEL LVDS
INT HDMI
INT CRT
Port6
PCIE x1
6 x 6mm
Port3
PCIE x1
PCIE x1
9 x 9mm
USB2.0
HDA
6 x 6mm48pin
PAGE 22
Stereo
Giga LAN
Realtek
RTL8111F
48pin-QFN
PAGE 17
CardBus
Ricoh
R5U242A
144 pin CSP
PAGE 25~26
HP Jack
MIC Jack
SPEAKER
5
1W+1W
REGULATOR
+1.8V_RUN
+0.75V_DDR_VTT
+VCCSA
POWER SW
+3V_S5/+5V_S5
+3V_LAN
+3V_RUN/+5V_RUN
LVDS Conn.(15.6")
HDMI Conn.
TRANFORMER RJ45
PAGE 22
PAGE 14
PAGE 15
PAGE 17
Port2
Port10
Port9
Port12
TP BTN/B
Conn.
PAGE 22
PAGE 22
PAGE 16
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
6
Date: Sheet of
CRT
PAGE 15
SD slot
PCMCIA
Type II x1
Mini Card
WLAN
USB2.0 x1
Web Camera
USB/B
Conn.
PAGE 16
Wednesday, March 06, 2013
Wednesday, March 06, 2013
Wednesday, March 06, 2013
7
DC/DC
+VCC_CORE
+3VPCU/+5VPCU
+1.5V_SUS/+0.75V_DDR_VTT
+1.05V_RUN
+VCC_GFX_CORE
PAGE 17
PAGE 26
PAGE 21
PAGE 16
PWR/B
Conn.
PAGE 16
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
BLOCK DIAGRAM
BLOCK DIAGRAM
BLOCK DIAGRAM
RR3
RR3
RR3
1 35
1 35
1 35
8
ES1
ES1
ES1
1
Table of Contents
PAGE DESCRIPTION
01
Schematic Block Diagram
02
Front Page
03
SMBUS Address
04
A A
05-07
08-12
25~26
B B
Power Sequence
CPU Ivy/Sandy Bridge 35W
PCH PantherPoint
DDRIII SO-DIMM(204P) X2
13
LCD CONN
14
CRT CONN/HDMI CONN
15
16
TPM/LED/USB/LED CONN
GLAN RTL8111F/RJ45/Transformer
17
HDD/ODD/NUT
18
USB CONN
19
KB/TOUCH PAD/LED
20
MINI-Card (WLAN)/mSATA
21
CODEC (ALC282)
22
EC (NPC985)
23
FAN/Thermal sensor/Serial Port/Super IO
24
Card Bus (R5U242)
27
3VPCU&RVCC5(PM6686)
28
+VCCSA/VCC1.8
29
1.5VSUS/VTT_MEM
30
+VCC_CORE(ISL95836)
31
+1.05V(G5602R41U)
32
Thermal Protection
33
AD IN/BAT IN
34
CHARGER(BD8617MUV-E2)
Power Tree
35
2
3
RR3 Power Rails
4
5
6
7
8
Reference data sheet
02
Power S0
+3VPCU
+5VPCU
+15VPCU 15V
+3V_LAN
+3V_S5
+5V_S5
+VDDR_REF_CPU
+0.75V_DDR_VTT
+5V_RUN
+3V_RUN
+1.5V 1.5V
+1.05V
+1.8V
+VCCSA By VID
+VCC_CORE
Voltage
3.3V
5V
3.3V
3.3V
5V
1.5V V V+1.5V_SUS SLP_S4#
0.75V
0.75V SLP_S3#
5V
3.3V
1.05V
1.8V
By VID
V V V V 51427ALDO5
V
V
V
V
V V
V
V
V
V
V
V
V
V
V
S3
V
V
NOTE 1
V
S4
V
V
NOTE 1 NOTE 1
NOTE 2 NOTE 2
NOTE 2 NOTE 2
V
V
Ctl SignalS5
51427ALDO5
51427ALDO5
LAN_ON_D
S5_ON
S5_ON
+1.5V
RUN_ON
RUN_ON
SLP_S3#
+3V_RUN
1.05V_PCH_PWRGD
VCCSA_EN
IMVP_VR_ON
Design Guide
471984_471984_Chief_River_DG_Rev_2.0.pdf
CPU
473716_473716_IVB_EDS_Mobile_Rev2_1.pdf
PCH
474146_474146_PPT_EDS_Rev2_1.pdf
Audio
ALC282_DataSheet_0.82
Card Bus
R5U242A -datasheet
LAN
RTL8111F-CG_Datasheet_1.7
EC
NOTE 1:ON/OFF ACCORDING TO WOL FUNCTION SETTING
NOTE 2:ON FOR WAKE UP FUNCTION ENABLE DURING S4/S5
C C
NPCE985x_995x_Rev0.7_DS_Quanta
Check list
460603_CR_SCH_CHKLST_Rev2p0
Super IO
NCT5577D Datasheet V1_2
USB Re-driver
PS8713_DS_Ver1.0_20120511_Quanta
D D
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Wednesday, March 06, 2013
Date: Sheet of
Wednesday, March 06, 2013
Date: Sheet of
1
2
3
4
5
6
Wednesday, March 06, 2013
7
PROJECT :
Frontpage
Frontpage
Frontpage
RR3
RR3
RR3
2 35
2 35
2 35
8
ES1
ES1
ES1
5
4
3
2
1
RR3 SMBus Address
+3VPCU
D D
+3VPCU
R
03
R
+3VPCU
+3VPCU
MBCLK_BAT
R
MBDATA_BAT
BAT/CHARGE
ALSCLK_EC
ALSDATA_EC
EC
NPC985
C C
(128 Pin LQFP)
MBCLK
MBDATA
+3V_S5
+3V_S5
R
+3VPCU
R R
+3VPCU
D
D
+3V_S5
G
NMOS
NMOS
S
S
+3V_S5
D
D
G
NMOS
NMOS
S
S
+3V_S5RR+3V_S5
Human sensor
+3V_S5RR+3V_S5
R R
PCH
INTEL
B B
(HM76)
27mm X 25mm
Controller
SMLink0
Controller
SMLink1
SMB_ME0_CLK
SMB_ME0_DAT
Slave ADDRESS :4BH
SMB_ME1_DAT
SMB_ME1_CLK
+3V_S5
+3V_RUN+3V_S5
+3V_RUN
Slave ADDRESS :A0H Slave ADDRESS :A4H
+3V_RUN
R R
SMB_PCH_CLK
A A
5
HOST
SMBUS
SMB_PCH_DATA
4
G
D
NMOS
D S
NMOS
R R
S
SMB_RUN_CLK
SMB_RUN_DAT
3
DDR3-SODIMM
CH.A(STD)
2
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
DDR3-SODIMM
CH.B(STD)
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
SM BUS
SM BUS
SM BUS
RR3
RR3
RR3
1
ES1
ES1
ES1
3 35Wednesday, March 06, 2013
3 35Wednesday, March 06, 2013
3 35Wednesday, March 06, 2013
1
RR3 Power Sequence
+5VPCU
+3VPCU
A A
VIN
DDR/0.75V
B B
C C
D D
S4
+1.5V_SUS
+5VPCU
VIN
1.05V
VR
S3
EN
1
SUS
SW
G
PG
RC Delay
SLP_S3
SWITCH
G
VIN
RUN PWR
SWITCH
G
PG
PCH
+1.5V_SUS
+0.75V_DDR_VTT
1.5V_SUS_PWRGD
SLP_S3#
SLP_S4#
+1.05V
1.05V_PCH_PWRGD
+3V_RUN
2
+5V_S5
+3V_S5
S5_ON
9
8
7
17
20
21
VCCSA_PWRGD
30
15
26
14
+1.5V
+VDDR_REF_CPU
SLP_S3#
EC: SLP_S3# to RUN_ON delay 12ms
+5V_RUN
+3V_RUN+3VPCU
RUN_ON
1.05V_PCH_PWRGD
18
19
15
23
24
22
25
26
24
2
3
6
NBSWON#
31
HWPG
SPEC: HWPG to EC_PWROK >99ms
4
PWR SW VR
NBSWON#
6
EC
S5_ON
7
22
RUN_ON
+5V_S5
EC_PWROK
IMVP_VR_ON
3233
15
1.8V
VR
EN
26
1.05V_PCH_PWRGD
+5V_S5
5
2
51427ALDO5
VIN
3V/5V
EN2
51427ALDO5
10
RSMRST#
SUS_PWR_ACK
AC_PRESENT
EC_PWRBTN#
16
SPEC:Low >200ns SIO_PWRBTN# to S3#/ S5#
EC: High-> monitor S3#/S5#
SLP_S5#13SLP_S4#14SLP_S3#
27
+1.8V
VCCSA_EN
PG
29
+VCCSA
28
11
12
41
33
34
33
6
+3VPCU
+5VPCU
15VPCU
EN1
3
4
5
7
1
BAT+VIN
CHARGER Battery
2
SPEC: >10ms +3V_S5/ +5V_S5(stable) to RSMRST#
EC: S5_ON to RSMRST# delay 20ms
SLP_S5#
SLP_S4#
SLP_S3#
PM_DRAM_PWRGD
34
PCH_CLK
SYS_PWROK
IMVP_PWRGD
35
SYS_PWROK
13
14
15
DPWROK
SUSWARN#
ACPRESENT
PWRBTN#
SLP_S5#
SLP_S3#
APWROK
DRAMPWROK
SYS_PWROK
42
EC_PWROK
PM_DRAM_PWRGD
EC_PWROK
U18
36
SM_SDRAMPWROK
U2
Battery Mode
PCH
37
SVID
38
8
04
PROCPWRGD
PLTRST#
H_PWRGOOD
43
RESET# PLTRST#
VCCSA
VR
EN
VIN
PG
28
VCCSA_PWRGD
VCCSA_EN
+VCC_CORE
IMVP
VR
EN
SVID
38
3
4
CPU
PG
5
+VCC_GFX_CORE
IMVP_PWRGD
30
39
40
41
IMVP_VR_ON
32
UNCOREPWRGOOD
CPU
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Wednesday, March 06, 2013 4 35
Date: Sheet of
Wednesday, March 06, 2013 4 35
Date: Sheet of
6
Wednesday, March 06, 2013 4 35
7
PROJECT :
POWER SEQUENCE
POWER SEQUENCE
POWER SEQUENCE
RR3
RR3
RR3
ES1
ES1
ES1
8
5
4
3
2
1
VCC_DIE_SENSE
VSS_DIE_SENSE
RSVD28
RSVD29
RSVD30
RSVD31
RSVD32
RSVD33
RSVD34
RSVD35
RSVD37
RSVD38
RSVD39
RSVD40
RSVD41
RSVD42
RSVD43
RSVD44
RSVD45
RSVD46
RSVD47
RSVD48
RSVD49
RSVD50
RSVD51
RSVD52
BCLK_ITP
BCLK_ITP#
RSVD56
RSVD57
RSVD58
05
AH27
AH26
L7
AG7
AE7
AK2
W8
AT26
AM33
AJ27
T8
J16
H16
G16
AR35
AT34
AT33
AP35
AR34
B34
A33
A34
B35
C35
AJ32
AK32
AN35
AM35
AT2
AT1
AR1
B1
KEY
Ivy Bridge Processor (DMI,PEG,FDI)
D D
DMI_TXN0<8>
DMI_TXN1<8>
DMI_TXN2<8>
DMI_TXN3<8>
DMI_TXP0<8>
DMI_TXP1<8>
DMI_TXP2<8>
DMI_TXP3<8>
DMI_RXN0<8>
DMI_RXN1<8>
DMI_RXN2<8>
DMI_RXN3<8>
DMI_RXP0<8>
DMI_RXP1<8>
DMI_RXP2<8>
DMI_RXP3<8>
FDI_TXN0<8>
FDI_TXN1<8>
FDI_TXN2<8>
FDI_TXN3<8>
FDI_TXN4<8>
FDI_TXN5<8>
FDI_TXN6<8>
FDI_TXN7<8>
FDI_TXP0<8>
FDI_TXP1<8>
FDI_TXP2<8>
FDI_TXP3<8>
FDI_TXP4<8>
FDI_FSYNC0<8>
FDI_FSYNC1<8>
FDI_LSYNC0<8>
FDI_LSYNC1<8>
R80 24.9/F_4
EC_PWROK<8,23>
PM_DRAM_PWRGD<8>
FDI_TXP5<8>
FDI_TXP6<8>
FDI_TXP7<8>
FDI_INT<8>
eDP_COMP
DDR3_DRAMRST#<13>
DRAMRST_CNTRL_PCH<10>
C C
+1.05V
eDP_COMPIO
4/15 mils, <500 mils
eDP_ICOMPO
12/15 mils, <500 mils
eDP_HPD can be left NC if
entire eDP is disable.
B B
A A
U21A
B27
DMI_RX#[0]
B25
DMI_RX#[1]
A25
DMI_RX#[2]
B24
DMI_RX#[3]
B28
DMI_RX[0]
B26
DMI_RX[1]
A24
DMI_RX[2]
B23
DMI_RX[3]
G21
DMI_TX#[0]
E22
DMI_TX#[1]
F21
DMI_TX#[2]
D21
DMI_TX#[3]
G22
DMI_TX[0]
D22
DMI_TX[1]
F20
DMI_TX[2]
C21
DMI_TX[3]
A21
FDI0_TX#[0]
H19
FDI0_TX#[1]
E19
FDI0_TX#[2]
F18
FDI0_TX#[3]
B21
FDI1_TX#[0]
C20
FDI1_TX#[1]
D18
FDI1_TX#[2]
E17
FDI1_TX#[3]
A22
FDI0_TX[0]
G19
FDI0_TX[1]
E20
FDI0_TX[2]
G18
FDI0_TX[3]
B20
FDI1_TX[0]
C19
FDI1_TX[1]
D19
FDI1_TX[2]
F17
FDI1_TX[3]
J18
FDI0_FSYNC
J17
FDI1_FSYNC
H20
FDI_INT
J19
FDI0_LSYNC
H17
FDI1_LSYNC
A18
eDP_COMPIO
A17
eDP_ICOMPO
B16
eDP_HPD
C15
eDP_AUX
D15
eDP_AUX#
C17
eDP_TX[0]
F16
eDP_TX[1]
C16
eDP_TX[2]
G15
eDP_TX[3]
C18
eDP_TX#[0]
E16
eDP_TX#[1]
D16
eDP_TX#[2]
F15
eDP_TX#[3]
Ivy Bridge_rPGA_2DPC_Rev0p61
+3V_S5
C110 0.1U/10V_4
2
U14
1
74AHC1G09
3 5
R94 1K/F_4
R171 *0/short_4_NC
4
+1.5V_SUS
R93
1K/F_4
J22
PEG_COMP
PEG_ICOMPI
J21
PEG_ICOMPO
H22
PEG_RCOMPO
K33
PEG_RX#[0]
M35
PEG_RX#[1]
L34
PEG_RX#[2]
J35
PEG_RX#[3]
J32
PEG_RX#[4]
H34
PEG_RX#[5]
H31
PEG_RX#[6]
PEG_RX#[7]
PEG_RX#[8]
PEG_RX#[9]
PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
PEG_RX#[13]
PEG_RX#[14]
PEG_RX#[15]
PEG_RX[0]
PEG_RX[1]
PEG_RX[2]
PEG_RX[3]
PEG_RX[4]
PEG_RX[5]
PEG_RX[6]
PEG_RX[7]
PEG_RX[8]
PEG_RX[9]
PEG_RX[10]
PEG_RX[11]
PEG_RX[12]
PEG_RX[13]
PEG_RX[14]
PEG_RX[15]
PEG_TX#[0]
PEG_TX#[1]
PEG_TX#[2]
PEG_TX#[3]
PEG_TX#[4]
PEG_TX#[5]
PEG_TX#[6]
PEG_TX#[7]
PEG_TX#[8]
PEG_TX#[9]
PEG_TX#[10]
PEG_TX#[11]
PEG_TX#[12]
PEG_TX#[13]
PEG_TX#[14]
PEG_TX#[15]
PEG_TX[0]
PEG_TX[1]
PEG_TX[2]
PEG_TX[3]
PEG_TX[4]
PEG_TX[5]
PEG_TX[6]
PEG_TX[7]
PEG_TX[8]
PEG_TX[9]
PEG_TX[10]
PEG_TX[11]
PEG_TX[12]
PEG_TX[13]
PEG_TX[14]
PEG_TX[15]
+1.5V
R88
200/F_4
R86 130/F_4
Q13
2N7002
2
C106
0.047U/10V/X7R_4_KEN
1
G33
G30
F35
E34
E32
D33
D31
B33
C32
J33
L35
K34
H35
H32
G34
G31
F33
F30
E35
E33
F32
D34
E31
C33
B32
M29
M32
M31
L32
L29
K31
K28
J30
J28
H29
G27
E29
F27
D28
F26
E25
M28
M33
M30
L31
L28
K30
K27
J29
J27
H28
G28
E28
F28
D27
E26
D25
R84
4.99K/F_4
CPU_DRAMRST#
DMI
Intel(R) FDI
PCI EXPRESS* - GRAPHICS
eDP
3
R296 24.9/F_4
PEG_ICOMPI
4/15 mils, <500 mils
PEG_ICOMPO
12/15 mils, <500 mils
PEG_RCOMPO
4/15 mils, <500 mils
CPU_PLTRST#
PM_DRAM_PWRGD_R
+1.05V
EC_PECI spacing at least 18 mils
EC_PECI<11,23>
Clost to CPU
H_PROCHOT#<30>
PM_THRMTRIP#<11>
R282
1K_4
4 3
PM_THRMTRIP#
Q23
2N7002DW
PM_SYNC<8>
H_PWRGOOD<11>
+1.05V
CPU_PLTRST#
PLTRST# <10,16,17,21,23,24,25>
R141 330_4
Rout on one layer is recommanded
+3V_S5
6
215
IVYB 1/4(HOST&PCIE&CFG)
Ivy Bridge Processor (CLK,MISC,JTAG)
U21B
A28
BCLK
H_SNB_IVB#<9>
TP45
TP46
1 2
R6 43_4
R290
56/J_4
R292 *0/short_4_NC
R291 10K_4
R19 75/J_4
PROCHOT<23>
SKTOCC#
TP_CATERR#
PECI_EC_REC_PECI
H_PROCHOT#_RH_PROCHOT#
R289 *0/short_4_NC
PM_DRAM_PWRGD_R
R20
43_4
+5V_RUN
2
Q9
METR3904-G
1 3
R29
100K/F_4
C26
PROC_SELECT#
AN34
SKTOCC#
AL33
CATERR#
AN33
PECI
AL32
PROCHOT#
AN32
THERMTRIP#
AM34
PM_SYNC
AP33
UNCOREPWRGOOD
V8
SM_DRAMPWROK
AR33
RESET#
Ivy Bridge_rPGA_2DPC_Rev0p61
R140
10K/F_4
+1.05V
R36
62_4
H_PROCHOT#
3
2
Q5
2N7002
1
215
C54
0.1U/10V_4
4 3
Clost to CPU
C39
47P/50V/NPO_4_KEN
Place close to VR.
43P in DG.
Also check VR side.
MISCTHERMALPWR MANAGEMENT
CLOCKS
DDR3
JTAG & BPM
SHDN# <23,27,32>
IMVP_PWRGD <8,23,30>
6
Q8
2N7002DW
DPLL_REF_CLK#
MISC
BCLK#
DPLL_REF_CLK
SM_DRAMRST#
SM_RCOMP[0]
SM_RCOMP[1]
SM_RCOMP[2]
PRDY#
PREQ#
TRST#
DBR#
BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]
BPM#[4]
BPM#[5]
BPM#[6]
BPM#[7]
A27
A16
A15
R8
AK1
A5
A4
AP29
AP27
AR26
TCK
AR27
TMS
AP30
AR28
TDI
AP26
TDO
AL35
AT28
AR29
AR30
AT30
AP32
AR31
AT31
AR32
CLK_DPLL_SSCLKP_R
CLK_DPLL_SSCLKN_R
CPU_DRAMRST#
SM_RCOMP_0
SM_RCOMP_1
SM_RCOMP_2
XDP_TCLK_R
XDP_TMS_R
XDP_TRST#_R
XDP_TDI_R
XDP_TDO_R
XDP_DBRST#
R18 1K_4
CLK_CPU_BCLKP <10>
CLK_CPU_BCLKN <10>
R151 1K_4
R144 1K_4
For not using eDP on
SNB, can leave as NC.
R298 140/F_4
R83 25.5/F_4
R82 200/F_4
TP56
TP57
TP58
TP59
TP55
1 2
Processor Strapping
CFG2
(PEG Static Lane Reversal)
CFG7
(PEG Defer Training)
Ivy Bridge Processor (RSVD, CFG)
CFG0
TP38
CFG1
TP1
CFG2
CFG3
TP3
CFG4
CFG5
+1.05V
SM_RCOMP_0
20/20 mils, <50 0 mils
SM_RCOMP_1
20/20 mils, <50 0 mils
SM_RCOMP_2
15/20 mils, <50 0 mils
+3V_RUN
CFG2
R50 *1K/F_4_NC
CFG4
R60 *1K/F_4_NC
CFG7
R128 *1K/F_4_NC
CFG5
R61 *1K/F_4_NC
CFG6
R62 *1K/F_4_NC
CFG[6:5] (PCIE Port Bifurcation Straps)
11: (Default) x16 - X16 PEG interface
10: PEG x8 x8 bifurcation enableddisabled
01: Reserved - (Device 1 function 1 disabled ; function 2 enabled)
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
The CFG signals have a default value of '1' if not terminated on the board.
1 0
Normal Operation
CFG4
(DP Presence Strap)
Disable; No physical DP
attached to eDP
PEG train immediately following
xxRESETB de assertion
CFG6
CFG7CFG7
Lane Reversed
Enable; An ext DP device is
connected to eDP
PEG wait for BIOS training
U21E
AK28
CFG[0]
AK29
CFG[1]
AL26
CFG[2]
AL27
CFG[3]
AK26
CFG[4]
AL29
CFG[5]
AL30
CFG[6]
AM31
CFG[7]
AM32
CFG[8]
AM30
CFG[9]
AM28
CFG[10]
AM26
CFG[11]
AN28
CFG[12]
AN31
CFG[13]
AN26
CFG[14]
AM27
CFG[15]
AK31
CFG[16]
AN29
CFG[17]
AJ31
VAXG_VAL_SENSE
AH31
VSSAXG_VAL_SENSE
AJ33
VCC_VAL_SENSE
AH33
VSS_VAL_SENSE
AJ26
RSVD5
F25
RSVD8
F24
RSVD9
F23
RSVD10
D24
RSVD11
G25
RSVD12
G24
RSVD13
E23
RSVD14
D23
RSVD15
C30
RSVD16
A31
RSVD17
B30
RSVD18
B29
RSVD19
D30
RSVD20
B31
RSVD21
A30
RSVD22
C29
RSVD23
J20
RSVD24
B18
RSVD25
J15
RSVD27
Ivy Bridge_rPGA_2DPC_Rev0p61
CFG
RESERVED
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Wednesday, March 06, 2013
Date: Sheet of
Wednesday, March 06, 2013
Date: Sheet of
5
4
3
2
Wednesday, March 06, 2013
PROJECT :
SNB 1/3(HOST&PCIE&CFG)
SNB 1/3(HOST&PCIE&CFG)
SNB 1/3(HOST&PCIE&CFG)
1
RR3
RR3
RR3
5 35
5 35
5 35
ES1
ES1
ES1
5
4
3
2
1
06
IVYB 2/3(DDR3 I/F&GND)
D D
Ivy Bridge Processor (DDR3)
U21C
AB6
SA_CLK[0]
M_A_DQ[63:0]<13>
C C
B B
M_A_BS#0< 13>
M_A_BS#1< 13>
M_A_BS#2< 13>
M_A_CAS#<13>
M_A_RAS#<13>
M_A_WE#<13>
M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63
C5
SA_DQ[0]
D5
SA_DQ[1]
D3
SA_DQ[2]
D2
SA_DQ[3]
D6
SA_DQ[4]
C6
SA_DQ[5]
C2
SA_DQ[6]
C3
SA_DQ[7]
F10
SA_DQ[8]
F8
SA_DQ[9]
G10
SA_DQ[10]
G9
SA_DQ[11]
F9
SA_DQ[12]
F7
SA_DQ[13]
G8
SA_DQ[14]
G7
SA_DQ[15]
K4
SA_DQ[16]
K5
SA_DQ[17]
K1
SA_DQ[18]
J1
SA_DQ[19]
J5
SA_DQ[20]
J4
SA_DQ[21]
J2
SA_DQ[22]
K2
SA_DQ[23]
M8
SA_DQ[24]
N10
SA_DQ[25]
N8
SA_DQ[26]
N7
SA_DQ[27]
M10
SA_DQ[28]
M9
SA_DQ[29]
N9
SA_DQ[30]
M7
SA_DQ[31]
AG6
SA_DQ[32]
AG5
SA_DQ[33]
AK6
SA_DQ[34]
AK5
SA_DQ[35]
AH5
SA_DQ[36]
AH6
SA_DQ[37]
AJ5
SA_DQ[38]
AJ6
SA_DQ[39]
AJ8
SA_DQ[40]
AK8
SA_DQ[41]
AJ9
SA_DQ[42]
AK9
SA_DQ[43]
AH8
SA_DQ[44]
AH9
SA_DQ[45]
AL9
SA_DQ[46]
AL8
SA_DQ[47]
AP11
SA_DQ[48]
AN11
SA_DQ[49]
AL12
SA_DQ[50]
AM12
SA_DQ[51]
AM11
SA_DQ[52]
AL11
SA_DQ[53]
AP12
SA_DQ[54]
AN12
SA_DQ[55]
AJ14
SA_DQ[56]
AH14
SA_DQ[57]
AL15
SA_DQ[58]
AK15
SA_DQ[59]
AL14
SA_DQ[60]
AK14
SA_DQ[61]
AJ15
SA_DQ[62]
AH15
SA_DQ[63]
AE10
SA_BS[0]
AF10
SA_BS[1]
V6
SA_BS[2]
AE8
SA_CAS#
AD9
SA_RAS#
AF9
SA_WE#
Ivy Bridge_rPGA_2DPC_Rev0p61
DDR SYSTEM MEMORY A
SA_CLK#[0]
SA_CKE[0]
SA_CLK[1]
SA_CLK#[1]
SA_CKE[1]
SA_CLK[2]
SA_CLK#[2]
SA_CKE[2]
SA_CLK[3]
SA_CLK#[3]
SA_CKE[3]
SA_CS#[0]
SA_CS#[1]
SA_CS#[2]
SA_CS#[3]
SA_ODT[0]
SA_ODT[1]
SA_ODT[2]
SA_ODT[3]
SA_DQS#[0]
SA_DQS#[1]
SA_DQS#[2]
SA_DQS#[3]
SA_DQS#[4]
SA_DQS#[5]
SA_DQS#[6]
SA_DQS#[7]
SA_DQS[0]
SA_DQS[1]
SA_DQS[2]
SA_DQS[3]
SA_DQS[4]
SA_DQS[5]
SA_DQS[6]
SA_DQS[7]
SA_MA[0]
SA_MA[1]
SA_MA[2]
SA_MA[3]
SA_MA[4]
SA_MA[5]
SA_MA[6]
SA_MA[7]
SA_MA[8]
SA_MA[9]
SA_MA[10]
SA_MA[11]
SA_MA[12]
SA_MA[13]
SA_MA[14]
SA_MA[15]
AA6
V9
AA5
AB5
V10
AB4
AA4
W9
AB3
AA3
W10
AK3
AL3
AG1
AH1
AH3
AG3
AG2
AH2
C4
G6
J3
M6
AL6
AM8
AR12
AM15
D4
F6
K3
N6
AL5
AM9
AR11
AM14
AD10
W1
W2
W7
V3
V2
W3
W6
V1
W5
AD8
V4
W4
AF8
V5
V7
M_A_DQSN0
M_A_DQSN1
M_A_DQSN2
M_A_DQSN3
M_A_DQSN4
M_A_DQSN5
M_A_DQSN6
M_A_DQSN7
M_A_DQSP0
M_A_DQSP1
M_A_DQSP2
M_A_DQSP3
M_A_DQSP4
M_A_DQSP5
M_A_DQSP6
M_A_DQSP7
M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15
M_A_CLKP0 <13>
M_A_CLKN0 <1 3>
M_A_CKE0 <13>
M_A_CLKP1 <13>
M_A_CLKN1 <1 3>
M_A_CKE1 <13>
M_A_CS#0 <13>
M_A_CS#1 <13>
M_A_ODT0 <13>
M_A_ODT1 <13>
M_A_DQSN[7:0] <13>
M_A_DQSP[7:0] <13>
M_A_A[15:0] < 13> M_B_A[15:0] < 13>
M_B_DQ[63:0]<13>
M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63
M_B_BS#0< 13>
M_B_BS#1< 13>
M_B_BS#2< 13>
M_B_CAS#<13>
M_B_RAS#<13>
M_B_WE#<13>
U21D
C9
SB_DQ[0]
A7
SB_DQ[1]
D10
SB_DQ[2]
C8
SB_DQ[3]
A9
SB_DQ[4]
A8
SB_DQ[5]
D9
SB_DQ[6]
D8
SB_DQ[7]
G4
SB_DQ[8]
F4
SB_DQ[9]
F1
SB_DQ[10]
G1
SB_DQ[11]
G5
SB_DQ[12]
F5
SB_DQ[13]
F2
SB_DQ[14]
G2
SB_DQ[15]
J7
SB_DQ[16]
J8
SB_DQ[17]
K10
SB_DQ[18]
K9
SB_DQ[19]
J9
SB_DQ[20]
J10
SB_DQ[21]
K8
SB_DQ[22]
K7
SB_DQ[23]
M5
SB_DQ[24]
N4
SB_DQ[25]
N2
SB_DQ[26]
N1
SB_DQ[27]
M4
SB_DQ[28]
N5
SB_DQ[29]
M2
SB_DQ[30]
M1
SB_DQ[31]
AM5
SB_DQ[32]
AM6
SB_DQ[33]
AR3
SB_DQ[34]
AP3
SB_DQ[35]
AN3
SB_DQ[36]
AN2
SB_DQ[37]
AN1
SB_DQ[38]
AP2
SB_DQ[39]
AP5
SB_DQ[40]
AN9
SB_DQ[41]
AT5
SB_DQ[42]
AT6
SB_DQ[43]
AP6
SB_DQ[44]
AN8
SB_DQ[45]
AR6
SB_DQ[46]
AR5
SB_DQ[47]
AR9
SB_DQ[48]
AJ11
SB_DQ[49]
AT8
SB_DQ[50]
AT9
SB_DQ[51]
AH11
SB_DQ[52]
AR8
SB_DQ[53]
AJ12
SB_DQ[54]
AH12
SB_DQ[55]
AT11
SB_DQ[56]
AN14
SB_DQ[57]
AR14
SB_DQ[58]
AT14
SB_DQ[59]
AT12
SB_DQ[60]
AN15
SB_DQ[61]
AR15
SB_DQ[62]
AT15
SB_DQ[63]
AA9
SB_BS[0]
AA7
SB_BS[1]
R6
SB_BS[2]
AA10
SB_CAS#
AB8
SB_RAS#
AB9
SB_WE#
Ivy Bridge_rPGA_2DPC_Rev0p61
AE2
SB_CLK[0]
SB_CLK#[0]
SB_CKE[0]
SB_CLK[1]
SB_CLK#[1]
SB_CKE[1]
SB_CLK[2]
SB_CLK#[2]
SB_CKE[2]
SB_CLK[3]
SB_CLK#[3]
SB_CKE[3]
SB_CS#[0]
SB_CS#[1]
SB_CS#[2]
SB_CS#[3]
SB_ODT[0]
SB_ODT[1]
SB_ODT[2]
SB_ODT[3]
SB_DQS#[0]
SB_DQS#[1]
SB_DQS#[2]
SB_DQS#[3]
SB_DQS#[4]
SB_DQS#[5]
SB_DQS#[6]
SB_DQS#[7]
SB_DQS[0]
SB_DQS[1]
SB_DQS[2]
SB_DQS[3]
SB_DQS[4]
SB_DQS[5]
SB_DQS[6]
DDR SYSTEM MEMORY B
SB_DQS[7]
SB_MA[0]
SB_MA[1]
SB_MA[2]
SB_MA[3]
SB_MA[4]
SB_MA[5]
SB_MA[6]
SB_MA[7]
SB_MA[8]
SB_MA[9]
SB_MA[10]
SB_MA[11]
SB_MA[12]
SB_MA[13]
SB_MA[14]
SB_MA[15]
M_B_CLKP0 <13>
AD2
M_B_CLKN0 <1 3>
R9
M_B_CKE0 <13>
AE1
M_B_CLKP1 <13>
AD1
M_B_CLKN1 <1 3>
R10
M_B_CKE1 <13>
AB2
AA2
T9
AA1
AB1
T10
AD3
M_B_CS#0 <13>
AE3
M_B_CS#1 <13>
AD6
AE6
AE4
M_B_ODT0 <13>
AD4
M_B_ODT1 <13>
AD5
AE5
D7
M_B_DQSN0
F3
M_B_DQSN1
K6
M_B_DQSN2
N3
M_B_DQSN3
AN5
M_B_DQSN4
AP9
M_B_DQSN5
AK12
M_B_DQSN6
AP15
M_B_DQSN7
C7
M_B_DQSP0
G3
M_B_DQSP1
J6
M_B_DQSP2
M3
M_B_DQSP3
AN6
M_B_DQSP4
AP8
M_B_DQSP5
AK11
M_B_DQSP6
AP14
M_B_DQSP7
AA8
M_B_A0
T7
M_B_A1
R7
M_B_A2
T6
M_B_A3
T2
M_B_A4
T4
M_B_A5
T3
M_B_A6
R2
M_B_A7
T5
M_B_A8
R3
M_B_A9
AB7
M_B_A10
R1
M_B_A11
T1
M_B_A12
AB10
M_B_A13
R5
M_B_A14
R4
M_B_A15
M_B_DQSN[7:0] <13>
M_B_DQSP[7:0] <13>
U21H
AT35
AT32
AT29
AT27
AT25
AT22
AT19
AT16
AT13
AT10
AT7
AT4
AT3
AR25
AR22
AR19
AR16
AR13
AR10
AR7
AR4
AR2
AP34
AP31
AP28
AP25
AP22
AP19
AP16
AP13
AP10
AP7
AP4
AP1
AN30
AN27
AN25
AN22
AN19
AN16
AN13
AN10
AN7
AN4
AM29
AM25
AM22
AM19
AM16
AM13
AM10
AM7
AM4
AM3
AM2
AM1
AL34
AL31
AL28
AL25
AL22
AL19
AL16
AL13
AL10
AL7
AL4
AL2
AK33
AK30
AK27
AK25
AK22
AK19
AK16
AK13
AK10
AK7
AK4
AJ25
Ivy Bridge_rPGA_2DPC_Rev0p61
Ivy Bridge Processor (GND)
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
AJ22
AJ19
AJ16
AJ13
AJ10
AJ7
AJ4
AJ3
AJ2
AJ1
AH35
AH34
AH32
AH30
AH29
AH28
AH25
AH22
AH19
AH16
AH7
AH4
AG9
AG8
AG4
AF6
AF5
AF3
AF2
AE35
AE34
AE33
AE32
AE31
AE30
AE29
AE28
AE27
AE26
AE9
AD7
AC9
AC8
AC6
AC5
AC3
AC2
AB35
AB34
AB33
AB32
AB31
AB30
AB29
AB28
AB27
AB26
Y9
Y8
Y6
Y5
Y3
Y2
W35
W34
W33
W32
W31
W30
W29
W28
W27
W26
U9
U8
U6
U5
U3
U2
U21I
T35
VSS161
T34
VSS162
T33
VSS163
T32
VSS164
T31
VSS165
T30
VSS166
T29
VSS167
T28
VSS168
T27
VSS169
T26
VSS170
P9
VSS171
P8
VSS172
P6
VSS173
P5
VSS174
P3
VSS175
P2
VSS176
N35
VSS177
N34
VSS178
N33
VSS179
N32
VSS180
N31
VSS181
N30
VSS182
N29
VSS183
N28
VSS184
N27
VSS185
N26
VSS186
M34
VSS187
L33
VSS188
L30
VSS189
L27
VSS190
L9
VSS191
L8
VSS192
L6
VSS193
L5
VSS194
L4
VSS195
L3
VSS196
L2
VSS197
L1
VSS198
K35
VSS199
K32
VSS200
K29
VSS201
K26
VSS202
J34
VSS203
J31
VSS204
H33
VSS205
H30
VSS206
H27
VSS207
H24
VSS208
H21
VSS209
H18
VSS210
H15
VSS211
H13
VSS212
H10
VSS213
H9
VSS214
H8
VSS215
H7
VSS216
H6
VSS217
H5
VSS218
H4
VSS219
H3
VSS220
H2
VSS221
H1
VSS222
G35
VSS223
G32
VSS224
G29
VSS225
G26
VSS226
G23
VSS227
G20
VSS228
G17
VSS229
G11
VSS230
F34
VSS231
F31
VSS232
F29
VSS233
Ivy Bridge_rPGA_2DPC_Rev0p61
VSS
VSS234
VSS235
VSS236
VSS237
VSS238
VSS239
VSS240
VSS241
VSS242
VSS243
VSS244
VSS245
VSS246
VSS247
VSS248
VSS249
VSS250
VSS251
VSS252
VSS253
VSS254
VSS255
VSS256
VSS257
VSS258
VSS259
VSS260
VSS261
VSS262
VSS263
VSS264
VSS265
VSS266
VSS267
VSS268
VSS269
VSS270
VSS271
VSS272
VSS273
VSS274
VSS275
VSS276
VSS277
VSS278
VSS279
VSS280
VSS281
VSS282
VSS283
VSS284
VSS285
F22
F19
E30
E27
E24
E21
E18
E15
E13
E10
E9
E8
E7
E6
E5
E4
E3
E2
E1
D35
D32
D29
D26
D20
D17
C34
C31
C28
C27
C25
C23
C10
C1
B22
B19
B17
B15
B13
B11
B9
B8
B7
B5
B3
B2
A35
A32
A29
A26
A23
A20
A3
A A
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Wednesday, March 06, 2013
Date: Sheet of
Wednesday, March 06, 2013
Date: Sheet of
5
4
3
2
Wednesday, March 06, 2013
PROJECT :
IVYB 2/3(DDR3 I/F&GND)
IVYB 2/3(DDR3 I/F&GND)
IVYB 2/3(DDR3 I/F&GND)
1
RR3
RR3
RR3
6 35
6 35
6 35
ES1
ES1
ES1
5
4
3
2
1
07
Ivy Bridge Processor (GRAPHIC POWER)Ivy Bridge Processor (POWER)
VAXG1
VAXG2
VAXG3
VAXG4
VAXG5
VAXG6
VAXG7
VAXG8
VAXG9
VAXG10
VAXG11
VAXG12
VAXG13
VAXG14
VAXG15
VAXG16
VAXG17
VAXG18
VAXG19
VAXG20
VAXG21
VAXG22
VAXG23
VAXG24
VAXG25
VAXG26
VAXG27
VAXG28
VAXG29
VAXG30
VAXG31
VAXG32
VAXG33
VAXG34
VAXG35
VAXG36
VAXG37
VAXG38
VAXG39
VAXG40
VAXG41
VAXG42
VAXG43
VAXG44
VAXG45
VAXG46
VAXG47
VAXG48
VAXG49
VAXG50
VAXG51
VAXG52
VAXG53
VAXG54
VCCPLL1
VCCPLL2
VCCPLL3
POWER
GRAPHICS
1.8V RAIL
+1.05V +1.05V
12
0.1U/10V_4
C98
R138
130/F_4
R600 43_4
2
+1.05V
SENSE
LINES
SA_DIMM_VREFDQ
VREFMISC
SB_DIMM_VREFDQ
DDR3 -1.5V RAILS
SA RAIL
R129
75/J_4
VAXG_SENSE
VSSAXG_SENSE
SM_VREF
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
VCCSA1
VCCSA2
VCCSA3
VCCSA4
VCCSA5
VCCSA6
VCCSA7
VCCSA8
VCCSA_SENSE
VCCSA_VID[0]
VCCSA_VID[1]
VCCIO_SEL
+1.05V
12
0.1U/10V_4
C97
AK35
AK34
AL1
+VDDR_REF_CPU
CAD Note: +VDDR_REF_CPU should
have 10 mil trace width
B4
D1
(5A)
AF7
+1.5V
AF4
AF1
AC7
C315 *330U/2V_7343_NC
AC4
AC1
C302 10U/6.3V/X5R_6
Y7
C303 10U/6.3V/X5R_6
Y4
C306 10U/6.3V/X5R_6
Y1
C305 10U/6.3V/X5R_6
U7
C307 10U/6.3V/X5R_6
U4
C301 10U/6.3V/X5R_6
U1
P7
C296 22U/6.3V_8
P4
C300 *22U/6.3V_8_NC
P1
6A
M27
M26
L26
J26
J25
J24
H26
H25
H23
C22
C24
A19
+VCCSA
C286 10U/6.3V/X5R_6
C285 10U/6.3V/X5R_6
C284 10U/6.3V/X5R_6
C51 *330U/2V_7343_NC
VCCSA_VID0 <28>
VCCSA_VID1 <28>
SVID CLK
Close to VR
R31
54.9/F_4
H_CPU_SVIDCLK < 30>
(50 ohm)
SVID DATA
Close to VR
R283
130/F_4
H_CPU_SVIDDAT <30>
(50 ohm)
SVID ALERT
(50 ohm)
VR_SVID_ALERT# <30>
R288 100_F_4
R287 100_F_4
+VDDR_REF_CPU
+VCC_GFX
VCC_AXG_SENSE <30>
VSS_AXG_SENSE <30>
0305_1 Change C315 P/N to CH733RM8825
+
+
(For +0.85V)
VCCUSA_SENSE <28>
R75 *10K_4_NC
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Wednesday, March 06, 2013
Date: Sheet of
Wednesday, March 06, 2013
Date: Sheet of
Wednesday, March 06, 2013
PROJECT :
IVYB 3/3(POWER)
IVYB 3/3(POWER)
IVYB 3/3(POWER)
1
RR3
RR3
RR3
7 35
7 35
7 35
ES1
ES1
ES1
D D
CPU Core Power
C336 10U/6.3V/X5R_8
C192 10U/6.3V/X5R_8
C279 10U/6.3V/X5R_8
C310 10U/6.3V/X5R_8
C276 10U/6.3V/X5R_8
C322 10U/6.3V/X5R_8
C338 10U/6.3V/X5R_8
C277 10U/6.3V/X5R_8
C278 10U/6.3V/X5R_8
C323 10U/6.3V/X5R_8
C194 22U/6.3V_8
C332 22U/6.3V_8
HOLE1
*intel-CPU-bracket
C327 22U/6.3V_8
C193 *22U/6.3V_8_NC
C269 *22U/6.3V_8_NC
C328 *22U/6.3V_8_NC
C324 *22U/6.3V_8_NC
C274 10U/6.3V/X5R_6
C230 10U/6.3V/X5R_6
C326 10U/6.3V/X5R_6
C268 10U/6.3V/X5R_6
C196 10U/6.3V/X5R_6
C270 10U/6.3V/X5R_6
C275 10U/6.3V/X5R_6
C195 10U/6.3V/X5R_6
C325 10U/6.3V/X5R_6
C333 10U/6.3V/X5R_6
34
PS_S3CNTRL<1 3>
5
C C
B B
1 2
A A
IVYB:53A
+VCC_CORE
SLP_S3#<8,23,29>
+5VPCU
15VPCU
AG35
AG34
AG33
AG32
AG31
AG30
AG29
AG28
AG27
AG26
AF35
AF34
AF33
AF32
AF31
AF30
AF29
AF28
AF27
AF26
AD35
AD34
AD33
AD32
AD31
AD30
AD29
AD28
AD27
AD26
AC35
AC34
AC33
AC32
AC31
AC30
AC29
AC28
AC27
AC26
AA35
AA34
AA33
AA32
AA31
AA30
AA29
AA28
AA27
AA26
Y35
Y34
Y33
Y32
Y31
Y30
Y29
Y28
Y27
Y26
V35
V34
V33
V32
V31
V30
V29
V28
V27
V26
U35
U34
U33
U32
U31
U30
U29
U28
U27
U26
R35
R34
R33
R32
R31
R30
R29
R28
R27
R26
P35
P34
P33
P32
P31
P30
P29
P28
P27
P26
1 2
R37 10K_4
PS_S3CNTRL
1 2
R39 100K_4
POWER
U21F
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
VCC30
VCC31
VCC32
VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48
VCC49
VCC50
VCC51
VCC52
VCC53
VCC54
VCC55
VCC56
VCC57
VCC58
VCC59
VCC60
VCC61
VCC62
VCC63
VCC64
VCC65
VCC66
VCC67
VCC68
VCC69
VCC70
VCC71
VCC72
VCC73
VCC74
VCC75
VCC76
VCC77
VCC78
VCC79
VCC80
VCC81
VCC82
VCC83
VCC84
VCC85
VCC86
VCC87
VCC88
VCC89
VCC90
VCC91
VCC92
VCC93
VCC94
VCC95
VCC96
VCC97
VCC98
VCC99
VCC100
Ivy Bridge_rPGA_2DPC_Rev0p61
SLP_S3#
CORE SUPPLY
5
2
6
Q9013
2N7002DW
PEG AND DDR
VIDALERT#
VCC_SENSE
VSS_SENSE
VCCIO_SENSE
VSS_SENSE_VCCIO
SENSE LINES SVID
43
1
VCCIO1
VCCIO2
VCCIO3
VCCIO4
VCCIO5
VCCIO6
VCCIO7
VCCIO8
VCCIO9
VCCIO10
VCCIO11
VCCIO12
VCCIO13
VCCIO14
VCCIO15
VCCIO16
VCCIO17
VCCIO18
VCCIO19
VCCIO20
VCCIO21
VCCIO22
VCCIO23
VCCIO24
VCCIO25
VCCIO26
VCCIO27
VCCIO28
VCCIO29
VCCIO30
VCCIO31
VCCIO32
VCCIO33
VCCIO34
VCCIO35
VCCIO36
VCCIO37
VCCIO38
VCCIO39
VCCIO40
VIDSCLK
VIDSOUT
AH13
AH10
AG10
AC10
Y10
U10
P10
L10
J14
J13
J12
J11
H14
H12
H11
G14
G13
G12
F14
F13
F12
F11
E14
E12
E11
D14
D13
D12
D11
C14
C13
C12
C11
B14
B12
A14
A13
A12
A11
J23
AJ29
AJ30
AJ28
AJ35
AJ34
B10
A10
4
8.5A
C308 *330U/2V_7343_NC
R295 *0/short_4_NC
H_CPU_SVIDALRT#
H_CPU_SVIDCLK
H_CPU_SVIDDAT
S3 Power reduce
+1.5V_SUS +1.5V
PS_S3CNTRL_S
*4700P/25V_4_NC
+1.05V
+
C358 22U/6.3V_8
C355 22U/6.3V_8
C352 22U/6.3V_8
C353 22U/6.3V_8
C341 22U/6.3V_8
C359 22U/6.3V_8
C354 22U/6.3V_8
C340 22U/6.3V_8
C348 10U/6.3V/X5R_6
C343 10U/6.3V/X5R_6
C309 10U/6.3V/X5R_6
C360 *22U/6.3V_8_NC
C351 *22U/6.3V_8_NC
R285 100/F_4
R286 100/F_4
1 2
R41 10_4
1 2
R42 10_4
5A
Q9014
RJK0397DPA
3
D
S
2
5
1
G
4
12
C95
+1.05V
+1.05V
+VCC_CORE
VCCP_SENSE <31>
VSSP_SENSE <31>
VCC_SENSE <30>
VSS_SENSE <30>
+VCC_GFX
1.5A
+1.8V
C319
10U/6.3V/X5R_6
+VDDR_REF_CPU+1.5V
R44
1K/F_4
1 2
12
0.1U/10V_4
R45
C96
1K/F_4
1 2
3
33A
C291 22U/6.3V_8
C295 22U/6.3V_8
C292 22U/6.3V_8
C299 22U/6.3V_8
C290 22U/6.3V_8
C298 *22U/6.3V_8_NC
C287 *22U/6.3V_8_NC
C339 10U/6.3V/X5R_6
C289 10U/6.3V/X5R_6
C297 10U/6.3V/X5R_6
C304 10U/6.3V/X5R_6
C288 10U/6.3V/X5R_6
C318
C317
1U/10V/X5R_4
1U/10V/X5R_4
+
C320
*330U/2V_7343_NC
U21G
AT24
AT23
AT21
AT20
AT18
AT17
AR24
AR23
AR21
AR20
AR18
AR17
AP24
AP23
AP21
AP20
AP18
AP17
AN24
AN23
AN21
AN20
AN18
AN17
AM24
AM23
AM21
AM20
AM18
AM17
AL24
AL23
AL21
AL20
AL18
AL17
AK24
AK23
AK21
AK20
AK18
AK17
AJ24
AJ23
AJ21
AJ20
AJ18
AJ17
AH24
AH23
AH21
AH20
AH18
AH17
B6
A6
A2
Ivy Bridge_rPGA_2DPC_Rev0p61
Layout note: need routing
together and ALERT need
between CLK and DATA
H_CPU_SVIDCLK
Place PU resistor close to CPU
H_CPU_SVIDDAT
Place PU resistor close to CPU
H_CPU_SVIDALRT#
5
4
3
2
1
RR3
RR3
RR3
08
+3V_RUN
INT. HDMI INT. DP
8 35
8 35
8 35
ES1
ES1
ES1
PCH 1/5 (DMI/FDI/VIDEO)
Panther Point (DMI,FDI,PM)
D D
U24C
DMI_COMP
SUSACK#_R
SYS_RESET#
BC24
DMI0RXN
BE20
DMI1RXN
BG18
DMI2RXN
BG20
DMI3RXN
BE24
DMI0RXP
BC20
DMI1RXP
BJ18
DMI2RXP
BJ20
DMI3RXP
AW24
DMI0TXN
AW20
DMI1TXN
BB18
DMI2TXN
AV18
DMI3TXN
AY24
DMI0TXP
AY20
DMI1TXP
AY18
DMI2TXP
AU18
DMI3TXP
BJ24
DMI_ZCOMP
BG25
DMI_IRCOMP
BH21
DMI2RBIAS
C12
SUSACK#
K3
SYS_RESET#
P12
SYS_PWROK
L22
PWROK
L10
APWROK
B13
DRAMPWROK
C21
RSMRST#
K16
SUSWARN#/SUSPWRDNACK/GPIO30
E20
PWRBTN#
H20
ACPRESENT / GPIO31
E10
BATLOW# / GPIO72
A10
RI#
PantherPoint
+3V_S5
+3V_S5
+3V_S5
DSW
+3V_S5
+3V_S5
DMI
FDI
+3V
CLKRUN# / GPIO32
SUS_STAT# / GPIO61
SUSCLK / GPIO62
SLP_S5# / GPIO63
System Power Management
SLP_LAN# / GPIO29
DMI_RXN0<5>
DMI_RXN1<5>
DMI_RXN2<5>
DMI_RXN3<5>
DMI_RXP0<5>
DMI_RXP1<5>
DMI_RXP2<5>
DMI_RXP3<5>
DMI_TXN0< 5>
DMI_TXN1< 5>
DMI_TXN2< 5>
DMI_TXN3< 5>
DMI_TXP0<5>
DMI_TXP1<5>
DMI_TXP2<5>
DMI_ZCOMP, DMI_IRCOMP
4 mils, <500 mils
+1.05V
C C
SUS_PWR _ACK
EC_PWR OK<5,23>
HWPG<8,23>
PM_DRAM_PW RGD<5>
RSMRST#<23>
SUS_PWR _ACK<23>
EC_PWR BTN#<23>
AC_PRESENT<23>
PM_RI#<24>
DMI_TXP3<5>
R9244 49.9/F_4
R9245 750/F_4
R9246 *0/short_4_NC
SYS_PWROK
EC_PWR OK
HWPG
PM_DRAM_PW RGD
RSMRST#
SUS_PWR _ACK
EC_PWR BTN#
AC_PRESENT
PM_BATLOW #
PM_RI#
PCH Pull-high/low(CLG)
B B
CLKRUN#
SYS_RESET#
RSMRST#
SYS_PWROK
----- No Deep S4/S5, No ME -----Â#SYS_RESET: Like DT reset button, NC.
#SYS_PWROK: The latest PWROK means all power in platform is stable,
After getting this signql, PCH prepares to deliver PLT_RST#.
#PWROK: All power in platform except to VCC_CORE and VCC_GFX_CORE is stable
#APWROK: Can be the same as SLP_S3 PWR stable if ME is not implemented.
A A
#DRAMPWROK: Indicates RAM power is stable, go after the PWROK is high and
can be set time by register.
#:SUSWARN#/SUSPWRDNACK: Asserted by the PCH on behalf of the Intel ME when it
does not require the PCH Suspend well to be powered. WHAT DOES IT MEAN??
#:DPWROK: Connect to RSMRST#
#:SLP_SUS#: NC
#:SLP_A#: Can the same as or earlier than SLP_S3#, Connect to SLP_S3#
#:SLP_LAN#: Can be the same as or earlier than SLP_A#.
#:SUS_ACK#: Tell PCH that got the massage of entering Deep S4/S5 or not.
R361 8.2K/J_4
R373 10K_4
R420 10K_4
R197 10K_4
5
+3V_RUN
PM_RI#
PM_BATLOW #
PCIE_EC_WA KE#
SUS_PWR _ACK
AC_PRESENT
PM_DRAM_PW RGD
This segment should less
than 500 mils.
R396 10K_4
R242 8.2K/J_4
R394 10K_4
R255 10K_4
R425 10K_4
R414 200/F_4
+3V_S5
FDI_RXN0
FDI_RXN1
FDI_RXN2
FDI_RXN3
FDI_RXN4
FDI_RXN5
FDI_RXN6
FDI_RXN7
FDI_RXP0
FDI_RXP1
FDI_RXP2
FDI_RXP3
FDI_RXP4
FDI_RXP5
FDI_RXP6
FDI_RXP7
FDI_FSYNC0
FDI_FSYNC1
FDI_LSYNC0
FDI_LSYNC1
DSWVRMEN
DPWROK
+3V_S5
SLP_SUS#
PMSYNCH
BJ14
AY14
BE14
BH13
BC12
BJ12
BG10
BG9
BG14
BB14
BF14
BG13
BE12
BG12
BJ10
BH9
AW16
FDI_INT
AV12
BC10
AV14
BB10
A18
DSWVRE N
E22
DPWRO K
B9
PCIE_EC_WA KE#
WAKE#
N3
CLKRUN#
G8
N14
SUSCLK_R S USCLK
D10
H4
SLP_S4#
F4
SLP_S3#
G10
SLP_A#
G16
AP14
K14
4
FDI_TXN0 <5>
FDI_TXN1 <5>
FDI_TXN2 <5>
FDI_TXN3 <5>
FDI_TXN4 <5>
FDI_TXN5 <5>
FDI_TXN6 <5>
FDI_TXN7 <5>
FDI_TXP0 <5>
FDI_TXP1 <5>
FDI_TXP2 <5>
FDI_TXP3 <5>
FDI_TXP4 <5>
FDI_TXP5 <5>
FDI_TXP6 <5>
FDI_TXP7 <5>
FDI_INT <5>
FDI_FSYNC0 <5>
FDI_FSYNC1 <5>
FDI_LSYNC0 <5>
FDI_LSYNC1 <5>
PCIE_EC_WA KE# <17>
TP12
TP13
TP14
TP16
RSMRST#
SLP_S5# <23>
SLP_S4# <23,29>
SLP_S3# <7,23,29>
PM_SYNC <5>
R9248 *0/short_4_NC
R121 0_4
Intel sequence
1.5V_SUS_PW RGD<29>
VCCSA_PW RGD<28> HWPG <8,23>
SYS_PWROK
EC61
*10P/50V_4_NC
4
TC7SH08FU
INT_LVDS_BLON<23>
INT_LVDS_VDD EN<14>
INT_LVDS_BRIGHT<14>
INT_LVDS_EDIDC LK<14>
INT_LVDS_EDIDD ATA< 14>
+3V_RUN
INT_TXLCLKOU TN<14>
INT_TXLCLKOU TP<14>
INT_TXLOUTN 0<14>
INT_TXLOUTN 1<14>
INT_TXLOUTN 2<14>
INT_TXLOUTP0<14>
INT_TXLOUTP1<14>
INT_TXLOUTP2<14>
INT_TXUCLKOU TN<14>
INT_TXUCLKOU TP<14>
INT_TXUOUT N0<14>
INT_TXUOUT N1<14>
INT_TXUOUT N2<14>
INT_TXUOUT P0<14>
INT_TXUOUT P1<14>
INT_TXUOUT P2<14>
SUSCLK <16>
INT_CRT_HS YNC<15>
INT_CRT_VSYNC<15>
R place close to PCH <800 mil
R379 150/F_4
R376 150/F_4
R372 150/F_4
INT_CRT_BLU<15>
INT_CRT_GR E<15>
INT_CRT_RE D<15>
INT_DDCCLK<15>
INT_DDCDA T<15>
R385 33/J _4
R382 33/J _4
R place close to PCH <600 mil
INT_CRT_BLU
INT_CRT_GR E
INT_CRT_RE D
R9241 2.2K_4
R9242 2.2K_4
R9243 2.37K/F_4
INT_LVDS_EDIDC LK
INT_LVDS_EDIDD ATA
INT_CRT_HS YNC_R
INT_CRT_VSYNC _R
Note: INT_DDCCLK & INT_DDCDAT Pull High in CRT connector side
+3V_S5
C357
1
0.1U/10V_4
2
1
3 5
R9250 *0_4_NC
3
2
EC_PWR OK
12
R9251 0_4
R9252 0_4
R179
100K_4
+3V_RUN
R371
1K/F_4
+3V_S5
C375
*1000P/50V/X7R/10%_4_K EN_NC
R374
*1K/F_4_NC
HWPGVCCSA_PW RGD
U18
1.5V_SUS_PW RGD
Panther Point (LVDS,DDI)
U24D
J47
DIS_L_CTRL_CLK
DIS_L_CTRL_DA TA
LVDS_IBG
TP11
INT_TXLCLKOU TN
INT_TXLCLKOU TP
INT_TXLOUTN 0
INT_TXLOUTN 1
INT_TXLOUTN 2
INT_TXLOUTP0
INT_TXLOUTP1
INT_TXLOUTP2
INT_TXUCLKOU TN
INT_TXUCLKOU TP
INT_TXUOUT N0
INT_TXUOUT N1
INT_TXUOUT N2
INT_TXUOUT P0
INT_TXUOUT P1
INT_TXUOUT P2
INT_CRT_BLU
INT_CRT_GR E
INT_CRT_RE D
INT_DDCCLK
INT_DDCDA T
DAC_IREF
R164
1K/F_4
IMVP_PWRGD <5,23,30>
AM47
AM49
AF37
AF36
AE48
AE47
AK39
AK40
AN48
AK47
AJ48
AN47
AK49
AJ47
AF40
AF39
AH45
AH47
AF49
AF45
AH43
AH49
AF47
AF43
M45
P45
T40
K47
T45
P39
N48
P49
T49
T39
M40
M47
M49
T43
T42
L_BKLTEN
L_VDD_EN
L_BKLTCTL
L_DDC_CLK
L_DDC_DATA
L_CTRL_CLK
L_CTRL_DATA
LVD_IBG
LVD_VBG
LVD_VREFH
LVD_VREFL
LVDSA_CLK#
LVDSA_CLK
LVDSA_DATA#0
LVDSA_DATA#1
LVDSA_DATA#2
LVDSA_DATA#3
LVDSA_DATA0
LVDSA_DATA1
LVDSA_DATA2
LVDSA_DATA3
LVDSB_CLK#
LVDSB_CLK
LVDSB_DATA#0
LVDSB_DATA#1
LVDSB_DATA#2
LVDSB_DATA#3
LVDSB_DATA0
LVDSB_DATA1
LVDSB_DATA2
LVDSB_DATA3
CRT_BLUE
CRT_GREEN
CRT_RED
CRT_DDC_CLK
CRT_DDC_DATA
CRT_HSYNC
CRT_VSYNC
DAC_IREF
CRT_IRTN
PantherPoint
2
SDVO_TVCLKINN
SDVO_TVCLKINP
SDVO_CTRLCLK
SDVO_CTRLDATA
LVDS
DDPC_CTRLCLK
DDPC_CTRLDATA
Digital Display Interface
DDPD_CTRLCLK
DDPD_CTRLDATA
CRT
SDVO_STALLN
SDVO_STALLP
SDVO_INTN
SDVO_INTP
DDPB_AUXN
DDPB_AUXP
DDPB_HPD
DDPB_0N
DDPB_0P
DDPB_1N
DDPB_1P
DDPB_2N
DDPB_2P
DDPB_3N
DDPB_3P
DDPC_AUXN
DDPC_AUXP
DDPC_HPD
DDPC_0N
DDPC_0P
DDPC_1N
DDPC_1P
DDPC_2N
DDPC_2P
DDPC_3N
DDPC_3P
DDPD_AUXN
DDPD_AUXP
DDPD_HPD
DDPD_0N
DDPD_0P
DDPD_1N
DDPD_1P
DDPD_2N
DDPD_2P
DDPD_3N
DDPD_3P
HDMI_SCL
R9249 2.2K_4
HDMI_SDA
R9253 2.2K_4
AP43
AP45
AM42
AM40
AP39
AP40
P38
HDMI_SCL
M39
HDMI_SDA
AT49
AT47
AT40
INT_HDMI_HPD
AV42
INT_HDMI_TXN2
AV40
INT_HDMI_TXP2
AV45
INT_HDMI_TXN1
AV46
INT_HDMI_TXP1
AU48
INT_HDMI_TXN0
AU47
INT_HDMI_TXP0
AV47
INT_HDMI_TXCN
AV49
INT_HDMI_TXCP
P46
P42
AP47
AP49
AT38
AY47
AY49
AY43
AY45
BA47
BA48
BB47
BB49
M43
M36
AT45
AT43
BH41
BB43
BB45
BF44
BE44
BF42
BE42
BJ42
BG42
DSWVRE N
On Die DSW VR Enable
High = Enable (Default)
Low = Disable
Size D ocument Numb er Rev
Size D ocument Numb er Rev
Size D ocument Numb er Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
HDMI_SCL <15>
HDMI_SDA <15>
INT_HDMI_HPD <15>
INT_HDMI_TXN2 <1 5>
INT_HDMI_TXP2 <15>
INT_HDMI_TXN1 <1 5>
INT_HDMI_TXP1 <15>
INT_HDMI_TXN0 <1 5>
INT_HDMI_TXP0 <15>
INT_HDMI_TXCN <15>
INT_HDMI_TXCP < 15>
+3V_RTC
R423
330K/J_4
R424
*330K/J_4_NC
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
PCH 1/5 (DMI/FDI/VIDEO)
PCH 1/5 (DMI/FDI/VIDEO)
PCH 1/5 (DMI/FDI/VIDEO)
Wednesd ay, March 06, 2013
Wednesd ay, March 06, 2013
Wednesd ay, March 06, 2013
1
5
4
3
2
1
RTC Circuitry (RTC)
(non Rechargable BATT)
30mils
+3V_RTC
R417 20K/J_4
30mils
3
R416 20K/J_4
C401
1U/10V/X5R_4
C404
1U/10V/X5R_4
C403
1U/10V/X5R_4
12
1
2
BAT54C T/R
R347
1K_4
CON2
BAT_CONN
D8
+3VPCU
R9284
1K_4
+VCCRTC3
D D
C C
RTC_RST#
12
J1
*SHORT_ PAD1
SRTC_RST#
PCH Strap Table
B B
Strap descriptionPin Name
INTVRMEN
GNT1# / GPIO51
GPIO19
HDA_SDO
DF_TVS
A A
GPIO28
HDA_SYNC
Boot BIOS Selection 1 [bit-1]
Boot BIOS Selection 0 [bit-0]
Flash Descriptor Security
DMI/FDI Termination voltage
On-die PLL Voltage Regulator
On-Die PLL VR Voltage Select
5
Sampled
ALWAYSIntegrated 1.05V VRM enable
PWROK
PWROK
PWROK
PWROK
RSMRST#
RSMRST
Configuration
Should be always pull-up
GNT1# GNT0#
1 1
0
1= Override
0 = Default (weak pull-down20K)
0 = Set to Vss for Ivy Bridge
1 = Set to Vcc for Sandy Bridge
(weak pull-down 20K)
0 = Disable
1 = Enable (Default)
0 = Support by 1.8V (weak pull-down)
1 = Support by 1.5V
Boot Location
SPI
0
LPC
4
Default weak pull-up on GNT0/1#
[Need external pull-down for LPC BIOS]
*
+3V_S5
PCH 2/5(SATA/RTC/HDA/LPC)
Panther Point (HDA,JTAG,SATA)
C407
R422 330K/J_4
+3V_RTC
R327 2.2K_4
R322 1K_4
R427 *1K_4_NC
R256 1K_4
C8411 CLOSE TO PCH
PCH_INVRMEN
+1.8V
DF_TVS <11>
H_SNB_IVB# <5>
PLL_ODVR_EN <11>
ACZ_SYNC_R
18p_4
C398
18p_4
41
2 3
+3V_RTC
C8411 *10P/50V_4_NC
ACZ_BITCLK<22>
SPKR<22>
ACZ_RST#<22>
ACZ_SDIN0<22>
C8412 *10P/50V_4_NC
ACZ_SDOUT<22>
ME_OVERRIDE<23>
Y4
32.768KHZ
R9285 1M_4
R9292 33/J_4
1 2
R193 1K_4
TP30
TP31
TP32
TP34
SCK_PCH<23>
CS0#_PCH<23>
TP35
SDO_PCH<23>
SDI_PCH<23>
SERIRQ
GPIO21
BBS_BIT0
3
R408
10M/J_4
R9287 33/J_4
ACZ_SYNC_R
R9290 33/J_4
R590 1K_4
R155 8.2K/J_4
R364 10K_4
R587 10K_4
RTC_X1
RTC_X2
RTC_RST#
SRTC_RST#
SM_INTRUDER#
PCH_INVRMEN
ACZ_BITCLK_R1
ACZ_RST#_R
ME_OVERRIDE_R
PCH_JTAG_TCK_R
PCH_JTAG_TMS_RPCH_JTAG_TMS_R
PCH_JTAG_TDO_RPCH_JTAG_TDO_R
SCK_PCH
CS0#_PCH
SPI_CS1#
SDI_PCH
+3V_RUN
U24A
A20
RTCX1
C20
RTCX2
D20
RTCRST#
G22
SRTCRST#
K22
INTRUDER#
C17
INTVRMEN
N34
HDA_BCLK
L34
HDA_SYNC
T10
SPKR
K34
HDA_RST#
E34
HDA_SDIN0
G34
HDA_SDIN1
C34
HDA_SDIN2
A34
HDA_SDIN3
A36
HDA_SDO
C36
HDA_DOCK_EN# / GPIO33
N32
HDA_DOCK_RST# / GPIO13
J3
JTAG_TCK
H7
JTAG_TMS
K5
JTAG_TDI
H1
JTAG_TDO
T3
SPI_CLK
Y14
SPI_CS0#
T1
SPI_CS1#
V4
SPI_MOSI
U3
SPI_MISO
PantherPoint
+5V_RUN
ACZ_SYNC<22>
+3V
RTCIHDA
+3V
+3V_S5
JTAG
SPI
+3V
+3V
R254 10K_4
R436 33/J_4
2
FWH0 / LAD0
FWH1 / LAD1
FWH2 / LAD2
FWH3 / LAD3
LPC
FWH4 / LFRAME#
LDRQ0#
LDRQ1# / GPIO23
SERIRQ
SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP
SATA1RXN
SATA1RXP
SATA 6G
SATA1TXN
SATA1TXP
SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP
SATA3RXN
SATA3RXP
SATA3TXN
SATA3TXP
SATA4RXN
SATA4RXP
SATA4TXN
SATA
SATA4TXP
SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP
SATAICOMPO
SATAICOMPI
SATA3RCOMPO
SATA3COMPI
SATA3RBIAS
SATALED#
SATA0GP / GPIO21
SATA1GP / GPIO19
1
2
C38
A38
B37
C37
D36
E36
K36
V5
AM3
AM1
AP7
AP5
AM10
AM8
AP11
AP10
AD7
AD5
AH5
AH4
AB8
AB10
AF3
AF1
Y7
Y5
AD3
AD1
Y3
Y1
AB3
AB1
Y11
Y10
AB12
AB13
AH1
P3
V14
P1
Q19
2N7002
3
R9476 22/J_4
R9477 22/J_4
R9478 22/J_4
R9479 22/J_4
PCH_DRQ#0
PCH_DRQ#1
SERIRQ
SATA_RXN0
SATA_RXP0
SATA_TXN0
SATA_TXP0
SATA_RXN1
SATA_RXP1
SATA_TXN1
SATA_TXP1
SATA_RXN3
SATA_RXP3
SATA_TXN3
SATA_TXP3
SATA_COMPPCH_JTAG_TDI_R
SATA3_COMP
SATA3_RBIAS
SATA_ACT#
GPIO21SDO_PCH
BBS_BIT0
ACZ_SYNC_R
LAD0
LAD0 <16,21,23,24>
LAD1
LAD1 <16,21,23,24>
LAD2
LAD2 <16,21,23,24>
LAD3
LFRAME#
TP18
TP19
LAD3 <16,21,23,24>
LFRAME# <16,21,23,24>
SERIRQ <16,23,24>
SATA_RXN0 <18>
SATA_RXP0 <18>
SATA_TXN0 <18>
SATA_TXP0 <18>
SATA_RXN1 <21>
SATA_RXP1 <21>
SATA_TXN1 <21>
SATA_TXP1 <21>
SATA_RXN3 <18>
SATA_RXP3 <18>
SATA_TXN3 <18>
SATA_TXP3 <18>
SATA HDD
mSATA
SATA ODD
Length < 500 mils
R9296 37.4/F_4
R9297 49.9/F_4
R9298 750/F_4
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Wednesday, March 06, 2013
Date: Sheet of
Wednesday, March 06, 2013
Date: Sheet of
Wednesday, March 06, 2013
+1.05V
Length < 500 mils
SATA_ACT# <20>
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
PCH 2/5(SATA/RTC/HDA/LPC)
PCH 2/5(SATA/RTC/HDA/LPC)
PCH 2/5(SATA/RTC/HDA/LPC)
1
RR3
RR3
RR3
9 35
9 35
9 35
09
ES1
ES1
ES1
5
4
3
2
1
PCH 3/5(PCIE/USB/CLK/NV)
Panther Point-M (PCI,USB,NVRAM)
D D
USB3_RXN1<19>
USB3_RXN2<19>
USB3_RXN3<16>
USB3_RXN4<16>
USB3_RXP1<19>
USB3_RXP2<19>
C C
For USB3.0 reserve
+3V_RUN
SATA_ODD_MD#<18>
CLK_33M_TPM<16>
B B
CLK_33M_IO<24>
CLK_PCI_EC<23>
CLK_LPC_DEBUG< 21>
*10P/50V_4_NC
USB3_RXP3<16>
USB3_RXP4<16>
USB3_TXN1<19>
USB3_TXN2<19>
USB3_TXN3<16>
USB3_TXN4<16>
USB3_TXP1<19>
USB3_TXP2<19>
USB3_TXP3<16>
USB3_TXP4<16>
PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
R226 10K_4
R224 10K_4
R225 10K_4
PCI_GNT3#
TP60
MPC_PWR_CTRL#
SATA_ODD_MD#
EXTTS_SNI_DRV0_PCH
EXTTS_SNI_DRV1_PCH
PCI_PME#
TP23
PCI_PLTRST# USB_OC0#
R204 22/J_4
CLK_PCI_FB CLK_PCI_FB_R
R203 22/J_4
R205 22/J_4
R195 22/J_4
R250 22/J_4
C316
*10P/50V_4_NC
CLK_33M_TPM_R
CLK_33M_IO_R
CLK_PCI_EC_R
CLK_33M_IO
CLK_PCI_FB
C362
CLK_33M_TPM
PLTRST#(CLG)
+3V_S5
C420
U27
3 5
TC7SH08FU
0.1U/10V_4
PLTRST#_R1
5
R126
4
R122 *0_4_NC
C211
*470P/50V_4_NC
2
1
PCI_PLTRST#
A A
BG26
BH25
BG16
AH38
AH37
AK43
AK45
AH12
AB46
AB45
AY16
BG46
BE28
BC30
BE32
BC28
BE30
BF32
BG32
AV26
BB26
AU28
AY30
AU26
AY26
AV28
AW30
*10P/50V_4_NC
300_4
BJ26
BJ16
C18
N30
H3
AM4
AM5
Y13
K24
L24
B21
M20
BJ32
K40
K38
H38
G38
C46
C44
E40
D47
E42
F46
G42
G40
C42
D44
K10
C6
H49
H43
J48
K42
H40
C373
U24E
TP1
TP2
TP3
TP4
TP5
TP6
TP7
TP8
TP9
TP10
TP11
TP12
TP13
TP14
TP15
TP16
TP17
TP18
TP19
TP20
TP21
TP22
TP23
TP24
TP25
TP26
TP27
TP28
TP29
TP30
TP31
TP32
TP33
TP34
TP35
TP36
TP37
TP38
TP39
TP40
PIRQA#
PIRQB#
PIRQC#
PIRQD#
REQ1# / GPIO50
REQ2# / GPIO52
REQ3# / GPIO54
GNT1# / GPIO51
GNT2# / GPIO53
GNT3# / GPIO55
PIRQE# / GPIO2
PIRQF# / GPIO3
PIRQG# / GPIO4
PIRQH# / GPIO5
PME#
PLTRST#
CLKOUT_PCI0
CLKOUT_PCI1
CLKOUT_PCI2
CLKOUT_PCI3
CLKOUT_PCI4
PantherPoint
C334
*10P/50V_4_NC
AY7
RSVD1
AV7
RSVD2
AU3
RSVD3
BG4
RSVD4
AT10
RSVD5
BC8
RSVD6
AU2
RSVD7
AT4
RSVD8
AT3
RSVD9
AT1
RSVD10
AY3
RSVD11
AT5
RSVD12
AV3
RSVD13
AV1
RSVD14
BB1
RSVD15
BA3
RSVD16
BB5
RSVD17
BB3
RSVD18
BB7
RSVD19
BE8
RSVD20
BD4
RSVD21
BF6
RSVD22
RSVD
PCI
+3V
+3V
+3V
USB
+3V
+3V
+3V
+3V
+3V
+3V
+3V
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
C374
22P/50V_4
RSVD23
RSVD24
RSVD25
RSVD26
RSVD27
RSVD28
RSVD29
USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P
USBP10N
USBP10P
USBP11N
USBP11P
USBP12N
USBP12P
USBP13N
USBP13P
USBRBIAS#
USBRBIAS
OC0# / GPIO59
OC1# / GPIO40
OC2# / GPIO41
OC3# / GPIO42
OC4# / GPIO43
OC5# / GPIO9
OC6# / GPIO10
OC7# / GPIO14
AV5
AV10
AT8
AY5
BA2
AT12
BF3
C24
A24
C25
B25
C26
A26
K28
H28
E28
D28
C28
A28
C29
B29
N28
M28
L30
K30
G30
E30
C30
A30
L32
K32
G32
E32
C32
A32
C33
B33
A14
K20
B17
C16
L16
A16
D14
C14
PCI/USBOC# Pull-up(CLG)
USB_OC7#
USB_OC6#
USB_OC5#
PLTRST# <5,16,17,21,23,24,25>
PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
SATA_ODD_MD#
EXTTS_SNI_DRV0_PCH
EXTTS_SNI_DRV1_PCH
MPC Switch Control
MPC_PWR_CTRL#
MPC_PWR_CTRL#
R596 10K_4
R597 10K_4
R598 10K_4
R217 8.2K/J_4
R428 8.2K/J_4
R216 8.2K/J_4
R219 8.2K/J_4
R232 10K_4
R410 10K_4
R239 10K_4
Low = MPC ON
High = MPC OFF (Default)
R211 *1K_4_NC
R233 10K_4
USBP0- <19>
USBP0+ <19>
USBP1- <19>
USBP1+ <19>
USBP2- <16>
USBP2+ <16>
USBP3- <16>
USBP3+ <16>
Port6, 7 not support for HM76
USBP9- <16>
USBP9+ <16>
USBP10- <21>
USBP10+ <21>
USBP12- <14>
USBP12+ <14>
USB_BIAS
R9340 22.6/F_4
USB_OC1#
USB_OC2#
USB_OC3#
USB_OC4#
USB_OC5#
USB_OC6#
USB_OC7#
OC USB Port
OC0#
0,1
OC1#
2,3
OC2#
4,5
OC3#
6,7
OC4#
8,9
OC5#
10,11
OC6#
12,13
OC7#
GPIO
+3V_S5
+3V_RUN
+3V_RUN
4
For USB on board
For SW BD
USB2.0(Debug)
USB2.0(Debug)
WLAN
Camera
USB_OC0# < 19>
USB_OC1# < 19>
USB_OC2# < 19>
USB_OC3# < 19>
USB_OC4# < 19>
EHCI1
EHCI2
Space: 15 mils,
Length < 500 mils
CLK_REQ/Strap Pin(CLG)
+3V_S5
+3V_S5
+3V_S5
SMB_PCH_CLK
SMB_PCH_DAT
R388 10K_4
R381 10K_4
R244 10K_4
R236 10K_4
R241 10K_4
R176 10K_4
R251 10K_4
+3V_RUN
R153 10K_4
R369 10K_4
R200 10K_4
R248 1K_4
R243 10K_4
R395 2.2K_4
R249 2.2K_4
R245 10K_4
R433
2.2K_4
+3V_S5
WLAN
Card Bus
LAN
WLAN
Card Bus
LAN
PCIE_CLK_REQ3#
PCIE_CLK_REQ0#
PCIE_CLK_REQ4#
CLK_PCIE_REQ6#
CLK_PEGB_REQ#
PCIE_CLKREQ_LAN#
CLK_PCIE_REQ7#
PCIE_CLKREQ_CARD#
PCIE_CLKREQ_WLAN#
PCIE_CLKREQ_PEG#
DRAMRST_CNTRL_PCH
SMBALERT#
SMB_ME0_CLK
SMB_ME0_DAT
SML1ALERT#_R
R452
2.2K_4
5
2
6
PCIE_RXN6_LAN<17>
PCIE_RXP6_LAN<17>
Q35
2N7002DW
3
PCIE_RXN2<21>
PCIE_RXP2<21>
PCIE_TXN2<21>
PCIE_TXP2<21>
PCIE_RXN3<25>
PCIE_RXP3<25>
PCIE_TXN3<25>
PCIE_TXP3<25>
PCIE_TXN6_LAN<17>
PCIE_TXP6_LAN<17>
PCIE_CLKREQ_WLAN#< 21>
CLK_PCIE_CARDN<25>
CLK_PCIE_CARDP<25 >
PCIE_CLKREQ_CARD#<25>
43
1
C440 0.1U/10V_4
C441 0.1U/10V_4
C235 0.1U/10V_4
C240 0.1U/10V_4
C220 0.1U/10V_4
C219 0.1U/10V_4
CLK_PCIE_WLANN<21>
CLK_PCIE_WLANP<21>
CLK_PCIE_LANN<17>
CLK_PCIE_LANP<17>
PCIE_CLKREQ_LAN#<17>
+3V_RUN
R434
R451
4.7K_4
4.7K_4
Panther Point-M (PCI-E,SMBUS,CLK)
U24B
BG34
PERN1
BJ34
PERP1
AV32
PETN1
AU32
PETP1
BE34
PERN2
BF34
PERP2
BB32
PCIE_TXN2_C
PCIE_TXP2_C
PCIE_TXN3_C
PCIE_TXP3_C
PCIE_TXN6_LAN_C
PCIE_TXP6_LAN_C
PCIE_CLK_REQ0#
PCIE_CLKREQ_WLAN#
PCIE_CLKREQ_CARD#
PCIE_CLK_REQ3#
PCIE_CLK_REQ4#
PCIE_CLKREQ_LAN#
CLK_PEGB_REQ#
CLK_PCIE_REQ6#
CLK_PCIE_REQ7#
CLKOUTFLEX0 /GP IO64
CLKOUTFLEX1 /GP IO65
CLKOUTFLEX2 /GP IO66
CLKOUTFLEX3 /GP IO67
PETN2
AY32
PETP2
BG36
PERN3
BJ36
PERP3
AV34
PETN3
AU34
PETP3
BF36
PERN4
BE36
PERP4
AY34
PETN4
BB34
PETP4
BG37
PERN5
BH37
PERP5
AY36
PETN5
BB36
PETP5
BJ38
PERN6
BG38
PERP6
AU36
PETN6
AV36
PETP6
BG40
PERN7
BJ40
PERP7
AY40
PETN7
BB40
PETP7
BE38
PERN8
BC38
PERP8
AW38
PETN8
AY38
PETP8
Y40
CLKOUT_PCIE0N
Y39
CLKOUT_PCIE0P
J2
PCIECLKRQ0# / GPIO73
AB49
CLKOUT_PCIE1N
AB47
CLKOUT_PCIE1P
M1
PCIECLKRQ1# / GPIO18
AA48
CLKOUT_PCIE2N
AA47
CLKOUT_PCIE2P
V10
PCIECLKRQ2# / GPIO20
Y37
CLKOUT_PCIE3N
Y36
CLKOUT_PCIE3P
A8
PCIECLKRQ3# / GPIO25
Y43
CLKOUT_PCIE4N
Y45
CLKOUT_PCIE4P
L12
PCIECLKRQ4# / GPIO26
V45
CLKOUT_PCIE5N
V46
CLKOUT_PCIE5P
L14
PCIECLKRQ5# / GPIO44
AB42
CLKOUT_PEG_B_N
AB40
CLKOUT_PEG_B_P
E6
PEG_B_CLKRQ# / GPIO56
V40
CLKOUT_PCIE6N
V42
CLKOUT_PCIE6P
T13
PCIECLKRQ6# / GPIO45
V38
CLKOUT_PCIE7N
V37
CLKOUT_PCIE7P
K12
PCIECLKRQ7# / GPIO46
AK14
CLKOUT_ITPXDP_N
AK13
CLKOUT_ITPXDP_P
PantherPoint
SMBus/Pull-up(CLG)
For DIMMs
MBCLK<23>SMB_RUN_CLK <13>
MBDATA<23>SMB_RUN_DAT <13>
Configurable as a GPIO or as a programmable ou tput clock
which can be co nfigured as one of the followin g:
33 /27 /48/ 14. 318 MHz / DC Ou tput logic ‘0’
‧
unsupported clo ck output value (Default) / 27/ 14.318 MHz outp ut to SIO/EC /4 8/24 MHz
33/25/27/48/24 /14.318 MHz / D C Output logic ‘ 0’
‧
27/14.318 out put to SIO/48/2 4 MHz (Default)
‧
SMB_RUN_CLK
SMB_RUN_DAT
For EC
MBCLK SMB_ME1_CLK
+3V_S5
+3V_S5
SMBUSController
+3V_S5
SML1ALERT# / PCHHOT# / GPIO74
+3V_S5
+3V_S5
PCI-E*
+3V_S5
+3V_S5
CLOCKS
+3V
+3V
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V
+3V
+3V_S5
+3V
+3V
C8422
*10P/50V_4_NC
Q33
5
+3V_S5+3V_RUN
2
+3V_S5+3V_RUN
6
2N7002DW
2
SMBALERT# / GPIO11
SML0ALERT# / GPIO60
SML1CLK / GPIO58
SML1DATA / GPIO75
Link
PEG_A_CLKRQ# / GPIO47
CLKOUT_PEG_A_N
CLKOUT_PEG_A_P
CLKOUT_DMI_N
CLKOUT_DMI_P
CLKOUT_DP_N
CLKOUT_DP_P
CLKIN_DMI_N
CLKIN_DMI_P
CLKIN_GND1_N
CLKIN_GND1_P
CLKIN_DOT_96N
CLKIN_DOT_96P
CLKIN_SATA_N
CLKIN_SATA_P
CLKIN_PCILOOPBACK
XCLK_RCOMP
CLKOUTFLEX0 / GPIO64
CLKOUTFLEX1 / GPIO65
CLKOUTFLEX2 / GPIO66
CLKOUTFLEX3 / GPIO67
FLEX CLOCKS
C8430
*10P/50V_4_NC
R431
2.2K_4
43
1
SMBCLK
SMBDATA
SML0CLK
SML0DATA
CL_CLK1
CL_DATA1
CL_RST1#
REFCLK14IN
XTAL25_IN
XTAL25_OUT
+3V_S5
SMB_ME1_DATMBDATA
R407
2.2K_4
E12
H14
C9
A12
C8
G12
C13
E14
M16
M7
T11
P10
M10
AB37
AB38
AV22
AU22
AM12
AM13
BF18
BE18
BJ30
BG30
G24
E24
AK7
AK5
K45
H45
V47
V49
Y47
K43
F47
H47
K49
SMBALERT#
SMB_PCH_CLK
SMB_PCH_DAT
DRAMRST_CNTRL_PCH
SMB_ME0_CLK
SMB_ME0_DAT
SML1ALERT#_R
SMB_ME1_CLK
SMB_ME1_DAT
PCIE_CLKREQ_PEG#
CLK_CPU_BCLKN <5>
CLK_CPU_BCLKP <5>
CLK_BUF_PCIE_3GPLLN
CLK_BUF_PCIE_3GPLLP
CLK_BUF_BCLKN
CLK_BUF_BCLKP
CLK_BUF_DREFCLKN
CLK_BUF_DREFCLKP
CLK_BUF_DREFSSCLKN
CLK_BUF_DREFSSCLKP
CLK_PCH_14M
CLK_PCI_FB
XTAL25_IN
XTAL25_OUT
XCLK_RCOMP
TP27
TP25
IOCLK_24M_R
For DIMMs
DRAMRST_CNTRL_PCH <5>
For EC
R9329 10K_4
R601 10K_4
R9331 10K_4
R602 10K_4
R9335 10K_4
R603 10K_4
R9337 10K_4
R604 10K_4
R9339 10K_4
C391 10P/50V_4
4
3
Y1
R360
25MHz
1M_4
1
2
C443 10P/50V_4
R349 90.9/F_4
R252 22/J_4
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
+1.05V
C369
22P/50V_4
MBCLK
MBDATA
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
PCH 3/5(PCIE/USB/CLK/NV)
PCH 3/5(PCIE/USB/CLK/NV)
PCH 3/5(PCIE/USB/CLK/NV)
Wednesday, March 06, 2013
Wednesday, March 06, 2013
Wednesday, March 06, 2013
1
IOCLK_24M <24>
*10P/50V_4_NC
C8416
RR3
RR3
RR3
10
C8421
*10P/50V_4_NC
10 35
10 35
10 35
ES1
ES1
ES1
5
4
3
2
1
11
PCH 4/5(GPIO/CPU/STRAP/GND)
Panther Point (GND)
D D
BMBUSY#
EC_EXT_SMI#<23>
EC_EXT_SCI#<23>
TPM_DET<16>
SATA_MCARD3_DET#<21>
BIOS_WP#<23>
C C
PLL_ODVR_EN<9>
WLAN_RADIO_DIS#<21>
MODC_EN<18>
EC_EXT_SMI#
PCIE_MCARD1_DET #
EC_EXT_SCI#
TPM_DET
HOST_ALERT#1_R
SATA_MCARD3_DET#
GPIO27
GPIO34
CAMERA_CBL_DET#
GPIO37
WLAN_RADIO_DIS#
DGPU_PRSNT#
TEST_SET_UP
MODC_EN
SV_DET
GPIO Pull-up/Pull-down(CLG)
B B
A A
TPM_DET
EC_EXT_SMI#
EC_EXT_SCI#
GPIO34
EC_A20GATE
EC_RCIN#
BMBUSY#
PCIE_MCARD1_DET #
SATA_MCARD3_DET#
GPIO27
HOST_ALERT#1_R
Intel ME Crypto Transport Layer
Security (TLS) cipher suite
Low = Disable (Default)
R386 10K_4
R401 10K_4
R223 10K_4
R377 10K_4
R181 10K_4
R180 10K_4
R184 10K_4
R354 10K_4
R589 10K_4
R426 10K_4
R389 *1K_4_NC
High = Enable
MFG-TEST
WLAN_RADIO_DIS#
R370 10K_4
5
Panther Point (GPIO,VSS_NCTF,RSVD)
U24F
+3V_S5
+3V_RUN
+3V_S5
+3V_RUN
T7
BMBUSY# / GPIO0
A42
TACH1 / GPIO1
H36
TACH2 / GPIO6
E38
TACH3 / GPIO7
C10
+3V_S5
GPIO8
C4
LAN_PHY_PWR_CTRL / GPIO12
G2
+3V_S5
GPIO15
U2
SATA4GP / GPIO16
D40
TACH0 / GPIO17
T5
SCLOCK / GPIO22
E8
GPIO24 / MEM_LED
E16
V13
A44
A45
A46
B47
BD1
BD49
BE1
BE49
BF1
BF49
GPIO27
P8
GPIO28
K1
STP_PCI# / GPIO34
K4
GPIO35
V8
SATA2GP / GPIO36
M5
SATA3GP / GPIO37
N2
SLOAD / GPIO38
M3
SDATAOUT0 / GPIO39
SDATAOUT1 / GPIO48
V3
SATA5GP / GPIO49
D6
GPIO57
A4
VSS_NCTF_1
VSS_NCTF_2
VSS_NCTF_3
VSS_NCTF_4
A5
VSS_NCTF_5
A6
VSS_NCTF_6
B3
VSS_NCTF_7
VSS_NCTF_8
VSS_NCTF_9
VSS_NCTF_10
VSS_NCTF_11
VSS_NCTF_12
VSS_NCTF_13
VSS_NCTF_14
PantherPoint
+3V_S5
R240 *10K_4_NC
+3V_RUN
DSW
+3V_S5
+3V
+3V_S5
+3V
+3V
+3V
+3V
+3V
+3V
+3V
+3V_S5
+3V
+3V
+3V
+3V
+3V
+3V
+3V
DGPU_PRSNT#
RP30 10KX4
1
3
5
7
+3V
+3V
+3V
+3V
+3V_S5
GPIO
NCTF
R378 100K_4
SV_DET
2
4
6
8
4
TACH4 / GPIO68
TACH5 / GPIO69
TACH6 / GPIO70
TACH7 / GPIO71
CPU/MISC
VSS_NCTF_15
VSS_NCTF_16
VSS_NCTF_17
VSS_NCTF_18
VSS_NCTF_19
VSS_NCTF_20
VSS_NCTF_21
VSS_NCTF_22
VSS_NCTF_23
VSS_NCTF_24
VSS_NCTF_25
VSS_NCTF_26
VSS_NCTF_27
VSS_NCTF_28
VSS_NCTF_29
VSS_NCTF_30
VSS_NCTF_31
VSS_NCTF_32
A20GATE
PECI
RCIN#
PROCPWRGD
THRMTRIP#
INIT3_3V#
DF_TVS
TS_VSS1
TS_VSS2
TS_VSS3
TS_VSS4
NC_1
R235 100K_4
PCH_GPIO69
PCH_GPIO70
PCH_GPIO71
PCH_GPIO68
C40
PCH_GPIO68
B41
PCH_GPIO69
C41
PCH_GPIO70
A40
PCH_GPIO71
P4
AU16
PCH_PECI EC_PECI
P5
EC_RCIN#
AY11
AY10
PCH_THRMT RIP#BIOS_REC
T14
AY1
R321 *0/short_4_NC
AH8
AK11
AH10
AK10
P37
BG2
BG48
BH3
BH47
BJ4
BJ44
BJ45
BJ46
BJ5
BJ6
C2
C48
D1
D49
E1
E49
F1
F49
EC_A20GATE <23>
R125 *0_4_NC
EC_RCIN# <23>
H_PWRGOOD <5>
R139 390/J_4
DF_TVS <9>
SV_SET_UP
High = Strong (Default)
TEST_SET_UP
R154 10K_4
R212 100K_4
FDI TERMINATION
VOLTAGE
OVERRIDE
EC_PECI <5,23>
PM_THRMTRIP# <5>
+3V_RUN
GPIO37
R207 *1K/F_4_NC
LOW - Tx, Rx terminated
to same voltage
3
U24H
H5
VSS[0]
AA17
VSS[1]
AA2
VSS[2]
AA3
VSS[3]
AA33
VSS[4]
AA34
VSS[5]
AB11
VSS[6]
AB14
VSS[7]
AB39
VSS[8]
AB4
VSS[9]
AB43
VSS[10]
AB5
VSS[11]
AB7
VSS[12]
AC19
VSS[13]
AC2
VSS[14]
AC21
VSS[15]
AC24
VSS[16]
AC33
VSS[17]
AC34
VSS[18]
AC48
VSS[19]
AD10
VSS[20]
AD11
VSS[21]
AD12
VSS[22]
AD13
VSS[23]
AD19
VSS[24]
AD24
VSS[25]
AD26
VSS[26]
AD27
VSS[27]
AD33
VSS[28]
AD34
VSS[29]
AD36
VSS[30]
AD37
VSS[31]
AD38
VSS[32]
AD39
VSS[33]
AD4
VSS[34]
AD40
VSS[35]
AD42
VSS[36]
AD43
VSS[37]
AD45
VSS[38]
AD46
VSS[39]
AD8
VSS[40]
AE2
VSS[41]
AE3
VSS[42]
AF10
VSS[43]
AF12
VSS[44]
AD14
VSS[45]
AD16
VSS[46]
AF16
VSS[47]
AF19
VSS[48]
AF24
VSS[49]
AF26
VSS[50]
AF27
VSS[51]
AF29
VSS[52]
AF31
VSS[53]
AF38
VSS[54]
AF4
VSS[55]
AF42
VSS[56]
AF46
VSS[57]
AF5
VSS[58]
AF7
VSS[59]
AF8
VSS[60]
AG19
VSS[61]
AG2
VSS[62]
AG31
VSS[63]
AG48
VSS[64]
AH11
VSS[65]
AH3
VSS[66]
AH36
VSS[67]
AH39
VSS[68]
AH40
VSS[69]
AH42
VSS[70]
AH46
VSS[71]
AH7
VSS[72]
AJ19
VSS[73]
AJ21
VSS[74]
AJ24
VSS[75]
AJ33
VSS[76]
AJ34
VSS[77]
AK12
VSS[78]
AK3
VSS[79]
PantherPoint
BIOS_REC
BIOS RECOVERY
R175 10K_4
R169 *0_4_NC
+3V_RUN
High = Disable (Default)
Low = Enable
R161 10K_4
DMI TERMINATION
VOLTAGE OVERRIDE
AK38
VSS[80]
AK4
VSS[81]
AK42
VSS[82]
AK46
VSS[83]
AK8
VSS[84]
AL16
VSS[85]
AL17
VSS[86]
AL19
VSS[87]
AL2
VSS[88]
AL21
VSS[89]
AL23
VSS[90]
AL26
VSS[91]
AL27
VSS[92]
AL31
VSS[93]
AL33
VSS[94]
AL34
VSS[95]
AL48
VSS[96]
AM11
VSS[97]
AM14
VSS[98]
AM36
VSS[99]
AM39
VSS[100]
AM43
VSS[101]
AM45
VSS[102]
AM46
VSS[103]
AM7
VSS[104]
AN2
VSS[105]
AN29
VSS[106]
AN3
VSS[107]
AN31
VSS[108]
AP12
VSS[109]
AP19
VSS[110]
AP28
VSS[111]
AP30
VSS[112]
AP32
VSS[113]
AP38
VSS[114]
AP4
VSS[115]
AP42
VSS[116]
AP46
VSS[117]
AP8
VSS[118]
AR2
VSS[119]
AR48
VSS[120]
AT11
VSS[121]
AT13
VSS[122]
AT18
VSS[123]
AT22
VSS[124]
AT26
VSS[125]
AT28
VSS[126]
AT30
VSS[127]
AT32
VSS[128]
AT34
VSS[129]
AT39
VSS[130]
AT42
VSS[131]
AT46
VSS[132]
AT7
VSS[133]
AU24
VSS[134]
AU30
VSS[135]
AV16
VSS[136]
AV20
VSS[137]
AV24
VSS[138]
AV30
VSS[139]
AV38
VSS[140]
AV4
VSS[141]
AV43
VSS[142]
AV8
VSS[143]
AW14
VSS[144]
AW18
VSS[145]
AW2
VSS[146]
AW22
VSS[147]
AW26
VSS[148]
AW28
VSS[149]
AW32
VSS[150]
AW34
VSS[151]
AW36
VSS[152]
AW40
VSS[153]
AW48
VSS[154]
AV11
VSS[155]
AY12
VSS[156]
AY22
VSS[157]
AY28
VSS[158]
+3V_RUN+3V_RUN
CAMERA_CBL_DET#
R158
*200K/F_4_NC
Low = Tx, Rx terminated to
same voltage (DC Coupling Mode)
(DEFAULT)
2
AY42
AY46
BB12
BB16
BB20
BB22
BB24
BB28
BB30
BB38
BB46
BC14
BC18
BC22
BC26
BC32
BC34
BC36
BC40
BC42
BC48
BD46
BE22
BE26
BE40
BF10
BF12
BF16
BF20
BF22
BF24
BF26
BF28
BF30
BF38
BF40
BG17
BG21
BG33
BG44
BH11
BH15
BH17
BH19
BH27
BH31
BH33
BH35
BH39
BH43
AY4
AY8
B11
B15
B19
B23
B27
B31
B35
B39
B7
F45
BB4
BC2
BD5
BD3
BF8
BG8
H10
BH7
D3
D12
D16
D18
D22
D24
D26
D30
D32
D34
D38
D42
D8
E18
E26
G18
G20
G26
G28
G36
G48
H12
H18
H22
H24
H26
H30
H32
H34
F3
U24I
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]
VSS[181]
VSS[182]
VSS[183]
VSS[184]
VSS[185]
VSS[186]
VSS[187]
VSS[188]
VSS[189]
VSS[190]
VSS[191]
VSS[192]
VSS[193]
VSS[194]
VSS[195]
VSS[196]
VSS[197]
VSS[198]
VSS[199]
VSS[200]
VSS[201]
VSS[202]
VSS[203]
VSS[204]
VSS[205]
VSS[206]
VSS[207]
VSS[208]
VSS[209]
VSS[210]
VSS[211]
VSS[212]
VSS[213]
VSS[214]
VSS[215]
VSS[216]
VSS[217]
VSS[218]
VSS[219]
VSS[220]
VSS[221]
VSS[222]
VSS[223]
VSS[224]
VSS[225]
VSS[226]
VSS[227]
VSS[228]
VSS[229]
VSS[230]
VSS[231]
VSS[232]
VSS[233]
VSS[234]
VSS[235]
VSS[236]
VSS[237]
VSS[238]
VSS[239]
VSS[240]
VSS[241]
VSS[242]
VSS[243]
VSS[244]
VSS[245]
VSS[246]
VSS[247]
VSS[248]
VSS[249]
VSS[250]
VSS[251]
VSS[252]
VSS[253]
VSS[254]
VSS[255]
VSS[256]
VSS[257]
VSS[258]
PantherPoint
H46
VSS[259]
K18
VSS[260]
K26
VSS[261]
K39
VSS[262]
K46
VSS[263]
K7
VSS[264]
L18
VSS[265]
L2
VSS[266]
L20
VSS[267]
L26
VSS[268]
L28
VSS[269]
L36
VSS[270]
L48
VSS[271]
M12
VSS[272]
P16
VSS[273]
M18
VSS[274]
M22
VSS[275]
M24
VSS[276]
M30
VSS[277]
M32
VSS[278]
M34
VSS[279]
M38
VSS[280]
M4
VSS[281]
M42
VSS[282]
M46
VSS[283]
M8
VSS[284]
N18
VSS[285]
P30
VSS[286]
N47
VSS[287]
P11
VSS[288]
P18
VSS[289]
T33
VSS[290]
P40
VSS[291]
P43
VSS[292]
P47
VSS[293]
P7
VSS[294]
R2
VSS[295]
R48
VSS[296]
T12
VSS[297]
T31
VSS[298]
T37
VSS[299]
T4
VSS[300]
W34
VSS[301]
T46
VSS[302]
T47
VSS[303]
T8
VSS[304]
V11
VSS[305]
V17
VSS[306]
V26
VSS[307]
V27
VSS[308]
V29
VSS[309]
V31
VSS[310]
V36
VSS[311]
V39
VSS[312]
V43
VSS[313]
V7
VSS[314]
W17
VSS[315]
W19
VSS[316]
W2
VSS[317]
W27
VSS[318]
W48
VSS[319]
Y12
VSS[320]
Y38
VSS[321]
Y4
VSS[322]
Y42
VSS[323]
Y46
VSS[324]
Y8
VSS[325]
BG29
VSS[328]
N24
VSS[329]
AJ3
VSS[330]
AD47
VSS[331]
B43
VSS[333]
BE10
VSS[334]
BG41
VSS[335]
G14
VSS[337]
H16
VSS[338]
T36
VSS[340]
BG22
VSS[342]
BG24
VSS[343]
C22
VSS[344]
AP13
VSS[345]
M14
VSS[346]
AP3
VSS[347]
AP1
VSS[348]
BE16
VSS[349]
BC16
VSS[350]
BG28
VSS[351]
BJ28
VSS[352]
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Wednesday, March 06, 2013
Date: Sheet of
Wednesday, March 06, 2013
Date: Sheet of
Wednesday, March 06, 2013
PROJECT :
PCH 4/5(GPIO/CPU/STRAP/GND)
PCH 4/5(GPIO/CPU/STRAP/GND)
PCH 4/5(GPIO/CPU/STRAP/GND)
RR3
RR3
RR3
11 35
11 35
1
11 35
ES1
ES1
ES1
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