MXIC MX29F002BPI-90, MX29F002BQC-12, MX29F002BQC-55, MX29F002BQC-70, MX29F002BQC-90 Datasheet

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GENERAL DESCRIPTION
The MX29F002T/B is a 2-mega bit Flash memory organ­ized as 256K bytes of 8 bits only. MXIC's Flash memories offer the most cost-effective and reliable read/write non­volatile random access memory. The MX29F002T/B is packaged in 32-pin PDIP,PLCC and 32-pin TSOP(I). It is designed to be reprogrammed and erased in-system or in­standard EPROM programmers.
The standard MX29F002T/B offers access time as fast as 55ns, allowing operation of high-speed microprocessors without wait states. To eliminate bus contention, the MX29F002T/B has separate chip enable (CE) and output enable (OE) controls.
MXIC's Flash memories augment EPROM functionality with in-circuit electrical erasure and programming. The MX29F002T/B uses a command register to manage this functionality. The command register allows for 100% TTL level control inputs and fixed power supply levels during erase and programming, while maintaining maximum EPROM compatibility.
FEATURES
262,144x 8 only
Fast access time: 55/70/90/120ns
Low power consumption
- 30mA maximum active current(5MHz)
- 1uA typical standby current
Programming and erasing voltage 5V ± 10%
Command register architecture
- Byte Programming (7us typical)
- Sector Erase (16K-Byte x1, 8K-Byte x 2, 32K-Byte x1, and 64K-Byte x 3)
Auto Erase (chip & sector) and Auto Program
- Automatically erase any combination of sectors or the whole chip with Erase Suspend capability.
- Automatically programs and verifies data at specified address
Erase Suspend/Erase Resume
- Suspends an erase operation to read data from, or program data to, a sector that is not being erased, then resumes the erase operation.
Status Reply
1
- Data polling & Toggle bit for detection of program and erase cycle completion.
Sector protection
- Hardware method to disable any combination of sectors from program or erase operations
- Sector protect/unprotect for 5V only system or 5V/ 12V system
100,000 minimum erase/program cycles
Latch-up protected to 100mA from -1 to VCC+1V
Boot Code Sector Architecture
- T = Top Boot Sector
- B = Bottom Boot Sector
Hardware RESET pin(only for 29F002T/B)
- Resets internal state machine to read mode
Low VCC write inhibit is equal to or less than 3.2V
Package type:
- 32-pin PDIP
- 32-pin PLCC
- 32-pin TSOP (Type 1)
20 years data retention
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MXIC's Flash technology reliably stores memory contents even after 100,000 erase and program cycles. The MXIC cell is designed to optimize the erase and programming mechanisms. In addition, the combination of advanced tunnel oxide processing and low internal electric fields for erase and programming operations produces reliable cycling. The MX29F002T/B uses a 5.0V ± 10% VCC supply to perform the High Reliability Erase and auto Program/Erase algorithms.
The highest degree of latch-up protection is achieved with MXIC's proprietary non-epi process. Latch-up protection is proved for stresses up to 100 milliamps on address and data pin from -1V to VCC + 1V.
MX29F002/002N
2M-BIT [256K x 8] CMOS FLASH MEMORY
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MX29F002/002N
PIN CONFIGURATIONS
32 PDIP
SECTOR STRUCTURE32 PLCC
32 TSOP (TYPE 1)
(NORMAL TYPE)
PIN DESCRIPTION
SYMBOL PIN NAME
A0~A17 Address Input Q0~Q7 Data Input/Output CE Chip Enable Input WE Write Enable Input RESET Hardware Reset Pin/Sector Protect Unlock OE Output Enable Input VCC Power Supply Pin (+5V) GND Ground Pin
MX29F002T Sector Architecture
MX29F002B Sector Architecture
MX29F002T/B
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
RESET
A16 A15 A12
A7 A6 A5 A4 A3 A2 A1 A0 Q0 Q1 Q2
GND
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
VCC WE A17 A14 A13 A8 A9 A11 OE A10 CE Q7 Q6 Q5 Q4 Q3
NC on MX29F002NT/B
A11
A9
A8 A13 A14 A17
WE
VCC
RESET
A16 A15 A12
A7
A6
A5
A4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
OE A10 CE Q7 Q6 Q5 Q4 Q3 GND Q2 Q1 Q0 A0 A1 A2 A3
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
MX29F002T/B
(NC on MX29F002NT/B)
1
4
5
9
13
14 17 20
21
25
29
32
30
A14 A13 A8 A9 A11 OE A10 CE Q7
A7 A6 A5 A4 A3 A2 A1 A0 Q0
Q1
Q2
VSS
Q3Q4Q5
Q6
A12
A15
A16
RESET
VCCWEA17
MX29F002T/B
NC on MX29F002NT/B
16 K-BYTE
8 K-BYTE
8 K-BYTE
32 K-BYTE
00000H
3FFFFH
(BOOT SECTOR)
64 K-BYTE
64 K-BYTE 64 K-BYTE
3BFFFH
39FFFH
37FFFH 2FFFFH 1FFFFH
0FFFFH
A17~A0
16 K-BYTE
8 K-BYTE
8 K-BYTE
32 K-BYTE
00000H
(BOOT SECTOR)
64 K-BYTE
64 K-BYTE 64 K-BYTE
3FFFFH 2FFFFH 1FFFFH
07FFFH 05FFFH 03FFFH
0FFFFH
A17~A0
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BLOCK DIAGRAM
CONTROL INPUT LOGIC
PROGRAM/ERASE
HIGH VOLTAGE
WRITE
STATE
MACHINE
(WSM)
STATE REGISTER
MX29F002
FLASH ARRA Y
X-DECODER
ADDRESS
LA TCH
AND
BUFFER
Y-PASS GATE
Y-DECODER
ARRAY
SOURCE
HV
COMMAND
DATA DECODER
COMMAND
DATA LATCH
I/O BUFFER
PGM
DATA
HV
PROGRAM
DATA LATCH
SENSE
AMPLIFIER
Q0-Q7
A0~A17
WE
OE
WP
RESET
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AUTOMATIC PROGRAMMING
The MX29F002T/B is byte programmable using the Automatic Programming algorithm. The Automatic Programming algorithm does not require the system to time out or verify the data programmed. The typical chip programming time of the MX29F002T/B at room temperature is less than 3.5 seconds.
AUTOMATIC CHIP ERASE
Typical erasure at room temperature is accomplished in less than 3 seconds. The device is erased using the Automatic Erase algorithm. The Automatic Erase algorithm automatically programs the entire array prior to electrical erase. The timing and verification of electrical erase are internally controlled by the device.
AUTOMATIC SECTOR ERASE
The MX29F002T/B is sector(s) erasable using MXIC's Auto Sector Erase algorithm. Sector erase modes allow sectors of the array to be erased in one erase cycle. The Automatic Sector Erase algorithm automatically pro­grams the specified sector(s) prior to electrical erase. The timing and verification of electrical erase are inter­nally controlled by the device.
AUTOMATIC PROGRAMMING ALGORITHM
MXIC's Automatic Programming algorithm requires the user to only write a program set-up commands include 2 unlock write cycle and A0H and a program command (program data and address). The device automatically times the programming pulse width, verifies the pro­gram, and counts the number of sequences. A status bit similar to DATA polling and a status bit toggling between consecutive read cycles, provides feedback to the user as to the status of the programming operation.
MXIC's Automatic Erase algorithm requires the user to write commands to the command register using stand­ard microprocessor write timings. The device will automatically pre-program and verify the entire array. Then the device automatically times the erase pulse width, verifies the erase, and counts the number of sequences. A status bit similar to DATA polling and status bit toggling between consecutive read cycles provides feedback to the user as to the status of the programming operation.
Commands are written to the command register using standard microprocessor write timings. Register con­tents serve as inputs to an internal state-machine which controls the erase and programming circuitry. During write cycles, the command register internally latches address and data needed for the programming and erase operations. During a system write cycle, addresses are latched on the falling edge, and data are latched on the rising edge of WE .
MXIC's Flash technology combines years of EPROM experience to produce the highest levels of quality, relia­bility, and cost effectiveness. The MX29F002T/B electri­cally erases all bits simultaneously using Fowler-Nord­heim tunneling. The bytes are programmed one byte at a time using the EPROM programming mechanism of hot electron injection.
During a program cycle, the state-machine will control the program sequences and command register will not re­spond to any command set. During a Sector Erase cycle, the command register will only respond to Erase Suspend command. After Erase Suspend is completed, the device stays in read mode. After the state machine has com­pleted its task, it will allow the command register to respond to its full command set.
AUTOMATIC ERASE ALGORITHM
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First Bus Second Bus Third Bus Fourth Bus Fifth Bus Sixth Bus
Command Bus Cycle Cycle Cycle Cycle Cycle Cycle
Cycle Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data Reset 1 XXXH F0H Read 1 RA RD Read Silicon ID 4 555H AAH 2AAH 5 5H 555H 90H ADI DDI Sector Protect 4 555H AAH 2AAH 55H 555H 90H (SA) 00H Verification (X02H) 01H Porgram 4 555H AAH 2AAH 55H 555H A0H PA PD Chip Erase 6 555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H 555H 10H Sector Erase 6 555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H SA 30H Sector Erase Suspend 1 XXXH B0H Sector Erase Resume 1 XXXH 30H Unlock for sector 6 555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H 555H 20H protect/unprotect
TABLE1. SOFTWARE COMMAND DEFINITIONS
COMMAND DEFINITIONS
Device operations are selected by writing specific ad­dress and data sequences into the command register. Writing incorrect address and data values or writing them in the improper sequence will reset the device to the read mode. Table 1 defines the valid register command
Note:
1. ADI = Address of Device identifier; A1=0,A0 =0 for manufacture code,A1=0, A0 =1 for device code (Refer to Table 3). DDI = Data of Device identifier : C2H for manufacture code, 00B0h/0034h for device code. X = X can be VIL or VIH RA=Address of memory location to be read. RD=Data to be read at location RA.
2. PA = Address of memor y location to be programmed. PD = Data to be programmed at location PA. SA = Address to the sector to be erased.
3.The system should generate the following address patterns: 555H or 2AAH to Address A0~A10. Address bit A11~A17=X=Don't care for all address commands except for Program Address (PA) and Sector Address (SA). Write Sequence may be initiated with A11~A17 in either state.
4.For Sector Protect V erification Operation : If read out data is 01H, it means the sector has been protected. If read out data is 00H, it means the sector is still not being protected.
sequences. Note that the Erase Suspend (B0H) and Erase Resume (30H) commands are valid only while the Sector Erase operation is in progress. Either of the two reset command sequences will reset the device(when applicable).
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MX29F002/002N
Pins CE OE WE A0 A1 A6 A9 Q0~Q7 Mode
Read Silicon ID L L H L L X V
ID
(2) C2H Manfacturer Code(1) Read Silicon ID L L H H L X VID(2) B0h/34h Device Code(1) Read L L H A0 A1 A6 A9 D
OUT
Standby H X X X X X X HIGH Z Output Disable L H H X X X X HIGH Z Write L H L A0 A1 A6 A9 DIN(3) Sector Protect with 12V L VID(2) L X X L VID(2) X system(6) Chip Unprotect with 12V L VID(2) L X X H VID(2) X system(6) Verify Sector Protect L L H X H X VID(2) Code(5) with 12V system Sector Protect without 12V L H L X X L H X system (6) Chip Unprotect without 12V L H L X X H H X system (6) Verify Sector Protect/Unprotect L L H X H X H Code(5) without 12V system (7) Reset X X X X X X X HIGH Z
TABLE 2. MX29F002T/B BUS OPERATION
NOTES:
1. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 1.
2. VID is the Silicon-ID-Read high voltage, 11.5V to 12.5V.
3. Refer to Table 1 for valid Data-In during a write operation.
4. X can be VIL or VIH.
5. Code=00H means unprotected. Code=01H means protected. A17~A13=Sector address for sector protect.
6. Refer to sector protect/unprotect algorithm and waveform. Must issue "unlock for sector protect/unprotect" command before "sector protect/unprotect without 12V system" command.
7. The "verify sector protect/unprotect without 12V sysytem" is only following "Sector protect/unprotect without 12V system" com­mand.
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READ/RESET COMMAND
The read or reset operation is initiated by writing the read/ reset command sequence into the command register. Microprocessor read cycles retrieve array data. The device remains enabled for reads until the command register contents are altered.
If program-fail or erase-fail happen, the write of F0H will reset the device to abort the operation. A valid command must then be written to place the device in the desired state.
SILICON-ID-READ COMMAND
Flash memories are intended for use in applications where the local CPU alters memory contents. As such, manufacturer and device codes must be accessible while the device resides in the target system. PROM programmers typically access signature codes by raising A9 to a high voltage. However, multiplexing high voltage onto address lines is not generally desired system design practice.
The MX29F002T/B contains a Silicon-ID-Read operation to supplement traditional PROM programming methodol­ogy. The operation is initiated by writing the read silicon ID command sequence into the command register. Fol­lowing the command write, a read cycle with A1=VIL, A0=VIL retrieves the manufacturer code of C2H. A read cycle with A1=VIL, A0=VIH returns the device code of B0h for MX29F002T, 34h for MX29F002B.
Pins A0 A1 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Code(Hex)Code
Manufacture code VIL VIL 1 1 0 0 0 0 1 0 C2H Device code VIHVIL101 1 0000 B0h for MX29F002T Device code VIHVIL001 1 0100 34h for MX29F002B
Sector Protection X VIH 0 0 0 0 0 0 0 1 01H (Protected) Verification X VIH 0 0 0 0 0 0 0 0 00H (Unprotected)
TABLE 3. EXPANDED SILICON ID CODE
SET-UP AUTOMATIC CHIP/SECTOR ERASE COMMANDS
Chip erase is a six-bus cycle operation. There are two "unlock" write cycles. These are followed by writing the "set-up" command 80H. Two more "unlock" write cycles are then followed by the chip erase command 10H.
The Automatic Chip Erase does not require the device to be entirely pre-programmed prior to executing the Auto­matic Chip Erase. Upon executing the Automatic Chip Erase, the device will automatically program and verify the entire memory for an all-zero data pattern. When the device is automatically verified to contain an all-zero pattern, a self-timed chip erase and verify begin. The erase and verify operations are completed when the data on Q7 is "1" at which time the device returns to the Read mode. The system is not required to provide any control or timing during these operations.
When using the Automatic Chip Erase algorithm, note that the erase automatically terminates when adequate erase margin has been achieved for the memory array(no erase verify command is required).
If the Erase operation was unsuccessful, the data on Q5 is "1"(see Table 4), indicating the erase operation exceed internal timing limit.
The automatic erase begins on the rising edge of the last WE pulse in the command sequence and terminates when the data on Q7 is "1" and the data on Q6 stops toggling for two consecutive read cycles, at which time the device returns to the Read mode.
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SET-UP AUTOMATIC SECTOR ERASE COMMANDS
The Automatic Sector Erase does not require the device to be entirely pre-programmed prior to executing the Automatic Set-up Sector Erase command and Automatic Sector Erase command. Upon executing the Automatic Sector Erase command, the device will automatically program and verify the sector(s) memory for an all-zero data pattern. The system does not require to provide any control or timing during these operations.
When the sector(s) is automatically verified to contain an all-zero pattern, a self-timed sector erase and verification begin. The erase and verification operations are com­plete when the data on Q7 is "1" and the data on Q6 stops toggling for two consecutive read cycles, at which time the device returns to the Read mode. The system does not required to provide any control or timing during these operations.
When using the Automatic Sector Erase algorithm, note that the erase automatically terminates when adequate erase margin has been achieved for the memory array (no erase verify command is required). Sector erase is a six­bus cycle operation. There are two "unlock" write cycles. These are followed by writing the set-up command-80H. Two more "unlock" write cycles are then followed by the sector erase command-30H. The sector address is latched on the falling edge of WE, while the command(data) is latched on the rising edge of WE. Sector addresses
selected are loaded into internal register on the sixth falling edge of WE. Each successive sector load cycle started by the falling edge of WE must begin within 30us from the rising edge of the preceding WE. Otherwise, the loading period ends and internal auto sector erase cycle starts. (Monitor Q3 to determine if the sector erase timer window is still open, see section Q3, Sector Erase Timer.) Any command other than Sector Erase (30H) or Erase Suspend (BOH) during the time-out period resets the device to read mode.
ERASE SUSPEND
This command is only valid while the state machine is executing Automatic Sector Erase operation, and therefore will only be responded during Automatic Sector Erase operation. Writing the Erase Suspend command during the Sector Erase time-out immediately terminates the time-out period and suspends the erase operation. After this command has been executed, the command register will initiate erase suspend mode. The state machine will return to read mode automatically after suspend is ready. At this time, state machine only allows the command register to respond to the Read Memory Array, Erase Resume and Program commands. The system can determine the status of the program operation using the Q7 or Q6 status bits, just as in the standard program operation. After an erase-suspendend program operation is complete, the system can once again read array data within non-suspended sectors.
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Note:
1. Q7 and Q2 require a valid address when reading status information. Refer to the appropriate subsection for further details.
2. Q5 switches to '1' when an Auto Program or Auto Erase operation has exceeded the maximum timing limits. See "Q5:Exceeded Timing Limits " for more information.
Status Q7 Q6 Q5 Q3 Q2
Note1 Note2
Byte Program in Auto Program Algorithm Q7 Toggle 0 N/A No Toggle Auto Erase Algorithm 0 Toggle 0 1 Toggle
Erase Suspend Read 1 N o 0 N/A Toggle
In Progress (Erase Suspended Sector) Toggle
Erase Suspended Mode Erase Suspend Read Data Data Data Data Data
(Non-Erase Suspended Sector) Erase Suspend Program Q7 Toggle 0 N/A N/A
Byte Program in Auto Program Algorithm Q7 Toggle 1 N/A No Toggle Exceeded Auto Erase Algorithm 0 Toggle 1 1 Toggle Time Limits Erase Suspend Program Q7 Toggle 1 N/A N/A
Table 4. Write Operation Status
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ERASE RESUME
This command will cause the command register to clear the suspend state and return back to Sector Erase mode but only if an Erase Suspend command was previously issued. Erase Resume will not have any effect in all other conditions.Another Erase Suspend command can be written after the chip has resumed erasing.
SET-UP AUTOMATIC PROGRAM COMMANDS
To initiate Automatic Program mode, a three-cycle command sequence is required. There are two "unlock" write cycles. These are followed by writing the Automatic Program command A0H.
Once the Automatic Program command is initiated, the next WE pulse causes a transition to an active programming operation. Addresses are latched on the falling edge, and data are internally latched on the rising edge of the WE pulse. The rising edge of WE also begins the programming operation. The system does not require to provide further controls or timings. The device will automatically provide an adequate internally generated program pulse and verify margin.
If the program opetation was unsuccessful, the data on Q5 is "1", indicating the program operation exceed internal timing limit. The automatic programming operation is completed when the data read on Q6 stops toggling for two consecutive read cycles and the data on Q7 and Q6 are equivalent to data written to these two bits, at which time the device returns to the Read mode(no program verify command is required).
WRITE OPERATION STATUS
DATA POLLING-Q7
The MX29F002T/B also features Data Polling as a method to indicate to the host system that the Automatic Program or Erase algorithms are either in progress or completed.
While the Automatic Programming algorithm is in operation, an attempt to read the device will produce the complement data of the data last written to Q7. Upon completion of the Automatic Program Algorithm an attempt to read the device will produce the true data last written to Q7. The Data Polling feature is valid after the rising edge of the fourth WE pulse of the four write pulse sequences for automatic program.
While the Automatic Erase algorithm is in operation, Q7 will read "0" until the erase operation is competed. Upon completion of the erase operation, the data on Q7 will read "1". The Data Polling feature is valid after the rising edge of the sixth WE pulse of six write pulse sequences for automatic chip/sector erase.
The Data Polling feature is active during Automatic Program/Erase algorithm or sector erase time-out.(see section Q3 Sector Erase Timer)
Q6:Toggle BIT I
The MX29F002T/B features a "Toggle Bit" as a method to indicate to the host system that the Auto Program/Erase
algorithms are either in progress or completed.
During an Automatic Program or Erase algorithm operation, successive read cycles to any address cause Q6 to toggle. The system may use either OE or CE to control the read cycles. When the operation is complete, Q6 stops toggling.
After an erase command sequence is written, if all sectors selected for erasing are protected, Q6 toggles and returns to reading array data. If not all selected sectors are protected, the Automatic Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected.
The system can use Q6 and Q2 together to determine whether a sector is actively erasing or is erase suspended. When the device is actively erasing (that is, the Automatic Erase algorithm is in progress), Q6 toggling. When the device enters the Erase Suspend mode, Q6 stops toggling. However, the system must also use Q2 to determine which sectors are erasing or erase-suspended. Alternatively, the system can use Q7(see the subsection on Q7:Data Polling).
If a program address falls within a protected sector, Q6 toggles for approximately 2 us after the program command sequence is written, then returns to reading array data.
Q6 also toggles during the erase-suspend-program mode, and stops toggling once the Automatic Program algorithm is complete.
The Write Operation Status table shows the outputs for Toggle Bit I on Q6. Refer to the toggle bit algorithmg.
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Q2:Toggle Bit II
The "Toggle Bit II" on Q2, when used with Q6, indicates whether a particular sector is actively eraseing (that is, the Automatic Erase alorithm is in process), or whether that sector is erase-suspended. Toggle Bit I is valid after the rising edge of the final WE pulse in the command sequence.
Q2 toggles when the system reads at addresses within those sectors that have been selected for erasure. (The system may use either OE or CE to control the read cycles.) But Q2 cannot distinguish whether the sector is actively erasing or is erase-suspended. Q6, by comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus, both status bits are required for sectors and mode information. Refer to Table 4 to compare outputs for Q2 and Q6.
Reading Toggle Bits Q6/ Q2
Refer to the toggle bit algorithm for the following discussion. Whenever the system initially begins reading toggle bit status, it must read Q7-Q0 at least twice in a row to determine whether a toggle bit is toggling. Typically, the system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can read array data on Q7-Q0 on the following read cycle.
However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of Q5 is high (see the section on Q5). If it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as Q5 went high. If the toggle bit is no longer toggling, the device has successfuly completed the program or erase operation. If it is still toggling, the device did not complete the operation successfully, and the system must write the reset command to return to reading array data.
The remaining scenario is that system initially determines that the toggle bit is toggling and Q5 has not gone high. The system may continue to monitor the toggle bit and Q5 through successive read cycles, determining the status as
Q5 Exceeded Timing Limits
Q5 will indicate if the program or erase time has exceeded the specified limits(internal pulse count). Under these conditions Q5 will produce a "1". This time-out condition which indicates that the program or erase cycle was not successfully completed. Data Polling and Toggle Bit are the only operating functions of the device under this condition.
If this time-out condition occurs during sector erase operation, it specifies that a particular sector is bad and it may not be reused. However, other sectors are still functional and may be used for the program or erase operation. The device must be reset to use other sectors. Write the Reset command sequence to the device, and then execute program or erase command sequence. This allows the system to continue to use the other active sectors in the device.
If this time-out condition occurs during the chip erase operation, it specifies that the entire chip is bad or combination of sectors are bad.
If this time-out condition occurs during the byte programming operation, it specifies that the entire sector containing that byte is bad and this sector maynot be reused, (other sectors are still functional and can be reused).
The Q5 time-out condition may also appear if a user tries to program a non blank location without erasing. In this case the device locks out and never completes the Automatic Algorithm operation. Hence, the system never reads a valid data on Q7 bit and Q6 never stops toggling. Once the Device has exceeded timing limits, the Q5 bit will indicate a "1". Please note that this is not a device failure condition since the device was incorrectly used.
described in the previous paragraph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation(top of the toggle bit algorithm flow chart).
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Q3 Sector Erase Timer
After the completion of the initial sector erase command sequence th sector erase time-out will begin. Q3 will remain low until the time-out is complete. Data Polling and Toggle Bit are valid after the initial sector erase command sequence.
If Data Polling or the Toggle Bit indicates the device has been written with a valid erase command, Q3 may be used to determine if the sector erase timer window is still open. If Q3 is high ("1") the internally controlled erase cycle has begun; attempts to write subsequent commands to the device will be ignored until the erase operation is completed as indicated by Data Polling or Toggle Bit. If Q3 is low ("0"), the device will accept additional sector erase commands. To insure the command has been accepted, the system software should check the status of Q3 prior to and following each subsequent sector erase command. If Q3 were high on the second status check, the command may not have been accepted.
DATA PROTECTION
The MX29F002T/B is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transition. During power up the device automatically resets the state machine in the Read mode. In addition, with its control register architecture, alteration of the memory contents only occurs after successful completion of specific command sequences. The device also incorporates several features to prevent inadvertent write cycles resulting from VCC power-up and power-down transition or system noise.
WRITE PULSE "GLITCH" PROTECTION
Noise pulses of less than 5ns(typical) on CE or WE will not initiate a write cycle.
LOGICAL INHIBIT
Writing is inhibited by holding any one of OE = VIL, CE = VIH or WE = VIH. To initiate a write cycle CE and WE must be a logical zero while OE is a logical one.
POWER SUPPLY DECOUPLING
In order to reduce power switching effect, each device should have a 0.1uF ceramic capacitor connected between its VCC and GND.
SECTOR PROTECTION WITH 12V SYSTEM
The MX29F002T/B features hardware sector protection. This feature will disable both program and erase operations for these sectors protected. To activate this mode, the programming equipment must force VID on address pin A9 and control pin OE, (suggest VID = 12V) A6 = VIL and CE = VIL.(see Table 2) Programming of the protection circuitry begins on the falling edge of the WE pulse and is terminated on the rising edge. Please refer to sector protect algorithm and waveform.
To verify programming of the protection circuitry, the programming equipment must force VID on address pin A9 ( with CE and OE at VIL and WE at VIH. When A1=1, it will produce a logical "1" code at device output Q0 for a protected sector. Otherwise the device will produce 00H for the unprotected sector. In this mode, the addresses,except for A1, are in "don't care" state. Address locations with A1 = VIL are reserved to read manufacturer and device codes.(Read Silicon ID)
It is also possible to determine if the sector is protected in the system by writing a Read Silicon ID command. Performing a read operation with A1=VIH, it will produce a logical "1" at Q0 for the protected sector.
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REV. 1.1, JUN. 14, 2001
P/N: PM0547
MX29F002/002N
Temporary Sector Unprotect Operation (For 29F002T/B only)
Start
RESET = VID (Note 1)
Perform Erase or Program Operation
RESET = VIH
Temporary Sector Unprotect Completed(Note 2)
2. All previously protected sectors are protected again.
Note :
Operation Completed
1. All protected sectors are temporary unprotected. VID=11.5V~12.5V
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REV. 1.1, JUN. 14, 2001
P/N: PM0547
MX29F002/002N
TEMPORARY SECTOR UNPROTECT
Parameter Std. Description Test Setup AllSpeed Options Unit tVIDR VID Rise and Fall Time (See Note) Min 50 0 ns tRSP RESET Setup Time for Temporary Sector Unprotect Min 4 us
Note: Not 100% tested
Temporary Sector Unprotect Timing Diagram(For 29F002T/B only)
RESET
CE
WE
tVIDR
tVIDR
Program or Erase Command Sequence
12V
0 or 5V
0 or 5V
tRSP
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REV. 1.1, JUN. 14, 2001
P/N: PM0547
MX29F002/002N
RESET TIMING WAVFORM (For 29F002T/B only)
Note: Not 100% tested
AC CHARACTERISTICS
Parameter Std Description Test Setup All Speed Options Unit tREADY RESET PIN Low (Not During Automatic Algorithms) MAX 50 0 ns
to Read or Write (See Note) tRP1 RESET Pulse Width (During Automatic Algorithms) MIN 10 us tRP2 RESET Pulse Width (NOT During Automatic Algorithms) MIN 500 ns tR H RESET High Time Before Read(See Note) MIN 0 ns
tRH
tRP2
tRP1
tReady
CE, OE
RESET
Reset Timing NOT during Automatic Algorithms
Reset Timing during Automatic Algorithms
RESET
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