MXIC MX27C8000MC-10, MX27C8000MC-12, MX27C8000MC-15, MX27C8000PC-10, MX27C8000PC-12 Datasheet

...

MX27C8000

FEATURES

1M x 8 organization

Single +5V power supply

+12.5V programming voltage

Fast access time: 100/120/150 ns

Totally static operation

Completely TTL compatible

8M-BIT [1M x8] CMOS EPROM

Operating current: 60mA

Standby current: 100uA

Package type:

-32 pin plastic DIP

-32 pin PLCC/SOP

-32 pin TSOP

GENERAL DESCRIPTION

The MX27C8000 is a 5V only, 8M-bit, One Time Programmable Read Only Memory. It is organized as 1M words by 8 bits per word, operates from a single +5 volt supply, has a static standby mode, and features fast single address location programming. All programming signals are TTL levels, requiring a single pulse. For programming outside from the system, existing EPROM

programmers may be used. The MX27C8000 supports a intelligent fast programming algorithm which can result in programming time of less than two minutes.

This EPROM is packaged in industry standard 32 pin dual-in-line packages, 32 lead PLCC, 32 lead TSOP and 32 lead SOP packages.

PIN CONFIGURATIONS

32 PDIP/SOP

A19

1

 

A16

2

 

A15

3

 

A12

4

 

A7

5

MX27C8000

A6

6

 

A5

7

 

A4

8

 

A3

9

 

A2

10

 

A1

11

 

A0

12

 

Q0

13

 

Q1

14

 

Q2

15

 

GND

16

 

32 VCC

31 A18

30 A17

29 A14

28 A13

27 A8

26 A9

25 A11

24 OE/VPP

23 A10

22 CE

21 Q7

20 Q6

19 Q5

18 Q4

17 Q3

 

32 PLCC

 

 

 

 

 

 

32 TSOP

 

 

 

 

 

 

 

A12

A15

A16

A19

VCC

A18

A17

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A11

 

1

 

32

 

OE/VPP

 

 

 

 

 

 

 

4

 

 

1

32

 

30

 

 

A9

 

2

 

31

 

A10

 

 

 

 

 

 

A8

 

3

 

30

 

 

 

 

 

 

 

 

A14

 

 

 

CE

A7

5

 

 

 

 

 

29

A13

 

4

 

29

 

Q7

A6

 

 

 

 

 

 

 

A13

A14

 

5

 

28

 

Q6

A5

 

 

 

 

 

 

 

A8

A17

 

6

 

27

 

Q5

 

 

 

 

 

 

 

A18

 

7

 

26

 

Q4

A4

 

 

 

 

 

 

 

A9

VCC

 

8

MX27C8000

25

 

Q3

A3

9

 

MX27C8000

25

A11

A19

 

9

24

 

GND

 

A16

 

10

 

23

 

Q2

 

 

 

 

 

 

 

 

 

 

 

 

 

A2

 

 

 

 

 

 

 

OE/VPP

 

 

 

 

 

 

 

 

A15

 

11

 

22

 

Q1

A1

 

 

 

 

 

 

 

A10

A12

 

12

 

21

 

Q0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A7

 

13

 

20

 

A0

 

 

 

 

 

 

 

 

 

 

 

 

 

A0

 

 

 

 

 

 

 

CE

 

 

 

 

 

 

 

 

 

 

 

Q0

13

 

 

 

 

 

21

Q7

A6

 

14

 

19

 

A1

 

 

 

 

 

 

 

 

 

 

 

 

 

A5

 

15

 

18

 

A2

 

14

 

 

17

 

 

20

 

 

A4

 

16

 

17

 

A3

 

Q1

Q2

GND

Q3

Q4

Q5

Q6

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BLOCK DIAGRAM

 

 

 

 

 

 

 

 

 

 

PIN DESCRIPTION

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CE

 

 

CONTROL

 

 

OUTPUT

 

 

 

 

Q0~Q7

SYMBOL

PIN NAME

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

LOGIC

 

 

BUFFERS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

OE/VPP

 

 

 

 

 

 

 

 

 

 

A0~A19

Address Input

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Q0~Q7

Data Input/Output

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

.

Y-DECODER

.

 

Y-SELECT

 

 

 

 

 

 

 

CE

 

Chip Enable Input

 

 

 

 

 

 

 

 

 

 

.

 

 

 

.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Output Enable Input/Program Supply Voltage

A0~A19

 

 

 

 

.

 

 

 

.

 

 

 

 

 

 

 

 

 

 

OE/VPP

 

.

 

 

 

.

 

8M BIT

 

 

 

 

 

 

 

 

 

 

ADDRESS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VCC

Power Supply Pin (+5V)

 

 

 

 

 

 

.

 

 

 

.

 

 

 

 

 

 

 

 

 

 

 

 

X-DECODER

 

CELL

 

 

 

 

 

 

INPUTS

 

 

 

 

.

.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MAXTRIX

 

 

 

 

 

 

GND

Ground Pin

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

.

 

 

 

.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

.

 

 

 

.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VCC

GND

P/N: PM00259 REV. 3.5, AUG. 20, 2001

1

MX27C8000

FUNCTIONAL DESCRIPTION

THE PROGRAMMING OF THE MX27C8000

When the MX27C8000 is delivered, or it is erased, the chip has all 8M bits in the "ONE" or HIGH state. "ZEROs" are loaded into the MX27C8000 through the procedure of programming.

For programming, the data to be programmed is applied with 8 bits in parallel to the data pins.

Vcc must be applied simultaneously or before Vpp, and removed simultaneously or after Vpp. When programming an MXIC EPROM, a 0.1uF capacitor is required across Vpp and ground to suppress spurious voltage transients which may damage the device.

FAST PROGRAMMING

The device is set up in the fast programming mode when the programming voltage OE/VPP = 12.75V is applied, with VCC = 6.25 V (Algorithm is shown in Figure 1). The programming is achieved by applying a single TTL low level 50us pulse to the CE input after addresses and data line are stable. If the data is not verified, an additional pulse is applied for a maximum of 25 pulses. This process is repeated while sequencing through each address of the device. When the programming mode is completed, the data in all address is verified at VCC = 5V

±10%.

PROGRAM INHIBIT MODE

Programming of multiple MX27C8000s in parallel with different data is also easily accomplished by using the Program Inhibit Mode. Except for CE and OE, all like inputs of the parallel MX27C8000 may be common. A TTL low-level program pulse applied to an MX27C8000 CE input with OE/VPP = 12.5 ± 0.5 Vwill program that MX27C8000. A high-level CE input inhibits the other MX27C8000s from being programmed.

PROGRAM VERIFY MODE

Verification should be performed on the programmed bits to determine that they were correctly programmed. The verification should be performed with OE /VPPand CE, at VIL, data should be verified tDV after the falling edge of CE.

AUTO IDENTIFY MODE

The auto identify mode allows the reading out of a binary code from an EPROM that will identify its manufacturer and device type. This mode is intended for use by programming equipment for the purpose of automatically matching the device to be programmed with its corresponding programming algorithm. This mode is functional in the 25°C ±5°C ambient temperature range that is required when programming the MX27C8000.

To activate this mode, the programming equipment must force 12.0 ±0.5 V on address line A9 of the device. Two identifier bytes may then be sequenced from the device outputs by toggling address line A0 from VIL to VIH. All other address lines must be held at VIL during auto identify mode.

Byte 0 ( A0 = VIL) represents the manufacturer code, and byte 1 (A0 = VIH), the device identifier code. For the MX27C8000, these two identifier bytes are given in the Mode Select Table. All identifiers for manufacturer and device codes will possess odd parity, with the MSB (Q7) defined as the parity bit.

READ MODE

The MX27C8000 has two control functions, both of which must be logically satisfied in order to obtain data at the outputs. Chip Enable (CE) is the power control and should be used for device selection. Output Enable (OE) is the output control and should be used to gate data to the output pins, independent of device selection. Assuming that addresses are stable, address access time (tACC) is equal to the delay from CE to output (tCE). Data is available at the outputs tOE after the falling edge of OE's, assuming that CE has been LOW and addresses have been stable for at least tACC - tOE.

STANDBY MODE

The MX27C8000 has a CMOS standby mode which reduces the maximum VCC current to 100 uA. It is placed in CMOS standby when CE is at VCC ±0.3 V. The MX27C8000 also has a TTL-standby mode which reduces the maximum VCC current to 1.5 mA. It is placed in TTL-standby when CE is at VIH. When in standby mode, the outputs are in a high-impedance state, independent of the OE input.

P/N: PM00259

REV. 3.5, AUG. 20, 2001

 

2

MX27C8000

TWO-LINE OUTPUT CONTROL FUNCTION

To accommodate multiple memory connections, a twoline control function is provided to allow for:

1.Low memory power dissipation,

2.Assurance that output bus contention will not occur.

It is recommended that CE be decoded and used as the primary device-selecting function, while OE be made a common connection to all devices in the array and connected to the READ line from the system control bus. This assures that all deselected memory devices are in their low-power standby mode and that the output pins are only active when data is desired from a particular memory device.

SYSTEM CONSIDERATIONS

During the switch between active and standby conditions, transient current peaks are produced on the rising and falling edges of Chip Enable. The magnitude of these transient current peaks is dependent on the output capacitance loading of the device. At a minimum, a 0.1 uF ceramic capacitor (high frequency, low inherent inductance) should be used on each device between VCC and GND to minimize transient effects. In addition, to overcome the voltage drop caused by the inductive effects of the printed circuit board traces on EPROM arrays, a 4.7 uF bulk electrolytic capacitor should be used between VCC and GND for each eight devices. The location of the capacitor should be close to where the power supply is connected to the array.

MODE SELECT TABLE

PINS

MODE

CE

OE/VPP

A0

A9

OUTPUTS

 

 

 

 

 

 

Read

VIL

VIL

X

X

DOUT

 

 

 

 

 

 

Output Disable

VIL

VIH

X

X

High Z

 

 

 

 

 

 

Standby (TTL)

VIH

X

X

X

High Z

 

 

 

 

 

 

Standby (CMOS)

VCC±0.3V

X

X

X

High Z

 

 

 

 

 

 

Program

VIL

VPP

X

X

DIN

 

 

 

 

 

 

Program Verify

VIL

VIL

X

X

DOUT

 

 

 

 

 

 

Program Inhibit

VIH

VPP

X

X

High Z

 

 

 

 

 

 

Manufacturer Code(3)

VIL

VIL

VIL

VH

C2H

 

 

 

 

 

 

Device Code(3)

VIL

VIL

VIH

VH

80H

 

 

 

 

 

 

NOTES: 1.

VH

= 12.0 V ± 0.5 V

3.

A1 - A8 = A10 - A19 = VIL(For auto select)

2.

X =

Either VIH or VIL

4.

See DC Programming Characteristics for VPP voltage during

 

 

 

 

programming.

P/N: PM00259

REV. 3.5, AUG. 20, 2001

 

3

MXIC MX27C8000MC-10, MX27C8000MC-12, MX27C8000MC-15, MX27C8000PC-10, MX27C8000PC-12 Datasheet

MX27C8000

FIigure 1. FAST PROGRAMMING FLOW CHART

 

 

START

 

 

 

 

ADDRESS = FIRST LOCATION

 

 

 

 

VCC = 6.25V

 

 

 

 

OE/VPP = 12.75V

 

 

 

 

PROGRAM ONE 50 us PULSE

 

 

 

NO

LAST

 

 

INCREMENT ADDRESS

 

ADDRESS ?

 

 

 

 

 

 

 

 

YES

 

 

 

 

ADDRESS = FIRST LOCATION

 

 

INCREMENT ADDRESS

 

X = 0

 

 

 

 

 

 

NO

 

 

 

 

LAST

PASS

FAIL

 

INCREMENT X

ADDRESS ?

 

VERIFY BYTE

 

 

 

 

 

YES

 

 

 

 

 

 

 

NO

X = 25 ?

 

 

PROGRAM ONE 50us PULSE

 

 

 

 

 

 

 

VCC = 5.25V

 

YES

 

 

 

 

 

 

OE/VPP = VIL

 

 

 

 

COMPARE

FAIL

DEVICE FAILED

 

 

ALL BYTES

 

 

 

TO ORIGINAL

 

 

 

 

DATA

 

 

 

 

PASS

 

 

 

 

DEVICE PASSED

 

 

P/N: PM00259

REV. 3.5, AUG. 20, 2001

 

4

MX27C8000

SWITCHING TEST CIRCUITS

DEVICE

1.8K ohm

UNDER

+5V

 

TEST

 

CL

DIODES = IN3064

OR EQUIVALENT

6.2K ohm

CL = 100 pF including jig capacitance(60pF for 100ns parts)

SWITCHING TEST WAVEFORMS

2.0V

2.0V

AC driving levels

TEST POINTS

0.8V

0.8V

INPUT

OUTPUT

AC TESTING: AC driving levels are 2.4V/0.4V for commercial grade.

Input pulse rise and fall times are < 10ns.

P/N: PM00259

REV. 3.5, AUG. 20, 2001

 

5

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