MXIC MX23L12810RC-12, MX23L12810RC-10, MX23L12810TC-10, MX23L12810TC-12 Datasheet

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FEATURES
PRELIMINARY
MX23L12810
NEW
128M-BIT (16M x 8 / 8M x 16) MASK ROM
FOR TSOP PACKAGE
• Bit organization
- 16M x 8 (byte mode)
- 8M x 16 (word mode)
• Fast access time
- Random access: 100ns (max.)
- Operating:30mA
- Standby:15uA(max.)
PIN CONFIGURATION
48 TSOP (Top View)
A9 A8
A7 A6 A5 A4 A3 A2 A1 A0
CE
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
BYTE
A16 A15 A14 A13 A12 A11 A10
A19 A21 A20 A18 A17
• Supply voltage
• Package
• Temperature
MX23L12810
(Normal T ype)
- 2.7V~3.6V for 120ns
- 3.0V~3.6V for 100ns
- 48 pin TSOP (12mm x 20mm)
- 48 pin TSOP reverse type
- 0 ~ 70°C
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
VSS VSS D15/A-1 D7 D14 D6 D13 D5 D12 D4 VCC VCC A22 D11 D3 D10 D2 D9 D1 D8 D0 OE VSS VSS
48 TSOP (Top View)
D7 D6 D5 D4
D3 D2
D9 D1 D8 D0
OE
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
MX23L12810
(Reverse Type)
VSS VSS
D15/A-1
D14 D13 D12
VCC VCC
A22 D11
D10
VSS VSS
P/N:PM0592 REV. 1.8, OCT. 15, 2001
1
1
BYTE
2
A16
3
A15
4
A14
5
A13
6
A12
7
A11
8
A10
9
A9
10
A8
11
A19
12
A21
13
A20
14
A18
15
A17
16
A7
17
A6
18
A5
19
A4
20
A3
21
A2
22
A1
23
A0
24
CE
PIN DESCRIPTION
MX23L12810
Symbol Pin Function
A0~A22 Address Inputs D0~D14 Data Outputs D15/A-1 D15 (Word Mode)/ LSB Address
(Byte Mode)
CE Chip Enable Input
Symbol Pin Function
OE Output Enable Input Byte Word/ Byte Mode Selection VC C Po wer Supply Pin VSS Ground Pin N C No Connection
ORDER INFORMATION
Part No. Access Time Package VCC
MX23L12810TC-10 100ns 48 pin TSOP 3.0V~3.6V MX23L12810TC-12 120ns 48 pin TSOP 3.0V~3.6V *MX23L12810TC-12 120ns 48 pin TSOP 2.7V~3.6V
(under development) MX23L12810RC-10 100ns 48 pin TSOP (Reverse type) 3.0V~3.6V MX23L12810RC-12 120ns 48 pin TSOP (Reverse type) 3.0V~3.6V *MX23L12810RC-12 120ns 48 pin TSOP (Rev erse type) 2.7V~3.6V
(under development)
MODE SELECTION
CE OE Byte D15/A-1 D0~D7 D8~D15 Mode Po wer
H X X X High Z High Z - Stand-by L H X X High Z High Z - Active L L H Output D0~D7 D8~D15 Word Active L L L Input D0~D7 High Z Byte Active
BLOCK DIAGRAM
D0
D15/(D7)
REV. 1.8, OCT. 15, 2001
P/N:PM0592
A0/(A-1)
A22
CE
BYTE
OE
Address
Buffer
Memory
Array
Sense
Amplifier
2
Word/
Byte
Output
Buffer
MX23L12810
ABSOLUTE MAXIMUM RATINGS
Item Symbol Ratings
V oltage on any Pin Relative to VSS VIN -1.3V to VCC+2.0V (Note) Ambient Operating Temperature T opr 0°C to 70°C Storage T emperature Tstg -65°C to 125°C
Note: Minimum DC voltage on input or I/O pins is -0.5V. During voltage transitions, inputs may undershoot VSS to -1.3V for periods of up to 20ns. Maximum DC v oltage on input or I/O pins is VCC+0.5V. During voltage transitions, inputs ma y ov ershoot VCC to VCC+2.0V for periods of up to 20ns.
DC CHARACTERISTICS (Ta = 0°C ~ 70°C, VCC = 2.7V~3.6V)
Item Symbol MIN. MAX. Conditions
Output High Voltage VOH 2.4V - IOH = -0.4mA Output Low Voltage VOL - 0.4V IOL = 1.6mA Input High Voltage VIH 2.2V VCC+0.3V Input Low Voltage VIL -0.3V 0.2 x VCC Input Leakage Current ILI - 5uA 0V , VCC Output Leakage Current ILO - 5uA 0V, VCC Operating Current ICC - 30mA f=5MHz, all outputs open,
CE=VIL(Chip Enable)
OE=VIH(Output Disabled) Standby Current (TTL) ISTB1 - 1mA CE = VIH Standby Current (CMOS) ISTB2 - 15uA CE>VCC-0.2V Input Capacitance CIN - 10pF Ta = 25°C, f = 1MHZ Output Capacitance COUT - 10pF Ta = 25°C, f = 1MHZ
AC CHARACTERISTICS (Ta = 0°C ~ 70°C, VCC = 2.7V~3.6V)
Item Symbol 23L12810-10 23L12810-12 23L12810-15
MIN. MAX. MIN. MAX. MIN. MAX.
Read Cycle Time t RC 100ns - 120ns - 150ns ­Address Access Time tAA - 100ns - 120ns - 150ns Chip Enable Access Time tACE - 100ns - 120ns - 150ns Output Enable Time tOE - 30ns - 50ns - 70ns Output Hold After Address tOH 0 ns - 0ns - 0 ns ­Output High Z Delay tHZ - 20ns - 20ns - 20ns
Note: Output high-impedance dela y (tHZ) is measured from OE or CE going high, and this parameter guaran­teed by design over the full voltage and temperature operating range - not tested.
P/N:PM0592
3
REV. 1.8, OCT. 15, 2001
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