MXIC MX23L12811TC-12, MX23L12811TC-10, MX23L12811RC-12, MX23L12811RC-10 Datasheet

FEATURES

PRELIMINARY

MX23L12811

NEW

128M-BIT (16M x 8 / 8M x 16) MASK ROM WITH PAGE MODE

(TSOP PACKAGE)

• Bit organization

- 16M x 8 (byte mode)

- 8M x 16 (word mode)

• Fast access time

- Random access: 100ns (max.)

- Page access: 30ns (max.)

• Page size

- 8 words per page

• Current

- Operating:40mA

- Standby:15uA

PIN CONFIGURATION

48 TSOP (Normal Type)

A16 A15 A14 A13 A12 A11 A10

A19 A21 A20 A18 A17

CE

1 2 3 4 5 6 7 8 9

A9

10

A8

11 12 13 14 15 16

A7

17

A6

18

A5

19

A4

20

A3

21

A2

22

A1

23

A0

24

BYTE

MX23L12811

(Normal T ype)

• Supply voltage

- 2.7V~3.6V for 120ns

- 3.0V~3.6V for 100ns

• Package

- 48 pin TSOP (12mm x 20mm)

- 48 pin TSOP reverse type

• Temperature

- 0 ~ 70°C

48

VSS

47

VSS

46

D15/A-1

45

D7

44

D14

43

D6

42

D13

41

D5

40

D12

39

D4

38

VCC

37

VCC

36

A22

35

D11

34

D3

33

D10

32

D2

31

D9

30

D1

29

D8

28

D0

27

OE

26

VSS

25

VSS

48 TSOP (Reverse Type)

48

VSS

47

VSS

D7

D14

D6

D13

D5

D12

D4 VCC VCC

A22 D11

D3

D10

D2

D9

D1

D8

D0

OE VSS VSS

46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25

MX23L12811

(Reverse Type)

D15/A-1

P/N:PM0594 REV. 1.7, OCT. 12, 2001

1

BYTE

2

A16

3

A15

4

A14

5

A13

6

A12

7

A11

8

A10

9

A9

10

A8

11

A19

12

VSS

13

A20

14

A18

15

A17

16

A7

17

A6

18

A5

19

A4

20

A3

21

A2

22

A1

23

A0

24

CE

PIN DESCRIPTION

MX23L12811

Symbol Pin Function

A0~A22 Address Inputs D0~D14 Data Outputs D15/A-1 D15 (Word Mode)/ LSB Address

(Byte Mode)

CE Chip Enable Input

Symbol Pin Function

OE Output Enable Input Byte Word/ Byte Mode Selection VC C Power Supply Pin VSS Ground Pin N C No Connection

ORDER INFORMATION

Part No. Access Time Page Time Package VCC

MX23L12811TC-10 100ns 30ns 48 pin TSOP 3.0V~3.6V MX23L12811TC-12 120ns 30ns 48 pin TSOP 3.0V~3.6V *MX23L12811TC-12 120ns 30ns 48 pin TSOP 2.7V~3.6V

(under development) MX23L12811RC-10 100ns 30ns 48 pin TSOP (Reverse type) 3.0V~3.6V MX23L12811RC-12 120ns 30ns 48 pin TSOP (Reverse type) 3.0V~3.6V *MX23L12811RC-12 120ns 30ns 48 pin TSOP (Reverse type) 2.7V~3.6V

(under development)

MODE SELECTION

CE OE Byte D15/A-1 D0~D7 D8~D15 Mode Power

H X X X High Z High Z - Stand-by L H X X High Z High Z - Active L L H Output D0~D7 D8~D15 Word Active L L L Input D0~D7 High Z Byte Active

BLOCK DIAGRAM

A0/(A-1)

A2

A3

A22

CE

BYTE

OE

Address

Buffer

Memory

Array

Page

Buffer

Page

Decoder

Word/

Byte

Output

Buffer

D0

D15/(D7)

P/N:PM0594

REV. 1.7, OCT. 12, 2001

2

MX23L12811

ABSOLUTE MAXIMUM RATINGS

Item Symbol Ratings

V oltage on an y Pin Relativ e to VSS VIN -1.3V to VCC+2.0V (Note) Ambient Operating T emperature Topr 0°C to 70°C Storage T emperature Tstg -65°C to 125°C

Note: Minim um DC voltage on input or I/O pins is -0.5V. During voltage transitions , inputs may undershoot VSS to -

1.3V for periods of up to 20ns. Maximum DC voltage on input or I/O pins is VCC+0.5V. During v oltage tr ansitions, inputs may ov ershoot VCC to VCC+2.0V f or periods of up to 20ns.

DC CHARACTERISTICS (Ta = 0°C ~ 70°C, VCC =2.7V~3.6V)

Item Symbol MIN. MAX. Conditions

Output High V oltage V OH 2.4V - IOH = -0.4mA Output Low Voltage VO L - 0.4V IOL = 1.6mA Input High V oltage VIH 2.2V VCC+0.3V Input Low V oltage VIL -0.3V 0.2 x VCC Input Leakage Current ILI - 5uA 0V, VCC Output Leakage Current ILO - 5uA 0V , VCC Operating Current ICC - 40mA f=5MHz, all outputs open,

CE=VIL(Chip Enable)

OE=VIH(Output Disabled) Standby Current (TTL) ISTB1 - 1mA CE = VIH Standby Current (CMOS) ISTB2 - 15uA CE>VCC-0.2V Input Capacitance C IN - 10pF Ta = 25°C, f = 1MHZ Output Capacitance COUT - 10pF Ta = 25°C, f = 1MHZ

AC CHARACTERISTICS (Ta = 0°C ~ 70°C, VCC = 2.7V~3.6V)

Item Symbol 23L12811-10 23L12811-12

MIN. MAX. MIN. MAX.

Read Cycle Time tR C 100ns - 120ns Address Access Time tAA - 100ns - 120ns Chip Enable Access Time tACE - 100ns - 120ns Page Mode Access Time tPA - 30ns - 30ns Output Enable Time tOE - 30ns - 30ns Output Hold After Address tO H 0ns - 0 ns Output High Z Delay tHZ - 20ns - 20ns

Note: Output high-impedance delay (tHZ) is measured from OE or CE going high, and this parameter guaranteed by design over the full voltage and temperature operating range - not tested.

P/N:PM0594

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REV. 1.7, OCT. 12, 2001