MXIC MX27C2048PC-10, MX27C2048PC-15, MX27C2048PC-70, MX27C2048PC-90, MX27C2048QC-12 Datasheet

...

MX27C2100/27C2048

2M-BIT [256Kx8/128x16] CMOS EPROM

FEATURES

128K x 16 organization(MX27C2048, JEDEC pin out)

256K x 8 or 128K x 16 organization(MX27C2100, ROM pin out compatible)

+12.5V programming voltage

Fast access time: 55/70/90/120/150 ns

Totally static operation

GENERAL DESCRIPTION

The MX27C2100/2048 is a 5V only, 2M-bit, One Time Programmable Read Only Memory. It is organized as 128K words by 16 bits per word(MX27C2048), 256K x 8 or 128K x 16(MX27C2100), operates from a single + 5 volt supply, has a static standby mode, and features fast single address location programming. All programming signals are TTL levels, requiring a single pulse. For programming outside from the system, existing EPROM

PIN CONFIGURATIONS

PDIP(MX27C2048)

VPP

1

 

40

VCC

 

 

 

 

 

 

PGM

 

CE

2

 

39

Q15

3

 

38

A16

Q14

4

 

37

A15

Q13

5

 

36

A14

Q12

6

 

35

A13

Q11

7

 

34

A12

Q10

8

MX27C2048

33

A11

 

 

Q9

9

32

A10

 

 

 

 

 

Q8

10

 

31

A9

GND

11

 

30

GND

 

 

Q7

12

 

29

A8

 

 

Q6

13

 

28

A7

 

 

Q5

14

 

27

A6

 

 

Q4

15

 

26

A5

 

 

Q3

16

 

25

A4

 

 

Q2

17

 

24

A3

 

 

Q1

18

 

23

A2

 

 

Q0

19

 

22

A1

OE

20

 

21

A0

40-TSOP(I)10x14mm (MX27C2048)

A9

 

1

 

40

 

GND

A10

 

2

 

39

 

A8

A11

 

3

 

38

 

A7

A12

 

4

 

37

 

A6

A13

 

5

 

36

 

A5

A14

 

6

 

35

 

A4

A15

 

7

 

34

 

A3

A16

 

8

 

33

 

A2

PGM

 

9

 

32

 

A1

VCC

 

10

MX27C2048

31

 

A0

VPP

 

11

30

 

OE

CE

 

12

 

29

 

Q0

 

 

 

Q15

 

13

 

28

 

Q1

 

 

 

Q14

 

14

 

27

 

Q2

 

 

 

Q13

 

15

 

26

 

Q3

 

 

 

Q12

 

16

 

25

 

Q4

 

 

 

Q11

 

17

 

24

 

Q5

Q10

 

18

 

23

 

Q6

 

 

 

Q9

 

19

 

22

 

Q7

 

 

 

Q8

 

20

 

21

 

GND

 

 

 

P/N: PM0158

Completely TTL compatible

Operating current: 40mA

Standby current: 100uA

Package type:

-40 pin plastic DIP

-44 pin PLCC(MX27C2048)

-40 pin TSOP(I)(MX27C2048)

programmers may be used. The MX27C2100/2048 supports a intelligent fast programming algorithm which can result in programming times of less than one minute.

This EPROM is packaged in industry standard 40 pin dual-in-line packages, 44 lead PLCC, and 40 lead TSOP(I) packages.

PLCC(MX27C2048)

 

 

 

 

 

 

 

 

 

 

 

 

Q13

Q14

Q15

 

CE

 

VPP

NC

VCC

PGM

A16

A15

A14

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Q12

6

 

 

 

 

 

 

 

 

1

44

 

 

 

40

 

A13

 

 

 

 

 

 

 

 

 

 

 

7

 

 

 

 

 

 

 

 

 

 

 

 

 

39

 

 

 

 

 

 

 

 

 

 

 

 

Q11

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A12

 

 

 

 

 

 

 

 

 

 

 

Q10

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A11

 

 

 

 

 

 

 

 

 

 

 

Q9

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A10

 

 

 

 

 

 

 

 

 

 

 

Q8

 

 

 

 

MX27C2048

 

 

 

 

A9

 

 

 

 

 

 

 

 

 

 

 

GND

12

 

 

 

 

 

34

 

GND

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

NC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

NC

 

 

 

 

 

 

 

 

 

 

 

Q7

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A8

 

 

 

 

 

 

 

 

 

 

 

Q6

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A7

 

 

 

 

 

 

 

 

 

 

 

Q5

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A6

 

 

 

 

 

 

 

 

 

 

 

Q4

17

 

 

 

 

 

 

 

 

23

 

 

 

 

29

 

A5

 

 

 

 

 

 

 

 

 

 

 

 

18

 

 

 

 

 

 

 

 

 

 

 

 

28

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Q3

Q2

Q1

 

Q0

 

OE

NC

A0 A1

A2

A3

A4

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BLOCK DIAGRAM (MX27C2048)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CE

 

 

 

CONTROL

 

 

 

 

 

 

 

 

 

OUTPUT

 

 

 

 

 

Q0~Q15

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PGM

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

LOGIC

 

 

 

 

 

 

 

 

 

BUFFERS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

OE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

.

Y-DECODER

 

.

 

 

 

 

Y-SELECT

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

.

 

 

 

 

.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A0~A16

 

 

 

 

.

 

 

 

 

.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

.

 

 

 

 

.

 

 

 

 

 

2M BIT

 

 

 

 

 

 

 

ADDRESS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

.

 

 

 

 

.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

X-DECODER

 

 

 

 

 

 

 

CELL

 

 

 

 

 

 

 

INPUTS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

.

 

 

.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MAXTRIX

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

.

 

 

 

 

.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

.

 

 

 

 

.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VCC VPP

VSS

REV. 4.3, AUG. 22, 2000

1

MX27C2100/27C2048

PIN CONFIGURATIONS

PDIP(MX27C2100)

NC

1

 

A7

2

 

A6

3

 

A5

4

 

A4

5

 

A3

6

 

A2

7

 

A1

8

MX27C2100

A0

9

 

CE

10

 

GND

11

 

 

 

 

 

OE

12

 

Q0

13

 

Q8

14

 

Q1

15

 

Q9

16

 

Q2

17

 

Q10

18

 

Q3

19

 

Q11

20

 

40 A8

39 A9

38 A10

37 A11

36 A12

35 A13

34 A14

33 A15

32 A16

31 BYTE/VPP

30 GND

29 Q15/A-1

28 Q7

27 Q14

26 Q6

25 Q13

24 Q5

23 Q12

22 Q4

21 VCC

BLOCK DIAGRAM (MX27C2100)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CE

 

 

 

CONTROL

 

 

 

OUTPUT

 

 

 

 

Q0~Q14

 

 

 

OE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

LOGIC

 

 

 

BUFFERS

 

 

 

 

Q15/A-1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BYTE/VPP

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

.

Y-DECODER

.

 

Y-SELECT

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

.

 

 

 

.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A0~A16

 

 

 

 

.

 

 

 

.

 

 

 

 

 

 

 

 

 

 

.

 

 

 

.

 

2M BIT

 

 

 

 

 

 

ADDRESS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

.

 

 

 

.

 

 

 

 

 

 

 

 

 

 

 

 

X-DECODER

 

CELL

 

 

 

 

 

 

INPUTS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

.

.

 

 

 

 

 

 

 

 

 

 

 

MAXTRIX

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

.

 

 

 

.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

.

 

 

 

.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VCC

GND

PIN DESCRIPTION(MX27C2100)

 

SYMBOL

PIN NAME

 

 

 

 

 

 

 

 

A0~A16

Address Input

 

 

 

 

 

 

 

 

Q0~Q14

Data Input/Output

 

 

 

 

 

 

 

 

 

 

 

 

 

Chip Enable Input

CE

 

 

 

 

 

 

 

 

 

 

Output Enable Input

 

 

OE

 

 

 

 

 

 

 

 

 

 

 

 

Word/Byte Selection

 

BYTE/VPP

 

 

 

 

 

 

/Program Supply Voltage

 

 

 

 

 

 

 

 

Q15/A-1

Q15(Word mode)/LSB addr. (Byte mode)

 

 

 

 

 

 

 

 

VCC

Power Supply Pin (+5V)

 

 

 

 

 

 

 

 

GND

Ground Pin

 

 

 

 

 

 

 

PIN DESCRIPTION(MX27C2048)

SYMBOL

PIN NAME

 

 

 

 

 

 

 

A0~A16

Address Input

 

 

 

 

 

 

 

Q0~Q15

Data Input/Output

 

 

 

 

 

 

 

 

 

 

 

Chip Enable Input

 

CE

 

 

 

 

 

 

 

 

 

 

 

 

Output Enable Input

 

OE

 

 

 

 

 

 

 

 

 

 

 

 

 

PGM

Program Enable Input

 

 

 

 

 

 

 

VPP

Program Supply Voltage

 

 

 

 

 

 

 

VCC

Power Supply Pin (+5V)

 

 

 

 

 

 

 

GND

Ground Pin

 

 

 

 

 

 

 

TRUTH TABLE OF BYTE FUNCTION(MX27C2100)

BYTE MODE(BYTE = GND)

CE

OE

Q15/A-1

MODE

Q0-Q7

SUPPLY CURRENT

 

 

 

 

 

 

H

X

X

Non selected

High Z

Standby(ICC2)

 

 

 

 

 

 

L

H

X

Non selected

High Z

Operating(ICC1)

 

 

 

 

 

 

L

L

A-1 input

Selected

DOUT

Operating(ICC1)

 

 

 

 

 

 

WORD MODE(BYTE = VCC)

CE

OE

Q15/A-1

MODE

Q0-Q14

SUPPLY CURRENT

 

 

 

 

 

 

H

X

High Z

Non selected

High Z

Standby(ICC2)

 

 

 

 

 

 

L

H

High Z

Non selected

High Z

Operating(ICC1)

 

 

 

 

 

 

L

L

DOUT

Selected

DOUT

Operating(ICC1)

 

 

 

 

 

 

NOTE : X = H or L

 

 

 

 

 

 

 

 

 

 

 

P/N: PM0158

 

 

 

 

REV. 4.3, AUG. 22, 2001

 

 

 

2

 

 

MX27C2100/27C2048

FUNCTIONAL DESCRIPTION

THE PROGRAMMING OF THE MX27C2100/2048

When the MX27C2100/2048 is delivered, or it is erased, the chip has all 2M bits in the "ONE", or HIGH state. "ZEROs" are loaded into the MX27C2100/2048 through the procedure of programming.

For programming, the data to be programmed is applied with 16 bits in parallel to the data pins.

VCC must be applied simultaneously or before VPP, and removed simultaneously or after VPP. When programming an MXIC EPROM, a 0.1uF capacitor is required across VPP and ground to suppress spurious voltage transients which may damage the device.

FAST PROGRAMMING

The device is set up in the fast programming mode when the programming voltage VPP = 12.75V is applied, with VCC = 6.25 V and PGM = VIL(or OE = VIH) (Algorithm is shown in Figure 1). The programming is achieved by applying a single TTL low level 100us pulse to the PGM input after addresses and data line are stable. If the data is not verified, an additional pulse is applied for a maximum of 25 pulses. This process is repeated while sequencing through each address of the device. When the programming mode is completed, the data in all address is verified at VCC = VPP = 5V ± 10%.

PROGRAM INHIBIT MODE

Programming of multiple MX27C2100/2048's in parallel with different data is also easily accomplished by using the Program Inhibit Mode. Except for CE and OE, all like inputs of the parallel MX27C2100/2048 may be common. A TTL low-level program pulse applied to an MX27C2100/2048 CE input with VPP = 12.5 ±0.5 V will program the MX27C2100/2048. A high-level CE input inhibits the other MX27C2100/2048s from being programmed.

PROGRAM VERIFY MODE

Verification should be performed on the programmed bits to determine that they were correctly programmed. The verification should be performed with OE and CE at

VIL(for MX27C2048), OE at VIL, CE at VIH(for MX27C2100) and VPP at its programming voltage.

AUTO IDENTIFY MODE

The auto identify mode allows the reading out of a binary code from an EPROM that will identify its manufacturer and device type. This mode is intended for use by programming equipment for the purpose of automatically matching the device to be programmed with its corresponding programming algorithm. This mode is functional in the 25°C ± 5°C ambient temperature range that is required when programming the MX27C2100/2048.

To activate this mode, the programming equipment must force 12.0 ±0.5 V on address line A9 of the device. Two identifier bytes may then be sequenced from the device outputs by toggling address line A0 from VIL to VIH. All other address lines must be held at VIL during auto identify mode.

Byte 0 ( A0 = VIL) represents the manufacturer code, and byte 1 (A0 = VIH), the device identifier code. For the MX27C2100/2048, these two identifier bytes are given in the Mode Select Table. All identifiers for manufacturer and device codes will possess odd parity, with the MSB (Q15) defined as the parity bit.

READ MODE

The MX27C2100/2048 has two control functions, both of which must be logically satisfied in order to obtain data at the outputs. Chip Enable (CE) is the power control and should be used for device selection. Output Enable (OE) is the output control and should be used to gate data to the output pins, independent of device selection. Assuming that addresses are stable, address access time (tACC) is equal to the delay from CE to output (tCE). Data is available at the outputs tOE after the falling edge of OE's, assuming that CE has been LOW and addresses have been stable for at least tACC - t OE.

WORD-WIDE MODE

With BYTE/VPP at VCC ± 0.2V outputs Q0-7 present data Q0-7 and outputs Q8-15 present data Q8-15, after CE and OE are appropriately enabled.

P/N: PM0158

REV. 4.3, AUG. 22, 2001

3

MX27C2100/27C2048

BYTE-WIDE MODE

With BYTE/VPP at GND ± 0.2V, outputs Q8-15 are tristated. If Q15/A-1 = VIH, outputs Q0-7 present data bits Q8-15. If Q15/A-1 = VIL, outputs Q0-7 present data bits Q0-7.

STANDBY MODE

The MX27C2100/2048 has a CMOS standby mode which reduces the maximum VCC current to 100 uA. It is placed in CMOS standby when CE is at VCC ± 0.3 V. The MX27C2100/2048 also has a TTL-standby mode which reduces the maximum VCC current to 1.5 mA. It is placed in TTL-standby when CE is at VIH. When in standby mode, the outputs are in a high-impedance state, independent of the OE input.

TWO-LINE OUTPUT CONTROL FUNCTION

To accommodate multiple memory connections, a twoline control function is provided to allow for:

1.Low memory power dissipation,

2.Assurance that output bus contention will not occur.

It is recommended that CE be decoded and used as the primary device-selecting function, while OE be made a common connection to all devices in the array and connected to the READ line from the system control bus. This assures that all deselected memory devices are in their low-power standby mode and that the output pins are only active when data is desired from a particular memory device.

SYSTEM CONSIDERATIONS

During the switch between active and standby conditions, transient current peaks are produced on the rising and falling edges of Chip Enable. The magnitude of these transient current peaks is dependent on the output capacitance loading of the device. At a minimum, a 0.1 uF ceramic capacitor (high frequency, low inherent inductance) should be used on each device between Vcc and GND to minimize transient effects. In addition, to overcome the voltage drop caused by the inductive effects of the printed circuit board traces on EPROM arrays, a 4.7 uF bulk electrolytic capacitor should be used between VCC and GND for each eight devices.

The location of the capacitor should be close to where the power supply is connected to the array.

P/N: PM0158

REV. 4.3, AUG. 22, 2001

4

MX27C2100/27C2048

MODE SELECT TABLE (MX27C2048)

PINS

MODE

 

 

CE

OE

PGM

A0

A9

VPP

OUTPUTS

 

 

 

 

 

 

 

 

 

 

Read

 

 

VIL

VIL

VIH

X

X

VCC

DOUT

 

 

 

 

 

 

 

 

Output Disable

VIL

VIH

VIH

X

X

VCC

High Z

 

 

 

 

 

 

 

 

Standby (TTL)

VIH

X

X

X

X

VCC

High Z

 

 

 

 

 

 

 

 

Standby (CMOS)

VCC±0.3V

X

X

X

X

VCC

High Z

 

 

 

 

 

 

 

 

 

 

Program

 

 

VIL

VIH

VIL

X

X

VPP

DIN

 

 

 

 

 

 

 

 

Program Verify

VIL

VIL

VIH

X

X

VPP

DOUT

 

 

 

 

 

 

 

 

Program Inhibit

VIH

X

X

X

X

VPP

High Z

 

 

 

 

 

 

 

 

Manufacturer Code(3)

VIL

VIL

X

VIL

VH

VCC

00C2H

 

 

 

 

 

 

 

 

Device Code(3)

VIL

VIL

X

VIH

VH

VCC

0122H

 

 

 

 

 

 

 

 

 

NOTES: 1.

VH

= 12.0 V ± 0.5 V

 

3.

A1 - A8

= A10 - A16

= VIL(For auto select)

 

2.

X =

Either VIH or VIL

 

4. See DC Programming Characteristics for VPP voltage during

 

 

 

 

 

 

programming.

 

 

MODE SELECT TABLE (MX27C2100)

 

 

 

 

 

 

 

 

BYTE/

 

 

 

 

 

 

 

 

 

 

 

 

 

MODE

 

 

 

A9

A0

Q15/A-1

VPP(5)

Q8-14

Q0-7

CE

 

OE

 

 

 

 

 

 

 

 

 

 

 

 

Read (Word)

VIL

VIL

X

X

Q15 Out

VCC

Q8-14 Out

Q0-7 Out

 

 

 

 

 

 

 

 

 

 

 

Read (Upper Byte)

VIL

VIL

X

X

VIH

GND

High Z

Q8-15 Out

 

 

 

 

 

 

 

 

 

 

 

Read (Lower Byte)

VIL

VIL

X

X

VIL

GND

High Z

Q0-7 Out

 

 

 

 

 

 

 

 

 

 

 

Output Disable

VIL

VIH

X

X

High Z

X

High Z

High Z

 

 

 

 

 

 

 

 

 

 

 

Standby

VIH

X

X

X

High Z

X

High Z

High Z

 

 

 

 

 

 

 

 

 

 

 

Program

VIL

VIH

X

X

Q15 In

VPP

Q8-14 In

Q0-7 In

 

 

 

 

 

 

 

 

 

 

 

Program Verify

VIH

VIL

X

X

Q15 Out

VPP

Q8-14 Out

Q0-7 Out

 

 

 

 

 

 

 

 

 

 

 

Program Inhibit

VIH

VIH

X

X

High Z

VPP

High Z

High Z

 

 

 

 

 

 

 

 

 

 

 

Manufacturer Code(3)

VIL

VIL

VH

VIL

0B

VCC

00H

C2H

 

 

 

 

 

 

 

 

 

 

 

Device Code(3)

VIL

VIL

VH

VIH

0B

VCC

01H

8AH

 

 

 

 

 

 

 

 

 

 

 

NOTES: 1. VH = 12.0V ± 0.5V

2.X = Either VIH or VIL.

3.A1 - A8, A10 - A16 = VIL(For auto select)

4.See DC Programming Characteristics for VPP voltages.

5.BYTE/VPP is intended for operation under DC Voltage conditions only.

P/N: PM0158

REV. 4.3, AUG. 22, 2001

5

MXIC MX27C2048PC-10, MX27C2048PC-15, MX27C2048PC-70, MX27C2048PC-90, MX27C2048QC-12 Datasheet

MX27C2100/27C2048

FIGURE 1. FAST PROGRAMMING FLOW CHART

 

 

START

 

 

 

ADDRESS = FIRST LOCATION

 

 

 

VCC = 6.25V

 

 

 

VPP = 12.75V

 

 

 

X = 0

 

 

 

PROGRAM ONE 50us PULSE

 

INTERACTIVE

 

INCREMENT X

 

SECTION

 

 

 

 

 

X = 25?

YES

 

 

 

 

 

NO

 

 

 

FAIL

 

 

 

VERIFY BYTE

 

 

 

?

 

 

 

PASS

 

 

 

NO

 

 

INCREMENT ADDRESS

LAST ADDRESS

 

 

 

 

 

 

 

FAIL

 

 

YES

 

 

 

VCC = VPP = 5.25V

 

VERIFY SECTION

 

 

FAIL

 

 

VERIFY ALL BYTES

 

 

DEVICE FAILED

 

 

?

 

 

 

PASS

 

 

 

DEVICE PASSED

 

P/N: PM0158

REV. 4.3, AUG. 22, 2001

6

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