Mitsubishi microcomputers
M16C / 62A Group
Description |
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER |
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Description
The M16C/62A group of single-chip microcomputers are built using the high-performance silicon gate CMOS process using a M16C/60 Series CPU core and are packaged in a 100-pin plastic molded QFP. These single-chip microcomputers operate using sophisticated instructions featuring a high level of instruction efficiency. With 1M bytes of address space, they are capable of executing instructions at high speed. They also feature a built-in multiplier and DMAC, making them ideal for controlling office, communications, industrial equipment, and other high-speed processing applications.
The M16C/62A group includes a wide range of products with different internal memory types and sizes and various package types.
• Memory capacity.................................. |
ROM (See Figure 1.1.4. ROM Expansion) |
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RAM 3K to 20K bytes |
• Shortest instruction execution time ...... |
62.5ns (f(XIN)=16MHZ, VCC=5V) |
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100ns (f(XIN)=10MHZ, VCC=3V, with software one-wait) : Mask ROM, flash memory 5V version |
• Supply voltage ..................................... |
4.2V to 5.5V (f(XIN)=16MHZ, without software wait) : Mask ROM, flash memory 5V version |
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2.7V to 5.5V (f(XIN)=10MHZ with software one-wait) : Mask ROM, flash memory 5V version |
• Low power consumption ...................... |
25.5mW ( f(XIN)=10MHZ, with software one-wait, VCC = 3V) |
• Interrupts.............................................. |
25 internal and 8 external interrupt sources, 4 software |
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interrupt sources; 7 levels (including key input interrupt) |
• Multifunction 16-bit timer ...................... |
5 output timers + 6 input timers |
• Serial I/O .............................................. |
5 channels (3 for UART or clock synchronous, 2 for clock synchro- |
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nous) |
• DMAC .................................................. |
2 channels (trigger: 24 sources) |
• A-D converter....................................... |
10 bits X 8 channels (Expandable up to 10 channels) |
• D-A converter....................................... |
8 bits X 2 channels |
• CRC calculation circuit ......................... |
1 circuit |
• Watchdog timer .................................... |
1 line |
• Programmable I/O ............................... |
87 lines |
• Input port |
_______ |
1 line (P85 shared with NMI pin) |
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• Memory expansion .............................. |
Available (to a maximum of 1M bytes) |
• Chip select output ................................ |
4 lines |
• Clock generating circuit ....................... |
2 built-in clock generation circuits |
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(built-in feedback resistor, and external ceramic or quartz oscillator) |
Applications |
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Audio, cameras, office equipment, communications equipment, portable equipment
------Table of Contents------
Central Processing Unit (CPU) ..................... |
11 |
Reset ............................................................. |
14 |
Processor Mode ............................................ |
21 |
Clock Generating Circuit ............................... |
34 |
Protection ...................................................... |
43 |
Interrupts ....................................................... |
44 |
Watchdog Timer ............................................ |
64 |
DMAC ........................................................... |
66 |
Timer ............................................................. |
76 |
Serial I/O ..................................................... |
106 |
A-D Converter ............................................. |
147 |
D-A Converter ............................................. |
157 |
CRC Calculation Circuit .............................. |
159 |
Programmable I/O Ports ............................. |
161 |
Electrical characteristic ............................... |
176 |
Flash memory version ................................. |
227 |
1
Mitsubishi microcomputers
M16C / 62A Group
Description |
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER |
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Figures 1.1.1 and 1.1.2 show the pin configurations (top view).
PIN CONFIGURATION (top view)
/D8 P10
/D9 P11
/D10 P12
/D11 P13
/D12 P14
/INT313 /DP15
/INT414 /DP16
/INT515 P1/D7
)-/
(/D0 /A0 P20
)/D0
(/D1 /A1 P21
)/D1
(/D2 /A2 P22
)/D2
(/D3 /A3 P23
/D)3
(/D4 /A4 P24
)/D4
(/D5 /A5 P25
)/D5
(/D6 /A6 P26
)/D6
(/D7 /A7 P27
Vss
/D)7 -(/ /A8 P30
Vcc
/A9 P31
/A10 P32
/A11 P33
/A12 P34
/A13 P35
/A14 P36
/A15 P37
/A16 P40
/A17 P41
/A18 P42
/A19 P43
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
P07/D7 81
P06/D6 82
P05/D5 83
P04/D4 84
P03/D3 85
P02/D2 86
P01/D1 87
P00/D0 88 P107/AN7/KI3 89 P106/AN6/KI2 90 P105/AN5/KI1 91 P104/AN4/KI0 92
P103/AN3 93
P102/AN2 94
P101/AN1 95 AVSS 96 P100/AN0 97
VREF 98
AVcc 99 P97/ADTRG/SIN4 100
M16C/62A Group
50 |
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P44/CS0 |
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49 |
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P45/CS1 |
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48 |
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P46/CS2 |
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47 |
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P47/CS3 |
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46 |
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P50/WRL/WR |
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45 |
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P51/WRH/BHE |
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P52/RD |
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P53/BCLK |
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42 |
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P54/HLDA |
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41 |
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P55/HOLD |
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40 |
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P56/ALE |
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P57/RDY/CLKOUT |
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38 |
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P60/CTS0/RTS0 |
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37 |
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P61/CLK0 |
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36 |
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P62/RxD0 |
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35 |
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P63/TXD0 |
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34 |
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P64/CTS1/RTS1/CLKS1 |
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33 |
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P65/CLK1 |
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32 |
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P66/RxD1 |
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31 |
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P67/TXD1 |
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1 2 3
P9/ANEX1/S46OUT |
P9/ANEX0/CLK45 |
P9/DA/TB441IN |
4 5
P9/DA/TB330IN |
P9/TB2/S32INOUT |
6 7
P9/TB1/S31ININ |
P9/TB0/CLK30IN |
8 9
BYTE |
CNVss |
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
P8/X7CIN |
P8/X6COUT |
RESET XOUT |
VSS |
XIN |
VCC |
P8/NMI5 |
P8/INT42 |
P8/INT31 |
P8/INT20 |
P8/TA4/U1IN |
P8/TA4/U0OUT |
P7/TA37IN |
P7/TA36OUT |
P7/TA2/W5IN |
P7/TA2/W4OUT |
P7/CTS/RTS/TA1/V322IN |
P7/CLK/TA1/V22OUT |
/RxD/SCL/TA0/TB512ININ |
P7/TD/SDA/TA00X2OUT |
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P7 |
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Package: 100P6S-A
Figure 1.1.1. Pin configuration (top view)
2
Mitsubishi microcomputers
M16C / 62A Group
Description |
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER |
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PIN CONFIGURATION (top view)
P12/D10 76
P11/D9 77
P10/D8 78
P07/D7 79
P06/D6 80
P05/D5 81
P04/D4 82
P03/D3 83
P02/D2 84
P01/D1 85
P00/D0 86 P107/AN7/KI3 87 P106/AN6/KI2 88 P105/AN5/KI1 89 P104/AN4/KI0 90
P103/AN3 91
P102/AN2 92
P101/AN1 93 AVSS 94 P100/AN0 95
VREF 96
AVcc 97 P97/ADTRG/SIN4 98 P96/ANEX1/SOUT4 99 P95/ANEX0/CLK4 100
P1/D311 |
P1/D412 |
P1/D/INT5133 |
P1/D/INT6144 |
P1/D/INT7155 |
P2/A(/D/-)000 |
P2/A(/D/D)1110 |
P2/A(/D/D)2221 |
P2/A(/D/D)3332 |
P2/A(/D/D)4443 |
P2/A(/D/D)5554 |
P2/A(/D/D)6665 |
P2/A(/D/D)7776 |
Vss P3/A(/-/D)087 |
Vcc P3/A19 |
P3/A210 |
P3/A311 |
P3/A412 |
P3/A513 |
P3/A614 |
P3/A715 |
P4/A016 |
P4/A117 |
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
M16C/62A Group
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
P9/DA/TB441IN |
P9/DA/TB330IN |
P9/TB2/S32INOUT |
P9/TB1/S31ININ |
P9/TB0/CLK30IN |
BYTE CNVss P8/X7CIN |
P8/X6COUT |
RESET XOUT |
VSS |
XIN |
VCC |
P8/NMI5 |
P8/INT42 |
P8/INT31 |
P8/INT20 |
P8/TA4/U1IN |
P8/TA4/U0OUT |
P7/TA37IN |
P7/TA36OUT |
P7/TA2/W5IN |
P7/TA2/W4OUT |
/CTS/RTS/TA1/V22IN |
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P73 |
50 P42/A18
49 P43/A19
48 P44/CS0
47 P45/CS1
46 P46/CS2
45 P47/CS3
44 P50/WRL/WR
43 P51/WRH/BHE
42 P52/RD
41 P53/BCLK
40 P54/HLDA
39 P55/HOLD
38 P56/ALE
37 P57/RDY/CLKOUT
36 P60/CTS0/RTS0 35 P61/CLK0
34 P62/RxD0
33 P63/TXD0
32 P64/CTS1/RTS1/CLKS1 31 P65/CLK1
30 P66/RxD1
29 P67/TXD1
28 P70/TXD2/SDA/TA0OUT
27 P71/RxD2/SCL/TA0IN/TB5IN
26 P72/CLK2/TA1OUT/V
Package: 100P6Q-A
Figure 1.1.2. Pin configuration (top view)
3
Mitsubishi microcomputers
M16C / 62A Group
Description |
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER |
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Figure 1.1.3 is a block diagram of the M16C/62A group.
Block diagram of the M16C/62A group
I/O ports
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8 |
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Port P0 |
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Port P1 |
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Port P2 |
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Port P3 |
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Port P4 |
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Port P5 |
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Port P6 |
Internal peripheral functions
Timer
Timer TA0 (16 bits)
Timer TA1 (16 bits)
Timer TA2 (16 bits)
Timer TA3 (16 bits)
Timer TA4 (16 bits)
Timer TB0 (16 bits)
Timer TB1 (16 bits)
Timer TB2 (16 bits)
Timer TB3 (16 bits)
Timer TB4 (16 bits)
Timer TB5 (16 bits)
Watchdog timer
(15 bits)
DMAC
(2 channels)
D-A converter
(8 bits X 2 channels)
A-D converter
(10 bits X 8 channels
Expandable up to 10 channels)
UART/clock synchronous SI/O
(8 bits X 3 channels)
CRC arithmetic circuit (CCITT ) (Polynomial : X16+X12+X5+1)
System clock generator
XIN-XOUT
XCIN-XCOUT
Clock synchronous SI/O
(8 bits X 2 channels)
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M16C/60 series16-bit CPU core |
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Memory |
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Registers |
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Program counter |
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ROM |
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(Note 1) |
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R0H |
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R0L |
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PC |
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R0H |
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R0L |
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RAM |
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R1H |
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R1L |
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R1HR2 |
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R1L |
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Stack pointer |
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(Note 2) |
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R2 |
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ISP |
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R3 |
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R3 |
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USP |
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A0 |
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A0 |
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A1 |
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Vector table |
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A1 |
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FB |
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FB |
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INTB |
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Multiplier |
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Flag register |
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SB |
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FLG |
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Note 1: ROM size depends on MCU type. Note 2: RAM size depends on MCU type.
P7Port |
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P8Port |
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5P8Port |
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P9Port |
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P10Port |
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8 |
Figure 1.1.3. Block diagram of M16C/62A group
4
Mitsubishi microcomputers
M16C / 62A Group
Description |
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER |
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Table 1.1.1 is a performance outline of M16C/62A group.
Table 1.1.1. Performance outline of M16C/62A group
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Item |
Performance |
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Number of basic instructions |
91 instructions |
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Shortest instruction execution time |
62.5ns(f(XIN)=16MHZ, VCC=5V) |
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100ns (f(XIN)=10MHZ, VCC=3V, with software one-wait) |
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: Mask ROM, flash memory 5V version |
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Memory |
ROM |
(See the figure 1.1.4. ROM Expansion) |
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capacity |
RAM |
3K to 20K bytes |
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I/O port |
P0 to P10 (except P85) |
8 bits x 10, 7 bits x 1 |
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Input port |
P85 |
1 bit x 1 |
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Multifunction |
TA0, TA1, TA2, TA3, TA4 |
16 bits x 5 |
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timer |
TB0, TB1, TB2, TB3, TB4, TB5 |
16 bits x 6 |
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Serial I/O |
UART0, UART1, UART2 |
(UART or clock synchronous) x 3 |
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SI/O3, SI/O4 |
(Clock synchronous) x 2 |
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A-D converter |
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10 bits x (8 + 2) channels |
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D-A converter |
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8 bits x 2 |
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DMAC |
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2 channels (trigger: 24 sources) |
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CRC calculation circuit |
CRC-CCITT |
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Watchdog timer |
15 bits x 1 (with prescaler) |
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Interrupt |
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25 internal and 8 external sources, 4 software sources, 7 levels |
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Clock generating circuit |
2 built-in clock generation circuits |
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(built-in feedback resistor, and external ceramic or quartz oscillator) |
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Supply voltage |
4.2V to 5.5V (f(XIN)=16MHZ, without software wait) |
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: Mask ROM, flash memory 5V version |
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2.7V to 5.5V (f(XIN)=10MHZ with software one-wait) |
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: Mask ROM, flash memory 5V version |
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Power consumption |
25.5mW (f(XIN) = 10MHZ, VCC=3V with software one-wait) |
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I/O |
I/O withstand voltage |
5V |
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characteristics |
Output current |
5mA |
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Memory expansion |
Available (to a maximum of 1M bytes) |
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Device configuration |
CMOS high performance silicon gate |
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Package |
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100-pin plastic mold QFP |
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5
Mitsubishi microcomputers
M16C / 62A Group
Description |
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER |
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Mitsubishi plans to release the following products in the M16C/62A group:
(1)Support for mask ROM version, external ROM version, and flash memory version
(2)ROM capacity
(3)Package
100P6S-A : Plastic molded QFP (mask ROM, one-time PROM, and flash memory versions) 100P6Q-A : Plastic molded QFP(mask ROM, one-time PROM, and flash memory versions)
ROM Size |
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(Byte) |
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External |
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M30620SAFP/GP |
ROM |
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M30622SAFP/GP |
256K |
M30624MGA-XXXFP/GP |
M30624FGAFP/GP |
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128K |
M30620MCA-XXXFP/GP |
M30620FCAFP/GP |
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M30622MCA-XXXFP/GP |
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96K |
M30620MAA-XXXFP/GP |
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M30622MAA-XXXFP/GP |
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64K |
M30620M8A-XXXFP/GP |
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M30622M8A-XXXFP/GP |
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32K |
M30622M4A-XXXFP/GP |
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Mask ROM version |
Flash memory version |
External ROM version |
Figure 1.1.4. ROM expansion
The M16C/62A group products currently supported are listed in Table 1.1.2.
Table 1.1.2. M16C/62A group |
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December. 1999 |
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Type No |
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ROM capacity |
RAM capacity |
Package type |
Remarks |
M30622M4A-XXXFP |
** |
32K byte |
3K byte |
100P6S-A |
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M30622M4A-XXXGP |
** |
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100P6Q-A |
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M30620M8A-XXXFP |
** |
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10K byte |
100P6S-A |
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M30620M8A-XXXGP |
** |
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100P6Q-A |
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64K byte |
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M30622M8A-XXXFP |
** |
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100P6S-A |
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4K byte |
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M30622M8A-XXXGP |
** |
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100P6Q-A |
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M30620MAA-XXXFP |
** |
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10K byte |
100P6S-A |
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M30620MAA-XXXGP |
** |
96K byte |
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100P6Q-A |
Mask ROM version |
M30622MAA-XXXFP |
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100P6S-A |
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** |
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5K byte |
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M30622MAA-XXXGP |
** |
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100P6Q-A |
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M30620MCA-XXXFP |
** |
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10K byte |
100P6S-A |
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M30620MCA-XXXGP |
** |
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100P6Q-A |
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128K byte |
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M30622MCA-XXXFP |
** |
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100P6S-A |
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5K byte |
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M30622MCA-XXXGP |
** |
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100P6Q-A |
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M30624MGA-XXXFP |
** |
256K byte |
20K byte |
100P6S-A |
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M30624MGA-XXXGP |
** |
100P6Q-A |
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M30620FCAFP |
** |
128K byte |
10K byte |
100P6S-A |
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M30620FCAGP |
** |
100P6Q-A |
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Flash memory |
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M30624FGAFP |
** |
256K byte |
20K byte |
100P6S-A |
5V version |
M30624FGAGP |
** |
100P6Q-A |
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M30620SAFP |
** |
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10K byte |
100P6S-A |
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M30620SAGP |
** |
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100P6Q-A |
External ROM |
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M30622SAFP |
** |
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3K byte |
100P6S-A |
version |
M30622SAGP |
** |
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100P6QA-A |
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**: Under development
6
Mitsubishi microcomputers
M16C / 62A Group
Description |
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER |
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Type No. M 3 0 6 2 2 M 8 A– X X X F P
Package type: |
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FP |
: Package |
100P6S-A |
GP |
: |
100P6Q-A |
ROM No.
Omitted for flash memory version
ROM capacity: 4 : 32K bytes 8 : 64K bytes A : 96K bytes C : 128K bytes G: 256K bytes
Memory type:
M : Mask ROM version
S : External ROM version
F : Flash memory version
Shows RAM capacity, pin count, etc (The value itself has no specific meaning)
M16C/62 Group
M16C Family
Figure 1.1.5. Type No., memory size, and package
7
Mitsubishi microcomputers
M16C / 62A Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Pin Description
Pin Description
Pin name |
Signal name |
I/O type |
VCC, VSS |
Power supply |
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input |
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CNVSS |
CNVSS |
Input |
RESET |
Reset input |
Input |
XIN |
Clock input |
Input |
XOUT |
Clock output |
Output |
BYTE |
External data |
Input |
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bus width |
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select input |
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AVCC |
Analog power |
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supply input |
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AVSS |
Analog power |
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supply input |
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VREF |
Reference |
Input |
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voltage input |
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P00 to P07 |
I/O port P0 |
Input/output |
D0 to D7 |
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Input/output |
P10 to P17 |
I/O port P1 |
Input/output |
D8 to D15 |
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Input/output |
P20 to P27 |
I/O port P2 |
Input/output |
A0 to A7 |
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Output |
A0/D0 to |
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Input/output |
A7/D7 |
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A0, A1/D0 |
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Output |
to A7/D6 |
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Input/output |
P30 to P37 |
I/O port P3 |
Input/output |
A8 to A15 |
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Output |
A8/D7, |
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Input/output |
A9 to A15 |
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Output |
P40 to P47 |
I/O port P4 |
Input/output |
CS0 to CS3, |
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Output |
A16 to A19 |
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Output |
Function
Supply 2.7 to 5.5 V to the VCC pin. Supply 0 V to the VSS pin.
This pin switches between processor modes. Connect this pin to the VSS pin when after a reset you want to start operation in single-chip mode (memory expansion mode) or the VCC pin when starting operation in microprocessor mode.
A “L” on this input resets the microcomputer.
These pins are provided for the main clock generating circuit.Connect a ceramic resonator or crystal between the XIN and the XOUT pins. To use an externally derived clock, input it to the XIN pin and leave the XOUT pin open.
This pin selects the width of an external data bus. A 16-bit width is selected when this input is “L”; an 8-bit width is selected when this input is “H”. This input must be fixed to either “H” or “L”. Connect this pin to the VSS pin when not using external data bus.
This pin is a power supply input for the A-D converter. Connect this pin to VCC.
This pin is a power supply input for the A-D converter. Connect this pin to VSS.
This pin is a reference voltage input for the A-D converter.
This is an 8-bit CMOS I/O port. It has an input/output port direction register that allows the user to set each pin for input or output individually. When used for input in single-chip mode, the port can be set to have or not have a pull-up resistor in units of four bits by software. In memory expansion and microprocessor modes, selection of the internal pull-resistor is not available.
When set as a separate bus, these pins input and output data (D0–D7).
This is an 8-bit I/O port equivalent to P0. Pins in this port also function as external interrupt pins as selected by software.
When set as a separate bus, these pins input and output data (D8–D15).
This is an 8-bit I/O port equivalent to P0.
These pins output 8 low-order address bits (A0–A7).
If the external bus is set as an 8-bit wide multiplexed bus, these pins input and output data (D0–D7) and output 8 low-order address bits (A0–A7) separated in time by multiplexing.
If the external bus is set as a 16-bit wide multiplexed bus, these pins input and output data (D0–D6) and output address (A1–A7) separated in time by multiplexing. They also output address (A0).
This is an 8-bit I/O port equivalent to P0.
These pins output 8 middle-order address bits (A8–A15).
If the external bus is set as a 16-bit wide multiplexed bus, these pins input and output data (D7) and output address (A8) separated in time by multiplexing. They also output address (A9–A15).
This is an 8-bit I/O port equivalent to P0.
These pins output CS0–CS3 signals and A16–A19. CS0–CS3 are chip select signals used to specify an access space. A16–A19 are 4 highorder address bits.
8
Mitsubishi microcomputers
M16C / 62A Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Pin Description
Pin Description
Pin name |
Signal name |
I/O type |
|
P50 to P57 |
I/O port P5 |
Input/output |
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WRL / WR, |
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Output |
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WRH / BHE, |
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Output |
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RD, |
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Output |
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BCLK, |
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Output |
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HLDA, |
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Output |
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HOLD, |
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Input |
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ALE, |
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Output |
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RDY |
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Input |
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P60 to P67 |
I/O port P6 |
Input/output |
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P70 to P77 |
I/O port P7 |
Input/output |
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P80 to P84, |
I/O port P8 |
Input/output |
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P86, |
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Input/output |
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P87, |
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Input/output |
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P85 |
I/O port P85 |
Input |
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P90 to P97 |
I/O port P9 |
Input/output |
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P100 to P107 |
I/O port P10 |
Input/output |
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Function
This is an 8-bit I/O port equivalent to P0. In single-chip mode, P57 in this port outputs a divide-by-8 or divide-by-32 clock of XIN or a clock of the same frequency as XCIN as selected by software.
Output WRL, WRH (WR and BHE), RD, BCLK, HLDA, and ALE signals. WRL and WRH, and BHE and WR can be switched using software control.
WRL, WRH, and RD selected
With a 16-bit external data bus, data is written to even addresses when the WRL signal is “L” and to the odd addresses when the WRH signal is “L”. Data is read when RD is “L”.
WR, BHE, and RD selected
Data is written when WR is “L”. Data is read when RD is “L”. Odd addresses are accessed when BHE is “L”. Use this mode when using an 8-bit external data bus.
While the input level at the HOLD pin is “L”, the microcomputer is placed in the hold state. While in the hold state, HLDA outputs a “L” level. ALE is used to latch the address. While the input level of the RDY pin is “L”, the microcomputer is in the ready state.
This is an 8-bit I/O port equivalent to P0. When used for input in singlechip, memory expansion, and microprocessor modes, the port can be set to have or not have a pull-up resistor in units of four bits by software. Pins in this port also function as UART0 and UART1 I/O pins as selected by software.
This is an 8-bit I/O port equivalent to P6 (P70 and P71 are N channel open-drain output). Pins in this port also function as timer A0–A3, timer B5 or UART2 I/O pins as selected by software.
P80 to P84, P86, and P87 are I/O ports with the same functions as P6. Using software, they can be made to function as the I/O pins for timer A4 and the input pins for external interrupts. P86 and P87 can be set using software to function as the I/O pins for a sub clock generation circuit. In this case, connect a quartz oscillator between P86 (XCOUT pin) and P87 (XCIN pin). P85 is an input-only port that also functions for NMI. The NMI interrupt is generated when the input at this pin changes from “H” to “L”. The NMI function cannot be cancelled using software. The pull-up cannot be set for this pin.
This is an 8-bit I/O port equivalent to P6. Pins in this port also function as SI/O3, 4 I/O pins, Timer B0–B4 input pins, D-A converter output pins, A-D converter extended input pins, or A-D trigger input pins as selected by software.
This is an 8-bit I/O port equivalent to P6. Pins in this port also function as A-D converter input pins. Furthermore, P104–P107 also function as input pins for the key input interrupt function.
9
Mitsubishi microcomputers
M16C / 62A Group
Memory |
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER |
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The M16C/62A group accommodates certain units in a single chip. These units include ROM and RAM to store instructions and data and the central processing unit (CPU) to execute arithmetic/logic operations. Also included are peripheral units such as timers, serial I/O, D-A converter, DMAC, CRC calculation circuit, A-D converter, and I/O ports.
The following explains each unit.
Memory
Figure 1.3.1 is a memory map of the M16C/62A group. The address space extends the 1M bytes from address 0000016 to FFFFF16. From FFFFF16 down is ROM. For example, in the M30622MCA-XXXFP,
there is 128K bytes of internal ROM from E000016 to FFFFF16. The vector table for fixed interrupts such as
_______
the reset and NMI are mapped to FFFDC16 to FFFFF16. The starting address of the interrupt routine is stored here. The address of the vector table for timer interrupts, etc., can be set as desired using the internal register (INTB). See the section on interrupts for details.
From 0040016 up is RAM. For example, in the M30622MCA-XXXFP, 5K bytes of internal RAM is mapped to the space from 0040016 to 017FF16. In addition to storing data, the RAM also stores the stack used when calling subroutines and when interrupts are generated.
The SFR area is mapped to 0000016 to 003FF16. This area accommodates the control registers for peripheral devices such as I/O ports, A-D converter, serial I/O, and timers, etc. Figures 1.6.1 to 1.6.3 are location of peripheral unit control registers. Any part of the SFR area that is not occupied is reserved and cannot be used for other purposes.
The special page vector table is mapped to FFE0016 to FFFDB16. If the starting addresses of subroutines or the destination addresses of jumps are stored here, subroutine call instructions and jump instructions can be used as 2-byte instructions, reducing the number of program steps.
In memory expansion mode and microprocessor mode, a part of the spaces are reserved and cannot be used. For example, in the M30622MCA-XXXFP, the following spaces cannot be used.
•The space between 0180016 and 03FFF16 (Memory expansion and microprocessor modes)
•The space between D000016 and D7FFF16 (Memory expansion mode)
Type No. |
Address XXXXX16 |
Address YYYYY16 |
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M30622M4A |
00FFF16 |
F800016 |
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M30620M8A |
02BFF16 |
F000016 |
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M30620MAA |
02BFF16 |
E800016 |
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M30620MCA/FCA |
02BFF16 |
E000016 |
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M30622M8A |
013FF16 |
F000016 |
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M30622MAA |
017FF16 |
E800016 |
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M30622MCA |
017FF16 |
E000016 |
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M30624MGA/FGA |
053FF16 |
C000016 |
0000016
SFR area
For details, see Figures
1.6.1 to 1.6.3
FFE0016
0040016
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Internal RAM area |
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Special page |
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XXXXX16 |
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vector table |
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Internal reserved |
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area (Note 1) |
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0400016 |
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FFFDC16 |
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Undefined instruction |
External area |
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Overflow |
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BRK instruction |
D000016 |
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Address match |
Internal reserved |
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Single step |
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area (Note 2) |
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YYYYY16 |
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Watchdog timer |
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Internal ROM area |
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DBC |
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NMI |
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FFFFF16 |
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FFFFF16 |
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Reset |
Note 1: During memory expansion and microprocessor modes, can not be used. Note 2: In memory expansion mode, can not be used.
Note 3: These memory maps show an instance in which PM13 is set to 0; but in the case of M30624MGA/FGA, they show an instance in which PM13 is set to 1.
Figure 1.3.1. Memory map
10
Mitsubishi microcomputers
M16C / 62A Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CPU
The CPU has a total of 13 registers shown in Figure 1.4.1. Seven of these registers (R0, R1, R2, R3, A0, A1, and FB) come in two sets; therefore, these have two register banks.
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b15 |
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b8 b7 |
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b0 |
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R0(Note) |
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H |
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L |
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b15 |
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b8 b7 |
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b0 |
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R1(Note) |
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H |
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L |
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b15 |
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b0 |
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R2(Note) |
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b15 |
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b0 |
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R3(Note) |
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b15 |
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b0 |
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A0(Note) |
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b15 |
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b0 |
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A1(Note) |
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b15 |
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b0 |
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FB(Note) |
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b19 |
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b0 |
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PC |
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Program counter |
Data |
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registers |
b19 |
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b0 |
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INTB |
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H |
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L |
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Interrupt table |
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register |
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b15 |
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b0 |
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USP |
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User stack pointer |
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b15 |
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b0 |
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ISP |
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Interrupt stack |
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Address |
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pointer |
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registers |
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b15 |
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b0 |
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SB |
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Static base |
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register |
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b15 |
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b0 |
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Frame base |
FLG |
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Flag register |
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registers |
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IPL |
U |
I |
O |
B |
S |
Z |
D |
C |
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Note: These registers consist of two register banks.
Figure 1.4.1. Central processing unit register
(1) Data registers (R0, R0H, R0L, R1, R1H, R1L, R2, and R3)
Data registers (R0, R1, R2, and R3) are configured with 16 bits, and are used primarily for transfer and arithmetic/logic operations.
Registers R0 and R1 each can be used as separate 8-bit data registers, high-order bits as (R0H/R1H), and low-order bits as (R0L/R1L). In some instructions, registers R2 and R0, as well as R3 and R1 can use as 32-bit data registers (R2R0/R3R1).
(2) Address registers (A0 and A1)
Address registers (A0 and A1) are configured with 16 bits, and have functions equivalent to those of data registers. These registers can also be used for address register indirect addressing and address register relative addressing.
In some instructions, registers A1 and A0 can be combined for use as a 32-bit address register (A1A0).
11
Mitsubishi microcomputers
M16C / 62A Group
CPU |
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER |
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(3) Frame base register (FB)
Frame base register (FB) is configured with 16 bits, and is used for FB relative addressing.
(4) Program counter (PC)
Program counter (PC) is configured with 20 bits, indicating the address of an instruction to be executed.
(5) Interrupt table register (INTB)
Interrupt table register (INTB) is configured with 20 bits, indicating the start address of an interrupt vector table.
(6) Stack pointer (USP/ISP)
Stack pointer comes in two types: user stack pointer (USP) and interrupt stack pointer (ISP), each configured with 16 bits.
Your desired type of stack pointer (USP or ISP) can be selected by a stack pointer select flag (U flag). This flag is located at the position of bit 7 in the flag register (FLG).
(7) Static base register (SB)
Static base register (SB) is configured with 16 bits, and is used for SB relative addressing.
(8) Flag register (FLG)
Flag register (FLG) is configured with 11 bits, each bit is used as a flag. Figure 1.4.2 shows the flag register (FLG). The following explains the function of each flag:
• Bit 0: Carry flag (C flag)
This flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit.
• Bit 1: Debug flag (D flag)
This flag enables a single-step interrupt.
When this flag is “1”, a single-step interrupt is generated after instruction execution. This flag is cleared to “0” when the interrupt is acknowledged.
• Bit 2: Zero flag (Z flag)
This flag is set to “1” when an arithmetic operation resulted in 0; otherwise, cleared to “0”.
• Bit 3: Sign flag (S flag)
This flag is set to “1” when an arithmetic operation resulted in a negative value; otherwise, cleared to “0”.
• Bit 4: Register bank select flag (B flag)
This flag chooses a register bank. Register bank 0 is selected when this flag is “0” ; register bank 1 is selected when this flag is “1”.
• Bit 5: Overflow flag (O flag)
This flag is set to “1” when an arithmetic operation resulted in overflow; otherwise, cleared to “0”.
•Bit 6: Interrupt enable flag (I flag)
This flag enables a maskable interrupt.
An interrupt is disabled when this flag is “0”, and is enabled when this flag is “1”. This flag is cleared to “0” when the interrupt is acknowledged.
12
Mitsubishi microcomputers
M16C / 62A Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CPU
• Bit 7: Stack pointer select flag (U flag)
Interrupt stack pointer (ISP) is selected when this flag is “0” ; user stack pointer (USP) is selected when this flag is “1”.
This flag is cleared to “0” when a hardware interrupt is acknowledged or an INT instruction of software interrupt Nos. 0 to 31 is executed.
•Bits 8 to 11: Reserved area
•Bits 12 to 14: Processor interrupt priority level (IPL)
Processor interrupt priority level (IPL) is configured with three bits, for specification of up to eight processor interrupt priority levels from level 0 to level 7.
If a requested interrupt has priority greater than the processor interrupt priority level (IPL), the interrupt is enabled.
• Bit 15: Reserved area
The C, Z, S, and O flags are changed when instructions are executed. See the software manual for details.
b15 |
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b0 |
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IPL |
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U |
I |
O |
B |
S |
Z |
D |
C |
Flag register (FLG) |
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Carry flag |
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Debug flag |
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Zero flag |
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Sign flag |
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Register bank select flag |
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Overflow flag |
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Interrupt enable flag |
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Stack pointer select flag |
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Reserved area |
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Processor interrupt priority level |
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Reserved area |
Figure 1.4.2. Flag register (FLG)
13
Mitsubishi microcomputers
M16C / 62A Group
Reset |
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER |
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Reset
There are two kinds of resets; hardware and software. In both cases, operation is the same after the reset. (See “Software Reset” for details of software resets.) This section explains on hardware resets.
When the supply voltage is in the range where operation is guaranteed, a reset is effected by holding the reset pin level “L” (0.2VCC max.) for at least 20 cycles. When the reset pin level is then returned to the “H” level while main clock is stable, the reset status is cancelled and program execution resumes from the address in the reset vector table.
Figure 1.5.1 shows the example reset circuit. Figure 1.5.2 shows the reset sequence.
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5V |
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4.0V |
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VCC |
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0V |
RESET |
VCC |
5V |
RESET
0.8V
0V
Example when VCC = 5V.
Figure 1.5.1. Example reset circuit
XIN |
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More than 20 cycles are needed |
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Microprocessor |
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mode BYTE = “H” |
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RESET |
BCLK |
24cycles |
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BCLK |
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Content of reset vector |
Address |
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FFFFC16 |
FFFFD16 |
FFFFE16 |
RD |
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WR |
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CS0 |
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Microprocessor |
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Content of reset vector |
mode BYTE = “L” |
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Address |
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FFFFC16 |
FFFFE16 |
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RD |
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WR |
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CS0 |
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Single chip |
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FFFFC16 |
Content of reset vector |
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Address |
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FFFFE16 |
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Figure 1.5.2. Reset sequence
14
Mitsubishi microcomputers
M16C / 62A Group
Reset |
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER |
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Table 1.5.1 shows the statuses of the other pins while the RESET pin level is “L”. Figures 1.5.3 and 1.5.4 show the internal status of the microcomputer immediately after the reset is cancelled.
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Table 1.5.1. Pin status when RESET pin level is “L”
Status |
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Pin name |
CNVSS = VCC |
CNVSS = VSS |
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BYTE = VSS |
BYTE = VCC |
P0 |
Input port (floating) |
Data input (floating) |
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P1 |
Input port (floating) |
Data input (floating) |
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P2, P3, P40 to P43 |
Input port (floating) |
Address output (undefined) |
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P44 |
Input port (floating) |
CS0 output (“H” level is output) |
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P45 to P47 |
Input port (floating) |
Input port (floating) |
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(pull-up resistor is on) |
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P50 |
Input port (floating) |
WR output (“H” level is output) |
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P51 |
Input port (floating) |
BHE output (undefined) |
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P52 |
Input port (floating) |
RD output (“H” level is output) |
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P53 |
Input port (floating) |
BCLK output |
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P54 |
Input port (floating) |
HLDA output (The output value |
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depends on the input to the |
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HOLD pin) |
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P55 |
Input port (floating) |
HOLD input (floating) |
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P56 |
Input port (floating) |
ALE output (“L” level is output) |
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P57 |
Input port (floating) |
RDY input (floating) |
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P6, P7, P80 to P84, |
Input port (floating) |
Input port (floating) |
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P86, P87, P9, P10 |
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Data input (floating)
Input port (floating)
Address output (undefined)
CS0 output (“H” level is output)
Input port (floating) (pull-up resistor is on)
WR output (“H” level is output)
BHE output (undefined)
RD output (“H” level is output)
BCLK output
HLDA output (The output value depends on the input to the HOLD pin)
HOLD input (floating)
ALE output (“L” level is output)
RDY input (floating)
Input port (floating)
15
Mitsubishi microcomputers
M16C / 62A Group
Reset |
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER |
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(1) |
Processor mode register 0 (Note 1) |
(000416)··· |
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0016 |
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(29) UART1 receive interrupt control register |
(005416)··· |
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0 |
0 |
0 |
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(30)Timer A0 interrupt control register |
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(2) |
Processor mode register 1 |
(000516)··· |
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0 |
0 |
0 |
0 |
0 |
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0 |
(005516)··· |
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0 |
0 |
0 |
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(31) Timer A1 interrupt control register |
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(3) |
System clock control register 0 |
(000616)··· |
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1 |
0 |
0 |
1 |
0 |
0 |
0 |
(005616)··· |
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? |
0 |
0 |
0 |
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(32)Timer A2 interrupt control register |
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(4) |
System clock control register 1 |
(000716)··· |
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0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
(005716)··· |
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? |
0 |
0 |
0 |
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(5) |
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(000816)··· |
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(33) Timer A3 interrupt control register |
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Chip select control register |
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0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
(005816)··· |
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0 |
0 |
0 |
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(34)Timer A4 interrupt control register |
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(6) |
Address match interrupt enable register |
(000916)··· |
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0 |
0 |
(005916)··· |
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? |
0 |
0 |
0 |
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(7) |
Protect register |
(000A16)··· |
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(35)Timer B0 interrupt control register |
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0 |
0 |
0 |
(005A16)··· |
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? |
0 |
0 |
0 |
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(8) |
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(36) Timer B1 interrupt control register |
(005B16)··· |
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Watchdog timer control register |
(000F16)··· |
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0 |
0 |
0 |
? |
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? |
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0 |
0 |
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(9) |
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(37)Timer B2 interrupt control register |
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Address match interrupt register 0 |
(001016)··· |
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0016 |
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(005C16)··· |
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0 |
0 |
0 |
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(38) INT0 interrupt control register |
(005D16)··· |
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(001116)··· |
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0016 |
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0 |
0 |
? |
0 |
0 |
0 |
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(39) INT1 interrupt control register |
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(001216)··· |
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0 |
0 |
0 |
0 |
(005E16)··· |
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0 |
0 |
? |
0 |
0 |
0 |
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(10)Address match interrupt register 1 |
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(40) INT2 interrupt control register |
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(001416)··· |
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0016 |
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(005F16)··· |
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0 |
0 |
? |
0 |
0 |
0 |
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(41)Timer B3,4,5 count start flag |
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(001516)··· |
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0016 |
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(034016)··· |
0 |
0 |
0 |
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(42)Three-phase PWM control register 0 |
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(001616)··· |
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0 |
0 |
0 |
0 |
(034816)··· |
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0016 |
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(43)Three-phase PWM control register 1 |
(034916)··· |
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(11)DMA0 control register |
(002C16)··· |
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0 |
0 |
0 |
0 |
0 |
? |
0 |
0 |
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0016 |
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(44) Three-phase output buffer register 0 |
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(12)DMA1 control register |
(003C16)··· |
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0 |
0 |
0 |
0 |
0 |
? |
0 |
0 |
(034A16)··· |
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0016 |
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(45) Three-phase output buffer register 1 |
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(13) INT3 interrupt control register |
(004416)··· |
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0 |
0 |
? |
0 |
0 |
0 |
(034B16)··· |
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0016 |
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(14)Timer B5 interrupt control register |
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(46)Timer B3 mode register |
(035B16)··· |
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(004516)··· |
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? |
0 |
0 |
0 |
0 |
0 |
? |
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0 |
0 |
0 |
0 |
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(15)Timer B4 interrupt control register |
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(47) Timer B4 mode register |
(035C16)··· |
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(004616)··· |
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? |
0 |
0 |
0 |
0 |
0 |
? |
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0 |
0 |
0 |
0 |
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(16)Timer B3 interrupt control register |
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(48) Timer B5 mode register |
(035D16)··· |
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(004716)··· |
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0 |
0 |
0 |
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0 |
? |
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0 |
0 |
0 |
0 |
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(17)SI/O4 interrupt control register |
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(49)Interrupt cause select register |
(035F16)··· |
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(004816)··· |
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0 |
0 |
? |
0 |
0 |
0 |
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0016 |
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(18)SI/O3 interrupt control register |
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(50) SI/O3 control register |
(036216)··· |
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(004916)··· |
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0 |
0 |
? |
0 |
0 |
0 |
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4016 |
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(19)Bus collision detection interrupt |
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(51) SI/O4 control register |
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(004A16)··· |
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0 |
0 |
0 |
(036616)··· |
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4016 |
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control register |
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(52) UART2 special mode register 3 (Note 2) |
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(20) DMA0 interrupt control register |
(004B16)··· |
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? |
0 |
0 |
0 |
(037516)··· |
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? |
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(21) DMA1 interrupt control register |
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(53) UART2 special mode register 2 |
(037616)··· |
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(004C16)··· |
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? |
0 |
0 |
0 |
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0016 |
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(22) Key input interrupt control register |
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(004D16)··· |
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? |
0 |
0 |
0 |
(54)UART2 special mode register |
(037716)··· |
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0016 |
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(23)A-D conversion interrupt control register |
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(004E16)··· |
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? |
0 |
0 |
0 |
(55) UART2 transmit/receive mode register |
(037816)··· |
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0016 |
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(24)UART2 transmit interrupt control register |
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(004F16)··· |
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? |
0 |
0 |
0 |
(56)UART2 transmit/receive control register 0 |
(037C16)··· |
0 |
0 |
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0 |
0 |
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1 |
0 |
0 |
0 |
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(25) UART2 receive interrupt control register |
(005016)··· |
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? |
0 |
0 |
0 |
(57)UART2 transmit/receive control register 1 |
(037D16)··· |
0 |
0 |
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0 |
0 |
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0 |
0 |
1 |
0 |
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(26)UART0 transmit interrupt control register |
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(005116)··· |
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? |
0 |
0 |
0 |
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(27)UART0 receive interrupt control register |
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(005216)··· |
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? |
0 |
0 |
0 |
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(28)UART1 transmit interrupt control register |
(005316)··· |
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? |
0 |
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0 |
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x : Nothing is mapped to this bit ? : Undefined
The content of other registers and RAM is undefined when the microcomputer is reset. The initial values must therefore be set.
Note 1: When the VCC level is applied to the CNVSS pin, it is 0316 at a reset.
Note 2: “0016” is read out when set bit 7 (SDDS) of the UART2 special mode register ( address 037716) to “1”.
Figure 1.5.3. Device's internal status after a reset is cleared
16
Mitsubishi microcomputers
M16C / 62A Group
Reset |
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER |
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(58)Count start flag |
(038016)··· |
0016 |
(84) A-D control register 1 |
(03D716)··· |
0016 |
(59)Clock prescaler reset flag
(60)One-shot start flag
(038116)··· |
0 |
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(038216)··· |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
(85) |
D-A control register |
(03DC16)··· |
0016 |
(86) |
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Port P0 direction register |
(03E216)··· |
0016 |
(61)Trigger select flag |
(038316)··· |
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0016 |
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(87) |
Port P1 direction register |
(03E316)··· |
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0016 |
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(62)Up-down flag |
(038416)··· |
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0016 |
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(88) |
Port P2 direction register |
(03E616)··· |
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0016 |
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(039616)··· |
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(63)Timer A0 mode register |
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0016 |
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(89) |
Port P3 direction register |
(03E716)··· |
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0016 |
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(64)Timer A1 mode register |
(039716)··· |
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0016 |
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(90) |
Port P4 direction register |
(03EA16)··· |
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0016 |
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(039816)··· |
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(65)Timer A2 mode register |
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0016 |
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(91) |
Port P5 direction register |
(03EB16)··· |
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0016 |
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(66)Timer A3 mode register |
(039916)··· |
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0016 |
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(92) |
Port P6 direction register |
(03EE16)··· |
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0016 |
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(67)Timer A4 mode register |
(039A16)··· |
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0016 |
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(93) |
Port P7 direction register |
(03EF16)··· |
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0016 |
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(039B16)··· |
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(68)Timer B0 mode register |
0 |
0 |
? |
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0 |
0 |
0 |
0 |
(94) |
Port P8 direction register |
(03F216)··· |
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0 |
0 |
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0 |
0 |
0 |
0 |
0 |
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(69)Timer B1 mode register |
(039C16)··· |
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0 |
0 |
? |
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0 |
0 |
0 |
0 |
(95) |
Port P9 direction register |
(03F316)··· |
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0016 |
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(039D16)··· |
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(70)Timer B2 mode register |
0 |
0 |
? |
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0 |
0 |
0 |
0 |
(96) |
Port P10 direction register |
(03F616)··· |
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0016 |
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(71)UART0 transmit/receive mode register |
(03A016)··· |
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0016 |
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(97) |
Pull-up control register 0 |
(03FC16)··· |
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0016 |
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(03A416)··· |
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(72)UART0 transmit/receive control register 0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
(98) |
Pull-up control register 1(Note1) |
(03FD16)··· |
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0016 |
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(03A516)··· |
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(73)UART0 transmit/receive control register 1 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
(99) |
Pull-up control register 2 |
(03FE16)··· |
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0016 |
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(03A816)··· |
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(74)UART1 transmit/receive mode register |
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0016 |
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(100) |
Port control register |
(03FF16)··· |
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0016 |
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(03AC16)··· |
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(75)UART1 transmit/receive control register 0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
(101) |
Data registers (R0/R1/R2/R3) |
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000016 |
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(03AD16)··· |
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(76)UART1 transmit/receive control register 1 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
(102) |
Address registers (A0/A1) |
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000016 |
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(77)UART transmit/receive control register 2 |
(03B016)··· |
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0 |
0 |
0 |
0 |
0 |
0 |
0 |
(103) |
Frame base register (FB) |
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000016 |
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(78)Flash memory control register 1 (Note2) |
(03B616)··· |
? |
? |
? |
? |
0 |
? |
? |
? |
(104) |
Interrupt table register (INTB) |
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0000016 |
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User stack pointer (USP) |
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(79)Flash memory control register 0 (Note2) |
(03B716)··· |
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0 |
0 |
0 |
0 |
0 |
1 |
(105) |
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000016 |
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(80)DMA0 cause select register |
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Interrupt stack pointer (ISP) |
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(03B816)··· |
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0016 |
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(106) |
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000016 |
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(81)DMA1 cause select register |
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Static base register (SB) |
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(03BA16)··· |
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0016 |
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(107) |
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000016 |
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Flag register (FLG) |
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(82) A-D control register 2 |
(03D416)··· |
0 |
0 |
0 |
0 |
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0 |
(108) |
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000016 |
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(83) A-D control register 0 |
(03D616)··· |
0 |
0 |
0 |
0 |
0 |
? |
? |
? |
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x : Nothing is mapped to this bit |
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? : Undefined |
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The content of other registers and RAM is undefined when the microcomputer is reset. The initial values must therefore be set.
Note1: When the VCC level is applied to the CNVSS pin, it is 0216 at a reset.
Note2: This register is only exist in flash memory version.
Figure 1.5.4. Device's internal status after a reset is cleared
17
Mitsubishi microcomputers
M16C / 62A Group
SFR |
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER |
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000016
000116
000216
000316
000416
000516
000616
000716
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
001016
001116
001216
001316
001416
001516
001616
001716
001816
001916
001A16
001B16
001C16
001D16
001E16
001F16
002016
002116
002216
002316
002416
002516
002616
002716
002816
002916
002A16
002B16
002C16
002D16
002E16
002F16
003016
003116
003216
003316
003416
003516
003616
003716
003816
003916
003A16
003B16
003C16
003D16
003E16
003F16
Processor mode register 0 (PM0) Processor mode register 1(PM1) System clock control register 0 (CM0) System clock control register 1 (CM1) Chip select control register (CSR)
Address match interrupt enable register (AIER) Protect register (PRCR)
Watchdog timer start register (WDTS) Watchdog timer control register (WDC)
Address match interrupt register 0 (RMAD0)
Address match interrupt register 1 (RMAD1)
DMA0 source pointer (SAR0)
DMA0 destination pointer (DAR0)
DMA0 transfer counter (TCR0)
DMA0 control register (DM0CON)
DMA1 source pointer (SAR1)
DMA1 destination pointer (DAR1)
DMA1 transfer counter (TCR1)
DMA1 control register (DM1CON)
004016
004116
004216
004316
004416
004516
004616
004716
004816
004916
004A16
004B16
004C16
004D16
004E16
004F16
005016
005116
005216
005316
005416
005516
005616
005716
005816
005916
005A16
005B16
005C16
005D16
005E16
005F16
006016
006116
006216
006316
006416
006516
032A16
032B16
032C16
032D16
032E16
032F16
033016
033116
033216
033316
033416
033516
033616
033716
033816
033916
033A16
033B16
033C16
033D16
033E16
033F16
INT3 interrupt control register (INT3IC)
Timer B5 interrupt control register (TB5IC) Timer B4 interrupt control register (TB4IC) Timer B3 interrupt control register (TB3IC) SI/O4 interrupt control register (S4IC)
INT5 interrupt control register (INT5IC) SI/O3 interrupt control register (S3IC) INT4 interrupt control register (INT4IC)
Bus collision detection interrupt control register (BCNIC)
DMA0 interrupt control register (DM0IC) DMA1 interrupt control register (DM1IC) Key input interrupt control register (KUPIC)
A-D conversion interrupt control register (ADIC)
UART2 transmit interrupt control register (S2TIC) UART2 receive interrupt control register (S2RIC) UART0 transmit interrupt control register (S0TIC) UART0 receive interrupt control register (S0RIC) UART1 transmit interrupt control register (S1TIC) UART1 receive interrupt control register (S1RIC)
Timer A0 interrupt control register (TA0IC) Timer A1 interrupt control register (TA1IC) Timer A2 interrupt control register (TA2IC) Timer A3 interrupt control register (TA3IC) Timer A4 interrupt control register (TA4IC) Timer B0 interrupt control register (TB0IC) Timer B1 interrupt control register (TB1IC) Timer B2 interrupt control register (TB2IC)
INT0 interrupt control register (INT0IC) INT1 interrupt control register (INT1IC)
INT2 interrupt control register (INT2IC)
Note 1: Locations in the SFR area where nothing is allocated are reserved areas. Do not access these areas for read or write.
Figure 1.6.1. Location of peripheral unit control registers (1)
18
Mitsubishi microcomputers
M16C / 62A Group
SFR
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
034016
034116
034216
034316
034416
034516
034616
034716
034816
034916
034A16
034B16
034C16
034D16
034E16
034F16
035016
035116
035216
035316
035416
035516
035616
035716
035816
035916
035A16
035B16
035C16
035D16
035E16
035F16
036016
036116
036216
036316
036416
036516
036616
036716
036816
036916
036A16
036B16
036C16
036D16
036E16
036F16
037016
037116
037216
037316
037416
037516
037616
037716
037816
037916
037A16
037B16
037C16
037D16
037E16
037F16
Timer B3, 4, 5 count start flag (TBSR)
Timer A1-1 register (TA11)
Timer A2-1 register (TA21)
Timer A4-1 register (TA41)
Three-phase PWM control register 0(INVC0) Three-phase PWM control register 1(INVC1) Three-phase output buffer register 0(IDB0)
Three-phase output buffer register 1(IDB1) Dead time timer(DTT)
Timer B2 interrupt occurrence frequency set counter(ICTB2)
Timer B3 register (TB3)
Timer B4 register (TB4)
Timer B5 register (TB5)
Timer B3 mode register (TB3MR)
Timer B4 mode register (TB4MR)
Timer B5 mode register (TB5MR)
Interrupt cause select register (IFSR)
SI/O3 transmit/receive register (S3TRR)
SI/O3 control register (S3C) SI/O3 bit rate generator (S3BRG)
SI/O4 transmit/receive register (S4TRR)
SI/O4 control register (S4C)
SI/O4 bit rate generator (S4BRG)
UART2 special mode register 3(U2SMR3) UART2 special mode register 2(U2SMR2) UART2 special mode register (U2SMR)
UART2 transmit/receive mode register (U2MR) UART2 bit rate generator (U2BRG)
UART2 transmit buffer register (U2TB)
UART2 transmit/receive control register 0 (U2C0) UART2 transmit/receive control register 1 (U2C1)
UART2 receive buffer register (U2RB)
038016
038116
038216
038316
038416
038516
038616
038716
038816
038916
038A16
038B16
038C16
038D16
038E16
038F16
039016
039116
039216
039316
039416
039516
039616
039716
039816
039916
039A16
039B16
039C16
039D16
039E16
039F16
03A016
03A116
03A216
03A316
03A416
03A516
03A616
03A716
03A816
03A916
03AA16
03AB16
03AC16
03AD16
03AE16
03AF16
03B016
03B116
03B216
03B316
03B416
03B516
03B616
03B716
03B816
03B916
03BA16
03BB16
03BC16
03BD16
03BE16
03BF16
Count start flag (TABSR)
Clock prescaler reset flag (CPSRF)
One-shot start flag (ONSF)
Trigger select register (TRGSR)
Up-down flag (UDF)
Timer A0 (TA0)
Timer A1 (TA1)
Timer A2 (TA2)
Timer A3 (TA3)
Timer A4 (TA4)
Timer B0 (TB0)
Timer B1 (TB1)
Timer B2 (TB2)
Timer A0 mode register (TA0MR)
Timer A1 mode register (TA1MR)
Timer A2 mode register (TA2MR)
Timer A3 mode register (TA3MR)
Timer A4 mode register (TA4MR)
Timer B0 mode register (TB0MR)
Timer B1 mode register (TB1MR)
Timer B2 mode register (TB2MR)
UART0 transmit/receive mode register (U0MR)
UART0 bit rate generator (U0BRG)
UART0 transmit buffer register (U0TB)
UART0 transmit/receive control register 0 (U0C0) UART0 transmit/receive control register 1 (U0C1)
UART0 receive buffer register (U0RB)
UART1 transmit/receive mode register (U1MR)
UART1 bit rate generator (U1BRG)
UART1 transmit buffer register (U1TB)
UART1 transmit/receive control register 0 (U1C0) UART1 transmit/receive control register 1 (U1C1)
UART1 receive buffer register (U1RB)
UART transmit/receive control register 2 (UCON)
Flash memory control register 1 (FMR1) (Note1) Flash memory control register 0 (FMR0) (Note1) DMA0 request cause select register (DM0SL)
DMA1 request cause select register (DM1SL)
CRC data register (CRCD)
CRC input register (CRCIN)
Note 1: This register is only exist in flash memory version.
Note 2: Locations in the SFR area where nothing is allocated are reserved areas. Do not access these areas for read or write.
Figure 1.6.2. Location of peripheral unit control registers (2)
19
Mitsubishi microcomputers
M16C / 62A Group
SFR |
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER |
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03C016
03C116
03C216
03C316
03C416
03C516
03C616
03C716
03C816
03C916
03CA16
03CB16
03CC16
03CD16
03CE16
03CF16
03D016
03D116
03D216
03D316
03D416
03D516
03D616
03D716
03D816
03D916
03DA16
03DB16
03DC16
03DD16
03DE16
03DF16
03E016
03E116
03E216
03E316
03E416
03E516
03E616
03E716
03E816
03E916
03EA16
03EB16
03EC16
03ED16
03EE16
03EF16
03F016
03F116
03F216
03F316
03F416
03F516
03F616
03F716
03F816
03F916
03FA16
03FB16
03FC16
03FD16
03FE16
03FF16
A-D register 0 (AD0)
A-D register 1 (AD1)
A-D register 2 (AD2)
A-D register 3 (AD3)
A-D register 4 (AD4)
A-D register 5 (AD5)
A-D register 6 (AD6)
A-D register 7 (AD7)
A-D control register 2 (ADCON2)
A-D control register 0 (ADCON0) A-D control register 1 (ADCON1) D-A register 0 (DA0)
D-A register 1 (DA1)
D-A control register (DACON)
Port P0 (P0)
Port P1 (P1)
Port P0 direction register (PD0)
Port P1 direction register (PD1)
Port P2 (P2)
Port P3 (P3)
Port P2 direction register (PD2)
Port P3 direction register (PD3)
Port P4 (P4)
Port P5 (P5)
Port P4 direction register (PD4)
Port P5 direction register (PD5)
Port P6 (P6)
Port P7 (P7)
Port P6 direction register (PD6)
Port P7 direction register (PD7)
Port P8 (P8)
Port P9 (P9)
Port P8 direction register (PD8)
Port P9 direction register (PD9)
Port P10 (P10)
Port P10 direction register (PD10)
Pull-up control register 0 (PUR0) Pull-up control register 1 (PUR1) Pull-up control register 2 (PUR2) Port control register (PCR)
Note : Locations in the SFR area where nothing is allocated are reserved areas. Do not access these areas for read or write.
Figure 1.6.3. Location of peripheral unit control registers (3)
20
Mitsubishi microcomputers
M16C / 62A Group
Software Reset |
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER |
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Software Reset
Writing “1” to bit 3 of the processor mode register 0 (address 000416) applies a (software) reset to the microcomputer. A software reset has the same effect as a hardware reset. The contents of internal RAM are preserved.
(1) Types of Processor Mode
One of three processor modes can be selected: single-chip mode, memory expansion mode, and microprocessor mode. The functions of some pins, the memory map, and the access space differ according to the selected processor mode.
• Single-chip mode
In single-chip mode, only internal memory space (SFR, internal RAM, and internal ROM) can be accessed. However, after the reset has been released and the operation of shifting from the microprocessor mode has started (“H” applied to the CNVSS pin), the internal ROM area cannot be accessed even if the CPU shifts to the single-chip mode.
Ports P0 to P10 can be used as programmable I/O ports or as I/O ports for the internal peripheral functions.
• Memory expansion mode
In memory expansion mode, external memory can be accessed in addition to the internal memory space (SFR, internal RAM, and internal ROM). However, after the reset has been released and the operation of shifting from the microprocessor mode has started (“H” applied to the CNVSS pin), the internal ROM area cannot be accessed even if the CPU shifts to the memory expansion mode.
In this mode, some of the pins function as the address bus, the data bus, and as control signals. The number of pins assigned to these functions depends on the bus and register settings. (See “Bus Settings” for details.)
• Microprocessor mode
In microprocessor mode, the SFR, internal RAM, and external memory space can be accessed. The internal ROM area cannot be accessed.
In this mode, some of the pins function as the address bus, the data bus, and as control signals. The number of pins assigned to these functions depends on the bus and register settings. (See “Bus Settings” for details.)
(2) Setting Processor Modes
The processor mode is set using the CNVSS pin and the processor mode bits (bits 1 and 0 at address 000416). Do not set the processor mode bits to “102”.
Regardless of the level of the CNVSS pin, changing the processor mode bits selects the mode. Therefore, never change the processor mode bits when changing the contents of other bits. Also do not attempt to shift to or from the microprocessor mode within the program stored in the internal ROM area.
• Applying VSS to CNVSS pin
The microcomputer begins operation in single-chip mode after being reset. Memory expansion mode is selected by writing “012” to the processor mode is selected bits.
• Applying VCC to CNVSS pin
The microcomputer starts to operate in microprocessor mode after being reset.
Figure 1.7.1 shows the processor mode register 0 and 1.
Figure 1.7.2 shows the memory maps applicable for each of the modes.
21
Mitsubishi microcomputers
M16C / 62A Group
Processor Mode |
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER |
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Processor mode register 0 (Note 1)
b7 |
b6 |
b5 |
b4 |
b3 |
b2 |
b1 |
b0 |
Symbol |
Address |
When reset |
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PM0 |
000416 |
0016 (Note 2) |
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Bit symbol |
Bit name |
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Function |
R W |
PM00 |
Processor mode bit |
b1 b0 |
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0 |
0: Single-chip mode |
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0 |
1: Memory expansion mode |
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PM01 |
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1 |
0: Inhibited |
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1 |
1: Microprocessor mode |
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PM02 |
R/W mode select bit |
0 |
: RD,BHE,WR |
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Software reset bit |
1 |
: RD,WRH,WRL |
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PM03 |
The device is reset when this bit is set |
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to “1”. The value of this bit is “0” when |
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read. |
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Multiplexed bus space |
b5 b4 |
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PM04 |
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0 0 : Multiplexed bus is not used |
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select bit |
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0 1 : Allocated to CS2 space |
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PM05 |
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1 0 : Allocated to CS1 space |
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1 1 : Allocated to entire space (Note4) |
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PM06 |
Port P40 to P43 function |
0 : Address output |
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select bit (Note 3) |
1 : Port function |
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(Address is not output) |
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PM07 |
BCLK output disable bit |
0 : BCLK is output |
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1 : BCLK is not output |
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(Pin is left floating)
Note 1: Set bit 1 of the protect register (address 000A16) to “1” when writing new values to this register.
Note 2: If the VCC voltage is applied to the CNVSS, the value of this register when reset is 0316. (PM00 and PM01 both are set to “1”.)
Note 3: Valid in microprocessor and memory expansion modes.
Note 4: If the entire space is of multiplexed bus in memory expansion mode, choose an 8-
bit width.The processor operates using the separate bus after reset is revoked, so the entire space multiplexed bus cannot be chosen in microprocessor mode.
The higher-order address becomes a port if the entire space multiplexed bus is chosen, so only 256 bytes can be used in each chip select.
Processor mode register 1 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
0 0 0 0
Symbol |
Address |
When reset |
PM1 |
000516 |
00000XX02 |
Bit symbol |
Bit name |
Function |
R W |
Reserved bit |
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Must always be set to “0” |
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Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate.
PM13 |
Internal reserved area |
0: The same internal reserved |
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expansion bit (Note 2) |
area as that of M16C/60 and |
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M16C/61 group |
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1: Expands the internal RAM area |
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and internal ROM area to 23 K |
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bytes and to 256K bytes |
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respectively. (Note 2) |
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Reserved bit |
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Must always be set to “0” |
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Reserved bit |
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Must always be set to “0” |
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Reserved bit |
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Must always be set to “0” |
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PM17 |
Wait bit |
0 : No wait state |
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1 : Wait state inserted |
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Note 1: Set bit 1 of the protect register (address 000A16) to “1” when writing new values to this register. Note 2: Be sure to set this bit to 0 except products whose RAM size and ROM size exceed 15K bytes
and 192K bytes respectively.
In using M30624MAG/FGA, a product having a RAM of more than 15K bytes and a ROM of more than 192K bytes, set this bit to “1” at the beginning of user program.
Specify D000016 or a subsequent address, which becomes an internal ROM area if PM13 is set to “0” at the time reset is revoked, for the reset vector table of user program
Figure 1.7.1. Processor mode register 0 and 1
22
Mitsubishi microcomputers
M16C / 62A Group
Processor Mode |
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER |
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Single-chip mode |
Memory expansion mode |
Microprocessor mode |
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0000016 |
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SFR area |
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SFR area |
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SFR area |
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0040016 |
Internal |
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Internal |
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Internal |
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RAM area |
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RAM area |
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RAM area |
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XXXXX16 |
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Internally reserved area
0400016
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Inhibited |
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External |
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area |
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D000016 |
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Internally |
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YYYYY16 |
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reserved area |
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Internal |
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Internal |
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ROM area |
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ROM area |
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FFFFF16 |
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Type No. |
Address XXXXX16 |
Address YYYYY16 |
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M30622M4A |
00FFF16 |
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F800016 |
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M30620M8A |
02BFF16 |
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F000016 |
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M30620MAA |
02BFF16 |
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E800016 |
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M30620MCA/FCA |
02BFF16 |
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E000016 |
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M30622M8A |
013FF16 |
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F000016 |
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M30622MAA |
017FF16 |
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E800016 |
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M30622MCA |
017FF16 |
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E000016 |
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M30624MGA/FGA |
053FF16 |
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C000016 |
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Internally reserved area
External
area
External area : Accessing this area allows the user to access a device connected externally to the microcomputer.
Note : These memory maps show an instance in which PM13 is set to 0; but in the case of M30624MGA/FGA, they show an instance in which PM13 is set to 1.
Figure 1.7.2. Memory maps in each processor mode (without memory area expansion, normal mode)
23
Mitsubishi microcomputers
M16C / 62A Group
Processor Mode |
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER |
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Figure 1.7.3 shows the memory maps and the chip selection areas effected by PM13 (the internal reserved area expansion bit) in each processor mode for the product having an internal RAM of more than 15K bytes and a ROM of more than 192K bytes.
Internal reserved area expansion bit=“0”
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Memory expansion |
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Microprocessor |
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mode |
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mode |
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0000016 |
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SFR area |
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SFR area |
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(1K bytes) |
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(1K bytes) |
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0040016 |
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Internal RAM area |
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Internal RAM area |
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(15K bytes) |
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(15K bytes) |
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0400016 |
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CS3(16K bytes) |
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0800016 |
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CS2(128K bytes) |
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2800016 |
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CS1(32K bytes) |
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3000016 |
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External area |
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External area |
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CS0 |
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CFFFF16 |
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Memory expansion mode |
D000016 |
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: 640K bytes |
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Internal ROM area |
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Microprocessor mode |
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: 832K bytes |
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(192K bytes) |
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FFFFF16 |
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After reset |
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Internal reserved area expansion bit=“1”
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Memory expansion |
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Microprocessor |
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mode |
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mode |
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0000016 |
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SFR area |
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SFR area |
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(1K bytes) |
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(1K bytes) |
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0040016 |
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Internal RAM area |
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Internal RAM area |
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(20K bytes) |
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(20K bytes) |
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0540016 |
Internal reserved area |
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Internal reserved area |
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0600016 |
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CS3(8K bytes) |
0800016 |
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CS2(128K bytes) |
2800016 |
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CS1(32K bytes) |
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3000016 |
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BFFFF16 |
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External area |
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External area |
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CS0 |
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C000016 |
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Memory expansion mode |
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Internal ROM area |
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: 576K bytes |
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Microprocessor mode |
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(256K bytes) |
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: 832K bytes |
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FFFFF16
After reset, and set the Internal reserved area expansion bit to “1”
Note: The reset vector lies in an area between D000016 and FFFFB16.
Figure 1.7.3. Memory location and chip select area in each processor mode
24
Mitsubishi microcomputers
M16C / 62A Group
Bus Settings |
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER |
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Bus Settings
The BYTE pin and bits 4 to 6 of the processor mode register 0 (address 000416) are used to change the bus settings. Table 1.8.1 shows the factors used to change the bus settings.
Table 1.8.1. Factors for switching bus settings
Bus setting |
Switching factor |
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Switching external address bus width |
Bit 6 of processor mode register 0 |
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Switching external data bus width |
BYTE pin |
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Switching between separate and multiplex bus |
Bits 4 and 5 of processor mode register 0 |
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(1) Selecting external address bus width
The address bus width for external output in the 1M bytes of address space can be set to 16 bits (64K bytes address space) or 20 bits (1M bytes address space). When bit 6 of the processor mode register 0 is set to “1”, the external address bus width is set to 16 bits, and P2 and P3 become part of the address bus. P40 to P43 can be used as programmable I/O ports. When bit 6 of processor mode register 0 is set to “0”, the external address bus width is set to 20 bits, and P2, P3, and P40 to P43 become part of the address bus.
(2) Selecting external data bus width
The external data bus width can be set to 8 or 16 bits. (Note, however, that only the separate bus can be set.) When the BYTE pin is “L”, the bus width is set to 16 bits; when “H”, it is set to 8 bits. (The internal bus width is permanently set to 16 bits.) While operating, fix the BYTE pin either to “H” or to “L”.
(3) Selecting separate/multiplex bus
The bus format can be set to multiplex or separate bus using bits 4 and 5 of the processor mode register 0.
• Separate bus
In this mode, the data and address are input and output separately. The data bus can be set using the BYTE pin to be 8 or 16 bits. When the BYTE pin is “H”, the data bus is set to 8 bits and P0 functions as the data bus and P1 as a programmable I/O port. When the BYTE pin is “L”, the data bus is set to 16 bits and P0 and P1 are both used for the data bus.
When the separate bus is used for access, a software wait can be selected.
• Multiplex bus
In this mode, data and address I/O are time multiplexed. With an 8-bit data bus selected (BYTE pin = “H”), the 8 bits from D0 to D7 are multiplexed with A0 to A7.
With a 16-bit data bus selected (BYTE pin = “L”), the 8 bits from D0 to D7 are multiplexed with A1 to A8. D8 to D15 are not multiplexed. In this case, the external devices connected to the multiplexed bus are mapped to the microcomputer’s even addresses (every 2nd address). To access these external devices, access the even addresses as bytes.
The ALE signal latches the address. It is output from P56.
Before using the multiplex bus for access, be sure to insert a software wait.
If the entire space is of multiplexed bus in memory expansion mode, choose an 8-bit width.
The processor operates using the separate bus after reset is revoked, so the entire space multiplexed bus cannot be chosen in microprocessor mode.
The higher-order address becomes a port if the entire space multiplexed bus is chosen, so only 256 bytes can be used in each chip select.
25
Mitsubishi microcomputers
M16C / 62A Group
Bus Settings |
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER |
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Table 1.8.2. Pin functions for each processor mode
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Processor mode |
Single-chip |
Memory expansion mode/microprocessor modes |
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“01”, “10” |
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“00” |
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Multiplexed bus |
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Either CS1 or CS2 is for |
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space select bit |
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multiplexed bus and others |
(separate bus) |
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are for separate bus |
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Data bus width |
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8 bits |
16 bits |
8 bits |
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16 bits |
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BYTE pin level |
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“H” |
“L” |
“H” |
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“L” |
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P00 to P07 |
I/O port |
Data bus |
Data bus |
Data bus |
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Data bus |
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P10 to P17 |
I/O port |
I/O port |
Data bus |
I/O port |
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Data bus |
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P20 |
I/O port |
Address bus |
Address bus |
Address bus |
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Address bus |
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/data bus(Note 2) |
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P21 to P27 |
I/O port |
Address bus |
Address bus |
Address bus |
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Address bus |
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/data bus(Note 2) |
/data bus(Note 2) |
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P30 |
I/O port |
Address bus |
Address bus |
Address bus |
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Address bus |
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/data bus(Note 2) |
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P31 to P37 |
I/O port |
Address bus |
Address bus |
Address bus |
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Address bus |
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P40 to P43 |
I/O port |
I/O port |
I/O port |
/O port |
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I/O port |
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Port P40 to P43 |
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function select bit = 1 |
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P40 to P43 |
I/O port |
Address bus |
Address bus |
Address bus |
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Address bus |
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Port P40 to P43 |
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function select bit = 0 |
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Memory expansion mode
“11” (Note 1) multiplexed bus for the entire
space
8 bit “H”
I/O port
I/O port
Address bus /data bus
Address bus /data bus
A8/D7
I/O port
I/O port
I/O port
P44 to P47 |
I/O port |
P50 to P53 |
I/O port |
CS (chip select) or programmable I/O port (For details, refer to “Bus control”)
Outputs RD, WRL, WRH, and BCLK or RD, BHE, WR, and BCLK (For details, refer to “Bus control”)
P54 |
I/O port |
HLDA |
HLDA |
HLDA |
HLDA |
HLDA |
P55 |
I/O port |
HOLD |
HOLD |
HOLD |
HOLD |
HOLD |
P56 |
I/O port |
ALE |
ALE |
ALE |
ALE |
ALE |
P57 |
I/O port |
RDY |
RDY |
RDY |
RDY |
RDY |
Note 1: If the entire space is of multiplexed bus in memory expansion mode, choose an 8-bit width.
The processor operates using the separate bus after reset is revoked, so the entire space multiplexed bus cannot be chosen in microprocessor mode.
The higher-order address becomes a port if the entire space multiplexed bus is chosen, so only 256 bytes can be used in each chip select.
Note 2: Address bus when in separate bus mode.
26
Mitsubishi microcomputers
M16C / 62A Group
Bus Control |
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER |
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Bus Control
The following explains the signals required for accessing external devices and software waits. The signals required for accessing the external devices are valid when the processor mode is set to memory expansion mode and microprocessor mode. The software waits are valid in all processor modes.
(1) Address bus/data bus
The address bus consists of the 20 pins A0 to A19 for accessing the 1M bytes of address space. The data bus consists of the pins for data I/O. When the BYTE pin is “H”, the 8 ports D0 to D7 function as the data bus. When BYTE is “L”, the 16 ports D0 to D15 function as the data bus.
When a change is made from single-chip mode to memory expansion mode, the value of the address bus is undefined until external memory is accessed.
(2) Chip select signal
The chip select signal is output using the same pins as P44 to P47. Bits 0 to 3 of the chip select control register (address 000816) set each pin to function as a port or to output the chip select signal. The chip select control register is valid in memory expansion mode and microprocessor mode. In single-chip mode, P44 to P47 function as programmable I/O ports regardless of the value in the chip select control
register.
_______
In microprocessor mode, only CS0 outputs the chip select signal after the reset state has been cancelled. CS1 to CS3 function as input ports. Figure 1.9.1 shows the chip select control register.
The chip select signal can be used to split the external area into as many as four blocks. Tables 1.9.1 and 1.9.2 show the external memory areas specified using the chip select signal.
Table 1.9.1. External areas specified by the chip select signals
(A product having an internal RAM equal to or less than 15K bytes and a ROM equal to or less than 192K bytes)(Note)
Processor mode |
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Chip select signal |
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CS0 |
CS1 |
CS2 |
CS3 |
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Memory expansion mode |
3000016 to |
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CFFFF16 |
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0800016 to |
0400016 to |
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(640K bytes) |
2800016 to |
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3000016 to |
2FFFF16 |
27FFF16 |
07FFF16 |
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(32K bytes) |
(128K bytes) |
(16K bytes) |
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Microprocessor mode |
FFFFF16 |
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(832K bytes)
Note :Be sure to set bit 3 (PM13) of processor mode register 1 to “0”.
27
Mitsubishi microcomputers
M16C / 62A Group
Bus Control |
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER |
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Table 1.9.2. External areas specified by the chip select signals
(A product having an internal RAM of more than 15K bytes and a ROM of more than 192K bytes)
Processor mode |
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Chip select signal |
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CS0 |
CS1 |
CS2 |
CS3 |
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When PM13=0 |
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When PM13=0 |
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3000016 to CFFFF16 |
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0400016 to |
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Memory expansion mode |
(640K bytes) |
2800016 to |
0800016 to |
07FFF16 |
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When PM13=1 |
(16K bytes) |
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2FFFF16 |
27FFF16 |
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3000016 to BFFFF16 |
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(32K bytes) |
(128K bytes) |
When PM13=1 |
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(576K bytes) |
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0600016 to |
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0300016 to FFFFF16 |
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Microprocessor mode |
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07FFF16 |
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(816K bytes) |
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(8K bytes) |
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Chip select control register
b7 |
b6 |
b5 |
b4 |
b3 |
b2 |
b1 |
b0 |
Symbol |
Address |
When reset |
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CSR |
000816 |
0116 |
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Bit symbol |
Bit name |
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Function |
R W |
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CS0 |
CS0 output enable bit |
0 |
: Chip select output disabled |
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CS1 |
CS1 output enable bit |
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(Normal port pin) |
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1 |
: Chip select output enabled |
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CS2 |
CS2 output enable bit |
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CS3 |
CS3 output enable bit |
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CS0W |
CS0 wait bit |
0 |
: Wait state inserted |
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CS1W |
CS1 wait bit |
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1 |
: No wait |
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CS2W |
CS2 wait bit |
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CS3W |
CS3 wait bit |
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Figure 1.9.1. Chip select control register
28
Mitsubishi microcomputers
M16C / 62A Group
Bus Control |
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER |
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(3) Read/write signals
With a 16-bit data bus (BYTE pin =“L”), bit 2 of the processor mode register 0 (address 000416) select the combinations of RD, BHE, and WR signals or RD, WRL, and WRH signals. With an 8-bit data bus (BYTE pin = “H”), use the combination of RD, WR, and BHE signals. (Set bit 2 of the processor mode register 0 (address 000416) to “0”.) Tables 1.9.3 and 1.9.4 show the operation of these signals.
After a reset has been cancelled, the combination of RD, WR, and BHE signals is automatically selected. When switching to the RD, WRL, and WRH combination, do not write to external memory until bit 2 of the processor mode register 0 (address 000416) has been set (Note).
Note: Before attempting to change the contents of the processor mode register 0, set bit 1 of the protect register (address 000A16) to “1”.
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_____ |
________ |
_________ |
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Table 1.9.3. Operation of RD, WRL, and WRH signals |
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Data bus width |
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RD |
WRL |
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WRH |
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Status of external data bus |
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L |
H |
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H |
Read data |
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16-bit |
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H |
L |
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H |
Write 1 byte of data to even address |
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(BYTE = “L”) |
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H |
H |
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L |
Write 1 byte of data to odd address |
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H |
L |
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L |
Write data to both even and odd addresses |
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_____ |
______ |
________ |
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Table 1.9.4. Operation of RD, WR, and BHE signals |
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Data bus width |
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RD |
WR |
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BHE |
A0 |
Status of external data bus |
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H |
L |
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L |
H |
Write 1 byte of data to odd address |
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L |
H |
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L |
H |
Read 1 byte of data from odd address |
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16-bit |
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H |
L |
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H |
L |
Write 1 byte of data to even address |
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(BYTE = “L”) |
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L |
H |
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H |
L |
Read 1 byte of data from even address |
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H |
L |
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L |
L |
Write data to both even and odd addresses |
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L |
H |
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L |
L |
Read data from both even and odd addresses |
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8-bit |
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H |
L |
Not used |
H / L |
Write 1 byte of data |
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(BYTE = “H”) |
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L |
H |
Not used |
H / L |
Read 1 byte of data |
(4) ALE signal
The ALE signal latches the address when accessing the multiplex bus space. Latch the address when the
ALE signal falls.
When BYTE pin = “H” |
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When BYTE pin = “L” |
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ALE |
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ALE |
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D0/A0 to D7/A7 |
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Address |
Data (Note 1) |
A0 |
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Address |
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A8 to A19 |
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Address (Note 2) |
D0/A1 to D7/A8 |
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Address |
Data (Note 1) |
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A9 to A19 |
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Address |
Note 1: Floating when reading.
Note 2: When multiplexed bus for the entire space is selected, these are I/O ports.
Figure 1.9.2. ALE signal and address/data bus
29
Mitsubishi microcomputers
M16C / 62A Group
Bus Control |
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER |
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________
(5) The RDY signal
________
RDY is a signal that facilitates access to an external device that requires long access time. As shown in
________
Figure 1.9.3, if an “L” is being input to the RDY at the BCLK falling edge, the bus turns to the wait state. If
________
an “H” is being input to the RDY pin at the BCLK falling edge, the bus cancels the wait state. Table 1.9.5 shows the state of the microcomputer with the bus in the wait state, and Figure 1.9.3 shows an example
in which the RD signal is prolonged by the RDY signal.
________
The RDY signal is valid when accessing the external area during the bus cycle in which bits 4 to 7 of the
________
chip select control register (address 000816) are set to “0”. The RDY signal is invalid when setting “1” to
________
all bits 4 to 7 of the chip select control register (address 000816), but the RDY pin should be treated as properly as in non-using.
Table 1.9.5. Microcomputer status in ready state (Note)
Item |
|
Status |
Oscillation |
|
On |
___ |
_____ |
________ |
R/W signal, address bus, data bus, CS |
Maintain status when RDY signal received |
|
__________ |
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ALE signal, HLDA, programmable I/O ports |
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Internal peripheral circuits |
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On |
________
Note: The RDY signal cannot be received immediately prior to a software wait.
In an instance of separate bus
BCLK
RD
CSi (i=0 to 3)
RDY
tsu(RDY - BCLK)
Accept timing of RDY signal
In an instance of multiplexed bus
BCLK
RD
CSi (i=0 to 3)
RDY
:Wait using RDY signal
:Wait using software
tsu(RDY - BCLK)
Accept timing of RDY signal
_____ |
________ |
Figure 1.9.3. Example of RD signal extended by RDY signal
30