Intel® I/O Controller Hub 8 LAN
NVM Map and Information Guide
January 2008
316234-006
Revision 2.8
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processor families. See http://www.intel.com/products/processor_number for details.
This document contains information on products in the design phase of development. The information here is subject to change without notice. Do not
finalize a design with this information.
The I/O Control Hub (ICH8 ) may c ontai n des ign de fects o r er rors kno wn as er r ata whi ch ma y caus e the p ro duct to d evia te from p ub lished specifications.
Current characterized errata are available on request.
Hyper-Threading Technology requir es a computer syste m with an Intel
chipset, BIOS and operating system. Performance will vary depending on the specific hardware and software you use. See http://www.intel.com/
products/ht/Hyperthreading_more.htm for addition a l information.
®
Pentium® 4 processor supporting HT T echnology and a HT Technology enabled
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from:
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2.5April 2007R emov ed all references to ICH9. Minor edit all sections.
2.4Jan 2007
2.3Jan 2007Added ICH9 and 82567 NVM information.
2.2Oct 2006Added device IDs for the 82562G and 82562GT 10/100 Mb/s Platform LAN Connects.
2.1July 2006Changed bit 1 of word 13h to 0b.
2.0June 2006
1.75April 2006Updated bit descriptions for words 13h, 14h, and 19h.
1.5Feb 2006
1.0Dec 2005
0.75July 2005Initial release (Intel Secret).
Updated bit descriptions for words 0Fh, 13h, 14h, 15h, 16h, 32h, and 33h.
Updated NVM images in Appendix A.
Updated sections 1.2, 1.4.6, 1.4.13, 1.4.14, 1.4.19, and 1.4.20.
Added sections 1.4.25.1 through 1.4.25.4 (PXE words 30h through 33h).
Initial public release.
Added new LAN Word Offset 19h description to Tables 1 and 17.
Added new EEPROM images to Appendix A.
Updated bit defaults and descriptions to Tables 9, 10, 13, 15, and 16.
Initial Intel Confidential release.
Converted this to a stand-alone document. Previously, it was AP-478 Addendum.
Added Section 1.1, ”NVM Programming Procedure Overview,” and Section 1.2,
”EEUPDATE Utility.”
Updated the following sections:
Section 2.12, ”Shared Initialization Control (Word 13h),” bits 10 and 0
Section 2.13, ”Extended Configuration Word 1 (Word 14h),” bits 15, 14, and 11:0
Section 2.14, ”Extended Configuration Word 2 (Word 15h),” bits 15:8
Section 2.15, ”Extended Configuration Word 3 (Word 16h)”
Section 2.16, ”LED 1 Configuration and Power Management (Wo rd 17h),” bit 7
Section 2.17, ”LED 0 and 2 Configuration Defaults (Word 18h),” bit 7
Section 2.18, ”Future Initialization Word 1 (Words 19h)”
Section 2.20, ”Checksum (Word 3Fh)”
Appendix A.1 ”82566DM NVM Image with ICH8”
Appendix A.3 ”82562V NVM Image with ICH8”
Updated Section 2.12, ”Shared Initialization Control (Word 13h),” Table 9 to add the
Ext Pwr Polarity bit.
Added the 82566 NVM image to A.1 ”82566DM NVM Image with ICH8.”
4
ICH8—NVM Information Guide
1.0Non-Volatile Memory (NVM)
1.1Introduction
The document is intended for designs using the 10/100/1000 Mb/s LAN controller that
is integrated into the Intel
The NVM space is used for hardware and software configuration. It is also read by
software to determine and configure specific design features.
Unless otherwise sp ec ified, all numbers in this document use the f ollowing numbering
convention:
• Numbers that do not have a suffix are decimal (base 10).
• Numbers with a suffix of “h” are hexadecimal (base 16).
• Numbers with a suffix of “b” are binary (base 2).
®
I/O Control Hub 8 (ICH8) device.
1.2NVM Programming Procedure Overview
The LAN NVM shares space on an SPI Flash device (or devices) along with the BIOS,
Manageability Firmware, and a Flash Descriptor Region. It is programmed through the
ICH8. This combi ned image is show n in Figure 1. The Flash Descriptor Region is used to
define vendor specific information and the location, allocated space, and read and write
permissions for each region. The Manageability (ME) Region contains the code and
configuration data for ME functions such as Intel
and Advanced Fan Speed Control. The system BIOS is contained in the BIOS Region.
The ME Region and BIOS Region are beyond t he scope of this document and a more
detailed explanation of these areas can be found in the Intel(ICH8) Family External Design Specification (ICH8 EDS) . This document describes the
LAN image contained in the Gigabit Ethernet (GbE) region. Fast Ethernet (82562V)
images are also described.
®
Active Management Technology , ASF,
®
I/O Controller Hub 8
5
Flash Descriptor
Region
Region
BIOS
Region
ME
Region
GbE
NVM Information Guide—ICH8
1
2
3
0
Figure 1.LAN NVM Regions
To access the NVM, it is essential to correctly setup the following:
1. A valid Flash Descriptor Region must be present. Details for the Flash Descriptor
Region are contained in the ICH8 EDS. The
method of configuring this descriptor region. This process is described in detail in
the Intel
FTOOL.exe and the Intel
can be obtained as part of the Intel A c tive Client Manager kit on ARMS
(https://platformsw.intel.com/) or by contacting your local Intel representative.
2. The GbE region must be part of th e original image flashed onto the part.
3. For Intel LAN tools and drivers to work correctly, the BIOS must set the VSCC
register(s) correctly. This information is described in ICH8 EDS, section 24.1.
4. The GbE region of the NVM must be accessible. To keep this region accessible, the
Protected Range reg ister of the GbE LAN Memory Mapped Con fi guration registers
must be set to their default value of 0000 0000h. (The GbE Protected Range
registers are described in the ICH8 EDS).
5. If you are using the 82566, the ICH8 soft strap for the GLCI interface must be set
correctly . Bit 19 of STRP0 must be set to 1b (as described in the ICH8 EDS). F or the
82562V, this bit can be set to 0b, since it does not us e the GLCI bus.
®
Active Management Technology OEM Bring-Up Guide.
®
Active Manageme nt Technology OEM Bring-Up Gu ide
FTOOL.exe utility provi des the easiest
6
ICH8—NVM Information Guide
6. The sector size of the NVM must equal 256 bytes, 4 KB, or 64 KB. When a Flash
device that uses a 64 KB sector erase is used, the GbE region size must equal
128 KB. If the Flash part uses a 4 KB or 25 6-byte sect or erase, then the GbE region
size must be set to 8 KB.
The NVM image contains both static and dynamic data. The static data is the basic
platform configuration, and includes OEM specific configuration bits as well as the
unique Printed Circuit Board Assembly (PBA). The dynamic data holds the product’s
Ethernet Individual Address (IA ) and C he c ksum. This file can be created in a simple
text editor and follows the format shown in Appendix A, whic h provides examples of
GbE Region NVM maps for ICH8-based designs. Fast Ethernet (82562V) images are
also provided.
1.3EEUPDATE Utility
Intel has created an EEUPD ATE utility that can be us ed to up date the GbE region
images during in -circu it pro gr amming. T he too l uses t wo b asic d ata fil es outli ned i n the
following sect io n ( sta tic data file and IA addres s file). The EEUPDATE utility is flexible
and can be used to update the entire GbE region image or only the IA address of the
LAN controller. In addition, it also corrects the GbE component checksum field after the
region is modified (FTOOL does not have this ability). For more information on how to
use EEUPDATE, refer to the
utility.
eeupdate.txt file that is included with the EEUPDATE
To obtain a copy of this program, contact your Intel repres entative.
1.3.1Command Line Parameters
The DOS command format is as follows:
EEUPDATE Parameter_1 Parameter_2
where:
Parameter_1 = /D or /A
/D is used to update the entire GbE region image.
/A is used to update just the Et hernet Individual Address.
Parameter_2 = filename
In Example 1, Pa rameter_2 is
a specific format used to update the complete GbE region. All comments in the
file must be preceded by a semicolon (;).
Example 1. EEUPDATE /D file1.eep
In Example 1, Parameter 2 is
EEUPDATE utility finds the first unused address from this file and uses it to update the
NVM. An address is marked used if it is followed by a date stamp. When the utility uses
a specific ad dress, a log file c alled eelog .dat is updat ed with that addre ss. This update d
file should be used as the
Appendix A provides an example of the raw GbE region contents. F a s t Ethernet
(82562V) images are also provided.
file1.eep, which c ontains the complete NVM im age in
file2.dat, which contains a list of IA addresses. The
.dat file for the next update.
.eep
7
1.4LAN NVM Format and Contents
Table 1 lists the NVM maps for the LAN region. Each word listed is described in detail in
the following sec tions.
Table 1.LAN NVM Address Map
NVM Information Guide—ICH8
LAN
Word
Offset
00h00
01h02
02h04
03h06ReservedSW0800h
04h08ReservedSWFFFFh
05h0AImage Version Information 1SW
06h0ChReservedSWFFFFh
07h0EhReservedSWFFFFh
08h10hPBA LowSW
09h12hPBA HighSW
0Ah14hPCI Initialization Control WordHW-PCI
0Bh16hSubsystem IDHW-PCI
0Ch18hSubsystem Vendor IDHW-PCI
0Dh1AhDevice IDHW-PCI
0Eh1ChVendor IDHW-PCI
0Fh1EhDevice REV IDHW-PCI
10h20hLAN Power ConsumptionHW-PCI
11h22hReserved
12h24hReserved
13h26hShared Initialization Control Word
14h28hExtended Configuration Word 1
15h2AhExtended Configuration Word 2
16h2ChExtended Configuration Wo rd 3
17h2EhLEDCTL 1
18h30hLEDCTL 0 2
19h32hFuture Initialization Word 1
1Ah34hFuture Initialization Word 2
NVM
Byte
Offset
HIgh Byte (Bits 15:8)Low Byte (Bits 7:0)Used By
Ethernet Individual Address
Byte 2
Ethernet Individual Address
Byte 4
Ethernet Individual Address
Byte 6
Ethernet Individual Address
Byte 1
Ethernet Individual Address
Byte 3
Ethernet Individual Address
Byte 5
HW-
Shared
HW-
Shared
HW-
Shared
HW-
Shared
HW-
Shared
HW-
Shared
HW-
Shared
HW-
Shared
HW-
Shared
HW-
Shared
HW-
Shared
Image
Value
IA (2,1)
IA (4,3)
IA (6,5)
0000h
0000h
8
ICH8—NVM Information Guide
LAN
Word
Offset
1Bh to
2Fh
30h to
3Eh
3Fh7EhSoftware Checksum (bytes 00h through 7Dh)SW
Notes:
1.SW = Software: This is access from the network configuration tools and drivers.
2.PXE = PXE Boot Agent: This is access from the PXE Option ROM code in BIOS.
3.HW-Shared = Hardware - Shared: This is read on when the Shared Configuration is reset.
4.HW-PCI = Hardware - PCI: This is read when the PCI Configuration is reset.
The Ethernet Individual Address (IA) is a six-byte field that must be unique for each
adapter card or LOM and unique for each copy of the NVM image. The first three bytes
are vendor specific . (For example, these bytes equal 00 AA 00 or 00 A 0 C9 for Intel
products.) The last three bytes must be unique for each copy of the NVM. OEM versions
of the product m ight be requ ired t o ha ve non- Inte l ID’ s in th e fi rst thr ee by te po sitio ns.
The value from this field is loaded into the Receive Address Register 0 (RAL0/RAH0).
The Intel default is listed in Table 2.
Note:The Ethernet IA is byte swapped, as listed in Table 2.
The IA bytes read from the NVM are used by the ICH8 until an IA Setup comm a nd is
issued by software. The IA defined by the IA Setup command overrides the IA read
from the NVM.
1.4.2Reserved (Word 03h)
Table 3.Reserved (Word 03h)
BitNameDefaultDescription
15:12 Reserved0000bThese bits are reserved and should be set to 0000b.
11IBA LOM1bMust be set to 1b for Intel Boot Agent (IBA) to function correctly.
10:0Reserved0hThese bits are reserved and should be set to 0h.
5
9
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