Intel 80303, 80302 User Manual

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Intel® 80303 and 80302 I/O

Processors

Specification Update

May 6, 2003

Notice: The Intel® 80303 and Intel® 80302 I/O Processors processor may contain design defects or errors known as errata. Characterized errata that may cause the product’s behavior to deviate from pubished specifications are documented in this specification update.

Order Number: 273355-010

INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.

Intel products are not intended for use in medical, life saving, life sustaining applications.

Intel may make changes to specifications and product descriptions at any time, without notice.

Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

The Intel® 80303 and Intel® 80302 I/O Processors may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request.

Intel® internal code names are subject to change.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548-4725 or by visiting Intel's website at http://www.intel.com.

Copyright© Intel Corporation, 2003

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*Other names and brands may be claimed as the property of others.

Intel® 80303 and 80302 I/O Processors Specification Update

Contents

 

Revision History .........................................................................................

5

Preface.......................................................................................................

7

Summary Table of Changes.......................................................................

8

Identification Information..........................................................................

14

Errata .......................................................................................................

16

Specification Changes .............................................................................

23

Specification Clarifications .......................................................................

25

Documentation Changes .........................................................................

28

Intel® 80303 and 80302 I/O Processors Specification Update

3

This Page Intentionally Left Blank

4

Intel® 80303 and 80302 I/O Processors Specification Update

Revision History

Revision History

sc

Date

Version

Description

 

 

 

05/01/03

010

Added Errata 2.

Revised Specification Clarifications 4, 7 and 8.

 

 

 

 

 

08/27/02

009

Reworded Specification Clarification 4.

Added Specification Clarifications 7 and 8.

 

 

 

 

 

11/15/01

008

Added Specification Clarifications 5 and 6.

Added Document Changes 32 and 33.

 

 

 

 

 

08/22/01

007

Added Specification Clarification 4.

Added Document Changes 30 and 31.

 

 

 

 

 

 

 

Added Document Changes 25 through 29.

04/24/01

006

Revised Device ID Registers “A-2” Revision ID Registers data.

 

 

Added Note to Device ID Registers.

 

 

 

04/02/01

005

Added Specification Clarification 3.

 

 

 

 

 

Added Errata 1.

 

 

Added Specification Change 1.

03/22/01

004

Added Specification Clarifications 1 and 2.

 

 

Added Document Changes 13 through 24.

 

 

Updated Die Details Table and Device ID Registers for A-2 step.

 

 

 

02/23/01

003

Die Details and Device ID Registers tables, corrected stepping A-0 to A-1.

 

 

 

 

 

Updated Die Details Table.

08/2000

002

Revised Device ID Registers Table.

 

 

Added Document Changes 1 through 12.

 

 

 

06/2000

001

This is the new Specification Update document. It contains all identified errata published

prior to this date.

 

 

 

 

 

Intel® 80303 and 80302 I/O Processors Specification Update

5

Preface

Preface

This document is an update to the specifications contained in the Affected Documents/Related Documents table below. This document is a compilation of device and documentation errata, specification clarifications and changes. It is intended for hardware system manufacturers and software developers of applications, operating systems, or tools.

Information types defined in Nomenclature are consolidated into the specification update and are no longer published in other documents.

This document may also contain information that was not previously published.

Affected Documents/Related Documents

 

 

Title

Order #

 

 

 

 

Intel®

80303

I/O Processor Developer’s Manual

273353

Intel®

80303

I/O Processor Data Sheet

273358

Intel®

80303

I/O Processor Design Guide

273308

Nomenclature

Errata are design defects or errors. These may cause the Intel® 80303 and Intel® 80302 I/O Processors behavior to deviate from published specifications. Hardware and software designed to be used with any given stepping must assume that all errata documented for that stepping are present on all devices.

Specification Changes are modifications to the current published specifications. These changes will be incorporated in any new release of the specification.

Specification Clarifications describe a specification in greater detail or further highlight a specification’s impact to a complex design situation. These clarifications will be incorporated in any new release of the specification.

Documentation Changes include typos, errors, or omissions from the current published specifications. These will be incorporated in any new release of the specification.

Note: Errata remain in the specification update throughout the product’s lifecycle, or until a particular stepping is no longer commercially available. Under these circumstances, errata removed from the specification update are archived and available upon request. Specification changes, specification clarifications and documentation changes are removed from the specification update when the appropriate changes are made to the appropriate product specification or user documentation (datasheets, manuals, etc.).

6

Intel® 80303 and 80302 I/O Processors Specification Update

Summary Table of Changes

Summary Table of Changes

The following table indicates the errata, specification changes, specification clarifications, or documentation changes which apply to the Intel® 80303 and Intel® 80302 I/O Processors product. Intel may fix some of the errata in a future stepping of the component, and account for the other outstanding issues through documentation or specification changes as noted. This table uses the following notations:

Codes Used in Summary Table

Stepping

X:

Errata exists in the stepping indicated. Specification Change or

 

Clarification that applies to this stepping.

(No mark)

 

or (Blank box):

This erratum is fixed in listed stepping or specification change does not

 

apply to listed stepping.

Page

(Page):

Page location of item in this document.

Status

Doc:

Document change or update will be implemented.

Fix:

This erratum is intended to be fixed in a future step of the component.

Fixed:

This erratum has been previously fixed.

NoFix:

There are no plans to fix this erratum.

Eval:

Plans to fix this erratum are under evaluation.

Row

Change bar to left of table row indicates this erratum is either new or modified from the previous version of the document.

Intel® 80303 and 80302 I/O Processors Specification Update

7

Summary Table of Changes

Errata

No.

 

Steppings

 

Page

Status

Errata

 

 

 

 

 

 

A-0

 

A-1

 

A-2

 

 

 

 

 

 

 

 

 

 

 

 

1

X

 

X

 

X

12

NoFix

Single-bit and Multi-bit Error Reporting Cannot Be

 

 

Individually Enabled by ECC Control Register

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2

X

 

X

 

X

12

NoFix

Instruction Sequence Can Scoreboard a Register

 

 

Indefinitely

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Specification Changes

 

 

Steppings

 

 

 

 

No.

 

 

 

 

 

Page

Status

Specification Changes

 

A-2

 

#-#

 

#-#

 

 

 

 

 

 

 

 

 

 

 

 

1

X

 

 

 

 

14

Doc

Summary of the Intel® 80302 I/O Processor

 

 

 

 

 

 

 

 

 

Specification Clarifications

No.

 

Steppings

 

Page

Status

Specification Clarifications

 

 

 

 

 

 

A-0

 

A-1

 

A-2

 

 

 

 

 

 

 

 

 

 

 

 

1

X

 

X

 

X

15

Doc

ECC is Always Enabled

 

 

 

 

 

 

 

 

 

2

X

 

X

 

X

15

Doc

32-bit SDRAM is Not Supported

 

 

 

 

 

 

 

 

 

3

X

 

X

 

X

15

Doc

Non-Battery Backup Systems

 

 

 

 

 

 

 

 

 

4

X

 

X

 

X

15

Doc

POCCDR and SOCCDR Functionality

 

 

 

 

 

 

 

 

 

5

X

 

X

 

X

15

Doc

‘Bus Hold’ Devices on the RAD Bus

 

 

 

 

 

 

 

 

 

6

X

 

X

 

X

16

Doc

SREQ64# Functionality

 

 

 

 

 

 

 

 

 

7

X

 

X

 

X

16

Doc

PCI Local Bus Specification, Revision 2.3 Compliancy

 

 

 

 

 

 

 

 

 

8

X

 

X

 

X

16

Doc

DMA and AAU End of Chain Functionality

 

 

 

 

 

 

 

 

 

8

Intel® 80303 and 80302 I/O Processors Specification Update

Summary Table of Changes

Documentation Changes

No.

Document Revision

Page

Status

Documentation Changes

 

 

 

 

 

1

272353-001

17

Doc

Title Page revision number

 

 

 

 

 

2

272353-001

17

Doc

Figure 9-3 on pg 9-9 did not print correctly

 

 

 

 

 

3

272353-001

18

Doc

Figure 13-22 on pg 13-40 did not print correctly

 

 

 

 

 

4

272353-001

18

Doc

Figure 13-18, pg 13-35

 

 

 

 

 

5

272353-001

19

Doc

Figure 15-2 on pg 15-3 did not print correctly

 

 

 

 

 

6

272353-001

20

Doc

Incorrect Vendor ID in ATU register

 

 

 

 

 

7

272353-001

20

Doc

Section 23.2 on pg 23-2 has incorrect text

 

 

 

 

 

8

272353-001

21

Doc

Table 24-4 on pg 24-8 is incorrect

 

 

 

 

 

9

272353-001

31

Doc

Figure 25-1 on pg 25-1 has incorrect data

 

 

 

 

 

10

272353-001

31

Doc

Section 25.1.3 on page 25-2

 

 

 

 

 

11

272353-001

32

Doc

Figure 25-2 on pg 25-2 did not print correctly

 

 

 

 

 

12

272353-001

32

Doc

Table 25-2 on page 25-3 did not print completely

 

 

 

 

 

13

272353-001

33

Doc

Section 1.2.2 on page 1-2 has incorrect data

 

 

 

 

 

14

272353-001

33

Doc

Figure 12-2 on page 12-10 has incorrect data

 

 

 

 

 

15

272353-001

33

Doc

Section 19.1 on page 19-1 has incorrect data

 

 

 

 

 

16

272353-001

33

Doc

Table 14-46 on page 14-109 has missing data

 

 

 

 

 

17

272353-001

34

Doc

Section 13.2.4.3 on page 13-30 has incorrect data

 

 

 

 

 

18

272353-001

34

Doc

Figure 15-3 on page 15-7 has missing text

 

 

 

 

 

19

272353-001

34

Doc

Section 15.7.39 on page 15-100 has incorrect data

 

 

 

 

 

20

272353-001

35

Doc

Table 8-17 on page 8-38 has incorrect data

 

 

 

 

 

21

272353-001

35

Doc

Section 11.2.8 on page 11-5 has incorrect data

 

 

 

 

 

22

272353-001

35

Doc

Section 13.2.3.1 on page 13-13 has incorrect data

 

 

 

 

 

23

272353-001

35

Doc

Table 13-4 on page 13-9 has incorrect data

 

 

 

 

 

24

272353-001

36

Doc

Table 8-15 on page 8-36 needs clarification

 

 

 

 

 

25

272353-001

36

Doc

Table 13-13 on page 13-30 has incorrect data

 

 

 

 

 

26

272353-001

37

Doc

Section 13.2.4.3, First Paragraph after Table 13-13 has

Incorrect Data

 

 

 

 

 

 

 

 

 

27

272353-001

37

Doc

Section 13.2.4.3, First Paragraph after “Current” Figure

13-16. H-Matrix has Incorrect Data

 

 

 

 

 

 

 

 

 

28

272353-001

37

Doc

Section 11.3.1.5 FAIL# Code

 

 

 

 

 

29

272353-001

37

Doc

Section 13.5 Reset Conditions has Incorrect Data

 

 

 

 

 

30

272353-001

37

Doc

Section 13.2.4.2, First Sentence has Incorrect Data

 

 

 

 

 

31

272353-001

37

Doc

Section 13.6.2, Second Sentence has Incorrect Data

 

 

 

 

 

32

272358-007

38

Doc

Section 4.5.2 on page 50 is only correct for A-0 and A-1

steppings

 

 

 

 

 

 

 

 

 

33

272353-001

38

Doc

Section 17.5.1 on page 17-12 is only correct for A-0 and

A-1 steppings

 

 

 

 

 

 

 

 

 

Intel® 80303 and 80302 I/O Processors Specification Update

9

Identification Information

Identification Information

Markings

Topside Markings

 

GC80303

 

SSSSSS

 

MALAY

 

FFFFFFFF-[{SN}]

 

INTEL M © ‘2000

Intel®

80303 I/O Processor

Die Details

 

 

 

 

Intel®

 

 

 

QDF/

Voltage

i960® Core

 

Part Number

Stepping

Spec

Processor

Notes

(V)

 

 

Number

Speed

 

 

 

 

 

 

 

 

 

(MHz)

 

 

 

 

 

 

 

GC80303

A-0

Q176

3.3

100

Samples - limited testing

 

 

 

 

 

 

GC80303

A-0

Q196

3.3

100

Samples - limited testing

 

 

 

 

 

 

GC80303

A-1

Q189

3.3

100

Samples - limited testing

 

 

 

 

 

 

GC80303

A-1

SL4Q4

3.3

100

Production

 

 

 

 

 

 

 

 

 

 

 

Production - Yield

GC80303

A-2

SL57T

3.3

100

improvement only, no

 

 

 

 

 

functionality changes.

 

 

 

 

 

 

 

 

 

 

 

Samples - limited testing,

GC80302

A-2

Q229

3.3

100

66 MHz internal bus and

 

 

 

 

 

SDRAM memory interface.

 

 

 

 

 

 

 

 

 

 

 

Production - 66 MHz internal

GC80302

A-2

SL5HS

3.3

100

bus and SDRAM memory

 

 

 

 

 

interface.

 

 

 

 

 

 

10

Intel® 80303 and 80302 I/O Processors Specification Update

Identification Information

Device ID Registers

 

Processor

PCI-to-PCI

Address

Intel® i960® Core Processor

 

Translation Unit

Device and

Device ID

Bridge Unit

Revision ID

Device ID

Stepping

Register

Revision ID

Register

(DEVICEID - 0xFF00 8710)

 

(PDIDR - 0x1710)

(RIDR - 0x1008)

 

(ATURID - 0x1208)

 

 

 

 

 

 

 

 

 

 

80303 A-0

08879013

0x00

0x00

00823013

 

 

 

 

 

80303 A-1

18879013

0x01

0x01

00823013

 

 

 

 

 

80303 A-2

18879013

0x01

0x01

00823013

 

 

 

 

 

80302 A-2

18878013

0x01

0x01

00823013

 

 

 

 

 

NOTE: There are no functionality differences between the A-1 and A-2 steppings of the 80303. Therefore, the Device IDs are the same.

Intel® 80303 and 80302 I/O Processors Specification Update

11

Errata

Errata

1. Single-bit and Multi-bit Error Reporting Cannot Be Individually Enabled by ECC Control Register

Problem: The ECC Control Register ECCR is described as having the ability to select multi-bit error and/or single-bit error reporting (see Table 13-24 on page 13-31 of the Intel® 80303 I/O Processor Developer’s Manual). However, the algorithm does not allow individual enabling; that is, the reporting is either on or off for both multi-bit and single bit error reporting.

Implication: The error reporting selection (enabled or disabled) will apply to both multi-bit and single-bit errors.

Workaround: There is no current workaround. If either the ECCR.0 bit or the ECCR.1 bit is selected for reporting, then both multi-bit and single-bit error reporting are enabled. If neither bit is selected for reporting, then both multi-bit and single-bit error reporting are disabled.

Status: NoFix. See the Table “Summary Table of Changes” on page 7.

2. Instruction Sequence Can Scoreboard a Register Indefinitely

Problem: Register scoreboarding maintains register coherency by preventing parallel execution units from accessing registers for which there is an outstanding operation (see section 3.2.3 in the Intel® 80303 I/O Processor Developer’s Manual).

An instruction sequence that coincides with some specific instruction cache conditions can scoreboard a local or global register indefinitely. When this happens, processing can stall at the next access to that register, awaiting a scoreboard release that does not come. In that case, external bus accesses cease.

A hardware reset is the only way to release the scoreboard.

The following three conditions are required to scoreboard a register:

1.Execution of the following three-instruction sequence:

a.emul

b.ld, ldos, ldis, ldob, or ldib

c.mulo or muli

Only two-word, MEMB format load instructions that execute in two clock cycles cause the failure. Table 1 lists all the versions of these instructions that can produce this failure. Any version can be used for each instruction and still produce the failure as long as the sequential order is maintained.

2.The emul must appear at address 0xXXXXXXX8.

3.Instruction caching must be enabled. The emul instruction must be fetched from external memory along with the first word of the load instruction. Also, the second word of the load and the multiply instruction must already reside in cache. To accomplish this, the code must have run once in order to load the instructions into cache followed by code which causes the invalidation of the cache line containing the emul instruction. At this point, re-execution of the code sets up the failure condition.

Once the failure condition occurs, the processor will continue code execution until an instruction using the scoreboarded register is encountered, then indefinite processor stall will occur.

12

Intel® 80303 and 80302 I/O Processors Specification Update

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