Intel 80C188EA, 80L186EA, 80C186EA, 80L188EA User Manual

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80C186EA/80C188EA AND 80L186EA/80L188EA 16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS

Y80C186 Upgrade for Power Critical Applications

YFully Static Operation

YTrue CMOS Inputs and Outputs

YIntegrated Feature Set

ÐStatic 186 CPU Core

ÐPower Save, Idle and Powerdown Modes

ÐClock Generator

Ð2 Independent DMA Channels

Ð3 Programmable 16-Bit Timers

ÐDynamic RAM Refresh Control Unit

ÐProgrammable Memory and Peripheral Chip Select Logic

ÐProgrammable Wait State Generator

ÐLocal Bus Controller

ÐSystem-Level Testing Support (High Impedance Test Mode)

YSpeed Versions Available (5V):

Ð25 MHz (80C186EA25/80C188EA25)

Ð20 MHz (80C186EA20/80C188EA20)

Ð13 MHz (80C186EA13/80C188EA13)

YSpeed Versions Available (3V):

Ð13 MHz (80L186EA13/80L188EA13)

Ð8 MHz (80L186EA8/80L188EA8)

YDirect Addressing Capability to

1 Mbyte Memory and 64 Kbyte I/O

YSupports 80C187 Numeric Coprocessor Interface (80C186EA only)

YAvailable in the Following Packages:

Ð68-Pin Plastic Leaded Chip Carrier (PLCC)

Ð80-Pin EIAJ Quad Flat Pack (QFP)

Ð80-Pin Shrink Quad Flat Pack (SQFP)

YAvailable in Extended Temperature Range (b40§C to a85§C)

The 80C186EA is a CHMOS high integration embedded microprocessor. The 80C186EA includes all of the features of an ``Enhanced Mode'' 80C186 while adding the additional capabilities of Idle and Powerdown Modes. In Numerics Mode, the 80C186EA interfaces directly with an 80C187 Numerics Coprocessor.

272432 ± 1

*Other brands and names are the property of their respective owners.

Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of Intel products except as provided in Intel's Terms and Conditions of Sale for such products. Intel retains the right to make changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata.

October 1995

Order Number: 272432-003

COPYRIGHT © INTEL CORPORATION, 1995

1

 

80C186EA/80C188EA, 80L186EA/80L188EA

80C186EA/80C188EA AND 80L186EA/80L188EA

16-Bit High Integration Embedded Processor

CONTENTS

PAGE

INTRODUCTION ААААААААААААААААААААААААААА 4

80C186EA CORE ARCHITECTURE ААААААА 4

Bus Interface Unit АААААААААААААААААААААААААА 4

Clock Generator ААААААААААААААААААААААААААА 4

80C186EA PERIPHERAL

ARCHITECTURE АААААААААААААААААААААААА 5

Interrupt Control Unit ААААААААААААААААААААААА 5

Timer/Counter Unit АААААААААААААААААААААААА 5

DMA Control Unit АААААААААААААААААААААААААА 7

Chip-Select Unit АААААААААААААААААААААААААААА 7

Refresh Control Unit ААААААААААААААААААААААА 7

Power Management АААААААААААААААААААААААА 7

80C187 Interface (80C186EA Only) ААААААААА 8

ONCE Test Mode АААААААААААААААААААААААААА 8

DIFFERENCES BETWEEN THE

80C186XL AND THE 80C186EA АААААААА 8

Pinout Compatibility АААААААААААААААААААААААА 8

Operating Modes ААААААААААААААААААААААААААА 8

TTL vs CMOS Inputs ААААААААААААААААААААААА 8

Timing Specifications ААААААААААААААААААААААА 8

PACKAGE INFORMATION АААААААААААААААА 9

Prefix Identification ААААААААААААААААААААААААА 9

Pin Descriptions АААААААААААААААААААААААААААА 9

80C186EA Pinout ААААААААААААААААААААААААА 15

CONTENTS

PAGE

PACKAGE THERMAL

SPECIFICATIONS АААААААААААААААААААААА 20

ELECTRICAL SPECIFICATIONS ААААААААА 21

Absolute Maximum Ratings ААААААААААААААА 21

Recommended Connections АААААААААААААА 21

DC SPECIFICATIONS АААААААААААААААААААА 22

ICC versus Frequency and Voltage ААААААААА 24

PDTMR Pin Delay Calculation ААААААААААААА 24

AC SPECIFICATIONS АААААААААААААААААААА 25

AC CharacteristicsÐ80C186EA20/13 ААААА 25

AC CharacteristicsÐ80L186EA13/8 ААААААА 27

Relative Timings АААААААААААААААААААААААААА 29

AC TEST CONDITIONS АААААААААААААААААА 30

AC TIMING WAVEFORMS ААААААААААААААА 30

DERATING CURVES ААААААААААААААААААААА 33

RESET ААААААААААААААААААААААААААААААААААА 33

BUS CYCLE WAVEFORMS АААААААААААААА 36

EXECUTION TIMINGS ААААААААААААААААААА 43

INSTRUCTION SET SUMMARY АААААААААА 44

REVISION HISTORY ААААААААААААААААААААА 50

ERRATA ААААААААААААААААААААААААААААААААА 50

2

2

80C186EA/80C188EA, 80L186EA/80L188EA

272432 ± 2

NOTE:

Pin names in parentheses apply to the 80C186EA/80L188EA

Figure 1. 80C186EA/80C188EA Block Diagram

3

3

80C186EA/80C188EA, 80L186EA/80L188EA

INTRODUCTION

Unless specifically noted, all references to the 80C186EA apply to the 80C188EA, 80L186EA, and 80L188EA. References to pins that differ between the 80C186EA/80L186EA and the 80C188EA/ 80L188EA are given in parentheses. The ``L'' in the part number denotes low voltage operation. Physically and functionally, the ``C'' and ``L'' devices are identical.

The 80C186EA is the second product in a new generation of low-power, high-integration microprocessors. It enhances the existing 80C186XL family by offering new features and operating modes. The 80C186EA is object code compatible with the 80C186XL embedded processor.

The 80L186EA is the 3V version of the 80C186EA. The 80L186EA is functionally identical to the 80C186EA embedded processor. Current 80C186EA customers can easily upgrade their designs to use the 80L186EA and benefit from the reduced power consumption inherent in 3V operation.

The feature set of the 80C186EA/80L186EA meets the needs of low-power, space-critical applications. Low-power applications benefit from the static design of the CPU core and the integrated peripherals as well as low voltage operation. Minimum current consumption is achieved by providing a Powerdown Mode that halts operation of the device, and freezes the clock circuits. Peripheral design enhancements ensure that non-initialized peripherals consume little current.

Space-critical applications benefit from the integration of commonly used system peripherals. Two flexible DMA channels perform CPU-independent data transfers. A flexible chip select unit simplifies memory and peripheral interfacing. The interrupt unit provides sources for up to 128 external interrupts and will prioritize these interrupts with those generated from the on-chip peripherals. Three general purpose timer/counters round out the feature set of the 80C186EA.

Figure 1 shows a block diagram of the 80C186EA/ 80C188EA. The Execution Unit (EU) is an enhanced 8086 CPU core that includes: dedicated hardware to speed up effective address calculations, enhance execution speed for multiple-bit shift and rotate instructions and for multiply and divide instructions, string move instructions that operate at full bus bandwidth, ten new instructions, and static operation. The Bus Interface Unit (BIU) is the same as that found on the original 80C186 family products. An independent internal bus is used to allow communication between the BIU and internal peripherals.

4

80C186EA CORE ARCHITECTURE

Bus Interface Unit

The 80C186EA core incorporates a bus controller that generates local bus control signals. In addition, it employs a HOLD/HLDA protocol to share the local bus with other bus masters.

The bus controller is responsible for generating 20 bits of address, read and write strobes, bus cycle status information and data (for write operations) information. It is also responsible for reading data off the local bus during a read operation. SRDY and ARDY input pins are provided to extend a bus cycle beyond the minimum four states (clocks).

The local bus controller also generates two control signals (DEN and DT/R) when interfacing to external transceiver chips. This capability allows the addition of transceivers for simple buffering of the mulitplexed address/data bus.

Clock Generator

The processor provides an on-chip clock generator for both internal and external clock generation. The clock generator features a crystal oscillator, a divide- by-two counter, and two low-power operating modes.

The oscillator circuit is designed to be used with either a parallel resonant fundamental or third-over- tone mode crystal network. Alternatively, the oscillator circuit may be driven from an external clock source. Figure 2 shows the various operating modes of the oscillator circuit.

The crystal or clock frequency chosen must be twice the required processor operating frequency due to the internal divide-by-two counter. This counter is used to drive all internal phase clocks and the external CLKOUT signal. CLKOUT is a 50% duty cycle processor clock and can be used to drive other system components. All AC timings are referenced to CLKOUT.

The following parameters are recommended when choosing a crystal:

Temperature Range:

Application Specific

ESR (Equivalent Series Resistance):

60X max

C0 (Shunt Capacitance of Crystal):

7.0 pF max

CL (Load Capacitance):

 

20 pF g 2 pF

Drive Level:

 

2 mW max

4

80C186EA/80C188EA, 80L186EA/80L188EA

272432 ± 4

 

272432 ± 3

(A) Crystal Connection

(B) Clock Connection

NOTE:

The L1C1 network is only required when using a third-overtone crystal.

Figure 2. Clock Configurations

80C186EA PERIPHERAL ARCHITECTURE

The 80C186EA has integrated several common system peripherals with a CPU core to create a compact, yet powerful system. The integrated peripherals are designed to be flexible and provide logical interconnections between supporting units (e.g., the interrupt control unit supports interrupt requests from the timer/counters or DMA channels).

The list of integrated peripherals include:

#4-Input Interrupt Control Unit

#3-Channel Timer/Counter Unit

#2-Channel DMA Unit

#13-Output Chip-Select Unit

#Refresh Control Unit

#Power Management logic

The registers associated with each integrated periheral are contained within a 128 x 16 register file called the Peripheral Control Block (PCB). The PCB can be located in either memory or I/O space on any 256 byte address boundary.

Figure 3 provides a list of the registers associated with the PCB when the processor's Interrupt Control Unit is in Master Mode. In Slave Mode, the definitions of some registers change. Figure 4 provides register definitions specific to Slave Mode.

Interrupt Control Unit

The 80C186EA can receive interrupts from a number of sources, both internal and external. The Interrupt Control Unit (ICU) serves to merge these requests on a priority basis, for individual service by the CPU. Each interrupt source can be independently masked by the Interrupt Control Unit or all interrupts can be globally masked by the CPU.

Internal interrupt sources include the Timers and DMA channels. External interrupt sources come from the four input pins INT3:0. The NMI interrupt pin is not controlled by the ICU and is passed directly to the CPU. Although the timers only have one request input to the ICU, separate vector types are generated to service individual interrupts within the Timer Unit.

Timer/Counter Unit

The 80C186EA Timer/Counter Unit (TCU) provides three 16-bit programmable timers. Two of these are highly flexible and are connected to external pins for control or clocking. A third timer is not connected to any external pins and can only be clocked internally. However, it can be used to clock the other two timer channels. The TCU can be used to count external events, time external events, generate non-repeti- tive waveforms, generate timed interrupts, etc.

5

5

80C186EA/80C188EA, 80L186EA/80L188EA

PCB

Function

 

PCB

Function

 

PCB

Function

 

PCB

Function

Offset

 

Offset

 

Offset

 

Offset

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

00H

Reserved

 

40H

Reserved

 

80H

Reserved

 

C0H

DMA0 Src. Lo

 

 

 

 

 

 

 

 

 

 

 

02H

Reserved

 

42H

Reserved

 

82H

Reserved

 

C2H

DMA0 Src. Hi

 

 

 

 

 

 

 

 

 

 

 

04H

Reserved

 

44H

Reserved

 

84H

Reserved

 

C4H

DMA0 Dest. Lo

 

 

 

 

 

 

 

 

 

 

 

06H

Reserved

 

46H

Reserved

 

86H

Reserved

 

C6H

DMA0 Dest. Hi

 

 

 

 

 

 

 

 

 

 

 

08H

Reserved

 

48H

Reserved

 

88H

Reserved

 

C8H

DMA0 Count

 

 

 

 

 

 

 

 

 

 

 

0AH

Reserved

 

4AH

Reserved

 

8AH

Reserved

 

CAH

DMA0 Control

 

 

 

 

 

 

 

 

 

 

 

0CH

Reserved

 

4CH

Reserved

 

8CH

Reserved

 

CCH

Reserved

 

 

 

 

 

 

 

 

 

 

 

0EH

Reserved

 

4EH

Reserved

 

8EH

Reserved

 

CEH

Reserved

 

 

 

 

 

 

 

 

 

 

 

10H

Reserved

 

50H

Timer 0 Count

 

90H

Reserved

 

D0H

DMA1 Src. Lo

 

 

 

 

 

 

 

 

 

 

 

12H

Reserved

 

52H

Timer 0 Compare A

 

92H

Reserved

 

D2H

DMA1 Src. Hi

 

 

 

 

 

 

 

 

 

 

 

14H

Reserved

 

54H

Timer 0 Compare B

 

94H

Reserved

 

D4H

DMA1 Dest. Lo

 

 

 

 

 

 

 

 

 

 

 

16H

Reserved

 

56H

Timer 0 Control

 

96H

Reserved

 

D6H

DMA1 Dest. Hi

 

 

 

 

 

 

 

 

 

 

 

18H

Reserved

 

58H

Timer 1 Count

 

98H

Reserved

 

D8H

DMA1 Count

 

 

 

 

 

 

 

 

 

 

 

1AH

Reserved

 

5AH

Timer 1 Compare A

 

9AH

Reserved

 

DAH

DMA1 Control

 

 

 

 

 

 

 

 

 

 

 

1CH

Reserved

 

5CH

Timer 1 Compare B

 

9CH

Reserved

 

DCH

Reserved

 

 

 

 

 

 

 

 

 

 

 

1EH

Reserved

 

5EH

Timer 1 Control

 

9EH

Reserved

 

DEH

Reserved

 

 

 

 

 

 

 

 

 

 

 

20H

Reserved

 

60H

Timer 2 Count

 

A0H

UMCS

 

E0H

Refresh Base

 

 

 

 

 

 

 

 

 

 

 

22H

End of Interrupt

 

62H

Timer 2 Compare

 

A2H

LMCS

 

E2H

Refresh Time

 

 

 

 

 

 

 

 

 

 

 

24H

Poll

 

64H

Reserved

 

A4H

PACS

 

E4H

Refresh Control

 

 

 

 

 

 

 

 

 

 

 

26H

Poll Status

 

66H

Timer 2 Control

 

A6H

MMCS

 

E6H

Reserved

 

 

 

 

 

 

 

 

 

 

 

28H

Interrupt Mask

 

68H

Reserved

 

A8H

MPCS

 

E8H

Reserved

 

 

 

 

 

 

 

 

 

 

 

2AH

Priority Mask

 

6AH

Reserved

 

AAH

Reserved

 

EAH

Reserved

 

 

 

 

 

 

 

 

 

 

 

2CH

In-Service

 

6CH

Reserved

 

ACH

Reserved

 

ECH

Reserved

 

 

 

 

 

 

 

 

 

 

 

2EH

Interrupt Request

 

6EH

Reserved

 

AEH

Reserved

 

EEH

Reserved

 

 

 

 

 

 

 

 

 

 

 

30H

Interrupt Status

 

70H

Reserved

 

B0H

Reserved

 

F0H

Power-Save

 

 

 

 

 

 

 

 

 

 

 

32H

Timer Control

 

72H

Reserved

 

B2H

Reserved

 

F2H

Power Control

 

 

 

 

 

 

 

 

 

 

 

34H

DMA0 Int. Control

 

74H

Reserved

 

B4H

Reserved

 

F4H

Reserved

 

 

 

 

 

 

 

 

 

 

 

36H

DMA1 Int. Control

 

76H

Reserved

 

B6H

Reserved

 

F6H

Step ID

 

 

 

 

 

 

 

 

 

 

 

38H

INT0 Control

 

78H

Reserved

 

B8H

Reserved

 

F8H

Reserved

 

 

 

 

 

 

 

 

 

 

 

3AH

INT1 Control

 

7AH

Reserved

 

BAH

Reserved

 

FAH

Reserved

 

 

 

 

 

 

 

 

 

 

 

3CH

INT2 Control

 

7CH

Reserved

 

BCH

Reserved

 

FCH

Reserved

 

 

 

 

 

 

 

 

 

 

 

3EH

INT3 Control

 

7EH

Reserved

 

BEH

Reserved

 

FEH

Relocation

 

 

 

 

 

 

 

 

 

 

 

Figure 3. Peripheral Control Block Registers

6

6

PCB

Function

Offset

 

 

 

20H

Interrupt Vector

 

 

22H

Specific EOI

 

 

24H

Reserved

 

 

26H

Reserved

 

 

28H

Interrupt Mask

 

 

2AH

Priority Mask

 

 

2C

In-Service

 

 

2E

Interrupt Request

 

 

30

Interrupt Status

 

 

32

TMR0 Interrupt Control

 

 

34

DMA0 Interrupt Control

 

 

36

DMA1 Interrupt Control

 

 

38

TMR1 Interrupt Control

 

 

3A

TMR2 Interrupt Control

 

 

3C

Reserved

 

 

3E

Reserved

 

 

Figure 4. 80C186EA Slave Mode Peripheral

Control Block Registers

DMA Control Unit

The 80C186EA DMA Contol Unit provides two independent high-speed DMA channels. Data transfers can occur between memory and I/O space in any combination: memory to memory, memory to I/O, I/O to I/O or I/O to memory. Data can be transferred either in bytes or words. Transfers may proceed to or from either even or odd addresses, but even-aligned word transfers proceed at a faster rate. Each data transfer consumes two bus cycles (a minimum of eight clocks), one cycle to fetch data and the other to store data. The chip-select/ready logic may be programmed to point to the memory or I/O space subject to DMA transfers in order to provide hardware chip select lines. DMA cycles run at higher priority than general processor execution cycles.

80C186EA/80C188EA, 80L186EA/80L188EA

Chip-Select Unit

The 80C186EA Chip-Select Unit integrates logic which provides up to 13 programmable chip-selects to access both memories and peripherals. In addition, each chip-select can be programmed to automatically terminate a bus cycle independent of the condition of the SRDY and ARDY input pins. The chip-select lines are available for all memory and I/O bus cycles, whether they are generated by the CPU, the DMA unit, or the Refresh Control Unit.

Refresh Control Unit

The Refresh Control Unit (RCU) automatically generates a periodic memory read bus cycle to keep dynamic or pseudo-static memory refreshed. A 9-bit counter controls the number of clocks between refresh requests.

A 9-bit address generator is maintained by the RCU with the address presented on the A9:1 address lines during the refresh bus cycle. Address bits A19:13 are programmable to allow the refresh address block to be located on any 8 Kbyte boundary.

Power Management

The 80C186EA has three operational modes to control the power consumption of the device. They are Power Save Mode, Idle Mode, and Powerdown Mode.

Power Save Mode divides the processor clock by a programmable value to take advantage of the fact that current is linearly proportional to frequency. An unmasked interrupt, NMI, or reset will cause the 80C186EA to exit Power Save Mode.

Idle Mode freezes the clocks of the Execution Unit and the Bus Interface Unit at a logic zero state while all peripherals operate normally.

Powerdown Mode freezes all internal clocks at a logic zero level and disables the crystal oscillator. All internal registers hold their values provided VCC is maintained. Current consumption is reduced to transistor leakage only.

7

7

80C186EA/80C188EA, 80L186EA/80L188EA

80C187 Interface (80C186EA Only)

The 80C187 Numerics Coprocessor may be used to extend the 80C186EA instruction set to include floating point and advanced integer instructions. Connecting the 80C186EA RESOUT and TEST/ BUSY pins to the 80C187 enables Numerics Mode operation. In Numerics Mode, three of the four MidRange Chip Select (MCS) pins become handshaking pins for the interface. The exchange of data and control information proceeds through four dedicated I/O ports.

If an 80C187 is not present, the 80C186EA configures itself for regular operation at reset.

NOTE:

The 80C187 is not specified for 3V operation and therefore does not interface directly to the 80L186EA.

ONCE Test Mode

To facilitate testing and inspection of devices when fixed into a target system, the 80C186EA has a test mode available which forces all output and input/ output pins to be placed in the high-impedance state. ONCE stands for ``ON Circuit Emulation''. The ONCE mode is selected by forcing the UCS and LCS pins LOW (0) during a processor reset (these pins are weakly held to a HIGH (1) level) while RESIN is active.

DIFFERENCES BETWEEN THE 80C186XL AND THE 80C186EA

The 80C186EA is intended as a direct functional upgrade for 80C186XL designs. In many cases, it will be possible to replace an existing 80C186XL with little or no hardware redesign. The following sections describe differences in pinout, operating modes, and AC and DC specifications to keep in mind.

Pinout Compatibility

The 80C186EA requires a PDTMR pin to time the processor's exit from Powerdown Mode. The original pin arrangement for the 80C186XL in the PLCC package did not have any spare leads to use for PDTMR, so the DT/R pin was sacrificed. The arrangement of all the other leads in the 68-lead PLCC is identical between the 80C186XL and the 80C186EA. DT/R may be synthesized by latching the S1 status output. Therefore, upgrading a PLCC 80C186XL to PLCC 80C186EA is straightforward.

8

The 80-lead QFP (EIAJ) pinouts are different between the 80C186XL and the 80C186EA. In addition to the PDTMR pin, the 80C186EA has more power and ground pins and the overall arrangement of pins was shifted. A new circuit board layout for the 80C186EA is required.

Operating Modes

The 80C186XL has two operating modes, Compatible and Enhanced. Compatible Mode is a pin-to-pin replacement for the NMOS 80186, except for numerics coprocessing. In Enhanced Mode, the processor has a Refresh Control Unit, the Power-Save feature and an interface to the 80C187 Numerics Coprocessor. The MCS0, MCS1, and MCS3 pins change their functions to constitute handshaking pins for the 80C187.

The 80C186EA allows all non-80C187 users to use all the MCS pins for chip-selects. In regular operation, all 80C186EA features (including those of the Enhanced Mode 80C186) are present except for the interface to the 80C187. Numerics Mode disables the three chip-select pins and reconfigures them for connection to the 80C187.

TTL vs CMOS Inputs

The inputs of the 80C186EA are rated for CMOS switching levels for improved noise immunity, but the 80C186XL inputs are rated for TTL switching levels. In particular, the 80C186EA requires a minimum VIH of 3.5V to recognize a logic one while the 80C186XL requires a minimum VIH of only 1.9V (assuming 5.0V operation). The solution is to drive the 80C186EA with true CMOS devices, such as those from the HC and AC logic families, or to use pullup resistors where the added current draw is not a problem.

Timing Specifications

80C186EA timing relationships are expressed in a simplified format over the 80C186XL. The AC performance of an 80C186EA at a specified frequency will be very close to that of an 80C186XL at the same frequency. Check the timings applicable to your design prior to replacing the 80C186XL.

8

PACKAGE INFORMATION

This section describes the pins, pinouts, and thermal characteristics for the 80C186EA in the Plastic Leaded Chip Carrier (PLCC) package, Shrink Quad Flat Pack (SQFP), and Quad Flat Pack (QFP) package. For complete package specifications and information, see the Intel Packaging Outlines and Dimensions Guide (Order Number: 231369).

With the extended temperature range operational characteristics are guaranteed over a temperature range corresponding to b40§C to a85§C ambient. Package types are identified by a two-letter prefix to the part number. The prefixes are listed in Table 1.

Table 1. Prefix Identification

Prefix

Note

Package

Temperature

Type

Range

 

 

 

 

 

 

TN

 

PLCC

Extended

 

 

 

 

TS

 

QFP (EIAJ)

Extended

 

 

 

 

SB

1

SQFP

Extended/Commercial

 

 

 

 

N

1

PLCC

Commercial

 

 

 

 

S

1

QFP (EIAJ)

Commercial

 

 

 

 

NOTE:

1.The 25 MHz version is only available in commercial temperature range corresponding to 0§C to a70§C ambient.

Pin Descriptions

Each pin or logical set of pins is described in Table 3. There are three columns for each entry in the Pin Description Table.

The Pin Name column contains a mnemonic that describes the pin function. Negation of the signal name (for example, RESIN) denotes a signal that is active low.

The Pin Type column contains two kinds of information. The first symbol indicates whether a pin is power (P), ground (G), input only (I), output only (O) or

80C186EA/80C188EA, 80L186EA/80L188EA

input/output (I/O). Some pins have multiplexed functions (for example, A19/S6). Additional symbols indicate additional characteristics for each pin. Table 3 lists all the possible symbols for this column.

The Input Type column indicates the type of input (asynchronous or synchronous).

Asynchronous pins require that setup and hold times be met only in order to guarantee recognition at a particular clock edge. Synchronous pins require that setup and hold times be met to guarantee proper operation. For example, missing the setup or hold time for the SRDY pin (a synchronous input) will result in a system failure or lockup. Input pins may also be edgeor level-sensitive. The possible characteristics for input pins are S(E), S(L), A(E) and A(L).

The Output States column indicates the output state as a function of the device operating mode. Output states are dependent upon the current activity of the processor. There are four operational states that are different from regular operation: bus hold, reset, Idle Mode and Powerdown Mode. Appropriate characteristics for these states are also indicated in this column, with the legend for all possible characteristics in Table 2.

The Pin Description column contains a text description of each pin.

As an example, consider AD15:0. I/O signifies the pins are bidirectional. S(L) signifies that the input function is synchronous and level-sensitive. H(Z) signifies that, as outputs, the pins are high-imped- ance upon acknowledgement of bus hold. R(Z) signifies that the pins float during reset. P(X) signifies that the pins retain their states during Powerdown Mode.

9

9

80C186EA/80C188EA, 80L186EA/80L188EA

 

Table 2. Pin Description Nomenclature

 

 

Symbol

Description

 

 

P

Power Pin (Apply aVCC Voltage)

G

Ground (Connect to VSS)

I

Input Only Pin

O

Output Only Pin

I/O

Input/Output Pin

 

 

S(E)

Synchronous, Edge Sensitive

S(L)

Synchronous, Level Sensitive

A(E)

Asynchronous, Edge Sensitive

A(L)

Asynchronous, Level Sensitive

 

 

H(1)

Output Driven to VCC during Bus Hold

H(0)

Output Driven to VSS during Bus Hold

H(Z)

Output Floats during Bus Hold

H(Q)

Output Remains Active during Bus Hold

H(X)

Output Retains Current State during Bus Hold

 

 

R(WH)

Output Weakly Held at VCC during Reset

R(1)

Output Driven to VCC during Reset

R(0)

Output Driven to VSS during Reset

R(Z)

Output Floats during Reset

R(Q)

Output Remains Active during Reset

R(X)

Output Retains Current State during Reset

 

 

I(1)

Output Driven to VCC during Idle Mode

I(0)

Output Driven to VSS during Idle Mode

I(Z)

Output Floats during Idle Mode

I(Q)

Output Remains Active during Idle Mode

I(X)

Output Retains Current State during Idle Mode

 

 

P(1)

Output Driven to VCC during Powerdown Mode

P(0)

Output Driven to VSS during Powerdown Mode

P(Z)

Output Floats during Powerdown Mode

P(Q)

Output Remains Active during Powerdown Mode

P(X)

Output Retains Current State during Powerdown Mode

 

 

10

10

 

 

 

 

 

 

 

 

 

 

 

 

 

80C186EA/80C188EA, 80L186EA/80L188EA

 

 

 

 

 

 

 

 

 

Table 3. Pin Descriptions

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Pin

Pin

Input

Output

 

 

 

 

Description

 

 

Name

Type

Type

States

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VCC

P

 

 

POWER connections consist of six pins which must be shorted

 

 

 

 

 

 

 

 

 

externally to a VCC board plane.

VSS

G

 

 

GROUND connections consist of five pins which must be shorted

 

 

 

 

 

 

 

 

 

externally to a VSS board plane.

CLKIN

I

A(E)

 

CLocK INput is an input for an external clock. An external

 

 

 

 

 

 

 

 

 

oscillator operating at two times the required processor operating

 

 

 

 

 

 

 

 

 

frequency can be connected to CLKIN. For crystal operation,

 

 

 

 

 

 

 

 

 

CLKIN (along with OSCOUT) are the crystal connections to an

 

 

 

 

 

 

 

 

 

internal Pierce oscillator.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

OSCOUT

O

 

H(Q)

OSCillator OUTput is only used when using a crystal to generate

 

 

 

 

 

 

 

 

R(Q)

the external clock. OSCOUT (along with CLKIN) are the crystal

 

 

 

 

 

 

 

 

P(Q)

connections to an internal Pierce oscillator. This pin is not to be

 

 

 

 

 

 

 

 

 

used as 2X clock output for non-crystal applications (i.e., this pin is

 

 

 

 

 

 

 

 

 

N.C. for non-crystal applications). OSCOUT does not float in

 

 

 

 

 

 

 

 

 

ONCE mode.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CLKOUT

O

 

H(Q)

CLocK OUTput provides a timing reference for inputs and outputs

 

 

 

 

 

 

 

 

R(Q)

of the processor, and is one-half the input clock (CLKIN)

 

 

 

 

 

 

 

 

P(Q)

frequency. CLKOUT has a 50% duty cycle and transistions every

 

 

 

 

 

 

 

 

 

falling edge of CLKIN.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RESIN

I

A(L)

 

RESet IN causes the processor to immediately terminate any bus

 

 

 

 

 

 

 

 

 

cycle in progress and assume an initialized state. All pins will be

 

 

 

 

 

 

 

 

 

driven to a known state, and RESOUT will also be driven active.

 

 

 

 

 

 

 

 

 

The rising edge (low-to-high) transition synchronizes CLKOUT with

 

 

 

 

 

 

 

 

 

CLKIN before the processor begins fetching opcodes at memory

 

 

 

 

 

 

 

 

 

location 0FFFF0H.

 

 

 

 

 

 

 

 

 

 

 

 

RESOUT

O

 

H(0)

RESet OUTput that indicates the processor is currently in the

 

 

 

 

 

 

 

 

R(1)

reset state. RESOUT will remain active as long as RESIN remains

 

 

 

 

 

 

 

 

P(0)

 

active. When tied to the TEST/BUSY pin, RESOUT forces the

 

 

 

 

 

 

 

 

 

 

80C186EA into Numerics Mode.

 

 

 

 

 

 

 

 

 

 

 

 

PDTMR

I/O

A(L)

H(WH)

Power-Down TiMeR pin (normally connected to an external

 

 

 

 

 

 

 

 

R(Z)

capacitor) that determines the amount of time the processor waits

 

 

 

 

 

 

 

 

P(1)

after an exit from power down before resuming normal operation.

 

 

 

 

 

 

 

 

 

The duration of time required will depend on the startup

 

 

 

 

 

 

 

 

 

characteristics of the crystal oscillator.

 

 

 

 

 

 

 

 

 

 

 

 

NMI

I

A(E)

 

Non-Maskable Interrupt input causes a Type 2 interrupt to be

 

 

 

 

 

 

 

 

 

serviced by the CPU. NMI is latched internally.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TEST/BUSY

I

A(E)

 

TEST/BUSY is sampled upon reset to determine whether the

 

 

 

 

 

 

 

80C186EA is to enter Numerics Mode. In regular operation, the pin

 

(TEST)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

is TEST. TEST is used during the execution of the WAIT

 

 

 

 

 

 

 

 

 

instruction to suspend CPU operation until the pin is sampled

 

 

 

 

 

 

 

 

 

active (low). In Numerics Mode, the pin is BUSY. BUSY notifies the

 

 

 

 

 

 

 

 

 

80C186EA of 80C187 Numerics Coprocessor activity.

 

 

 

 

 

AD15:0

I/O

S(L)

H(Z)

These pins provide a multiplexed Address and Data bus. During

(AD7:0)

 

 

R(Z)

the address phase of the bus cycle, address bits 0 through 15 (0

 

 

 

 

 

 

 

 

P(X)

through 7 on the 8-bit bus versions) are presented on the bus and

 

 

 

 

 

 

 

 

 

can be latched using ALE. 8- or 16-bit data information is

 

 

 

 

 

 

 

 

 

transferred during the data phase of the bus cycle.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

NOTE:

Pin names in parentheses apply to the 80C188EA and 80L188EA.

11

11

80C186EA/80C188EA, 80L186EA/80L188EA

Table 3. Pin Descriptions (Continued)

 

 

 

 

 

Pin

Pin

Input

Output

 

 

 

 

 

 

 

 

 

 

 

Description

 

 

 

Name

Type

Type

States

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A18:16

O

 

H(Z)

These pins provide multiplexed Address during the address

 

A19/S6 ± A16

 

 

R(Z)

phase of the bus cycle. Address bits 16 through 19 are

 

(A19 ± A8)

 

 

P(X)

presented on these pins and can be latched using ALE.

 

 

 

A18:16 are driven to a logic 0 during the data phase of the bus

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

cycle. On the 8-bit bus versions, A15 ± A8 provide valid address

 

 

 

 

 

 

 

 

 

 

 

information for the entire bus cycle. Also during the data

 

 

 

 

 

 

 

 

 

 

 

phase, S6 is driven to a logic 0 to indicate a CPU-initiated bus

 

 

 

 

 

 

 

 

 

 

 

cycle or logic 1 to indicate a DMA-initiated bus cycle or a

 

 

 

 

 

 

 

 

 

 

 

refresh cycle.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

S2:0

O

 

H(Z)

Bus cycle Status are encoded on these pins to provide bus

 

 

 

 

 

 

 

 

 

 

R(Z)

transaction information. S2:0 are encoded as follows:

 

 

 

 

 

 

 

 

 

 

P(1)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

S2

 

S1

 

S0

Bus Cycle Initiated

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

 

0

 

0

 

 

Interrupt Acknowledge

 

 

 

 

 

 

 

 

 

 

 

0

 

0

 

1

 

 

Read I/O

 

 

 

 

 

 

 

 

 

 

 

0

 

1

 

0

 

 

Write I/O

 

 

 

 

 

 

 

 

 

 

 

0

 

1

 

1

 

 

Processor HALT

 

 

 

 

 

 

 

 

 

 

 

1

 

0

 

0

 

 

Queue Instruction Fetch

 

 

 

 

 

 

 

 

 

 

 

1

 

0

 

1

 

 

Read Memory

 

 

 

 

 

 

 

 

 

 

 

1

 

1

 

0

 

 

Write Memory

 

 

 

 

 

 

 

 

 

 

 

1

 

1

 

1

 

 

Passive (no bus activity)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ALE/QS0

O

 

H(0)

Address Latch Enable output is used to strobe address

 

 

 

 

 

 

 

 

 

 

R(0)

information into a transparent type latch during the address

 

 

 

 

 

 

 

 

 

 

P(0)

phase of the bus cycle. In Queue Status Mode, QS0 provides

 

 

 

 

 

 

 

 

 

 

queue status information along with QS1.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BHE

O

 

H(Z)

Byte High Enable output to indicate that the bus cycle in

 

 

 

 

 

 

 

 

 

 

progress is transferring data over the upper half of the data

 

(RFSH)

 

 

R(Z)

 

 

 

 

 

 

 

 

 

 

P(X)

bus. BHE and A0 have the following logical encoding:

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A0

BHE

Encoding (For 80C186EA/80L186EA Only)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

 

 

0

 

 

Word Transfer

 

 

 

 

 

 

 

 

 

 

 

 

 

0

 

 

1

 

 

Even Byte Transfer

 

 

 

 

 

 

 

 

 

 

 

 

 

1

 

 

0

 

 

Odd Byte Transfer

 

 

 

 

 

 

 

 

 

 

 

 

 

1

 

 

1

 

 

Refresh Operation

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

On the 80C188EA/80L188EA, RFSH is asserted low to

 

 

 

 

 

 

 

 

 

 

 

indicate a Refresh bus cycle.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RD/QSMD

O

 

H(Z)

ReaD output signals that the accessed memory or I/O device

 

 

 

 

 

 

 

 

 

 

R(WH)

must drive data information onto the data bus. Upon reset, this

 

 

 

 

 

 

 

 

 

 

P(1)

pin has an alternate function. As QSMD, it enables Queue

 

 

 

 

 

 

 

 

 

 

Status Mode when grounded. In Queue Status Mode, the

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ALE/QS0 and WR/QS1 pins provide the following information

 

 

 

 

 

 

 

 

 

 

 

about processor/instruction queue interaction:

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

QS1

 

QS0

 

Queue Operation

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

 

 

0

 

 

No Queue Operation

 

 

 

 

 

 

 

 

 

 

 

 

 

0

 

 

1

 

 

First Opcode Byte Fetched from the Queue

 

 

 

 

 

 

 

 

 

 

 

 

 

1

 

 

1

 

 

Subsequent Byte Fetched from the Queue

 

 

 

 

 

 

 

 

 

 

 

 

 

1

 

 

0

 

 

Empty the Queue

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

NOTE:

Pin names in parentheses apply to the 80C188EA and 80L188EA.

12

12

 

 

 

 

 

 

 

 

 

 

 

 

80C186EA/80C188EA, 80L186EA/80L188EA

 

 

 

 

 

 

 

 

 

 

 

Table 3. Pin Descriptions (Continued)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Pin

Pin

Input

Output

Description

 

Name

Type

Type

States

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

WR/QS1

O

 

H(Z)

WRite output signals that data available on the data bus are to be

 

 

 

 

 

 

 

 

 

 

 

R(Z)

written into the accessed memory or I/O device. In Queue Status

 

 

 

 

 

 

 

 

 

 

 

P(1)

Mode, QS1 provides queue status information along with QS0.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ARDY

I

A(L)

 

Asychronous ReaDY is an input to signal for the end of a bus cycle.

 

 

 

 

 

 

 

 

 

 

S(L)

 

ARDY is asynchronous on rising CLKOUT and synchronous on falling

 

 

 

 

 

 

 

 

 

 

 

 

CLKOUT. ARDY or SRDY must be active to terminate any processor

 

 

 

 

 

 

 

 

 

 

 

 

bus cycle, unless they are ignored due to correct programming of the

 

 

 

 

 

 

 

 

 

 

 

 

Chip Select Unit.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SRDY

I

S(L)

 

Synchronous ReaDY is an input to signal for the end of a bus cycle.

 

 

 

 

 

 

 

 

 

 

 

 

ARDY or SRDY must be active to terminate any processor bus cycle,

 

 

 

 

 

 

 

 

 

 

 

 

unless they are ignored due to correct programming of the Chip Select

 

 

 

 

 

 

 

 

 

 

 

 

Unit.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DEN

O

H(Z)

 

Data ENable output to control the enable of bidirectional transceivers

 

 

 

 

 

 

 

 

 

 

R(Z)

 

when buffering a system. DEN is active only when data is to be

 

 

 

 

 

 

 

 

 

 

P(1)

 

transferred on the bus.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DT/R

O

 

H(Z)

Data Transmit/Receive output controls the direction of a bi-

 

 

 

 

 

 

 

 

 

 

 

R(Z)

directional buffer in a buffered system. DT/R is only available on the

 

 

 

 

 

 

 

 

 

 

 

P(X)

QFP (EIAJ) package and the SQFP package.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

LOCK

O

 

H(Z)

LOCK output indicates that the bus cycle in progress is not to be

 

 

 

 

 

 

 

 

 

 

 

R(WH)

interrupted. The processor will not service other bus requests (such

 

 

 

 

 

 

 

 

 

 

 

P(1)

as HOLD) while LOCK is active. This pin is configured as a weakly

 

 

 

 

 

 

 

 

 

 

 

 

held high input while RESIN is active and must not be driven low.

 

 

 

 

 

 

 

 

 

 

 

HOLD

I

A(L)

 

HOLD request input to signal that an external bus master wishes to

 

 

 

 

 

 

 

 

 

 

 

 

gain control of the local bus. The processor will relinquish control of

 

 

 

 

 

 

 

 

 

 

 

 

the local bus between instruction boundaries not conditioned by a

 

 

 

 

 

 

 

 

 

 

 

 

LOCK prefix.

 

 

 

 

 

 

 

 

 

 

 

HLDA

O

 

H(1)

HoLD Acknowledge output to indicate that the processor has

 

 

 

 

 

 

 

 

 

 

 

R(0)

relinquished control of the local bus. When HLDA is asserted, the

 

 

 

 

 

 

 

 

 

 

 

P(0)

processor will (or has) floated its data bus and control signals allowing

 

 

 

 

 

 

 

 

 

 

 

 

another bus master to drive the signals directly.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

UCS

O

 

H(1)

Upper Chip Select will go active whenever the address of a memory

 

 

 

 

 

 

 

 

 

 

 

R(1)

or I/O bus cycle is within the address limitations programmed by the

 

 

 

 

 

 

 

 

 

 

 

P(1)

user. After reset, UCS is configured to be active for memory accesses

 

 

 

 

 

 

 

 

 

 

 

 

between 0FFC00H and 0FFFFFH. During a processor reset, UCS and

 

 

 

 

 

 

 

 

 

 

 

 

LCS are used to enable ONCE Mode.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

LCS

O

 

H(1)

Lower Chip Select will go active whenever the address of a memory

 

 

 

 

 

 

 

 

 

 

 

R(1)

bus cycle is within the address limitations programmed by the user.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P(1)

LCS is inactive after a reset. During a processor reset, UCS and LCS

 

 

 

 

 

 

 

 

 

 

 

 

are used to enable ONCE Mode.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

NOTE:

Pin names in parentheses apply to the 80C188EA and 80L188EA.

13

13

80C186EA/80C188EA, 80L186EA/80L188EA

Table 3. Pin Descriptions (Continued)

 

 

 

 

Pin

Pin

Input

Output

Description

 

Name

Type

Type

States

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MCS0/PEREQ

I/O

A(L)

H(1)

These pins provide a multiplexed function. If enabled,

 

 

 

 

 

 

 

 

 

 

 

 

 

 

these pins normally comprise a block of Mid-Range Chip

 

MCS1/ERROR

 

 

R(1)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Select outputs which will go active whenever the address

 

MCS2

 

 

 

 

 

P(1)

 

 

 

of a memory bus cycle is within the address limitations

 

MCS3/NCS

 

 

 

 

 

 

 

programmed by the user. In Numerics Mode (80C186EA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

only), three of the pins become handshaking pins for the

 

 

 

 

 

 

 

 

 

 

 

 

 

 

80C187. The CoProcessor REQuest input signals that a

 

 

 

 

 

 

 

 

 

 

 

 

 

 

data transfer is pending. ERROR is an input which

 

 

 

 

 

 

 

 

 

 

 

 

 

 

indicates that the previous numerics coprocessor

 

 

 

 

 

 

 

 

 

 

 

 

 

 

operation resulted in an exception condition. An interrupt

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type 16 is generated when ERROR is sampled active at

 

 

 

 

 

 

 

 

 

 

 

 

 

 

the beginning of a numerics operation. Numerics

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Coprocessor Select is an output signal generated when

 

 

 

 

 

 

 

 

 

 

 

 

 

 

the processor accesses the 80C187.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PCS4:0

O

 

H(1)

Peripheral Chip Selects go active whenever the address

 

 

 

 

 

 

 

 

 

 

 

 

 

R(1)

of a memory or I/O bus cycle is within the address

 

 

 

 

 

 

 

 

 

 

 

 

 

P(1)

limitations programmed by the user.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PCS5/A1

O

 

H(1)/H(X)

These pins provide a multiplexed function. As additional

 

 

 

 

 

 

 

 

 

Peripheral Chip Selects, they go active whenever the

 

PCS6/A2

 

 

R(1)

 

 

 

 

 

 

 

 

 

 

 

 

 

P(1)

address of a memory or I/O bus cycle is within the

 

 

 

 

 

 

 

 

 

 

 

 

 

address limitations by the user. They may also be

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

programmed to provide latched Address A2:1 signals.

 

 

 

 

 

 

 

 

 

 

T0OUT

O

 

H(Q)

Timer OUTput pins can be programmed to provide a

 

T1OUT

 

 

R(1)

single clock or continuous waveform generation,

 

 

 

 

 

 

 

 

 

 

 

 

 

P(Q)

depending on the timer mode selected.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

T0IN

I

A(L)

 

Timer INput is used either as clock or control signals,

 

T1IN

 

A(E)

 

depending on the timer mode selected.

 

 

 

 

 

 

 

 

 

 

DRQ0

I

A(L)

 

DMA ReQuest is asserted by an external request when it

 

DRQ1

 

 

 

is prepared for a DMA transfer.

 

 

 

 

 

 

 

 

 

 

INT0

 

 

I

A(E,L)

 

Maskable INTerrupt input will cause a vector to a specific

 

INT1/SELECT

 

 

 

Type interrupt routine. To allow interrupt expansion, INT0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

and/or INT1 can be used with INTA0 and INTA1 to

 

 

 

 

 

 

 

 

 

 

 

 

 

 

interface with an external slave controller. INT1 becomes

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SELECT when the ICU is configured for Slave Mode.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

INT2/INTA0

I/O

A(E,L)

H(1)

These pins provide multiplexed functions. As inputs, they

 

 

 

 

 

 

 

provide a maskable INTerrupt that will cause the CPU to

 

INT3/INTA1/IRQ

 

 

R(Z)

 

 

 

 

 

 

 

 

 

 

 

 

 

P(1)

vector to a specific Type interrupt routine. As outputs,

 

 

 

 

 

 

 

 

 

 

 

 

 

each is programmatically controlled to provide an

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

INTerrupt Acknowledge handshake signal to allow

 

 

 

 

 

 

 

 

 

 

 

 

 

 

interrupt expansion. INT3/INTA1 becomes IRQ when the

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ICU is configured for Slave Mode.

 

 

 

 

 

 

 

N.C.

 

 

 

No Connect. For compatibility with future products, do not

 

 

 

 

 

 

 

 

 

 

 

 

 

 

connect to these pins.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

NOTE:

Pin names in parentheses apply to the 80C188EA and 80L188EA.

14

14

80C186EA PINOUT

Tables 4 and 5 list the 80C186EA pin names with package location for the 68-pin Plastic Leaded Chip Carrier (PLCC) component. Figure 9 depicts the complete 80C186EA/80L186EA pinout (PLCC package) as viewed from the top side of the component (i.e., contacts facing down).

Tables 6 and 7 list the 80C186EA pin names with package location for the 80-pin Quad Flat Pack (EIAJ) component. Figure 6 depicts the complete

80C186EA/80C188EA, 80L186EA/80L188EA

80C186EA/80C188EA (EIAJ QFP package) as viewed from the top side of the component (i.e., contacts facing down).

Tables 8 and 9 list the 80C186EA/80C188EA pin names with package location for the 80-pin Shrink Quad Flat Pack (SQFP) component. Figure 7 depicts the complete 80C186EA/80C188EA (SQFP) as viewed from the top side of the component (i.e., contacts facing down).

Table 4. PLCC Pin Names with Package Location

Address/Data Bus

 

 

 

 

 

 

 

 

Bus Control

 

 

Processor Control

 

 

 

 

 

 

I/O

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Name

Location

 

 

 

 

Name

Location

 

 

Name

Location

 

 

 

Name

Location

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

AD0

17

 

 

ALE/QS0

61

 

RESIN

24

 

UCS

34

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

AD1

15

 

 

BHE (RFSH)

64

 

RESOUT

57

 

LCS

33

AD2

13

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

52

 

CLKIN

59

 

MCS0/PEREQ

38

 

 

S0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

AD3

11

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

OSCOUT

58

 

MCS1/ERROR

37

 

 

S1

53

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

AD4

8

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MCS2

36

 

 

S2

54

 

CLKOUT

56

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

AD5

6

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MCS3/NCS

35

 

 

RD/QSMD

62

 

TEST/BUSY

47

AD6

4

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PCS0

25

 

 

WR/QS1

63

 

PDTMR

40

 

 

 

 

 

 

 

AD7

2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ARDY

55

 

 

PCS1

27

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

NMI

46

 

AD8 (A8)

16

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PCS2

28

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SRDY

49

 

 

 

 

 

 

 

 

 

 

 

 

 

 

INT0

45

 

AD9 (A9)

14

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PCS3

29

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

AD10 (A10)

12

 

 

DEN

39

 

INT1/SELECT

44

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PCS4

30

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

AD11 (A11)

10

 

 

LOCK

48

 

INT2/INTA0

42

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PCS5/A1

31

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

AD12 (A12)

7

 

 

HOLD

50

 

INT3/INTA1/

41

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PCS6/A2

32

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

IRQ

 

 

AD13 (A13)

5

 

 

HLDA

51

 

 

 

T0OUT

22

 

 

 

 

 

 

 

 

 

 

 

AD14 (A14)

3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

T0IN

20

AD15 (A15)

1

 

 

 

 

 

 

 

 

 

Power

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

T1OUT

23

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A16

68

 

 

Name

 

 

 

Location

 

 

 

 

 

 

 

 

 

T1IN

21

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A17

67

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DRQ0

18

 

 

VSS

 

 

 

26, 60

 

 

 

 

 

 

 

 

 

A18

66

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DRQ1

19

A19/S6

65

 

 

VCC

 

 

 

9, 43

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

NOTE:

Pin names in parentheses apply to the 80C188EA/80L188EA.

15

15

+ 35 hidden pages