Intel® 7500, 7510, and 7512
Scalable Memory Buffer
Thermal/Mechanical Design Guidelines
April 2011
Reference Number: 322828-002
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BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS
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reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future
changes to them.
The Intel 7500, 7510, and 7512 Scalable Memory Buffer may contain design defects or errors known as errata, which may cause
the product to deviate from published specifications. Current characterized errata are available upon request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an order number and are referenced in this document, or other Intel literature may be obtained
4Intel® 7500, 7510, and 7512 Scalable Memory Buffer TMDG
Revision History
RevisionDescriptionDate
001Initial Release April 2010
• Added product specifications for Intel 7510 and 7512 Scalable Memory
buffer
• Replaced reference to ‘Intel 7500 Scalable Memory Buffer’ with
‘components’ where guidance also applies to Intel 7510 and 7512 Scalable
002
Memory Buffer. See change bars throughout document.
• Section 2: Revised the figures title
• Section 3.1: Reworded the paragraph
• Table 3-1: Updated the table
• Table 3-2: Added note 6
§
April 2011
Intel® 7500, 7510, and 7512 Scalable Memory Buffer TMDG5
6Intel® 7500, 7510, and 7512 Scalable Memory Buffer TMDG
Introduction
1Introduction
As the complexity of computer systems increases, so do the power dissipation
requirements. Care must be taken to ensure that the additional power is properly
dissipated. Typical methods to improve heat dissipation include selective use of
ducting, and/or passive heatsinks.
Note:This document addresses thermal design and specifications for the Intel® 7500, 7510,
and 7512 Scalable Memory Buffer. Information provided in this document is intended
only for use with these products. Unless otherwise specified, specification and guidance
provided in this document applies to products identified above. In this document the
term ‘component’ refer to Intel 7500, 7510, and 7512 Scalable Memory Buffer
components unless other wise identified.
The goals of this document are to:
• Outline the mechanical operating limits and specifications for the Intel® 7500,
7510, and 7512 Scalable Memory Buffer (MB).
• Outline reference TDP specifications for the Intel 7500, 7510, and 7512 Scalable
Memory Buffer specific to that of Intel® Xeon® processor 7500 series-based
platform and Intel® Itanium® processor 9300 series-based platform.
• Describe reference thermal solutions that meet the specifications of the Intel 7500,
7510, and 7512 Scalable Memory Buffer.
Properly designed thermal solutions provide adequate cooling to maintain the
component die temperature at or below thermal specifications. This is accomplished by
providing a low local-ambient temperature, ensuring adequate local airflow, and
minimizing the die to local-ambient thermal resistance. By maintaining the memory
buffer component die temperature at or below the specified limits, a system designer
can ensure the proper functionality, performance, and reliability of the chipset.
Operation outside the functional limits can degrade system performance and may
cause permanent changes in the operating characteristics of the component.
The simplest and most cost-effective method to improve the inherent system cooling
characteristics is through proper chassis design and placement of fans, vents, and
ducts. When additional cooling is required, component thermal solutions may be
implemented in conjunction with system thermal solutions. The size of the fan or
heatsink can be varied to balance size and space constraints with acoustic noise.
1.1Design Flow
To develop a reliable, cost-effective thermal solution, several tools have been provided
to the system designer. Figure 1-1 illustrates the design process implicit to this
document and the tools appropriate for each step.
Intel® 7500, 7510, and 7512 Scalable Memory Buffer TMDG7
Figure 1-1.Thermal Design Process
Step 1 : T herm al
Sim ulation
The rm al M od el
The rm al M od el U se r's G uide
Step 2 : H ea tsink S elec tion
1.2Definition of Terms
FC-BGAFlip Chip Ball Grid Array. A package type defined by a plastic substrate where
a die is mounted using an underfill C4 (Controlled Collapse Chip Connection)
attach style. The primary electrical interface is an array of solder balls
attached to the substrate opposite the die. Note that the device arrives at
the customer with solder balls attached.
BLTBond Line Thickness. Final settled thickness of the thermal interface
material after installation of heatsink.
MBIntel 7500 Scalable Memory Buffer. The chipset component responsible for
handling Intel® Scalable Memory Interconnect (Intel®SMI) channel and
memory requests to and from the local DIMM. All memory control for the
DRAM resides in the host, including memory request initiation, timing,
refresh, scrubbing, sparing, configuration access, and power management.
T
case_max
T
case_min
TDPThermal design power: Thermal solutions should be designed to dissipate
Maximum die operating temperature, and is measured at the geometric
center of the top of the die.
Minimum die operating temperature, and is measured at the geometric
center of the top of the die.
this target power level. TDP is not the maximum power that the chipset can
dissipate.
Introduction
The rm al R eferen ce
Me cha nical R efe renc e
S tep 3 : T herm al V alida tion
The rm al T es ting S oftware
So ftw a re Us e r's Gu ide
8Intel® 7500, 7510, and 7512 Scalable Memory Buffer TMDG
Introduction
1.3Reference Documents
The reader of this specification should also be familiar with material and concepts
presented in the following documents:
• Intel® 7500, 7510, and 7512 Scalable Memory Buffer Datasheet
• Various system thermal design suggestions (http://www.formfactors.org)
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Intel® 7500, 7510, and 7512 Scalable Memory Buffer TMDG9
Introduction
10Intel® 7500, 7510, and 7512 Scalable Memory Buffer TMDG
Packaging Technology
19.50mm.
2Packaging Technology
The Intel 7500, 7510, and 7512 Scalable Memory Buffer components uses a 24.5 mm x
19.5 mm, 12-layer FC-BGA package (see Figure 2-1, Figure 2-2 and Figure 2-3).
2.All dimensions are tolerances confirm to ANSI Y14.5M-1994.
12Intel® 7500, 7510, and 7512 Scalable Memory Buffer TMDG
Packaging Technology
2.1Package Mechanical Requirements
The component package has an exposed bare die which is capable of sustaining a
maximum static normal load of 15 lbf. The package is NOT capable of sustaining a
dynamic or static compressive load applied to any edge of the bare die. These
mechanical load limits must not be exceeded during heatsink installation, mechanical
stress testing, standard shipping conditions and/or any other use condition.
Notes:
1. The heatsink attach solutions must not include continuous stress onto the chipset
package with the exception of a uniform load to maintain the heatsink-to-package
thermal interface.
2. These specifications apply to uniform compressive loading in a direction
perpendicular to the bare die top surface.
3. These specifications are based on limited testing for design characterization.
Loading limits are for the package only.
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Intel® 7500, 7510, and 7512 Scalable Memory Buffer TMDG13
Packaging Technology
14Intel® 7500, 7510, and 7512 Scalable Memory Buffer TMDG
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