Frequency Range87.5–108.0MHz
Usable SensitivityIHF 1.3μV/13.2dBf
Signal-to-Noise RatioMono/Stereo 70/68dB
DistortionMono/Stereo 0.2/0.3%
Stereo Separation40dB @ 1kHz
Selectivity±400kHz, 70dB
Image Rejection80dB
IF Rejection90dB
AM Tuner Section
Frequency Range520–1720kHz
Signal-to-Noise Ratio45dB
Usable SensitivityLoop 500μV
Distortion1kHz, 50% Mod 0.8%
Selectivity±10kHz, 30dB
Video Section
Television FormatNTSC
Input Level/Impedance1Vp-p/75 ohms
Output Level/Impedance1Vp-p/75 ohms
Video Frequency Response
(Composite and S-Video)10Hz–8MHz (–3dB)
Video Frequency Response
(Component Video) 10Hz–50MHz (–3dB)
General
Power RequirementAC 120V/60Hz
Power Consumption65W idle, 540W maximum
Depth measurement includes knobs, buttons and terminal connections.
Height measurement includes feet and chassis.
All features and specifications are subject to change without notice.
Harman Kardon and Power for the Digital Revolution are registered trademarks of
Harman International Industries, Incorporated.
* Manufactured under license from Dolby Laboratories. “Dolby,” “Pro Logic” and the Double-D symbol
are trademarks of Dolby Laboratories.
DTS, DTS Surround, DTS-ES and DTS Neo:6 are registered trademarks of Digital Theater Systems, Inc.
VMAx is a registered trademark of Harman International Industries, Incorporated, and is an
implementation of Cooper Bauck Transaural Stereo under patent license.
Logic 7 is a registered trademark of Harman International Industries, Incorporated.
Cirrus is a registered trademark of Cirrus Logic, Inc.
46 TECHNICAL SPECIFICATIONS
SAFETY PRECAUTIONS
The following check should be performed for the continued
protection of the customer and service technician.
LEAKAGE CURRENT CHECK
Measure leakage current to a known earth ground (water
pipe, conduit, etc.) by connecting a leakage current tester
between the earth ground and all exposed metal parts of the
appliance (input/output terminals, screwheads, metal
overlays, control shaft, etc.). Plug the AC line cord of the
appliance directly into a 250V AC 50Hz outlet and turn the
AC power switch on. Any current measured must not exceed
o.5mA.
Reading should
not be above
0.5mA
Earth
ground
Device
under
test
Test all
exposed metal
surfaces
Also test with
plug reversed
(Using AC adapter
plug as required)
Leakage
current
tester
AC Leakage Test
ANY MEASUREMENTS NOT WITHIN THE LIMITS
OUTLINED ABOVE ARE INDICATIVE OF A
POTENTIAL SHOCK HAZARD AND MUST BE
CORRECTED BEFORE RETURNING THE APPLIANCE
TO THE CUSTOMER.
OPERATION
Surround Mode Chart
MODEFEATURES
Dolby DigitalAvailable only with digital input sources encoded with Dolby Digital data. It provides up to five separate main audio channels and
a special dedicated Low-Frequency Effects channel.
Dolby Digital EXAvailable when the receiver is configured for 6.1/7.1-channel operation, Dolby Digital EX is the latest version of Dolby Digital. When used with
movies or other programs that have special encoding, Dolby Digital EX reproduces specially encoded soundtracks so that a full 6.1/7.1 sound field is
available. When the receiver is set for 6.1/7.1 operation and a Dolby Digital signal is present, the EX mode is automatically selected. Even if specific
EX encoding is not available to provide the additional channel, the special algorithms will derive a 6.1/7.1 output.
DTS 5.1When the speaker configuration is set for 5.1-channel operation, the DTS 5.1 mode is available when DVD, audio-only music or laser discs encoded
with DTS data are played. DTS 5.1 provides up to five separate main audio channels and a special dedicated low-frequency channel.
DTS-ES 6.1 MatrixWhen the speaker configuration is set for 6.1/7.1 operation, playback of a DTS-encoded program source will automatically trigger the selection
DTS-ES 6.1 Discreteof one of the two DTS-ES modes. Newer discs with special DTS-ES discrete encoding will be decoded to provide six discrete, full-bandwidth
channels plus a separate low-frequency channel. All other DTS discs will be decoded using the DTS-ES Matrix mode, which creates a 6.1-channel
sound field from the original 5.1-channel soundtrack.
Dolby Pro Logic IIDolby Pro Logic II is the latest version of Dolby Laboratory’s benchmark surround technology that decodes full-range, discrete left, center right,
Movieright surround and left surround channels from either matrix surround-encoded programs and conventional stereo sources when an analog input
Musicis in use. The Dolby Pro Logic II Movie mode is optimized for movie soundtracks, while the Pro Logic II Music mode should be used with
Pro Logicmusical selections. The Pro Logic mode activates original Pro Logic processing for those who prefer that presentation.
Logic 7 CinemaExclusive to Harman Kardon for A/V receivers, Logic 7 is an advanced mode that extracts the maximum surround information from either
Logic 7 Musicsurround-encoded programs or conventional stereo material. Depending on the number of speakers in use and the selection made in the
Logic 7 Enhance
DTS Neo:6 CinemaThese two modes are available when any analog source is playing to create a six-channel surround presentation from conventional Matrix-encoded
DTS Neo:6 Musicand traditional Stereo sources. Select the Cinema version of Neo:6 when a program with any type of analog Matrix surround encoding is present.
Dolby 3 StereoUses the information contained in a surround-encoded or two-channel stereo program to create center-channel information. In addition, the
TheaterThe Theater mode creates a sound field that resembles the acoustic feeling of a standard live-performance theater.
Hall 1, Hall 2The two Hall modes create sound fields that resemble a small (Hall 1) and medium-sized (Hall 2) concert hall.
VMAx NearWhen only the two front-channel loudspeakers are used, Harman’s patented VMAx mode delivers a three-dimensional sound space with the illusion
VMAx Farof “phantom speakers” at the center and surround positions. The VMAx N, or “Near Field,” mode should be selected when your listening position is
5-Channel StereoThis mode takes advantage of multiple speakers to place a stereo signal at both the front and back of a room. Depending on whether the AVR
7-Channel Stereohas been configured for either 5.1 or 6.1/7.1 operation, one of these modes, but not both, is available at any time. Ideal for playing music in
SurroundThis mode turns off all surround processing and presents the pure left- and right-channel presentation of two-channel stereo programs.
Off (Stereo)
SURROUND SELECT menu, the “5.1” versions of Logic 7 modes are available when the 5.1 option is chosen, while the “7.1” versions of
Logic 7 produce a full sound field presentation, including back surround speakers when the “6.1/7.1” option is chosen. The Logic 7 C (or Cinema)
mode should be used with any source that contains Dolby Surround or similar matrix encoding. Logic 7 C delivers increased center-channel
intelligibility, and more accurate placement of sounds with fades and pans that are much smoother and more realistic than with other decoding
techniques. The Logic 7 M or Music mode should be used with analog or PCM stereo sources. Logic 7 M enhances the listening experience by
presenting a wider front soundstage and greater rear ambience. Both Logic 7 modes also direct low-frequency information to the subwoofer
(if installed and configured) to deliver maximum bass impact. The Logic 7 E (or Enhance) mode, available only when the 5.1 option is chosen,
is an extension of the Logic 7 mode that is primarily used with musical programs. Logic 7 adds additional bass enhancement that circulates low
frequencies in the 40Hz to 120Hz range to the front and surround speakers to deliver a less localized soundstage that appears broader and wider
than when the subwoofer is the sole source of bass energy.
Select the Music version of Neo:6 for optimal processing when a nonencoded, two-channel stereo program is being played.
information that is normally sent to the rear-channel surround speakers is carefully mixed in with the front-left and front-right channels for increased
realism. Use this mode when you have a center channel speaker but no surround speakers.
less than five feet from the speakers. The VMAx F, or “Far Field,” mode should be selected when your listening position is greater than five feet from
the speakers. The VMAx modes are also available using the
appear to push the sound field away from your ears, reducing the “inside the head” sensation often experienced when using headphones.
situations such as a party, it places the same signal at the front-left and surround-left, and front-right and surround-right speakers.
The center channel is fed a summed mono mix of the in-phase material of the left and right channels.
Headphones Output 4. When headphones are being used, the Far Field mode will
24 OPERATION
TROUBLESHOOTING GUIDE
SYMPTOMCAUSESOLUTION
Unit does not function when Main• No AC Power• Make certain AC power cord is plugged into
Power Switch is pusheda live outlet
• Check to see whether outlet is switch-controlled
Display lights, but no sound• Intermittent input connections• Make certain that all input and speaker connections
or pictureare secure
•
Mute is on• Press Mute Button
• Volume control is down• Turn up volume control
Unit turns on, but front panel • Display brightness is turned off• Follow the instructions in the Display Brightness section
display does not light upon page 28 so that the display is set to VFD FULL
No sound from any speaker;• Amplifier is in protection mode • Check speaker wire connections for shorts at receiver and
light around power switch is reddue to possible shortspeaker ends
• Amplifier is in protection mode • Contact your local Harman Kardon service center
due to internal problems
No sound from surround or• Incorrect surround mode• Select a mode other than Stereo
center speakers• Input is monaural• There is no surround information from mono sources
• Stereo or Mono program material• The surround decoder may not create center- or rear-channel
information from nonencoded programs
41
Unit does not respond to• Weak batteries in remote• Change remote batteries
remote commands• Wrong device selected• Press the AVR selector
• Remote sensor is obscured• Make certain front panel sensor is visible to remote
or connect remote sensor
Intermittent buzzing in tuner• Local interference• Move unit or antenna away from computers, fluorescent
lights, motors or other electrical appliances
Letters flash in the channel indicator• Digital audio feed paused• Resume play for DVD
display and digital audio stops• Check that Digital Input is selected
In addition to the items shown above, additional information on troubleshooting possible problems with your AVR 135, or installation-related issues, may be found in the list of
"Frequently Asked Questions" which is located in the Product Support section of our Web site at www.harmankardon.com.
Processor Reset
In the rare case where the unit’s operation or the displays seem abnormal, the cause may involve the erratic
operation of the system’s memory or microprocessor.
To correct this problem, first unplug the unit from the
AC wall outlet and wait at least three minutes. After the
pause, reconnect the AC power cord and check the
unit’s operation. If the system still malfunctions, a system reset may clear the problem.
NOTE: Resetting the processor will erase any configuration settings you have made for speakers, output
levels, surround modes, digital input assignments as
well as the tuner presets. The unit will be returned to
the factory presets, and all settings for these items
must be reentered.
If the system is still operating incorrectly, there may
have been an electronic discharge or severe AC line
interference that has corrupted the memory or
microprocessor.
To clear the AVR 135’s entire system memory including tuner presets, output level settings, delay times and
speaker configuration data, press and hold the
Mode Button
will turn on automatically.
5 button for three seconds. The unit
Tone
If these steps do not solve the problem, consult an
authorized Harman Kardon service center.
TROUBLESHOOTING GUIDE 45
AMPLIFIER SECTION BIAS ADJUSTMENT
Measurement condition
. No input signal or volume position is minimum.
Standard value.
. Ideal current = 48mA ( ± 5%)
. Ideal DC Voltage = 25.92mV (
± 5%)
CUP11651Y (BIAS PCB)
............
VR87
CN81
VR86
CN82
VR82
CN86
VR81
DC VOLTMETER..............Connect to CN81,CN82,CN83,CN84,CN85,CN86,CN87
Step 1. Output Voltage is equal to Power Source Voltage (VDD).
Step 2. When Input Voltage to Comparator reaches the state of Vref≥V
DD
·(Rb+Rc)/(Ra+Rb+Rc)at Point A (Detected Voltage –VDET), the output of Com-
parator is reserved, so that Output Voltage becomes GND.
Step 3. In the case of CMOS Output, Output Voltage becomes unstable when Supply Voltage (V
DD) is smaller than Minimum Operating Voltage. In the
case of Nch Open Drain Output, a pulled-up voltage is output.
Step 4. Output Voltage becomes equal to GND.
Step 5. When Input Voltage to Comparator reaches the state of Vref≤V
DD· (Rb)/(Ra+ Rb) at Point B (Released Voltage +VDET), the output of Comparator is reversed,
so that Output Voltage becomes equal to Supply Voltage (V
DD).
FIG. 2 Operation Diagram
StepStep 1Step 2Step 3Step 4Step 5
Comparator(+) Pin
Input Voltage
III II III
Comparator Output
HL
Indefinite
LH
Tr. 1OFFON
Indefinite
ONOFF
Output Tr.
PchONOFF
Indefinite
OFFON
NchOFFON
Indefinite
ONOFF
I
.
Rb + Rc
Ra + Rb + Rc
·V
DD
II
.
Rb
Ra + Rb
·V
DD
GND
OUT
V
DD
Ra
Rb
Rc
Tr.1
Vref
Pch
Nch
–
+
Detector Threshold Hysteresis
tPLH
1
2
3
4
5
A
B
• In R×5VT××A, Nch Tr. drain is
connected to OUT pin.
• In R
×5VT××C, Nch Tr. drain
and Pch Tr. drain are connected
to OUT pin.
Released Volage +V
DET
Supply VolageDetected Volage –V
DET
(VDD)
Minimum Operating Volage
GND
Output Volage
(OUT)
GND
R×5VL
2
BLOCK DIAGRAMS
•
Nch Open Drain Output (R×5VL××A)
•
CMOS Output (R×5VL××C)
TIME CHART
DEFINITION OF OUTPUT DELAY TIME t
PLH
2
3
Vref
OUT
GND
V
DD
–
+
1
VDD
2
1
3
Vref
OUT
GND
–
+
Detector Threshold Hysteresis
tPLH
Released Voltage+VDET
Detected Voltage–V
DET
Supply Voltage
(V
DD)
OutputVoltage
(OUT)
Minimum OperatingVoltage
GND
GND
tPLHtPHL
Input Voltage
(V
DD)
Output Voltage
Nch Open Drain Output
GND
GND
3.5V
7.0V
1.2V
+V
DET + 2.0V
tPLHtPHL
CMOS Output
GND
GND
1.2V
+V
DET +2.0V
+V
DET +2.0V
+V
DET +2.0V
2
Input Voltage
(V
DD)
Output Voltage
•
TO-92
PIN CONFIGURATION
•
SOT-89
•
SOT-23-5
PIN DESCRIPTION
•
TO-92
•
SOT-89
•
SOT-23-5
Pin NoSymbol
1OUT
2VDD
3GND
4NC
5NC
Pin NoSymbol
1OUT
2VDD
3GND
Pin NoSymbol
1OUT
2VDD
3GND
R×5VL
5
(mark side)
12
3
(mark side)
12
5
4
(mark side)
3
12
3
R×5VL
14
OPERATION
FIG. 1 Block Diagram
Operation Diagram
Step 1. Output Voltage is equal to Power Source Voltage (VDD).
Step 2. When Input Voltage to Comparator reaches the state of Vref ≥ V
DD
·(Rb+Rc)/(Ra+Rb+Rc)at Point A (Detected Voltage –VDET), the output of Com-
parator is reserved, so that Output Voltage becomes GND.
Step 3. In the case of CMOS Output, Output Voltage becomes unstable when Supply Voltage (V
DD) is smaller than Minimum Operating Voltage. In the
case of Nch Open Drain Output, a pulled-up voltage is output.
Step 4. Output Voltage becomes equal to GND.
Step 5. When Input Voltage to Comparator reaches the state of Vref≤V
DD·(Rb)/(Ra
+
Rb) at Point B (Released Voltage +V
DET), the output of Comparator is reserved,
so that Output Voltage becomes equal to Supply Voltage (V
DD)
FIG. 2 Operation Diagram
StepStep 1Step 2Step 3Step 4Step 5
Comparator(+)Pin
Input Voltage
I
IIIIIII
Comparator Output
HL
Indefinite
LH
Tr. 1OFFON
Indefinite
ONOFF
Output Tr.
PchONOFF
Indefinite
OFFON
NchOFFON
Indefinite
ONOFF
I
.
Rb
+
Rc
Ra
+Rb+
Rc
·V
DD
II.
Rb
Ra
+
Rb
·V
DD
GND
OUT
V
DD
Ra
Rb
Rc
Tr.1
Vref
Pch
Nch
–
+
Detector Threshold Hysteresis
tPLH
1
23 4
5
A
B
· In R×5VL ××A, Nch Tr. drain is con-
nected to OUT pin.
· In R
×5VL ××C, Nch Tr. drain and
Pch Tr. drain are connected to
OUT pin.
Released Volage +V
DET
Supply VolageDetected Volage –V
DET
(VDD)
Minimum Operating Volage
GND
Output Volage
(OUT)
GND
R×5VL
24
PACKAGE DIMENSIONS (Unit: mm)
•
TO-92
•
SOT-89
•
SOT-23-5
5.2MAX.
4.2MAX.
2.3MAX.
5.2MAX.
12.7MAX.
0.6MAX.
0.55MAX.
1.27
2.54
1
2
3
0.7
0.5MAX.
4.5±0.1
0.4±0.1
0.4±0.1
1.5±0.1
1.6±0.2
1.5±0.1
±0.1±0.1±0.1
1.5±0.1
2.5±0.1
0.4
MIN.
4.25MAX.
0.8
ø1.0
12
3
0.420.470.42
2.9±0.2
0.4±0.1
1.9±0.2
(0.95)(0.95)
54
123
+0.2
–0.1
1.6
+0.2
–0.1
1.1
+0.1
–0.05
0.15
2.8±0.3
0to0.1
0.2 MIN.
0.8±0.1
R×5VL
25
TAPING SPECIFICATIONS (Unit: mm)
•
TO-92
(Note) When taping is conducted, the pins of TO-92 are
subjected to a particular forming.
(Note) TZ type tape is not in the form of a reel, but is
packed in a zigzag state in a box.Therefore, the
tape can be used as either an RF type tape or an
RR type tape,depending upon the pulling out direction (B or F).
•
SOT-23-5
•
SOT-89
RFRR
±1.0
0.3
12.7
12.7
ø
4.0±0.2
6.0
±0.5
±
9.0±0.5
0.5
MAX.
18.0
+1.0
–0.5
16.0±0.5
19.0±0.5
24.7 MAX.
1.45 MAX.
0.7±0.2
*
*
:MarkSide
When TZ type tape is
pulled out from the
direction B
When TZ type tape is
pulled out from the
direction F
User Direction of Feed
(Note)
User Direction of Feed.
T1
ø
T2
8.0±0.1
5.0
1.5
4.0±0.1
2.0±0.05
1.5±0.1
5.65±0.05
4.7
12±0.3
+0.1
–0
2.5MAX.
0.3±0.1
TR
TL
2.0MAX.
0.3±0.1
4.0±0.1
2.0±0.05
4.0±0.1
3.3
3.2
8.0±0.3
1.75±0.1
3.5±0.05
1.5
+0.1
–0
ø
User Direction of Feed.
5.2 MAX.
4.2 MAX.
2.3 MAX.
5.2 MAX.12.7 MAX.
0.6 MAX.
0.55
1
2
3
0.7
0.5 MAX.
MAX.
2.5
–0.1
+0.4
1311 1214
@UQ124.12/
27
}
0
QdlnudsgdRbqdvr
2-QdlnuhmfsgdQd`qO`mdk
10
4653 210081/
7
8
0/
00
01
02
03
04
05
06
07
15
16
25
20
2/212223 24
1817
6
}
07
3
5
2
4
1
0
QdlnudsgdRbqdvr
3-QdlnuhmfsgdL`hmOBA
7
02
01
7
6
8
00
0/
02
}
0
5
2
0
1
}
08
0
QdlnudsgdRbqdvr
1-QdlnuhmfsgdEqnmsO`mdk
3
4
5
6
1
2
QdlnudsgdRbqdvr
0-QdlnuhmfsgdSnoB`ahmds
CHR@RRDLAKX
3
4
7
8
SAFETY PRECAUTIONS
The following check should be performed for the continued
protection of the customer and service technician.
LEAKAGE CURRENT CHECK
Measure leakage current to a known earth ground (water
pipe, conduit, etc.) by connecting a leakage current tester
between the earth ground and all exposed metal parts of the
appliance (input/output terminals, screwheads, metal
overlays, control shaft, etc.). Plug the AC line cord of the
appliance directly into a 250V AC 50Hz outlet and turn the
AC power switch on. Any current measured must not exceed
o.5mA.
Reading should
not be above
0.5mA
Earth
ground
Device
under
test
Test all
exposed metal
surfaces
Also test with
plug reversed
(Using AC adapter
plug as required)
Leakage
current
tester
AC Leakage Test
ANY MEASUREMENTS NOT WITHIN THE LIMITS
OUTLINED ABOVE ARE INDICATIVE OF A
POTENTIAL SHOCK HAZARD AND MUST BE
CORRECTED BEFORE RETURNING THE APPLIANCE
TO THE CUSTOMER.
P4.0 - P4.7 I/O Bit programmable port; input or output mode
Pin
Type
Pin
Description
Circuit
Type
Pin
Number
D-1 38-31 INT0–
selected by software; input or push-pull output.
Software assignable pull-up.
P4.0-P4.7 can alternately be used as inputs for
external interrupts INT0-INT7, respectively (with
noise filters and interrupt controller)
P5.0 - P5.7 I/O Bit programmable port; input or output mode
G 22-17,11-9 TxD1
selected by software; input or push-pull output.
Software assignable pull-up.
Alternately, P5.0~P5.3 can be used as I/O for serial
por, UART0, UART1, respectively.
P6.0 - P6.7 O N-channel, open-drain output only port. F 58–54,51-49
P7.0 - P7.7 I General-purpose digital input ports. Alternatively
E 48-45,42-39 ADC0-used as analog input pins for A/D converter modules.
P8.0 - P8.5 I/O Bit programmable port; input or output mode
D,D-1 64-59 INT8,INT9
selected by software; input or push-pull output.
Software assignable pull-up.
P8.4, P8.5 can alternately be used as inputs for
external interrupts INT8, INT9, respectively (with
noise filters and interrupt controller)
This is a general purpose I/O port. A setting in the pull-up
resistance setting register (RDR0) can be used to apply pull-up
resistance (RD00-RD07 = “1”) . (Disabled when pin is set for
C
(CMOS)
C
(CMOS)
E
(CMOS/H)
E
(CMOS/H)
output.)
In multiplex mode, these pins function as the external address/
data bus low I/O pins.
In non-multiplex mode, these pins function as the external data
bus low output pins.
This is a general purpose I/O port. A setting in the pull-up
resistance setting resister (RDR1) can be used to apply pull-up
resistance (RD10-RD17 = “1”) . (Disabled when pin is set for
output.)
In multiplex mode, these pins function as the external address/
data bus high I/O pins.
In non-multiplex mode, these pins function as the external data
bus high output pins.
This is a general purpose I/O port. When the bits of external
address output control register (HACR) are set to "1" in external
bus mode, these pins function as general purpose I/O ports.
When the bits of external address output control register (HACR)
are set to "0" in multiplex mode, these pins function as address
high output pins (A16-A19).
When the bits of external address output control register (HACR)
are set to "0" in non-multiplex mode, these pins function as
address high output pins (A16-A19).
This is a general purpose I/O port. When the bits of external
address output control register (HACR) are set to "1" in external
bus mode, these pins function as general purpose I/O ports.
When the bits of external address output control register (HACR)
are set to "0" in multiplex mode, these pins function as address
high output pins (A20-A23).
When the bits of external address output control register (HACR)
are set to "0" in non-multiplex mode, these pins function as
address high output pins (A20-A23).
PPG timer output pins.
Function
(Continued)
MB90482
Pin No.
1
LQFP*
QFP*
79
810
1012
1113
1214
1315
14
15
16
17
1618
1719
1820
2
Pin name
P30
A00
Circuit
type
E
(CMOS/H)
Function
This is a general purpose I/O port.
In non-multiplex mode, this pin functions as an external address pin.
In non-multiplex mode, this pin functions as an external
address pin.
This is a general purpose I/O port.
In non-multiplex mode, this pin functions as an external
address pin.
SIN2Simple serial I/O input pin.
P41
A09
F
(CMOS)
This is a general purpose I/O port.
In non-multiplex mode, this pin functions as an external
address pin.
SOT2Simple serial I/O output pin.
P42
A10
G
(CMOS/H)
This is a general purpose I/O port.
In non-multiplex mode, this pin functions as an external
address pin.
SCK2Simple serial I/O clock input/output pin.
(Continued)
MB90482
Pin No.
1
LQFP*
19
20
2224
23
24
6870
6971
7072
7173
7274
7375
QFP*
21
22
25
26
Circuit
type
F
(CMOS)
4
F*
(CMOS)
F
(CMOS)
This is a general purpose I/O port.
In non-multiplex mode, this pin functions as an external
address pin.
This is a general purpose I/O port.
In non-multiplex mode, this pin functions as an external
address pin.
This is a general purpose I/O port.
In non-multiplex mode, this pin functions as an external
address pin.
2
Pin name
P43, P44
A11, A12
P45
A13
P46, P47
A14, A15
OUT4/OUT5Output compare event output pins.
P50
ALE
P51
RD
D
(CMOS)
D
(CMOS)
This is a general purpose I/O port. In external bus mode, this pin
functions as the ALE pin.
In external bus mode, this pin functions as the address load
enable (ALE) signal pin.
This is a general purpose I/O port. In external bus mode, this pin
functions as the RD
pin.
In external bus mode, this pin functions as the read strobe output
(RD
) signal pin.
This is a general purpose I/O port. In external bus mode, when
P52
D
(CMOS)
WRL
the WRE pin in the EPCR register is set to “1”, this pin functions
as the WRL
pin.
In external bus mode, this pin functions as the lower data write
strobe output (WRL
) pin. When the WRE bit in the EPCR regis-
ter is set to “0”, this pin functions as a general purpose I/O port.
This is a general purpose I/O port. In external bus mode with
P53
D
(CMOS)
WRH
16-bit bus width, when the WRE bit in the EPCR register is set to
“1”, this pin functions as the WRH
In external bus mode with 16-bit bus width, this pin functions as
the upper data write strobe output (WRH
in the EPCR register is set to “0”, this pin functions as a general
purpose I/O port.
This is a general purpose I/O port. In external bus mode, when
P54
D
(CMOS)
HRQ
the HDE bit in the EPCR register is set to “1”, this pin functions
as the HRQ pin.
In external bus mode, this pin functions as the hold request input
(HRQ) pin. When the HDE bit in the EPCR register is set to “0”,
this pin functions as a general purpose I/O port.
This is a general purpose I/O port. In external bus mode, when
P55
D
(CMOS)
HAK
the HDE bit in the EPCR register is set to “1”, this pin functions
as the HAK
pin.
In external bus mode, this pin functions as the hold acknowledge
(HAK
) pin. When the HDE bit in the EPCR register is set to “0”,
this pin functions as a general purpose I/O port.
Function
pin.
) pin. When the WRE bit
(Continued)
MB90482
Pin No.
LQFP*
1
QFP*
2
7476
7678
36 to 39 38 to 41
AN0 to AN3These are the analog input pins.
41 to 44 43 to 46
AN4 to AN7These are the analog input pins.
2527
2628
2729
2830
2931
3032P75
3133P76
3234P77
45,
46
47,
48
IRQ0, IRQ1External interrupt input pins.
50 to 55 52 to 57
IRQ2 to IRQ7External interrupt input pins.
Pin name
Circuit
type
Function
This is a general purpose I/O port. In external bus mode, when
P56
D
(CMOS)
RDY
the RYE bit in the EPCR register is set to “1”, this pin functions
as the RDY pin.
In external bus mode, this pin functions as the external ready
(RDY) input pin. When the RYE bit in the EPCR register is set to
“0”, this pin functions as a general purpose I/O port.
This is a general purpose I/O port. In external bus mode, when
P57
D
(CMOS)
CLK
the CKE bit in the EPCR register is set to “1”, this pin functions
as the CLK pin.
In external bus mode, this pin functions as the machine cycle
clock (CLK) output pin. When the CKE bit in the EPCR register is
set to “0”, this pin functions as a general purpose I/O port.
P60 to P63
H
These are general purpose I/O ports.
(CMOS)
P64 to P67
H
These are general purpose I/O ports.
(CMOS)
P70
SIN0This is the UART data input pin.
P71
SOT0This is the UART data output pin.
P72
SCK0This is the UART clock I/O pin.
P73
TIN0This is the 16-bit reload timer event input pin.
P74
TOT0This is the 16-bit reload timer output pin.
G
(CMOS/H)
F
(CMOS)
G
(CMOS/H)
G
(CMOS/H)
F
(CMOS)
F*
(CMOS)
F*
(CMOS)
F*
(CMOS)
P80, P81
P82 to P87
E
(CMOS/H)
E
(CMOS/H)
This is a general purpose I/O port.
This is a general purpose I/O port.
This is a general purpose I/O port.
This is a general purpose I/O port.
This is a general purpose I/O port.
4
This is a general purpose I/O port.
5
This is a general purpose I/O port.
5
This is a general purpose I/O port.
These are general purpose I/O ports.
These are general purpose I/O ports.
(Continued)
MB90482
(Continued)
Pin No.
LQFP*
1
QFP*
2
Pin name
P90
5658
SIN1Simple serial I/O data input pin.
CS0Chip select 0.
P91
5759
SOT1Simple serial I/O data output pin.
CS1Chip select 1.
P92
5860
SCK1Simple serial I/O data input/output pin.
CS2Chip select 2.
P93
FRCK
5961
ADTG
CS3Chip select 3.
6062
P94
PPG4PPG timer output pin.
6163
P95
PPG5PPG timer output pin.
6264
P96
IN0Input capture channel 0 trigger input pin.
6365
P97
IN1Input capture channel 1 trigger input pin.
64 to 6766 to 69
PA0 to PA3
OUT0 to OUT3Output compare event output pins.
3335AV
CC⎯A/D converter power supply pin.
3436AVRH⎯A/D converter external reference voltage supply pin.
3537AV
SS⎯A/D converter power supply pin.
47 to 4949 to 51MD0 to MD2
21, 8223, 84V
9, 40, 79 11, 42, 81V
CC⎯3.3 V ± 0.3 V power supply pins (VCC3) .
SS⎯Power supply input pins (GND) .
Circuit
type
E
(CMOS/H)
D
(CMOS)
E
(CMOS/H)
E
(CMOS/H)
D
(CMOS)
D
(CMOS)
E
(CMOS/H)
E
(CMOS/H)
D
(CMOS)
J
(CMOS/H)
Function
This is a general purpose I/O port.
This is a general purpose I/O port.
This is a general purpose I/O port.
This is a general purpose I/O port.
When the free run timer is in use, this pin functions as the
external clock input pin.
When the A/D converter is in use, this pin functions as the
external trigger input pin.
This is a general purpose I/O port.
This is a general purpose I/O port.
This is a general purpose I/O port.
This is a general purpose I/O port.
These are general purpose I/O ports.
Operating mode selection input pins.
*1 : LQFP : FPT-100P-M05
*2 : QFP : FPT-100P-M06
*3 : The circuit type of MB90V480 is E (CMOS/H).
*4 : The circuit type of MB90V480 is G (CMOS/H).
*5 : The circuit type of MB90V480 is I (NMOS/H)
O.S.D IC (74763M)
Pin Functions (IC51)
Pin No.SymbolFunctionDescription
1V
SS
2Xtal
3Xtal
OUT1
4HSYNC
5Xtal
6Xtal
OUT2
7VSYNC
8CSEnable input
9SINData inputSerial data input (hysteresis input). Pull-up resistor built in (metal option).
10SCLKClock inputClock input for serial data input (hysteresis input). Pull-up resistor built in (metal option).
11SECAM
12525/625
13NTSC/PAL
143.58/4.433.58/4.43 switch input/outputDuring output, functions as general output port or halftone output (command switch).
15RSTReset input
16CV
17V
OUT
DD2
18CV
19CV
20SYNC
21SEP
22V
23PD
SS
OUT
24AMP
25AMP
26FCControl voltage inputAFC control voltage input
27VCO
28VCO
29SYNC
30V
DD1
GroundGround connection
IN1
Crystal oscillator connection
Horizontal synchronization Outputs the horizontal synchronization signal (AFC). The output polarity can be selected
OUT
output(metal option). Also functions as general output port (command switch).
IN2
Crystal oscillator connection
Vertical synchronization output
OUT
Connection for the crystal and capacitor used to form the crystal oscillator that generates
the internal synchronization signal. The oscillator can be selected with a command switch.
Connection for the crystal and capacitor used to form the crystal oscillator that generates
the internal synchronization signal.
Outputs the vertical synchronization signal. The output polarity can be selected (metal
option). Also functions as general output port (command switch).
Enables/disables serial data input. Serial data is enabled when this pin is low (hysteresis
input). Pull-up resistor built in (metal option).
SECAM mode switch input/
output (command switch)
525/625 switch input/output
(command switch)
NTSC/PAL switch input/output
(command switch)
During input, switches between SECAM and other modes.
During output, functions as general output port or internal V output (command switch).
Low = other modes, high = SECAM mode
During input, switches between 525 scan lines and 625 scan lines.
During output, functions as general output port or character data output (command switch).
Low = 525 lines, high = 625 lines
Switches the color mode between NTSC and PAL.
During output, functions as general output port or frame data output (command switch).
Low = NTSC, high = PAL
Switch FSC between 3.58 MHz and 4.43 MHz.
(command switch)Low = 3.58, high = 4.43
System reset input pin, low is active (hysteresis input).
Pull-up resistor built in (metal option).
Video signal outputComposite video output
Power supply connectionPower supply connection for composite video signal level generation
Video signal inputComposite video input
IN
Video signal inputSECAM chroma signal input
CR
Sync separator circuit inputBuilt-in sync separator circuit video signal input
31CLKSEL(GND)IDSP clock mode select pin: connect the GND
32FILT1Connects to an external filter for the on-chip phase-locked loop
33FILT1Connects to an external filter for the on-chip phase-locked loop
34+2.5V-Analog Power supply for clock generator . Normally +2.5V
35AGND-Analog ground supply for clock generator PLL.
36RESET(CS_RST)IMaster reset input pin
37DBDATA-Reserved pin and should be pulled up with an external resistor.
38DBCLK-Reserved pin and should be pulled up with an external resistor.
39AUD2(SDO2)OPCM multi-format digital-audio data ouput2 pin
40AUD1(SDO1)OPCM multi-format digital-audio data ouput1 pin
41AUD0(SDO0)OPCM multi-format digital-audio data ouput0 pin
42LRCLKIAudio output sample rate clock pin
43SCLK(BICK)IAudio ouput bit clock pin
44MCLKIAudio master clock output pin
PIN ASSIGNMENT.(CS493263)
VD1
DGND1
AUDATA3, XMT958
WR,DS,EMWR,GPIO10
RD,R/W,EMOE,GPIO11
A1,SCDIN
A0,SCCLK
DATA7,EMAD7,GPIO7
DATA6,EMAD6,GPIO6
DATA5,EMAD5,GPIO5
DATA4,EMAD4,GPIO4
VD2
DGND2
DATA3,EMAD3,GPIO3
DATA2,EMAD2,GPIO2
DATA1,EMAD1,GPIO1
DATA0,EMAD0,GPIO0
CS
SCDIO,SCDOUT,PSEL,GPIO9
ABOOT,INTREQ
EXTMEM,GPIO8
SDATAN1
7
8
9
10
11
12
13
14
15
16
17
6 5 4 3 2 1 44 43 42 41 40
CS493XXX-CLG
44-pin PLCC
Top View
18 19 20 21 22 23 24 25 26 27 28
MCLK
SCLK
LRCLK
AUDATA0
AUDATA1
AUDATA2
DC
39
38
37
36
35
34
33
32
31
30
29
DD
RESET
AGND
VA
FILT1
FILT2
CLKSEL
CLKIN
CMPREQ,LRCLKN2
CMPCLK,SCLKN2
CMPDAT,SCLKN2,RCV958
LRCLKN1
SCLKN1,STCCLK2
DGND3
VD3
BlOCK DIAGRAM(CS493263)
DATA7:0,
EMAD7:0,
GPIO7:0
RAM Input
PLL
CMPDAT
SDATAN2
CMPCLK
SCLKN2
CMPREQ
LRCLKN2
SCLKN1
STCCLK2
LRCLKN1
SDATAN1
CLKIN
CLKSEL
RESET
Compressed
Data Input
Interface
Digital
Audio
Input
Interface
Clock Manager
Framer
Shifter
Input
Buffer
Controller
Buffer
CS
(TOP VIEW)
RD,
R/W,
EMWR,
EMOE,
GPIO10
GPIO11
DSP Processing
RAM
Program
Memory
ROM
Program
Memory
WR,
DR,
SCDIO,
SCDOUT,
PSEL,
GPIO9
Parallel or Serial Host Interface
24-Bit
RAM
Data
Memory
ROM
Data
Memory
STC
A0,
SCCLK
Output
A1,
SCDIN
RAM
Buffer
A800T
INTERQ
EXTMEM.
GPIO8
Output
Formatter
DD
DC
MCLK
SCLK
LRCLK
AUDA
XMT95
FILTDFILTSVAAGNDDGND(3:1)VD(3:1)
ASAHI KASEIAKM CONFIDENTIAL[AK5381]
PDN
= Preliminary =
AK5381
24Bit 96kHz ΔΣ ADC
GENERAL DESCRIPTION
The AK5381 is a stereo A/D Converter with wide sampling rate of 4kHz ∼ 96kHz and is suitable for
High-end audio system. The AK5381 achieves high accuracy and low cost by using Enhanced dual bit
ΔΣ techniques. The AK5381 requires no external components because the analog inputs are singleended. The audio interface has two formats (MSB justified, I
music instrument and AV receiver.
FEATURES
Stereo ΔΣ ADC
On-Chip Digital Anti-Alias Filtering
Single-ended Input
Digital HPF for DC-Offset cancel
S/(N+D): 96dB@5V for 48kHz
DR:106dB@5V for 48kHz
S/N:106dB@5V for 48kHz
Sampling Rate Ranging from 4kHz to 96kHz
Master Clock:
Note: All digital input pins should not be left floating.
Rev.0.42002/08
- 3 -
ASAHI KASEI
I/F
PCM
DSD
AKM CONFIDENTIAL
[AK4358]
= Target Spec =
AK4358
192kHz 24-Bit 8ch DAC with DSD Input
GENERAL DESCRIPTION
The AK4358 is eight channels 24bit DAC corresponding to digital audio system. Using AKM's advanced
multi bit architecture for its modulator the AK4358 delivers a wide dynamic range while preserving
linearity for improved THD+N performance. The AK4358 has full differential SCF outputs, removing the
need for AC coupling capacitors and increasing performance for systems with excessive clock jitter. The
AK4358 accepts 192kHz PCM data and 1-Bit DSD data, ideal for a wide range of applications including
DVD-Audio and SACD.
FEATURES
Sampling Rate Ranging from 8kHz to 192kHz
24Bit 8 times Digital Filter with Slow roll-off option
THD+N:-94dB
DR, S/N:114dB
High Tolerance to Clock Jitter
Low Distortion Differential Output
DSD Data input available
Channel Independent Digital De-emphasis for 32, 44.1 & 48kHz sampling
Zero Detect function
Channel Independent Digital Attenuator with soft-transition (3 Speed mode)
01HD60PW4
04HD7ATT7ATTE
05HD7ATT7ATTE
06HD7ATT7ATTE
07HD7ATT7ATTE
08HD7ATT7ATTE
09HD7ATT7ATTE
0AHD7, D60, 0TDM1, TDM0
0BHNot availableLOUT4 ATT Control
0CHNot availableROUT4 ATT Control
0DHNot availableDZF1 control
0EHNot availableDZF2 control
0FHNot availableDZF3 control
When at “L”, the AK4358 is in the power-down mode and is held in reset.
The AK4358 should always be reset upon power-up.
BICKIAudio Serial Data Clock Pin
MCLKIMaster Clock Input Pin
An external TTL clock should be input on this pin.
DVDD-
Digital Power Supply Pin, +4.75∼+5.25V
DVSS-Digital Ground Pin
SDTI1IDAC1 Audio Serial Data Input Pin
SDTI2IDAC2 Audio Serial Data Input Pin
SDTI3IDAC3 Audio Serial Data Input Pin
SDTI4IDAC4 Audio Serial Data Input Pin
LRCKIL/R Clock Pin
I2CIControl Mode Select Pin
CCLK/SCLIControl Data Clock Pin
CDTI/SDAI/OControl Data Input Pin
CSN/CAD1IChip Select Pin
DCLKIDSD Clock Pin
DSDL1IDAC1 DSD Lch Data Input Pin
DSDR1IDAC1 DSD Rch Data Input Pin
DSDL2IDAC2 DSD Lch Data Input Pin
DSDR2IDAC2 DSD Rch Data Input Pin
DSDL3IDAC3 DSD Lch Data Input Pin
DSDR3IDAC3 DSD Rch Data Input Pin
DSDL4IDAC4 DSD Lch Data Input Pin
DSDR4IDAC4 DSD Rch Data Input Pin
DIF0IAudio Data Interface Format 0 Pin
VREFHIPositive Voltage Reference Input Pin
AVDD-
Analog Power Supply Pin, +4.75∼+5.25V
AVSS-Analog Ground Pin
ROUT4-ODAC4 Rch Negative Analog Output Pin
ROUT4+ODAC4 Rch Positive Analog Output Pin
LOUT4-ODAC4 Lch Negative Analog Output Pin
LOUT4+ODAC4 Lch Positive Analog Output Pin
ROUT3-ODAC3 Rch Negative Analog Output Pin
ROUT3+ODAC3 Rch Positive Analog Output Pin
LOUT3-ODAC3 Lch Negative Analog Output Pin
LOUT3+ODAC3 Lch Positive Analog Output Pin
ROUT2-ODAC2 Rch Negative Analog Output Pin
ROUT2+ODAC2 Rch Positive Analog Output Pin
LOUT2-ODAC2 Lch Negative Analog Output Pin
LOUT2+ODAC2 Lch Positive Analog Output Pin
ROUT1-ODAC1 Rch Negative Analog Output Pin
IPS0 I Input Channel Select 0 Pin in Parallel Mode
1
RX4 I Receiver Channel 4 Pin in Serial Mode (Internal biased pin)
2 NC(AVSS) I
DIF0 I Audio Data Interface Format 0 Pin in Parallel Mode
3
RX5 I Receiver Channel 5 Pin in Serial Mode (Internal biased pin)
4 TEST2 I
DIF1 I Audio Data Interface Format 1 Pin in Parallel Mode
5
RX6 I Receiver Channel 6 Pin in Serial Mode (Internal biased pin)
6 NC(AVSS) I
DIF2 I Audio Data Interface Format 2 Pin in Parallel Mode
7
RX7 I Receiver Channel 7 Pin in Serial Mode (Internal biased pin)
IPS1 I Input Channel Select 1 Pin in Parallel Mode
8
IIC I
9 P/SN I
10 XTL0 I X’tal Frequency Select 0 Pin
11 XTL1 I X’tal Frequency Select 1 Pin
12 VIN I V-bit Input Pin for Transmitter Output
13 TVDD I Input Buffer Power Supply Pin, 3.3V or 5V
14 NC I
15 TX0 O Transmit Channel (Through Data) Output 0 Pin
16 TX1 O
17 BOUT O
18 COUT O C-bit Output Pin for Receiver Input
19 UOUT O U-bit Output Pin for Receiver Input
20 VOUT O V-bit Output Pin for Receiver Input
21 DVDD I Digital Power Supply Pin, 3.3V
22 DVSS I Digital Ground Pin
23 MCKO1 O Master Clock Output 1 Pin
24 LRCK I/O Channel Clock Pin
25 SDTO O Audio Serial Data Output Pin
26 BICK I/O Audio Serial Data Clock Pin
27 MCKO2 O Master Clock Output 2 Pin
28 DAUX I Auxiliary Audio Data Input Pin
29 XTO O X'tal Output Pin
30 XTI I X'tal Input Pin
No Connect
No internal bonding. This pin should be connected to AVSS.
TEST 2 pin
This pin should be connect to AVSS.
No Connect
No internal bonding. This pin should be connected to AVSS.
IIC Select Pin in Serial Mode.
“L”: 4-wire Serial, “H”: IIC
Parallel/Serial Select Pin
“L”: Serial Mode, “H”: Parallel Mode
No Connect
No internal bonding. This pin should be open or connected to DVSS.
When TX bit = “0”, Transmit Channel (Through Data) Output 1 Pin.
When TX bit = “1”, Transmit Channel (DAUX Data) Output Pin (Default).
Block-Start Output Pin for Receiver Input
“H” during first 40 flames.
PIN/FUNCTION (Continued)
No.Pin NameI/OFunction
31PDNI
CM0IMaster Clock Operation Mode 0 Pin in Parallel Mode
CDTOOControl Data Output Pin in Serial Mode, IIC= “L”.32
CAD1IChip Address 1 Pin in Serial Mode, IIC= “H”.
CM1IMaster Clock Operation Mode 1 Pin in Parallel Mode
CDTIIControl Data Input Pin in Serial Mode, IIC= “L”.33
SDAI/OControl Data Pin in Serial Mode, IIC= “H”.
OCKS1IOutput Clock Select 1 Pin in Parallel Mode
CCLKIControl Data Clock Pin in Serial Mode, IIC= “L”34
SCLIControl Data Clock Pin in Serial Mode, IIC= “H”
OCKS0IOutput Clock Select 0 Pin in Parallel Mode
CSNIChip Select Pin in Serial Mode, IIC=”L”.35
CAD0IChip Address 0 Pin in Serial Mode, IIC= “H”.
36INT0OInterrupt 0 Pin
37INT1OInterrupt 1 Pin
38AVDDIAnalog Power Supply Pin, 3.3V