16-11, YUSHIMA 3-CHOME, BUNKYOU-KU, TOKYO 113-0034 JAPAN
X0180V.01 DE/CDM 0308
Page 2
SAFETY PRECAUTIONS
The following check should be performed for the continued protection of the customer and service technician.
LEAKAGE CURRENT CHECK
Before returning the unit to the customer, make sure you make either (1) a leakage current check or (2) a line to chassis
resistance check. If the leakage current exceeds 0.5 milliamps, or if the resistance from chassis to either side of the
power cord is less than 460 kohms, the unit is defective.
LASER RADIATION
Do not stare into beam or view directly with optical instruments, class 3A laser product.
500V
2DN-S3000
(1)
(2)
1M
(1)
(2)
2
Page 3
DISASSEMBLY
(Follow the procedure below in reverse order when reassembling.)
1. SLIP DISK, SLIP MAT
(1) Remove a screw and pull out Slip Disc and Slip Mat.
.
3DN-S3000
Washer
Slip Disc
Slip Mat
Slip Sheet
Anti-static Sheet
2. PLATTER
(1) Remove Belt from Motor Pully.
(2) Remove 3 screws and pull out Platter.
.
Motor Pully
Belt
Platter
3
Page 4
3. DRIVE UNIT
(1) Remove 4 screws and pull out Drive Unit.
(2) Disconnect Flat cable and Connector.
(3) Detach Drive Unit.
Drive Unit
71
4DN-S3000
71
Connector
Flat cable
Drive Unit
Note:
z Do not pull out aslant to prevent Flat cable damage.
z Do not fail to pull AC cord from wall outlet before disconnect the Flat cable and Connector.
If AC cord is remained plugged into wall outlet, power is kept supplied in the unit, which may cause danger.
4. COVER UNIT
(1) Remove 5 screws and pull out Cover Unit.
(2) Disconnect Connectors.
(3) Detach Cover unit.
CX042
Connector
CX101
Cover unit
CX041
Connector
CX031
Note:
z Do not fail to pull AC cord from wall outlet before disconnect Connectors.
If AC cord is remained plugged into wall outlet, power is kept supplied in the unit, which may cause danger.
4
Page 5
5. SENSOR AND SCALE UNITS OF PLATTER
(1) Remove 2 screws and pull out Sensor Cover and Sensor unit.
(2) Remove a E Ring.
(3) Pull out Scale unit.
5DN-S3000
E Ring
Sensor Cover
Sensor unit
6. SENSOR AND SCALE UNITS OF SLIP DISC
(1) Remove 2 screws and pull out Sensor Cover and Sensor unit.
(2) Remove a screw and pull out Scale unit.
Scale unit
Scale unit
Sensor Cover
7. POWER PWB
(1) Remove 5 screw and pull out Power PWB.
Sensor unit
Power PWB
5
Page 6
8. DSP PWB UNIT
(1) Remove 9 screws and pull out DSP PWB unit.
DSP PWB unit
9. DRIVE COVER
(1) Remove 4 screws and pull out Drive cover.
6DN-S3000
Drive cover
10. DRIVE
(1) Move Drive Rack in arrow direction through the Hole on the bottom chassis.
Loader frame comes out.
(2) Pull up Loader panel while pulling it towards front.
(3) Remove 4 screws and pull out Drive.
Drive
6
Page 7
BLOCK DIAGRAM
DN-S3000
7DN-S3000
-HB,F1,F2
GND,+5
ROM
DRIVE
ATAPI
INTERFACE
9V5.0V
SWITCHING
POWER SUPPLY
ATAPI
interface
-HB,F1,F2
±9.0V
5.0V
Interface
TMP86CM47U
5.0V
ATAP
CPU
Ragurater
128M
D16~31
SDRAM
RAM
32bit BUS
ADRESS
ADSP21065L
TXD0A
TXD0B
DSP
SHOCK PROOF
TXD1BCLOCKTMP86CM47U
BUS
selectTXD1A
16Bit BusTCK1
D0~D15
DMA
D0~15
CPU DSP32.0M32.0M5v
BUS
interface
miconSERIAL 2
8M
FRASH
memory
3.3V
memo
4M
FRASHD/A
memory
RAM control
D0~D16
ADRESS
TFS0
TCK0
TFS1
FLAG
CONTROL
SYSTEM
CPU
MN102H730F
RAM10K
LRCK
BCLK
MAIN
D/A
DIT
AK4353
AMP
Trans
analog out
digital out
MAIN DOUT
256fs
DISCRV PULSEDISC
URN TABLEDIRTURN TABLE
SERIAL 1
UART
FW PULSE
UART
SERIAL 3
UART
DRIVER
PANEL
X'EFFECT IN
X'EFFECT OUT
3.3-5VFADER
adress
5v
DISC
SENSORSENSOR
TURN TABLE
ML9207
PANEL
µcom
ROM32k
RAM1k
LED out
Key scan
VR in
HB
FLTFLT Driver
CONTROL
motor
driver
Motor
7
Page 8
8DN-S3000
CONFIRMING THE SERVO
Required Measuring Implement
z Reference disc (TCD784 or CO-74176)
1. What is Service Program
Service program is a special program intended for confirming servo functions etc.
2. Contents of Service Program
Switch on the power while pushing the PITCH BEND + button and SCRATCH MODE button at the same time. After actuating
the servo program, select an aiming process number with the SELECT knob, A button, B button, SAMP button, or SAMP B
button. Press the SELECT knob to execute the selected process, the process number is then displayed on the track indicator
of the display. To exit from the service program, just switch off the power.
Process No.
(TRACK
Indication)
01
02
03
04
05
SELECT knob
06
07
Function
(Character-display)
com Version check
(Version No.)
OPEN/CLOSE
(Open Close)
Drive Diagnostic
(Drive_Diag)
Drive Data Read
(Data Read)
Error Code Check
(Error Data)
Total Running Time
(Total_Time)
Automatic
Servo Adjustment
call
Contents
Check Version with JOG dial.
1. System com version No.: “Sys_XXXX ”
2. DSP soft version No.: “Dsp_XXXX ”
3. ATAPI com version No.: “Atapi_XXXX ”
4. PANEL com version No.: “Panel_XXXX
5. ROM drive mecha. com version No.: “Drive_XXXX ”
Performs open/close each time when the SELECT knob is pushed.
ROM drive performs operation check when the SELECT knob is pushed, and
indicates the operational result. If the disc holder open, it starts the operation check
after closing. It indicates “Normal_End” if it ends normal. In case of error, ROM
drive error code is displayed in the character’s lower portion as “E
Starts continuous playback at its maximum reading speed from the beginning of
disc when the SELECT knob is pushed. It halts reading and stops if the knob is
pushed again.
Turn the PLATTER to display the logging error codes in the occurred order.
(“Error Data” is displayed.)
10 error logs are memorized at maximum.
Kinds of Error Code, displayed
Error Code Table (Appears only at Heat Run and Chucking Test function)
Pressing SELECT knob enters to data erase mode. (“Err Clear?” is displayed.)
If the SELECT knob is pushed again, the memorized error data are cleared.
Total time span of servo function that counted by the hour is displayed.
(“Total Time” is displayed.)
The display time is less than 65535 hours.
Note: No time is counted if powered down within 59 minutes.
Pressing SELECT knob enters to data erase mode. (“Time Clear?” is displayed.)
If the SELECT knob is pushed again, the memorized time data are cleared.
Starts automatic servo adjustment when the SELECT knob is pushed, and after
completing the adjustment, sort of the used disc is indicated. Data is selectable with
the PLATTER.
Starting with the PLAY/PAUSE button, it repeats open/close of the tray and
playback.
All tracks are played back if the track count is less than 20. Only the first and last
tracks are played back if the tracks are more than 21. When any errors, it stops
and indicates error code (see Error Code Table).
Starting with the PLAY/PAUSE button, it repeats open/close of the tray, servo on,
and TOC read.
The display shows the number of the tray operation. When any errors, it stops and
indicates error code (see Error Code Table).
It starts system check when the PLAY/PAUSE button is pushed, and indicates the
status by performing plain operational check in the system .
1. Communication judge between the system com and DSP
2. DSP SDRAM write/read operation check
3. Communication judge between the system com and ATAPI com
4. Communication judge between the ATAPI com and ROM drive
5. ROM drive operation check
After finishing the check, it indicates the result on the character display lower
portion.
When the 1. ~ 5. items are OK, their item numbers are indicated.
But if there is a NG item, its item number is not indicated.
Judges whether PLATTER can rotate at the specified rotating speed.
The message "Platter_OK" is displayed on the character display if the rotating
speed meets the specification. Otherwise, "Platter_NG" is displayed.
Detailed error can be displayed by PLATTER when error occurs.
10DN-S3000
Error Indication
TRMINSECFRAMCHARACTER
Displays the track
No. in which error
occurred.
Displays the time at which error occurred.“H
Operation count Error code
* * * *E * * *
”
5. System µcom and DSP Version Upgrade
System µcom and DSP can be upgraded in the following manner.
Version Upgrade Method
(1) Record the version upgrade software on a CD-R or CD-RW disc, only as one file with the format ISO9660 Mode-1.
The file name of the supplied version upgrade software should be used as is and this disc needs to finalize.
(2) After loading the disc made in above step 1, turn off the power. Then, turn on the power while pressing the NEXT TRACK
button and FAST SEARCH FWD () button. The version upgrade starts with reading data of the disc.
(3) When you start version upgrade operation, messages "Version_Up" and "System&DSP" are displayed on the character dis-
play.
Recovery positions are turned on one by one from the left end according as the upgrade operation proceeds. When this operation is completed, all recovery positions are turned on.
In case of some error or the power is turned off during the version upgrade, it may be impossible to operate at all thereafter.
Changing of IC502 on GU-3546 is necessary in this case, and software writing to IC502 should be done beforehand.
(4) When the upgrade is completed, the disk is ejected and operation returns to the normal mode.
(5) File name of the upgrade software indicates version numbers.
File nameT3.
System com
* * ** * *
version
. BIN
DSP version
6. ROM Drive (FG-5000) µcom Version Upgrade
Drive (FG-5000) µcom can be upgraded in the following manner.
Version Upgrade Method
(1) Record the version upgrade software on a CD-R or CD-RW disc, only as one file with the format ISO9660 Mode-1.
The file name of the supplied version upgrade software should be used as is and this disc needs to finalize.
(2) After turning on the power, load the disc made in above step 1 into the mecha. you want to upgrade the version.
(3) "Drive" and "Version UP?" are indicated in the character display. Press the CD EJECT button and remove the disc when not
upgrade the version.
(4) Press the PLAY/PAUSE to start the version upgrade. "Now Loading" is indicated.
(5) When the version upgrade is finished, "Complete" is indicated and the disc EJECT.
(6) Turn off the power once and turn on again after take out the disc.
The version upgrade ends in 20~30 seconds normally. If the power turned off underway or the version upgrade ends
abnormally, the drive may become malfunction. In such a case, version upgrade with PC will be needed.
(7) File name of the upgrade software indicates version number.
Only major semiconductors are shown, general semiconductors etc. are omitted to list.
主な半導体を記載しています。汎用の半導体は記載を省略しています。
1. IC’s
Note : Abbreviation ahead of IC No. indicates the name of P.W.B., etc.
注 ): ICNo. の前の記号は、基板の名称を表します。
DS : DSP P.W.B.
PA : PANEL P.W.B.
CD : CD-ROM P.W.B.
ADSP-21065L (DS: IC401)
208157
11DN-S3000
156
105
52
1
TOP VIEW
53
104
ADSP-21065L Terminal Function
Pin
No.
1VDDVDD VDD—————Power (+3.3V)
2RFS0YLRCKYLRCKI—IPu—H
3GNDGND GND —————GND
4RCLK0YBCKYBCKI————Receive frame sync (BCK) signal (Serial port IN 0)
5DR0AADDATA ADDATAI—IPu—HData receive A (serial port IN 0)
6DR0BI—IPu—HData receive B (serial port IN 0)
7TFS0YLRCKYLRCKI—IPu—H
8TCLK0YBCKYBCKI————Send frame sync (BCK) signal (Serial port OUT 0)
9VDDVDD VDD—————Power (+3.3V)
10GNDGND GND —————GND
11DT0AMOUT1MOUT2O—IPu—HData send A (Serial port OUT 0)
12DTOBDOUT1DOUT2O—IPu—HData send B (Serial port OUT 0)
13RFS1LRCK1LRCK2I—IPu—H
14GNDGND GND —————GND
15RCLK1BCK1BCK2I——L—Receive frame sync (BCK) signal (Serial port IN 1)
16DR1ASAMP2SAMP1I—IPu—HData receive A (serial por t IN 1)
17DR1BI—IPu—HData receive B (serial port IN 1)
18TFS1LRCK2LRCK1I/O—IPu—H
19TCLK1BCK2BCK1I/O————Send frame sync (BCK) signal (Serial port OUT 1)
20
21VDDVDD VDD—————Power (+3.3V)
22DT1ASOUT1SOUT2O—IPu—HData send A (Serial port OUT 1)
23DT1BSAMP1SAMP2O—IPu—HData send B (Serial port OUT 1)
24PWM_EVENT1I/O—Pd—LPWM1 output
25GNDGND GND —————GND
26PWM_EVENT0I/O—Pd—LPWM0 output
27BR1_I—Pu—HMulti-processing bus request 1
28BR2_I—Pu—HMulti-processing bus request 1
29VDDVDD VDD—————Power (+3.3V)
30CLKINI————Clock input
31XTAL_O————X’tal oscillator pin
32VDDVDD VDD—————Power (+3.3V)
Port Name
VDDVDD VDD—————Power (+3.3V)
Symbol
(IC301)
Symbol
(IC401)
I/ODETExtIni
Res
Receive frame sync (LRCK) signal (Serial port IN 0)
Send frame sync (LRCK) signal (Serial port OUT 0)
Receive frame sync (LRCK) signal (Serial port IN 1)
Send frame sync (LRCK) signal (Serial port OUT 1)
Function
11
Page 12
12DN-S3000
Pin
No.
33GNDGND GND —————GND
34SDCLK1O—Pd—LSDRAM clock enable 1
35GNDGND GND —————GND
36VDDVDD VDD—————Power (+3.3V)
37SDCLK0I/O————SDRAM clock enable 0
38DMAR1_I—PuHHDMA request 1
39DMAR2_I—PuHHDMA request 2
40HBR_I—Pu—HHost bus request (BOOT)
41GNDGND GND —————GND
42RAS_I/O—PuHHSDRAM row access strobe
43CAS_I/O—PuHHSDRAM column access strobe
44SDWE_I/O—PuHHSDRAM write enable
45VDDVDD VDD—————Power (+3.3V)
46DQMO————SDRAM data mask
47SDCKEI/O——H—SDRAM clock enable
48SDA10O—PdLLSDRAM A10
49GNDGND GND —————GND
50DMAG1_O——H—DMA ground 1
51DMAG2_O——H—DMA ground 2
52HBG_O——H—Host bus ground (BOOT)
53BMSTRO——H—Bus master output (H out)
54VDDVDD VDD—————Power (+3.3V)
55CS_I——LLChip select (BOOT)
56SBTS_I—PuHHExtend bus three state
57GNDGND GND —————GND
58WR_I/O————Memory write strobe
59RD_I/O————Memory read strobe
60GNDGND GND —————GND
61VDDVDD VDD—————Power (+3.3V)
62GNDGND GND —————GND
63REDYO————Host bus ACK
64SW_I/O————Sync type write select
65CPA_I/O————Core priority access
66VDDVDD VDD—————Power (+3.3V)
67VDDVDD VDD—————Power (+3.3V)
68GNDGND GND —————GND
69ACKI/O————Memory ACK
70MS0_I/O—PuHHMemory select 0
71MS1_I/O————Memory select 1
72GNDGND GND —————GND
73GNDGND GND —————GND
74MS2_I/O————Memory select 2
75MS3_I/O————Memory select 3
76FLAG11
77VDDVDD VDD—————Power (+3.3V)
78FLAG10
79FLAG9JOGB1JOGB2I————
80FLAG8JOGA1JOGA2I————
81GNDGND
82DATA0I/O————Ext. bus data 0
83DATA1I/O————Ext. bus data 1
84DATA2I/O————Ext. bus data 2
85VDDVDD VDD—————Power (+3.3V)
86DATA3I/O————Ext. bus data 3
87DATA4I/O————Ext. bus data 4
88DATA5I/O————Ext. bus data 5
89GNDGND GND —————GND
90DATA6I/O————Ext. bus data 6
91DATA7I/O————Ext. bus data 7
92DATA8I/O————Ext. bus data 8
93VDDVDD VDD—————Power (+3.3V)
94GNDGND GND —————GND
Port Name
Symbol
(IC301)
DMABSY1
SAMPCOP
Symbol
(IC401)
DMABSY2
SAMPCOPY
GND —————GND
I/ODETExtIni
O—Pu—HGeneral flag 11 (In DMA flag L: DMA)
I/O—Pu—HGeneral flag 10 (In SAMPLER copy flag)
Res
General flag 9 (JOG turning direction detect signal B)
General flag 8 (JOG turning direction detect signal A)
Function
12
Page 13
13DN-S3000
Pin
No.
95VDDVDD VDD—————Power (+3.3V)
96DATA9I/O————Ext. bus data 9
97DATA10I/O————Ext. bus data 10
98DATA11I/O————Ext. bus data 11
99GNDGND GND —————GND
100DATA12I/O————Ext. bus data 12
101DATA13I/O————Ext. bus data 13
102NC—————NC
103NC—————NC
104DATA14I/O————Ext. bus data 14
105VDDVDD VDD—————Power (+3.3V)
106GNDGND GND —————GND
107DATA15I/O————Ext. bus data 15
108DATA16I/O————Ext. bus data 16
109DATA17I/O————Ext. bus data 17
110VDDVDD VDD—————Power (+3.3V)
111DATA18I/O————Ext. bus data 18
112DATA19I/O————Ext. bus data 19
113DATA20I/O————Ext. bus data 20
114GNDGND GND —————GND
115NC—————NC
116DATA21I/O————Ext. bus data 21
117DATA22I/O————Ext. bus data 22
118DATA23I/O————Ext. bus data 23
119GNDGND GND —————GND
120VDDVDD VDD—————Power (+3.3V)
121DATA24I/O————Ext. bus data 24
122DATA25I/O————Ext. bus data 25
123DATA26I/O————Ext. bus data 26
124VDDVDD VDD—————Power (+3.3V)
125GNDGND GND —————GND
126DATA27I/O————Ext. bus data 27
127DATA28I/O————Ext. bus data 28
128DATA29I/O————Ext. bus data 29
129GNDGND GND —————GND
130VDDVDD VDD—————Power (+3.3V)
131VDDVDD VDD—————Power (+3.3V)
132DATA30I/O————Ext. bus data 30
133DATA31I/O————Ext. bus data 31
134 FLAG7DFLG12 DFLG22I/O—Pu—HGeneral flag 7 (RESERVE)
135GNDGND GND —————GND
136 FLAG6DFLG11 DFLG21I/O—Pu—HGeneral flag 6 (RESERVE)
137 FLAG5DTIMB1DTIMB2O————
138 FLAG4DTIMA1DTIMA2O————
139GNDGND GND —————GND
140VDDVDD VDD—————Power (+3.3V)
141VDDVDD VDD—————Power (+3.3V)
142NC—————NC
143 ID1I——LLMulti-processing ID1 (Single processor : 0)
144 ID0I——LLMulti-processing ID2 (Single processor : 0)
145 EMU_EMU1_EMU2_O————Emulation status
146
147 TRST_TRST1_TRST2_I—IPu—HTest reset (JTAG)
148 TDITDI1TDI2I—Pd—LTest data input (JTAG)
149 TMSTMS1TMS2I—IPu—HTest mode select (JTAG)
150GNDGND GND —————GND
151 TCKTCK1TCK2I—Pu—HTest clock (JTAG)
152 BSELI——HHEPROM boot select (Boot by EPROM: 1)
153 BMS_BMS1_BMS2_I——HHBoot memory select (Host processor boot: 1)
154GNDGND GND —————GND
155GNDGND GND —————GND
156VDDVDD VDD—————Power (+3.3V)
Port Name
TD0TD01TD02O————Test data output (JTAG)
Symbol
(IC301)
Symbol
(IC401)
I/ODETExtIni
Res
General flag 5 (Pulse output for generating monitor play time)
General flag 4 (Pulse output for generating main play time)
Function
13
Page 14
14DN-S3000
Pin
No.
157 RESET_DRES_DRES_I——HLDSP reset signal
158VDDVDD VDD—————Power (+3.3V)
159GNDGND GND —————GND
160 ADDR23I/O————Ext. bus address 23
161 ADDR22I/O————Ext. bus address 22
162 ADDR21I/O————Ext. bus address 21
163VDDVDD VDD—————Power (+3.3V)
164 ADDR20I/O————Ext. bus address 20
165 ADDR19I/O————Ext. bus address 19
166 ADDR18I/O————Ext. bus address 18
167GNDGND GND —————GND
168GNDGND GND —————GND
169 ADDR17I/O————Ext. bus address 17
170 ADDR16I/O————Ext. bus address 16
171 ADDR15I/O————Ext. bus address 15
172VDDVDD VDD—————Power (+3.3V)
173 ADDR14I/O————Ext. bus address 14
174 ADDR13I/O————Ext. bus address 13
175 ADDR12I/O————Ext. bus address 12
176VDDVDD VDD—————Power (+3.3V)
177GNDGND GND —————GND
178 ADDR11I/O————Ext. bus address 11
179 ADDR10I/O————Ext. bus address 10 (SDRAM: Connects SDA10)
180 ADDR9I/O————Ext. bus address 9
181GNDGND GND —————GND
182VDDVDD VDD—————Power (+3.3V)
183 ADDR8I/O————Ext. bus address 8
184 ADDR7I/O————Ext. bus address 7
185 ADDR6I/O————Ext. bus address 6
186GNDGND GND —————GND
187GNDGND GND —————GND
188 ADDR5I/O————Ext. bus address 5
189 ADDR4I/O————Ext. bus address 4
190 ADDR3I/O————Ext. bus address 3
191VDDVDD VDD—————Power (+3.3V)
192VDDVDD VDD—————Power (+3.3V)
193 ADDR2I/O————Ext. bus address 2
194 ADDR1I/O————Ext. bus address 1
195 ADDR0I/O————Ext. bus address 0
196GNDGND GND —————GND
197 FLAG0DR_/W1 DR_/W2I/O————General flag 0 (Command read write select)
198 FLAG1DACK1_ DACK2_I/O————General flag 1
199 FLAG2DBSY1DBSY2I/O————General flag 2
200VDDVDD VDD—————Power (+3.3V)
201 FLAG3DFLG10 DFLG20I/O—Pu—HGeneral flag 3 (RESERVE)
202NC——————
203NC——————
204GNDGND GND —————GND
205 IRQ0_DREQ1DREQ2I—Pu—HInterrupt request input 0 (SYS mcom interface)
206 IRQ1_DREQ1_ DREQ2_I—Pu—LInterrupt request input 1 (SYS mcom interface)
207 IRQ2_JOGINT1 JOGINT2I————
208
2XSRFINI/AAnalog RF signal input after passing through the equalizer
3XSIPINI/AInverting input pin of data slicer
5XSDSSLVO/ASlice level output pin
6XSRSLINTI/AReference current setting pin for analog data slicer
8XSAWRCO/AOutput for enlarge VCO range. Analog output from DAC buffer
9XSRFGCO/ARF gain control output
10XSEFGCO/AE,F gain control output
11
XSFOCUSO/AOutput voltage level for focusing buffer IC
12XSTRACKO/A Output voltage level for tracking buffer IC
13XSSLEGO/AOutput voltage level for sledge buffer IC
15XSMOTORO/AOutput voltage level for spindle motor buffer IC
17XSRFRPLPI/AHigh bandwidth low pass filter input for RFRP
18XSTELPI/AHigh bandwidth low pass filter input for TE
19XSVREF2I/A2.1V reference voltage input
20XSRFRPI/ARF ripple/envelope signal input
21XSTEXII/ATracking zero crossing input signal
23XSTEII/ATracking error input signal
24XSFEII/AFocus error input signal
25
XSCEII/A
1. Center error input signal
2. Photo Interrupt input
DescriptionPin No.
PC
MPEG
DEC.
15
Page 16
16DN-S3000
Pin Name
27XSSBADI/ASub-beam addition signal input
166XSPDIREFI/A
167XSFDIREFI/A
169XSPLLFTR2I/AData PLL loop filter pin#2
171XSFDOO/AOutput node of frequency detector charge pump circuit
172XSFTROPII/AInput node of loop filter OP circuit
173XSVR_PLLI/APLL reference voltage input
174XSPDOFTR2I/APhase detector filter pin#1
175XSVREFOO/AReference voltage output
176XSAWRCVCOI/AAuto Wide Range Control of VCO input pin. For enlarge VCO range in CAV mode
29XSDFCTIDetect detection signal input
30XSCSJOChip select signal for accessing control registers
31XSCLKOClock output for accessing control registers
32XSDATAI/ORegisters data input/output pin
33XSLDCOLaser diode on/off control output for both CD/DVD
34XSFGINIMotor Hall sensor input
35XSSPDONOSpindle motor on output
36, 37, 38, 39 XSFLAG[3:0]OThese pins are used to monitor some status of servo control block
48, 51, 52XGPIO[2:0]I/O
40XMP1_7I/OInternal microcontroller programmable I/O port 1.7.
41XMP1_6I/OInternal microcontroller programmable I/O port 1.6.
43XMP1_5I/OThis pin is now changed to be NC.
44XMP1_4I/OInternal microcontroller programmable I/O port 1.4.
45XMP1_3I/OInternal microcontroller programmable I/O port 1.3.
47XMP1_2I/OInternal microcontroller programmable I/O port 1.2.
49XMP1_1I/OInternal microcontroller programmable I/O port 1.1.
57XMP1_0I/O
46XMFSCSJI/OOutput chip select connected to external flash ROM chip enable pin
54XMPSENJI/OOutput program store enable connected to external ROM PSENJ pin.
56XMALEI/OThis signal is used as address latch signal in address/data mux mode
70XMCSJI/O
71XMRDJI/O
72XMWRJI/OThis signal is used as the Wire Strobe signal
73XMINT1JI/O
74, 75, 77, 78,
79, 80, 81, 82,
83, 84, 85, 86,
87, 89, 90, 91
62, 63, 64, 65,
66, 67, 68, 69bus for the 8-bit processor mode.
163XTPLCKI/OPLCK test pin
164XTSLRFI/OSLRF test pin
59XOSC1ICrystal input/System clock. The input frequency from outside crystal or oscillator is 33.8688MHz
60
53XCRSTJI
94XHCS1JIThis pin is used to select the command block task file registers
93XHCS3JIThis pin is used to select the control block task file registers
103XHIORJIAsserted by the host during a host I/O read operation
104XHIOWJIAsserted by the host during a host I/O write operation
105
101XHDACKJI
99XHCS16JO
50XHRSTJIHost Reset. The reset of ATA bus
100XHINTO
XMA[15:0]I/OThese pins are used as address bus
XMD[7:0]I/O
XOSC2OCrystal output
XHDRQO
Type
Phase detector reference current generator. Connect a resistor between this pin and
ground to set reference current
Frequency detector reference current generator. Connect a resistor between this pin and
ground to set reference current
1. These pins are used as general purpose I/O bus
2. When use internal microcontroller, XGPIO[2] can be used as programmable I/O port 3.6.
Internal microcontroller programmable I/O port 1.0.
This pin is default used as the A16 (microcontroller address line 16)
1. This signal must be asserted for all microcontroller accesses to the register of this chip
2. When use internal microcontroller, this signal can be used as programmable I/O port 3.1
1. This signal is used as the Read Strobe signal
2. When use internal microcontroller, this signal can be used as programmable I/O port 3.0
1. This signal is an interrupt line to the microcontroller
2. When use internal microcontroller, this signal can be used as programmable I/O port 3.7
These pins are used as data bus for the 16-bit processor mode, or the address/data mux
Chip Reset. As asserted low input generates a component reset that stops all operations within
the chip and deasserts all output signals. All input/output signals are set to input.
DMA request. This pin is configured as the DMA request signal, and is used during DMA transfer
1.
between the host and the controller. This pin is tri-stated when DMA transfers are not enabled.
2.
MPEG acknowledge. This pin is used as the ACKJ signal when MPEG interface mode is selected.
1. DMA acknowledge. This pin is configured as DACKJ, and is used as the DMA acknowledge
signal during DMA data transfers.
2. MPEG request. This pin is used as the REQ signal when MPEG interface mode is selected
1. 16-bit data select. This signal indicates that a 16-bit data transfer is active on the host data
bus. This pin is open-drain tri-state output.
2. MPEG clock. This pin is used as the CLOCK signal when MPEG interface mode is selected.
1. Host interface request. This tri-state pin is the host interrupt request, and is asserted to
indicate to the host that the controller needs attention.
2. MPEG begin. This pin is used as the BEGIN signal when MPEG interface mode is selected
DescriptionPin No.
16
Page 17
17DN-S3000
Pin Name
97XHPDIAGJI/OThis pin is used as the Passed Diagnostics signal, and may be an input or an open-drain output
92XHDASPJI/O
102XHIORDYI/O
95, 96, 98XHA[2:0]I
106, 107, 108,2.
109, 111, 112,3. VCD I/F. Bit3-0 are used as VCD I/F signal when VCD function is enabled. The relationship of
113, 114, 116,bit3-0 and VCD I/F is as follow
117, 118, 119,HD0—CD-DATA
120, 121, 122,HD1—CD-LRCK
123HD2—CD-BCK
143XRSDCLKOThis signal is the clock output for SDRAM
147XROEJO
142XRWEJOThis signal is asserted low when a buffer memory write operation is active
124, 125, 126,
127, 128, 129,
131, 132, 134,
135, 136, 137,
138, 139, 140,
141
4AVDD5_DSAnalog Power +5V for Data Slicer part
14AVDD5_D
26AVDD5_ADAnalog Power +5V for ADC part
168AVDD5_PLAnalog Power +5V for Data PLL part
7, 55, 58, 76,
115, 146,
150, 162
1AVSS_DSAnalog Ground for Data Slicer part
16AVSS_DAAnalog Ground for DAC part
22AVSS_ADAnalog Ground for ADC part
170AVSS_PLAnalog Ground for Data PLL part
28, 42, 61,
88, 110, 130,
138, 154, 165
XHD[15.0]I/O
XRA[11:0]O1: Normal operation
XRD[15:0]
VDDPower +3.3V for digital core logic and pad
GNDDigital Ground core logic and pad.
Type
This pin is used as the Drive Active/Slave Present signal, and is an input or an open-drain
output. This pin is used for Master/Slave drive communication and/or for driving an LED
1. I/O channel ready. This signal is driven low to extend host transfer cycles when the controller
is not ready to respond. This pin will be tri-stated when a read or write is not in progress.
2. MPEG error. This pin is used as the ERROR signal when MPEG interface mode is selected
Host address lines. The host address lines A[2:0] are used to access the various host control,
status, and data registers
1. Host data bus. This bus is used to transfer data and status between the host and the controller.
MPEG data bus 7-8. The HD[7:0] are used as the DATA [7:0] when MPEG interface mode is selected.
HD3—CD-C2PO
This signal is used as the memory output enable for external DRAM buffers. After RSTJ is
asserted, this signal will be low
This signal is used as Row address output to external DRAM buffer. After RSTJ is asserted, this
signal will be high
This signal is used as column address output to external DRAM. After RSTJ is asserted, this
signal will be high
1. RAM address lines. These are bits11-0 for addressing the buffer memory.
2. Hardware setting. The bits6-0 are used as hardware setting for some functions.
RA[9] : FLASH size is 64K/128K
1: FLASH size is 64K
0: FLASH size is 128K
RA[8] : External CPU is 8032/H8
1: 8032
0: H8
RA[7] : Microcontroller programmable I/O port 1 pin control
1: By internal microcontroller
0: By registers to decide input/output
RA[6] : System test pin output
0: System test pin output
RA[5] : For testing purpose, donít need to set
RA[4] : IDE master/slave
1: Slave
0: Master
RA[3] : For testing purpose, donít need to set
RA[2] : For testing purpose, donít need to set
RA[1-0] : MCU Mode selection
11: Normal Mode (internal uP, internal address latch)
10: Outside uP Mode (ICE Mode)
01: Test mode for internal uP testing
00: Internal uP mode with external address latch
I/OThese signals are the 8-bit parallel data lines to/from the buffer memory.
AAnalog Power +5V for DAC part
DescriptionPin No.
17
Page 18
MN102H730F (DS: IC501)
18DN-S3000
9665
9764
TOP VIEW
12833
132
MN102H730F Terminal Function
Pin
No.
1CS0_CS0_O—Pu——Ext. memory chip select 0 (Flash ROM CS)
2CS1_CS1_O—Pu——Ext. memory chip select 1 (Flash ROM for memo)
3D00DQ0I/O————Ext. memory data in/output 0, DSP interface 0
4D01DQ1I/O————Ext. memory data in/output 1, DSP interface 1
5D02DQ2I/O————Ext. memory data in/output 2, DSP interface 2
6D03DQ3I/O————Ext. memory data in/output 3, DSP interface 3
7VDDVDD—————
8VSSVSS—————GND
9D04DQ4I/O————Ext. memory data in/output 4, DSP interface 4
10D05DQ5I/O————Ext. memory data in/output 5, DSP interface 5
11D06DQ6I/O————Ext. memory data in/output 6, DSP interface 6
12D07DQ7I/O
13D08DQ8———
14D09DQ9———
15D10DQ10———
16PD0,DMAACK1_RESERVE—
17PD1,DMAREQ1_RESERVE—
18D11DQ11———
19D12DQ12———
20D13DQ13———
21D14DQ14———
22D15DQ15———
23WORDWORDI——Data bus width select (H: 16bit), GND fixed
24VDDVDD—————Power (+3.3V)
25MODEMODEI——LLProcessor mode, GND fixed
Pin Name
Symbol
DETExtIniRes
I/O
Power (+3.3V)
————Ext. memory data in/output 7, DSP interface 7
—
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
—
—
—
O
—
O
—
—
—
—
—
L—
L—
Ext. memory data in/output 8, DSP interface 8
Ext. memory data in/output 9, DSP interface 9
Ext. memory data in/output 10, DSP interface 10
Ext. memory data in/output 11, DSP interface 11
Ext. memory data in/output 12, DSP interface 12
Ext. memory data in/output 13, DSP interface 13
Ext. memory data in/output 14, DSP interface 14
Ext. memory data in/output 15, DSP interface 15
Function
18
Page 19
19DN-S3000
Pin
No.
26PC3MUTEO—PuHHMute signal (H: Mute)
27XIXII————Oscillation input
28XOXOO————Oscillation output
29VDDVDD—————Power (+3.3V)
30OSCIOSCII————Oscillation input, 32.0MHz
31OSCOOSCOO————Oscillation output
32VSSVSS—————
33P57,BOSCTEST
34PC5,NMII——
35RST_RST_I—
36PC0YMCLKO—
37P76TESTO—Pu—P.W.B. check mode IN
38P60,IRQ0DTIMAI— PuHHMain playback clock input
39P61,IRQ1DTIMBI— PuHHMonitor playback clock input
40P62,IRQ2,TM10IOA TABLEI—(Pu)HHClock pulse input for platter
41P63,IRQ3,TM10IOA CLK4MI——Clock pulse input for platter
42P64,IRQ4ATANS_I—(Pu)—HATAPI µcom serial interface
43P65,IRQ5,TM12IOA DISCPAI—(Pu)HHClock pulse input for scratch disc
44P66,IRQ6DISCDIRI—(Pu)HHDirection pulse input for scratch disc
45P67,IRQ7DISCINTI—(Pu)HH
46P70,TM13IOBDISCAI—
47P71YMDATAO——H—AK4353 output data
48PD2,DMAACK0_NRES_O—PdLLAK4353 reset signal
49PD3,TM3IODISCPA_I———
50
51P77RESERVE
52P72,TM14IOBDISCPBI————SCRATCH for DISC pulse B count input
53P73O——L
54P74
55P75,TM12IOBCLK4MI————Clock pulse input for disc
56PA0,SBI0RXD1I—(Pu)—HData receive from PANEL
57PA1,SBO0TXD1O—PuHHData send to PANEL (PU µcom specify)
58PA2,SBT0MCMD_O—PuHHATAPI µcom serial interface (PU µcom specify)
59PA3,SBI1X'RXDOUTI—(Pd)—HData receive from X'EFFECT OUT
60PA4,SBO1X'TXDOUTO—PuHHData send to X'EFFECT OUT
6 1PA5
62PB0,SBI2X’RXD INI—(Pd)—HData receive from X’EFFECT IN
63PB1,SBO2X’TXD INO—PuHHData send to X’EFFECT IN
64PB2APRES_O—PdLLATAPI µcom reset signal
65PB3,SBI3ATDATAI—(Pu)—HATAPI µcom serial receive signal
66PB4,SBO3MDATAO—H
67PB5,SBT3MCLKO——
68VDDVDD—————Power (+3.3V)
69VSSVSS—————GND
70AVSSAVSS—————Analog ref. GND for A/D conversion, GND
71VrefVref—————Analog ref. V for A/D conversion, GND
72P80DFLG2I/O—Pu—HDSP gener al flag 2
73P81DFLG1I/O—Pu—HDSP gener al flag 1
74P82DR_/W1O——H—DSP interf ace send/receive select signal
75P83DACK_I—PuHHDSP interf ace ACK
76P84DBSY_I—Pu
77P85DFLG0I/O—Pu—
78P86DREQ_O—PuHH
79P87FPLAY1I—Main fader start PLAY input
80PD4FCUE1
81PD5I—H
82P90I—
83P91RESERVEO——L—
84P92PNLRST—LL
85P93APOWERO—Pd
86Vref+Vref+—————Analog ref. V for A/D conversion, +3.3V
87AVDDAVDD—————Power (+3.3V)
Pin Name
VDDVDD—————P—ower (+3.3V)
Symbol
NMI
RESERVE
RESERVE
RESERVE
TESTIN1
TESTIN2
I/O
DETExtIniRes
GND
I—32.0MHz output
O——
O—
O—
I—(Pu)HHMain fader start CUE input
———
——
—
———
—L
—L
—L
—
(Pu)
Pu
Pu
—Pd
—
—
Connect to Power
—
µcom reset
H—Clock for AK4353 data
—
—
—
Start pulse input for scratch disc
SCRATCH for DISC pulse A count input
Clock invert pulse input for scratch disc
—
—
—
—
ATAPI µcom serial send signal
—
HATAPI µcom serial send/receive clock
HHDSP interf ace busy signal
HDSP gener al flag 0
DSP interf ace request signal
HH
—
—
H
Panel µcom reset signal (L:Reset)
L
LAnalog output voltage ON/OFF (L:OFF)
Function
19
Page 20
20DN-S3000
Pin
No.
88P94MCNT0O—PuLLMotor control signal 0
89P95MCNT1O—Pu
90P96,DAC2MCNTDAO—L
91P97,DAC3RESERVEO——H—
92BREQ_BREQ_I—(Pu)HHBus request signal
93BRACK_BRACK_O—PuHHBus request accept signal
94WEL_WE_O—Pu—HExt. memory write enable (Lower 8bit)
95P51RESERVEO——H—
96RE_RE_O—Pu—HExt. memory read enable
97CS2_CS2_O—Pu—HExt. memory chip select 2 (DSP1 interface)
98VDDVDD—————Power (+3.3V)
99VSSVSS—————GND
100 P54, BSTREMLO——H—AK4353 chip select
101 P55, WR_RESERVEO——H—
102 CS3_CS3_O————Not used
103 A00A00O————Ext. memory address bus 0
104 A01A01O————Ext. memory address bus 1
105 A02A02O————Ext. memory address bus 2
106 A03A03O————Ext. memory address bus 3
107 A04A04O————Ext. memory address bus 4
108 A05A05O————Ext. memory address bus 5
109 A06A06O————Ext. memory address bus 6
110 A07A07O————Ext. memory address bus 7
111 A08A08O————Ext. memory address bus 8
112 PD6RESERVEO——L—
113 PD7,TM7IOI—
114 A09A09
115 A10A10O————Ext. memory address bus 10
116 A11
117 A12A12O————Ext. memory address bus 12
118 A13A13O————Ext. memory address bus 13
119 VDDVDD—————Power (+3.3V)
120 PC4RESERVEO——L—
121 A14A14O————Ext. memory address bus 14
122 A15A15O————Ext. memory address bus 15
123 A16A16O————Ext. memory address bus 16
124 A17A17O—Pu——Ext. memory address bus 17
125 A18A18O—Pu——Ext. memory address bus 18
126 A19A19O—Pu——Ext. memory address bus 19
127 A20A20O—Pu——Ext. memory address bus 20
128 A21A21O—Pu——Ext. memory address bus 21
Analog inputs for RF Single Buffer. Differential analog inputs to the RF single-ended output buffer
and full wave rectifier
Low Impedance Enable. A TTL compatible input pin that activates the FDCHG switches. A low
32FDCHG#I
level activates the switches and the falling edge of the internal FDCHG triggers the fast decay for
the MIRR bottom hold circuit. (open high)
49HOLD1I
Hold Control. A TLL compatible control pin which, when pulled high, disables the RF AGC charge
pump and holds the RF AGC amplifier gain at its present value. (open high)
11~14D, C, B, AIPhoto Detector Interface Inputs. Inputs from the main beam Photo detector matrix outputs
5~8A2, B2, C2, D2I
Photo Detector Interface Inputs. AC coupled inputs for the DPD from the main beam Photo
detector matrix outputs
15~16F, EICD tracking Error Inputs. Inputs from the CD photo detector error outputs.
3~4PD1, PD2ICD Photo detector Interface Inputs. Inputs from the CD photo detector error outputs
40MEIIMirror Envelope Inputs. The SIGO envelope input pin
35MINI
RF signal Input for Mirror. AC coupled inputs for the mirror detection circuit from the pull-in signal
(PI)
output.
21DVDPDIAPC Input. DVD APC input pin from the monitor photo diode
23CDPDIAPC Input. CD APC input pin from the monitor photo diode
25LDON#IAPC Output On/Off. APC output control pin. A low level activates the LD output. (open high)
22DVDLDOAPC output. DVD APC output pin to control the laser power
24CDLDOAPC output. CD APC output pin to control the laser power
56BYPI/OThe RF AGC integration capacitor CBYP, is connected between BYP and VPA
9CPI/O
10CNI/O
45LCP—Center Error LPF pin. An external capacitance is connected between this pin and the LCN pin
44LCN—Center Error LPF pin. An external capacitance is connected between this pin and the LCP pin
30MP—MIRR signal Peak hold pin. An external capacitance is connected to between this pin and VPB
31MB—MIRR signal Bottom hold pin. An external capacitance is connected to between this pin and VPB
39MEV—Sigo Bottom Envelope pin. An external capacitance is connected to between this pin and VPB
17CDTE—CD Tracking. E-F Opamp output for feedback
38TPH—PI Top Hold pin. An external capacitance is connected to between this pin and VPB
26VC—
27
18VCI2—Reference Voltage input. DC bias voltage input for the servo input reference
55RX—
33MLPF—MIRR signal LPF pin. An external capacitance is connected between this pin and VPB
19NC—No Connect
48SDENI
47SDATAI/O
46SCLKI
58VPAPower. Power supply pin for the RF block and serial port
28VPBPower. Power supply pin for the servo block
50VNAGround. Ground pin for the RF block and serial port
20VNBGround. Ground pin for the servo bolck
VCI—Reference Voltage input. DC bias voltage input for the servo input reference
Type
Defect Output. Pseudo CMOS output. When a defect is detected, the DFT output goes high. Also
the servo AGC output can be monitored at this pin, when CAR bits 7-4 are ‘0011’
Pull-in Signal Output. The summing signal output of A, B, C, D or PD1, PD2 for mirror detection.
Reference to VCI
Differential Phase tracking LPF pin. An external capacitance is connected between this pin and
the CN pin
Differential Phase tracking LPF pin. An external capacitance is connected between this pin and
the CP pin
Reference Voltage output. This pin provides the internal DC bias reference voltage (+2.5V lix).
Output Impedance is less than 50ohms
Reference Resistor Input. An external 8.2kohm, 1% resistor is connected from this pin to ground
to establish a precise PTAT (proportional to absolute temperature) reference current for the filter
Serial Data Enable. Serial Enable CMOS input. A high level input enable the serial port (Not to be
left open)
Serial Data. Serial data bi-directional CMOS pin. NRZ programming data for the internal registers
is applied to this input ( Not to be left open)
Serial Clock. Serial Clock CMOS input. The clock applied to this pin is synchronized with the data
applied to SDATA (Not to be left open)
DescriptionPin No.
25
Page 26
TMP86CM47U-4V14 (PA: IC102)
33
26DN-S3000
23
34
22
TOP VIEW
44
1
12
11
TMP86CM47U-4V14 Terminal Function
Pin No.Pin NameSymbolI/ODET ExtIniResFunction
1VssVss-----GND (0V)
2XINXINI----Oscillation input 16.0MHz
3XOUTXOUTO----Oscillation output
4TESTTESTI----Fixed to L
5VddVdd-----Power (+5.0V)
6P21PITCHLEDO-PuHHLED ON/OFF (L:ON)
7P22EJECTLEDO-PuHHLED ON/OFF (L:ON)
8RESET_RST_I----ucom RESET
9P20LED4O-PuHHLED ON/OFF (L:ON)
10P00TRSBI-Pu-HTrack select encoder B input
11P01PM LEDO-PuHHLED ON/OFF (L:ON)
12P02RXDI-Pu-HData receive from main unit
13P03TXDO-PuHHData send to main unit
14P04FLDAO-PuHHML9207 data signal
15P05FLCS_O-PuHHML9207 latch signal
16P06FLCP_O-PuHHClock signal for ML9207 data output
17P07NEXT LEDO-PuHHLED ON/OFF (L:ON)
18P17KIN5I-Pu-HKey scan input 5
19P16KIN4I-Pu-HKey scan input 4
20P15KIN3I-Pu-HKey scan input 3
21P14KIN2I-Pu-HKey scan input 2
22P13KIN1I-Pu-HKey scan input 1
23P12KIN0I-Pu-HKey scan input 0
24P11TRSAIEdPu-HTrack select encoder A interrupt input
25P10FLRES_O-PdLLML9207 reset signal
26P30PITCHI----Pitch VR signal
27P31PITCHCI----Pitch VR center value signal
28P32MAIN LEDO-PuHHLED ON/OFF (L:ON)
29P33SAMP LEDO-PuHHLED ON/OFF (L:ON)
30P34DISC LEDO-PuHHLED ON/OFF (L:ON)
31P35KINADI-PuÅ|HKey A/D input
32P36PLAYI/O-PuHHPLAY/PAUSE key scan (PLAY/PAUSE LED L:ON)
33P37CUEI/O-PuHHCUE key scan (CUE LED L:ON)
34VAREFVAREFI----Power (+5.0V), Analog ref. V for A/D conversion
35AVDDAVDDI----Power (+5.0V), For A/D conversion circuit only
36AVSSAVSSI----GND (0V), Analog GND for A/D conversion
37P40KOUT0O-PuHHKey scan output 0/LED line select 0 (L: Select)
38P41KOUT1O-PuHHKey scan output 1/LED line select 1 (L: Select)
39P42KOUT2I/O-PuHHKey scan output 2/ (Other than scan, IN)
40P43KOUT3I/O-PuHHKey scan output 3/ (Other than scan, IN)
41P44LED0O--H-LED ON/OFF0 (L:ON)
42P45LED1O--H-LED ON/OFF1
43P46LED2O--H-LED ON/OFF2
44P47LED3O--H-LED ON/OFF3
*Pd or Pu detected in input port when power on, Pd=CD1, Pu=CD2
26
Page 27
TMP86CM47U-3RD2 (DS: IC151)
27DN-S3000
33
34
23
22
TOP VIEW
44
1
11
TMP86CM47U-3RD2 Terminal Function
Pin
No.
1VSSVSS—————GND (0V)
2XINXINI————Oscillation input 8.0MHz
3XOUTXOUTO————Oscillation output
4TESTTESTI————Fixed to L
5VDDVDD—————Power (+3.3V)
6P21(LED)DVSELO—PuLHNot used
7P22BREQ1_O—PuHHSystem µcom bus request
8RESET_RST_I————µcom reset
9P20DRLCHO—PuHHATAPI data register latch signal, H: Latch
10P00(INT0)MCMD_I————System µcom serial interface
11P01DMAO—PuLHATAPI DMA mode select (H: DMA)
12P02DMABSY1I—Pu—HIn DMA flag (L: DMA data transfer)
13P03ATANSO—PuHHSystem µcom serial interface
14P04(SO)ATDATAO—PuHHSystem µcom serial data receive signal
15P05(SI)MDATAI————System µcom serial data send signal
16P06(SCK_)MCLKI————System µcom serial send/receive clock
17P07(INT4/LED)BSYIN_I———HTXD BUSY input
18P17BSYOUT_O—PuHHTXD BUSY output signal (L: BUSY)
19P16DRES_O—PdLLDSP reset (L: Reset)
20P15DMAR_/WI/O—Pu/PdHL/HATAPI DMA direction select (L: Read) *
21P14RD_O——H—ATAPI read strobe
22P13WR_O——H—ATAPI write strobe
23P12(INT2)INTRQILv———ATAPI interrupt request signal
24P11(INT1)DMARQILvPd——ATAPI DMA request signal (Pd with 5.6kW)
25P10IORDYI—Pu—H
26P30D0I/O—PdLLATAPI data bus 0 (APRES_ATAPI reset)
27P31D1I/O————ATAPI data bus 1 (CS1 device register chip select 1)
28P32D2I/O————ATAPI data bus 2 (CS0 device register chip select 0)
29P33D3I/O————ATAPI data bus 3 (DA2 device register select 2)
30P34D4I/O————ATAPI data bus 4 (DA1 device register select 1)
31P35D5I/O————ATAPI data bus 5 (DA0 device register select 0)
32P36D6I/O————ATAPI data bus 6
33P37D7I/O————ATAPI data bus 7
34VAREFVAREFI————
35AVDDAVDDI————Power (+3.3V), Power for A/D conversion circuit only
36AVSSAVSSI————GND (0V), Analog GND for A/D conversion
37P40D8I/O————ATAPI data bus 8
38P41D9I/O————ATAPI data bus 9
39P42D10I/O————ATAPI data bus 10
40P43D11I/O————ATAPI data bus 11
41P44D12I/O————ATAPI data bus 12
42P45D13I/O————ATAPI data bus 13
43P46D14I/O————ATAPI data bus 14
44P47D15I/O————ATAPI data bus 15
* Pd or Pu detected in input port when power on, Pd=CD1, Pu=CD2
Pin NameSymbolDETExtIniRes
12
FunctionI/O
ATAPI data transfer cycle extend request signal (Pu with 1.0kW)
GND (0V), Analog ref. V for A/D conversion, A/D not used
27
Page 28
W29EE011P (CD: IC507)
A12
A15
A16NCVDDWENC
303132
1234
A7
5
A6
6
A5
7
A4
8
A3
A2
A1
A0
DQ0
TOP
9
VIEW
10
11
12
13
14 15 16 17 18 19 20
DQ1
DQ2
DQ3
GND
DQ4
DQ5
29
28
27
26
25
24
23
22
21
DQ6
A14
A13
A8
A9
A11
OE
A10
CE
DQ7
V
V
CE
OE
WE
A0
A16
DD
SS
.
.
.
.
.
.
.
CONTROL
DECODER
OUTPUT
BUFFER
CORE
ARRA
28DN-S3000
Terminal Function
DQ0
:
7
DQ
Y
NameFunction
A0 - A16
DQ0 - DQ7
CE
OE
WE
VDD
GND
NC
Address Inputs
Data Inputs/Outputs
Chip Enable
Output Enable
Write Enable
Power Supply
Ground
No Connection
9CP1 Capacitor pin 1 for charge pump
10CP2 Capacitor pin 2 for charge pump
11VGCapacitor connection pin for charge pump
12CNF Capacitor connection pin for phase compensation
13SBShort Brake Pin
14VCC Power supply for signal division
15VMPower supply for driver
16ECR Torque control standard voltage input terminal
17ECTorque control voltage input terminal
18PSPower Save in
19 RNF2 Resistor connection pin for current sense
20A3Output3 for motor
21 RNF1 Resistor connection pin for current sense
22A2Output2 for motor
23 RNF1 Resistor connection pin for current sense
24A1Output1 for motor
25VMPower supply for driver
26VHHall bias pin
27FGFG output pin
28FG3 FG3 output pin
Function
28
Page 29
BA5954FP (CD: IC509)
BA5954FP Terminal Function
Pin
No.
1VINFC Focus driver input
2 CFCerr1 Cap. connection pin for error amp filter
3 CFCerr2 Cap. connection pin for error amp filter
4 VINSL+ Op. amp input (+) for sled driver
5 VINSL- Op. amp input (-) for sled driver
6VOSL Op. amp output for sled driver
7 VNFFC Focus driver feedback pin
8VccPre Vcc, power Vcc for sled driver
9PVcc1 Power Vcc for loading driver
10 PGND Power GND
11 VOSL- Output (-) of sled driver
12 VOSL+ Output (+) of sled driver
13 VOFC- Output (-) of focus driver
14 VOFC+ Output (+) of focus driver
28
10k
STAND
BY
THERMAL
SHUT DOWN
20k
7.5k
10k
1272263254245236227
Pin
Name
7.5k
20k
7.5k
Function
DET.AMP.
x2
7.5k
x2
DET.AMP.
15
16
17
18
19
20
21
Pin
PGNDPreGND
LOADING
DRIVER
SLED
DRIVER
PGND
11
10
9
ACTUATOR
DRIVER
ACTUATOR
DRIVER
14
13
12
Function
PVcc2
10k15k
10k
25k
Pin
No.
Vcc PVcc1
8
Name
15 VOTK+ Output (+) of tracking driver
16 VOTK- Output (-) of tracking driver
17 VOLD+ Output (+) of loading driver
18 VOLD- Output (-) of loading driver
19 PGND Power GND
20 VNFTK Tracking driver feedback pin
21 PVcc2 Power Vcc for actuator driver
22 PreGND Pre GND
23 VINLD Loading driver input
24 CTKerr2 Cap. connection pin for error amp filter
25 CTKerr1 Cap. connection pin for error amp filter
26 VINTK Tracking driver input
27BIAS Bias input
28 STBY Standby pin
PVcc1
PVcc2
Vcc
29DN-S3000
AK4353VF (DS: IC709)
1MCKO
TX
DVDD
DVSS
MCKI
BICK
SDTI7
LRCK8
CSN
SCL/CCLK11
SDA/CDTI12
2
3
4
5
6
9PDN
10
Top
View
Block Diagram
DZF
24
NC
23
AVDD
22
AVSS
21
VCOM
20
AOUTL
19
AOUTR
18
CAD1
17
CAD0
16
I2C
15
TTL
14
TST
13
TX
LRCK
BICK
SDTI
TTL
DVDD
DVSS
DZF
CAD0CAD1
DIT
Serial Input
Interface
Mixer
PDN
I2C
ATT
ATT
CCLK CDTICSN
8X
Interpolator
8X
Interpolator
Clock Generator
MCKI
∆Σ
Modulator
∆Σ
Modulator
MCKO
LPF
LPF
AVDD
AVSS
VCOM
AOUTL
AOUTR
29
Page 30
AK4353VF Terminal Function
No.Pin NameI/ ODescription
1MCKOOMaster Clock Output Pin
2TXOTransmit Channel Output Pin
3DVDD4DVSS-Digital Ground Pin, 0V
5MCKIIMaster Clock Input Pin
6BICKISerial Data Clock Pin
7SDTIISerial Data Input Pin
8LRCKISerial Input Channel Clock Pin
9P D NIPower- Down Pi n
10CSNIChip Select Pin at 3-wire Serial control mode
SCLIControl Clock Pin at I2C bus control mode11
CCLKIControl Clock Pin at 3-wire serial control mode
SDAI/OControl Data Input/Output Pin at I2C Bus control mode12
CDTIIControl Data Input Pin at 3-wire serial control mode
13TSTITest pin
14TTLIDigital Input Level Select Pin
15I2CIControl Mode Select Pin
16CAD0IChip Address Select 0 Pin
17CAD1IChip Address Select 1 Pin
18AOUTRORch Analog Output Pin
19AOUTLOLch Analog Output Pin
20VCOMOCommon Voltage Output Pin, AVDD/2
21AVSS-Analog Ground Pin
22AVDD-Analog Power Supply Pin
23NC-No Connect
24DZFOZero Input Detect Pin
Same frequency as MCKI is output
Digital Power Supply Pin, +2.7∼+5.5V
When “L”, the circuit is in power-down mode.
The AK4353 should always be reset upon power-up.
2
This pin should be connected to DVDD at I
C Bus control mode.
This pin should be connected to DVDD.
“L”: CMOS, “H”: TTL
“L”: 3-wire Serial, “H”: I
2
C Bus
Used for analog common voltage.
Large external capacitor is used to reduce power supply noise.
Nothing should be connected externally to this pin.
When SDTI follows a total 8192 LRCK cycles with “0” input data
or RSTN = “0”, this pin goes to “H”.
l Part indicated with the mark "" are not always in stock and possibly to
take a long period of time for supplying, or in some case supplying of
part may be refused.
l When ordering of part, clearly indicate "1" and "I" (i) to avoid mis-
supplying.
l Ordering part without stating its part number can not be supplied.
l Part indicated with the mark "
l Not including Carbon Film Resister ±5%, 1/4W Type in the P.W.Board
parts list. (Refer to the Schematic Diagram for those parts.)
l Not including Carbon Chip Resister 1/16W Type in the P.W.Board parts
list. (Refer to the Schematic Diagram for those parts.)
WARNING:
Parts marked with this symbol
Use ONLY replacement parts recommended by the manufacturer.
ll
Resistors
l
ll
Ex.: RN14K2E182GFR
Type Shape Power Resist- Allowable Others
and per-anceerror
formance
" is not illustrated in the exploded view.
have critical characteristics.
38DN-S3000
5% 1/4W
1/16W
RN14K2E182GFR
RD : Carbon2B : 1/8W F : ±1%P : Pulse-resistant type
RC : Composition2E : 1/4W G : ±2%NL : Low noise type
RS : Metal oxide film2H : 1/2W J : ±5%NB : Non-burning type
RW : Winding3A : 1WK : ±10% FR : Fuse-resistor
RN : Metal film3D : 2WM : ±20% F : Lead wire forming
RK : Metal mixture3F : 3W
] Resistance
1 8 2⇒1800 ohm = 1.8 kohm
s
s
• Units: ohm
1 R 2⇒1.2 ohm
s
s
• Units: ohm
ll
l Capacitors
ll
Ex.: CE04W1H2R2MBP
Type Shape Dielectric Capacity Allowable Others
3H : 5W
Indicates number of zeros after effective number.
2-digit effective number.
1-digit effective number.
2-digit effective number, decimal point indicated by R.
and per- strengtherror
formance
CE : Aluminum foil0J : 6.3VF : ±1%HS : High stability type
electrolytic
CA : Aluminum solid1A : 10VG : ± 2%BP : Non-polar type
electrolytic
CS : Tantalum electrolytic1C : 16VJ : ±5%HR : Ripple-resistant type
CQ : Film1E : 25VK : ±10%DL : For change and discharge
CK : Ceramic1V : 35VM : ±20%HF : For assuring high
CC : Ceramic1H : 50VZ : +80%U : UL part
CP : Oil2A : 100V–20%C : CSA part
CM : Mica2B : 125VP : +100%W : UL-CSA type
CF : Metallized2C : 160V–0%F : Lead wire forming
CH : Metallized2D : 200VC : ±0.25pF
Parts marked with this symbol ! have critical characteristics.
Use ONLY replacement parts recommended by the manufacturer.
CAUTION:
Before returning the unit to the customer, make sure you make
either (1) a leakage current check or (2) a line to chassis resistance check. If the leakage current exceeds 0.5 milliamps, or if
the resistance from chassis to either side of the power cord is
less than 460 kohms, the unit is defective.
WARNING:
DO NOT return the unit to the customer until the problem is located and corrected.
NOTICE:
ALL RESISTANCE VALUES IN OHM. k=1,000 OHM
M=1,000,000 OHM
ALL CAPACITANCE VALUES IN MICRO FARAD.
P=MICRO-MICRO FARAD
EACH VOLTAGE AND CURRENT ARE MEASURED AT
NO SIGNAL INPUT CONDITION.
CIRCUIT AND PARTS ARE SUBJECT TO CHANGE
WITHOUT PRIOR NOTICE.