Page 1
Micrel, Inc.
FEATURES
■ 3.3V and 5V power supply option
■ 50ps output-to-output skew
■ 50% duty cycle outputs
■ Synchronous enable/disable
■ Master Reset for synchronization
■ Internal 75KΩ input pull-down resistors
■ Available in 20-pin SOIC package
÷2/4, ÷4/5/6 CLOCK
GENERATION CHIP
DESCRIPTION
The SY100S839V is a low skew ÷2/4, ÷4/5/6 clock
generation chip designed explicitly for low skew clock
generation applications. The internal dividers are
synchronous to each other, therefore, the common output
edges are all precisely aligned. The device can be driven
by either a differential or single-ended ECL/LVECL or, if
positive power supplies are used, PECL/LVPECL input
signal. In addition, by using the VBB output, a sinusoidal
source can be AC-coupled into the device. If a singleended input is to be used, the VBB output should be
connected to the /CLK input and bypassed to ground via
a 0.01µF capacitor. The VBB output is designed to act as
the switching reference for the input of the S839V under
single-ended input conditions. As a result, this pin can
only source/sink up to 0.5mA of current.
The common enable (/EN) is synchronous so that the
internal dividers will only be enabled/disabled when the
internal clock is already in the LOW state. This avoids
any chance of generating a runt clock pulse on the
internal clock when the device is enabled/disabled as
can happen with an asynchronous control. An internal
runt pulse could lead to losing synchronization between
the internal divider stages. The internal enable flip-flop is
clocked on the falling edge of the input clock, therefore,
all associated specification limits are referenced to the
negative edge of the clock input.
Upon start-up, the internal flip-flops will attain a
random state; the master reset (MR) input must be
asserted to ensure synchronization. For systems which
only use one S839V, the MR pin need not be exercised
as the internal divider designs ensures synchronization
between the ÷2/4, and the ÷4/5/6 outputs of a single
device.
Precision Edge
Precision Edge
SY100S839V
SY100S839V
Precision Edge
®
®
®
Precision Edge is a registered trademark of Micrel, Inc.
M9999-032206
hbwhelp@micrel.com or (408) 955-1690
1
Rev.: B Amendment: /0
Issue Date: March 2006
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Micrel, Inc.
PACKAGE/ORDERING INFORMATION
Ordering Information
Precision Edge
SY100S839V
®
/EN
DIVSELb0
CLK
/CLK
VBB
MR
VCC
DIVSELb1
DIVSELa
1VCC
2
3
4
5
6
7
8
9
10
20 VCC
Q0
19
/Q0
18
Q1
17
/Q1
16
Q2
15
/Q2
14
Q3
13
/Q3
12
VEE
11
Part Number Type Range Marking Finish
SY100S839VZC Z20-1 Commercial SY100S839VZC Sn-Pb
SY100S839VZCTR
SY100S839VZG
SY100S839VZGTR
Notes:
1. Tape and Reel.
2. Pb-Free package is recommended for new designs.
20-Pin SOIC (Z20-1)
TRUTH TABLE
CLK /EN MR Function
Z L L Divide
ZZ H L Hold Q0–3
X X H Reset Q0–3
Note:
Z = LOW-to-HIGH transition
ZZ = HIGH-to-LOW transition
DIVSELa Q0, Q1 OUTPUTS
0 Divide by 2
1 Divide by 4
(2)
(1)
(1, 2)
Package Operating Package Lead
Z20-1 Commercial SY100S839VZC Sn-Pb
Z20-1 Industrial SY100S839VZG with Pb-Free
Pb-Free bar-line indicator NiPdAu
Z20-1 Industrial SY100S839VZG with Pb-Free
Pb-Free bar-line indicator NiPdAu
PIN NAMES
Pin Function
CLK Differential Clock Inputs
/EN Synchronous Enable
MR Master Reset
VBB Reference Output
Q0, Q1 Differential ÷2/4 Outputs
Q2, Q3 Differential ÷4/5/6 Outputs
DIVSEL Frequency Select Input
DIVSELb1 DIVSELb0 Q2, Q3 OUTPUTS
0 0 Divide by 4
0 1 Divide by 6
1 0 Divide by 5
1 1 Divide by 5
M9999-032206
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Micrel, Inc.
Precision Edge
SY100S839V
®
DC ELECTRICAL CHARACTERISTICS
(1)
VEE = VEE (min) to VEE (max); VCC = GND
TA = –40°CTA = 0°CTA = +25°CTA = +85°C
Symbol Parameter Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit
IEE Power Supply Current — 50 95 — 50 95 — 50 95 — 54 95 mA
BB Output Reference –1.38 — –1.26 –1.38 — –1.26 –1.38 — –1.26 –1.38 — –1.26 V
V
Voltage
IIH Input High Current ——150——150——150——150µA
(4)
(2)
–1085 –1005 –880 –1025 –955 –880 –1025 –955 –880 –1025 –955 –880 mV
(2)
–1830 –1695 –1555 –1810 –1705 –1620 –1810 –1705 –1620 –1810 –1705 –1620 mV
(3)
–1095 — — –1035 — — –1035 — — –1035 — — mV
(3)
— — –1555 — — –1610 — — –1610 — — –1610 mV
0.5 — — 0.5 — — 0.5 — — 0.5 — — µA
VOH Output HIGH Voltage
VOL Output LOW Voltage
VOHA Output HIGH Voltage
VOLA Output LOW Voltage
VIH Input HIGH Voltage –1165 — –880 –1165 — –880 –1165 — –880 –1165 — –880 mV
VIL Input LOW Voltage –1810 — –1475 –1810 — –1475 –1810 — –1475 –1810 — –1475 mV
IL Input LOW Current
I
Note:
1. Parametric values specified at: -3.0V to -3.8V or -4.2V to -5.5V.
2. VIN = VIH(Max) or VIL(Min): Loading with 50Ω to –2.0V.
3. VIN = VIH(Min) or VIL(Max): Loading with 50Ω to –2.0V.
4. VIN = VIL(Min).
M9999-032206
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Micrel, Inc.
Precision Edge
SY100S839V
®
AC ELECTRICAL CHARACTERISTICS
(1)
VEE = VEE (min) to VEE (max); VCC = GND
TA = –40°CTA = 0°CTA = +25°CTA = +85°C
Symbol Parameter Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit
fMAX Maximum Toggle Frequency 1000 — — 1000 — — 1000 — — 1000 — — MHz
PD Propagation Delay to Output ps
t
CLK
➝ Output (Diff.) 725 — 925 725 — 925 725 — 925 725 — 925
CLK
➝ Output (S.E.) 675 — 975 675 — 975 675 — 975 675 — 975
MR ➝ Output 600 — 900 600 — 900 610 — 910 630 — 930
tskew Within-Device Skew
(2)
Q0 — Q3 ——50——50——50——50 ps
Part-to-Part Q0 — Q3 (Diff.) — — 200 — — 200 — — 200 — — 200
t
S Set-up Time /EN ➝ /CLK 250 — — 250 — — 250 — — 250 — — ps
DIVSEL ➝ CLK 400 — — 400 — — 400 — — 400 — —
t
H Hold Time /CLK ➝ /EN 100 — — 100 — — 100 — — 100 — — ps
CLK ➝ DIVSEL 150 — — 150 — — 150 — — 150 — —
VPP Minimum Input Swing
VCMR Common Mode Range
(3)
CLK 250 — — 250 — — 250 — — 250 — — mV
(4), (5)
-1.6 — -0.4 -1.7 — -0.4 -1.7 — -0.4 -1.7 — -0.4 V
tRR Reset Recovery Time — — 100 — — 100 — — 100 — — 100 ps
t
PW Minimum Pulse Width CLK 500 — — 500 — — 500 — — 500 — — ps
MR 700 — — 700 — — 700 — — 700 — —
tr Output Rise/Fall Times Q 280 — 550 280 — 550 280 — 550 280 — 550 ps
tf (20% —80%)
Notes:
1. Parametric values specified at: -3.0V to -3.8V or -4.2V to -5.5V.
2. Skew is measured between outputs under identical transitions.
3. Minimum input swing for which AC parameters are guaranteed. The device will function reliably with differential inputs down to 100mV.
4. The CMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within the specified
range and the peak-to-peak voltage lies between VPP min. and 1V. The lower end of the CMR range varies 1:1 with VEE. The numbers in the spec table
assume a nominal VEE = –3.3V. Note for PECL operation, the VCMR (min) will be fixed at 3.3V – IVCMR (min)I.
5. Duty Cycle: (Min. 48%; Max. 52%) } over temp.
M9999-032206
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Page 5
Micrel, Inc.
LOGIC DIAGRAM
DIVSELa
CLK
CLK
(÷ 2/4)
R
Precision Edge
®
SY100S839V
Q
0
Q
0
Q
1
Q
1
DIVSELb0
DIVSELb1
TIMING DIAGRAMS
CLK
Q (÷ 2)
Q (÷ 4)
V
EN
BB
MR
(÷4/5/6)
R
Q
2
Q
2
Q
3
Q
3
Q (÷ 5)
Q (÷ 6)
M9999-032206
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Page 6
Micrel, Inc.
20-PIN SOIC .300" WIDE (Z20-1)
Precision Edge
SY100S839V
®
Rev. 03
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
The information furnished by Micrel in this datasheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use.
Micrel reserves the right to change circuitry and specifications at any time without notification to the customer.
TEL + 1 (408) 944-0800 FAX + 1 (408) 474-1000 WEB http://www.micrel.com
Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can
reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into
the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser’s
use or sale of Micrel Products for use in life support appliances, devices or systems is at Purchaser’s own risk and Purchaser agrees to fully indemnify
M9999-032206
hbwhelp@micrel.com or (408) 955-1690
Micrel for any damages resulting from such use or sale.
© 2006 Micrel, Incorporated.
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