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COMPAL CONFIDENTIAL
MODEL NAME : Goliad MLK 12 UMA
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PCB NO : LA-A971P BOM P/N : 4319RJ31LXX
GPIO MAP: 3.3b
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Goliad MLK 12" UMA |
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Broadwell U Processor |
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2013-12-23 |
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REV : 0.3 (X01) |
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@ : Nopop Component |
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EMC@ : EMI, ESD and RF Component |
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@EMC@ : EMI, ESD and RF Nopop Component |
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CXDP@ : XDP Component |
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CONN@ : Connector Component |
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VPRO@ : Vpro Component |
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Layout Dell logo |
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NVPRO@ : Non-Vpro Component |
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COPYRIGHT 2013 |
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ALL RIGHT RESERVED |
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REV: X01 |
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PWB: 89XM3 |
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DATE: 1351-05 |
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4 |
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MB PCB |
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Part Number |
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Description |
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DELL CONFIDENTIAL/PROPRIETARY |
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DAA00083000 |
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PCB 14A LA-A971P REV0 MB WITH DOCKING 2 |
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Compal Electronics, Inc. |
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PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL |
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Title |
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TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT |
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Cover Sheet |
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BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, |
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Rev |
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NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD |
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LA-A971P |
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0.1 |
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PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. |
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Date: |
Wednesday, March 19, 2014 |
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Sheet 1 |
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1
2
3
4
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B |
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E |
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Reverse Type |
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Goliad MLK 12 UMA Block Diagram |
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DDR3L-DIMM X2 |
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BANK 0, 1, 2, 3 |
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Trough eDP Cable |
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Memory BUS (DDR3L) |
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PAGE 18 19 |
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1333/1600MHz |
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LCD Touch |
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USB2.0[4] |
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1 |
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PAGE 23 |
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eDP CONN |
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Dual Lane eDP1.3 |
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USB2.0[5] |
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Camera |
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PAGE 23 |
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DOCKED_LIO_EN |
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PAGE 23 |
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INTEL |
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SW_USB2.0[3] |
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mDP CONN |
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DDI2 |
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USB2.0[3] |
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NX3DV221 |
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USB20 Switch |
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USB3.0[4] |
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USB3.0/2.0 |
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PAGE 24 |
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BROADWELL ULT |
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USB |
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DOCKED |
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PAGE 31 |
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DOCK _USB2.0[3] |
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PAGE 31 |
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USB2.0[0]_PS |
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VGA |
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SW_USB2.0[0] |
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TPS2544 |
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DOCKING |
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Parade |
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Parade |
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USB2.0[0] |
PI3USB3102 |
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SW_USB3.0[1] |
USB POWER SHARE |
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USB3.0/2.0+PS |
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DP |
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IDT |
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DP |
PS8338 |
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DP |
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PS8339 |
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DDI1 |
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USB3.0[1] |
USB3&2 Switch |
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PAGE 31 |
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CONN |
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DP |
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VMM3320 |
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PAGE 26 |
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PAGE 25 |
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PAGE 31 |
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DOCK _USB2.0[0] |
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PAGE 34 |
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PAGE 22 |
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WIGIG_DP |
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DOCK_USB3.0[1] |
USB2.0[1] |
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USB3.0[2] |
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USB3.0/2.0 |
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2 |
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DAI |
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HDMI CONN |
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HDMI |
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PAGE 32 |
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LAN |
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PAGE 24 |
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PAGE 6~17 |
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HD Audio I/F |
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SATA1 |
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INT.Speaker |
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DOCK_USB2.0[0] |
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Card reader |
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PCIE1 |
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PAGE 21 |
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SD4.0 |
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DOCK_USB2.0[5] |
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O2 Micro OZ777FJ2LN |
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SATA1 |
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HDA Codec |
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DOCK_USB3.0[3] |
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PAGE 29 |
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PAGE 29 |
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Universal Jack |
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SPI |
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ALC3235 |
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PAGE 21 |
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PCI Express BUS |
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PAGE 21 |
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W25Q64CVSSIQ |
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Dig. MIC |
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Trough eDP Cable |
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LPC |
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PCIE3 |
PCIE6_L0 |
PCIE6_L1 |
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PCIE5_L0 |
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PCIE4 |
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64M 4K sector |
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W25Q32BVSSIQ |
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LID switch |
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Full Mini Card |
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SIM+HALL/B |
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32M 4K sector |
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PAGE 7 |
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mSATAPAGE 20 |
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Intel |
Clarkville |
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SMSC SIO |
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USH CONN |
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3 |
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WWAN/LTE |
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WLAN/BT/ |
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ECE5048 |
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Discrete TPM |
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PAGE 27 |
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I218LM |
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AT97SC3205 |
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WIGIG |
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PAGE 28 |
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PAGE 35 |
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PAGE 27 |
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CPU XDP Port |
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PAGE 30 |
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PAGE 30 |
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PAGE 9 |
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USB2.0[7] |
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USB2.0[2] |
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Transformer |
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KB/TP CONN |
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Automatic Power |
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WIGIG_DP |
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BC BUS |
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SMSC KBC |
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Switch (APS)PAGE 9 |
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PAGE 28 |
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PAGE 37 |
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MEC5085 |
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FAN CONN |
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PAGE 36 |
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RJ45 |
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PAGE 36 |
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PAGE 28 |
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DC/DC Interface |
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PAGE 38 |
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Near Field |
PAGE 20 |
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Power On/Off |
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SW & LED PAGE 39 |
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Smart Card |
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TDA8034HN |
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Communications con |
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4 |
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BCM5882 |
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DELL CONFIDENTIAL/PROPRIETARY |
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RFID |
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Compal Electronics, Inc. |
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Fingerprint |
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FP_USB |
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USB2.0[6] |
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CONN |
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PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL |
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Title |
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Block diagram |
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PAGE 27 USH board |
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TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT |
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BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, |
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Size |
Document Number |
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Rev |
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NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD |
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LA-A971P |
0.1 |
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PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. |
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Date: |
Wednesday, March 19, 2014 |
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Sheet 2 of 48 |
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A |
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B |
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C |
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D |
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E |
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5 |
4 |
3 |
2 |
1 |
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POWER STATES |
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Signal |
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SLP |
SLP |
SLP |
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SLP |
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ALWAYS |
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M |
SUS |
RUN |
CLOCKS |
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PCIE |
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USB3.0 |
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SATA |
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DESTINATION |
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State |
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S3# |
S4# |
S5# |
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A# |
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PLANE |
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PLANE |
PLANE |
PLANE |
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USB3.0 1 |
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JUSB1-->Rear left |
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D |
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S0 (Full ON) / M0 |
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HIGH |
HIGH |
HIGH |
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HIGH |
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ON |
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ON |
ON |
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ON |
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ON |
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USB3.0 2 |
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JUSB3-->Right |
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D |
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S3 (Suspend to RAM) / M3 |
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LOW |
HIGH |
HIGH |
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HIGH |
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ON |
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ON |
ON |
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OFF |
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OFF |
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PCIE 1 |
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USB3.0 3 |
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MMI (CARD READER) |
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S4 (Suspend to DISK) / M3 |
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LOW |
LOW |
HIGH |
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HIGH |
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ON |
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ON |
OFF |
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OFF |
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OFF |
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PCIE 2 |
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USB3.0 4 |
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JUSB2-->Rear Right |
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S5 (SOFT OFF) / M3 |
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LOW |
LOW |
LOW |
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HIGH |
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ON |
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ON |
OFF |
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OFF |
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OFF |
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PCIE 3 |
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LOM |
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S3 (Suspend to RAM) / M-OFF |
LOW |
HIGH |
HIGH |
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LOW |
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ON |
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OFF |
ON |
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OFF |
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OFF |
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PCIE 4 |
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WLAN - JNGFF1 |
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S4 (Suspend to DISK) / M-OFF |
LOW |
LOW |
HIGH |
|
LOW |
|
ON |
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OFF |
OFF |
|
OFF |
|
OFF |
|
PCIE 5 |
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WiGig - JNGFF1 |
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S5 (SOFT OFF) / M-OFF |
|
LOW |
LOW |
LOW |
|
LOW |
|
ON |
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OFF |
OFF |
|
OFF |
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OFF |
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PCIE 6 |
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SATA 3 |
HCA & SATA Cache - JNGFF2 |
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C |
|
PM TABLE |
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SATA 2 |
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SATA Cache - JNGFF2 |
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C |
|||||
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SATA 1 |
|
JMINI3 |
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||
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+5V_ALW |
|
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+3.3V_SUS |
|
+5V_RUN |
|
+3.3V_M |
|
+3.3V_M |
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|||||||||||||
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+3.3V_ALW |
|
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+1.35V_MEM |
|
+3.3V_RUN |
|
+1.05V_M |
|
+1.05V_M |
|
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|
SATA 0 |
|
JDOCK1 |
|
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|||||||||||
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|
|
power |
+3.3V_ALW _PCH |
|
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+0.675V_DDR_VTT |
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|
(M-OFF) |
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||||||||||
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+3.3V_RTC_LDO |
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+1.05V_RUN |
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|||||||
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plane |
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+VCC_CORE |
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USB PORT# |
DESTINATION |
|
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|||||||
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State |
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0 |
|
JUSB1 or DOCK1 |
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||||||
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1 |
|
JUSB3 |
|
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|||
|
|
|
S0 |
|
ON |
|
|
ON |
|
|
ON |
|
ON |
|
|
ON |
|
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|||||
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2 |
|
WLAN + BT |
|
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|||||||||||||||||
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||||||||
B |
|
|
S3 |
|
ON |
|
|
ON |
|
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OFF |
|
ON |
|
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OFF |
|
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|
BDW |
|
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B |
|||||
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3 |
|
JUSB2 or DOCK2 |
|
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||||||||||||||||||||
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|
ULT |
|
|
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|
||||||||
|
|
|
S5 S4/AC |
|
ON |
|
|
OFF |
|
|
OFF |
|
ON |
|
|
OFF |
|
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||||||
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4 |
|
Touch Screen |
|
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|||||||||||||||||
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|
||||||||
|
|
|
S5 S4/AC doesn't exist |
|
OFF |
|
|
OFF |
|
|
OFF |
|
OFF |
|
|
OFF |
|
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|||||
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5 |
|
CAMERA |
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||||||||||||||
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6 |
|
USH |
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7 |
|
WWAN |
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0 |
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BIO |
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USH |
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1 |
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NA |
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|||||
A |
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DELL CONFIDENTIAL/PROPRIETARY |
|
|
A |
|||||||
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||||||||
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|
Compal Electronics, Inc. |
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|
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL |
|
Title |
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||||||||||||||
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TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT |
|
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|
Port assignment |
|
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BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, |
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NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD |
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LA-A971P |
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0.1 |
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PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. |
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Date: |
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W ednesday, March 19, 2014 |
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Sheet 3 of |
40 |
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5 |
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1 |
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5 |
4 |
3 |
2 |
1 |
D
C
B
A
ADAPTER
BATTERY
CHARGER
ISL95813
(PU501)
H_VR_EN
+VCC_CORE
RUN_ON MPHYP_PWR_EN
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TPS22966 |
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SI3456 |
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(UZ7) |
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(QZ6) |
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D |
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EN_INVPWR |
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FDC654P |
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+BL_PWR_SRC |
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(QV1) |
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+1.05V_RUN |
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+1.05V_MODPHY |
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A_ON |
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SY8208 |
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+1.05V_M |
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(PU300) |
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+PWR_SRC |
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ALWON |
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TPS51285 |
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+5V_ALW |
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(PU100) |
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C |
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+3.3V_ALW |
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SUSON |
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HDD3.3V EN |
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3.3VWWAN EN |
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AUXEN WOWL |
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SLPSIO LAN# |
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ONA |
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LCDPWREN |
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RUNON |
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RUNON |
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USB_PWR_SHR_EN# |
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USB_PWR_EN1# |
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USB_PWR_EN2# |
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RT8207 |
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(PU200) |
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TPS22966 |
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TPS22966 |
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TPS22966 |
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APL3512 |
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TPS22966 |
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TPS2544 |
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G547I2P81U |
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G547I2P81U |
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(UZ8) |
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B |
SUS_ON |
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VTT_ON |
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+1.35V_MEM |
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DDR_ |
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0.675V_ |
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+3.3V_SUS |
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+0.675V_DDR_VTT |
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+3.3V_HDD |
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+3.3V_M |
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3.3V_ |
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+3.3V_CAM |
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LP2301ALT1G |
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(QZ1) |
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A |
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DELL CONFIDENTIAL/PROPRIETARY |
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Compal Electronics, Inc. |
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PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL |
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Title |
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TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT |
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Power rails |
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BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, |
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Size |
Document Number |
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NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD |
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LA-A971P |
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0.1 |
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PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. |
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Date: |
Wednesday, March 19, 2014 |
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Sheet 4 |
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of 40 |
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5 |
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4 |
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3 |
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5 |
4 |
3 |
2 |
1 |
2.2K 2.2K
SMBUS Address [0x9a]
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+3.3V_ALW_PCH |
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+3.3V_RUN |
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2.2K |
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2.2K |
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AP2 |
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MEM_SMBCLK |
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4 202 |
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2N7002 |
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AH1 |
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MEM_SMBDATA |
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200 |
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DIMMA |
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D |
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BDW |
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1K |
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2N7002 |
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202 |
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D |
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AN1 |
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SML0CLK |
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1K |
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+3.3V_ALW_PCH |
28 |
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200 |
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DIMMB |
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AK1 |
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SML0DATA |
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31 |
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LOM |
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AH3 |
AU3 |
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53 |
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XDP |
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2.2K |
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51 |
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SML1_SMBDATA |
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+3.3V_ALW_PCH |
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SML1_SMBCLK |
2.2K |
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A5 |
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B6 |
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2.2K |
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3A |
3A |
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+3.3V_ALW |
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B4 |
DOCK_SMB_CLK |
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2.2K |
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|||||||
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1A |
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1A |
|
A3 |
DOCK_SMB_DAT |
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2.2K |
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|||||
C |
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2.2K |
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+3.3V_ALW |
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C |
||||||||||
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|||||
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B5 |
LCD_SMBCLK |
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|||||||||
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||||||||||||
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1B |
|
A4 |
LCD_SMDATA |
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|||||
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||||||||||||
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1B |
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2.2K |
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||||
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KBC |
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+3.3V_ALW |
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|||||||||
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2.2K |
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7 |
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||||||||||||||||
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||||||||||||||||||||||
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1C |
|
A56 |
PBAT_SMBCLK |
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100 ohm |
|
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BATTERY |
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|||||||||||
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||||
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100 ohm |
6 |
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||||||||||
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1C |
|
B59 |
PBAT_SMBDAT |
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||||||||||||||||||
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CONN |
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|||||||||||||||
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2.2K |
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2.2K |
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+3.3V_SUS |
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MEC 5085 |
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1E |
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A50 |
USH_SMBCLK |
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M9 |
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B53 |
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L9 |
USH |
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1E |
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USH_SMBDAT |
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B |
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B |
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2.2K |
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2.2K |
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+3.3V_ALW |
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2B |
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A49 |
CARD_SMBCLK |
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2B |
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B52 |
CARD_SMBDAT |
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10K |
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10K |
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+3.3V_ALW |
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1G |
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B50 |
CHARGER_SMBCLK |
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9 |
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1G |
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A47 |
CHARGER_SMBDAT |
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8 |
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Charger |
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2.2K |
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2.2K |
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+3.3V_ALW |
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2D |
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B7 |
BAY_SMBDAT |
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A |
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BAY_SMBCLK |
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A |
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2D |
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A7 |
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2.2K |
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DELL CONFIDENTIAL/PROPRIETARY |
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2.2K |
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+3.3V_ALW |
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Compal Electronics, Inc. |
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2A |
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B48 |
GPU_SMBDAT |
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PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL |
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Title |
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B49 |
GPU_SMBCLK |
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TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT |
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SMbus Block diagram |
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2A |
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BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, |
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Size |
Document Number |
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Rev |
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NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD |
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LA-A971P |
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0.1 |
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PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. |
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Date: |
Wednesday, March 19, 2014 |
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Sheet 5 |
of |
40 |
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5 |
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4 |
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3 |
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2 |
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1 |
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5 |
4 |
3 |
2 |
1 |
D
C
B
A
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UMA SATA port |
SATA0 |
SATA1 |
PCB |
SATA2/PCIE6 L1 |
SATA3/PCIE6 L0 |
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E-Dock |
mSATA |
G12 UMA |
M2 3042 |
M2 3042 |
contact to WWAN |
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2nd PCIe Lane for PCIe Cache |
(HCA & SATA-Cache) |
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Service Mode Switch: |
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NA |
mSATA |
G12 Entry |
NA |
NA |
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Add a switch to ME_FWP signal to unlock the ME region and |
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allow the entire region of the SPI flash to be updated using FPT. |
E-Dock |
mSATA |
G14 DSC |
M2 3042 |
M2 3030 WIGIG |
SATA2/PCIE6_L1 contact to WWAN |
D |
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+3.3V_ALW_PCH |
ME_FWP_EC 2 |
1 |
ME_FWP |
SATA3/PCIE6 L0 contact to WLAN |
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SATA-Cache(no HCA) |
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@ RC301 |
0_0402_5% |
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E-Dock |
HDD |
G14 UMA |
M2 3042 |
M2 3042 |
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1 |
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PT, ST pop RC2 & SW1; MP pop RC301. |
contact to WWAN |
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2nd PCIe Lane for PCIe Cache |
(HCA & SATA-Cache) |
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RC2 |
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1K_0402_5% |
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2 |
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<36> |
ME_FWP_EC |
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1 |
SW1 |
NA |
mSATA |
G14D_En |
NA |
M2 3030 WIGIG |
contact to WLAN |
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A |
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2 |
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NA |
HDD |
G14U_En |
NA |
NA |
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+RTC_CELL |
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B |
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ME_FWP |
3 |
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4 |
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C |
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2 1 |
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5 |
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G1 |
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RC1 5% 0402 330K |
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G2 |
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SS3-CMFTQR9_3P |
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ME_FWP PCH has internal 20K PD. |
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FLASH DESCRIPTOR SECURITY OVERRIDE |
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PCH_INTVRMEN |
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LOW = ENABLE (DEFAULT) |
-->Pin1 & Pin3 short |
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HIGH = DISABLE (ME can update) -->Pin2 & Pin3 short |
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CC1 |
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INTVRMEN - INTEGRATED SUS 1.05V VRM |
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1 |
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2 |
PCH_RTCX1_R |
1 |
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2 |
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PCH_RTCX1 |
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ENABLE |
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@ RC4 |
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0_0402_5% |
10M |
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12P_0402_50V8J |
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1 |
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C |
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High - Enable Internal VRs |
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1 |
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0402_ |
RC7 |
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Low - Enable External VRs |
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2 |
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YC1 |
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2 |
5%_ |
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UC1E |
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BDW_ULT_DDR3L |
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32.768KHZ_12.5PF_9H03220008 |
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CC2 |
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1 |
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2 |
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PCH_RTCX2 |
AW5 |
RTCX1 |
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AY5 |
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RTCX2 |
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1 |
2 |
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12P_0402_50V8J |
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INTRUDER# |
AU6 |
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J5 |
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INTRUDER |
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SATA_RN0/PERN6_L3 |
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SATA_PRX_DKTX_N0_C |
<34> |
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RC9 |
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1M_0402_5% |
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PCH_INTVRMEN |
AV7 |
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H5 |
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for DOCK |
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INTVRMEN |
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SATA_RP0/PERP6_L3 |
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SATA_PRX_DKTX_P0_C |
<34> |
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+RTC_CELL |
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1 |
2 |
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SRTCRST# |
AV6 |
RTC |
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B15 |
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RC10 |
1 |
2 |
20K_0402_5% |
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PCH_RTCRST# |
AU7 |
SRTCRST |
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SATA_TN0/PETN6_L3 |
A15 |
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SATA_PTX_DKRX_N0_C |
<34> |
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RC8 |
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20K_0402_5% |
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RTCRST |
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SATA_TP0/PETP6_L3 |
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SATA_PTX_DKRX_P0_C |
<34> |
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<9> |
PCH_RTCRST# |
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SATA_RN1/PERN6_L2 |
J8 |
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SATA_PRX_DTX_N1 |
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<20> |
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H8 |
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1 |
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2 |
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SATA_RP1/PERP6_L2 |
A17 |
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SATA_PRX_DTX_P1 |
|
<20> |
SATA HDD |
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1 |
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2 |
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SATA_TN1/PETN6_L2 |
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SATA_PTX_DRX_N1 |
|
<20> |
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||||||||
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B17 |
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SATA_TP1/PETP6_L2 |
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SATA_PTX_DRX_P1 |
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<20> |
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PCH_AZ_BITCLK |
AW8 |
HDA_BCLK/I2S0_SCLK |
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SATA_RN2/PERN6_L1 |
J6 |
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PCIE_PRX_SATATX_N6_L1 |
<30> |
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@ |
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PCH_AZ_SYNC |
AV11 |
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H6 |
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HDA_SYNC/I2S0_SFRM |
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SATA_RP2/PERP6_L1 |
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PCIE_PRX_SATATX_P6_L1 |
<30> |
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|||||||||
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CMOS1 |
SHORT PADS~D |
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PCH_AZ_RST# |
AU8 |
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B14 |
|
for PCIe Cache (WWAN) |
|||||||||||||
1 |
2 |
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1 |
2 |
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<21> PCH_AZ_CODEC_SDIN0 |
|
PCH_AZ_CODEC_SDIN0 |
AY10 |
HDA_RST/I2S_MCLK |
AUDIO |
SATA |
SATA_TN2/PETN6_L1 |
C15 |
|
PCIE_PTX_SATARX_N6_L1 |
<30> |
||||||||||||
CC3 |
1U_0402_6.3V6K |
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CC4 |
1U_0402_6.3V6K |
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AU12 |
HDA_SDI0/I2S0_RXD |
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SATA_TP2/PETP6_L1 |
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PCIE_PTX_SATARX_P6_L1 |
<30> |
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HDA_SDI1/I2S1_RXD |
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|||||||||
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CMOS place near DIMM |
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ME_FWP |
1 |
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2 |
PCH_AZ_SDOUT |
AU11 |
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F5 |
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||||||
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RC11 |
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1K_0402_5% |
AW10 |
HDA_SDO/I2S0_TXD |
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SATA_RN3/PERN6_L0 |
E5 |
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PCIE_PRX_SATATX_N6_L0 |
<30> |
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AV10 |
HDA_DOCK_EN/I2S1_TXD |
|
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SATA_RP3/PERP6_L0 |
C17 |
|
PCIE_PRX_SATATX_P6_L0 |
<30> |
for SATA-CACHE (WWAN) |
||||||
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HDA_DOCK_RST/I2S1_SFRM |
|
SATA_TN3/PETN6_L0 |
|
PCIE_PTX_SATARX_N6_L0 |
<30> |
||||||||||
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AY8 |
|
D17 |
|
||||||||||||
ME_CLR1 |
TPM setting |
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CMOS_CLR1 |
CMOS setting |
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I2S1_SCLK |
|
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SATA_TP3/PETP6_L0 |
|
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PCIE_PTX_SATARX_P6_L0 |
<30> |
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|||||||||
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|||||||||
Shunt |
Clear ME RTC Registers |
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|
Shunt |
|
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Clear CMOS |
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|
SATA0GP/GPIO34 |
V1 |
MPCIE_RST# |
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|||
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U1 |
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B |
||||||||
Open |
Keep ME RTC Registers |
|
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|
Open |
|
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Keep CMOS |
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|
SATA1GP/GPIO35 |
V6 |
SATA2_PCIE6_L1 |
HDD_DET# |
<20> |
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||||
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|
SATA2GP/GPIO36 |
SATA2_PCIE6_L1 |
<12,35> |
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|||||||||||||
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AC1 |
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||||||||||||||
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|
SATA3GP/GPIO37 |
|
mCARD_PCIE#_SATA |
<36,7> |
|
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|||||
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|
<9> |
PCH_JTAG_TRST# |
|
PCH_JTAG_TRST# |
AU62 |
|
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|
|||||||||
+1.05V_M |
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PCH_TRST |
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||||||
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|
PCH_JTAG_TCK |
AE62 |
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|
A12 |
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|
||||||
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|
|
<9> |
PCH_JTAG_TCK |
|
PCH_TCK |
|
|
SATA_IREF |
|
|
|
+PCH_ASATA3PLL |
|
|
||||||||||
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RPC21 |
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PCH_JTAG_TDI |
AD61 |
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L11 |
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<9> |
PCH_JTAG_TDI |
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PCH_TDI |
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RSVD |
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PCH_JTAG_TDO |
AE61 |
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K10 |
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<9> |
PCH_JTAG_TDO |
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PCH_TDO |
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RSVD |
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8 |
1 |
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@ RC300 |
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PCH_JTAG_TMS |
AD62 |
JTAG |
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C12 |
SATA_COMP |
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<9> |
PCH_JTAG_TMS |
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PCH_TMS |
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SATA_RCOMP |
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+3.3V_RUN |
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7 |
2 |
PCH_JTAG_TDO |
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AL11 |
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U3 |
SATA_ACT# |
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RSVD |
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SATALED |
SATA_ACT# |
<39> |
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6 |
3 |
PCH_JTAG_TMS |
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+1.05V_M |
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1 |
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2 |
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PM_TEST_RST |
AC4 |
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RPC18 |
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5 |
4 |
PCH_JTAG_TDI |
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<9> |
PCH_JTAG_JTAGX |
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AE63 |
RSVD |
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MPCIE_RST# |
5 |
4 |
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JTAGX |
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10K_0402_5% |
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AV2 |
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HDD_DET# |
6 |
3 |
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RSVD |
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51_0804_8P4R_5% |
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7 |
2 |
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2 |
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<29,7> |
MMICLK_REQ# |
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8 |
1 |
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<10> |
DGPU_PWROK |
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2 |
1 |
PCH_JTAG_JTAGX |
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@ CC100 |
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@ RC18 |
1K_0402_1% |
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1 |
1U_0402_6.3V6K |
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10K_8P4R_5% |
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2 |
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1 |
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PCH_JTAG_TCK |
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BDW-ULT-DDR3L_BGA1168 |
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SATA Impedance Compensation |
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@ RC21 |
51_0402_5% |
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5 OF 19 |
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+PCH_ASATA3PLL |
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SATA_COMP |
1 |
2 |
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HDA for Codec |
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3.01K_0402_1% |
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RC17 |
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CAD note: |
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<21> PCH_AZ_CODEC_SDOUT |
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1 |
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2 |
PCH_AZ_SDOUT |
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Place the resistor within 500 mils of the PCH. Avoid |
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RC19 |
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33_0402_5% |
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routing next to clock pins. |
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<21> PCH_AZ_CODEC_SYNC |
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1 |
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2 |
PCH_AZ_SYNC |
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RC20 |
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33_0402_5% |
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<21> PCH_AZ_CODEC_RST# |
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1 |
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2 |
PCH_AZ_RST# |
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A |
|||||||||
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RC22 |
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33_0402_5% |
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<21> PCH_AZ_CODEC_BITCLK |
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1 EMC@ |
2 |
PCH_AZ_BITCLK |
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12 |
RC23 |
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33_0402_5% |
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CC5 @EMC@ 50V8J040227P |
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DELL CONFIDENTIAL/PROPRIETARY |
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Compal Electronics, Inc. |
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PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL |
|
Title |
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TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT |
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CPU (1/12) |
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||||||||
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Reserve for EMI |
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BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, |
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Size |
Document Number |
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Rev |
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NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD |
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0.1 |
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LA-A971P |
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PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. |
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Date: |
Wednesday, March 19, 2014 |
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Sheet 6 |
of |
48 |
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5 |
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4 |
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3 |
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2 |
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1 |
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D
C
B
A
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5 |
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4 |
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3 |
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2 |
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1 |
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+3.3V_RUN |
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+3.3V_ALW_PCH |
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UC1G |
BDW_ULT_DDR3L |
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<20,35,36> |
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LPC_LAD0 |
LPC_LAD0 |
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AU14 |
LAD0 |
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SMBALERT/GPIO11 |
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AN2 |
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PCH_SMB_ALERT# <11> |
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2 |
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LPC_LAD1 |
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AW12 |
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AP2 |
MEM_SMBCLK |
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RPC14 |
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<20,35,36> |
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LPC_LAD1 |
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LAD1 |
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SMBCLK |
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LPC_LAD2 |
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AY12 |
LPC |
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AH1 |
MEM_SMBDATA |
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SML1_SMBDATA |
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1 |
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8 |
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<20,35,36> |
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LPC_LAD2 |
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LAD2 |
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SMBDATA |
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LPC_LAD3 |
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AW11 |
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SMBUS |
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AL2 |
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MEM_SMBCLK |
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6 |
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1 |
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SML1_SMBCLK |
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2 |
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7 |
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<20,35,36> |
|
LPC_LAD3 |
LPC_LFRAME# |
AV12 |
LAD3 |
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SML0ALERT/GPIO60 |
|
AN1 |
SML0_SMBCLK |
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DDR_XDP_WAN_SMBCLK |
<18,19,9> |
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MEM_SMBCLK |
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3 |
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6 |
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<20,35,36> |
LPC_LFRAME# |
LFRAME |
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SML0CLK |
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AK1 |
SML0_SMBDATA |
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5 |
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QC1A |
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MEM_SMBDATA |
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4 |
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5 |
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SML0DATA |
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AU4 |
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DMN66D0LDW-7_SOT363-6 |
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SML1ALERT/PCHHOT/GPIO73 |
|
AU3 |
SML1_SMBCLK |
|
PCH_GPIO73 |
<12> |
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2.2K_0804_8P4R_5% |
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SML1CLK/GPIO75 |
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AH3 |
SML1_SMBDATA |
SML1_SMBCLK |
<36> |
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MEM_SMBDATA |
3 |
4 |
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PCH_SPI_CLK |
AA3 |
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SML1DATA/GPIO74 |
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SML1_SMBDATA |
<36> |
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DDR_XDP_WAN_SMBDAT |
<18,19,9> |
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SML0_SMBCLK |
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2 |
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1 |
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<27> |
PCH_SPI_CLK |
SPI_CLK |
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PCH_SPI_CS0# |
Y7 |
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AF2 |
PCH_CL_CLK1 |
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QC1B |
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499_0402_1% |
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RC33 |
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SPI_CS0 |
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CL_CLK |
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PCH_CL_CLK1 <30> |
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PCH_SPI_CS1# |
Y4 |
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AD2 |
PCH_CL_DATA1 |
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DMN66D0LDW-7_SOT363-6 |
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SML0_SMBDATA |
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2 |
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1 |
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SPI_CS1 |
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CL_DATA |
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PCH_CL_DATA1 <30> |
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PCH_SPI_CS2# |
AC2 |
SPI |
C-LINK |
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AF4 |
PCH_CL_RST1# |
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499_0402_1% |
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RC34 |
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<27> |
PCH_SPI_CS2# |
SPI_CS2 |
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CL_RST |
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PCH_CL_RST1# |
<30> |
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PCH_SPI_DO |
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AA2 |
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+3.3V_RUN |
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<27> |
PCH_SPI_DO |
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SPI_MOSI |
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PCH_SPI_DIN |
AA4 |
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<27> |
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PCH_SPI_DIN |
PCH_SPI_DO2 |
Y6 |
SPI_MISO |
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SML0_SMBCLK |
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2 |
1 |
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PCH_SPI_DO3 |
AF1 |
SPI_IO2 |
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@ RC30 |
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0_0402_5% |
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LAN_SMBCLK |
<28> |
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DDR_XDP_WAN_SMBDAT |
2 |
1 |
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SPI_IO3 |
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SML0_SMBDATA |
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2 |
1 |
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LAN_SMBDATA |
<28> |
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2.2K_0402_5% |
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RN3 |
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@ RC32 |
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0_0402_5% |
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+3.3V_SPI |
DDR_XDP_WAN_SMBCLK |
2 |
1 |
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2.2K_0402_5% |
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RN4 |
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CC6 |
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1 |
2 |
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BDW-ULT-DDR3L_BGA1168 |
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64Mb Flash ROM |
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7 OF 19 |
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0.1U_0402_25V6 |
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UC2 |
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SOFTWARE TAA |
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SPI_PCH_CS0# |
1 |
2 |
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SPI_PCH_CS0#_R 1 |
/CS |
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VCC |
8 |
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|||||||||
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@ RC35 |
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0_0402_5% |
SPI_DIN64 |
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2 |
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7 |
SPI_PCH_DO3_64 |
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SPI_PCH_DO2_64 |
3 |
DO(IO1) |
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/HOLD(IO3) |
6 |
SPI_CLK64 |
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/WP(IO2) |
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CLK |
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RPC11 |
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4 |
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5 |
SPI_DO64 |
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GND |
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DI(IO0) |
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|||||||
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SPI_PCH_DIN 1 |
8 |
SPI_DIN64 |
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|||||||
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SPI_CLK32 |
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SPI_CLK64 |
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+3.3V_SPI |
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SPI_PCH_DO 2 |
7 |
SPI_DO64 |
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W25Q64FVSSIQ_SO8 |
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||||||||||||
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SPI_PCH_CLK 3 |
6 |
SPI_CLK64 |
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|||
2 |
33 |
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2 |
33 |
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1 |
2 SPI_PCH_DO2 |
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SPI_PCH_DO3 4 |
5 |
SPI_PCH_DO3_64 |
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+3.3V_SPI |
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||||
@EMC@ |
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@EMC@ |
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RC29 |
|
1K_0402_5% |
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RC38 |
33_0402_5% |
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32Mb Flash ROM |
|
0.1U_0402_25V6 |
|
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||||||||||||||
1 |
RC61 5%0402_ |
|
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1 |
RC62 5%0402_ |
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1 |
2 SPI_PCH_DO3 |
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33_0804_8P4R_5% |
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CC7 VPRO@ |
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RC31 |
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1K_0402_5% |
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1 |
2 |
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SPI_PCH_DO2 1 |
2 |
SPI_PCH_DO2_64 |
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|||
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50V8J040233P |
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50V8J040233P |
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UC3 VPRO@ |
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||
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SPI_PCH_CS1# |
RC50 1 |
2 |
0_0402_5% |
SPI_PCH_CS1#_R |
1 |
/CS |
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VCC |
8 |
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|||||||
12 |
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12 |
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VPRO@ |
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SPI_DIN32 |
|
2 |
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|
7 |
SPI_PCH_DO3_32 |
|
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|||||||
@EMC@ CC9 |
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CC10 |
@EMC@ |
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DO/IO1 |
|
/HOLD/IO3 |
|
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|||||||||||||||
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SPI_PCH_DO |
|
3 |
6 |
SPI_DO32 |
|
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SPI_PCH_DO2_32 |
3 |
|
6 |
SPI_CLK32 |
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||||||||||||||||
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/WP/IO2 |
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CLK |
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||||||||
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RPC12 VPRO@ |
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4 |
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5 |
SPI_DO32 |
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||||||
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GND |
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DI/IO0 |
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||||||||
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SPI_PCH_DO3 1 |
8 SPI_PCH_DO3_32 |
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|||||||
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||||||
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|
SPI_PCH_CLK |
2 |
7 |
SPI_CLK32 |
|
|
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W25Q32FVSSIQ_SO8 |
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SPI_PCH_DIN |
4 |
5 |
SPI_DIN32 |
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33_0804_8P4R_5% |
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CC8 |
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SPI_PCH_DO2 1 |
2 SPI_PCH_DO2_32 |
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2 |
1 |
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RC55 |
33_0402_5% |
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VPRO@ |
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2 |
04021M |
RC63 |
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15P_0402_50V8J |
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PCIECLK for UMA |
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UC1F |
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BDW_ULT_DDR3L |
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3 4 |
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YC2 |
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_ |
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24MHZ_12PF_X3G024000DC1H |
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1 |
5% |
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1 2 |
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<29> |
CLK_PCIE_MMI# |
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C43 |
CLKOUT_PCIE_N0 |
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XTAL24_IN |
A25 |
XTAL24_IN |
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CC11 |
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MMI ---> |
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C42 |
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B25 |
XTAL24_OUT |
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1 |
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2 |
XTAL24_OUT_R |
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2 |
1 |
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<29> |
CLK_PCIE_MMI |
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MMICLK_REQ# |
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U2 |
CLKOUT_PCIE_P0 |
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XTAL24_OUT |
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@ RC65 |
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0_0402_5% |
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<29,6> |
MMICLK_REQ# |
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PCIECLKRQ0/GPIO18 |
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K21 |
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15P_0402_50V8J |
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B41 |
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RSVD |
M21 |
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A41 |
CLKOUT_PCIE_N1 |
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RSVD |
C26 |
CLK_BIASREF |
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CLKOUT_PCIE_P1 |
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DIFFCLK_BIASREF |
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+3.3V_RUN |
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RC66 1 |
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2 |
10K_0402_5% |
PCH_GPIO19 Y5 |
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PCIECLKRQ1/GPIO19 |
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+3.3V_RUN |
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C35 |
MCP_TESTLOW1 |
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+PCH_VCCACLKPLL |
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CLOCK |
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TESTLOW_C35 |
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C41 |
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C34 |
MCP_TESTLOW2 |
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<28> |
CLK_PCIE_LAN# |
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CLKOUT_PCIE_N2 |
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TESTLOW_C34 |
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10/100/1G LAN ---> |
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B42 |
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AK8 |
MCP_TESTLOW3 |
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CLK_BIASREF |
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1 |
2 |
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<28> |
CLK_PCIE_LAN |
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CLKOUT_PCIE_P2 |
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TESTLOW_AK8 |
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LANCLK_REQ# |
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AD1 |
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SIGNALS |
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AL8 |
MCP_TESTLOW4 |
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3.01K_0402_1% |
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RC69 |
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<28> |
LANCLK_REQ# |
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PCIECLKRQ2/GPIO20 |
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TESTLOW_AL8 |
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RPC6 |
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<30> |
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CLK_PCIE_WLAN# |
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B38 |
CLKOUT_PCIE_N3 |
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CLKOUT_LPC_0 |
AN15 |
PCI_CLK_LPC_0 |
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4 |
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5 |
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WLAN (NGFF1)---> |
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C37 |
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AP15 |
PCI_CLK_LPC_1 |
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MCP_TESTLOW1 RC240 |
1 |
2 |
10K_0402_5% |
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CONTACTLESS_DET# |
<10,27> |
<30> |
CLK_PCIE_WLAN |
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CLKOUT_PCIE_P3 |
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CLKOUT_LPC_1 |
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3 |
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6 LANCLK_REQ# |
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WLANCLK_REQ# |
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N1 |
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MCP_TESTLOW2 RC241 |
1 |
2 |
10K_0402_5% |
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<12,30> |
WLANCLK_REQ# |
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PCIECLKRQ3/GPIO21 |
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2 |
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7 |
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mCARD_PCIE#_SATA |
<36,6> |
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B35 |
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MCP_TESTLOW3 RC242 |
1 |
2 |
10K_0402_5% |
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CLKOUT_ITPXDP |
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1 |
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8 |
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A39 |
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A35 |
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MCP_TESTLOW4 RC243 |
1 |
2 |
10K_0402_5% |
|||||||||||
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PCH_GPIO16 |
<12> |
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<30> CLK_PCIE_WIGIG# |
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CLKOUT_PCIE_N4 |
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CLKOUT_ITPXDP_P |
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||||||||||||||||||
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WGIG (NGFF1)---> |
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B39 |
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10K_8P4R_5% |
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<30> |
CLK_PCIE_WIGIG |
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WIGIGCLK_REQ# |
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U5 |
CLKOUT_PCIE_P4 |
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<12,30> |
WIGIGCLK_REQ# |
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PCIECLKRQ4/GPIO22 |
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<30> |
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CLK_PCIE_SATA# |
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B37 |
CLKOUT_PCIE_N5 |
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HCA/PCIe cache (NGFF2)---> |
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A37 |
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<30> |
CLK_PCIE_SATA |
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CLKOUT_PCIE_P5 |
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T2 |
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<30> |
SATACLK_REQ# |
|
RC68 |
|
1 |
2 10K_0402_5% |
|
PCIECLKRQ5/GPIO23 |
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+3.3V_RUN |
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BDW-ULT-DDR3L_BGA1168 |
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support SPI TPM support LPC TPM |
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6 OF 19 |
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PCB |
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PCIE1 |
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PCIE2 |
PCIE3 |
PCIE4 |
PCIE5 |
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PCIE6 |
|
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PCI_CLK_LPC_0 EMC@ |
RC72 1 |
2 |
22_0402_5% |
CLK_PCI_SIO <35> |
|
from CPU |
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to SPI ROM |
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LPC_0 |
LPC_1 |
LPC_0 |
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LPC_1 |
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|||||||||||||||||||
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EMC@ |
RC74 1 |
2 |
22_0402_5% |
CLK_PCI_MEC |
<36> |
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JSPI1 |
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PCH_SPI_CS1# |
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2 |
1 |
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SPI_PCH_CS1# |
1 |
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1 |
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G12 UMA SD card |
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NA |
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LOM |
WLAN |
WIGIG |
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M2 3042 |
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RC224 |
0_0402_5% |
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2 |
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SIO |
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DOCK |
CLKBUFF |
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DOCK |
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PCI_CLK_LPC_1 EMC@ |
RC67 1 |
2 |
22_0402_5% |
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<20,36>PCH_SPI_DO |
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2 |
1 |
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SPI_PCH_DO |
3 |
2 |
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2 |
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(HCA & SATA-Cache) |
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CLK_PCI_LPDEBUG |
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3 |
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MEC |
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DEBUG |
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DEBUG |
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RC225 |
0_0402_5% |
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4 |
4 |
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4 |
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EMC@ |
RC70 1 |
2 |
22_0402_5% |
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PCH_SPI_DIN |
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2 |
1 |
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SPI_PCH_DIN |
5 |
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SIO |
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CLK_PCI_DOCK |
<34> |
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5 |
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G12 Entry SD card |
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NA |
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LOM |
WLAN |
WIGIG |
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NA |
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RC226 |
0_0402_5% |
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6 |
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PCH_SPI_CLK |
SPI_PCH_CLK |
6 |
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6 |
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MP Depop RC70. |
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MEC |
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RC227 |
0_0402_5% |
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8 |
7 |
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8 |
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8 |
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PCH_SPI_CS0# |
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2 |
1 |
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SPI_PCH_CS0# |
9 |
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TPM |
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9 |
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|||||||||
G14 DSC |
SD card |
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NA |
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LOM |
WLAN |
GPU |
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WIGIG |
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CLK_PCI_SIO |
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2 |
1 |
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RC228 |
0_0402_5% |
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10 |
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@EMC@ |
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PCH_SPI_DO2 |
SPI_PCH_DO2 |
10 |
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10 |
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33P_0402_50V8J |
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2 |
1 |
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11 |
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CC12 |
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RC229 |
0_0402_5% |
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12 |
11 |
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PCH_SPI_DO3 |
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2 |
1 |
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SPI_PCH_DO3 |
13 |
12 |
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12 |
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|||
G14 UMA SD card |
|
NA |
|
LOM |
WLAN |
WIGIG |
|
M2 3042 |
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CLK_PCI_MEC |
2 |
1 |
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RC230 |
0_0402_5% |
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14 |
13 |
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14 |
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14 |
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33P_0402_50V8J |
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@EMC@ |
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+3.3V_SPI |
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15 |
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||||||||||||||||||||
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(HCA & SATA-Cache) |
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CC13 |
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+3.3V_M |
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16 |
15 |
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17 |
16 |
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16 |
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|||
G14D_En SD card |
|
NA |
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LOM |
WLAN |
GPU |
|
WIGIG |
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|
|
CLK_PCI_LPDEBUG |
2 |
1 |
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2 |
1 |
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18 |
17 |
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33P_0402_50V8J |
|
@EMC@ |
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RC231 |
0_0402_5% |
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19 |
18 |
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18 |
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CC14 |
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20 |
19 |
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20 |
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20 |
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G14U_En SD card |
|
NA |
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LOM |
WLAN |
WIGIG |
|
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NA |
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CLK_PCI_DOCK |
2 |
1 |
@EMC@ |
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G1 |
21 |
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|||||||||||
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33P_0402_50V8J |
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22 |
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CC15 |
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G2 |
23 |
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G3 |
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24 |
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G4 |
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E-T_6700K-Y20N-00L |
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||||
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CONN@ |
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||
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Reserve for EMI |
|
DELL CONFIDENTIAL/PROPRIETARY |
|
|
|||||||
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|
Compal Electronics, Inc. |
|
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|
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL |
|
|
Title |
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|
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||
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|
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT |
|
|
|
CPU (2/12) |
|
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||
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|
|
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, |
|
|
Size |
Document Number |
|
|
|
Rev |
||
|
|
|
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD |
|
|
|
LA-A971P |
|
|
0.1 |
|||
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|
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. |
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Date: |
Wednesday, March 19, 2014 |
Sheet 7 |
of |
48 |
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5 |
4 |
3 |
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2 |
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1 |
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D
C
B
A
5 |
4 |
3 |
2 |
1 |
D |
|
|
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|
|
UC1C |
BDW_ULT_DDR3L |
|
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<19> |
DDR_B_D[0..63] |
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UC1D |
BDW_ULT_DDR3L |
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D |
|
|
<18> DDR_A_D[0..63] |
|
|
DDR_A_D0 |
AH63 |
SA_DQ0 |
|
SA_CLK#0 |
AU37 |
M_CLK_DDR#0 |
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|
M_CLK_DDR#0 <18> |
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|||||||
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DDR_A_D1 |
AH62 |
|
AV37 |
M_CLK_DDR0 |
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DDR_B_D0 |
AY31 |
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AM38 |
M_CLK_DDR#2 |
|
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||||||||||||
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SA_DQ1 |
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SA_CLK0 |
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M_CLK_DDR0 <18> |
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SB_DQ0 |
|
SB_CK#0 |
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M_CLK_DDR#2 <19> |
|||||||||
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DDR_A_D2 |
AK63 |
|
AW36 |
M_CLK_DDR#1 |
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DDR_B_D1 |
AW31 |
|
AN38 |
M_CLK_DDR2 |
||||||||||||||||||||
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SA_DQ2 |
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SA_CLK#1 |
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M_CLK_DDR#1 <18> |
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SB_DQ1 |
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SB_CK0 |
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M_CLK_DDR2 <19> |
|
|
|||||||
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DDR_A_D3 |
AK62 |
|
AY36 |
M_CLK_DDR1 |
|
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DDR_B_D2 |
AY29 |
|
AK38 |
M_CLK_DDR#3 |
|
|
|||||||||||||||||||
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SA_DQ3 |
|
SA_CLK1 |
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M_CLK_DDR1 |
<18> |
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SB_DQ2 |
|
SB_CK#1 |
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|
M_CLK_DDR#3 <19> |
||||||||
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DDR_A_D4 |
AH61 |
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DDR_B_D3 |
AW29 |
|
AL38 |
M_CLK_DDR3 |
||||||||||||||||||
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SA_DQ4 |
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SB_DQ3 |
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SB_CK1 |
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M_CLK_DDR3 |
<19> |
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||
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DDR_A_D5 |
AH60 |
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AU43 |
DDR_CKE0_DIMMA |
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DDR_CKE0_DIMMA <18> |
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DDR_B_D4 |
AV31 |
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SA_DQ5 |
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SA_CKE0 |
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SB_DQ4 |
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DDR_A_D6 |
AK61 |
SA_DQ6 |
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SA_CKE1 |
AW43 |
DDR_CKE1_DIMMA |
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DDR_CKE1_DIMMA |
<18> |
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DDR_B_D5 |
AU31 |
SB_DQ5 |
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SB_CKE0 |
AY49 |
DDR_CKE2_DIMMB |
DDR_CKE2_DIMMB <19> |
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DDR_A_D7 |
AK60 |
SA_DQ7 |
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SA_CKE2 |
AY42 |
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DDR_B_D6 |
AV29 |
SB_DQ6 |
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SB_CKE1 |
AU50 |
DDR_CKE3_DIMMB |
DDR_CKE3_DIMMB |
<19> |
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DDR_A_D8 |
AM63 |
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AY43 |
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DDR_B_D7 |
AU29 |
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AW49 |
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SA_DQ8 |
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SA_CKE3 |
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SB_DQ7 |
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SB_CKE2 |
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DDR_A_D9 |
AM62 |
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DDR_B_D8 |
AY27 |
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AV50 |
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SA_DQ9 |
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SB_DQ8 |
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SB_CKE3 |
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DDR_A_D10 |
AP63 |
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AP33 |
DDR_CS0_DIMMA# |
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DDR_CS0_DIMMA# <18> |
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DDR_B_D9 |
AW27 |
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SA_DQ10 |
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SA_CS#0 |
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SB_DQ9 |
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DDR_A_D11 |
AP62 |
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AR32 |
DDR_CS1_DIMMA# |
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DDR_B_D10 |
AY25 |
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AM32 |
DDR_CS2_DIMMB# |
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SA_DQ11 |
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SA_CS#1 |
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DDR_CS1_DIMMA# |
<18> |
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SB_DQ10 |
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SB_CS#0 |
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DDR_CS2_DIMMB# <19> |
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DDR_A_D12 |
AM61 |
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DDR_B_D11 |
AW25 |
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AK32 |
DDR_CS3_DIMMB# |
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SA_DQ12 |
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SB_DQ11 |
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SB_CS#1 |
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DDR_CS3_DIMMB# |
<19> |
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DDR_A_D13 |
AM60 |
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AP32 |
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DDR_B_D12 |
AV27 |
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SA_DQ13 |
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SA_ODT0 |
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SB_DQ12 |
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DDR_A_D14 |
AP61 |
SA_DQ14 |
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DDR_B_D13 |
AU27 |
SB_DQ13 |
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SB_ODT0 |
AL32 |
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DDR_A_D15 |
AP60 |
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AY34 |
DDR_A_RAS# |
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DDR_A_RAS# <18> |
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DDR_B_D14 |
AV25 |
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SA_DQ15 |
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SA_RAS |
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SB_DQ14 |
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DDR_A_D16 |
AP58 |
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AW34 |
DDR_A_WE# |
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DDR_B_D15 |
AU25 |
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AM35 |
DDR_B_RAS# |
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SA_DQ16 |
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SA_WE |
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DDR_A_WE# <18> |
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SB_DQ15 |
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SB_RAS |
DDR_B_RAS# <19> |
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DDR_A_D17 |
AR58 |
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AU34 |
DDR_A_CAS# |
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DDR_B_D16 |
AM29 |
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AK35 |
DDR_B_WE# |
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DDR_A_CAS# |
<18> |
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DDR_B_WE# <19> |
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SA_DQ17 |
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SA_CAS |
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SB_DQ16 |
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SB_WE |
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DDR_A_D18 |
AM57 |
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DDR_B_D17 |
AK29 |
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AM33 |
DDR_B_CAS# |
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DDR_B_CAS# |
<19> |
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SA_DQ18 |
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SB_DQ17 |
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SB_CAS |
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DDR_A_D19 |
AK57 |
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AU35 |
DDR_A_BS0 |
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DDR_A_BS0 <18> |
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DDR_B_D18 |
AL28 |
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||||||||||||
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SA_DQ19 |
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SA_BA0 |
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SB_DQ18 |
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DDR_A_D20 |
AL58 |
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AV35 |
DDR_A_BS1 |
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DDR_B_D19 |
AK28 |
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AL35 |
DDR_B_BS0 |
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||||||||||||
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SA_DQ20 |
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SA_BA1 |
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DDR_A_BS1 <18> |
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SB_DQ19 |
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SB_BA0 |
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DDR_B_BS0 <19> |
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DDR_A_D21 |
AK58 |
|
AY41 |
DDR_A_BS2 |
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DDR_B_D20 |
AR29 |
|
AM36 |
DDR_B_BS1 |
|
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SA_DQ21 |
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SA_BA2 |
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DDR_A_BS2 |
<18> |
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SB_DQ20 |
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SB_BA1 |
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DDR_B_BS1 <19> |
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DDR_A_D22 |
AR57 |
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DDR_B_D21 |
AN29 |
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AU49 |
DDR_B_BS2 |
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SA_DQ22 |
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DDR_A_MA[0..15] <18> |
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SB_DQ21 |
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SB_BA2 |
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DDR_B_BS2 |
<19> |
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||||||
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DDR_A_D23 |
AN57 |
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AU36 |
DDR_A_MA0 |
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DDR_B_D22 |
AR28 |
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SA_DQ23 |
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SA_MA0 |
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SB_DQ22 |
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DDR_B_MA[0..15] <19> |
||||
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DDR_A_D24 |
AP55 |
|
AY37 |
DDR_A_MA1 |
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DDR_B_D23 |
AP28 |
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AP40 |
DDR_B_MA0 |
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SA_DQ24 |
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SA_MA1 |
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SB_DQ23 |
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SB_MA0 |
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||
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DDR_A_D25 |
AR55 |
|
AR38 |
DDR_A_MA2 |
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DDR_B_D24 |
AN26 |
|
AR40 |
DDR_B_MA1 |
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SA_DQ25 |
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SA_MA2 |
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SB_DQ24 |
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SB_MA1 |
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||
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DDR_A_D26 |
AM54 |
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AP36 |
DDR_A_MA3 |
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DDR_B_D25 |
AR26 |
|
AP42 |
DDR_B_MA2 |
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SA_DQ26 |
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SA_MA3 |
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SB_DQ25 |
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SB_MA2 |
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||
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DDR_A_D27 |
AK54 |
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AU39 |
DDR_A_MA4 |
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DDR_B_D26 |
AR25 |
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AR42 |
DDR_B_MA3 |
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SA_DQ27 |
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SA_MA4 |
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SB_DQ26 |
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SB_MA3 |
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||
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DDR_A_D28 |
AL55 |
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AR36 |
DDR_A_MA5 |
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DDR_B_D27 |
AP25 |
|
AR45 |
DDR_B_MA4 |
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|||||||||||||
C |
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SA_DQ28 |
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SA_MA5 |
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SB_DQ27 |
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SB_MA4 |
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C |
||
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DDR_A_D29 |
AK55 |
SA_DQ29 |
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SA_MA6 |
AV40 |
DDR_A_MA6 |
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DDR_B_D28 |
AK26 |
SB_DQ28 |
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SB_MA5 |
AP45 |
DDR_B_MA5 |
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DDR_A_D30 |
AR54 |
SA_DQ30 |
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SA_MA7 |
AW39 |
DDR_A_MA7 |
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DDR_B_D29 |
AM26 |
SB_DQ29 |
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SB_MA6 |
AW46 |
DDR_B_MA6 |
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|||||||
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DDR CHANNEL A |
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DDR_A_D31 |
AN54 |
SA_DQ31 |
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SA_MA8 |
AY39 |
DDR_A_MA8 |
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DDR_B_D30 |
AK25 |
SB_DQ30 |
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SB_MA7 |
AY46 |
DDR_B_MA7 |
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DDR_A_D32 |
AY58 |
|
AU40 |
DDR_A_MA9 |
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DDR_B_D31 |
AL25 |
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AY47 |
DDR_B_MA8 |
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SA_DQ32 |
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SA_MA9 |
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SB_DQ31 |
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SB_MA8 |
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||
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DDR_A_D33 |
AW58 |
|
AP35 |
DDR_A_MA10 |
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DDR_B_D32 |
AY23 |
DDR CHANNEL B |
AU46 |
DDR_B_MA9 |
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SA_DQ33 |
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SA_MA10 |
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SB_DQ32 |
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SB_MA9 |
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|||
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DDR_A_D34 |
AY56 |
|
AW41 |
DDR_A_MA11 |
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DDR_B_D33 |
AW23 |
|
AK36 |
DDR_B_MA10 |
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|||||||||||||
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SA_DQ34 |
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SA_MA11 |
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SB_DQ33 |
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SB_MA10 |
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||||
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DDR_A_D35 |
AW56 |
|
AU41 |
DDR_A_MA12 |
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DDR_B_D34 |
AY21 |
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AV47 |
DDR_B_MA11 |
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SA_DQ35 |
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SA_MA12 |
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SB_DQ34 |
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SB_MA11 |
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DDR_A_D36 |
AV58 |
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AR35 |
DDR_A_MA13 |
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DDR_B_D35 |
AW21 |
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AU47 |
DDR_B_MA12 |
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SA_DQ36 |
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SA_MA13 |
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SB_DQ35 |
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SB_MA12 |
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DDR_A_D37 |
AU58 |
SA_DQ37 |
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SA_MA14 |
AV42 |
DDR_A_MA14 |
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DDR_B_D36 |
AV23 |
SB_DQ36 |
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SB_MA13 |
AK33 |
DDR_B_MA13 |
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DDR_A_D38 |
AV56 |
SA_DQ38 |
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SA_MA15 |
AU42 |
DDR_A_MA15 |
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DDR_B_D37 |
AU23 |
SB_DQ37 |
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SB_MA14 |
AR46 |
DDR_B_MA14 |
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DDR_A_D39 |
AU56 |
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DDR_A_DQS#[0..7] <18> |
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DDR_B_D38 |
AV21 |
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AP46 |
DDR_B_MA15 |
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SA_DQ39 |
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SB_DQ38 |
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SB_MA15 |
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DDR_A_D40 |
AY54 |
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AJ61 |
DDR_A_DQS#0 |
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DDR_B_D39 |
AU21 |
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DDR_B_DQS#[0..7] <19> |
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SA_DQ40 |
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SA_DQSN0 |
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SB_DQ39 |
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DDR_A_D41 |
AW54 |
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AN62 |
DDR_A_DQS#1 |
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DDR_B_D40 |
AY19 |
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AW30 |
DDR_B_DQS#0 |
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SA_DQ41 |
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SA_DQSN1 |
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SB_DQ40 |
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SB_DQSN0 |
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DDR_A_D42 |
AY52 |
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AM58 |
DDR_A_DQS#2 |
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DDR_B_D41 |
AW19 |
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AV26 |
DDR_B_DQS#1 |
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SA_DQ42 |
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SA_DQSN2 |
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SB_DQ41 |
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SB_DQSN1 |
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DDR_A_D43 |
AW52 |
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AM55 |
DDR_A_DQS#3 |
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DDR_B_D42 |
AY17 |
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AN28 |
DDR_B_DQS#2 |
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SA_DQ43 |
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SA_DQSN3 |
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SB_DQ42 |
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SB_DQSN2 |
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DDR_A_D44 |
AV54 |
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AV57 |
DDR_A_DQS#4 |
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DDR_B_D43 |
AW17 |
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AN25 |
DDR_B_DQS#3 |
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SA_DQ44 |
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SA_DQSN4 |
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SB_DQ43 |
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SB_DQSN3 |
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DDR_A_D45 |
AU54 |
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AV53 |
DDR_A_DQS#5 |
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DDR_B_D44 |
AV19 |
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AW22 |
DDR_B_DQS#4 |
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SA_DQ45 |
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SA_DQSN5 |
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SB_DQ44 |
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SB_DQSN4 |
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DDR_A_D46 |
AV52 |
SA_DQ46 |
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SA_DQSN6 |
AL43 |
DDR_A_DQS#6 |
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DDR_B_D45 |
AU19 |
SB_DQ45 |
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SB_DQSN5 |
AV18 |
DDR_B_DQS#5 |
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DDR_A_D47 |
AU52 |
|
AL48 |
DDR_A_DQS#7 |
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DDR_B_D46 |
AV17 |
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AN21 |
DDR_B_DQS#6 |
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SA_DQ47 |
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SA_DQSN7 |
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SB_DQ46 |
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SB_DQSN6 |
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DDR_A_D48 |
AK40 |
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DDR_A_DQS[0..7] <18> |
|
DDR_B_D47 |
AU17 |
|
AN18 |
DDR_B_DQS#7 |
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SA_DQ48 |
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SB_DQ47 |
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SB_DQSN7 |
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DDR_A_D49 |
AK42 |
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AJ62 |
DDR_A_DQS0 |
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DDR_B_D48 |
AR21 |
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DDR_B_DQS[0..7] <19> |
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SA_DQ49 |
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SA_DQSP0 |
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SB_DQ48 |
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DDR_A_D50 |
AM43 |
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AN61 |
DDR_A_DQS1 |
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DDR_B_D49 |
AR22 |
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AV30 |
DDR_B_DQS0 |
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SA_DQ50 |
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SA_DQSP1 |
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SB_DQ49 |
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SB_DQSP0 |
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DDR_A_D51 |
AM45 |
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AN58 |
DDR_A_DQS2 |
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DDR_B_D50 |
AL21 |
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AW26 |
DDR_B_DQS1 |
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SA_DQ51 |
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SA_DQSP2 |
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SB_DQ50 |
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SB_DQSP1 |
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DDR_A_D52 |
AK45 |
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AN55 |
DDR_A_DQS3 |
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DDR_B_D51 |
AM22 |
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AM28 |
DDR_B_DQS2 |
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SA_DQ52 |
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SA_DQSP3 |
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SB_DQ51 |
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SB_DQSP2 |
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DDR_A_D53 |
AK43 |
SA_DQ53 |
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SA_DQSP4 |
AW57 |
DDR_A_DQS4 |
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DDR_B_D52 |
AN22 |
SB_DQ52 |
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SB_DQSP3 |
AM25 |
DDR_B_DQS3 |
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DDR_A_D54 |
AM40 |
SA_DQ54 |
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SA_DQSP5 |
AW53 |
DDR_A_DQS5 |
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DDR_B_D53 |
AP21 |
SB_DQ53 |
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SB_DQSP4 |
AV22 |
DDR_B_DQS4 |
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DDR_A_D55 |
AM42 |
SA_DQ55 |
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SA_DQSP6 |
AL42 |
DDR_A_DQS6 |
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DDR_B_D54 |
AK21 |
SB_DQ54 |
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SB_DQSP5 |
AW18 |
DDR_B_DQS5 |
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DDR_A_D56 |
AM46 |
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AL49 |
DDR_A_DQS7 |
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DDR_B_D55 |
AK22 |
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AM21 |
DDR_B_DQS6 |
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SA_DQ56 |
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SA_DQSP7 |
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SB_DQ55 |
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SB_DQSP6 |
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DDR_A_D57 |
AK46 |
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DDR_B_D56 |
AN20 |
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AM18 |
DDR_B_DQS7 |
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SA_DQ57 |
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SB_DQ56 |
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SB_DQSP7 |
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||
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DDR_A_D58 |
AM49 |
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AP49 |
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+SM_VREF_CA |
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DDR_B_D57 |
AR20 |
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SA_DQ58 |
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SM_VREF_CA |
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SB_DQ57 |
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DDR_A_D59 |
AK49 |
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AR51 |
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DDR_B_D58 |
AK18 |
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||||||||||
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SA_DQ59 |
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SM_VREF_DQ0 |
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+SM_VREF_DQ0 |
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SB_DQ58 |
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||||
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DDR_A_D60 |
AM48 |
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AP51 |
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DDR_B_D59 |
AL18 |
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||||||||||
B |
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SA_DQ60 |
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SM_VREF_DQ1 |
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+SM_VREF_DQ1 |
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SB_DQ59 |
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B |
||||
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DDR_A_D61 |
AK48 |
SA_DQ61 |
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DDR_B_D60 |
AK20 |
SB_DQ60 |
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DDR_A_D62 |
AM51 |
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DDR_B_D61 |
AM20 |
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|||
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SA_DQ62 |
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SB_DQ61 |
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DDR_A_D63 |
AK51 |
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DDR_B_D62 |
AR18 |
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|||
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SA_DQ63 |
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SB_DQ62 |
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DDR_B_D63 |
AP18 |
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SB_DQ63 |
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BDW-ULT-DDR3L_BGA1168 |
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BDW-ULT-DDR3L_BGA1168 |
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3 OF 19 |
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4 OF 19 |
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A |
A |
DELL CONFIDENTIAL/PROPRIETARY
|
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Compal Electronics, Inc. |
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PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL |
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Title |
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TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT |
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CPU (3/12) |
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BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, |
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NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD |
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LA-A971P |
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0.1 |
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PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. |
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Date: |
Wednesday, March 19, 2014 |
Sheet 8 |
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48 |
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D
C
B
A
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1 |
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@ RC77 |
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2 0_0402_5% |
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+3.3V_RUN |
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+3.3V_RUN |
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+3.3V_ALW2 |
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+3.3V_ALW_PCH |
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5 |
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5 |
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XDP_DBRESET# |
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P |
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PCH_PLTRST# |
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P |
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5 |
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+RTC_CELL |
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ME_SUS_PWR_ACK |
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B |
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SYS_RESET# |
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4PCH_PLTRST#_EC |
PCH_PLTRST#_EC |
<20,27,30,35,36> |
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SIO_SLP_A# |
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RC79 |
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10K_0402_5% |
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1 ME_RESET# |
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O |
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B |
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PM_APWROK_R |
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SUSACK# |
@ RC80 |
8.2K_0402_5% |
A |
G |
@ UC4 |
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UC5 |
A |
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<43> 1.05V_M_PWRGD |
PM_APWROK |
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2 |
PM_APWROK_L |
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O |
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RC78 0402330K |
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@ RC304 |
<36> |
PM_APWROK |
2 |
G |
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RC81 |
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10K_0402_5% |
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74AHC1G09GW _TSSOP5 |
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TC7SH08FU_SSOP5~D |
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100K_0402_5% |
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@ RC26 |
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0_0402_5% |
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UC6 |
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SUS_STAT#/LPCPD# |
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TC7SH08FU_SSOP5~D |
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@ RC82 |
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10K_0402_5% |
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+PCH_VCCDSW3_3 |
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2 |
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@ RC27 |
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0_0402_5% |
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1 |
5% |
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DSWODVREN |
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RPC1 |
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Fix Intel 7260 can not detect issue. |
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4 |
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5 PCH_PCIE_WAKE# |
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It will cause “floating” situation before 3V_RUN coming of AND gate |
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AC_PRESENT |
<36,9> |
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1 |
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PCH_BATLOW# |
<9> |
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<22> |
PLTRST_VMM2320# |
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@ RC2191 |
2 |
0_0402_5% |
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@ RC87 1 |
2 |
0_0402_5% |
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DSWODVREN - ON DIE DSW VR ENABLE |
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<27> |
PLTRST_USH# |
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10K_8P4R_5% |
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@ RC88 1 |
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0_0402_5% |
PCH_PLTRST# |
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<29> |
PLTRST_MMI# |
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2 |
PM_LANPHY_ENABLE |
PM_LANPHY_ENABLE <12,28> |
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<28> |
PLTRST_LAN# |
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@ RC89 1 |
2 |
0_0402_5% |
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HIGH = ENABLED (DEFAULT) |
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@ RC92 |
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10K_0402_5% |
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LOW = DISABLED |
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PCH_RSMRST#_Q |
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RC91 |
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47K_0402_5% |
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UC1H |
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BDW_ULT_DDR3L |
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SYSTEM POWER MANAGEMENT |
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<36> SUSACK# |
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SUSACK# |
AK2 |
SUSACK |
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DSWVRMEN |
AW7 |
DSWODVREN |
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JAPS1 |
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SYS_RESET# |
AC3 |
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AV5 |
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PCH_DPWROK |
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+3.3V_ALW_PCH |
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1 |
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+3.3V_RUN |
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SYS_PWROK |
AG2 |
SYS_RESET |
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DPWROK |
AJ5 |
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PCH_PCIE_WAKE# |
PCH_DPWROK |
<36> |
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SIO_SLP_S3# |
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1 |
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<36> |
SYS_PWROK |
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AY7 |
SYS_PWROK |
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WAKE |
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PCH_PCIE_WAKE# |
<35,36> |
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+PCH_VCCDSW3_3 |
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3 |
2 |
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<15,36> |
RESET_OUT# |
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PM_APWROK_R |
AB5 |
PCH_PWROK |
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SIO_SLP_S5# |
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3 |
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1 |
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ME_RESET# |
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PCH_PLTRST# |
AG7 |
APWROK |
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CLKRUN/GPIO32 |
V5 |
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CLKRUN# |
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CLKRUN# |
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<10,35,36> |
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SIO_SLP_S4# |
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5 |
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@ RC95 |
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8.2K_0402_5% |
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PLTRST |
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AG4 |
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SUS_STAT#/LPCPD# |
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SIO_SLP_A# |
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6 |
5 |
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SUS_STAT/GPIO61 |
AE6 |
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SUSCLK_R |
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SUSCLK |
<30> |
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+PCH_VCCDSW3_3 |
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7 |
6 |
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SUSCLK/GPIO62 |
AP5 |
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SIO_SLP_S5# |
@ RC136 |
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0_0402_5% |
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8 |
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<37> PCH_RSMRST#_Q |
PCH_RSMRST#_Q |
AW6 |
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SLP_S5/GPIO63 |
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SIO_SLP_S5# <36> |
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<6> PCH_RTCRST# |
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PCH_RTCRST# |
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ME_SUS_PWR_ACK |
AV4 |
RSMRST |
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T8 |
PAD~D@ |
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10 |
9 |
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<36> |
ME_SUS_PWR_ACK |
SIO_PWRBTN# |
AL7 |
SUSWARN/SUSPWRDNACK/GPIO30 |
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AJ6 |
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SIO_SLP_S4# |
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T9 |
PAD~D @ |
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11 |
10 |
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<36> |
SIO_PWRBTN# |
PWRBTN |
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SLP_S4 |
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SIO_SLP_S4# <36> |
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<36,39> |
POWER_SW#_MB |
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11 |
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AC_PRESENT |
AJ8 |
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AT4 |
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SIO_SLP_S3# |
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12 |
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<36,9> |
AC_PRESENT |
PCH_BATLOW# |
AN4 |
ACPRESENT/GPIO31 |
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SLP_S3 |
AL5 |
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SIO_SLP_A# |
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SIO_SLP_S3# |
<36> |
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SYS_RESET# |
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13 |
12 |
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<9> |
PCH_BATLOW# |
SIO_SLP_S0# |
AF3 |
BATLOW/GPIO72 |
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SLP_A |
AP4 |
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SIO_SLP_SUS# |
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SIO_SLP_A# <36> |
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14 |
13 |
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SIO_SLP_WLAN# |
AM5 |
SLP_S0 |
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SLP_SUS |
AJ7 |
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SIO_SLP_LAN# |
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SIO_SLP_SUS# <36> |
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SIO_SLP_S0# |
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15 |
14 |
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<35> |
SIO_SLP_WLAN# |
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SLP_WLAN/GPIO29 |
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SLP_LAN |
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SIO_SLP_LAN# |
<28,36> |
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16 |
15 |
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17 |
16 |
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18 |
17 |
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19 |
18 |
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20 |
GND |
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+3.3V_RUN |
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BDW-ULT-DDR3L_BGA1168 |
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GND |
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8 OF 19 |
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CONN@ |
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CC17 CXDP@ |
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ACES_50506-01841-P01 |
C |
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2 |
1 |
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UC7 CXDP@ |
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0.1U_0402_25V6 |
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+1.05V_RUN |
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20130726 same as Goliad |
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+1.05V_RUN |
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+1.05V_RUN |
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14 |
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VCC |
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<6> |
PCH_JTAG_TDO |
1 |
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2 |
TDO_XDP |
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2 |
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3 |
CPU_XDP_TDO |
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.0 |
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.0 |
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RC98 |
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0_0402_5% |
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1A |
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1B |
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JXDP1 |
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CXDP@ |
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@ |
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@ |
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1 |
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2 |
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RUNPWROK |
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1 |
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2 1 |
CC18 25V604021U |
2 1 |
CC19 25V604021U |
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CPU_XDP_PREQ# |
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3 |
GND0 |
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GND1 |
4 |
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CFG17 |
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CFG17 |
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<13> |
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1OE |
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CPU_XDP_PRDY# |
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5 |
OBSFN_A0 |
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OBSFN_C0 |
6 |
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CFG16 |
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PCH_JTAG_TDI 1 |
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2 |
TDI_XDP_R |
5 |
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6 |
CPU_XDP_TDI |
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OBSFN_A1 |
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OBSFN_C1 |
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CFG16 |
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<13> |
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<6> PCH_JTAG_TDI |
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7 |
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8 |
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RC99 |
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0_0402_5% |
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2A |
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2B |
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<13> |
CFG0 |
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CFG0 |
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9 |
GND2 |
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GND3 |
10 |
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CFG8 |
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CFG8 |
<13> |
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CXDP@ |
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CFG1 |
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11 |
OBSDATA_A0 |
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OBSDATA_C0 |
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CFG9 |
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RUNPWROK |
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4 |
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<13> |
CFG1 |
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OBSDATA_A1 |
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OBSDATA_C1 |
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CFG9 |
<13> |
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13 |
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14 |
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2OE |
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<13> |
CFG2 |
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CFG2 |
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15 |
GND4 |
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GND5 |
16 |
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CFG10 |
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CFG10 |
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<13> |
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<6> |
PCH_JTAG_TMS |
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PCH_JTAG_TMS 9 |
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8 |
CPU_XDP_TMS |
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<13> |
CFG3 |
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CFG3 |
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17 |
OBSDATA_A2 |
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OBSDATA_C2 |
18 |
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CFG11 |
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CFG11 |
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<13> |
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3A |
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3B |
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Place near JXDP1 |
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19 |
OBSDATA_A3 |
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OBSDATA_C3 |
20 |
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XDP_OBS0_R |
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21 |
GND6 |
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GND7 |
22 |
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CFG19 |
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CFG19 |
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<13> |
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RUNPWROK |
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10 |
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XDP_OBS1_R |
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23 |
OBSFN_B0 |
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OBSFN_D0 |
24 |
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CFG18 |
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OBSFN_B1 |
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OBSFN_D1 |
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CFG18 |
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<13> |
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3OE |
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25 |
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26 |
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TRST#_XDP |
12 |
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11 |
CPU_XDP_TRST# |
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<13> |
CFG4 |
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CFG4 |
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27 |
GND8 |
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GND9 |
28 |
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CFG12 |
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CFG12 |
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<13> |
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OBSDATA_B0 |
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OBSDATA_D0 |
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4A |
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4B |
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<13> |
CFG5 |
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CFG5 |
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29 |
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30 |
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CFG13 |
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CFG13 |
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<13> |
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31 |
OBSDATA_B1 |
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OBSDATA_D1 |
32 |
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RC5 need to close to JCPU1 |
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GND10 |
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GND11 |
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<35,36> |
RUNPWROK |
RUNPWROK |
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13 |
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7 |
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<13> |
CFG6 |
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CFG6 |
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33 |
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34 |
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CFG14 |
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CFG14 |
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<13> |
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4OE |
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GND |
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RC102 |
1 |
2 1K_0402_5% |
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CFG7 |
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35 |
OBSDATA_B2 |
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OBSDATA_D2 |
36 |
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CFG15 |
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<15> H_VCCST_PWRGD |
<13> |
CFG7 |
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OBSDATA_B3 |
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OBSDATA_D3 |
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CFG15 |
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<13> |
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15 |
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CXDP@ |
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37 |
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38 |
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GND PAD |
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H_CPUPWRGD @ RC103 |
1 |
2 1K_0402_5% |
H_VCCST_PWRGD_XDP |
39 |
GND12 |
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GND13 |
40 |
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PWRGOOD/HOOK0 |
ITPCLK/HOOK4 |
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SIO_PWRBTN# |
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41 |
42 |
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74CBTLV3126BQ_DHVQFN14_2P5X3 |
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43 |
HOOK1 |
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ITPCLK#/HOOK5 |
44 |
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45 |
VCC_OBS_AB |
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VCC_OBS_CD |
46 |
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XDP_RST#_R |
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2 |
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1 |
PCH_PLTRST#_EC |
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<15> |
CPU_PWR_DEBUG# |
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HOOK2 |
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RESET#/HOOK6 |
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reference Shark Bay ULT Validation Customer Debug Port |
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SYS_PWROK |
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47 |
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48 |
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XDP_DBRESET# |
RC106 |
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1K_0402_5% |
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HOOK3 |
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DBR#/HOOK7 |
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49 |
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50 |
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CXDP@ |
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Implementation Requirement Rev 1.0 |
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<18,19,7> DDR_XDP_WAN_SMBDAT |
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51 |
GND14 |
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GND15 |
52 |
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TDO_XDP |
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<6> |
PCH_JTAG_TRST# |
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2 |
1 |
CPU_XDP_TRST# |
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53 |
SDA |
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TD0 |
54 |
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TRST#_XDP |
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0_0402_5% |
RC109 |
CXDP@ |
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<18,19,7> DDR_XDP_WAN_SMBCLK |
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55 |
SCL |
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TRST# |
56 |
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PCH_JTAG_TDI |
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<6> PCH_JTAG_TCK |
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TCK1 |
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TDI |
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CPU_XDP_TCLK |
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57 |
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58 |
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PCH_JTAG_TMS |
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+1.05V_VCCST |
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<6> |
PCH_JTAG_JTAGX |
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2 |
1 |
CPU_XDP_TCLK |
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59 |
TCK0 |
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TMS |
60 |
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CFG3_R |
1 |
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2 |
CFG3 |
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0_0402_5% |
RC112 |
CXDP@ |
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GND16 |
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GND17 |
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RC113 |
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1K_0402_5% |
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1 |
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2 |
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H_CATERR# |
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SAMTE_BSH-030-01-L-D-A |
CONN@ |
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CXDP@ |
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+1.05V_RUN |
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@ RC114 |
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49.9_0402_1% |
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2 |
1 |
TDO_XDP |
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1 |
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2 |
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H_PROCHOT# |
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0_0402_5% |
RC115 @ |
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RC116 |
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62_0402_5% |
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+3.3V_ALW_PCH |
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TDO_XDP |
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2 |
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1 |
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B |
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PCH_JTAG_TDO |
2 |
1 |
TDI_XDP_R |
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51_0402_5% |
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@ RC117 |
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0_0402_5% |
RC118 @ |
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PCH_JTAG_TCK 2 |
1 |
CPU_XDP_TCLK |
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2 |
CXDP@ RC120 1K |
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0_0402_5% |
RC119 @ |
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H_PROCHOT# |
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Place near JXDP1.48 |
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XDP_DBRESET# |
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1 |
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@EMC@ |
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CC20 |
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SYS_PWROK |
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22P_0402_50V8J |
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CC22 @ 25V6 0402 1U.0 |
2 1 1 |
04025%_ |
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2 1 |
25V604021U0. |
CXDP@CC21 |
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2 |
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UC1B |
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BDW_ULT_DDR3L |
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||||||||
EMI request add |
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D61 |
PROC_DETECT |
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H_CATERR# |
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K61 |
MISC |
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<36> PECI_EC |
|
PECI_EC |
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N62 |
CATERR |
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PRDY |
J62 |
CPU_XDP_PRDY# |
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Place near JXDP1.47 |
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PECI |
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K62 |
CPU_XDP_PREQ# |
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+3.3V_RUN |
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PREQ |
E60 |
CPU_XDP_TCLK |
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PROC_TCK |
E61 |
CPU_XDP_TMS |
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||
H_CPUPWRGD |
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<36,45,46> |
H_PROCHOT# |
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1 |
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2 |
H_PROCHOT#_R |
K63 |
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JTAG |
PROC_TMS |
E59 |
CPU_XDP_TRST# |
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XDP_DBRESET# |
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2 |
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1 |
RC122 |
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||||||||||||
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PROCHOT |
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PROC_TRST |
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|||||||||||||||||||||||||||
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RC121 |
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56_0402_5% |
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THERMAL |
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F63 |
CPU_XDP_TDI |
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1K_0402_5% |
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|||||||||||
21 5%040210K RC123 |
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50V8J 0402 100P |
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PROC_TDI |
F62 |
CPU_XDP_TDO |
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@EMC@ |
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PROC_TDO |
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+1.05V_RUN |
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1 |
CC83 |
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H_CPUPWRGD |
C61 |
PROCPWRGD |
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PWR |
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CPU_XDP_TMS |
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2 |
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1 |
@ RC124 |
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BPM#0 |
J60 |
XDP_OBS0_R |
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51_0402_5% |
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|||||||
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H60 XDP_OBS1_R |
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CPU_XDP_TDI |
|
2 |
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1 |
@ RC125 |
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||||||||||
2 |
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BPM#1 |
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H61 |
XDP_OBS2_R |
PAD~D |
T10 |
@ |
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51_0402_5% |
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||||||||||
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BPM#2 |
H62 |
XDP_OBS3_R |
PAD~D |
T11 |
@ |
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CPU_XDP_PREQ# |
2 |
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1 |
@ RC126 |
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BPM#3 |
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SM_RCOMP0 |
AU60 |
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K59 |
XDP_OBS4_R |
PAD~D |
T12 |
@ |
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51_0402_5% |
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SM_RCOMP1 |
AV60 |
SM_RCOMP0 |
DDR3L |
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BPM#4 |
H63 |
XDP_OBS5_R |
PAD~D |
T13 |
@ |
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CPU_XDP_TDO |
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RC127 |
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SM_RCOMP1 |
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BPM#5 |
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CAD Note: |
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SM_RCOMP2 |
AU61 |
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K60 |
XDP_OBS6_R |
PAD~D |
T14 |
@ |
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51_0402_5% |
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SM_RCOMP2 |
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BPM#6 |
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<18> DDR3_DRAMRST#_CPU |
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AV15 |
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J61 |
XDP_OBS7_R |
PAD~D |
T15 |
@ |
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Avoid stub in the PWRGD path |
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AV61 |
SM_DRAMRST |
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BPM#7 |
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<18> |
DDR_PG_CTRL |
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SM_PG_CNTL1 |
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while placing resistors RC123 |
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CPU_XDP_TCLK |
2 |
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1 |
RC128 |
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51_0402_5% |
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CPU_XDP_TRST# 2 |
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1 |
@ RC129 |
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BDW-ULT-DDR3L_BGA1168 |
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51_0402_5% |
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A |
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2 OF 19 |
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DDR3 COMPENSATION SIGNALS |
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200_0402_1% |
2 |
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1 |
RC130 |
SM_RCOMP0 |
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121_0402_1% |
2 |
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1 |
RC131 |
SM_RCOMP1 |
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100_0402_1% |
2 |
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1 |
RC132 |
SM_RCOMP2 |
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DELL CONFIDENTIAL/PROPRIETARY |
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CAD Note: |
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Compal Electronics, Inc. |
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PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL |
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Title |
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Trace width=12~15 mil, Spcing=20 mils |
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TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT |
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CPU (4/12) |
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Max trace length= 500 mil |
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BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, |
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Size |
Document Number |
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Rev |
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NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD |
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LA-A971P |
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0.1 |
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PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. |
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Date: |
Wednesday, March 19, 2014 |
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Sheet |
9 |
of |
48 |
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5 |
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4 |
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3 |
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2 |
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1 |
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5 |
4 |
3 |
2 |
1 |
D |
D |
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UC1A |
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BDW_ULT_DDR3L |
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<25> |
DDI1_LANE_N0 |
C54 |
DDI1_TXN0 |
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EDP_TXN0 |
C45 |
EDP_CPU_LANE_N0 |
EDP_CPU_LANE_N0 <23> |
COMPENSATION PU FOR eDP |
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C55 |
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B46 |
EDP_CPU_LANE_P0 |
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<25> DDI1_LANE_P0 |
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DDI1_TXP0 |
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EDP_TXP0 |
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EDP_CPU_LANE_P0 |
<23> |
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B58 |
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A47 |
EDP_CPU_LANE_N1 |
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<25> DDI1_LANE_N1 |
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DDI1_TXN1 |
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EDP_TXN1 |
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EDP_CPU_LANE_N1 |
<23> |
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C58 |
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B47 |
EDP_CPU_LANE_P1 |
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<25> |
DDI1_LANE_P1 |
B55 |
DDI1_TXP1 |
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EDP_TXP1 |
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EDP_CPU_LANE_P1 |
<23> |
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+VCCIOA_OUT |
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<25> DDI1_LANE_N2 |
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DDI1_TXN2 |
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A55 |
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C47 |
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<25> DDI1_LANE_P2 |
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DDI1_TXP2 |
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EDP_TXN2 |
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A57 |
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C46 |
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EDP_COMP 2 |
1 |
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<25> DDI1_LANE_N3 |
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DDI1_TXN3 |
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EDP_TXP2 |
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B57 |
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A49 |
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24.9_0402_1% |
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RC133 |
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<25> |
DDI1_LANE_P3 |
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DDI1_TXP3 |
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EDP_TXN3 |
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DDI |
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EDP_TXP3 |
B49 |
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<24> DDI2_LANE_N0 |
C51 |
DDI2_TXN0 |
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CAD Note:Trace width=20 mils ,Spacing=25mil, |
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C50 |
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A45 |
EDP_CPU_AUX# |
EDP_CPU_AUX# <23> |
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<24> |
DDI2_LANE_P0 |
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DDI2_TXP0 |
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EDP_AUXN |
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Max length=100 mils. |
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C53 |
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B45 |
EDP_CPU_AUX |
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<24> DDI2_LANE_N1 |
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DDI2_TXN1 |
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EDP_AUXP |
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EDP_CPU_AUX <23> |
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B54 |
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<24> DDI2_LANE_P1 |
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DDI2_TXP1 |
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C49 |
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D20 |
EDP_COMP |
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<24> DDI2_LANE_N2 |
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DDI2_TXN2 |
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EDP_RCOMP |
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<24> DDI2_LANE_P2 |
B50 |
DDI2_TXP2 |
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EDP_DISP_UTIL |
A43 |
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A53 |
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<24> DDI2_LANE_N3 |
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DDI2_TXN3 |
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B53 |
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<24> DDI2_LANE_P3 |
DDI2_TXP3 |
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C |
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C |
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BDW-ULT-DDR3L_BGA1168 |
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1 OF 19 |
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+3.3V_RUN |
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RPC15 |
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5 |
4 |
SIO_RCIN# |
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<12,36> |
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BDW_ULT_DDR3L |
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6 |
3 |
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UC1I |
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+3.3V_RUN |
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CLKRUN# |
<35,36,9> |
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7 |
2 |
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USH_DET# |
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<12,27> |
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8 |
1 |
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RPC2 |
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IRQ_SERIRQ |
<12,35,36> |
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CPU_DPB_CTRLDAT |
1 |
8 |
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10K_8P4R_5% |
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CPU_DPB_CTRLCLK |
2 |
7 |
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<23> EDP_BIA_PWM |
EDP_BIA_PWM |
B8 |
EDP_BKLCTL |
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DDPB_CTRLCLK |
B9 |
CPU_DPB_CTRLCLK |
CPU_DPB_CTRLCLK <25> |
CPU_DPC_CTRLCLK |
3 |
6 |
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PANEL_BKLEN |
A9 |
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C9 |
CPU_DPB_CTRLDAT |
CPU_DPC_CTRLDAT |
4 |
5 |
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<23> |
PANEL_BKLEN |
ENVDD_PCH |
C6 |
EDP_BKLEN |
eDP SIDEBAND |
DDPB_CTRLDATA |
D9 |
CPU_DPC_CTRLCLK |
CPU_DPB_CTRLDAT <25> |
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<23,36> |
ENVDD_PCH |
EDP_VDDEN |
DDPC_CTRLCLK |
CPU_DPC_CTRLCLK <24> |
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D11 |
CPU_DPC_CTRLDAT |
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2.2K_0804_8P4R_5% |
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DDPC_CTRLDATA |
CPU_DPC_CTRLDAT |
<24> |
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<27,7> |
CONTACTLESS_DET# |
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U6 |
PIRQA/GPIO77 |
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RPC20 |
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DGPU_PWROK |
P4 |
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C5 |
CPU_DPB_AUX# |
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CPU_DPB_AUX# |
1 |
8 |
|||||
1 |
2 |
ENVDD_PCH |
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<6> |
DGPU_PWROK |
HDD_FALL_INT |
N4 |
PIRQB/GPIO78 |
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DDPB_AUXN |
B6 |
CPU_DPC_AUX# |
CPU_DPB_AUX# <25> |
|
CPU_DPB_AUX |
2 |
7 |
|||
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<12> |
HDD_FALL_INT |
|
PIRQC/GPIO79 |
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DDPC_AUXN |
CPU_DPC_AUX# <24> |
|||||||||||||
@ RC139 |
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100K_0402_5% |
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N2 |
DISPLAY |
B5 |
CPU_DPB_AUX |
CPU_DPC_AUX |
3 |
6 |
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<12> |
PCH_GPIO80 |
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PIRQD/GPIO80 |
DDPB_AUXP |
CPU_DPB_AUX <25> |
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2 |
1 |
PCH_GPIO53 |
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AD4 |
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A6 |
CPU_DPC_AUX |
|
CPU_DPC_AUX# |
4 |
5 |
|||||||
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@ T16 |
PAD~D |
|
PME |
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DDPC_AUXP |
CPU_DPC_AUX |
<24> |
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@ RC140 |
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1K_0402_5% |
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PCIE |
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<12> TOUCHPAD_INTR# |
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U7 |
GPIO55 |
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100K_0804_8P4R_5% |
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L1 |
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<12> PCH_GPIO52 |
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GPIO52 |
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L3 |
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C8 |
DPB_HPD |
DPB_HPD |
<25> |
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GPIO54 |
DDPB_HPD |
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R5 |
A8 |
DPC_HPD |
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GPIO51 |
DDPC_HPD |
DPC_HPD |
<24> |
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PCH_GPIO53 |
L4 |
D6 |
EDP_CPU_HPD |
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GPIO53 |
EDP_HPD |
EDP_CPU_HPD <23> |
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B |
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EDP_CPU_HPD |
100K_0402_5% 2 |
1 |
RC141 |
B |
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DPB_HPD |
100K_0402_5% 2 |
1 |
RC142 |
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BDW-ULT-DDR3L_BGA1168 |
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9 OF 19 |
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A |
A |
DELL CONFIDENTIAL/PROPRIETARY
|
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Compal Electronics, Inc. |
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||
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|
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL |
|
Title |
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TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT |
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CPU (5/12) |
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BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, |
|
Size |
Document Number |
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Rev |
||
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NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD |
|
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LA-A971P |
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0.1 |
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PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. |
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Date: |
Wednesday, March 19, 2014 |
Sheet |
10 |
of |
48 |
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5 |
4 |
3 |
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2 |
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1 |
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5 |
4 |
3 |
2 |
1 |
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PCIE for UMA |
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D |
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UC1K |
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BDW_ULT_DDR3L |
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D |
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PCIE_PRX_WIGIGTX_N5 |
F10 |
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AN8 |
USBP0- |
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<30> PCIE_PRX_WIGIGTX_N5 |
PERN5_L0 |
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USB2N0 |
USBP0- |
<31> |
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PCB |
USB2 7 |
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<30> |
PCIE_PRX_WIGIGTX_P5 |
PCIE_PRX_WIGIGTX_P5 |
E10 |
PERP5_L0 |
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USB2P0 |
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AM8 |
USBP0+ |
USBP0+ |
<31> |
-----> Ext Port 1 Charge |
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|||||||||
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WIGIG ---> |
PCIE_PTX_WIGIGRX_N5 |
C23 |
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AR7 |
USBP1- |
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<30> PCIE_PTX_WIGIGRX_N5 |
PETN5_L0 |
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USB2N1 |
USBP1- |
<32> |
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PCIE_PTX_WIGIGRX_P5 |
C22 |
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AT7 |
USBP1+ |
-----> Ext Port 3 |
G12 UMA |
WWAN |
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<30> |
PCIE_PTX_WIGIGRX_P5 |
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PETP5_L0 |
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USB2P1 |
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USBP1+ |
<32> |
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F8 |
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AR8 |
USBP2- |
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PERN5_L1 |
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USB2N2 |
USBP2- |
<30> |
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E8 |
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AP8 |
USBP2+ |
-----> WLAN/BT |
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PERP5_L1 |
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USB2P2 |
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USBP2+ |
<30> |
G12 Entry |
NA |
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B23 |
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AR10 |
USBP3- |
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PETN5_L1 |
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USB2N3 |
USBP3- |
<31> |
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A23 |
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AT10 |
USBP3+ |
-----> Ext Port 2 |
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PETP5_L1 |
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USB2P3 |
USBP3+ |
<31> |
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H10 |
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AM15 |
USBP4- |
G14 DSC |
WWAN |
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||||||||||||
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PERN5_L2 |
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USB2N4 |
USBP4- |
<23> |
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G10 |
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AL15 |
USBP4+ |
-----> Touch |
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PERP5_L2 |
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USB2P4 |
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USBP4+ |
<23> |
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B21 |
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AM13 |
USBP5- |
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PETN5_L2 |
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USB2N5 |
USBP5- |
<23> |
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C21 |
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AN13 |
USBP5+ |
-----> Camera |
G14 UMA |
WWAN |
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|||||||||||
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PETP5_L2 |
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USB2P5 |
USBP5+ |
<23> |
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E6 |
PERN5_L3 |
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USB2N6 |
AP11 |
USBP6- |
USBP6- |
<27> |
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F6 |
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AN11 |
USBP6+ |
-----> USH |
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PERP5_L3 |
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USB2P6 |
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USBP6+ |
<27> |
G14D_En |
NA |
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B22 |
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AR13 |
USBP7- |
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PETN5_L3 |
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USB2N7 |
USBP7- |
<30> |
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A21 |
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AP13 |
USBP7+ |
-----> WWAN |
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PETP5_L3 |
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USB2P7 |
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USBP7+ |
<30> |
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<28> PCIE_PRX_GLANTX_N3 |
PCIE_PRX_GLANTX_N3 |
G11 |
PERN3 |
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G14U_En |
NA |
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G20 |
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PCIE_PRX_GLANTX_P3 |
F11 |
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||||||||||
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<28> |
PCIE_PRX_GLANTX_P3 |
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PERP3 |
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USB3RN1 |
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USB3RN1 |
<31> |
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|||
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10/100/1G LAN ---> |
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H20 |
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|||||||||||
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<28> |
PCIE_PTX_GLANRX_N3 |
PCIE_PTX_GLANRX_N3 |
C29 |
PETN3 |
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USB3RP1 |
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USB3RP1 |
<31> |
|
|
-----> Ext USB3 Port 1 Charge |
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||||||
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PCIE_PTX_GLANRX_P3 |
B30 |
PCIE |
USB |
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C33 |
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USB3TN1 |
<31> |
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|||||||
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<28> PCIE_PTX_GLANRX_P3 |
|
|
PETP3 |
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USB3TN1 |
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|||||
C |
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B34 |
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C |
||||||||||
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<30> PCIE_PRX_WLANTX_N4 |
PCIE_PRX_WLANTX_N4 |
F13 |
PERN4 |
|
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USB3TP1 |
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USB3TP1 |
<31> |
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||||
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PCIE_PRX_WLANTX_P4 |
G13 |
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E18 |
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|||||
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<30> |
PCIE_PRX_WLANTX_P4 |
PERP4 |
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USB3RN2 |
|
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USB3RN2 |
<32> |
|
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WLAN (Mini Card 2)---> |
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F18 |
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<30> PCIE_PTX_WLANRX_N4 |
PCIE_PTX_WLANRX_N4 |
B29 |
PETN4 |
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USB3RP2 |
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USB3RP2 |
<32> |
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-----> Ext USB3 Port 3 |
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PCIE_PTX_WLANRX_P4 |
A29 |
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B33 |
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USB3TN2 |
<32> |
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<30> PCIE_PTX_WLANRX_P4 |
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PETP4 |
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USB3TN2 |
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A33 |
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<29> PCIE_PRX_MMITX_N1 |
PCIE_PRX_MMITX_N1 |
G17 |
PERN1/USB3RN3 |
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USB3TP2 |
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USB3TP2 |
<32> |
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PCIE_PRX_MMITX_P1 |
F17 |
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<29> PCIE_PRX_MMITX_P1 |
PERP1/USB3RP3 |
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MMI --> |
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PCIE_PTX_MMIRX_N1 |
C30 |
PETN1/USB3TN3 |
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<29> PCIE_PTX_MMIRX_N1 |
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PCIE_PTX_MMIRX_P1 |
C31 |
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AJ10 |
USBRBIAS |
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<29> |
PCIE_PTX_MMIRX_P1 |
PETP1/USB3TP3 |
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USBRBIAS |
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AJ11 |
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USBRBIAS |
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<31> |
USB3RN4 |
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F15 |
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AN10 |
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PERN2/USB3RN4 |
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RSVD |
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G15 |
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AM10 |
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<31> |
USB3RP4 |
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PERP2/USB3RP4 |
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RSVD |
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<31> |
USB3TN4 |
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B31 |
PETN2/USB3TN4 |
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A31 |
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<31> |
USB3TP4 |
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PETP2/USB3TP4 |
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AL3 |
USB_OC0# |
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<31> -----> USB Port0 (JUSB1) |
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OC0/GPIO40 |
USB_OC0# |
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+3.3V_ALW_PCH |
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AT1 |
USB_OC1# |
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OC1/GPIO41 |
USB_OC1# |
<12,32> -----> USB Port1 (JUSB3) |
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AH2 |
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OC2/GPIO42 |
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USB_OC2# |
<12,31> -----> USB Port3 (JUSB2) |
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E15 |
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AV3 |
USB_OC3# |
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RSVD |
OC3/GPIO43 |
USB_OC3# |
<12> |
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E13 |
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RPC19 |
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+PCH_AUSB3PLL |
RC149 |
1 |
2 |
3.01K_0402_1% |
PCH_PCIE_RCOMP |
A27 |
RSVD |
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4 |
5 |
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PCIE_RCOMP |
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<12> |
PCH_GPIO44 |
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B27 |
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USB_OC0# |
3 |
6 |
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PCIE_IREF |
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2 |
7 |
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<7> PCH_SMB_ALERT# |
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1 |
8 |
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<12,37> |
KB_DET# |
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10K_8P4R_5% |
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BDW-ULT-DDR3L_BGA1168 |
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11 OF 19 |
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B |
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B |
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PCB |
PCIE1 |
PCIE2 |
PCIE3 |
PCIE4 |
PCIE5 |
PCIE6 |
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USBRBIAS |
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1 |
6.22 |
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G12 UMA |
SD card |
NA |
LOM |
WLAN |
WIGIG |
(HCA & SATA-Cache) |
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2 |
RC152 1%0402_ |
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M2 3042 |
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G12 Entry |
SD card |
NA |
LOM |
WLAN |
WIGIG |
NA |
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CAD NOTE: |
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G14 DSC |
SD card |
NA |
LOM |
WLAN |
GPU |
WIGIG |
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Route single-end 50-ohms and max 500-mils length. |
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Avoid routing next to clock pins or under stitching capacitors. |
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M2 3042 |
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Recommended minimum spacing to other signal traces is 15 |
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G14 UMA |
SD card |
NA |
LOM |
WLAN |
WIGIG |
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mils. |
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(HCA & SATA-Cache) |
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G14D_En |
SD card |
NA |
LOM |
WLAN |
GPU |
WIGIG |
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G14U_En |
SD card |
NA |
LOM |
WLAN |
WIGIG |
NA |
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A |
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A |
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DELL CONFIDENTIAL/PROPRIETARY |
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Compal Electronics, Inc. |
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PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL |
|
Title |
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TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT |
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CPU (6/12) |
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BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, |
|
Size |
Document Number |
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Rev |
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|
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD |
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LA-A971P |
|
0.1 |
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PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. |
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Date: |
Wednesday, March 19, 2014 |
Sheet 11 of |
48 |
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||||||
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5 |
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4 |
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3 |
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2 |
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1 |
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5 |
4 |
3 |
2 |
1 |
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+PCH_VCCDSW3_3 |
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2 |
1 |
LAN_WAKE# |
|
RC153 |
10K_0402_5% |
|
|
+3.3V_RUN |
|
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D |
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2 |
1 |
MPHYP_PWR_EN |
|
RC155 |
|
100K_0402_5% |
|
2 |
1 |
SIO_EXT_SCI# |
|
RC156 |
|
100K_0402_5% |
|
+3.3V_RUN |
|
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1 |
2 |
TPM_PIRQ# |
|
RC247 |
10K_0402_5% |
|
C |
+3.3V_ALW_PCH |
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RPC10 |
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4 |
5 |
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3 |
6 |
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2 |
7 |
SLATE_MODE |
|
1 |
8 |
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10K_8P4R_5% |
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RPC5 |
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4 |
5 |
SIO_EXT_SMI# |
|
3 |
6 |
PCH_GPIO9 |
|
2 |
7 |
MEDIACARD_RST# |
|
1 |
8 |
MEDIACARD_IRQ# |
|
10K_8P4R_5% |
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RPC7 |
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4 |
5 |
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3 |
6 |
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2 |
7 |
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1 |
8 |
PCH_GPIO57 |
|
10K_8P4R_5% |
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2 |
1 |
PCH_GPIO59 |
B |
RC245 |
|
100K_0402_5% |
|
2 |
1 |
3.3V_CAM_EN# |
|
RC174 |
|
100K_0402_5% |
|
2 |
1 |
NFC_IRQ |
|
RC175 |
|
100K_0402_5% |
|
2 |
1 |
MPHYP_PWR_EN |
|
@ RC171 |
|
10K_0402_5% |
A
5
|
|
|
<12,36> SIO_EXT_WAKE# |
||||||
|
<28,9> |
PM_LANPHY_ENABLE |
|||||||
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<7> |
PCH_GPIO16 |
||||
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<27> |
TPM_PIRQ# |
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||
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|
<28,36> |
LAN_WAKE# |
||||||
PCH_NFC_RST for Goliad |
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<11> |
PCH_GPIO44 |
|||
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<29> |
MEDIACARD_IRQ# |
||||
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@ T22 PAD~D |
|||
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<23> TOUCH_PANEL_INTR# |
||||||
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<38> |
MPHYP_PWR_EN |
||||
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<11,37> |
KB_DET# |
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|
||||
USB_OC2# |
<11,31> |
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@T21 |
PAD~D |
|||
|
|
<23> |
3.3V_CAM_EN# |
||||||
PCH_GPIO46 <12> |
|
|
<36> |
SIO_EXT_SMI# |
|||||
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<12> |
|
PCH_GPIO46 |
|||
PCH_GPIO73 |
<7> |
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@ T27 |
PAD~D |
||
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<30> |
|
mSATA_DEVSLP |
|||
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<20> |
|
HDD_DEVSLP |
|||
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<36> |
SIO_EXT_SCI# |
||||
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<21> |
SPKR |
|
USB_OC3# |
<11> |
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|
SIO_EXT_WAKE# <12,36> |
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USB_OC1# |
<11,32> |
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+3.3V_RUN |
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|||
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2 1 |
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5% 0402 1K |
RC176 @ |
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PCH_GPIO66 |
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|||
TOP-BLOCK SWAP OVERRIDE
HIGH ENABLE
LOW(DEFAULT) DISABLE
4
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+1.05V_VCCST |
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||||
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H_THERMTRIP# |
2 |
1 |
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1K_0402_5% |
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RC25 |
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D |
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+3.3V_RUN |
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RPC17 |
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PCH_GPIO76 |
5 |
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4 |
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<30,7> |
WLANCLK_REQ# |
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6 |
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7 |
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2 |
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BDW_ULT_DDR3L |
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<10> |
PCH_GPIO80 |
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UC1J |
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8 |
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1 |
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10K_8P4R_5% |
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CPPE# |
2 |
1 |
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PCH_GPIO76 |
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P1 |
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D60 |
H_THERMTRIP#_R |
@ 0_0402_5% 2 |
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1 RC161 |
H_THERMTRIP# |
<36> |
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100K_0402_5% |
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RC160 |
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BMBUSY/GPIO76 |
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THRMTRIP |
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SIO_EXT_WAKE# |
AU2 |
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V4 |
SIO_RCIN# |
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FFS_INT2 |
2 |
1 |
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SIO_RCIN# |
<10,36> |
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GPIO8 |
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RCIN/GPIO82 |
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AM7 |
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T4 |
IRQ_SERIRQ |
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100K_0402_5% |
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RC158 |
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LAN_PHY_PWR_CTRL/GPIO12 |
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SERIRQ |
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IRQ_SERIRQ |
<10,35,36> |
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HOST_ALERT1_R_N |
AD6 |
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CPU/ |
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AW15 |
PCH_OPI_COMP |
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PCH_GPIO67 |
2 |
1 |
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GPIO15 |
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PCH_OPI_RCOMP |
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Y1 |
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MISC |
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AF20 |
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10K_0402_5% |
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RC163 |
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GPIO16 |
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RSVD |
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TPM_PIRQ# |
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T3 |
GPIO17 |
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RSVD |
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AB21 |
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PCH_GPIO68 |
2 |
1 |
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AD5 |
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10K_0402_5% |
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RC164 |
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GPIO24 |
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LAN_WAKE# |
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AN5 |
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GPIO27 |
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AD7 |
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RPC16 |
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GPIO28 |
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NFC_IRQ |
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AN3 |
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CAM_MIC_CBL_DET# 5 |
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4 |
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GPIO26 |
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R6 |
GC6_EVENT#_Q |
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PCH_GPIO69 |
6 |
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3 |
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GSPI0_CS/GPIO83 |
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|||||
MEDIACARD_RST# |
AG6 |
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L6 |
GPU_GC6_FB_EN |
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GC6_EVENT#_Q |
7 |
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2 |
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GPIO56 |
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GSPI0_CLK/GPIO84 |
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|||||||
PCH_GPIO57 |
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AP1 |
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N6 |
PCH_GPIO85 |
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PCH_GPIO87 |
8 |
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1 |
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GPIO57 |
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GSPI0_MISO/GPIO85 |
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|||||||
SLATE_MODE |
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AL4 |
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L8 |
BBS_BIT |
@ T109 PAD~D |
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GPIO58 |
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GSPI0_MOSI/GPIO86 |
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||||||||||
PCH_GPIO59 |
|
AT5 |
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R7 |
PCH_GPIO87 |
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10K_8P4R_5% |
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||||||||||||||||||||||||||||
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GPIO59 |
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GSPI1_CS/GPIO87 |
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|||||||
PCH_GPIO44 |
|
AK4 |
GPIO |
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L5 |
3.3V_TP_EN |
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GPIO44 |
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GSPI1_CLK/GPIO88 |
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|||||||
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AB6 |
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N7 |
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3.3V_TS_EN |
<23> |
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RPC3 |
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||||||||||||||||||
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GPIO47 |
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GSPI1_MISO/GPIO89 |
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||||||||||
DIMM_DET |
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U4 |
GPIO48 |
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GSPI_MOSI/GPIO90 |
|
K2 |
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|
3.3V_HDD_EN <38> |
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|
TOUCH_PANEL_INTR# 5 |
|
4 |
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PCH_GPIO49 |
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Y3 |
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J1 |
CPPE# |
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<10> |
PCH_GPIO52 |
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6 |
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3 |
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C |
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GPIO49 |
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UART0_RXD/GPIO91 |
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TOUCH_PANEL_INTR# |
P3 |
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K3 |
CPUSB# |
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3.3V_TP_EN |
7 |
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2 |
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GPIO50 |
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UART0_TXD/GPIO92 |
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MPHYP_PWR_EN |
Y2 |
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J2 |
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GPU_GC6_FB_EN |
8 |
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1 |
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HSIOPC/GPIO71 |
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UART0_RTS/GPIO93 |
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KB_DET# |
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AT3 |
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SERIAL IO |
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G1 |
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GPIO13 |
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UART0_CTS/GPIO94 |
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PCH_GPIO14 |
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AH4 |
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K4 |
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10K_8P4R_5% |
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GPIO14 |
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UART1_RXD/GPIO0 |
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3.3V_CAM_EN# |
AM4 |
GPIO25 |
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UART1_TXD/GPIO1 |
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G2 |
FFS_INT2 |
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SIO_EXT_SMI# |
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AG5 |
GPIO45 |
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UART1_RST/GPIO2 |
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J3 |
LCD_CBL_DET# |
LCD_CBL_DET# |
<23> |
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RPC4 |
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AG3 |
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J4 |
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LCD_CBL_DET# |
5 |
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4 |
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GPIO46 |
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UART1_CTS/GPIO3 |
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F2 |
PCH_GPIO4 |
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CPUSB# |
6 |
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3 |
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I2C0_SDA/GPIO4 |
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PCH_GPIO9 |
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AM3 |
GPIO9 |
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I2C0_SCL/GPIO5 |
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F3 |
PCH_GPIO5 |
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3.3V_TS_EN |
7 |
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2 |
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PCH_GPIO10 |
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AM2 |
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G4 |
PCH_GPIO6 |
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PCH_GPIO85 |
8 |
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1 |
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GPIO10 |
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I2C1_SDA/GPIO6 |
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P2 |
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F1 |
PCH_GPIO7 |
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DEVSLP0/GPIO33 |
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I2C1_SCL/GPIO7 |
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||||||
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C4 |
SDIO_POWER_EN/GPIO70 |
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SDIO_CLK/GPIO64 |
|
E3 |
USH_DET# |
USH_DET# |
<10,27> |
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10K_8P4R_5% |
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L2 |
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F4 |
CAM_MIC_CBL_DET# |
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DEVSLP1/GPIO38 |
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SDIO_CMD/GPIO65 |
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CAM_MIC_CBL_DET# <23> |
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||||||||||
SIO_EXT_SCI# |
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N5 |
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D3 |
PCH_GPIO66 |
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RPC8 |
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||||||||||||||||||||||||||
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DEVSLP2/GPIO39 |
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SDIO_D0/GPIO66 |
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||||||
SPKR |
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V2 |
SPKR/GPIO81 |
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SDIO_D1/GPIO67 |
|
E4 |
PCH_GPIO67 |
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PCH_GPIO6 |
1 |
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8 |
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C3 |
PCH_GPIO68 |
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PCH_GPIO7 |
2 |
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7 |
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SDIO_D2/GPIO68 |
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E2 |
PCH_GPIO69 |
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PCH_GPIO5 |
3 |
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6 |
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SDIO_D3/GPIO69 |
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PCH_GPIO4 |
4 |
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5 |
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BDW-ULT-DDR3L_BGA1168 |
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10K_8P4R_5% |
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10 OF 19 |
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RPC9 |
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<10> |
HDD_FALL_INT |
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5 |
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4 |
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<30,7> |
WIGIGCLK_REQ# |
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6 |
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3 |
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7 |
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2 |
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<10> |
TOUCHPAD_INTR# |
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8 |
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1 |
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<35,6> SATA2_PCIE6_L1 |
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10K_8P4R_5% |
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||||||||
+3.3V_RUN |
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B |
2 1 |
|
5%0402 10K |
RC302@ |
|
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+3.3V_ALW_PCH |
|
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+3.3V_RUN |
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PCH_OPI_COMP 1 |
|
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2 |
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||||||||||||||
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12 |
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5%040210K |
RC303 |
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5%04021K |
RC179 |
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5%04021K |
RC180@ |
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DIMM_DET |
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49.9_0402_1% |
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HOST_ALERT1_R_N |
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SPKR |
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DIMM Detect |
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TLS CONFIDENTIALITY |
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No Reboot on TCO Timer expiration |
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HIGH |
1 DIMM |
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HIGH |
ENABLE |
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HIGH |
ENABLE |
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LOW |
2 DIMM |
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LOW(DEFAULT) |
DISABLE |
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LOW(DEFAULT) |
DISABLE |
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A |
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DELL CONFIDENTIAL/PROPRIETARY |
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Compal Electronics, Inc. |
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PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL |
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Title |
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TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT |
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CPU (7/12) |
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BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, |
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Document Number |
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Rev |
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NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD |
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LA-A971P |
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0.1 |
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PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. |
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Date: |
Wednesday, March 19, 2014 |
Sheet 12 |
of |
48 |
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3 |
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2 |
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1 |
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5 |
4 |
3 |
2 |
1 |
D
C
B
A
<9> CFG0 <9> CFG1 <9> CFG2 <9> CFG3 <9> CFG4 <9> CFG5 <9> CFG6 <9> CFG7 <9> CFG8 <9> CFG9 <9> CFG10 <9> CFG11 <9> CFG12 <9> CFG13 <9> CFG14 <9> CFG15
<9> CFG16 <9> CFG18 <9> CFG17 <9> CFG19
2
RC185
1
RC186
CFG10
2 1 |
1% 0402 1K |
RC188 @ |
SAFE MODE BOOT
CFG10
1: POWER FEATURES ACTIVATED DURING RESET
0: POWER FEATURES (ESPECIALLY CLOCK GATINE ARE NOT ACTIVATED
5
D
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CFG STRAPS for CPU |
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UC1S |
BDW_ULT_DDR3L |
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CFG0 |
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CFG0 |
AC60 |
CFG0 |
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RSVD_TP |
AV63 |
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PAD~D |
T28 @ |
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1 |
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RC183 @ 0402 1K |
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PAD~D |
T29 @ |
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1% |
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CFG1 |
AC62 |
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AU63 |
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2 |
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CFG1 |
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RSVD_TP |
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AC63 |
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CFG2 |
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AA63 |
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CFG4 |
AA60 |
CFG3 |
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C63 |
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PAD~D |
T30 @ |
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CFG4 |
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RSVD_TP |
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PAD~D |
T31 @ |
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Y62 |
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C62 |
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CFG5 |
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RSVD_TP |
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Y61 |
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B43 |
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CFG6 |
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RSVD |
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Y60 |
CFG7 |
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PAD~D |
T33 @ |
EAR-STALL/NOT STALL RESET SEQUENCE AFTER PCU PLL IS LOCKE |
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A51 |
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CFG8 |
V62 |
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CFG8 |
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RSVD_TP |
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PAD~D |
T34 @ |
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CFG9 |
V61 |
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B51 |
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CFG9 |
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RSVD_TP |
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CFG10 |
V60 |
CFG10 |
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PAD~D |
T35 @ |
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1:(Default) Normal Operation; No stall |
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L60 |
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U60 |
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CFG0 |
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CFG11 |
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RSVD_TP |
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T63 |
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0:Lane Reversed |
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CFG12 |
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N60 |
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T62 |
RESERVED |
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CFG13 |
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RSVD |
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T61 |
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CFG14 |
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T60 |
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W23 |
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C |
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CFG15 |
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RSVD |
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Y22 |
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RSVD |
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AA62 |
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AY15 |
PROC_OPI_RCOMP |
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CFG16 |
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U63 |
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CFG1 |
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CFG18 |
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AA61 |
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AV62 |
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CFG17 |
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RSVD |
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U62 |
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D58 |
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2 1 |
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CFG19 |
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RSVD |
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1%0402 1K |
RC184@ |
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P20 |
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CFG_RCOMP |
V63 |
CFG_RCOMP |
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VSS |
P22 |
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VSS |
N21 |
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A5 |
RSVD |
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RSVD |
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E1 |
RSVD |
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RSVD |
R20 |
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D1 |
RSVD |
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J20 |
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RSVD |
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H18 |
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RSVD |
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TDI_IREF |
B12 |
TD_IREF |
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PCH/PCH LESS MODE SELECTION |
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BDW-ULT-DDR3L_BGA1168 |
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19 OF 19 |
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1:(Default) Normal Operation |
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CFG1 |
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0:Lane Reversed |
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1 |
CFG_RCOMP |
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49.9_0402_1% |
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2 |
TDI_IREF |
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PROC_OPI_RCOMP 1 |
2 |
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8.2K_0402_1% |
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49.9_0402_1% |
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RC187 |
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B |
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CFG9 |
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CFG8 |
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CFG4 |
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1 |
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RC189 @ 1% 0402 1K |
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2 1 |
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RC190 @ 1% 0402 1K |
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2 1 |
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RC191 5% 0402 1K |
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2 |
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NO SVID PROTOCOL CAPABLE VR CONNECTED |
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ALLOW THE USE OF NOA ON LOCKED UNITS |
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Display Port Presence Strap |
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1: VRS support SVID protocol are present |
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1: Enable(Default): Noa will be disable in |
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1 : Disabled; No Physical Display Port |
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0:No VR support SVID is present |
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locked units and enable in un-locked |
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CFG9 |
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CFG8 |
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CFG4 |
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attached to Embedded Display Port |
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The chip will not generate(OR Respond to) |
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0:unitsEnable Noa will be available pegardless of |
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0 : Enabled; An external Display Port device is |
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SVID activity |
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the locking of the unit |
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connected to the Embedded Display Port |
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A |
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DELL CONFIDENTIAL/PROPRIETARY |
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Compal Electronics, Inc. |
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PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL |
|
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Title |
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TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT |
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CPU (8/12) |
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BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, |
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Size |
Document Number |
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Rev |
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NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD |
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LA-A971P |
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0.1 |
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PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. |
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Date: |
Wednesday, March 19, 2014 |
Sheet 13 |
of |
48 |
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4 |
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3 |
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2 |
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1 |
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D
C
B
A
5 |
4 |
3 |
2 |
1 |
D
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2 |
1 |
1 |
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0_0402_5% |
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@ RC192 |
|
UC1Q |
BDW_ULT_DDR3L |
||||
DC_TEST_AY2_AW2 |
AY2 |
DAISY_CHAIN_NCTF_AY2 |
DAISY_CHAIN_NCTF_A3 |
A3 |
DC_TEST_A3_B3 |
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DC_TEST_AY3_AW3 |
AY3 |
A4 |
DC_TEST_A4 |
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DAISY_CHAIN_NCTF_AY3 |
DAISY_CHAIN_NCTF_A4 |
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DC_TEST_AY60 |
AY60 |
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DC_TEST_AY61_AW61 |
AY61 |
DAISY_CHAIN_NCTF_AY60 |
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A60 |
DC_TEST_A60 |
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DAISY_CHAIN_NCTF_AY61 |
DAISY_CHAIN_NCTF_A60 |
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||||
DC_TEST_AY62_AW62 AY62 |
A61 |
DC_TEST_A61_B61 |
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2 |
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DAISY_CHAIN_NCTF_AY62 |
DAISY_CHAIN_NCTF_A61 |
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|||||
TP_DC_TEST_B2 |
B2 |
A62 |
DC_TEST_A62 |
2 |
1 |
|||
DC_TEST_A3_B3 |
B3 |
DAISY_CHAIN_NCTF_B2 |
DAISY_CHAIN_NCTF_A62 |
AV1 |
DC_TEST_AV1 |
0_0402_5% |
|
@ RC193 |
DAISY_CHAIN_NCTF_B3 |
DAISY_CHAIN_NCTF_AV1 |
|
||||||
DC_TEST_A61_B61 |
B61 |
AW1 |
DC_TEST_AW1 |
2 |
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1 |
||
DAISY_CHAIN_NCTF_B61 |
DAISY_CHAIN_NCTF_AW1 |
|
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|
B62 |
AW2 |
DC_TEST_AY2_AW2 |
0_0402_5% |
|
@ RC194 |
||
DC_TEST_B62_B63 |
B63 |
DAISY_CHAIN_NCTF_B62 |
DAISY_CHAIN_NCTF_AW2 |
AW3 |
DC_TEST_AY3_AW3 |
|
4 |
|
DAISY_CHAIN_NCTF_B63 |
DAISY_CHAIN_NCTF_AW3 |
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|||||
|
C1 |
AW61 |
DC_TEST_AY61_AW61 |
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DAISY_CHAIN_NCTF_C1 |
DAISY_CHAIN_NCTF_AW61 |
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DC_TEST_C1_C2 |
C2 |
AW62 |
DC_TEST_AY62_AW62 |
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DAISY_CHAIN_NCTF_C2 |
DAISY_CHAIN_NCTF_AW62 |
AW63 |
DC_TEST_AW63 |
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DAISY_CHAIN_NCTF_AW63 |
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BDW-ULT-DDR3L_BGA1168 |
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C |
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17 OF 19 |
3 |
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2 |
1 |
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0_0402_5% |
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@ RC195 |
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Package Daisy Chain: |
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1.B2-PKG-C1-PCB-C2-PKG-B3-PCB-A3-PKG-A4 |
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2.A62-PKG-A61-PCB-B61-PKG-B62-PCB-B63-PKG-A60 |
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3.AY60-PKG-AW61-PCB-AY61-PKG-AW62-PCB-AY62-PKG-AW63 |
||||||||||
4.AW1-PKG-AW3-PCB-AY3-PKG-AW2-PCB-AY2-PKG-AV1 |
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UC1R |
BDW_ULT_DDR3L |
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RSVD |
N23 |
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R23 |
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RSVD |
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AT2 |
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T23 |
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RSVD |
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RSVD |
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U10 |
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AU44 |
RSVD |
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RSVD |
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AV44 |
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B |
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RSVD |
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D15 |
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RSVD |
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AL1 |
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RSVD |
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AM11 |
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RSVD |
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F22 |
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AP7 |
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RSVD |
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RSVD |
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AU10 |
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H22 |
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RSVD |
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RSVD |
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AU15 |
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J21 |
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RSVD |
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RSVD |
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RSVD |
AW14 |
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AY14 |
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RSVD |
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BDW-ULT-DDR3L_BGA1168 |
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18 OF 19 |
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A
DELL CONFIDENTIAL/PROPRIETARY
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Compal Electronics, Inc. |
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||
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|
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL |
|
Title |
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|||
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TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT |
|
|
CPU (9/12) |
|
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|
||
|
|
|
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, |
|
Size |
Document Number |
|
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|
|
Rev |
||
|
|
|
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD |
|
|
LA-A971P |
|
|
|
0.1 |
|||
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PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. |
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Date: |
Wednesday, March 19, 2014 |
Sheet |
14 |
of |
48 |
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5 |
4 |
3 |
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2 |
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1 |
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D
C
B
A
5 |
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4 |
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3 |
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2 |
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1 |
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ESD Request |
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+1.05V_RUN |
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+VCCIO_OUT |
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+VCC_CORE |
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+1.35V_MEM |
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1 |
2 |
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+1.05V_RUN |
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2 |
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1 |
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@EMC@ CC23 |
22U_0603_6.3V6M |
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||||
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@ RC196 |
|
0_0603_5% |
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+1.35V_MEM |
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VDDQ DECOUPLING |
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+1.05V_RUN |
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+VCC_CORE |
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21 |
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CPU_PWR_DEBUG# |
RESISTOR STUFFING OPTIONS ARE |
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+1.05V_RUN |
1 |
2 |
+3.3V_RUN |
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12 |
CC25 3V6M.604022U.2 |
12 |
3V6M.604022U.2 |
CC26 |
12 |
CC27 3V6M.604022U.2 |
12 |
CC28 3V6M.604022U.2 |
12 |
3V6M.6060310U |
CC29 |
12 |
CC30 3V6M.6060310U |
12 |
CC31 3V6M.6060310U |
12 |
3V6M.6060310U |
CC32 |
12 |
3V6M.6060310U |
CC33 |
12 |
CC34 3V6M.6060310U |
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PROVIDED FOR TESTING PURPOSES |
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RC197 |
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@EMC@ CC79 |
22U_0603_6.3V6M |
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@ |
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@ |
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@ |
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@ |
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D |
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150_0402_5% |
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1 |
2 |
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@EMC@ CC84 |
22U_0603_6.3V6M |
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1 |
10K |
@ |
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1 |
2 |
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@EMC@ CC85 |
22U_0603_6.3V6M |
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2 |
5%0402 |
RC198 |
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H_VCCST_PWRGD |
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+1.05V_VCCST |
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1 |
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1 |
040210K |
RC199@ |
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@EMC@ |
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+VCC_CORE |
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2 |
CC24 |
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UC1L |
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BDW_ULT_DDR3L |
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VCC |
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100P_0402_50V8J |
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RSVD |
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+1.35V_MEM |
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L59 |
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C36 |
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2 |
5% |
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J58 |
RSVD |
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VCC |
C40 |
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C44 |
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H_VR_EN |
2 |
1 |
H_VR_READY |
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AH26 |
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VCC |
C48 |
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VDDQ |
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VCC |
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1.5K_0402_5% |
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RC201 |
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AJ31 |
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C52 |
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VDDQ |
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VCC |
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AJ33 |
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C56 |
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AJ37 |
VDDQ |
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VCC |
E23 |
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+1.05V_VCCST |
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VDDQ |
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VCC |
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AN33 |
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E25 |
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AP43 |
VDDQ |
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VCC |
E27 |
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AR48 |
VDDQ |
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VCC |
E29 |
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+3.3V_ALW |
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2 |
04021K |
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VDDQ |
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VCC |
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AY35 |
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E31 |
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1 |
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5 |
1 |
2 |
RC202 |
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AY50 |
VDDQ |
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VCC |
E37 |
C |
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VDDQ |
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VCC |
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AY40 |
VDDQ |
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VCC |
E33 |
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UC8 |
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AY44 |
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E35 |
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NC |
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VCC |
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@ CC35 |
0.1U_0402_25V6 |
1 |
5% |
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VDDQ |
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VCC |
E39 |
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VCC |
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2 |
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+VCC_CORE |
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F59 |
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E41 |
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<36,9> |
RESET_OUT# |
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A |
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4 |
H_VCCST_PWRGD |
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N58 |
VCC |
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VCC |
E43 |
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Y |
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RSVD |
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VCC |
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3 |
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AC58 |
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E45 |
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GND |
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RSVD |
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VCC |
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E47 |
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74AUP1G07GW_TSSOP5 |
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VCCSENSE |
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E63 |
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VCC |
E49 |
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VCC_SENSE |
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VCC |
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AB23 |
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E51 |
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RSVD |
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VCC |
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+VCCIO_OUT |
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A59 |
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E53 |
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E20 |
VCCIO_OUT |
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VCC |
E55 |
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+VCCIOA_OUT |
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VCCIOA_OUT |
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VCC |
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AD23 |
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E57 |
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RSVD |
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VCC |
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AA23 |
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F24 |
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AE59 |
RSVD |
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VCC |
F28 |
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RSVD |
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VCC |
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F32 |
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+1.05V_VCCST |
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VCC |
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SVID ALERT |
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H_CPU_SVIDALRT# |
L62 |
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F36 |
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<45> |
VIDSCLK |
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VIDSCLK |
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VCC |
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VIDSCLK |
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N63 |
VIDALERT |
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HSW ULT POWER |
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VCC |
F40 |
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VIDSOUT |
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L63 |
VIDSOUT |
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VCC |
F44 |
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H_VCCST_PWRGD |
B59 |
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F48 |
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1 |
75 |
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<9> |
H_VCCST_PWRGD |
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H_VR_EN |
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F60 |
VCCST_PWRGD |
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VCC |
F52 |
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0402_ |
RC204 |
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RC204 close to CPU 300 - |
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<45> H_VR_EN |
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H_VR_READY |
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D63 |
VR_EN |
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VCC |
G25 |
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VCC |
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CAD Note: Place the PU resistors close to CPU |
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<45> |
H_VR_READY |
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VR_READY |
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VCC |
G23 |
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2 |
1% |
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1500mils |
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H59 |
VSS |
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VCC |
G27 |
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<9> |
CPU_PWR_DEBUG# |
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PWR_DEBUG |
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VCC |
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P62 |
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G29 |
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2 |
|
1 |
H_CPU_SVIDALRT# |
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@ T74 |
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P60 |
VSS |
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VCC |
G31 |
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<45> VIDALERT_N |
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PAD~D |
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RSVD_TP |
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VCC |
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|||||||||
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43_0402_5% |
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RC207 |
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@ T75 |
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P61 |
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G33 |
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PAD~D |
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RSVD_TP |
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VCC |
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||||||||
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@ T76 |
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N59 |
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G35 |
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PAD~D |
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RSVD_TP |
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VCC |
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@ T77 |
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N61 |
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G37 |
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PAD~D |
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RSVD_TP |
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VCC |
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T59 |
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G39 |
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+1.05V_VCCST |
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RSVD |
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VCC |
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SVID DATA |
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AD60 |
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G41 |
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AA59 |
RSVD |
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VCC |
G45 |
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AD59 |
RSVD |
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VCC |
G43 |
B |
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110 |
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1 |
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|
CAD Note: Place the PU resistors close to CPU |
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AE60 |
RSVD |
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VCC |
G47 |
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||||||
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1%0402 |
RC208 |
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AC59 |
RSVD |
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VCC |
G49 |
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||||||
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RSVD |
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VCC |
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|||||
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|
RC208close to CPU 300 - 1500mils |
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AG58 |
RSVD |
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VCC |
G51 |
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U59 |
RSVD |
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VCC |
G53 |
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2 |
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V59 |
RSVD |
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VCC |
G55 |
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G57 |
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VCC |
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VIDSOUT |
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+1.05V_VCCST |
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AC22 |
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H23 |
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||||
<45> VIDSOUT |
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VCCST |
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VCC |
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||||||||
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AE22 |
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J23 |
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AE23 |
VCCST |
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VCC |
K23 |
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VCCST |
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VCC |
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K57 |
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VCC |
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+VCC_CORE |
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AB57 |
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L22 |
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AD57 |
VCC |
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VCC |
M23 |
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VCC |
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VCC |
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AG57 |
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M57 |
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VCC |
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VCC |
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VCC_SENSE |
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C24 |
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P57 |
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+VCC_CORE |
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C32 |
VCC |
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VCC |
W57 |
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|||||
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C28 |
VCC |
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VCC |
U57 |
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|||
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0402100 |
RC209 |
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VCC |
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VCC |
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1 |
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+1.05V_RUN |
|
+1.05V_VCCST |
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|
BDW-ULT-DDR3L_BGA1168 |
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||||||||
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12 OF 19 |
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_ |
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@ PJP23 |
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2 |
1% |
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CC36 3V6M.6060322U |
21 |
CC37 3V6K.604021U |
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21 |
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<45> VCCSENSE |
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VCCSENSE |
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PAD-OPEN1x1m |
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@ |
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CAD Note: RC209 SHOULD BE PLACED CLOSE TO CPU |
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A |
DELL CONFIDENTIAL/PROPRIETARY
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Compal Electronics, Inc. |
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PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL |
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Title |
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TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT |
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CPU (10/12) |
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BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, |
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Size |
Document Number |
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Rev |
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NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD |
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LA-A971P |
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0.1 |
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PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. |
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Date: |
Wednesday, March 19, 2014 |
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Sheet |
15 |
of |
48 |
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5 |
4 |
3 |
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2 |
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1 |
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D
C
B
A
5
PAD-OPEN1x1m |
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+1.05V_MODPHY PJP51 @ |
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+1.05V_MODPHY_PCH |
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1 |
2 |
2 1 |
3V6K.60402 1U |
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2 1 |
3V6K.604021UCC44 21 |
CC40 3V6K.60402 1U |
CC43 place near M9 |
CC43 |
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CC40 place near K9; |
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@ |
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CC44 place near L10 |
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VCCHSIO |
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S0 Iccmax = 1.838A |
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+1.05V_MODPHY |
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+PCH_AUSB3PLL |
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LC1 |
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1 |
2 |
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2.2UH_LQM2MPN2R2NG0L_30% |
2 1 |
.6060322U |
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2 1 |
CC47 .6060322U |
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CC47 place near B18 |
CC51 |
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VCCUSB3PLL |
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3V6M |
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3V6M |
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S0 Iccmax = 41mA |
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+1.05V_MODPHY |
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+PCH_ASATA3PLL |
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LC2 |
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1 |
2 |
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2.2UH_LQM2MPN2R2NG0L_30% |
12 |
3V6M.6060322U |
CC55 |
12 |
CC56 3V6M.6060322U |
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CC56 place near B11 |
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VCCSATA3PLL |
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S0 Iccmax = 42mA |
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+1.05V_RUN |
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+V1.05S_APLLOPI |
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LC3 |
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1 |
2 |
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2.2UH_LQM2MPN2R2NG0L_30% |
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CC67 3V6M.61206 100U |
2 1 |
3V6K.6 0402 1U |
CC68 |
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2 1 |
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CC68 place near AA21 |
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VCCAPLL |
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S0 Iccmax = 57mA |
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+PCH_VCCDSW 3_3 |
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+PCH_VCCDSW |
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1 |
2 |
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@ CC97 0.47U_0402_10V6K |
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CC97 place near AH10 |
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intel DG Rev 1.2 , page 500 |
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47.3 |
Boot Strap Capacitor |
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+3.3V_ALW _PCH |
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+PCH_VCCDSW 3_3 |
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1 |
2 |
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@ RC216 |
0_0402_5% |
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+3.3V_ALW |
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@ RC2171 |
2 0_0402_5% |
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CC80 place near AH10 |
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2 1 |
3V6K.6 0402 1U |
CC80 |
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S0 Iccmax = 114mA |
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VCCDSW3_3 |
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@ |
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5
4 |
3 |
2 |
1 |
+3.3V_ALW _PCH
1 |
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CC57 10V7K 0402 1U.0 |
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2 |
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+1.05V_RUN |
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+1.05V_MODPHY_PCH |
K9 |
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L10 |
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M9 |
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2 1 |
CC53 3V6K.60402 1U |
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N8 |
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AA21 |
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P9 |
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@ |
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+PCH_AUSB3PLL |
B18 |
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+PCH_ASATA3PLL |
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Y20 |
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+V1.05S_APLLOPI |
W21 |
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J13 |
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CC57 place near AH14 |
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AH14 |
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+3.3V_ALW _PCH |
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AH13 |
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CC63 place near AC9 |
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AC9 |
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+3.3V_RUN |
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AA9 |
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3V6M.6060322U CC63 21 |
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+PCH_VCCDSW 3_3 |
V8 |
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2 1 |
.6060322U CC64 +1.05V_RUN |
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+PCH_VCC1P05 |
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J18 |
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CC64 place near V8 |
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W9 |
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2013/06/10 refer 6L_WP chnage to +3.3V_M, 6/14 change back |
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3V6M |
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K19 |
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+PCH_VCCACLKPLL |
A20 |
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J17 |
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2 1 |
3V6K.604021UCC70 21 |
CC71 3V6K.60402 1U |
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AE21 |
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CC70 close to Pin J17 |
R21 |
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CC71 close to Pin R21 |
T21 |
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K18 |
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M20 |
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V21 |
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+3.3V_ALW _PCH |
AE20 |
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+1.05V_RUN |
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+PCH_VCC1P05 |
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LC4 |
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1 |
2 |
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2.2UH_LQM2MPN2R2NG0L_30% |
3V6M.61206100U |
CC77 21 |
CC78 3V6K.60402 1U |
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2 1 |
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CC78 place near J18 |
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VCCCLK |
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S0 Iccmax = 200mA |
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+PCH_VCCACLKPLL |
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+1.05V_RUN |
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LC5 |
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1 |
2 |
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2.2UH_LQM2MPN2R2NG0L_30% |
2 1 |
3V6M.61206100U CC81 21 |
CC82 3V6K.6 0402 1U |
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S0 Iccmax = 31mA |
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CC82 place near A20 |
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VCCACLKPLL |
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4
+1.05V_M |
+1.05V_RUN |
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12 |
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CC39 R6M5VY.2D3330U |
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R6M5VY.2D3330U |
CC42@EMC@ |
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1 |
R6M5VY.2D3330U |
CC41@EMC@ |
1 |
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+ |
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+ |
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+ |
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2 |
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2 |
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D
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+RTC_CELL |
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CC48,CC49, CC50 place near AG10 |
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UC1M |
BDW_ULT_DDR3L |
RTC |
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AH11 |
+PCH_RTC_VCCSUS3_3 |
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2 1 |
10V7K0402 1U.0 |
CC48 |
2 1 |
10V7K0402 1U.0 |
CC49 |
2 1 |
3V6K.6 0402 1U |
CC50 |
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VCCHSIO |
HSIO |
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@ |
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VCCHSIO |
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VCCHSIO |
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VCC1_05 |
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VCCSUS3_3 |
AG10 |
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VCC1_05 |
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VCCRTC |
AE7 |
+DCPRRTC 1 |
2 |
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VCCUSB3PLL |
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DCPRTC |
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CC52 |
0.1U_0402_10V7K |
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VCCSATA3PLL |
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+3.3V_M |
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RSVD |
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SPI |
VCCSPI |
Y8 |
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CC54 place near Y8 |
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.0 |
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OPI |
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VCCAPLL |
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10V7K0402 1U |
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VCCAPLL |
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VCC1_05 |
AG14 |
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J11; CC58 place near AE8 |
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2 1 |
@ |
+PCH_VCCDSW |
2 |
1 |
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DCPSUS3 |
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J11 |
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CC54 |
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VCCASW |
AG13 |
+1.05V_M |
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VCCASW |
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CC59 and CC60 place near |
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+1.05V_RUN |
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USB3 |
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VCC1_05 |
H11 |
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+1.05V_M |
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3V6M.6 0603 10U |
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RC211 |
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5.11_0402_1% |
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HDA |
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H15 |
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2 1 |
3V6K.6 0402 1U |
3V6K.6 0402 1U |
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.0 |
CC59 |
2 1 |
CC60 |
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12 |
R VCCDSW +PCH |
CC65 3V6K.604021U |
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VCC3_3 |
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CC61 |
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CC62 @ 3V6M.6 0603 22U |
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VCCHDA |
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VCC1_05 |
AE8 |
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1 2 |
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1 2 |
. 6 0402 1U |
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VCC1_05 |
AF22 |
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1 |
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CC58 |
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VRM |
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DCPSUSBYP |
AG19 |
+PCH_VCCDSW |
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VCC1_05 |
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DCPSUS2 |
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CORE |
DCPSUSBYP |
AG20 |
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VCCASW |
AE9 |
CC61 CC62 place near AE9 |
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3V6K |
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AG8 |
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VCCASW |
AF9 |
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VCCSUS3_3 |
GPIO/LPC |
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VCCASW |
AD10 |
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2 |
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CC65 place near AG19 |
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VCCSUS3_3 |
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DCPSUS1 |
AD8 |
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C |
VCCDSW3_3 |
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DCPSUS1 |
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VCC3_3 |
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+3.3V_RUN |
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VCC3_3 |
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VCCTS1_5 |
J15 |
+1.5V_RUN |
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THERMAL SENSOR |
K14 |
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10V7K 0402 1U |
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VCC3_3 |
K16 |
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2 1 |
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RSVD |
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2013/06/10 refer 6L_WP chnage to float,6/14 change back |
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CC66 |
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+1.05V_RUN |
12 |
3V6K.604021U |
CC69 |
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+3.3V_RUN |
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VCCCLK |
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SERIAL IO |
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U8 |
CC69 place near U8 |
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VCCCLK |
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VCCSDIO |
T9 |
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VCCACLKPLL |
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VCCSDIO |
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VCCCLK |
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+PCH_RTC_VCCSUS3_3 |
+3.3V_ALW _PCH |
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VCCCLK |
LPT LP POWER |
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VCCCLK |
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SUS OSCILLATOR |
DCPSUS4 |
AB8 |
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2 |
1 |
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RSVD |
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0_0402_5% |
RC212 @ |
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RSVD |
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RSVD |
AC20 |
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+3.3V_ALW |
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VCCSUS3_3 |
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AG16 CC72 place near AG16 |
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VCCSUS3_3 |
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USB2 |
VCC1_05 |
AG17 |
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CC72 3V6K.6 0402 1U |
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2 |
1 |
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VCC1_05 |
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3V6K.604021UCC73 21 |
0_0402_5% |
RC213 @ |
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2 1 |
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VCCSUS3_3 |
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BDW-ULT-DDR3L_BGA1168 |
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CC73 place near AH11 |
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13 OF 19 |
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S0 Iccmax = 63mA |
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B |
Reminder below power rail need isolation for layout refer attach file for more detail that from Intel review feedback.
A
DELL CONFIDENTIAL/PROPRIETARY
|
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Compal Electronics, Inc. |
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PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL |
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Title |
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TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT |
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CPU (11/12) |
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BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, |
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Size |
Document Number |
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Rev |
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NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD |
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|
|
LA-A971P |
|
|
0.1 |
||
|
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. |
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Date: |
Wednesday, March 19, 2014 |
Sheet 16 |
of |
48 |
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3 |
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2 |
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1 |
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