Apple macbook unibody a1342 Schematics

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_HEAD

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_HEAD

3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT

ECNREV

BRANCH

DRAWING NUMBER

REVISION

SIZE

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

DRAWING TITLE

THE POSESSOR AGREES TO THE FOLLOWING:

Apple Inc.

SHEET

DATE

THE INFORMATION CONTAINED HEREIN IS THE

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

3456

8 7 6 5 4 2 1

APPD

DESCRIPTION OF REVISION

04/26/2010

Schematic / PCB #’s

SCRATCHO

SCHEM MLB_LDO K87

1 OF 76

0000897412

051-8561

C.0.0

1 OF 109

PRODUCTION RELEASED

2010-04-26

MASTER

K87 SMBus Connections

(T27_MLB)

(12/15/2009)

LPC+SPI Debug Connector

(T27_MLB)

(10/27/2009)

SMC Support

T27_MLB

02/16/2010

SMC

(K84_MLB)

(10/03/2009)

External USB Connectors

MASTER

SATA Connectors

MASTER

ETHERNET CONNECTOR

MASTER

Ethernet PHY (RTL8211CL)

MASTER

X16 WIRELESS CONNECTOR

T27_MLB

02/16/2010

FSB/DDR3 Vref Margining

MASTER

SO-DIMM Pinswaps

T27_MLB

02/16/2010

DDR3 SO-DIMM Connector B

T27_MLB

02/16/2010

DDR3 SO-DIMM Connector A

(T27_MLB)

(10/07/2009)

SB Misc

T27_MLB

02/16/2010

MCP Graphics Support

(T27_MLB)

(11/16/2009)

MCP Standard Decoupling

T27_MLB

12/15/2009

MCP89 GFX Core Rail Gating

K6_MLB

02/16/2010

MCP89 Memory Rail Gating

T27_MLB

02/16/2010

MCP Power & Ground

T27_MLB

02/16/2010

MCP HDA, LPC & MISC

T27_MLB

02/16/2010

MCP SATA, USB & Ethernet

T27_MLB

02/16/2010

MCP Graphics

T27_MLB

02/16/2010

MCP PCIe Interfaces

T27_MLB

02/16/2010

MCP Memory Interface

T27_MLB

02/16/2010

MCP CPU Interface

(K84_MLB)

(02/25/2009)

eXtended Debug Port(MiniXDP)

T27_MLB

02/16/2010

CPU Decoupling

T27_MLB

02/16/2010

CPU Power & Ground

T27_MLB

02/16/2010

CPU FSB

(K84_MLB)

(02/04/2009)

SIGNAL ALIAS

MASTER

Power Aliases

MASTER

FUNC TEST

MASTER

Revision History

MASTER

Revision History

(K84_MLB)

(01/19/2009)

BOM Configuration

MASTER

Power Block Diagram

MASTER

System Block Diagram

109

K87 RULE DEFINITIONS

MASTER

108

K87 SPECIFIC CONSTRAINTS

MASTER

106

SMC Constraints

02/16/2010

T27_MLB

104

Ethernet Constraints

MASTER

103

MCP Constraints 2

02/16/2010

T27_MLB

102

MCP Constraints 1

02/16/2010

T27_MLB

101

Memory Constraints

02/16/2010

T27_MLB

100

CPU/FSB Constraints

02/16/2010

T27_MLB

LCD Backlight Support

(10/19/2009)

(K84_MLB)

LCD Backlight Driver (MC34845)

MASTER

DisplayPort Connector

MASTER

DISPLAYPORT SUPPORT

02/16/2010

K6_MLB

LVDS CONNECTOR

(10/19/2009)

(K84_MLB)

POWER FETS

MASTER

Power Sequencing

(10/27/2009)

(T27_MLB)

Misc Power Supplies

MASTER

CPU VTT(1.05V) SUPPLY

(02/04/2009)

(K84_MLB)

MCP VCore Regulator

(10/27/2009)

(K6_MLB)

IMVP6 CPU VCore Regulator

(11/18/2009)

(K84_MLB)

1.5V/0.75V DDR3 SUPPLY

(11/06/2009)

(K6_MLB)

5V/3.3V SUPPLY

(10/27/2009)

(K6_MLB)

PBus Supply & Battery Charger

(11/06/2009)

(K6_MLB)

DC-In & Battery Connectors

MASTER

AUDIO: JACK TRANSLATORS

02/16/2010

AUDIO

AUDIO: JACK

02/16/2010

AUDIO

AUDI0: SPEAKER AMP

02/16/2010

AUDIO

AUDIO: HEADPHONE FILTER

02/16/2010

AUDIO

AUDIO: LINE INPUT FILTER

02/16/2010

AUDIO

AUDIO: CODEC/REGULATOR

02/16/2010

AUDIO

SPI ROM

02/16/2010

T27_MLB

DEBUG SENSORS AND ADC

MASTER

SMS

MASTER

WELLSPRING 2

MASTER

WELLSPRING 1

02/16/2010

T27_MLB

Fan Connector

02/16/2010

T27_MLB

Thermal Sensors

MASTER

Current Sensing

02/02/2010

T27_MLB

Sync

(.csa)

Date

Contents

Page

1 NA

Table of Contents

Voltage Sensing

02/16/2010

T27_MLB

PCBF,MLB_LDO,K87820-2877

PCB

CRITICAL

Date

Page

Contents

(.csa)

Sync

SCHEM,MLB_LDO,K87

051-8561 CRITICAL

SCH

SCHEM,MLB_LDO,SCRATCHO,K87

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

BRANCH

REVISION

DRAWING NUMBER

SIZE

SHEET

PAGE TITLE

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

345678

8 7 5 4 2 1

PG 18

HALL EFFECT CONN

INTEL CPU

K86K87

2.4GHZ 1.2GHZ CULV

PENRYN

AMPS

GPIOs

PG 90

DISPLAY PORT

PG 94

SMB

PG 19

AUDIO CODEC

PG 62

PG 63

LINE IN

FILTER FILTER

HEADPHONE

PG 65

CONNS

PG 67

J6701,J6702,J6703,J6704

AUDIO

U6201

SPEAKER

U6610, U6620, U6630

PG 66

CONN

PG 32

E-NET

U3700

J3900

PG 37

10/100/1000 E-NET

GIGABIT

PG 34

CONN

PCI

J5100

PG 51

PG 70-79

LPC+SPI CONN

POWER SUPPLY

U5535,U5515

SMS

PG 69

PG 59

PG 69,70

PG 55

PG 53,54

PG 56

DC/BATT

TEMP SENSORS

VOLTAGE AND CURRNET SENSING

POWER SENSE

FAN CONN

J6950

U5920

J6950,U7000

J5601

J3100

J2900

DIMM

PG 29,30

MINI XDP CONN

DDR3-1067/1333MHZ

J1300

PG 13

2 UDIMMs

PG 15

MEMORY

MAIN

FSB

1067/1333 MHz

Prt

Ser

Fan

ADC

J4600, J4610

PG 46

CAMERA

B,0BSB

SMC

PG 49

SMSLID

U4900

CONN

PG 58

SPI

PG 61

J5800

J9000U5701

PG 90PG 57

TRACKPAD/

KEYBOARD

BLUETOOTH

PG 34

U6100

MISC

PG 19

CTRL

PWR

PG 19

PG 18

LPC

J3401

10 98764 51 20

J1300

MINI XDP CONN

PG 13

HDA

PG 19

FSB INTERFACE

NVIDIA

U1400

U1000

PG 10

PG 14

PG 19

MCP

PG 18

SATA

DP OUT

HDMI OUT

20 LANES3

UP TO

PCI-E

PG 45

CONN

J4500

LVDS

J9000

SATA

ODD

AIR PORT

CONN

J3401

J9400

PG 17

MAC

RGMII

PG 16

LAN

PG 17

64-Bit

USB

CONN

TRACKPAD

BOOT ROM

SPI

PG 17

(UP TO 12 DEVICES)

CONN

EXTERNAL USB

DVI OUT

RGB OUT

TMDS OUT

1.05V/3GHZ.

PG 45

SATA

CONN

J4501

1.05V/3GHZ.

LVDS OUT

RTL8251CA

SYNC_DATE=MASTER

SYNC_MASTER=MASTER

System Block Diagram

2 OF 109

C.0.0

051-8561

2 OF 76

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

BRANCH

REVISION

DRAWING NUMBER

SIZE

SHEET

PAGE TITLE

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

345678

8 7 5 4 2 1

PP5V_S0_FET

Q7948

P3V3S0_EN

U7840

P5V3V3_PGOOD

PP0V9_ENET_FET

ISL8009B

VOUT

VIN

1.05V

TPS51125

PPBUS_G3H

SLP_S4_L(P94)

SLP_S4_L

SMC_BATT_ISENSE

U7100

PGOOD

(8A MAX CURRENT)

U2850

PP4V5_AUDIO_ANALOG

ALL_SYS_PWRGD

RSMRST_PWRGD

SMC_ONOFF_L

U7750

P5VS3_EN_L

PM_SLP_RMGT_L

PPVBAT_G3H_CONN

09-3

DELAY

MCP89

SMC_CPU_VSENSE

CPUVTTS0_PGOOD

TPS51117

SMC_CPU_ISENSE

Q5315

PBUS_G3H_VSENSE

CPUVTT

RN5VD30A-F

U5010

LT3470

CPU VCORE

SMC

ISL9563A

U7500

U7300

TPS51116

U9700

MC34845

0.75V

1.5V

ISL88042

U7870

PPMCPCORE_S0_REG

VOUT2

VIN

99ms DLY

SMC_RESET_L

PLT_RST*

RSMRST_OUT(P15)

PWRGOOD

Q7910

U6200

(25A MAX CURRENT)

1.5V

PP1V8_S0_REG

P0V9_ENET_EN

P0V9S5_EN

15-2

P3V3S0_EN

PM_SLP_S3_L

BKLT_EN

ENA

Q7890,Q7891

VIN

VOUT1

U6990

CHGR_EN

PBUS SUPPLY/

CPUVTTS0_EN (S0)

6A FUSE

R7020

ENABLES

BATTERY CHARGER

IMVP_VR_ON_R

VOUT

PP1V05_S0

PGOOD

F7040

PPDCIN_G3H_OR_PBUS

(1.05V)

EN_PSV

U7600

VIN

VOUT

VIN

PM_SLP_RMGT_L

09-2

J6950

PM_SLP_S4_L

R7050

TPS62202

U7760

Q7920

AP_PWR_EN

(9 TO 12.6V)

U1400

PBUSVSENS_EN

1.8V

PP1V5_S0_FET

1.05V

TPS74701

S0PGOOD_RST_L

PP1V05_S0_MCP_PLL_OR

P3V3S3_EN

VOUT

PPVOUT_SW_LCDBKLT

(RT)

PGOOD1,2

VOUT

CURRENT)

PP1V05_S0_REG

NCP1529

Q7930

3.3V

VREG3

P5VS3_EN_L

P3V3S5_EN_L

Q7960

U7710

VOUT1

FDC638P

PP3V3_S0_FET

P60

U7740

PP1V05_S0

PP1V5_S0

PP3V3_S0

V2 V3

RST*

MCPPLLDO_PGOOD

MCPCORES0_PGOOD

CPUVTTS0_PGOOD

MCPCORES0_EN

SMC_ADAPTER_EN

MCP_CORE

VOUT

PPMCPCORE_S0_R

R7525

Q7890

PM_WLAN_EN_L

Q7930

PP3V3S0_EN

(S5)

EN2

EN1

VIN

U7201

MCP_PS_PWRGD

U1000

CPU

PWRGD

U1400

MCP89

CPU_RESET#

PWRBTN*

PLTRST*

RESET*

CPUPWRGD(GPIO49)

RSMRST*

FSB_CPURST_L

LPC_RESET_L

CPU_PWRGD

08-1

PM_RSMRST_L

PWR_BUTTON(P90)

RSMRST_IN(P13)

=DDRREG_EN

=DDTVTT_EN

04-1

VIN

VR_ON

PPVBAT_G3H_CHGR_R

Q7055

U7000

ISL6259

SMC

3.425V G3HOT

DELAY

09-1

PWRGD(P12)

IMVP_VR_ON(P16)

18-2

15-1

PM_SLP_S3_L

IMVP_VR_ON_R

PM_PWRBTN_L

PP1V5R1V35_SW_MCP

PP1V5_S3_REG

(1A MAX CURRENT)

(12A MAX CURRENT)

VOUT2

15-1

15-6

P5VS0_EN

15-5

15-4

15-3

MCPCORES0_EN

DELAY

P1V8S0_EN

CPUVTTS0_EN

P1V5S0_EN

DDRVTT_EN

3S2P

DELAY

(S0)

VIN

ADAPTER

DCIN(16.5V)

F6905

VIN

(S5)

PP18V5_DCIN_CONN

PPVBAT_G3H_CHGR_REG

Q7085

Q7080

8A FUSE

ISL9504B

SLP_S5_L

SLP_S3_L

SLP_S3_L(P93)

SLP_S5_L(P95)

U4900

PPBUS_G3H

ENABLE

VOUT

PP3V42_G3H_REG

SMC PWRGD

RST*

P17(BTN_OUT)

SMC_DCIN_ISENSE

CHGR_BGATE

U4900

Q3450

P3V3ENET_EN_L

VOUT

MAX8840

4.5V AUDIO

PP5V_S3_REG

(13A MAX CURRENT)

PP3V3_S5_REG

(5.5A MAX

SMC_PM_G2_EN

P16

PP0V75_S0_REG

(44A MAX CURRENT)

PPVCORE_S0_CPU

PP3V3_S3_FET

P3V3_S3_WLAN

P5VS0_EN

PP0V9_S5_REG

K86/K87 POWER SYSTEM ARCHITECTURE

VR_PWRGOOD_DELAY

P3V3S3_EN

PM_SLP_S3_L

DDRREG_EN

P5V3V3_PGOOD

PBUS_VSENSE

SYNC_MASTER=MASTER

SYNC_DATE=MASTER

Power Block Diagram

3 OF 109

C.0.0

051-8561

3 OF 76

TABLE_ALT_ITEM

PART NUMBER

ALTERNATE FOR

PART NUMBER

BOM OPTION

REF DES

COMMENTS:

TABLE_ALT_HEAD

TABLE_ALT_ITEM

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

BRANCH

REVISION

DRAWING NUMBER

SIZE

SHEET

PAGE TITLE

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

345678

8 7 5 4 2 1

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM NAME

BOM NUMBER

TABLE_BOMGROUP_HEAD

TABLE_ALT_ITEM

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM GROUP

TABLE_BOMGROUP_HEAD

BOM OPTIONS

BOM GROUP

TABLE_BOMGROUP_HEAD

TABLE_ALT_ITEM

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

TABLE_BOMGROUP_ITEM

Alternate Parts

514-0704 IS CLOUD GREY 4/LB3 PLASTIC W/PDNI PLATING VERSION OF 514-0692 PART FOR RJ45 CONNECTOR

BOM Groups (always-present)

BOM Groups (project phase-dependent)

SIGNAL(High Speed)

GROUND

SIGNAL(High Speed)

SIGNAL

GROUND

POWER

BOTTOM

8 9

10 11

TOP

K86/K87 BOARD STACK-UP

SIGNAL GROUND

SIGNAL(High Speed) SIGNAL(High Speed)

Bar Code Labels / EEE #’s

Part Substitutions (differences with K6/K69)

Development BOM

BOM Variants

POWER

LOCKED BOOTROM APN IS 341S2488 (QL: old info?)

Module Parts

353S2718 IS NEW INTERSIL PART FOR FIXING B4 DONGLE ISSUE

514-0705 IS CLOUD GREY 4/LB3 PLASTIC W/PDNI PLATING VERSION OF 514-0689 PART FOR USB CONNECTORS 514-0706 IS CLOUD GREY 4/LB3 PLASTIC W/PDNI PLATING VERSION OF 514-0691 PART FOR MINI DP CONNECTOR

Programmable Parts

514-0718 IS CLOUD GREY 4/LB3 PLASTIC W/PDNI PLATING VERSION OF 514-0694 PART FOR AUDIO CONNECTOR

ZS0912,ZS0913,ZS0914,ZS0915,ZS0919

CRITICAL870-1939

POGO PIN,TALL,NOISE-IMPROVED,SILVER,K87

152S0685152S0796

ALL

CYNTEC AS ALTERNATE

ALL

DALE/VISHAY AS ALTERNATE

104S0018 104S0023

152S0778

DALE/VISHAY, MAGLAYERS AS ALTERNATE

ALL

DELTA AS ALTERNATE

ALL

152S0874

MAGLAYERS AS ALTERNATE

ALL

152S0847

MAGLAYERS AS ALTERNATE

114S0125

LED:K86_K87

R5714

RES,MTL FILM,1/16W,113 OHM,1,0402,SMD,LF

CRITICAL826-4393

LBL,P/N LABEL,PCB,28MM X 6 MM

[EEEE_DD19]

EEEE:DD19

826-4393

[EEEE_DD17]

EEEE:DD17

CRITICAL

LBL,P/N LABEL,PCB,28MM X 6 MM

CRITICAL

826-4393

[EEEE_DD16]

EEEE:DD16

DEVELOPMENT_BOM

085-1632 CRITICAL

DEVEL

K87 MLB_LDO DEVELOPMENT BOM

CDC,SLGYW,PRQ,1.2,10W,800,R0,1M,BGA

U1000

CRITICAL CPU:1.2GHZ

ZS0900,ZS0901,ZS0902,ZS0903

CRITICAL870-1940

POGO PIN,MED,NOISE-IMPROVED,SILVER,K87

CRITICAL

ZS0917,ZS0918,ZS0916

870-1938

POGO PIN,THIN,NOISE-IMPROVED,SILVER,K87

U4900

SUBASSY, IC, SMC, K87

CRITICAL341T0252

SMC:PROG_K87

CRITICAL

338S0563

U4900

SMC:BLANK

U4900

SUBASSY, IC, SMC, K86

CRITICAL341T0250

SMC:PROG_K86

335S0610

U6100

CRITICAL

BOOTROM:BLANK

U6100

CRITICAL341T0251

BOOTROM:PROG

IC,WELLSPRING CONTROLLER,K87

U5701

CRITICAL

WELLSPRING:PROG

337S2983

U5701

CRITICAL

WELLSPRING:BLANK

KEMET AS ALTERNATE

ALL

353S1832

ALL

NEW IMPROVED INTERSIL PART AS ALTERNATE

ALL

MURATA AS ALTERNATE

SCREW1,SCREW2,SCREW3,SCREW4

CRITICAL452-1708

SCR.M1.6X0.35X6.0,D4,HO.3,BLK,M97

MOLEX_DDR_CONN

CRITICAL516-0213

J2900

CONN,204P,SODIMM,P=0.6MM

CRITICAL

U1400

337S3866

MCP89M:A02

IC,MCP89M-A02,31X31MM,BGA1168

337S3680

PDC,LGDZ,PRQ,2.40,25W,1066,R0,3M,BGA

CRITICAL

U1000

CPU:2.4GHZ

DEBUG_ADC,LPCPLUS_CON,S0PGOOD_ISL,EFI_DEBUG,MCPPLL_LDO,EXT1V05,XDP_CON,LPCPLUS

870-1939

ZS0904,ZS0905,ZS0906,ZS0907,ZS0910

CRITICAL

POGO PIN,TALL,NOISE-IMPROVED,SILVER,K87

ZS0908,ZS0909,ZS0911

870-1940

CRITICAL

POGO PIN,MED,NOISE-IMPROVED,SILVER,K87

CONN,204P,SODIMM,SOCKET,DDR3,RAM,BGA

516S0790

MOLEX_DDR_CONN

J3100

CRITICAL

516-0201

FOX_DDR_CONN

CRITICAL

J2900

CONN,204P,SODIMM,P=0.6MM

J3100

CONN,204P,SODIMM,SOCKET,DDR3,RAM,BGA

FOX_DDR_CONN

CRITICAL

U1400

MCP83M

IC,MCP83M-A02,31X31MM,BGA1168

U1400

337S3797 CRITICAL MCP89M:A01

IC,MCP89M-A01,31X31MM,BGA1168

K86_K87_COMMON

K86_K87_DEBUG:DEV

K86_K87_DEVELOPMENT_PVT

K86_K87_DEBUG:PRODPROJECT_PHASE:PROD

DEVELOPMENT_BOM

K86_SPECIFIC

K87_SPECIFIC

CPU:2.4GHZ,IMVP6:2PHASE,SMC:PROG_K87,MCP89M:A02

K86_K87_COMMON1

SYNC_MASTER=(K84_MLB)

BOM Configuration

SYNC_DATE=(01/19/2009)

CRITICAL

LBL,P/N LABEL,PCB,28MM X 6 MM

826-4393

EEEE:DD18

[EEEE_DD18]

085-1799

K86_K87_DEVELOPMENT_PVT

K87 MLB_LDO DEVELOPMENT BOM

K86_K87_COMMON,K87_SPECIFIC,MOLEX_DDR_CONN,EEEE:DD17

PCBA,MLB_LDO,MOLEX,K87

639-1116

639-1115

K86_K87_COMMON,K87_SPECIFIC,FOX_DDR_CONN,EEEE:DD16

PCBA,MLB_LDO,FOXCONN,K87

128S0093

152S0693

138S0602138S0603

353S2811

152S0516

128S0218

PROJECT_PHASE:DEV

LPCPLUS_CON,XDP_CON,VREFMRGN:YES,LPCPLUS

VREFMRGN:NO,BMON:PROD,BKLT:PROD,SENS_R:PROD,MCPHVDD:P2V5,LDO:FIXED,HTOL_SENSE:YES

VREFMRGN:YES,BMON:ENG,BKLT:ENG,SENS_R:ENG

K86_K87_COMMON1,PROJECT_PHASE:PROD,COMMON,ALTERNATE,BOOTROM:PROG,WELLSPRING:PROG,MCP_T_DIODE_SENSOR

DP_ESD,MIKEY,MCPPLL_R:REG,ENET1V05:INT,LED:K86_K87,S0PGOOD_BJT,ENET_ESD,VFRQ:SLPS3,SMC_DEBUG:YES,SPI:25MHZ,XDP,OLD_AUDIO_SWITCH

CPU:1.2GHZ,IMVP6:1PHASE,SMC:PROG_K86,MCP83M

337S3792

IC,FLASH,SPI,32MBIT,3.3V,86MHZ,8-SOP

IC,SMC,HS8/2117,9X9MM,TLP,HF

157S0055157S0058

152S0586

K86_K87_DEBUG:PROD

K86_K87_DEVELOPMENT_ONLY

337S3876

516S0706

341S2677

IC,PSOC+ W/ USB,56 PIN,MLF,CY8C24794

SUBASSY, IC, BOOT ROM, K86/K87

353S2988 353S2987

ALL

MIC5365 AS ALTERNATE

ALL

376S0634376S0908

TOSHIBA AS ALTERNATE

ALL

376S0634376S0907

ALL

FAIRCHILD AS ALTERNATE

376S0868376S0912

ONSEMI(NEW SPEC) AS ALTERNATE

4 OF 109

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051-8561

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Changed C7428 from 0.47uF => 0.33uF (132S0101) per Intersil

T27: Changed USB_RBIAS from 931-ohms to 887-ohms per DG v1.3 (pg. 18). <radar:7459260 > Design Guide v1.3 updates

2010-04-1: A.9.0

Added ONsemi new spec part(376S0912) as an alternate to Q2300(376S0868).

2010-04-14: C.0.0

CSA 4: Added Toshiba(376S0908), Fairchild(376S0907) as an alternate to 376S0634.

2010-04-14: B.0.0

rdar://7822714

CSA 77: Deleted U7740 1.05V LDO circuit to free space for U2592 and current mirror circuit.

Reverted the changes and synced back to A.0.0 Per <rdar://7783507> K87: Add cap to DDC line to avoid DDC line glitch issue

CSA 93: Added C9303 3300pF cap on DP_CA_DET.

CSA 4: Added Alternate part for U2592 LDO. 353S2987(TI), 353S2988(Micrel) to 353S2986(Intersil).

Reverted the changes and synced back to A.2.0.

CSA 25,49,50: Changed Q2592 gate control pin to SMC_P24 from SMC_P10.

CSA 25: Added R2600 0ohm resistor to help layout change.

CSA 25: Changed R2600 refdes to R2550 to match with page#.

CSA 69: R6905 kept same 1ohm. C6900 changed to 2.2uF. 138S0592. CSA 4: Devel BOM# changed to 085-1799. And BOM OPTIONS to K86_K87_DEVELOPMENT_PVT.

2010-04-1: A.10.0

Added IMVP6:2PHASE to R7413 per Intersil

Cosmetic cleanup csa 90: Deleted net properties for =PP5V_S3_CAMERA

csa 108: Added NET_PHYSICAL property to SATA_HDD_D2R_FILT_P and _N

csa 98: Deleted net properties for =PPBUS_S0_LCDBKLT

2009-12-09: 1.5.0

multiple: Added parentheses for SYNC_DATE property on all pages that have broken sync.

csa 4: Deleted entry in Module Parts table for R6612, R6617, R6630, R6633 since they were removed when we switched from piezo to dynamic speakers csa 69: Changed J6955 symbol to K87 Hall effect assembly (339S0114)

csa 74: Changed 1PHASE BOM table to correctly call out 132S0080 (0.22uF) instead of 0.022uF

csa 54: Began syncing from T27 per <radar:7432091 > BATT_ISENSE filter change to address lower max sink current on ISL6259 BMON pin (K17 auto-shutdown issue)

2010-03-30: A.7.0

2010-03-31: A.8.0

CSA 25: Added R2591,R2594 for LDO:ADJ option. Changed U2592 to LDO:FIXED option.

LDO:FIXED, MCPHVDD:P2V5 added in bom table.

csa 72: Changed L7220 from 152S0693 to 152S0778 per <rdar://problem/7347216> K69 L7260 combo footprint

C5490 changed from CAP_402-0.022UF,10%,16V,CERM-X5R to CAP_402-0.022UF,20%,16V,CERM

csa 29,31: Began syncing from T27 per <radar:7424246 > BOM: K87 needs omit on J3100 and J2900 from T27

csa 18: T27: Swapped USB_EXTB and USB_EXTD for NVRN-612340 (pg. 18). <radar:7416825> Ensure USB_EXTB is on ports 8-11 (NVRN-612340)

LDO:FIXED, MCPHVDD:P2V5 added in bom table.

Changed J5100 BOMOPTION from LPCPLUS to LPCPLUS_CON to unstuff connector at DVT

R7416 added to BOM Table, 16.9K, (APN 114S0336)

*** Started syncing with K6

CSA 25: Changed U2594 power to 3V3_S0 from 3V42_G3H.

Per <rdar://7783507> K87: Add cap to DDC line to avoid DDC line glitch issue

CSA 4: Added MCPHVDD:P2V5, LDO:FIXED, HTOL_SENSE:YES to BOM Group K86_K87_DEBUG:PROD

Added =PP3V3_S0_OPA330 alias to power U2593

CSA 8: Added =PP3V42_G3H_OPA330 alias to power U2594

CSA 93: Added C9303 3300pF cap on DP_CA_DET.

2010-03-22: A.4.0

csa 37: Per <rdar://problem/7548726> K86/K87 Ethernet series R’s need to be 0 ohmed

C7413 = 100pF 5% (131S1027)

2010-03-22: A.2.0

CSA 50: Removed SMC alias to TP for SMC_NB_MISC_ISENSE to enable sense circuitry connection to SMC

Changed BOMOPTION names from LDO:YES and LDO:NO to MCPHVDD:P2V5 and MCPHVDD:P3V3

Added R2594 and R2591 with LDO:ADJ BOMOPTION

Added C2599, R2597, R2596, U2593, Q2592, R2599, C2594, U2594, R2598, C2598 with BOMOPTION HTOL_SENSE:YES

Added BOM TABLE with LDO:FIXED, LDO:ADJ, and HTOL_SENSE:NO stuffing options

Removed SMC_P10 alias to TP_SMC_P10

2010-01-15: 2.3.0

csa 51: (Per <rdar://problem/7540522> K86/K87: Production Debug Components)

Added LPCPLUS_CON to K87_DEVEL_ENG (does not change BOM for DVT) Changed all instances of K87_DEBUG_xxxx to K87_DEBUG:xxxx

IMVP6:1PHASE BOM Table:

Changed description for 337S3876 to "IC,MCP83M-A02,31X31MM,BGA1168"

VREFMRGN:YES ==> VREFMRGN:NO

Changed 085-1093 to call out K87_DEVEL_PVT instead of K87_DEVEL_ENG

csa 4: Cosmetic: changed text sizes and alignment

2010-01-13: 2.2.0

Changed C4585, C4586 to 131S4713 (47pF, 5%)

Updated APN text note

Added the following functional test points under the J5100 LPC+SPI CONN FUNC_TEST group

Changed text note to say "HALL EFFECT ASSEMBLY"

Changed R3440 color to green, deleted WF text note about needing PU

Per <rdar://problem/7495072> K87: Call out LED:K86_K87 BOMOPTION in the K87_MISC BOM group

Removed table entry that says 376S0868 is an alternate for 376S0624

Created SMC:PROG_K86 pointing to 341T0250 (SUBASSY, IC, SMC, K86)

Deleted BOM table for Hall effect assembly

Syncing with K6 to pick up new symbols for Q2355 and Q2356

Switching from Engineering to Production BOM should only require changing PROJECT_PHASE:DEV to PROJECT_PHASE:PROD

Per <rdar://7542674 > K86/K87 Text note change

csa 45: Added PLACEMENT_NOTE for passive deemphasis circuit.

Changed K87_MCP BOM group to call out MCP89-A02 csa 34: Changed U3440 from AP002 part to AP016 (343S0511) per <radar:7459498> BOM: APN updates for FPF1009 and SAK parts

Changed BOOTROM:PROG to call out 341T0251 (SUBASSY, IC, BOOT ROM, K86/K87)

Keeping K86 and K87 pgs identical for CSA 74, modifying BOM table for IMVP 1 phase on K87’s schematic to reflect changes for K86.

CSA 25: U2590 added, APN 353S2971. R2592 of 10K and C2592 of 1UF, C2593 of 1UF added. Nets MCP_PLL_LDO_EN and PP3V3_S0_LDO_R added.

2010-03-22: A.3.0

CSA 25: Copied from K6

2010-03-22: A.1.0

Summary of changes for MLB_LDO:

csa 74, csa 79:

Removed OMIT from R4585, R4586

2010-01-06: 1.11.0

2010-02-25: 2.19.0, 2.20.0

2010-03-04: B.0.0

CSA 74: Changed C7434 from 0.033uF to 0.047uF (APN 132S0189) per Liang

CSA 12: C1200, C1204, C1207, C1209, C1211, C1219, C1202, C1216 NOSTUFFED

Per <rdar://7488543> K87/K86 Task Measure each power supply in mlb.

CSA 69: C6970, C6971, C6972 of 1000pF (APN 131S0222) added

Per <rdar://7678515> K87:EMC:ESD: System hangs on air/contact discharge to MPM connector

CSA 4: MOLEX_DDR_CONN added to Module Parts, removed from Alternate table. Added second 639 and EEEE # to BOM table

2010-03-09: 0.8.0

** MLB_LDO branch

2010-02-26: 2.21.0

2010-02-25: 2.18.0

CSA 67: J6700 changed from APN 514-0718 to 514-0750

CSA 12: C1233, C1230, C1237, C1234 changed from NOSTUFF to STUFFED.

2010-02-15: 2.10.0

2010-02-18: 2.12.0

CSA 74: For K86 only: C7434 = 0.1uF added, R7417 changed to 8.25Kohm

2010-02-16: 2.11.0

2010-02-15: 2.9.0

2010-02-02: 2.8.0

*** Resynced with T27 and K6 (no differences) *** Resynced Audio pages with the following changes:

csa 97: Changed R9710 from 7.32K 0402 1% to 7.68K (APN 114S0304) to support old K84 panel csa 4: Added OLD_AUDIO_SWITCH BOM OPTION to K86_K87_COMMON1

csa 54: Broke sync with T27. Per <rdar://problem/7605797> K69/K86/K87 sensor IN1C unreliable U5400 changed from OPA348 to OPA330. C5434 changed to NOSTUFF

CSA 74: R7417 changed to 5.90K, C7428 changed to 0.47uF, C7434 changed to 0.033uF

csa 4: Added BOM entry under Module Parts table to include CULV processor (337S3779) to minimize delta on this page between K86 and K87 per Diana

NOTE: All page numbers are .csa, not PDF. See page 1 for .csa -> PDF mapping.

csa 2: Updated CPU block text to include CPU description for both K86 and K87

Changed C9706 from 120pF to 220pF (131S2225)

Changed C9705 from 8.2nF to 33nF (132S0131)

-pg. 67, no stuffed R6712 and R6713

*** Resynced Audio pages with the following changes:

Added L4530, L4531 (APN 155S0137) to SIL connector pins csa 97: Per <rdar://problem/7589365> K86/k87: Compensation settings change to provide more phase margin, reduce ripple

-pg. 62, changed R6211 to 22 Ohms

csa 37: Per <rdar://problem/7554342> K86/K87: Change L3720 to 152S1182 Changed L3720 to 152S1182 (IND,PWR,SHD,4.7UH,20%,0.91A,31X31X12MM) for lower ESR

LPC_SERIRQ

Added text note with part numbers for components of the assembly

csa 69: Per <rdar://problem/7494087> K87: remove OMIT from J6955 and delete BOM table

Changed K87_PROGPARTS BOM group to point to SMC:PROG_K87

- MCO: 056-3515

Created SMC:PROG_K87 pointing to 341T0252 (SUBASSY, IC, SMC, K87)

2009-12-16: 1.8.0

csa 25: T27: Removed R2575 & R2580 per DG v1.3 (pg. 25). per <radar:7459260 > Design Guide v1.3 updates

*** Started syncing the following pages:

T27: Added gain note for U5402 and SMC_BATT_ISENSE (pg. 54).

*** Other changes

Changed component color to Green

=PP3V3_S0_DPCONN’

csa 45: Added passive deemphasis to SATA HDD D2R lines:

2009-12-10: 1.6.0

=PP1V05_S0_MCP_AVDD_UF’

R7411 = 255 1% (114S0160)

=PPSPD_S0_MEM_B’

=PP5V_S0_HDD’

R7409 = 1.58k 1% (114S0236)

Added BOM table to insert the following APNs for IMVP6:1PHASE:

- UPDATED SCHEMATIC AND PCB PART NUMBER INFO

- ALL PAGES SYNC’ED FROM K84

2009-12-08: 1.3.0

INITIAL RELEASE 0.0.1-

2009-12-07: 1.2.0

2009-12-04: 1.1.0

=PP3V3_S0_PWRCTL’

=PP5V_S0_MCPREG’

csa 8: Deleted net properties for the following nets:

2009-12-08: 1.4.0

10/1/2009:

2009-12-03: Proto 0 release 1.0.0

csa 74: Component value changes per Leo (Intersil):

C7434 from 0.12uF => 0.022uF, 10% (132S0102) Implemented different stuffing options for 1-phase vs 2-phase: Added IMVP6:2PHASE to the following components: R7417, C7428, R7409, R7411, C7406, R7414, C7414, C7413

C7428 = 0.22uF 10% (132S0102)

C7406 = 470pF 10% (132S4720) R7414 = 97.6k 1% (114S0410)

csa 74: Changed C7434 from NOSTUFF to IMVP6:2PHASE per Intersil

T27: Changed RC balance on BATT_ISENSE, same time constant (pg. 54).

Alternates table on csa 4 already has 152S0778 as alternate to 152S0693

STILL NEED TO UPDATE VALUE OF C7428!

C7414 = 1000pF 10% (132S0045) Updated table to add new values for 1phase (PWM freq., Max current, Load line)

Added C4585, C4586 (10pF, 5%, 131S0029) and NOSTUFFed

csa 57: Began syncing from T27 per <radar:7304029 > T27 schematic bom option for R5714 & R5030 to keep K87 in sync

Added R5714 (114S0125) to table with BOMOPTION LED:K86_K87

2009-12-17: 1.9.0

csa 4: Added BOM table to substitute in parts that have BOMOPTION xxx:K6_K69 (to allow sync with T27)

R7417 = 7.68k 1% (114S0304)

R7417 from 5.36k => 6.34k, 1% (114S0296)

csa 34: Deleted net properties for =PP3V3_S3_WLAN

csa 4: Per <rdar://problem/7473229> K86: Move to MCP83 This is for K86 ONLY. Adding entry to minimize delta on csa 4 between K87 and K86

Per <rdar://problem/7495116> K87: remove ON Semi alternate for Q2300 (376S0624)

Added LED:K86_K87 BOMOPTION to the K87_MISC BOM group

BOMOPTION is "MCP83M"

2009-12-22: 1.10.0

Updated DLY text note for U3440 to match T27

Changed R3454 to 100k, 1% (114S0411) to match T27 and K69

Added BOM table entry for MCP83M (337S3876)

- BOM: 639-0680

2010-01-07: 1.12.0

Changed BOMOPTION for R7872 from S0PGOOD_ISL to NOSTUFF

- Conn APN:518S0788" csa 78: Per <rdar://problem/7495000> K87: Add NOSTUFF to R7872 to disconnect U7870 from ALL_SYS_PWRGD

- PCBF: 820-2801

"Assembly APN: 339S0114

Deleted OMIT BOMOPTION from J6955

LPCPLUS_GPIO SMC_TMS

csa 23: *** BROKE SYNC WITH T27

csa 20; T27: Added CKPLUS_WAIVE properties to dismiss false errors (pg. 20). <radar:7368529> TASK: Waive false CheckPlus errors

2010-01-08: 2.0.0

Changed R4585, R4586 to 114S0065 (27.4 ohm, 1%)

csa 70: Per <rdar://problem/7519048> K86/K87: Change U7000 to 353S2929

Updated Q2355 and Q2356 with new schematic symbols

Changed K87_COMMON to call out K87_DEBUG_PVT instead of K87_DEBUG_ENG Diff from the two changes above:

Per <rdar://problem/7540522> K86/K87: Production Debug Components

csa 4: Per <rdar://problem/7540383> K86: Update CPU part number to 337S3792

R7417 changed to 7.87K (APN 114S0305)

R5714 has BOMOPTION LED:K6_K69, and we need to substitute a different part on csa 4

csa 74: Cosmetic change: moved R7413, C7406 BOMOPTION label so they don’t look like wire name

csa 7: Per <rdar://problem/7517432> K86/K87 functional net property needed on signals in schematics

Need to resync with T27 once the change has been made there Changed U7000 from 353S2392 to 353S2929

Deleted BOM table that stuffsdel the bypass option

2010-01-13: 2.1.0

Changed U1000 CPU:1.2GHZ BOMOPTION from 337S3779 to 337S3792

Toggled:

BKLT:ENG ==> BKLT:PROD Removed:

csa 74: Per <rdar://7525313 > K86 CPU loadline, OCP update

Added IMVP6:2PHASE BOM option to R7416 for K87’s 13.7K

Per <rdar://problem/7544629> K86/K87: Update MCP83 description on csa 4

Should switch syncing back to T27 once it is updated there

Changed BOM group structure to match that in the radar (see PDF attached to radar)

Reverted back to ENG BOM, no longer PROD BOM (i.e. reverted much of 2.2.0 changes)

Per <rdar://problem/7495021> K86/K87: Replace "S" APNs with "T" APNs for programmed SMC and BR

csa 45: Per <rdar://problem/7524364> K86/K87: change SATA HDD D2R passive EQ values

BMON:ENG ==> BMON:PROD SENS_R:ENG ==> SENS_R:PROD DEBUG_ADC, S0PGOOD_ISL, EFI_DEBUG, MCPPLL_LDO, EXT1V05, MCP_T_DIODE_SENSOR, XDP_CON

Unchanged: LPCPLUS, DEVEL_BOM, SMC_DEBUG:YES, XDP

Changed all instances of K87_DEVEL_xxxx to K87_DEVEL:xxxx

2010-01-18: 2.4.0

*** Resynced all synced pages and picked up the following (change notes from T27):

Revision History

=PP3V3_S0_CPUVTTISNS’

2010-01-28: 2.7.0

Changed BOMOPTIONs to be mutually exclusive (changed "_" to ":")

Added row to EEE table for E3T

2010-01-19: 2.5.0

- REPLACED K84 MCP AND CPU PAGES WITH K6 PAGES

Changed R9726 from 22k to 10k (114S0315) and removed NOSTUFF

*** Resynced with T27 and K6 (no differences)

csa 4: Per <rdar://problem/7571786> K86/K87: Add E3T EEE code for K86 to schematic

2010-01-22: 2.6.0

-pg. 66, added C6602 csa 45: Per <rdar://problem/7561001> K87:EMC: Radiated Emissions: Right Audio emissions fail

Added BOM table to stuff 0-ohms until we get go-ahead for filter

Added R4585, R4586 (51.1 ohm, 1%, 114S0093) and OMITted

csa 3: Updated text note to include "K86" in title

-pg. 67, added BOM options for U6700, R6712, and R6713 to support MAX14560 and MAX14504

Resync with T27 and K6. Clean up and rerelease schematic.

CSA 75: R7572 changed to 147K

Per <rdar://7644836> K87 power component update

CSA 69: J6955 BOMOPTION change to OMIT. Added BOM table with 607-6831 for J6955

2010-02-18: 2.17.0

Per <rdar://7686179> K86/K87 schematic: Change audio jack part number for new connector cap

CSA 97: U9700 changed to APN 353S2965

CSA 12: For K86 only: C1272 = 330uF added.

2010-02-18: 2.16.0

Per <rdar://7634730> K86/K87: add an RC on the LVDS_IG_BKL_PWM

Per <rdar://7685202> K86/K87 schematic: change U9700 to 353S2965 for Freescale backlight issue

Per <rdar://7488543> K86/K86 Task: Measure each Power supply in MLB

Per <rdar://7676934> K86/K87: Hall eff documentation change. Substitute 607-6831 for doc purposes

CSA 97: R9725 changed to 200ohm, C9799 of 47pF added. R9726.1 connection moved to LVDS_IG_BKLPWM

CSA 70: R7015 changed to 56.2K, C7015 changed to 1000pF, C7042 changed to 0.068uF

CSA 12: Added pads for 0603 caps (APN 138S0635). Compoonents C1230, C1231, C1232, C1233, C1234, C1235, C1236, C1237.

Per <rdar://7685811> K86/K87 schematic: add additional 639 for differentiation between Foxconn and Molex DIMM connectors

Per <rdar://7683852> K87 Proto1: 5 of 6 systems failing graphics noise (Underwater) acoustic spec by up to 3.1dB

Changed R3790-R3795 to 116S0004 (0-ohm, 0402) from 22-ohm

csa 23: Per <rdar://problem/7544657> K86/K87: Fix schematic symbol for Q2355, Q2356

Net change was to move LPCPLUS to the 639 (from the 085)

csa 4: Per <rdar://problem/7549122> K86/K87: Switch to new BOM group structure

Cleaned up text notes for 1phase, 2phase, and edp #s per radar request.

CSA 4: Added Alternate part for U2592 LDO. 353S2987(TI), 353S2988(Micrel) to 353S2986(Intersil).

2010-03-22: A.5.0

Removed NOSTUFF from C4585, C4586

Per <rdar://problem/7519025> K86/K87: update all instances of 376S0786 schematic symbols

Removed Intersil LDO(353S2986).

csa 4: Added BOM table entry for MCP89-A02 per <radar:7416858 > Task: Get part numbers for A02 rev.

*** Made the following changes to follow T27 on the following unsynced pages:

T27: Added CKPLUS_WAIVE properties to dismiss false errors (pg. 54).

T27: Added BOMOPTIONs and APNs for Foxconn and Molex SO-DIMM connectors (pp. 29, 31).

2009-12-11: 1.7.0

csa 69: Added OMIT to J6955, BOM table to stuff K84 Hall effect connector

Revision History

SYNC_DATE=MASTER

SYNC_MASTER=MASTER

5 OF 109

C.0.0

051-8561

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II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

BRANCH

REVISION

DRAWING NUMBER

SIZE

SHEET

PAGE TITLE

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

345678

8 7 5 4 2 1

Revision History

NOTE: All page numbers are .csa, not PDF. See page 1 for .csa -> PDF mapping.

SYNC_DATE=MASTER

SYNC_MASTER=MASTER

Revision History

6 OF 109

C.0.0

051-8561

6 OF 76

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

BRANCH

REVISION

DRAWING NUMBER

SIZE

SHEET

PAGE TITLE

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

345678

8 7 5 4 2 1

Functional Test Points

FSB SIGNALS WITH NOTEST

(NEED TO ADD 1 GND TP)

(NEED 2 TP)

(NEED 4 TP)

(NEED TO ADD 3 GND TP)

(NEED 2 TP)

DC POWER CONN FUNC_TEST

(NEED TO ADD 2 GND TP)

(NEED TO ADD 4 GND TP)

(NEED TO ADD 5 GND TP)

POWER NETS FUNC_TEST

(NEED 2 TP)

X16 WIRELESS CONN FUNC_TEST

(NEED 4 TP)

MIC FUNC_TEST

SPEAKER FUNC_TEST

J5100 LPC+SPI CONN FUNC_TEST

(NEED TO ADD 6 GND TP)

(NEED TO ADD 1 GND TP)

(NEED TO ADD 4 GND TP)

(NEED TO ADD 2 GND TP)

KEYBOARD CONN FUNC_TEST

(NEED 3 TP)

SATA ODD CONN FUNC_TEST

LVDS FUNC_TEST

IPD_FLEX_CONN FUNC_TEST

(NEED TO ADD 2 GND TP)

BATT POWER CONN FUNC_TEST

(NEED 2 TP)

FAN CONNECTORS FUNC_TEST

(NEED TO ADD 3 GND TP)

SATA HDD/SIL FUNC_TEST

HALL EFFECT CONNECTOR FUNC_TEST

(NEED TO ADD 4 GND TP)

TRUE

SPI_MISO

PP3V3_S0_LCD_DDC_F

TRUE

FSB_A_L<35..3>

NO_TEST=TRUE

PM_SLP_S4_L

TRUE

PP3V3_S3

TRUE

PP1V5R1V35_S3

TRUE

PP5V_SW_ODD

TRUE

PP1V5_S0

TRUE

PP1V05_S0

TRUE

PPVCORE_S0_MCP

PP5V_S0

TRUE

PP5V_S0

TRUE

PP1V8_S0

PPDDRVTT_S0

TRUE

PP0V9_S5

TRUE

PP5V_S3_CAMERA_F

TRUE

SMC_PM_G2_EN

PM_SLP_S3_L

TRUE

PP4V5_AUDIO_ANALOG

TRUE

PP3V3_S5_AVREF_SMC

TRUE

PP3V3_SW_LCD_PANEL_F

PPVOUT_S0_LCDBKLT

TRUE

PP5V_S0_HDD_FLT

TRUE

CONN_PCIE_MINI_D2R_N

TRUE

PPVCORE_S0_CPU

FSB_HIT_L

NO_TEST=TRUE

FSB_DINV_L<3..0>

NO_TEST=TRUE

FSB_DSTB_L_N<3..0>

NO_TEST=TRUE

FSB_LOCK_L

NO_TEST=TRUE

FSB_HITM_L

NO_TEST=TRUE

WS_CONTROL_KBD

TRUE

WS_LEFT_OPTION_KBD

TRUE

WS_LEFT_SHIFT_KBD

WS_KBD15_CAP

TRUE

CONN_PCIE_MINI_R2D_N

WS_KBD14

TRUE

WS_KBD13

WS_KBD5

TRUE

FSB_D_L<63..0>

NO_TEST=TRUE

FSB_ADS_L

NO_TEST=TRUE

TRUE

WS_KBD7

TRUE

WS_KBD8

TRUE

WS_KBD9

TRUE

WS_KBD10

PP3V3_S3

TRUE

USB_CAMERA_CONN_P

TRUE

LVDS_IG_A_DATA_P<0>

TRUE

LVDS_IG_A_DATA_N<0>

TRUE

LVDS_IG_A_DATA_N<1>

TRUE

WS_KBD4

PSOC_SCLK

TRUE

WS_KBD23

TRUE

SATA_HDD_R2D_N

TRUE

LVDS_IG_A_DATA_P<1>

TRUE

SATA_HDD_D2R_C_P

TRUE

PP3V42_G3H

TRUE

SMC_LID_R

TRUE

CONN_PCIE_MINI_R2D_P

TRUE

Z2_HOST_INTN

TRUE

PSOC_F_CS_L

TRUE

PP3V3_S3_BT_F

WS_KBD_ONOFF_L

TRUE

PP3V42_G3H WS_KBD1

TRUE

ADAPTER_SENSE

TRUE

PP18V5_DCIN_FUSE

PICKB_L

TRUE

Z2_SCLK

TRUE

PSOC_MOSI

PSOC_MISO

TRUE

SPKRAMP_L_N_OUT

TRUE

Z2_MISO

TRUE

Z2_CS_L

TRUE

USB_CAMERA_CONN_N

NO_TEST=TRUE

FSB_REQ_L<4..0>

FSB_DSTB_L_P<3..0>

NO_TEST=TRUE

FSB_ADSTB_L<1..0>

NO_TEST=TRUE

Z2_DEBUG3

TRUE

Z2_CLKIN

TRUE

Z2_KEY_ACT_L

TRUE

Z2_BOOST_EN

WS_KBD22

TRUE

LED_RETURN_5

TRUE

PP5V_S0

TRUE

CONN_PCIE_MINI_D2R_P

TRUE

PCIE_CLK100M_MINI_CONN_P

PCIE_WAKE_L

TRUE

BI_MIC_P

TRUE

PP3V3_S0

TRUE

PP3V3_S5

FAN_RT_TACH

TRUE

PP3V42_G3H

TRUE TRUE

SPI_CLK

TRUE

PPVTT_S3_DDR_BUF

TRUE

PP1V05_S0_MCP_PLL_UF

TRUE

SPKRAMP_R_P_OUT

BI_MIC_N

TRUE

FAN_RT_PWM

TRUE

PP3V42_G3H

TRUE

PP3V3_G3_RTC

PP0V9_ENET

TRUE

PPBUS_G3H

TRUE

PP5V_S3

Z2_MOSI

TRUE

Z2_RESET

TRUE

SMBUS_SMC_A_S3_SDA

WS_KBD2

TRUE TRUE

WS_KBD3

TRUE

WS_KBD11

TRUE

WS_KBD12

TRUE

LED_RETURN_3

TRUE

LED_RETURN_2

TRUE

LVDS_IG_A_CLK_F_P

TRUE

LVDS_IG_A_CLK_F_N

LED_RETURN_1

TRUE

SMBUS_SMC_A_S3_SCL

TRUE

PP3V3_SW_LCD_PANEL_F

TRUE

LVDS_IG_DDC_CLK

TRUE

LVDS_IG_DDC_DATA

TRUE

PPVOUT_S0_LCDBKLT

TRUE

SPKRAMP_SUB_P_OUT

TRUE

CONN_USB2_BT_N AP_CLKREQ_Q_L

TRUE

AP_RESET_CONN_L

TRUE

PP18V5_S3

TRUE

PP3V3_WLAN

PP3V3_ENET

TRUE

SPI_MOSI

PP18V5_S3

TRUE

SPI_CS0_L

SPIROM_USE_MLB

TRUE TRUE

LPCPLUS_GPIO

TRUE

LPC_SERIRQ

TRUE

SMC_TMS

WS_KBD21

TRUE

WS_KBD20

TRUE

WS_KBD19

TRUE

WS_KBD18

TRUE

WS_KBD17

WS_KBD16_NUM

TRUE

WS_KBD6

TRUE

SMC_ODD_DETECT

TRUE

SATA_HDD_D2R_C_N

TRUE

SYS_LED_ANODE_R

TRUE

PPVBAT_G3H_CONN

TRUE

PP5V_S0_HDD_FLT

CONN_USB2_BT_P

TRUE

PP3V3_S3

TRUE

BI_MIC_SHIELD

TRUE

PCIE_CLK100M_MINI_CONN_N PP3V3_WLAN

TRUE

SPKRAMP_SUB_N_OUT

TRUE

SPKRAMP_L_P_OUT

TRUE TRUE

SPKRAMP_R_N_OUT

TRUE

PP5V_SW_ODD

TRUE

PP5V_S3_CAMERA_F

TRUE

LED_RETURN_6

TRUE

LED_RETURN_4

TRUE

LVDS_IG_A_DATA_P<2>

LVDS_IG_A_DATA_N<2>

TRUE

SMBUS_SMC_BSA_SDA

TRUE

SYS_DETECT_L

TRUE

SMBUS_SMC_BSA_SCL

TRUE

SATA_HDD_R2D_P

TRUE

SATA_ODD_D2R_C_P

SATA_ODD_D2R_C_N

TRUE

SATA_ODD_R2D_N

TRUE

SATA_ODD_R2D_P

SYNC_DATE=MASTER

FUNC TEST

SYNC_MASTER=MASTER

I449

I448

I447

I446 I445

I444

I443

I442

I421

I418

I417

I413

I412 I411

I410

I409

I408

I407

I406

I405

I404 I403

I402

I401

I400

I399

I398

I397

I396

I395

I393

I392

I391

I390

I389

I388

I386

I385

I383

I382

I381

I380

I378

I377

I376

I374

I372

I371

I370

I369

I368

I366

I365

I364

I363

I362

I361

I360

I359

I358

I357

I355

I354

I353

I352

I351

I350

I349

I348

I347

I346

I345

I344

I343

I342

I341

I340

I339

I338

I337

I336

I335

I334

I333

I332

I331

I330

I329

I328

I327

I326

I322

I321

I320

I319

I318

I317

I315

I314

I313

I312

I308

I307

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I302

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I298

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I273

I271

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I266

I265

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I262

I261

I260

I258

I257

I256

I255

I254

I253

I252

I251

I250

I249

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I245

I239

I238 I237

I231

I230

I229

I228

I227

I226

I16

I15

I12

7 OF 109

C.0.0

051-8561

7 OF 76

72 37 19

69 14 10

62 36 35 19

8 7

46 33

75 62

8 7

62 35

66 62 35 19

36 35

67 64 46

75 30

69 14 10

75 30

69 14 10

8 7

75 64

71 64

44 43

71 33

71 64

71 33

8 7

75 30

44 43

8 7

44 43

52 51

44 43

75 64

69 14 10

44 43

67 64

8 7

75 30

30 16

75 53 52

75 62

8 7

72 37

52 51

75 53 52

8 7

23 20 19

44 43

74 38

67 64

75 64

67 64

74 38

67 64 46

52 51

75 30

72 37

47 37 19

37 19

37 35 19

37 36 35

35 33

71 33

55 54

75 30

8 7

53 52

75 30

52 51

46 33

67 64

71 64

74 38

71 33

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

BRANCH

REVISION

DRAWING NUMBER

SIZE

SHEET

PAGE TITLE

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

345678

8 7 5 4 2 1

0 MA

LVDDR VRef/VTT (0.75V/0.675V) Rails

4250 MA

DIGITAL GROUND

(CONNECTS TO THE DECAPS)

(SINCE PE0[3:0] IS NOT USED ON K6)

(CONNECTS TO MCP BALLS)

(CPU VCORE PWR)

"S3" RAILS

"G3H" RAILS"S0,S0M" RAILS

UNUSED MCP PE0[3:0] AVDD/DVDD

(MCP VCORE AFTER SENSE RES)

(CONNECTS TO THE DECAPS)

FIX ME!! OUTPUT OF REGULATOR VALUES

105/241 MA

"S5" RAILS

"ENET" RAILS

MIN_NECK_WIDTH=0.20MM

MIN_LINE_WIDTH=0.50MM

GND

VOLTAGE=0V

=PP3V3_S3_PDCISENS

=PP3V3_S3_MCP_GPIO

=PPBUS_G3H

=PP3V42_G3H_OPA330

=PP3V42_G3H_BMON_ISNS

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM

PP3V42_G3H

VOLTAGE=3.42V

=PP3V42_G3H_HALL

=PPLVDDR_S3_MEM_A

MIN_NECK_WIDTH=0.17 mm

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 mm

PP1V5R1V35_S3

VOLTAGE=1.5V

=PP1V05_S0_MCP_PLL_IFP =PP1V05_S0_MCP_DP0_VDD

=PP3V3_S0_FAN_RT

=PPVCORE_S0_MCPGFXFET

=PP1V05_SW_MCP_FSB

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM

PPVCORE_S0_MCP

VOLTAGE=1.05V MAKE_BASE=TRUE

=PPVCORE_S0_MCP

PPVTT_S3_DDR_BUF

MIN_LINE_WIDTH=0.3 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=0.75V MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=1.5 mm

VOLTAGE=1.5V

PP1V5_S0

MAKE_BASE=TRUE

=PPCPUVTT_S0_REG

MIN_NECK_WIDTH=0.20 MM

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.30 MM

VOLTAGE=5V

PP5V_S0

=PP1V05_S0_CPU =PP1V05_S0_MCP_FSB

=PPVIN_S3_DDRREG

=PPBUS_S5_CPUREGS_ISNS_R

PPBUS_G3H

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.4 mm

VOLTAGE=12.6V

=PPVIN_S5_3V3S5

=PPBUS_S0_LCDBKLT

PPBUS_S5_IMVP_VTT_ISNS

MIN_LINE_WIDTH=0.6 mm

VOLTAGE=12.6V

MIN_NECK_WIDTH=0.3 MM

MAKE_BASE=TRUE

=PP3V3_S3_BT

=PPDCIN_S5_CHGR

=PP3V42_G3H_ONEWIRE

MIN_NECK_WIDTH=0.25 mm

PP3V3_S3

VOLTAGE=3.3V MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.5 mm

=PP5V_S0_LPCPLUS

=PP3V3_S5_REG

=PP3V3_S5_P3V3S3FET

=PP3V3_S5_MCPPWRGD

=PP3V3_S5_MCP

=PP3V3_S0_LCD_PANEL

=PP3V3_S0_FET

=PP3V3_S0_MCP_HVDD

=PP3V3_S0_P1V8S0

=PP3V3_S0_SMBUS_MCP_1

=PP3V3_S0_SMBUS_SMC_0_S0 =PP3V3_S0_SMBUS_SMC_B_S0

=PP3V3_S0_XDP

=PP3V3_S5_DP_PORT_PWR

=PP3V3_S5_P0V9S5 =PP3V3_S5_P3V3ENETFET

=PP3V3_S5_P3V3S0FET

=PP3V3_S5_VMON

=PP3V3_S3_SMBUS_SMC_MGMT

=PPVCORE_S0_CPU

=PPVTT_S3_DDR_BUF

=PP5V_S0_CPU_IMVP

=PP5V_S0_FAN_RT

=PP5VR3V3_S0_DPCADET =PP5V_S0_CPUVTTS0

=PP3V3_S3_VREFMRGN

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V

PP3V3_ENET_PHY_VDDREG

=PP3V3_ENET_PHY_VDDREG

=PP3V3_S3_SMBUS_SMC_A_S3

=PP5V_S3_P5VS0FET

=PP3V3_ENET_PHY

=PP1V5_S0_FET

=PP1V5R1V35_S0_MCPDDRFET

=PP1V5R1V35_S3_MCP_MEM

=PPDDR_S3_REG

=PPLVDDR_S3_MEM_B

=PPVIN_S0_DDRREG_LDO

=PP1V05_S0_REG

PP1V05_S0_REG

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.2mm

MIN_LINE_WIDTH=0.4MM

MAKE_BASE=TRUE

RTL8211_REGOUT

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.2mm

MIN_LINE_WIDTH=0.4MM

MAKE_BASE=TRUE

=PP1V05_ENET_PHY

=PP0V9_ENET_FET

=PPDDRVTT_S0_MEM_B

MIN_LINE_WIDTH=0.6 mm VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2 mm

MAKE_BASE=TRUE

PP3V3_ENET

=PP3V3_ENET_MCP_RMGT

=PP3V3_ENET_MCP_PLL_MAC

=PP3V3_ENET_FET

=PP0V9_ENET_P0V9ENETFET

=PP1V05_S0_MCP_PLL_UF_R =PP1V05_S0_MCP_M2CLK_DLL

=PPVCORE_S0_CPU_REG

=PP3V42_G3H_REG

PPDDRVTT_S0

MIN_NECK_WIDTH=0.2 mm

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.4 MM VOLTAGE=0.75V

=PP3V3R1V8_S0_MCP_IFP_VDD

=PP5V_S3_REG

=PP3V3_S3_TPAD

MAKE_BASE=TRUE

PP1V05_S0_MCP_PE_AVDD

=PP1V05_S0_MCP_PE_DVDD1

=PP1V05_S0_MCP_PE_DVDD

=PP1V05_S0_MCP_PE_AVDD0

=PP1V05_S0_MCP_PE_DVDD0

=PP3V3_S3_FET

=PPVIN_S5_SMCVREF

=PP3V42_G3H_PWRCTL

=PP3V42_G3H_SMBUS_SMC_BSA

=PP3V3_S5_SMC

=PP3V42_G3H_SMCUSBMUX =PP3V42_G3H_TPAD

=PP3V42_G3H_CHGR

=PP3V3_S5_LPCPLUS

=PP1V05_S0_MCP_PE_AVDD1

=PPVIN_S0_CPUVTTS0 =PPVIN_S5_CPU_IMVP

=PP1V05_S0_MCP_PLL_UF

=PPBUS_S5_CPUREGS_ISNS

=PP5V_S3_MCPDDRFET

=PP18V5_DCIN_CONN

PP1V8_S0

MIN_LINE_WIDTH=0.10MM

VOLTAGE=1.8V MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.10MM

=PP3V3R1V5_S0_AUDIO

=PP1V8R1V5_S0_AUDIO

=PP1V5_S0_CPU

=PPDDRVTT_S0_MEM_A

=PPVTT_S0_DDR_LDO

=PP1V05_S0_MCP_PLL_OR

PP1V05_S0_MCP_PLL_UF

MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V

MIN_LINE_WIDTH=0.6 mm

MAKE_BASE=TRUE

PP3V3_G3_RTC

=PP3V3_S3_SMS

=PP1V05_S0_MCP_SATA_DVDD

=PPMCPCORE_S0_REG

=RTL8211_REGOUT

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.4 mm

PP0V9_ENET

VOLTAGE=0.9V

=PP0V9_ENET_MCP_RMGT

=PP1V5_S0_MCP_PLL_VLDO

=PP1V8_S0_REG

=PP3V3R1V5_S0_MCP_HDA

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.2mm

MIN_LINE_WIDTH=0.4MM

MAKE_BASE=TRUE

PP1V05_ENET

=PP3V3_S5_P0V9ENETFET

=PP5V_S3_AUDIO_AMP

=PP3V3_S3_WLAN

=PP5V_S0_MCPFSBFET

=PP5V_S0_FET

=PP3V3_S0_AUDIO

=PP3V3_S0_IMVP

=PP3V3_S0_LCD_DDC

MAKE_BASE=TRUE

VOLTAGE=5V

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

PP5V_S3

=PP5V_S3_EXTUSB

=PPVIN_S3_5VS3

VOLTAGE=18.5V

PP18V5_G3H

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.3 MM

MAKE_BASE=TRUE

=PPVIN_S0_MCPCORE

=PP3V3_S0_SMBUS_MCP_0

=PPSPD_S0_MEM_A

=PP3V3_S0_MCP_GPIO

=PP3V3_S0_MCP_PLL_UF

=PP5V_S3_ODD

=PP5V_S3_SYSLED

=PP5V_S3_DEBUG_ISNS

=PP5V_S3_AUDIO

=PP5V_S3_TPAD

=PP5V_S3_DEBUG_ADC_AVDD

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM

MAKE_BASE=TRUE

VOLTAGE=1.05V

PP0V9_S5

=PP0V9_S5_MCP_VDD_AUXC

=PP5V_S3_CAMERA

=PP5V_S3_DEBUG_ADC_DVDD

=PP5V_S3_DDRREG

MAKE_BASE=TRUE

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.20MM

PP3V3_S5

MIN_LINE_WIDTH=0.30MM

=PP3V3_S5_MCP_GPIO =PP3V3_S5_ROM

=PP0V9_S5_REG

=PP3V3_S0_ODD

=PP3V3_S0_MCP

=PP3V3_S0_SMC =PP3V3_S0_MCPTHMSNS

=PP5V_S0_HDD =PP5V_S0_MCPREG

=PP1V05_S0_MCP_AVDD_UF

=PPSPD_S0_MEM_B =PP3V3_S0_PWRCTL

=PP3V3_S0_DPCONN

=PP3V3_S0_CPUVTTISNS

=PP1V05_S0_MCP_PE_DVDD

PPVCORE_S0_CPU

MIN_NECK_WIDTH=0.3 MM VOLTAGE=1.25V

MIN_LINE_WIDTH=0.6 MM

MAKE_BASE=TRUE

=PP3V3_S0_CPUTHMSNS

=PP3V3_S0_MCP_PLL_VLDO =PP3V3_S0_MCPDDRISNS =PP3V3_S0_DEBUGROM

MIN_NECK_WIDTH=0.20MM

MIN_LINE_WIDTH=0.30MM

MAKE_BASE=TRUE

PP3V3_S0

VOLTAGE=3.3V

=PP3V3_S0_MCPCOREISNS =PP3V3_S0_OPA330

MAKE_BASE=TRUE

VOLTAGE=1.05V

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm

PP1V05_S0

SYNC_DATE=MASTER

SYNC_MASTER=MASTER

Power Aliases

R0814

402

MF-LF

ENET1V05:INT

1/16W

R0813

ENET1V05:EXT

1/16W05%

402

MF-LF

R0812

402

MF-LF

ENET1V05:INT

1/16W

8 OF 109

C.0.0

051-8561

8 OF 76

1 2

24 17

23 20

75 62

13 12 11 10

23 20 14

23 20

12 11

57 29

63 57

23 20 18

63 62 61

23 15

24 17

44 43

36 35

62 55

12 11

23 20 19

23 20

23 19

53 52 48

19 18 17

52 50 48

23 20

75 62

19 18

23 20

75 62

OUT

IN IN

IN IN IN

OUT

OUT OUT OUT

BI BI

BI BI OUT

IN IN

OUT

BI BI

BI BI OUT

OUT

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

BRANCH

REVISION

DRAWING NUMBER

SIZE

SHEET

PAGE TITLE

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

345678

8 7 5 4 2 1

USB ALIASES

UNUSED USB PORTS

SMC ALIASES

LVDS ALIASES

ETHERNET ALIASES

1 1 1

BSEL<2..0>

0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0

0 0 0

133 200

333 100

(RSVD)

(166)

(400)

266

FSB MHZ

MCP89 MISC ALIASES

MLB MOUNTING (TO C. BRACKET) SCREW HOLES

MLB MOUNTING (TO TOPCASE) SCREW HOLES

LVDS CONNECTOR HOLE

EMI THINBC POGO PINS

EMI TALL POGO PINS

(870-1698 )

LEFT OF CPU

EMI IO MEDIUM POGO PINS

PCI-E ALIASES

ABOVE CPU

BELOW CPU

(870-1794 )

HEATSINK STANDOFFS

FAN STANDOFF

UNUSED GPU LANES

CPU FSB FREQUENCY STRAPS

CHARGER SIGNAL

MCP89 ETHERNET VREF

UNUSED ETHERNET LANE

UNUSED FIREWIRE LANE

DISPLAY PORT ALIASES

BELOW MCP

(870-1820 )

CPU VCORE ALIASES

=PEG_D2R_P<15:0>

MAKE_BASE=TRUE

PCIE_AP_D2R_N

MAKE_BASE=TRUE

PCIE_AP_D2R_P

MAKE_BASE=TRUE

PCIE_AP_R2D_C_N

PCIE_MINI_R2D_C_N

CONN_PCIE_MINI_D2R_P

CONN_PCIE_MINI_D2R_N

DP_IG_AUX_CH1_N

DP_IG_ML1_P<0..3>

DP_IG_ML0_N<0..3>

=MCP_IFPA_TXC_P

LCD_IG_PWR_EN

LCD_IG_BKLT_EN

=PP3V3_ENET_PHY

MAKE_BASE=TRUE

TP_USB_EXTD_N

TP_USB_EXTC_N

MAKE_BASE=TRUE

NC_LVDS_IG_B_DATA_P<0..3>

NO_TEST=TRUE

MAKE_BASE=TRUE

LVDS_IG_BKL_ON

NC_LVDS_IG_B_CLK_N

NO_TEST=TRUE

MAKE_BASE=TRUE

LVDS_IG_BKL_PWM

LVDS_IG_A_CLK_P

MAKE_BASE=TRUE

NC_LVDS_IG_A_DATA_P3

NO_TEST=TRUE

MAKE_BASE=TRUE

TP_ENET_CLK125M_TXCLK TP_ENET_TXD<0..3>

ENET_CLK125M_TXCLK

MAKE_BASE=TRUE

ENET_TX_CTRL

MAKE_BASE=TRUE

TP_SMC_SYS_KBDLED

MAKE_BASE=TRUE

TP_CPU_PECI_MCP

=MCP_BSEL<0:2>

CPU_PECI_MCP

MAKE_BASE=TRUE

CPU_BSEL<0:2>

PCIE_ENET_R2D_C_N

PCIE_CLK100M_ENET_N

TP_PCIE_CLK100M_ENET_P

MAKE_BASE=TRUE

LVDS_IG_A_DATA_P<0..2>

LVDS_IG_A_DATA_N<0..2>

MAKE_BASE=TRUE

=MCP_IFPA_TXD_N<0..2>

=MCP_IFPA_TXD_P<0..2>

PCIE_AP_R2D_P

MAKE_BASE=TRUE

LVDS_IG_DDC_CLK

MAKE_BASE=TRUE

TP_FW_CLKREQ_L

PCIE_ENET_D2R_N

PCIE_ENET_D2R_P

ENET_ENERGY_DET

PCIE_CLK100M_FW_P

=PP3V3_ENET_FET

PCIE_ENET_R2D_C_P

TP_MCP_MEM_VDD_SEL_1V5

MAKE_BASE=TRUE

MCP_MEM_VDD_SEL_1V5

TP_ENET_CLKREQ_L

MAKE_BASE=TRUE

LVDS_IG_A_CLK_N

MAKE_BASE=TRUE

TP_ENET_MDC

TP_MCP_CLK25M_BUF0_R

TP_ENET_TX_CTRL

TP_ENET_RESET_L

ENET_RESET_L

MAKE_BASE=TRUE

MCP_CLK25M_BUF0_R

MAKE_BASE=TRUE

ENET_TXD<0..3>

TP_USB_MINI_P

MAKE_BASE=TRUE

TP_USB_T57_N

MAKE_BASE=TRUE

TP_USB_T57_P

MAKE_BASE=TRUE

TP_USB_WM_N

TP_USB_WM_P

MAKE_BASE=TRUE

USB_WM_N USB_IR_N

TP_USB_IR_N

MAKE_BASE=TRUE

TP_DP_IG_ML1N<0..3>

MAKE_BASE=TRUE

NC_LVDS_IG_B_CLK_P

NO_TEST=TRUE

NC_LVDS_IG_B_DATA_N<0..3>

NO_TEST=TRUE

MAKE_BASE=TRUE

=MCP_IFPA_TXC_N

=MCP_IFPAB_DDC_DATA

USB_MINI_P

PCIE_CLK100M_AP_P

MAKE_BASE=TRUE

PCIE_CLK100M_AP_N

CONN_PCIE_MINI_R2D_P

CONN_PCIE_MINI_R2D_N

=PEG_D2R_N<15:0>

MAKE_BASE=TRUE

TP_PCIE_FW_D2R_N

TP_PCIE_CLK100M_FW_N

MAKE_BASE=TRUE

TP_PCIE_CLK100M_FW_P

MAKE_BASE=TRUE

TP_FW_PME_L

FW_PWR_EN

PCIE_FW_D2R_N

LCD_IG_BKLT_PWM

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_PEG_R2D_C_P<15:0>

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_PEG_D2R_P<15:0>

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_PEG_D2R_N<15:0>

MAKE_BASE=TRUE

PCIE_AP_R2D_N

DP_IG_ML_N<0..3>

DP_IG_HPD1

=MCP_IFPA_TXD_P<3>

NC_LVDS_IG_A_DATA_N3

NO_TEST=TRUE

MAKE_BASE=TRUE

USB_EXTC_N

TP_PCIE_CLKREQ_L

MAKE_BASE=TRUE

=PEG_R2D_C_P<15:0>

=PEG_R2D_C_N<15:0>

USB_EXTD_N

MAKE_BASE=TRUE

TP_USB_EXTD_P

USB_EXTD_P

USB_EXTC_P

TP_USB_SDCARD_P

MAKE_BASE=TRUE

USB_MINI_N

USB_T57_N

PCIE_CLK100M_MINI_P

PCIE_CLK100M_MINI_N

USB_T57_P

USB_SDCARD_N

MAKE_BASE=TRUE

TP_USB_SDCARD_N

USB_WM_P

USB_SDCARD_P

PEG_CLK100M_P

PEG_CLKREQ_L

PCIE_AP_R2D_C_P

MAKE_BASE=TRUE

TP_USB_IR_P

USB_IR_P

=MCP_IFPAB_DDC_CLK

MAKE_BASE=TRUE

TP_USB_EXTC_P

TP_USB_MINI_N

MAKE_BASE=TRUE

PCIE_MINI_R2D_C_P

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_PEG_R2D_C_N<15:0>

PEG_CLK100M_N

MAKE_BASE=TRUE

TP_PEG_CLK100M_N

MAKE_BASE=TRUE

TP_PEG_CLK100M_P

MAKE_BASE=TRUE

ENET_MDC

MAKE_BASE=TRUE

LVDS_IG_DDC_DATA

DP_EXT_HPD

MAKE_BASE=TRUE

DP_EXT_CA_DET

DP_EXT_AUX_CH_C_N

MAKE_BASE=TRUE

TP_DP_IG_AUX_CH1N

DP_EXT_ML_P<0..3>

MAKE_BASE=TRUE

DP_IG_ML_P<0..3>

DP_EXT_AUX_CH_C_P

MAKE_BASE=TRUE

SMC_SYS_KBDLED

SMC_BC_ACOK

MAKE_BASE=TRUE

=PP3V3_ENET_MCP_RMGT

MCP_RGMII_VREF

=RTL8211_ENSWREG

=MCP_IFPB_TXD_N<0..3>

=MCP_IFPB_TXD_P<0..3>

=MCP_IFPB_TXC_P

LVDS_IG_PANEL_PWR

MAKE_BASE=TRUE

TP_PCIE_FW_R2D_C_N

TP_PCIE_FW_R2D_C_P

MAKE_BASE=TRUE

PCIE_FW_D2R_P

PCIE_FW_R2D_C_N

=MCP_IFPB_TXC_N

=MCP_IFPA_TXD_N<3>

MAKE_BASE=TRUE

TP_PCIE_FW_D2R_P

PCIE_FW_R2D_C_P

FW_PME_L

ENET_CLKREQ_L

TP_PCIE_ENET_D2R_P

MAKE_BASE=TRUE

PCIE_CLK100M_ENET_P

PCIE_CLK100M_FW_N

RTL8211_ENSWREG

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.4MM MIN_NECK_WIDTH=0.2mm

DP_EXT_ML_N<0..3>

MAKE_BASE=TRUE

TP_PCIE_CLK100M_ENET_N

MAKE_BASE=TRUE

DP_IG_AUX_CH1_P

DP_IG_HPD0

DP_IG_ML1_N<0..3>

DP_AUX_CH_C_N DP_AUX_CH_C_P DP_CA_DET

TP_PCIE_ENET_R2D_C_N

MAKE_BASE=TRUE

TP_PCIE_ENET_R2D_C_P

MAKE_BASE=TRUE

TP_PCIE_ENET_D2R_N

MAKE_BASE=TRUE

DP_IG_AUX_CH_N

MAKE_BASE=TRUE

TP_DP_IG_ML1P<0..3>

TP_DP_IG_AUX_CH1P

MAKE_BASE=TRUE

DP_IG_ML0_P<0..3>

DP_IG_AUX_CH0_N

MAKE_BASE=TRUE

DP_IG_AUX_CH_P

DP_IG_AUX_CH0_P

TP_FW_PWR_EN

MAKE_BASE=TRUE

IMVP6_NTC

MAKE_BASE=TRUE

TP_IMVP6_NTC

TP_IMVP6_VR_TT

MAKE_BASE=TRUE

=CHGR_ACOK

IMVP6_VR_TT

FW_CLKREQ_L

SYNC_DATE=(02/04/2009)

SIGNAL ALIAS

SYNC_MASTER=(K84_MLB)

2.0DIA-MLB-THIN-BC-K84

ZS0920

NOSTUFF

OMIT

2.0DIA-TALL-EMI-MLB-M97-M98

ZS0919

ZS0918

OMIT

2.0DIA-MLB-THIN-BC-K84

ZS0917

OMIT

2.0DIA-MLB-THIN-BC-K84

ZS0912

2.0DIA-TALL-EMI-MLB-M97-M98

OMIT

ZS0913

2.0DIA-TALL-EMI-MLB-M97-M98

OMIT OMIT

ZS0914

2.0DIA-TALL-EMI-MLB-M97-M98

ZS0915

2.0DIA-TALL-EMI-MLB-M97-M98

OMIT

ZS0916

2.0DIA-MLB-THIN-BC-K84

OMIT

Z0905

OMIT

3P2R2P7

Z0913

OMIT

3P2R2P7

ZS0911

2.0DIA-MED-EMI-MLB-K84

OMIT

ZS0909

2.0DIA-MED-EMI-MLB-K84

OMIT

ZS0908

2.0DIA-MED-EMI-MLB-K84

OMIT

ZS0903

2.0DIA-MED-EMI-MLB-K84

OMIT

ZS0902

OMIT

2.0DIA-MED-EMI-MLB-K84

OMIT

ZS0901

2.0DIA-MED-EMI-MLB-K84

ZS0900

2.0DIA-MED-EMI-MLB-K84

OMIT

ZS0910

OMIT

2.0DIA-TALL-EMI-MLB-M97-M98

Z0906

OMIT

3P2R2P7

Z0907

3P2R2P7

OMIT

ZS0907

2.0DIA-TALL-EMI-MLB-M97-M98

OMIT

ZS0904

OMIT

2.0DIA-TALL-EMI-MLB-M97-M98

OMIT

ZS0906

2.0DIA-TALL-EMI-MLB-M97-M98

ZS0905

2.0DIA-TALL-EMI-MLB-M97-M98

OMIT

Z0910

3P2R2P7

OMIT

R0940

1/16W

402

100K

MF-LF

69 10 14

Z0903

STDOFF-4.5OD.98H-1.1-3.48-TH

Z0902

STDOFF-4.5OD.98H-1.1-3.48-TH

Z0904

STDOFF-4.5OD.98H-1.1-3.48-TH

Z0901

STDOFF-4.5OD.98H-1.1-3.48-TH

Z0911

OMIT

3P2R2P7

R0916

ENET1V05:EXT

402

MF-LF

1/16W

R0915

5% 1/16W MF-LF

ENET1V05:INT

402

18 63 62 61

R0970

MF-LF

1/16W

100K

402

R0958

1.47K

1/16W

MF-LF

402

C0958

0.1UF

CERM

20%

402

10V

R0957

402

1/16W

1.47K

MF-LF

71 64

66 65

75 66

71 65

75 66

68 67

71 64

55 54 36 35

9 OF 109

C.0.0

051-8561

9 OF 76

1 2

1 1

1 1 1

11 1 1

71 16

71 16 30

75 30

73 31

71 16

18 73 31

73 31

72 18

71 16

75 30

71 16

72 18

71 16

72 18

71 16

73 31

23 20 18

71 16

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

IN IN IN

OUT

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

OUT OUT

OUT

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

BI BI BI BI BI

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

BI BI BI

BI BI

BI BI BI BI BI

OUT

IN IN IN IN IN

IN IN

OUT

IN IN

OUT

BI BI BI BI

TEST7

TEST6

DSTBP1* DINV1*

D31*

D30*

D25*

D11* D12* D13* D14*

DSTBP0* DINV0*

D9*

D8*

D7*

D6*

D19*

D18*

D0*

D32* D1* D2*

D5*

D16*

D20* D21* D22* D23* D24*

D26* D27* D28* D29*

DSTBN1*

GTLREF

TEST3 TEST4 TEST5

BSEL0 BSEL1 BSEL2

D33*

D34*

D35*

D36*

D37*

D38*

D39*

D40*

D41*

D42*

D43*

D44*

D45*

D46*

D47*

DSTBN2* DSTBP2*

DINV2*

D48*

D49*

D50*

D51*

D52*

D53*

D54*

D55*

D56*

D57*

D58*

D59*

D60*

D61*

D62*

D63*

DSTBN3* DSTBP3*

DINV3*

COMP0 COMP1 COMP2 COMP3

DPRSTP*

DPSLP*

DPWR*

PWRGOOD

SLP*

PSI*

D17*

D4*

D3*

DSTBN0*

D15*

D10*

TEST2

TEST1

2 OF 4

DATA GRP 3 DATA GRP 2

MISC

DATA GRP 0DATA GRP 1

LOCK*

INIT*

A20M*

A6*

A3* A4*

A14*

A16*

REQ0* REQ1* REQ2* REQ3* REQ4*

BCLK1

BCLK0

THERMTRIP*

THERMDA

PROCHOT*

DBR*

TRST*

TMS

TDO

TDI

TCK

PREQ*

PRDY*

BPM3*

BPM2*

BPM1*

BPM0*

HITM*

HIT*

TRDY*

RS2*

RS1*

RS0*

RESET*

IERR*

BR0*

DBSY*

DRDY*

DEFER*

BNR*

RSVD4

RSVD3

RSVD2

RSVD1

RSVD0

SMI*

LINT1

LINT0

STPCLK*

FERR*

ADSTB1*

A35*

A34*

A33*

A32*

A31*

A30*

A29*

A28*

A19*

A18*

A17*

ADSTB0*

A13*

A12*

BPRI*

A20* A21* A22* A23* A24*

A26* A27*

A9*

A8*

A7*

A11*

A25*

THERMDC

IGNNE*

ADS*

A10*

A15*

A5*

RSVD5 RSVD6 RSVD7 RSVD8

1 OF 4

CONTROL

THERMAL

XDP/ITP SIGNALS

H CLK

ADDR GROUP1

ICH

RESERVED

ADDR GROUP0

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

BRANCH

REVISION

DRAWING NUMBER

SIZE

SHEET

PAGE TITLE

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

345678

8 7 5 4 2 1

R1005.2: C1014.1:

R1006.1:

PLACE_NEARs:

R1022.1:

R1021.1:

R1020.1:

R1023.1:

CPU JTAG Support

54.9

1% 1/16W MF-LF

402

R1000

5% 1/16W MF-LF

402

R1002

1% 1/16W MF-LF 402

U1000.AD26:12.7 mm

R1005

2.0K

1% 1/16W MF-LF 402

U1000.AD26:12.7 mm

R1006

MF-LF

402

1/16W

54.9

U1000.Y1:12.7 mm

R1023

27.4

1% 1/16W MF-LF 402

U1000.AA1:12.7 mm

R1022

54.9

1% 1/16W MF-LF

402

U1000.U26:12.7 mm

R1021

1% MF-LF

402

1/16W

27.4

U1000.R26:12.7 mm

R1020

14 69

14 58 69

14 69

13 14 69

14 69

13 69

10 13 69

13 25

14 36 69

41 75

14 36 69

14 69

13 14 69

14 69

10 13 69

41 75

14 69

402

MF-LF

NO STUFF

1/16W

R1010

5% 1/16W MF-LF

402

NO STUFF

R1011

54.9

1% 1/16W MF-LF

402

R1001

402

MF-LF

1/16W

54.9

R1090

402

MF-LF

1/16W

54.9

R1091

402

MF-LF

1/16W

54.9

R1093

14 69

402

MF-LF

1/16W

649

R1094

5% 1/16W MF-LF 402

NO STUFF

R1012

0.1uF

402

10%

NO STUFF

U1000.AF26:12.7 mm

X5R

16V

C1014

PENRYN

OMIT

FCBGA

U1000

402

54.9

MF-LF

1/16W

PLACE_NEAR=J1300.51:12.7 mm

R1092

FCBGA

PENRYN

OMIT

U1000

SYNC_DATE=02/16/2010

SYNC_MASTER=T27_MLB

CPU FSB

FSB_D_L<16>

CPU_COMP<3>

CPU_COMP<2>

CPU_COMP<1>

FSB_D_L<63>

CPU_COMP<0>

TP_CPU_RSVD_D3

TP_CPU_RSVD_D22

TP_CPU_RSVD_D2

TP_CPU_RSVD_F6

FSB_A_L<5>

FSB_A_L<15>

FSB_A_L<10>

FSB_ADS_L

CPU_IGNNE_L

CPU_THERMD_N

FSB_A_L<25>

FSB_A_L<11>

FSB_A_L<7> FSB_A_L<8> FSB_A_L<9>

FSB_A_L<27>

FSB_A_L<26>

FSB_A_L<24>

FSB_A_L<23>

FSB_A_L<22>

FSB_A_L<21>

FSB_A_L<20>

FSB_BPRI_L

FSB_A_L<12> FSB_A_L<13>

FSB_ADSTB_L<0>

FSB_A_L<17> FSB_A_L<18> FSB_A_L<19>

FSB_A_L<28> FSB_A_L<29> FSB_A_L<30> FSB_A_L<31> FSB_A_L<32> FSB_A_L<33> FSB_A_L<34> FSB_A_L<35> FSB_ADSTB_L<1>

CPU_FERR_L

CPU_STPCLK_L CPU_INTR CPU_NMI CPU_SMI_L

TP_CPU_RSVD_M4 TP_CPU_RSVD_N5 TP_CPU_RSVD_T2 TP_CPU_RSVD_V3 TP_CPU_RSVD_B2

FSB_BNR_L

FSB_DEFER_L FSB_DRDY_L FSB_DBSY_L

FSB_BREQ0_L

FSB_CPURST_L FSB_RS_L<0> FSB_RS_L<1> FSB_RS_L<2> FSB_TRDY_L

FSB_HIT_L FSB_HITM_L

XDP_BPM_L<1> XDP_BPM_L<2> XDP_BPM_L<3> XDP_BPM_L<4>

XDP_TCK XDP_TDI XDP_TDO XDP_TMS XDP_TRST_L XDP_DBRESET_L

CPU_THERMD_P

PM_THRMTRIP_L

FSB_CLK_CPU_P

FSB_REQ_L<4>

FSB_REQ_L<3>

FSB_REQ_L<2>

FSB_REQ_L<1>

FSB_REQ_L<0>

FSB_A_L<16>

FSB_A_L<14>

FSB_A_L<4>

FSB_A_L<3>

FSB_A_L<6>

CPU_A20M_L

CPU_INIT_L

FSB_LOCK_L

FSB_D_L<10>

FSB_D_L<15> FSB_DSTB_L_N<0>

FSB_D_L<3> FSB_D_L<4>

FSB_D_L<17>

CPU_PSI_L

FSB_CPUSLP_L

CPU_PWRGD

FSB_DPWR_L

CPU_DPSLP_L

CPU_DPRSTP_L

FSB_DINV_L<3>

FSB_DSTB_L_P<3>

FSB_DSTB_L_N<3>

FSB_D_L<62>

FSB_D_L<61>

FSB_D_L<60>

FSB_D_L<59>

FSB_D_L<58>

FSB_D_L<57>

FSB_D_L<56>

FSB_D_L<55>

FSB_D_L<54>

FSB_D_L<53>

FSB_D_L<52>

FSB_D_L<51>

FSB_D_L<50>

FSB_D_L<49>

FSB_D_L<48>

FSB_DINV_L<2>

FSB_DSTB_L_P<2>

FSB_DSTB_L_N<2>

FSB_D_L<47>

FSB_D_L<46>

FSB_D_L<45>

FSB_D_L<44>

FSB_D_L<43>

FSB_D_L<42>

FSB_D_L<41>

FSB_D_L<40>

FSB_D_L<39>

FSB_D_L<38>

FSB_D_L<37>

FSB_D_L<36>

FSB_D_L<35>

FSB_D_L<34>

FSB_D_L<33>

CPU_BSEL<2>

CPU_BSEL<1>

CPU_BSEL<0>

TP_CPU_TEST5

TP_CPU_TEST3

FSB_DSTB_L_N<1>

FSB_D_L<29>

FSB_D_L<28>

FSB_D_L<27>

FSB_D_L<26>

FSB_D_L<24>

FSB_D_L<23>

FSB_D_L<22>

FSB_D_L<21>

FSB_D_L<20>

FSB_D_L<5>

FSB_D_L<2>

FSB_D_L<1>

FSB_D_L<32>

FSB_D_L<0>

FSB_D_L<18> FSB_D_L<19>

FSB_D_L<6> FSB_D_L<7> FSB_D_L<8> FSB_D_L<9>

FSB_DINV_L<0>

FSB_DSTB_L_P<0>

FSB_D_L<14>

FSB_D_L<13>

FSB_D_L<12>

FSB_D_L<11>

FSB_D_L<25>

FSB_D_L<30> FSB_D_L<31>

FSB_DINV_L<1>

FSB_DSTB_L_P<1>

TP_CPU_TEST6

TP_CPU_TEST7

CPU_IERR_L

XDP_BPM_L<5>

CPU_PROCHOT_L

XDP_TMS

XDP_TDI

CPU_GTLREF

XDP_TCK

XDP_TRST_L

CPU_TEST4

=PP1V05_S0_CPU

XDP_BPM_L<0>

FSB_CLK_CPU_N

XDP_TDO

CPU_TEST2

CPU_TEST1

10 OF 109

C.0.0

051-8561

10 OF 76

1 2

A26

M26 N24

N25

T25

P23

J23 H22 F26 K22

H26 H25

G24

K24

E23

E25

R23

P26

E22

Y22 F24 E26

G25

N22

L23 M24 L22 M23 P25

P22 T24 R24 L25

L26

AD26

C24

AF26

AF1

B22 B23 C21

AB24

V24

V26

V23

T22

U25

U23

Y25

W22

Y23

W24

W25

AA23

AA24

AB25

Y26

AA26

U22

AE24

AD24

AA21

AB22

AB21

AC26

AD20

AE22

AF23

AC25

AE21

AD21

AC22

AD23

AF22

AC23

AE25

AF24

AC20

R26

U26

AA1

D24

AE6

K25

F23

G22

J26

H23

J24

D25

C23

1 2

J4 L5

K3 H2 K2 J3 L1

A21

A22

A24

D21

C20

AB6

AB5

AB3

AA6

AC5

AC1

AC2

AC4

AD1

AD3

AD4

D20

F21

AA3

AB2

AA4

W6 U4 Y5 U1 R4

T3 W2

B25

F6 D2

D22

10 13 69

29 69

10 13 69

11 12 13

10 13 69

OUT OUT OUT OUT OUT OUT OUT

OUT

VCC

VCCP

VCCA

VID0 VID1 VID2 VID3 VID4 VID5 VID6

VCCSENSE

VSSSENSE

VCC

3 OF 4

VSS VSS

4 OF 4

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

BRANCH

REVISION

DRAWING NUMBER

SIZE

SHEET

PAGE TITLE

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

345678

8 7 5 4 2 1

(BR1#)

130 mA

(CPU INTERNAL PLL POWER 1.5V)

2500 mA (after VCC stable)

4500 mA (before VCC stable)

(CPU IO POWER 1.05V)

23 A (LV Design Target)

30.4 A (SV LFM)

41 A (SV HFM)

44 A (SV Design Target)

(CPU CORE POWER)

(Socket-P KEY)

Current numbers from Merom for Santa Rosa EMTS, doc #20905.

58 69

MF-LF 402

100

1% 1/16W

PLACE_NEAR=U1000.AE7:25.4 mm

R1101

58 69

OMIT

PENRYN

FCBGA

U1000

OMIT

PENRYN

FCBGA

U1000

100

1% 1/16W MF-LF 402

PLACE_NEAR=U1000.AF7:25.4 mm

R1100

SYNC_DATE=02/16/2010

SYNC_MASTER=T27_MLB

CPU Power & Ground

CPU_VID<6>

CPU_VID<5>

CPU_VID<4>

CPU_VID<3>

CPU_VID<2>

CPU_VID<1>

CPU_VID<0>

=PP1V5_S0_CPU

=PP1V05_S0_CPU

CPU_VCCSENSE_P

=PPVCORE_S0_CPU

CPU_VCCSENSE_N

=PPVCORE_S0_CPU

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AD15 AD17 AD18

C15

A10

A13

A17

B15 B17

B20

C17 C18

D12 D14

D18

E9 E10 E12 E13 E15 E17 E18 E20

F9 F10 F12 F14 F15

F18 F20 AA7 AA9

AA10 AA12 AA13 AA15 AA17 AA18 AA20

AB9

AC10 AB10 AB12 AB14 AB15 AB17 AB18

AB20 AB7 AC7 AC9 AC12 AC13 AC15 AC17 AC18 AD7 AD9 AD10 AD12 AD14

AE9 AE10 AE12 AE13 AE15 AE17 AE18 AE20 AF9 AF10 AF12 AF14 AF15 AF17 AF18 AF20

G21 V6 J6 K6 M6 J21 K21 M21 N21 N6 R21 R6 T21 T6 V21 W21

B26 C26

AD6 AF5 AE5 AF4 AE3 AF3 AE2

AF7

AE7

A12

A15

B14

B18

C9 C10 C12 C13

D10

D15 D17

B12

B10

A18

F17

A20

N23 N26

E19

B19

A23

D16

D11

C25

C22

A8 A11 A14 A16 A19

AF2

B11 B13 B16

B21 B24

C8 C11 C14 C16 C19

D13

D26

E11 E14 E16

E24

F8 F11 F13 F16 F19

F2 F22 F25

G1 G23 G26

H6 H21 H24

J5 J22 J25

K4 K23 K26

L21 L24

M5 M22 M25

P6 P21 P24 R2 R5 R22 R25 T1

T23 T26 U3 U6 U21 U24 V2 V5 V22 V25 W1 W4 W23 W26 Y3 Y6 Y21 Y24 AA2 AA5 AA8 AA11 AA14 AA16 AA19 AA22 AA25 AB1 AB4 AB8 AB11 AB13 AB16 AB19 AB23 AB26 AC3 AC6 AC8 AC11 AC14 AC16 AC19 AC21 AC24 AD2 AD5 AD8 AD11 AD13 AD16 AD19 AD22 AD25 AE1 AE4 AE8 AE11 AE14 AE16 AE19 AE23 AE26 A2 AF6 AF8 AF11 AF13 AF16 AF19 AF21 A25 AF25

E21

D23

D19

10 12 13

11 12

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

BRANCH

REVISION

DRAWING NUMBER

SIZE

SHEET

PAGE TITLE

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

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PAGE

NOTICE OF PROPRIETARY PROPERTY:

345678

8 7 5 4 2 1

PLACEMENT_NOTE (C1200-C1219):

4X 330UF. 20X 22UF 0805

1x 10uF, 1x 0.01uF

1x 330uF, 6x 0.1uF 0402

VCCA (CPU AVdd) DECOUPLING

VCCP (CPU I/O) DECOUPLING

CPU VCore HF and Bulk Decoupling

PLACEMENT_NOTE (C1240-C1243):

20%

CRITICAL

22UF

CERM-X5R

6.3V 805

Place inside socket cavity on secondary side.

C1206

C1260

20%

2.0V

POLY-TANT

D2T-SM2

330UF

PLACEMENT_NOTE=Place C1260 between CPU & NB.

CRITICAL

NO STUFF CRITICAL

6.3V X5R-CERM

20%

603

22UF

C1236

CRITICAL

C1235

22UF

X5R-CERM

NO STUFF

603

6.3V

20%

6.3V

20% X5R-CERM

CRITICAL

C1234

603

22UF

6.3V 603

X5R-CERM

CRITICAL

20%

22UF

C1233

CRITICAL

NO STUFF

C1231

603

X5R-CERM

6.3V

20%

22UF

CRITICAL

C1232

22UF

20%

NO STUFF

X5R-CERM 603

6.3V

CRITICAL 22UF

20% X5R-CERM

C1230

603

6.3V

NO STUFF

805

CRITICAL

CERM-X5R

6.3V

20%

Place inside socket cavity on secondary side.

22UF

C1204

C1237

20%

6.3V X5R-CERM 603

22UF

CRITICAL

22UF

805

CERM-X5R

6.3V

20%

Place inside socket cavity on secondary side.

C1216

CRITICAL

NO STUFF

CRITICAL

C1214

22UF

805

CERM-X5R

6.3V

20%

Place inside socket cavity on secondary side.

C1208

CRITICAL

22UF

805

CERM-X5R

6.3V

20%

Place inside socket cavity on secondary side.

22UF

20%

6.3V 805

C1203

Place inside socket cavity on secondary side.

CERM-X5R

CRITICAL

NO STUFF

20%

22UF

805

CERM-X5R

6.3V

Place inside socket cavity on secondary side.

C1207

CRITICAL

NO STUFF

6.3V

22UF

C1202

805

20%

Place inside socket cavity on secondary side.

CERM-X5R

CRITICALCRITICAL

22UF

20%

C1201

Place inside socket cavity on secondary side.

6.3V CERM-X5R 805

C1213

CRITICAL

22UF

805

CERM-X5R

20%

Place inside socket cavity on secondary side.

6.3V

C1212

22UF

CERM-X5R

20%

805

6.3V

Place inside socket cavity on secondary side.

CRITICAL

C1211

CRITICAL

22UF

805

CERM-X5R

6.3V

20%

Place inside socket cavity on secondary side.

NO STUFF NO STUFF

CRITICAL

22UF

805

CERM-X5R

6.3V

20%

C1219

Place inside socket cavity on secondary side.Place inside socket cavity on secondary side.

22UF

6.3V 805

20% CERM-X5R

C1200

CRITICAL

NO STUFF

20% CERM-X5R

C1210

22UF

CRITICAL

805

6.3V

Place inside socket cavity on secondary side.

C1261

20% 10V CERM 402

0.1UF

CRITICAL

805

CERM-X5R

6.3V

20%

22UF

Place inside socket cavity on secondary side.

C1205

NO STUFF

805

CERM-X5R

CRITICAL

C1209

20%

6.3V

22UF

Place inside socket cavity on secondary side.

C1215

805

22UF

6.3V

20% CERM-X5R

Place inside socket cavity on secondary side.

CRITICAL

20%

22UF

805

CERM-X5R

6.3V

C1217

CRITICAL

Place inside socket cavity on secondary side.

C1262

20% 10V CERM 402

0.1UF

C1263

20% 10V CERM 402

0.1UF

C1264

20% 10V CERM 402

0.1UF

C1265

20% 10V CERM 402

0.1UF

C1266

20% 10V CERM 402

0.1UF

CRITICAL 22UF

805

6.3V

20%

C1218

CERM-X5R

Place inside socket cavity on secondary side.

C1251

BYPASS=U1000.B26::4 mm

10% 16V CERM 402

0.01UF

C1250

20%

6.3V X5R 603

10uF

Place on secondary side.

D2T-SM

2.0V

20%

470UF-4MOHM

POLY-TANT

NO STUFF

CRITICAL

C1240

20%

Place on secondary side.

2.0V POLY-TANT D2T-SM

470UF-4MOHM

CRITICAL

C1241

CRITICAL

C1242

470UF-4MOHM

Place on secondary side.

20%

2.0V POLY-TANT D2T-SM

2.0V

20%

CRITICAL 470UF-4MOHM

POLY-TANT

Place on secondary side.

C1243

D2T-SM

CPU Decoupling

SYNC_DATE=02/16/2010

SYNC_MASTER=T27_MLB

=PP1V05_S0_CPU

=PP1V5_S0_CPU

=PPVCORE_S0_CPU

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3 2

10 11 13

BI BI

OUT

IN IN

OUT

OUT OUT

OUT

IN IN

OUT OUT OUT

OUT

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

BRANCH

REVISION

DRAWING NUMBER

SIZE

SHEET

PAGE TITLE

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

345678

8 7 5 4 2 1

Direction of XDP module

Please avoid any obstructions

ON ODD-NUMBERED SIDE OF J1300

OBSFN_C0 OBSFN_C1

OBSDATA_C0 OBSDATA_C1

OBSDATA_C2 OBSDATA_C3

OBSFN_D0 OBSFN_D1

OBSDATA_D0 OBSDATA_D1

OBSDATA_D2 OBSDATA_D3

ITPCLK/HOOK4 ITPCLK#/HOOK5 VCC_OBS_CD RESET#/HOOK6 DBR#/HOOK7 NOTE: XDP_DBRESET_L must be pulled-up to 3.3V. TDO TRSTn TDI TMS XDP_PRESENT#

TCK0

TCK1

SCL

SDA

HOOK2 HOOK3

VCC_OBS_AB

HOOK1

PWRGD/HOOK0

OBSDATA_B3

OBSDATA_B2

OBSDATA_B1

OBSDATA_B0

OBSFN_B1

OBSFN_B0

OBSDATA_A3

OBSDATA_A2

OBSDATA_A1

OBSDATA_A0

OBSFN_A1

OBSFN_A0

MCP89-SPECIFIC PINOUT

Mini-XDP Connector

USE WITH 920-0782 ADAPTER FLEX TO SUPPORT CPU, MCP DEBUGGING.

NOTE: This is not the standard XDP pinout.

518S0774

10 14 69

1/16W

402

MF-LF

XDP

R1399

19 38 72

1/16W

402

MF-LF

54.9

XDP

R1315

16V

10%

402

X5R

0.1uF

XDP

C1300

16V

10%

402

X5R

0.1uF

XDP

C1301

10 69

10 14 69

PLACE_NEAR=U1000.C1:5 MM

1/16W

402

MF-LF

XDP

R1303

10 69

14 69

10 69

10 25

10 69

XDP_CON

CRITICAL

F-ST-SM-HF

DF40C-60DS-0.4V

J1300

SYNC_MASTER=(K84_MLB)

eXtended Debug Port(MiniXDP)

SYNC_DATE=(02/25/2009)

TP_XDP_OBSDATA_C2 TP_XDP_OBSDATA_C3

PM_LATRIGGER_L JTAG_MCP_TCK

=PP1V05_S0_CPU

XDP_OBS20

XDP_BPM_L<1>

XDP_CPURST_L

XDP_TDO

XDP_TDI XDP_TMS

XDP_BPM_L<5>

TP_XDP_OBSDATA_B0

TP_XDP_OBSDATA_B2

XDP_TCK

SMBUS_MCP_0_CLK

XDP_BPM_L<4>

XDP_BPM_L<2>

XDP_BPM_L<3>

XDP_BPM_L<0>

TP_XDP_OBSFN_B1

TP_XDP_OBSFN_B0

TP_XDP_OBSDATA_B1

TP_XDP_OBSDATA_B3

XDP_PWRGD

SMBUS_MCP_0_DATA

TP_XDP_OBSDATA_D3

TP_XDP_OBSDATA_D0

JTAG_MCP_TMS

JTAG_MCP_TDI

TP_XDP_OBSDATA_C0 TP_XDP_OBSDATA_C1

JTAG_MCP_TRST_L

JTAG_MCP_TDO

XDP_TRST_L

XDP_DBRESET_L

CPU_PWRGD

FSB_CPURST_L

FSB_CLK_ITP_P

TP_XDP_OBSDATA_D1

TP_XDP_OBSDATA_D2

FSB_CLK_ITP_N

=PP3V3_S0_XDP

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1 2

19 21

25 27 29

41 43 45 47 49 51 53

38 40

32 34

16 18 20

6 8

2 4

56 58 60

10 11 12

IN IN IN

OUT

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

BI BI BI

BI BI

IN BI

OUT OUT OUT

OUT OUT

OUT OUT OUT OUT OUT OUT

OUT

OUT OUT OUT OUT OUT

OUT OUT

BI BI

CPU_A18*

CPU_D35*

CPU_D37*

CPU_A10*

CPU_A9*

CPU_D48*

CPU_A16*

CPU_D33*

CPU_RS2*

CPU_RS1*

CPU_RS0*

CPU_BSEL2 CPU_BSEL1

CPU_THERMTRIP*

CPU_PECI CPU_PROCHOT*

CPU_DBSY*

CPU_ADSTB1*

CPU_REQ1*

CPU_REQ4*

CPU_BR0*

CPU_BNR*

CPU_ADS*

CPU_REQ2* CPU_REQ3*

CPU_REQ0*

CPU_ADSTB0*

CPU_A31* CPU_A32*

CPU_A30*

CPU_A28*

CPU_A26* CPU_A27*

CPU_A23* CPU_A24* CPU_A25*

CPU_A21* CPU_A22*

CPU_A19* CPU_A20*

CPU_A13* CPU_A14*

CPU_A12*

CPU_A11*

CPU_A8*

CPU_A5* CPU_A6* CPU_A7*

CPU_A3* CPU_A4*

CPU_DSTBN0* CPU_DBI0*

CPU_DSTBP1* CPU_DSTBN1* CPU_DBI1*

CPU_DSTBP2* CPU_DSTBN2* CPU_DBI2*

CPU_DSTBP3* CPU_DSTBN3* CPU_DBI3*

CPU_BSEL0

CPU_COMP_GND

BCLK_VML_COMP_VDD

CPU_COMP_VCC

BCLK_VML_COMP_GND

CPU_D1* CPU_D2* CPU_D3* CPU_D4* CPU_D5* CPU_D6*

CPU_D9*

CPU_D11* CPU_D12* CPU_D13* CPU_D14* CPU_D15* CPU_D16* CPU_D17* CPU_D18* CPU_D19* CPU_D20* CPU_D21* CPU_D22* CPU_D23* CPU_D24* CPU_D25* CPU_D26* CPU_D27* CPU_D28* CPU_D29* CPU_D30* CPU_D31* CPU_D32*

CPU_D34*

CPU_D36*

CPU_D38* CPU_D39* CPU_D40* CPU_D41* CPU_D42*

CPU_D45* CPU_D46* CPU_D47*

CPU_D49* CPU_D50* CPU_D51* CPU_D52* CPU_D53* CPU_D54* CPU_D55* CPU_D56* CPU_D57* CPU_D58* CPU_D59* CPU_D60* CPU_D61* CPU_D62* CPU_D63*

CPU_A20M*

CPU_IGNNE*

CPU_INIT*

CPU_INTR

CPU_NMI

CPU_SMI*

CPU_PWRGD

CPU_RESET*

CPU_DPRSLPVR

CPU_SLP*

CPU_D10*

CPU_D8*

CPU_D7*

CPU_A33* CPU_A34* CPU_A35*

CPU_D44*

CPU_D43*

CPU_DSTBP0*

CPU_TRDY*

CPU_LOCK*

CPU_HIT*

CPU_DRDY*

CPU_HITM*

CPU_DPRSTP*

CPU_D0*

CPU_DPSLP*

CPU_DPWR*

CPU_STPCLK*

CPU_A15*

CPU_A17*

CPU_A29*

CPU_BPRI*

CPU_DEFER*

CPU_FERR*

BCLK_OUT_CPU_P

BCLK_OUT_CPU_N

BCLK_OUT_ITP_P

BCLK_OUT_ITP_N

BCLK_OUT_NB_N

BCLK_IN_N

BCLK_IN_P

BCLK_OUT_NB_P

(1 OF 11)

FSB

OUT

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

BRANCH

REVISION

DRAWING NUMBER

SIZE

SHEET

PAGE TITLE

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

345678

8 7 5 4 2 1

Loop-back clock for delay matching.

10 69

10 13 69

10 69

13 69

10 69

10 13 69

10 69

10 58 69

10 36 69

10 69

49.9

402

MF-LF

1/16W

R1436

1/16W

402

MF-LF

49.9

R1431

49.9

MF-LF

402

1/16W

R1430

49.9

1/16W

1% MF-LF

402

R1435

1/16W 402

MF-LF

R1415

1/16W

402

MF-LF

54.9

R1410

5% MF-LF

402

NO STUFF

1/16W

150

R1440

OMIT

MCP89M-A01

FBGA

U1400

58 69

10 69

SYNC_DATE=02/16/2010

SYNC_MASTER=T27_MLB

MCP CPU Interface

=PP1V05_S0_MCP_FSB

FSB_CLK_MCP_P

FSB_CLK_MCP_N

FSB_CLK_ITP_N FSB_CLK_ITP_P

FSB_CLK_CPU_N FSB_CLK_CPU_P

CPU_FERR_L

FSB_DEFER_L

FSB_BPRI_L

FSB_A_L<29>

FSB_A_L<17>

FSB_A_L<15>

CPU_STPCLK_L

FSB_DPWR_L

CPU_DPSLP_L

FSB_D_L<0>

CPU_DPRSTP_L

FSB_HITM_L

FSB_DRDY_L FSB_HIT_L

FSB_LOCK_L FSB_TRDY_L

FSB_DSTB_L_P<0>

FSB_D_L<43> FSB_D_L<44>

FSB_A_L<35>

FSB_A_L<34>

FSB_A_L<33>

FSB_D_L<7> FSB_D_L<8>

FSB_D_L<10>

FSB_CPUSLP_L

PM_DPRSLPVR

FSB_CPURST_L

CPU_PWRGD

CPU_SMI_L

CPU_NMI

CPU_INTR

CPU_INIT_L

CPU_IGNNE_L

CPU_A20M_L

FSB_D_L<63>

FSB_D_L<62>

FSB_D_L<61>

FSB_D_L<60>

FSB_D_L<59>

FSB_D_L<58>

FSB_D_L<57>

FSB_D_L<56>

FSB_D_L<55>

FSB_D_L<54>

FSB_D_L<53>

FSB_D_L<52>

FSB_D_L<51>

FSB_D_L<50>

FSB_D_L<49>

FSB_D_L<47>

FSB_D_L<46>

FSB_D_L<45>

FSB_D_L<42>

FSB_D_L<41>

FSB_D_L<40>

FSB_D_L<39>

FSB_D_L<38>

FSB_D_L<36>

FSB_D_L<34>

FSB_D_L<32>

FSB_D_L<31>

FSB_D_L<30>

FSB_D_L<29>

FSB_D_L<28>

FSB_D_L<27>

FSB_D_L<26>

FSB_D_L<25>

FSB_D_L<24>

FSB_D_L<23>

FSB_D_L<22>

FSB_D_L<21>

FSB_D_L<20>

FSB_D_L<19>

FSB_D_L<18>

FSB_D_L<17>

FSB_D_L<16>

FSB_D_L<15>

FSB_D_L<14>

FSB_D_L<13>

FSB_D_L<12>

FSB_D_L<11>

FSB_D_L<9>

FSB_D_L<6>

FSB_D_L<5>

FSB_D_L<4>

FSB_D_L<3>

FSB_D_L<2>

FSB_D_L<1>

MCP_BCLK_VML_COMP_GND

MCP_CPU_COMP_VCC

MCP_BCLK_VML_COMP_VDD

MCP_CPU_COMP_GND

=MCP_BSEL<0>

FSB_DINV_L<3>

FSB_DSTB_L_N<3>

FSB_DSTB_L_P<3>

FSB_DINV_L<2>

FSB_DSTB_L_N<2>

FSB_DSTB_L_P<2>

FSB_DINV_L<1>

FSB_DSTB_L_N<1>

FSB_DSTB_L_P<1>

FSB_DINV_L<0>

FSB_DSTB_L_N<0>

FSB_A_L<4>

FSB_A_L<3>

FSB_A_L<7>

FSB_A_L<6>

FSB_A_L<5>

FSB_A_L<8>

FSB_A_L<11> FSB_A_L<12>

FSB_A_L<14>

FSB_A_L<13>

FSB_A_L<20>

FSB_A_L<19>

FSB_A_L<22>

FSB_A_L<21>

FSB_A_L<25>

FSB_A_L<24>

FSB_A_L<23>

FSB_A_L<27>

FSB_A_L<26>

FSB_A_L<28>

FSB_A_L<30>

FSB_A_L<32>

FSB_A_L<31>

FSB_ADSTB_L<0>

FSB_REQ_L<0>

FSB_REQ_L<3>

FSB_REQ_L<2>

FSB_ADS_L FSB_BNR_L FSB_BREQ0_L

FSB_REQ_L<4>

FSB_REQ_L<1>

FSB_ADSTB_L<1>

FSB_DBSY_L

CPU_PROCHOT_L

CPU_PECI_MCP

PM_THRMTRIP_L

=MCP_BSEL<1>

=MCP_BSEL<2>

FSB_RS_L<0> FSB_RS_L<1> FSB_RS_L<2>

FSB_D_L<33>

FSB_A_L<16>

FSB_D_L<48>

FSB_A_L<9> FSB_A_L<10>

FSB_D_L<37>

FSB_D_L<35>

FSB_A_L<18>

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121

AB35

L31

P32

Y38

T37

C37

Y35

G34

AC31

AC33

AB29

B34 C34

W33

AH34

U28

AE29

AB34

T36

T35

AE30

AE32

AE31

U37 T38

U36

W36

AC35 AE37

AC37

AE36

AB37 AC34

AC38 AB36 AB38

AC36 AF36

Y34

AE38

U33 W34

Y36

W35

W38

U35 T34 W37

U38 U34

K35 L37

T31 T30 P28

K33 K32 N35

C36 D36 A35

A34

AH35

AH37

AH36

AH38

N36 P36 L36 N34 L35 P37

L34

K36 K38 N37 H37 L38 N28 U30 N29 P34 T29 T32 U32 T33 P31 P30 N30 P33 N31 T28 P35 P29 H33

L30

L33

N32 N33 H35 K31 H34

G33 H32 G35

D37 H38 G38 G37 G36 B35 E35 B36 E36 C35 D34 E38 D38 E34 E37

W30 AB30 AB28 W31 AC30 AC28 Y32 AE28 G1 Y33

K37

H36

P38

AE35 AE33 AE34

L32

K30

K34

AC29

AC32

W32

U29

AB31

W29

N38

AB33 U31 Y29

Y37

AF38

AF37

Y31 Y30

AB32

AF33

AF32

AF34

AF35

AF28

AF31

AF30

AF29

14 20 23

OUT

OUT OUT OUT OUT OUT OUT

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

OUT OUT OUT

OUT OUT

BI BI

BI BI BI BI

BI BI

BI BI BI

BI BI BI BI BI BI

OUT OUT OUT

OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT

OUT OUT

BI BI BI

BI BI BI BI BI BI

BI BI BI

BI BI BI BI BI BI

OUT

OUT OUT OUT OUT OUT OUT OUT

OUT OUT

MDQS0_7_P

MDQS0_6_N

MDQS0_6_P

MDQS0_7_N

MDQS0_5_N

MDQS0_5_P

MDQS0_4_P MDQS0_4_N MDQS0_3_P

MDQS0_2_P MDQS0_2_N MDQS0_1_P MDQS0_1_N MDQS0_0_P MDQS0_0_N

MRAS0* MCAS0*

MWE0*

MBA0_2 MBA0_1 MBA0_0

MA0_14

MA0_15

MA0_13 MA0_12 MA0_11

MA0_9

MA0_10

MA0_8 MA0_7 MA0_6

MA0_3

MA0_4

MA0_1

MA0_2

MA0_0

+VIO_M2CLK_DLL_1 +VIO_M2CLK_DLL_2

+VIO_PLL_MEM_2

+VIO_PLL_MEM_1

+VIO_PLL_FSB_1 +VIO_PLL_FSB_2

MCLK0A_1_P MCLK0A_1_N

MCLK0A_0_P MCLK0A_0_N

MCS0A_1* MCS0A_0*

MODT0A_0

MODT0A_1

MCKE0A_1 MCKE0A_0

MDQ0_63 MDQ0_62 MDQ0_61

MDQ0_58

MDQ0_59

MDQ0_55

MDQ0_57 MDQ0_56

MDQ0_53

MDQ0_54

MDQ0_50

MDQ0_52 MDQ0_51

MDQ0_48

MDQ0_49

MDQ0_45

MDQ0_46

MDQ0_47

MDQ0_43

MDQ0_44

MDQ0_41 MDQ0_40 MDQ0_39

MDQ0_37

MDQ0_38

MDQ0_36 MDQ0_35 MDQ0_34 MDQ0_33 MDQ0_32 MDQ0_31 MDQ0_30 MDQ0_29

MDQ0_27

MDQ0_28

MDQ0_26 MDQ0_25 MDQ0_24

MDQ0_22

MDQ0_23

MDQ0_19

MDQ0_21 MDQ0_20

MDQ0_17

MDQ0_18

MDQ0_16

MDQ0_14

MDQ0_15

MDQ0_12

MDQ0_13

MDQ0_11 MDQ0_10 MDQ0_9 MDQ0_8 MDQ0_7

MDQ0_5

MDQ0_6

MDQ0_4

MDQ0_2

MDQ0_3

MDQ0_1 MDQ0_0

MDQM0_7 MDQM0_6 MDQM0_5 MDQM0_4

MDQM0_2

MDQM0_3

MDQM0_0

MDQM0_1

MDQ0_42

MA0_5

+VIO_PLL_CPU_4

+VIO_PLL_CPU_3

+VIO_PLL_CPU_2

+VIO_PLL_CPU_1

MDQS0_3_N

MDQ0_60

MEMORY PARTITION 0

(2 OF 11)

MDQ1_51

MDQ1_13

MDQ1_25

MDQ1_39

MEM_COMP_VDD

MEM_COMP_GND

MDQM1_1

MDQ1_44 MDQ1_43 MDQ1_42 MDQ1_41 MDQ1_40

MDQ1_38

MDQ1_10

MDQ1_16

MDQ1_14

MDQ1_3 MDQ1_2 MDQ1_1

MDQM1_2

MDQM1_3

MDQM1_4

MDQM1_5

MDQM1_6

MDQM1_7

MDQS1_6_N

MDQS1_7_N

MDQS1_7_P

MDQ1_0

MDQ1_4

MDQ1_5

MDQ1_6

MDQ1_7

MDQ1_8

MDQ1_9

MDQ1_11

MDQ1_12

MDQ1_15

MDQ1_17

MDQ1_18

MDQ1_21

MDQ1_22

MDQ1_23

MDQ1_24

MDQ1_26

MDQ1_27

MDQ1_28

MDQ1_29

MDQ1_30

MDQ1_31

MDQ1_32

MDQ1_33

MDQ1_34

MDQ1_35

MDQ1_36

MDQ1_37

MDQ1_46

MDQ1_47

MDQ1_48

MDQ1_52

MDQ1_53

MDQ1_54

MDQ1_56

MDQ1_57

MDQ1_58

MDQ1_59

MDQ1_60

MDQ1_61

MDQ1_62

MDQ1_49

MDQS1_6_P

MDQ1_63

MDQ1_50

MDQM1_0

MDQ1_45

MDQ1_55

MDQS1_5_P MDQS1_5_N MDQS1_4_P MDQS1_4_N MDQS1_3_P MDQS1_3_N MDQS1_2_P MDQS1_2_N MDQS1_1_P MDQS1_1_N

MDQS1_0_N

MDQS1_0_P

MRAS1* MCAS1*

MWE1*

MBA1_2 MBA1_1 MBA1_0

MA1_15 MA1_14 MA1_13 MA1_12 MA1_11 MA1_10

MA1_9 MA1_8 MA1_7 MA1_6

MA1_4

MA1_5

MA1_3

MRESET0*

MCLK1A_1_P MCLK1A_1_N

MCLK1A_0_P MCLK1A_0_N

MCS1A_1* MCS1A_0*

MODT1A_1 MODT1A_0

MCKE1A_1 MCKE1A_0

MA1_1 MA1_0

MA1_2

MDQ1_19

MDQ1_20

MEMORY PARTITION 1

(3 OF 11)

OUT OUT

OUT

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

BRANCH

REVISION

DRAWING NUMBER

SIZE

SHEET

PAGE TITLE

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

345678

8 7 5 4 2 1

Current numbers from MCP89 A01 Bring-Up Support document (MCP89_TDP_EDP_Bringup_Targets_Apple.pdf, dated August 5, 2009). K6/K69 EDP currents used.

20 mA

25 mA

70 mA

550 mA

28 70

26 70

21 26 70

28 70

27 70

28 70

26 70 27 70

21 27 70

OMIT

FBGA

MCP89M-A01

U1400

OMIT

MCP89M-A01

FBGA

U1400

27 70

26 27

402

1/16W MF-LF

R1520

402

1/16W

40.2

MF-LF

R1511

MF-LF

402

1/16W

40.2

R1510

SYNC_DATE=02/16/2010

SYNC_MASTER=T27_MLB

MCP Memory Interface

MEM_A_A<8>

=PP1V5R1V35_SW_MCP_MEM

MEM_A_A<3>

MEM_B_DQ<15>

MEM_A_A<9>

MEM_A_A<11>

MEM_A_A<0>

=PP1V5R1V35_S3_MCP_MEM

MEM_A_DQS_N<5> MEM_A_DQS_P<4>

MEM_A_DQS_P<2> MEM_A_DQS_N<2>

MEM_A_DQ<62>

MEM_A_DQ<59>

MEM_A_DQ<60>

MEM_A_DQ<61>

MEM_A_DQ<58> MEM_A_DQ<57>

MEM_A_DQ<54>

MEM_A_DQ<55>

MEM_A_DQ<56>

MEM_A_DQ<52>

MEM_A_DQ<53>

MEM_A_DQ<49>

MEM_A_DQ<50>

MEM_A_DQ<51>

MEM_A_DQ<48> MEM_A_DQ<47> MEM_A_DQ<46> MEM_A_DQ<45> MEM_A_DQ<44>

MEM_A_DQ<42>

MEM_A_DQ<43>

MEM_A_DQ<41> MEM_A_DQ<40>

MEM_A_DQ<36>

MEM_A_DQ<37>

MEM_A_DQ<38>

MEM_A_DQ<35> MEM_A_DQ<34> MEM_A_DQ<33> MEM_A_DQ<32>

MEM_A_DQ<30> MEM_A_DQ<29>

MEM_A_DQ<27> MEM_A_DQ<26>

MEM_A_DQ<28>

MEM_A_DQ<24>

MEM_A_DQ<25>

MEM_A_DQ<23>

MEM_A_DQ<21>

MEM_A_DQ<22>

MEM_A_DQ<18>

MEM_A_DQ<19>

MEM_A_DQ<20>

MEM_A_DQ<16>

MEM_A_DQ<17>

MEM_A_DQ<14> MEM_A_DQ<13>

MEM_A_DQ<15>

MEM_A_DQ<12> MEM_A_DQ<11>

MEM_A_DQ<8>

MEM_A_DQ<6>

MEM_A_DQ<7>

MEM_A_DQ<5> MEM_A_DQ<4> MEM_A_DQ<3>

MEM_A_DQ<1>

MEM_A_DQ<2>

MEM_A_DQ<0> MEM_A_DM<7>

MEM_A_DM<6>

MEM_A_DM<4>

MEM_A_DM<5>

MEM_A_DM<1>

MEM_A_DM<2>

MEM_A_DM<3>

MEM_A_DM<0>

MEM_A_DQ<63>

MEM_A_DQ<10> MEM_A_DQ<9>

MEM_A_DQ<31>

MEM_A_CKE<1> MEM_A_CKE<0>

MEM_A_ODT<1> MEM_A_ODT<0>

MEM_A_CS_L<0>

MEM_A_CS_L<1>

MEM_A_CLK_N<0>

MEM_A_CLK_P<0>

MEM_A_CLK_N<1>

MEM_A_CLK_P<1>

MEM_A_A<1>

MEM_A_A<2>

MEM_A_A<4>

MEM_A_A<10>

MEM_A_A<12>

MEM_A_A<14>

MEM_A_A<15>

MEM_A_A<13>

MEM_A_BA<0>

MEM_A_BA<2> MEM_A_BA<1>

MEM_A_CAS_L

MEM_A_RAS_L

MEM_A_DQS_P<0> MEM_A_DQS_N<0>

MEM_A_DQS_P<1> MEM_A_DQS_N<1>

MEM_A_DQS_N<3>

MEM_A_DQS_N<4> MEM_A_DQS_P<3>

MEM_A_DQS_P<5>

MEM_A_DQS_P<6>

MEM_A_DQS_N<7>

MEM_A_DQS_P<7>

MEM_B_DQS_P<6>

MEM_B_DQ<49>

MEM_B_DQ<63> MEM_B_DQ<62> MEM_B_DQ<61> MEM_B_DQ<60> MEM_B_DQ<59> MEM_B_DQ<58> MEM_B_DQ<57> MEM_B_DQ<56> MEM_B_DQ<55> MEM_B_DQ<54> MEM_B_DQ<53> MEM_B_DQ<52>

MEM_B_DQ<50>

MEM_B_DQ<48> MEM_B_DQ<47> MEM_B_DQ<46>

MEM_B_DQ<37> MEM_B_DQ<36> MEM_B_DQ<35> MEM_B_DQ<34> MEM_B_DQ<33> MEM_B_DQ<32> MEM_B_DQ<31> MEM_B_DQ<30>

MEM_B_DQ<28>

MEM_B_DQ<26>

MEM_B_DQ<24> MEM_B_DQ<23> MEM_B_DQ<22> MEM_B_DQ<21>

MEM_B_DQ<18> MEM_B_DQ<17>

MEM_B_DQ<12> MEM_B_DQ<11>

MEM_B_DQ<8> MEM_B_DQ<7> MEM_B_DQ<6> MEM_B_DQ<5> MEM_B_DQ<4>

MEM_B_DQ<0>

MEM_B_DQS_P<7> MEM_B_DQS_N<7>

MEM_B_DQS_N<6> MEM_B_DQS_P<5> MEM_B_DQS_N<5> MEM_B_DQS_P<4> MEM_B_DQS_N<4> MEM_B_DQS_P<3> MEM_B_DQS_N<3> MEM_B_DQS_P<2> MEM_B_DQS_N<2> MEM_B_DQS_P<1> MEM_B_DQS_N<1> MEM_B_DQS_P<0> MEM_B_DQS_N<0>

MEM_B_CLK_N<0>

MEM_B_CS_L<0>

MEM_B_ODT<1> MEM_B_ODT<0>

MEM_B_CKE<1> MEM_B_CKE<0>

MEM_B_DM<7> MEM_B_DM<6> MEM_B_DM<5> MEM_B_DM<4> MEM_B_DM<3> MEM_B_DM<2>

MEM_B_DQ<1>

MEM_B_DQ<2>

MEM_B_DQ<3>

MEM_B_DQ<14>

MEM_B_DQ<16>

MEM_B_DQ<19>

MEM_B_DQ<20>

MEM_B_DQ<10>

MEM_B_A<15> MEM_B_A<14> MEM_B_A<13> MEM_B_A<12> MEM_B_A<11> MEM_B_A<10> MEM_B_A<9> MEM_B_A<8> MEM_B_A<7> MEM_B_A<6> MEM_B_A<5> MEM_B_A<4> MEM_B_A<3> MEM_B_A<2> MEM_B_A<1> MEM_B_A<0>

MEM_B_RAS_L MEM_B_CAS_L MEM_B_WE_L

MEM_B_BA<2> MEM_B_BA<1> MEM_B_BA<0>

MEM_B_DQ<38>

MEM_B_DQ<40>

MEM_B_DQ<41>

MEM_B_DQ<42>

MEM_B_DQ<43>

MEM_B_DQ<44>

MEM_B_DQ<45>

MEM_B_DM<0>

MEM_B_DM<1>

MCP_MEM_COMP_GND MCP_MEM_COMP_VDD

MEM_B_DQ<39>

MEM_B_DQ<25>

MEM_B_CS_L<1>

MEM_B_DQ<13>

MEM_B_DQ<51>

MEM_B_CLK_P<0>

MEM_B_CLK_N<1>

MEM_B_CLK_P<1>

MEM_RESET_L

MEM_A_WE_L

MEM_A_DQ<39>

MEM_B_DQ<27>

MEM_A_A<6> MEM_A_A<5>

MEM_B_DQ<29>

MEM_B_DQ<9>

=PP1V05_S0_MCP_M2CLK_DLL

PP1V05_S0_MCP_PLL_FSBMEM

MEM_A_A<7>

MEM_A_DQS_N<6>

15 OF 109

C.0.0

051-8561

15 OF 76

AN7

AM10

AN10

AM7

AM13

AN13

AL16 AK16 AH28

AM29 AN29 AP34 AP35 AH31 AG31

AN19 AL19 AL20

AL25 AN20 AM19

AK25

AK26

AJ20 AJ26 AH25

AH26

AM20

AN23 AJ25 AM22

AL23

AN22

AK23

AK22

AL22

AF24 AG25

AG26

AF25

AF26 AG28

AH23 AJ23

AJ22 AH22

AH19 AK20

AK19

AH20

AL26 AN25

AP5 AP7 AR8

AR5

AR4

AK11

AM8 AN8

AH13

AL11

AK10

AH14 AL10

AJ13

AN11

AJ16

AK14

AK13

AJ14

AH16

AM14 AN14 AK17

AN17

AL17

AJ19 AH17 AJ17 AM16 AM17 AN26 AH29 AK29

AM25

AL29

AM26 AL28 AK28

AP29

AM28

AP28

AL31 AN32

AN31

AN28

AM31

AM32

AR34

AL35

AL33

AP32 AP33 AM35 AL32 AJ35

AH32

AJ31

AH33

AL34

AJ34

AJ33 AJ32

AR7 AM11 AL14 AN16

AP31

AJ29

AJ30

AM34

AL13

AM23

AF27

AE26

AD26

AC26

AJ28

AP8

AV5

AR37

AV28

AV14

AG22

AG23

AT37

AR14 AR11 AP11 AT11 AP13

AU14

AU35

AT32

AT35

AP37 AP36 AJ38

AV32

AR28

AT14

AV10

AU7

AT2

AV8

AR1

AR2

AJ37

AL36

AJ36

AM37

AM36

AR38

AR36

AV34

AP38

AV35

AU32

AR31

AT34

AR32

AT31

AV29

AV26

AV25

AT29

AU29

AT26

AU26

AR16

AP16

AT13

AP14

AP17

AR17

AU10

AT10

AT8

AR10

AU8

AT7

AT4

AU3

AP2

AP3

AU4

AV4

AR3

AP10

AV7

AP1

AU5

AM38

AR13

AT5

AU11 AV11 AU13 AV13 AT28 AU28 AU31 AV31 AU36 AT36

AL37

AL38

AR19 AU17 AT17

AR25 AT19 AR20

AP26 AR26 AV16 AP25 AT23 AP20 AU23 AV22 AV23 AT22

AP23

AU22

AR23

AP4

AU20 AV20

AU19 AV19

AU16 AP19

AT16 AV17

AU25 AT25

AR22 AT20

AP22

AR29

AU34

20 21 23

IN IN

OUT OUT

OUT

OUT OUT

OUT

PE0_REFCLK_P PE0_REFCLK_N

PE1_REFCLK_P

PE2_REFCLK_P

PE1_REFCLK_N

PE3_REFCLK_P

PE2_REFCLK_N

PE4_REFCLK_P

PE3_REFCLK_N

PE5_REFCLK_P

PE4_REFCLK_N

PE5_REFCLK_N

PE0_TX0_P PE0_TX0_N

PE0_TX1_P PE0_TX1_N

PE0_TX2_P

PE0_TX3_P

PE0_TX2_N

PE0_TX4_P

PE0_TX3_N

PE0_TX5_P

PE0_TX4_N

PE0_TX5_N

PE1_TX0_N

PE1_TX0_P

PE1_TX1_P PE1_TX1_N

PEX_RST*

PEX0_TERM_P

PEA_CLKREQ*/GPIO_49

PEB_CLKREQ*/GPIO_50

PEC_CLKREQ*/GPIO_51

PEE_CLKREQ*/GPIO_53

PED_CLKREQ*/GPIO_52

PEF_CLKREQ*/GPIO_54

PE_WAKE*

PE0_RX0_P PE0_RX0_N

PE0_RX1_P PE0_RX1_N

PE0_RX3_P

PE0_RX4_P

PE0_RX3_N

PE0_RX4_N

PE0_RX5_P PE0_RX5_N

PE1_RX0_P PE1_RX0_N

PE1_RX1_N

PE1_RX1_P

+3.3V_PLL_HVDD_1 +3.3V_PLL_HVDD_2

+VIO_PLL_PE

+VIO_PLL_XREF_XS_1 +VIO_PLL_XREF_XS_2

+VIO_PLL_SATA_1

+VIO_PLL_XREF_XS_3

+VIO_PLL_SATA_2

+VIO_PLL_H

PE0_RX2_N

PE0_RX2_P

PCI EXPRESS

(4 OF 11)

OUT

OUT OUT

IN IN

OUT OUT

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

BRANCH

REVISION

DRAWING NUMBER

SIZE

SHEET

PAGE TITLE

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

345678

8 7 5 4 2 1

(IPU)

PE1 ports are Gen1-only. 2 RCs: x1, x1

PE0 ports are Gen2-capable. 4 RCs: 4x, x2, x1, x1

+VIO_PE_AVDD1 and +VIO_PE_DVDD1 can be GND

If PE0[3:0] are not used, +VIO_PE_AVDD0 and +VIO_PE_DVDD0 can be GND

If PE0[4:5] and PE1[0:1] are not used,

(IPU-S5)

50 mA

100 mA

120 mA

25 mA

80 mA

325 mA

Current numbers from MCP89 A01 Bring-Up Support document (MCP89_TDP_EDP_Bringup_Targets_Apple.pdf, dated August 5, 2009). K6/K69 EDP currents used.

(IPU)

(IPD)

PLACE_NEAR=U1400.U2:12.7 mm

402

MF-LF

1/16W

2.49K

R1610

FBGA

MCP89M-A01

OMIT

U1400

1/16W MF-LF 402

10K

NO STUFF

R1600

MCP PCIe Interfaces

SYNC_MASTER=T27_MLB

SYNC_DATE=02/16/2010

PCIE_ENET_R2D_C_N

PCIE_CLK100M_ENET_P

PCIE_CLK100M_AP_P

FW_PWR_EN

PCIE_CLK100M_FW_N

=PEG_R2D_C_P<3>

=PEG_R2D_C_N<0>

ENET_CLKREQ_L

=PEG_R2D_C_N<1>

=PEG_R2D_C_N<3>

=PEG_R2D_C_N<2>

PP1V05_S0_MCP_PLL_PEXSATA

PCIE_AP_D2R_N

TP_PCIE_CLK100M_PE4P

PCIE_AP_D2R_P

FW_PME_L

PCIE_FW_R2D_C_P

PCIE_FW_D2R_N

AP_CLKREQ_L

PEG_CLK100M_N

PEG_CLK100M_P

TP_PCIE_PE4_R2D_CN

PCIE_ENET_R2D_C_P

TP_PCIE_PE4_R2D_CP

PCIE_AP_R2D_C_N

PEG_CLKREQ_L

=PEG_D2R_P<0> =PEG_D2R_N<0>

=PEG_D2R_P<1> =PEG_D2R_N<1>

=PEG_D2R_P<2>

TP_PCIE_PE4_D2RN

PCIE_ENET_D2R_P

PCIE_CLK100M_FW_P

TP_PCIE_CLK100M_PE5P

=PEG_R2D_C_P<2>

PCIE_AP_R2D_C_P

MCP_PEX0_TERMP

FW_CLKREQ_L

TP_PCIE_CLK100M_PE4N

=PEG_R2D_C_P<0>

PCIE_WAKE_L

PCIE_FW_D2R_P

PCIE_ENET_D2R_N PP3V3_S0_MCP_PLL_HVDD

=PEG_R2D_C_P<1>

TP_PCIE_CLK100M_PE5N

PCIE_CLK100M_AP_N

PCIE_RESET_L

PCIE_CLK100M_ENET_N

PCIE_FW_R2D_C_N

TP_PCIE_PE4_D2RP

=PEG_D2R_N<3>

=PEG_D2R_P<3>

=PEG_D2R_N<2>

16 OF 109

C.0.0

051-8561

16 OF 76

Y1 W1

W10

W11

AC3 AC2

AB2 AB3

AC6

AC8

AC7

AB4

AC9

AB5

Y9 Y8

AC1 AB1

AC5 AC4

AB7

AB9

AB6

AB8

Y2 Y3

AB11 AB10

Y11

Y10

V11 V13

AH10

AG11 AF12

AH8

AF13

AH9

AH11

AC11

AC10

OUT

FLAT PANEL

RGB

(5 OF 11)

+3.3V_RGBDAC

DDC_DATA0/GPIO_39

DDC_CLK0/GPIO_38

RGB_DAC_RED

RGB_DAC_GREEN

RGB_DAC_HSYNC

RGB_DAC_BLUE

RGB_DAC_VSYNC

RGB_DAC_RSET RGB_DAC_VREF

IFPA_TXC_P

IFPA_TXD0_P

IFPA_TXC_N

IFPA_TXD0_N

DP0_3_P/TMDS0_TXC_P DP0_3_N/TMDS0_TXC_N

DP0_2_N/TMDS0_TX0_N

DDC_CLK3/DP_AUX_CH1_P DDC_DATA3/DP_AUX_CH1_N

DP0_1_P/TMDS0_TX1_P DP0_1_N/TMDS0_TX1_N DP0_0_P/TMDS0_TX2_P DP0_0_N/TMDS0_TX2_N

DP1_3_P/TMDS0B_TXC_P DP1_3_N/TMDS0B_TXC_N

DP1_2_P/TMDS0_TX3_P DP1_2_N/TMDS0_TX3_N DP1_1_P/TMDS0_TX4_P DP1_1_N/TMDS0_TX4_N DP1_0_P/TMDS0_TX5_P DP1_0_N/TMDS0_TX5_N

HPLUG_DET0/GPIO_20 HPLUG_DET1/GPIO_21 HPLUG_DET2/GPIO_22

DDC_CLK2/DP_AUX_CH0_P DDC_DATA2/DP_AUX_CH0_N

+3.3V_PLL_DP0_1

+VIO_PLL_IFPAB_1

+3.3V_PLL_USB_2

+VIO_PLL_IFPAB_2

+VIO_PLL_SPPLL0_1

+VIO_PLL_CORE_LEG

+VIO_PLL_SPPLL0_2

+VIO_PLL_NV_1

+VIO_PLL_V

+VDD_IFPA

+VIO_PLL_NV_2

+VDD_IFPB

+VIO_DP0_1 +VIO_DP0_2 +VIO_DP0_3

IFPA_TXD1_P IFPA_TXD1_N IFPA_TXD2_P IFPA_TXD2_N IFPA_TXD3_P IFPA_TXD3_N

IFPB_TXC_P IFPB_TXC_N

IFPB_TXD4_P IFPB_TXD4_N IFPB_TXD5_P IFPB_TXD5_N IFPB_TXD6_P IFPB_TXD6_N IFPB_TXD7_P IFPB_TXD7_N

DDC_CLK1/GPIO_40

DDC_DATA1/GPIO_41

TMDS0_RSET

TMDS0_VPROBE

IFPAB_RSET

IFPAB_VPROBE

+3.3V_PLL_USB_1

+3.3V_PLL_DP0_2

DP0_2_P/TMDS0_TX0_P

LCD_PANEL_PWR/GPIO_58

LCD_BKL_ON/GPIO_59

LCD_BKL_CTL/GPIO_57

OUT OUT OUT

OUT

OUT OUT OUT OUT

BI BI

OUT

OUT OUT

OUT

OUT OUT OUT OUT

IN IN

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

BRANCH

REVISION

DRAWING NUMBER

SIZE

SHEET

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8 7 5 4 2 1

NOTE: TMDS/HDMI not supported on IFPA/B for MCP89 A01.

140 mA

LVDS: Power +VDD_IFPx at 1.8V

=MCP_IFPAB_DDC_DATA

=MCP_IFPA_TXC_P/N

=MCP_IFPAB_DDC_CLK

=MCP_IFPB_TXD_P/N<3>

=MCP_IFPB_TXD_P/N<2>

=MCP_IFPB_TXD_P/N<1>

=MCP_IFPB_TXD_P/N<0>

=MCP_IFPB_TXC_P/N

=MCP_IFPA_TXD_P/N<3>

=MCP_IFPA_TXD_P/N<2>

=MCP_IFPA_TXD_P/N<1>

=MCP_IFPA_TXD_P/N<0>

(UNUSED)

MCP Signal

TMDS/HDMI

TMDS_IG_DDC_CLK TMDS_IG_DDC_DATA

TMDS_IG_TXD_P/N<5>

TMDS_IG_TXD_P/N<4>

TMDS_IG_TXD_P/N<3>

TMDS_IG_TXC_P/N

TMDS_IG_TXD_P/N<2>

TMDS_IG_TXD_P/N<1>

TMDS_IG_TXD_P/N<0>

Interface Mode

LVDS_IG_A_CLK_P/N LVDS_IG_A_DATA_P/N<0> LVDS_IG_A_DATA_P/N<1> LVDS_IG_A_DATA_P/N<2> LVDS_IG_A_DATA_P/N<3> LVDS_IG_B_CLK_P/N LVDS_IG_B_DATA_P/N<0> LVDS_IG_B_DATA_P/N<1> LVDS_IG_B_DATA_P/N<2> LVDS_IG_B_DATA_P/N<3>

LVDS_IG_DDC_DATA

LVDS_IG_DDC_CLK

LVDS

NOTE: No Composite/S-Video/Component Video support on MCP89

Okay to float all RGB_DAC signals. DDC_CLK0/DDC_DATA0 pull-ups still required (or use as GPIOs).

(GMUX_INT)

160 mA

Connect +3.3V_RGBDAC pin to GND.

RGB DAC Disable:

TMDS: Power +VDD_IFPx at 3.3V

180 mA

30 mA

210 mA

60 mA

40 mA 60 mA

40 mA 20 mA

180 mA

NOTE: 100K pull-downs required if HPLUG_DET0/HPLUG_DET1 are not used.

Current numbers from MCP89 A01 Bring-Up Support document (MCP89_TDP_EDP_Bringup_Targets_Apple.pdf, dated August 5, 2009). K6/K69 EDP currents used.

GPIO Pull-Ups

DDC Mode Pull-downs

NOTE: DP_AUX_CH1 also requires pull-downs if used for dual-mode DisplayPort (DP++). If unused no pulls are necessary, if used for TMDS/HDMI only then only pull-ups are necessary.

160 mA

24 71

FBGA

MCP89M-A01

OMIT

U1400

24 71

17 53

1/16W

402

MF-LF

10K

R1782

10K

MF-LF

402

1/16W

R1781

10K

MF-LF

402

1/16W

R1780

MF-LF

402

1/16W

100K

R1711

MF-LF

402

1/16W

100K

R1710

MCP Graphics

SYNC_MASTER=T27_MLB

SYNC_DATE=02/16/2010

=MCP_IFPA_TXC_N

TP_MCP_RGB_DAC_RSET

PP3V3_S0_MCP_PLL_DP_USB

DP_IG_AUX_CH1_N

DP_IG_ML1_N<0>

=MCP_IFPA_TXD_P<1>

TP_MCP_RGB_BLUE

=MCP_IFPA_TXD_N<1>

=MCP_IFPA_TXD_N<0>

=MCP_IFPB_TXD_N<2>

=MCP_IFPB_TXD_P<2>

=MCP_IFPB_TXD_N<1>

=MCP_IFPB_TXC_N

LCD_IG_PWR_EN

LCD_IG_BKLT_PWM

=PP1V05_S0_MCP_DP0_VDD

DP_IG_ML0_P<0>

DP_IG_ML0_P<1>

DP_IG_ML1_N<3>

=MCP_IFPAB_DDC_CLK

=MCP_IFPB_TXD_P<3>

MCP_TMDS0_VPROBE

DP_IG_ML1_N<1>

MCP_TMDS0_RSET

MCP_IFPAB_RSET

AUD_IP_PERIPHERAL_DET MIKEY_MIC_LOAD_DET

=MCP_IFPA_TXC_P

=MCP_IFPA_TXD_P<2> =MCP_IFPA_TXD_N<2> =MCP_IFPA_TXD_P<3> =MCP_IFPA_TXD_N<3>

=MCP_IFPB_TXC_P

=MCP_IFPB_TXD_P<1>

=MCP_IFPB_TXD_N<0>

=MCP_IFPB_TXD_N<3>

LCD_IG_BKLT_EN

TP_MCP_RGB_GREEN

TP_MCP_RGB_HSYNC

TP_MCP_RGB_RED

DP_IG_ML1_P<3>

DP_IG_ML1_N<2> DP_IG_ML1_P<1>

DP_IG_ML1_P<2>

DP_IG_ML0_P<2>

DP_IG_ML0_N<1>

DP_IG_ML0_N<2>

DP_IG_ML0_N<3>

TP_MCP_RGB_DAC_VREF

=MCP_IFPB_TXD_P<0>

MCP_IFPAB_VPROBE

=MCP_IFPAB_DDC_DATA

DP_IG_HPD0

=PP3V3R1V8_S0_MCP_IFP_VDD

PP1V05_S0_MCP_PLL_CORE

=PP1V05_S0_MCP_PLL_IFP

PP3V3_S0_MCP_DAC

DP_IG_ML0_N<0>

DP_IG_ML1_P<0>

=MCP_IFPA_TXD_P<0>

TP_MCP_RGB_VSYNC

DP_IG_HPD1 SATARDRVR_A_EN

DP_IG_AUX_CH1_P

DP_IG_AUX_CH0_P DP_IG_AUX_CH0_N

MIKEY_MIC_LOAD_DET

=PP3V3_S0_MCP_GPIO

AUD_IP_PERIPHERAL_DET

SATARDRVR_A_EN

DP_IG_AUX_CH0_N

DP_IG_AUX_CH0_P

DP_IG_ML0_P<3>

17 OF 109

C.0.0

051-8561

17 OF 76

B29

H25

F29

C31 B31

D31

A31

E31

C29 D29

K22

C22

L22

B22

D26 E26

F26

K25 K26

F25 G25 E25 D25

F28 G28

E28 D28 A28 A29 C28 B28

H26 J26 J25

L28 K28

M23

N23

M22

L24

N25

M25

L26

N24

M26

A22

L25

A23

A26 B26 C26

E22 D22 F22 G22 H22 J22

B23 C23

L23 K23 J23 H23 G23 F23 D23 E23

J28 G29

F31

H28

K20

L20

N21

N22

G26

C25

B25

A25

1 2

18 19

17 53

IN IN IN IN

IN IN

USB0_N USB0_P

SATA_A0_RX_N

SATA_A1_TX_P SATA_A1_TX_N

USB4_N

SATA_A0_RX_P

USB1_P USB1_N

USB2_P USB2_N

USB3_N

USB3_P

USB4_P

USB5_P USB5_N

USB6_P USB6_N

USB7_P USB7_N

USB8_N

USB9_N

USB9_P

USB10_N

USB10_P

USB_OC3*/GPIO_28_MGPIO_1

USB_RBIAS_GND

RGMII_VREF

RGMII_TXD1

RGMII_TXD0

RGMII_TXD3

RGMII_TXD2

RGMII_TXCLK RGMII_TXCTL

RGMII_MDC

RGMII_MDIO

BUF_25MHZ

RGMII_RESET*

SATA_A0_TX_P SATA_A0_TX_N

SATA_A1_RX_P

SATA_A1_RX_N

SATA_B0_TX_P SATA_B0_TX_N

SATA_B0_RX_N SATA_B0_RX_P

SATA_B1_TX_P SATA_B1_TX_N

SATA_B1_RX_N SATA_B1_RX_P

SATA_LED*/GPIO_30

SATA_TERMP

NC_1 NC_2

NC_4

NC_3

RGMII_RXD1

RGMII_RXD0

RGMII_RXD2 RGMII_RXD3

RGMII_RXCLK RGMII_RXCTL

RGMII_INTR/GPIO_35

+3.3V_PLL_MAC_DUAL

RGMII_COMP_VDD RGMII_COMP_GND

USB8_P

USB_OC2*/GPIO_27_MGPIO_0

USB_OC1*/GPIO_26

USB_OC0*/GPIO_25

USB11_P

USB11_N

LAN

SATA

USB

(6 OF 11)

OUT

NC NC NC NC

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

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REVISION

DRAWING NUMBER

SIZE

SHEET

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NOTICE OF PROPRIETARY PROPERTY:

345678

8 7 5 4 2 1

Geyser Trackpad/Keyboard

External C

Watermelon

Connect RGMII_INTR to 10K pull-down (if not used as GPIO).

Internal MAC Disable:

+3.3V_PLL_MAC_DUAL must remain connected to 3.3V RMGT rail. RGMII_COMP_VDD/_GND must remain connected as shown.

Connect RGMII_MDIO to 10K pull-down.

Connect RGMII_RXCTL to 10K pull-down.

20 mA

External A

Bluetooth

SD Card/ExpressCard

All other pins can be left TP or NC.

Connect RGMII_VREF to 10K pull-down.

Connect RGMII_RXCLK to 10K pull-down.

T57

Current numbers from MCP89 A01 Bring-Up Support document (MCP89_TDP_EDP_Bringup_Targets_Apple.pdf, dated August 5, 2009). K6/K69 EDP currents used.

Connect RGMII_RXD<0:3> together to 10K pull-down.

Camera/External E

External B

External D

OHCI0/EHCI0OHCI1/EHCI1

Internal 19.5K Pull-Downs on all USB pairs

USB JTAG in S3/S4/S5.

Only USB8-11 support nV

AirPort (PCIe Mini-Card)

OC3# Also for EXCARD

OC2# Also for EXTE

31 73

49.9

402

MF-LF

1/16W

R1810

1/16W MF-LF

49.9

402

R1811

MCP89M-A01

FBGA

OMIT

U1400

30 72

34 72

43 72

5% 1/16W MF-LF

8.2K

402

R1850

MF-LF 402

8.2K

5% 1/16W

R1851

8.2K

402

1/16W MF-LF

R1852

8.2K

402

1/16W MF-LF

R1853

64 72

34 72

1% MF-LF

402

1/16W

887

R1860

33 71

2.49K

1/16W 402

1% MF-LF

R1805

1/16W MF-LF

402

100K

R1800

MCP SATA, USB & Ethernet

SYNC_DATE=02/16/2010

SYNC_MASTER=T27_MLB

=PP3V3_ENET_MCP_RMGT

=PP3V3_S0_MCP_GPIO

=PP3V3_S5_MCP_GPIO

USB_BT_N USB_BT_P

USB_TPAD_P

MCP_MII_COMP_GND

MCP_MII_COMP_VDD

PP3V3_ENET_MCP_PLL_MAC

ENET_ENERGY_DET

ENET_RX_CTRL

ENET_CLK125M_RXCLK

ENET_RXD<3>

ENET_RXD<2>

ENET_RXD<0> ENET_RXD<1>

MCP_SATA_TERMP

MXM_GOOD_L

TP_SATA_D_D2RP

TP_SATA_D_D2RN

TP_SATA_D_R2D_CN

TP_SATA_D_R2D_CP

TP_SATA_C_D2RN

SATA_ODD_D2R_N SATA_ODD_D2R_P

SATA_HDD_R2D_C_N

SATA_HDD_R2D_C_P

TP_ENET_RESET_L

TP_MCP_CLK25M_BUF0_R

ENET_MDIO

TP_ENET_MDC

TP_ENET_TX_CTRL

TP_ENET_CLK125M_TXCLK

TP_ENET_TXD<2> TP_ENET_TXD<3>

TP_ENET_TXD<0> TP_ENET_TXD<1>

MCP_RGMII_VREF

USB_IR_P USB_IR_N

USB_EXTB_P USB_EXTB_N

USB_TPAD_N

USB_EXTD_N

USB_EXTD_P

USB_SDCARD_N

USB_SDCARD_P

USB_CAMERA_N

USB_CAMERA_P

USB_WM_P

USB_EXTC_P USB_EXTC_N

USB_T57_N

USB_T57_P

USB_MINI_P

SATA_HDD_D2R_P

USB_WM_N

SATA_ODD_R2D_C_N

SATA_ODD_R2D_C_P

SATA_HDD_D2R_N

USB_EXTA_N

TP_SATA_C_R2D_CP TP_SATA_C_R2D_CN

TP_SATA_C_D2RP

USB_EXTA_P

USB_MINI_N

USB_EXTB_OC_L

USB_EXTD_OC_L

MCP_USB_RBIAS_GND

USB_EXTC_OC_L

USB_EXTA_OC_L

18 OF 109

C.0.0

051-8561

18 OF 76

C20 B20

AJ4

AJ3 AJ2

D20

AJ5

J20 H20

C19 B19

F20

G20

E20

E19 D19

G19 F19

J17 H17

H19

B17

C17

D17

E17

K19

L19

C13

H13

G13

D14

F14

G14 E14

F13 K13

J13

J14

AH4 AH5

AH3

AH2

AJ6 AJ7

AH7 AH6

AL4 AL3

AL1 AL2

AH1

AJ1

G4 E7

C14

B14

D16 F16

E16 A14

H14

M16

D13 E13

J19

K17

L17

A17

F17

G17

8 9

20 23

17 19

OUT

HDA_SDATA_OUT

HDA_BITCLK

HDA_RESET*

HDA_SYNC

LPC_SERIRQ

LPC_FRAME*

LPC_RESET*

LPC_CLK0

MISC_VDDEN0/GPIO_47 MISC_VDDEN1/GPIO_48

MISC_VDDEN4/GPIO_19

MISC_VDDEN3/GPIO_18

MISC_VDDEN2/GPIO_17

MEM_VDD_SEL/GPIO_46

FANCTL0/GPIO_61

FANRPM0/GPIO_60/MGPIO_2

FANCTL1/GPIO_62

SLP_S3*

FANRPM1/GPIO_63/MGPIO_3

SLP_S5*

SLP_RMGT*

MCP_VID0/GPIO_13

MCP_VID2/GPIO_15

MCP_VID1/GPIO_14

SPI_CS0*/GPIO_10

SPI_DI/GPIO_08 SPI_DO/GPIO_09

SPI_CLK/GPIO_11

SPKR/GPIO_1

THERM_DIODE_N

THERM_DIODE_P

SMB_DATA0

SMB_CLK1/MSMB_CLK

SMB_CLK0

SMB_ALERT*/GPIO_64

SMB_DATA1/MSMB_DATA

SUS_CLK/GPIO_34

BUF_SIO_CLK/GPIO_33

PKG_TEST

TEST_MODE_EN

PKG_TEST2

+VDD_HDA

HDA_SDATA_IN0

HDA_PULLDN_COMP

HDA_SDATA_IN1/GPIO_2

LPC_AD1

LPC_AD0

LPC_DRQ0*/GPIO_43

LPC_AD3

LPC_AD2

LPC_CLKRUN*/GPIO_42

EXT_SMI*/GPIO_32

SIO_PME*/GPIO_31

A20GATE/GPIO_55 KBRDRSTIN*/GPIO_56

RSTBTN*

PWRBTN*

RTC_RST*

PWRGD_SB PWRGD

MCP_WAKE_REQ*

MCP_MEMVDD_EN/GPIO_44

MEMVTT_EN/GPIO_45

INTRUDER*

MGPU_PIO1/GPIO_7

MGPU_PIO0/GPIO_6

MGPU_PIO3/GPIO_24

MGPU_PIO2/GPIO_23

JTAG_TDO

JTAG_TDI

JTAG_TRST* JTAG_TCK

JTAG_TMS

XTALIN

XTALIN_RTC

XTALOUT

XTALOUT_RTC

MCP_VID3/GPIO_16

MCP_WAKE_DIS*

MISC LPC

(7 OF 11)

HDA

OUT

OUT OUT OUT

OUT

OUT OUT

OUT

OUT OUT

OUT

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

BRANCH

REVISION

DRAWING NUMBER

SIZE

SHEET

PAGE TITLE

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

345678

8 7 5 4 2 1

GPIO Pull-Ups/Downs

Output limited to +VDD_HDA.

(IPD)

Straps not provided on this page.

NOTE: 42 & 62 MHz use FAST_READ command.

62.5 MHz

42.7 MHz

31.2 MHz

25.0 MHz

Connects to SMC for automatic recovery.

NOTE: MCP89 A01 has

(IPU)

strong (~10K) pull-downs on these pins.

(IPU-S5)

(IPU)

(IPD)

70 mA

(IPD)

(IPU)

1 0

Frequency

24 MHz

14.31818 MHz

0 1

SPI Frequency Select

SPI_DO

Frequency

BIOS Boot Select

LPC_FRAME#

LPC

(IPU-S5)

(IPU)

(IPD)

(IPU)

NOTE: MCP89 does not support FWH, only LPC ROMs. So Apple designs will

HDA_SYNC

I/F

SPI_CLK

BUF_SIO_CLK Frequency

(IPU-S5)

SPI

(IPU)

NOTE: MCP SLP_S5# signal has the behavior of Intel’s SLP_S4# signal.

70 mA

not use LPC for BootROM override.

1 = SAFE mode (For ROMSIP recovery)

0 = USER mode (Normal boot mode)

MCP_SPKR:

(IPD) (IPD)

NOTE: MCP89 A01 has strong (~10K)

Platform-Specific Connections

(IPU)

(IPU-S5)

(IPD)

Confirmed OK for this signal.

pull-downs on these pins.

HDA Output Caps

For EMI Reduction on HDA interface

Current numbers from MCP89 A01 Bring-Up Support document (MCP89_TDP_EDP_Bringup_Targets_Apple.pdf, dated August 5, 2009). K6/K69 EDP currents used.

35 37 72

19 25 72

35 37 25 72

402

10K

5% 1/16W MF-LF

R1961

MCP89M-A01

FBGA

OMIT

U1400

MF-LF

1/16W

402

R1953

48 72

MF-LF

402

1/16W

R1952

402

MF-LF

1/16W

R1951

MF-LF

402

1/16W

R1950

48 72

402

1% 1/16W MF-LF

49.9

R1900

48 72

19 59

41 75

19 35 36 62

35 62 66

37 72

19 37 72

37 72

1/16W MF-LF

10K

402

R1970

1/16W MF-LF

402

10K

R1959

MF-LF

1% 1/16W

402

R1975

25 72

19 30 62

38 72

13 38 72

10K

MF-LF

1/16W

402

R1930

100K

MF-LF

1/16W

402

R1931

49.9K

MF-LF

402

1/16W

R1920

MF-LF

1/16W

402

49.9K

R1921

50V

402

CERM

10PF

C1951

CERM

50V

10PF

402

C1950

50V

10PF

402

CERM

C1953

10PF

402

CERM

50V

C1952

35 37

21 62

MF-LF

402

1/16W

R1960

MF-LF1/16W

402

R1910

402

MF-LF1/16W

R1912

5%221/16W MF-LF

402

R1911

402

MF-LF1/16W

R1913

35 37 72

19 37 47

19 22

19 26 27 35

19 33

35 36 62

19 36

MF-LF1/16W

100K

402

R1985

10K

MF-LF

402

1/16W

R1996

4025%

1/16W MF-LF

10K

R1988

402

1/16W5%MF-LF

10K

R1980

100K

MF-LF

402

1/16W

R1987

10K

MF-LF1/16W

5% 402

R1990

1/16W

402

MF-LF

10K

R1991

10K

MF-LF

402

1/16W

R1989

MF-LF

402

1/16W

100K

R1997

1/16W

402

MF-LF

10K

R1981

MF-LF1/16W

5% 402

100K

R1992

100K

MF-LF1/16W

5% 402

R1993

100K

MF-LF1/16W

5% 402

R1994

4025%

1/16W MF-LF

100K

R1995

402

10K

MF-LF1/16W

R1984

1/16W

100K

MF-LF

402

R1986

19 37

19 35 36 62 35

35 37 19 25 72

1/16W MF-LF

402

R1965

MF-LF 402

1/16W

10K

NO STUFF

R1966

402

10K

MF-LF1/16W

R1983

4025%

1/16W MF-LF

20K

R1998

402

MF-LF

100K

1/16W

R1999

SYNC_MASTER=T27_MLB

SYNC_DATE=02/16/2010

MCP HDA, LPC & MISC

HDA_BIT_CLK_R

MEM_EVENT_L

SMBUS_MCP_1_DATA

HDA_SDIN0

AUD_IPHS_SWITCH_EN

PM_BATLOW_L

MCP_PS_PWRGD

MCP_MEM_VDD_EN

LPC_AD<3>

LPC_AD<1>

LPC_AD<0>

GFXVCORE_PWR_EN

T57_RESET

JTAG_MCP_TMS

MCP_CLK25M_XTALOUT

LPC_AD<2>

MCP_MEM_VTT_EN

SMC_IG_THROTTLE_L

JTAG_MCP_TDI

LPC_PWRDWN_L

PM_SLP_S5_L

LPC_RESET_L

PM_SLP_S4_L

MAKE_BASE=TRUE

MCP_WAKE_REQ_L

MCP_CLK25M_XTALIN

JTAG_MCP_TDO

MCP_SPKR

HDA_SDOUT

HDA_RST_R_L

HDA_RST_L

HDA_BIT_CLK_R

HDA_BIT_CLK

=PP3V3_S0_MCP_GPIO

LPC_FRAME_L

HDA_SDOUT_R

ARB_DETECT_L

ENET_LOW_PWR SDCARD_RESET

PM_SLP_S4_L

SPI_CLK_R SPI_MISO SPI_MOSI_R

MCP_THMDIODE_N SMBUS_MCP_0_CLK

SMBUS_MCP_0_DATA SMBUS_MCP_1_CLK

AP_PWR_EN

PM_CLK32K_SUSCLK_R

SPIROM_USE_MLB

HDA_SYNC

LPC_FRAME_R_L

LPC_CLK33M_SMC_R

MCP_CPU_VTT_EN_L MLB_RAM_VENDOR T57_PWR_EN SMC_ADAPTER_EN

ODD_PWR_EN_L

SMC_RUNTIME_SCI_L

LPC_SERIRQ

LPCPLUS_GPIO

AUD_I2C_INT_L

MCP_HDA_PULLDN_COMP

=PP3V3R1V5_S0_MCP_HDA

LPC_AD_R<1>

LPC_AD_R<0>

PM_CLKRUN_L

LPC_AD_R<3>

LPC_AD_R<2>

TP_MLB_RAM_SIZE

PM_LATRIGGER_L

PM_PWRBTN_L

RTC_RST_L

PM_SYSRST_DEBOUNCE_L

PM_SLP_S3_L PM_SLP_RMGT_L

MCP_VID<0> MCP_VID<1> MCP_VID<2> MCP_VID<3>

MCP_THMDIODE_P

SPI_CS0_R_L

HDA_SYNC_R

MCP_TEST_MODE_EN

LPC_RESET_L

RTC_CLK32K_XTALOUT

PM_RSMRST_L

JTAG_MCP_TCK

JTAG_MCP_TRST_L

RTC_CLK32K_XTALIN

SPIROM_USE_MLB

MCP_CPU_VTT_EN_L MLB_RAM_VENDOR T57_PWR_EN LPCPLUS_GPIO

ODD_PWR_EN_L MEM_EVENT_L ENET_LOW_PWR SMC_IG_THROTTLE_L

MCP_VID<0> MCP_VID<1> MCP_VID<2>

AP_PWR_EN ARB_DETECT_L

HDA_RST_R_L HDA_SYNC_R

MCP_VID<3>

SPI_MISO

HDA_SDOUT_R

SM_INTRUDER_L

MCP_MEM_VDD_SEL_1V5

SMC_WAKE_SCI_L

PP3V3_G3_RTC

=PP3V3_S0_MCP_GPIO

=PP3V3_S5_MCP_GPIO =PP3V3_S3_MCP_GPIO

SDCARD_RESET T57_RESET GFXVCORE_PWR_EN

19 OF 109

C.0.0

051-8561

19 OF 76

K10 C8

H7 H6 G6

E11

F11 B8

B4 A5

H11

L16

K16

G11

D11

B3 H2

F10

J10

G16

C11

H16

G10

J16

J11

H10

D10

C10

E10 A10

B10

A11

B16

B11

C16

1 2

121

1 2

1 2 1 2

1 2

1 2 1 2 1 2 1 2

1 2

19 72

17 18 19

19 72

19 37 47

19 37

19 33

19 26 27 35

19 36

19 59

19 30 62

19 72

19 59

19 37 72

19 72

7 8

20 23

17 18 19

19 22

+VDD_MEM_30 +VDD_MEM_31

+VDD_MEM_28 +VDD_MEM_29

+VDD_MEM_25 +VDD_MEM_26 +VDD_MEM_27

+VDD_MEM_23 +VDD_MEM_24

+VDD_MEM_22

+VDD_MEM_20 +VDD_MEM_21

+VDD_MEM_17 +VDD_MEM_18 +VDD_MEM_19

+VDD_MEM_15 +VDD_MEM_16

+VDD_MEM_12 +VDD_MEM_13 +VDD_MEM_14

+VDD_MEM_10 +VDD_MEM_11

+VDD_MEM_8 +VDD_MEM_9

+VDD_MEM_7

+VDD_MEM_5 +VDD_MEM_6

+VDD_MEM_4

+VDD_MEM_3

+VDD_MEM_2

+VDD_MEM_1

+VTT_CPU2_1 +VTT_CPU2_2 +VTT_CPU2_3 +VTT_CPU2_4

+VTT_CPU_27

+VTT_CPU_24 +VTT_CPU_25 +VTT_CPU_26

+VTT_CPU_23

+VTT_CPU_22

+VTT_CPU_21

+VTT_CPU_20

+VTT_CPU_19

+VTT_CPU_18

+VTT_CPU_16 +VTT_CPU_17

+VTT_CPU_14 +VTT_CPU_15

+VTT_CPU_11 +VTT_CPU_12 +VTT_CPU_13

+VTT_CPU_9 +VTT_CPU_10

+VTT_CPU_8

+VTT_CPU_1

+VTT_CPU_7

+VTT_CPU_6

+VTT_CPU_5

+VTT_CPU_4

+VTT_CPU_3

+VTT_CPU_2

(8 OF 11)

POWER I

POWER II

(9 OF 11)

+VDD_COREB_1

+VDD_COREB_3

+VDD_COREB_2

+VDD_COREB_4 +VDD_COREB_5 +VDD_COREB_6

+VDD_COREB_8

+VDD_COREB_7

+VDD_COREB_9 +VDD_COREB_10 +VDD_COREB_11

+VDD_COREB_13

+VDD_COREB_12

+VDD_COREB_14 +VDD_COREB_15 +VDD_COREB_16

+VDD_COREB_18

+VDD_COREB_17

+VDD_COREB_19 +VDD_COREB_20 +VDD_COREB_21 +VDD_COREB_22 +VDD_COREB_23 +VDD_COREB_24

+VDD_COREB_26

+VDD_COREB_25

+VDD_COREB_27 +VDD_COREB_28 +VDD_COREB_29

+VDD_COREB_31

+VDD_COREB_30

+VDD_COREB_32 +VDD_COREB_33 +VDD_COREB_34

+VDD_COREB_36

+VDD_COREB_35

+VDD_COREB_37 +VDD_COREB_38 +VDD_COREB_39 +VDD_COREB_40 +VDD_COREB_41 +VDD_COREB_42

+VDD_COREB_SENSE

GND_COREB_SENSE

+VIO_SATA_AVDD_1

+VIO_SATA_AVDD_3

+VIO_SATA_AVDD_2

+VIO_SATA_AVDD_4 +VIO_SATA_AVDD_5

+VIO_SATA_DVDD_1 +VIO_SATA_DVDD_2 +VIO_SATA_DVDD_3 +VIO_SATA_DVDD_4 +VIO_SATA_DVDD_5 +VIO_SATA_DVDD_6 +VIO_SATA_DVDD_7 +VIO_SATA_DVDD_8

+VIO_SATA_DVDD_9 +VIO_SATA_DVDD_10 +VIO_SATA_DVDD_11 +VIO_SATA_DVDD_12

+VDD_DUAL_RMGT_1

+VDD_DUAL_RMGT_2

+3.3V_DUAL_RMGT_1

+3.3V_DUAL_USB_1

+3.3V_DUAL_RMGT_2

+3.3V_DUAL_USB_2

+3.3V_DUAL_1 +3.3V_DUAL_2

+3.3V_HVDD_3

+3.3V_HVDD_1 +3.3V_HVDD_2

+3.3V_5

+3.3V_3 +3.3V_4

+3.3V_2

+3.3V_1

+VDD_DUAL_AUXC_2

+VDD_DUAL_AUXC_1

+VDD_DUAL_AUXC_3

+3.3V_VBAT

+VIO_PE_AVDD1_4 +VIO_PE_AVDD1_5

+VIO_PE_AVDD1_1

+VIO_PE_AVDD1_3

+VIO_PE_AVDD1_2

+VIO_PE_AVDD0_5 +VIO_PE_AVDD0_6

+VIO_PE_AVDD0_3 +VIO_PE_AVDD0_4

+VIO_PE_AVDD0_2

+VIO_PE_AVDD0_1

+VIO_PE_DVDD1_2 +VIO_PE_DVDD1_3

+VIO_PE_DVDD1_1

+VIO_PE_DVDD0_3 +VIO_PE_DVDD0_4

+VIO_PE_DVDD0_2

+VIO_PE_DVDD0_1

+VDD_COREA_32 +VDD_COREA_33

+VDD_COREA_30 +VDD_COREA_31

+VDD_COREA_29

+VDD_COREA_28

+VDD_COREA_27

+VDD_COREA_25

+VDD_COREA_24

+VDD_COREA_26

+VDD_COREA_22 +VDD_COREA_23

+VDD_COREA_21

+VDD_COREA_19 +VDD_COREA_20

+VDD_COREA_18

+VDD_COREA_16 +VDD_COREA_17

+VDD_COREA_15

+VDD_COREA_14

+VDD_COREA_11 +VDD_COREA_12 +VDD_COREA_13

+VDD_COREA_9 +VDD_COREA_10

+VDD_COREA_6 +VDD_COREA_7 +VDD_COREA_8

+VDD_COREA_4 +VDD_COREA_5

+VDD_COREA_1

+VDD_COREA_3

+VDD_COREA_2

GND_COREA_SENSE

+VDD_COREA_SENSE

(10 OF 11)

GND

GND_28 GND_29

GND_27

GND_97 GND_98

GND_69

GND_68

GND_71

GND_70

GND_72

GND_74

GND_73

GND_75 GND_76 GND_77 GND_78 GND_79 GND_80 GND_81 GND_82

GND_84

GND_83

GND_85 GND_86 GND_87

GND_89

GND_88

GND_90

GND_92

GND_91

GND_94

GND_93

GND_95 GND_96

GND_99

GND_102

GND_100 GND_101

GND_103 GND_104 GND_105

GND_107

GND_106

GND_109

GND_108

GND_110

GND_112

GND_111

GND_113 GND_114 GND_115

GND_117

GND_116

GND_118 GND_119 GND_120

GND_122

GND_121

GND_123 GND_124 GND_125 GND_126 GND_127 GND_128

GND_130

GND_129

GND_131

GND_133

GND_132

GND_134

GND_2

GND_1

GND_4

GND_3

GND_6 GND_7

GND_5

GND_8 GND_9

GND_12

GND_11

GND_10

GND_14

GND_13

GND_15 GND_16 GND_17

GND_19

GND_18

GND_20 GND_21 GND_22 GND_23 GND_24 GND_25 GND_26

GND_30 GND_31 GND_32

GND_35

GND_34

GND_33

GND_37

GND_36

GND_38

GND_40

GND_39

GND_43

GND_41 GND_42

GND_45

GND_44

GND_47 GND_48

GND_46

GND_50

GND_49

GND_53

GND_52

GND_51

GND_55

GND_54

GND_56 GND_57 GND_58

GND_60

GND_59

GND_61 GND_62 GND_63 GND_64 GND_65 GND_66 GND_67

(11 OF 11)

GND

GND_157 GND_158

GND_199

GND_198

GND_197

GND_196

GND_195

GND_194

GND_193

GND_192

GND_191

GND_188

GND_190

GND_189

GND_187

GND_186

GND_183 GND_184 GND_185

GND_182

GND_181

GND_179 GND_180

GND_178

GND_177

GND_176

GND_175

GND_173 GND_174

GND_170

GND_172

GND_171

GND_169

GND_168

GND_166

GND_165

GND_167

GND_164

GND_163

GND_161

GND_160

GND_162

GND_159

GND_156

GND_155

GND_154

GND_153

GND_152

GND_150 GND_151

GND_147

GND_149

GND_148

GND_146

GND_145

GND_142 GND_143 GND_144

GND_140 GND_141

GND_138 GND_139

GND_137

GND_136

GND_135

GND_264

GND_263

GND_262

GND_261

GND_259

GND_258

GND_260

GND_256 GND_257

GND_254

GND_253

GND_255

GND_252

GND_251

GND_250

GND_249

GND_248

GND_246 GND_247

GND_245

GND_244

GND_243

GND_241 GND_242

GND_240

GND_239

GND_238

GND_236

GND_235

GND_237

GND_233 GND_234

GND_232

GND_230 GND_231

GND_228 GND_229

GND_227

GND_225 GND_226

GND_223 GND_224

GND_220

GND_222

GND_221

GND_219

GND_218

GND_217

GND_215 GND_216

GND_213

GND_212

GND_214

GND_211

GND_210

GND_209

GND_208

GND_207

GND_205 GND_206

GND_203 GND_204

GND_202

GND_200 GND_201

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

BRANCH

REVISION

DRAWING NUMBER

SIZE

SHEET

PAGE TITLE

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

345678

8 7 5 4 2 1

Current numbers from MCP89 A01 Bring-Up Support document (MCP89_TDP_EDP_Bringup_Targets_Apple.pdf, dated August 5, 2009). K6/K69 EDP currents used.

NOTE: "SW" rails are dynamically switched in the S0 state as needed, controlled by MCP89 GPIOs.

?? uA (G3)

250 mA

be used for remote sensing unless

NOTE: VDD_COREx_SENSE signals should NOT

(PE0[5:4], PE1[1:0])

(PE0[3:0])

as close to COREB FET as possible.

regulators.

COREA/COREB are powered by separate

4300 mA2000 mA

200 mA

8450 mA (0.85V)

15350 mA (0.85V)

300 mA

100 mA

300 mA

200 mA

40 mA

240 mA

140 mA

5 mA (S0)

150 mA

200 mA (DVDD0 & DVDD1)

30 mA

(PE0[3:0])

500 mA (AVDD0 & AVDD1)

Okay to GND if not using PE0[3:0]

500 mA (AVDD0 & AVDD1) (PE0[5:4], PE1[1:0])

Okay to GND if not using PE0[3:0]

200 mA (DVDD0 & DVDD1)

Instead connect regulator sense point

FBGA

OMIT

MCP89M-A01

U1400

CKPLUS_WAIVE=PwrTerm2GndCKPLUS_WAIVE=PwrTerm2GndCKPLUS_WAIVE=PwrTerm2GndCKPLUS_WAIVE=PwrTerm2Gnd

CKPLUS_WAIVE=PwrTerm2GndCKPLUS_WAIVE=PwrTerm2GndCKPLUS_WAIVE=PwrTerm2GndCKPLUS_WAIVE=PwrTerm2GndCKPLUS_WAIVE=PwrTerm2GndCKPLUS_WAIVE=PwrTerm2Gnd

OMIT

MCP89M-A01

FBGA

U1400

FBGA

OMIT

MCP89M-A01

U1400

MCP89M-A01

OMIT

FBGA

U1400

MCP Power & Ground

SYNC_DATE=02/16/2010

SYNC_MASTER=T27_MLB

=PP3V3_ENET_MCP_RMGT

=PP1V05_S0_MCP_FSB

=PP1V5R1V35_SW_MCP_MEM

=PP0V9_S5_MCP_VDD_AUXC

PP3V3_G3_RTC

TP_MCP_VDDCOREA_SENSEP

=PP1V05_SW_MCP_FSB

TP_MCP_VDDCOREB_SENSEN

=PPVCORE_SW_MCP_GFX

PP1V05_S0_MCP_SATA_AVDD

=PPVCORE_S0_MCP

TP_MCP_VDDCOREA_SENSEN =PP1V05_S0_MCP_PE_DVDD0

=PP1V05_S0_MCP_PE_DVDD1

=PP3V3_S0_MCP_HVDD

TP_MCP_VDDCOREB_SENSEP

=PP3V3_S5_MCP

=PP1V05_S0_MCP_PE_AVDD1

=PP3V3_S0_MCP

=PP1V05_S0_MCP_PE_AVDD0

=PP1V05_S0_MCP_SATA_DVDD

=PP0V9_ENET_MCP_RMGT

20 OF 109

C.0.0

051-8561

20 OF 76

AJ10 AF20

AJ8 AF14

AL8 AF17 AJ11

AM3 AL5

AF15

AH12 AM2

AG17 AL6 AG16

AJ9 AF19

AM5 AG19 AF23

AF22 AG20

AG13 AF16

AK8

AM1 AM4

AF21

AF18

AL7

AG14

W27 W28 Y27 Y28

N26

H31 B32 R26

T26

U26

H30

M28

E32

C32

U27 G31

H29 W26

P26 F32 A32

J29 N27

T27

G32

P27

V26

Y26

L29

D32

K29

N12 N4 N14

N10

V20

P3 P1 N11

N2 N9 N8

M10

N1 M5 M7 P2 M8 M11

V19

N16 P5 N5

N15

N13

P9 V17 V18

M13

M14

Y19 Y20 Y17 Y18 P7 P8

U10 T10

AE1

AE3

AE2

AE4 AE5

AF1 AF2 AF3 AF4 AF5 AF6 AF9 AF10 AF11 AE11 AE12 AE13

L12 L13

A13

A20

B13

A19

F8 E8

U13

T11 T12

E29

U12

U11

M17

L11

M20

A16

W12 W13

Y12

AA13

Y13

AD13 AB13

AC12 AD11

AB12

AC13

AE7 AE8

AE6

AE9

AE10

AF8

AF7

P10 P11

AA22

P12

Y22

W22

V22

U22

R5 T7

T8 R8

AB19

P13

AB21

AB18

T1 T2

AB17

R10

T6 T13 R11

R13

AB20

AB22

L10

M32

B18

AM27 AP27

B12

AD7

E12

D12

G12

AL12

AM6 AD37 AG32 H12 AR35 H9 G24 V10

AL30

G7 V29 AP15

AJ12

AN2

AR15

D21

N20

G21

E21

H21 AR27

AM15

AH24

AA31 AM9

K12 J31 E30

AK7

AU12

M31

AP6

A36

B37

F35 L27 D35

AP30

AL24

AH15 B21 AV3

B38

AT38

AA21 AD4 A37 AP18 AN4 B24

D30

AA7

AK4

AD34

R37

M37

AP21

AU37

AM21

D18

AC27

AD5

AM30

AT1

AP24

AT3

AM33 AE27 AJ24

AA8

AH18

AM18

J32 AJ21 AK35

H15

D33

E6 J5

K18

F34

AD10

AN34

R35

AR9

AA10

AA2

R32 AG29

AM12

AP12

V32 AR33

AH21

AA32

K24

AK37

AG34

K21

AG8

AN5

AD2

AD32

D15

AG2

L15 AK32 AR12 AN35 AN37

AH27

E18

H27

N19

AV37

AL27

G15

L18

B15

AJ15

AA4

H18

AU38

E9 E27 L21

AG10

AU1

AU27

AH30

J34

AU33

AR30

AK34

E15

D27

J35

R34

C38

V28

M34

AA11

B27

AL21

V34

K11

AK31

AU21

AA34

M19

K15

E24

N18

AK5

D24

AU30

H24

AR21

B30

AM24

AU9

AA5 G18

AL18 AR24

AD35 AJ18

AG5

AU15

AU24

U21

AA20

AA19

AA18

AB27

AA26

AA17

W19 W20

AD29

AD28

AG4

N17

AA29

AA28

V21

W17

W18 U20

U19

W21

U18

Y21 V31

U17

R31

R28

G30

R29

AB26 M29

AL9

F2 K27

L14 K14

AR18

AG37 AL15

V37 AA37

AU2

AD31

AP9

AD8

AG7

AG35

AJ27 G9

AV36

AR6

B33

AU18

AA35

G27

V35

J37

F37 C3

AK2 AU6

AV2

E33 M35

8 9

18 23

14 23

15 21 23

7 8

19 23

22 24

OUT

G S

VCC

DONE

GND

THRM

CNFG

PAD

SENSE

KELVIN

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

BRANCH

REVISION

DRAWING NUMBER

SIZE

SHEET

PAGE TITLE

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

345678

8 7 5 4 2 1

droop during Q2300 turn-on.

C2300 helps reduce input rail

STMFS4854N

10 mOhm @3.2V

4.3 A (EDP)

N-Channel

Part Type Rds(on) Loading

Q2300

(OR 1.35V)

4250 mA

- FET Ron <= 3.8 mOhms

- Max Ramp-Up Time: 65 uS (ENABLE to 90%)

- Min Ramp-Up Time: 20 uS (10% to 90%)

NOTE: nVidia recommends Infineon BSC030N03MS for Q2300. Gated Rail Savings: 120mW

(G driven to VCC)

Approx. Ramp Time (EN to 1.35V, uS): 7.91 + 0.0678 * R1(Kohms)

<R1>

DIMM CKE Clamps

NO STUBS on CKE signals!

Clamps enable before MCP89 MEMVDD rail switched off. Clamps release after MCP89 MEMVDD is up and CKEs are driven by MCP89. Clamps also discharge VTT rail via termination resistor on each CKE signal on DIMM.

CKE must be held low to keep memory in self-refresh.

Q2355/Q2356 chosen for low output capacitance.

NV Requirements:

1% 1/16W

402

560K

R2305

19 62

20% 10V CERM 402

0.1UF

C2305

100UF

20%

6.3V

CERM-X5R

1206-1

PLACE_NEAR=Q2300.9:2 mm

CRITICAL

C2300

15 27 70

15 26 70

SOD-VESM-HF

SSM3K15FV

Q2350

MF-LF

402

10K

1/16W

R2350

SLG5AP031

TDFN

CRITICAL

U2305

STMFS485NST1G

DFN

CRITICAL

Q2300

Q2355

SOT-963

NTUD3170NZXXG

CRITICAL

SOT-963

Q2356

NTUD3170NZXXG

CRITICAL

SYNC_MASTER=K6_MLB

SYNC_DATE=02/16/2010

MCP89 Memory Rail Gating

MCPDDRFET_KELVIN

MCPDDRFET_SENSE

MCP_MEM_VDD_EN

MCPMEM_CNFG

TP_MCPMEM_DONE

=PP1V5R1V35_S0_MCPDDRFET

MIN_LINE_WIDTH=0.6 mm

MAKE_BASE=TRUE

VOLTAGE=1.5V

MIN_NECK_WIDTH=0.2 mm

PP1V5R1V35_SW_MCP

=PP5V_S3_MCPDDRFET

MCPMEM_GATE

=PP5V_S3_MCPDDRFET

=PP1V5R1V35_SW_MCP_MEM

MEM_A_CKE<1>

MEM_A_CKE<0>

MEM_B_CKE<1>

MEMVTT_EN_L

MEM_B_CKE<0>

MCP_MEM_VTT_EN

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OUT

CNFG

THRM

GND

DONE

VCC

PAD

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

BRANCH

REVISION

DRAWING NUMBER

SIZE

SHEET

PAGE TITLE

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

345678

8 7 5 4 2 1

<C1>

Approx. Ramp Time (EN to 1V, uS): 43.9 + 0.6943 * C1(pF)

(G driven to VCC)

- Max Ramp-Up Time: 1500 uS (ENABLE to 90%)

Q2400

15.35 A (EDP)

NOTE: nVidia recommends Infineon BSC020N03MS for Q2400.

droop during Q2400 turn-on.

C2400 helps reduce input rail

N-Channel

Si4838BDY

3.2 mOhm @2.5V

- Min Ramp-Up Time: 100 uS (10% to 90%)

- FET Ron <= 2.5 mOhms

Gated Rail Savings: 860mW

NV Requirements:

Type

Part

Rds(on)

XW2401

PLACE_NEAR=C2400.2:1 mm

XW2400

PLACE_NEAR=C2400.1:1 mm

59 75

Q2400

CRITICAL

SI4838BDY

SO-8

C2405

20% 10V CERM 402

0.1UF

C2400

100UF

PLACE_NEAR=Q2400.5:2 mm

CRITICAL

1206-1

CERM-X5R

6.3V

20%

C2406

10% CERM

820PF

402

50V

U2405

SLG5AP033

TDFN

CRITICAL

SYNC_DATE=12/15/2009

SYNC_MASTER=T27_MLB

MCP89 GFX Core Rail Gating

=PP5V_S0_MCPFSBFET

TP_MCPGFX_DONE

VOLTAGE=0.9V

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm

MAKE_BASE=TRUE

PPVCORE_SW_MCP_GFX

GFXVCORE_PWR_EN

MCPGFX_CNFG

=PPVCORE_S0_MCPGFXFET

MCPGFX_GATE

MCPCORES0_VSEN_P

MCPCORES0_VSEN_N

=PPVCORE_SW_MCP_GFX

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20 24

OUT

+IN

-IN

V+

V-

+IN

-IN

V+

V-

VOUT

VIN

GND

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

BRANCH

REVISION

DRAWING NUMBER

SIZE

SHEET

PAGE TITLE

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

345678

8 7 5 4 2 1

DO NOT SYNC FROM T27. DECOUPLING CAP VALUES CHANGED.

MCP 1.05V PCIE Digital Power

MCP 2.0V-3.3V RTC Power

210 mA

140 mA

MCP 0.9V AUX Core Power

PLACEMENT_NOTEs:

(For R and C)

MCP 3.3V PLL Power

MCP S0 FSB (VTT) Power

MCP CPU FSB (VTT) Power

4300 mA (1.5V)

250 mA

MCP Memory Power

MCP Non-GFX Core Power

8450 mA (0.85V)

2000 mA

150 mA

200 mA

300 mA

240 mA

MCP 1.05V Memory DLL Power

200 mA

? uA (G3) 5 mA (S0)

30 mA

500 mA

325 mA

160 mA

MCP 1.05V PCIe Analog Power

MCP 1.05V PCIe/SATA PLL Power

MCP 1.05V CPU/FSB/MEM PLL Power

70 mA

300 mA

MCP 1.05V SATA Analog Power

800 mA

555 mA

MCP 1.05V Core/Misc PLL Power

MCP 3.3V I/O Power

70 mA

MCP 3.3V/1.5V HDA Power

20 mA

MCP 3.3V MAC PLL Power

550 mA

MCP 3.3V AUX/USB Power

50 mA

100 mA

MCP 0.9V MAC/SMU Power

MCP 3.3V MAC/SMU Power

Current #s from MCP89 A01 Bring-Up Support doc (MCP89_TDP_EDP_Bringup_Targets_Apple.pdf, dated August 5, 2009)

260 mA

MCP 1.05V SATA Digital Power

20 mA

MCP 3.3V PCIe/SATA I/O PLL Power

MCP 3.3V DP & USB PLL Power

C2503

0.22UF

402

X5R

20%

6.3V

1UF

C2502

10%

402-1

X5R

10V 10V

402

CERM

20%

C2507

0.1UF0.1UF

402

CERM

10V

20%

C2506C2505

10V

0.1UF

402

CERM

20%

0.1UF

10V

20% CERM

402

C2504

0.1UF

402

10V

20%

C2508

CERM

X5R

10V

10%

1UF

402-1

C2531

4.7UF

402

X5R

20%

C2536

402

0.1UF

10V CERM

20%

C2519

20% 10V CERM 402

0.1UF

C2518

10V CERM 402

20%

C2517

0.1UF

10V CERM 402

20%

0.1UF

C2516

0.1UF

10V CERM 402

20%

C2515C2514

20% 10V

402

CERM

0.1UF

C2513

20% 10V CERM 402

0.1UF0.1UF

20% 10V CERM 402

C2512

20% 10V CERM 402

C2511

0.1UF

402

20% X5R

4.7UF

C2510

L2560

30-OHM-5A

0603

L2567

30-OHM-5A

0603

10UF

603-1

X5R

20%

6.3V

C2500 C2501

X5R

4V 402

4.7UF

20%

C2527

20% 10V CERM 402

0.1uF

10V

20% CERM

402

0.1uF

C2526

C2537

0.1uF

402

20% 10V CERM

0.1uF

10V CERM 402

20%

C2534

CERM

20% 10V

402

C2556

0.1UF

20% CERM

10V 402

C2529

0.1uF

402

X5R

20%

4.7uF

C2528

20% 10V CERM 402

0.1uF

C2549

20%

CERM

4.7UF

6.3V 603

C2548

0.1uF

20% 10V CERM 402

C2535

402

0.1uF

CERM

10V

20%

C2554

4.7uF

C2553

CERM

20%

6.3V 603

0.1uF

20% 10V CERM 402

C2551

20%

CERM

4.7uF

6.3V 603

C2550

C2543

20%

CERM

4.7uF

6.3V 603 402

20% 10V CERM

0.1uF

C2544

402

20% 10V CERM

0.1uF

C2545

0.1uF

20% 10V CERM 402

C2546

CERM

0.1uF

402

10V

20%

C2547

C2520

10UF

603-1

X5R

20%

6.3V

20% X5R

402

4.7UF

C2521

1UF

402-1

X5R

10V

10%

C2522

X5R

1UF

402-1

10V

10%

C2523 C2525

1UF

X5R

10V

10%

402-1

4.7UF

402

X5R

20%

C2524

4.7UF

CERM

20%

6.3V 603

C2555

C2560

6.3V

10UF

603-1

X5R

20%

4.7UF

C2561

4V 402

X5R

20%

402-1

C2562

1UF

X5R

10V

10% 10%

C2563

402-1

1UF

X5R

10V

20%

0.1UF

402

CERM

10V

C2564

C2567

6.3V

10UF

603-1

X5R

20%

C2568

4.7UF

X5R

4V 402

20%

C2569

20% 10V CERM 402

0.1UF

C2565

0.1UF

402

CERM

10V

20%

402

CERM

10V

20%

C2566

0.1UF

20% X5R

402

4.7UF

C2540

20%

402

CERM

10V

C2542

0.1uF

C2541

603

6.3V

4.7UF

CERM

20%

C2572

20% 10V CERM 402

0.1uF

C2571

402

CERM

10V

20%

0.1UF

PLACE_NEAR=R2570.1:50 mil

20%

4.7UF

C2570

4V X5R 402

0402

R2570

0.33

5% MF

1/16W

C2573

0.1UF

402

CERM

10V

20%

C2578

0.1UF

402

CERM

10V

20%

C2577

0.1uF

402

CERM

10V

20%

C2576

0.1UF

20% 10V

402

CERM

402

4V X5R

20%

C2575

4.7UF

0.1UF

20% 10V CERM

C2583

402402

CERM

10V

20%

C2582

0.1uF

C2581

CERM

0.1UF

20%

402

10V X5R 402

20%

4.7UF

C2580

C2579

20% 10V CERM 402

0.1UF

CERM 402

20% 10V

0.1UF

C2584

4.7UF

C2552

603

6.3V

20%

CERM

0603

L2570

220-OHM-2.2A

CRITICAL

L2580

220-OHM-2.2A

0603

CRITICAL

0603

220-OHM-2.2A

L2575

CRITICAL

0402

FERR-240-OHM-200MA

L2555

C2530

2.2UF

6.3V

20%

402-LF

CERM

402-LF

C2533

6.3V CERM

2.2UF

20%

C2532

CERM

6.3V

20%

402-LF

2.2UF

X5R 402

Place close to SMC

6.3V

20%

0.22UF

C2598

HTOL_SENSE:YES

R2598

HTOL_SENSE:YES

402

1% 1/16W MF-LF

4.53K

Place close to SMC

0.1UF

20% 10V CERM 402

C2591

Q2592

CRITICAL

HTOL_SENSE:YES

SOT-563-HF

NTZD3152P

OPA330

SC70-5

HTOL_SENSE:YES

U2593

CRITICAL

402

HTOL_SENSE:YES

R2597

MF-LF

1/16W

OPA330

U2594

SC70-5

CRITICAL

HTOL_SENSE:YES

20%

CERM

603

6.3V

4.7UF

C2590

1/16W

R2590

1% MF-LF 402

HTOL_SENSE:YES

845K

L2590

0402

FERR-240-OHM-200MA

CRITICAL

0.1uF

C2597

20% 10V

402

CERM

402

20%

C2594

10V CERM

0.1UF

HTOL_SENSE:YES

R2599

402

MF-LF

1/16W

100K

R2596

402

MF-LF

1/16W

HTOL_SENSE:YES

CRITICAL

SOT-563-HF

NTZD3152P

Q2592

HTOL_SENSE:YES

10% 10V

402

X5R

1UF

C2592

MCPHVDD:P2V5

C2596

0.1UF

402

20% CERM

10V

4.7UF

CERM

20%

6.3V 603

C2595

PLACE_NEAR=R2595.1:50 mil

0402

1/16W

0.33

5% MF

R2595

20%

402

CERM

0.1UF

HTOL_SENSE:YES

C2599

10V

402

1/16W

MF-LF

10K

LDO:ADJ

R2594

MF-LF

LDO:ADJ

10K

402

R2591

1/16W

MCPHVDD:P3V3

MF-LF

402

R2593

1/16W

OMIT_TABLE

SC70

U2592

CRITICAL

MIC5365-2.5V

0603

L2595

220-OHM-2.2A

CRITICAL

MCPHVDD:P2V5

X5R 402

C2593

1UF

10% 10V

MCPHVDD:P2V5

402

R2592

MF-LF

1/16W

10K

1/16W MF-LF

402

R2550

353S2979

IC,LDO,TPS717,ADJ,150MA,3%,SC70,HFLF

CRITICAL

LDO:ADJ

U2592

353S2987

IC,TPS71725,LDO REG,2.5V,150MA,SC70

LDO:FIXED

U2592

CRITICAL

RES,0402,0,5%,1/16W

116S0004

R2596

HTOL_SENSE:NO

CRITICAL

SYNC_MASTER=(T27_MLB)

MCP Standard Decoupling

SYNC_DATE=(11/16/2009)

=PP3V3_S0_MCP_PLL_UF

=PP1V05_S0_MCP_PE_DVDD

=PP3V3_ENET_MCP_RMGT

SMC_N_MIRROR

SMC_NB_MISC_ISENSE

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM VOLTAGE=3.3V

PP3V3_S0_MCP_PLL_HVDD

=PP1V05_SW_MCP_FSB

=PP1V05_S0_MCP_M2CLK_DLL

=PP3V3_S5_MCP

=PP1V05_S0_MCP_FSB

=PP1V5R1V35_SW_MCP_MEM

PP3V3_G3_RTC

=PP3V3_S0_MCP_HVDD

VOLTAGE=1.05V

MIN_LINE_WIDTH=0.4 MM

PP1V05_S0_MCP_PE_AVDD

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM

PP1V05_S0_MCP_SATA_AVDD

VOLTAGE=1.05V

=PP1V05_S0_MCP_AVDD_UF

PP1V05_S0_MCP_PLL_FSBMEM

VOLTAGE=1.05V

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM

VOLTAGE=1.05V

PP1V05_S0_MCP_PLL_PEXSATA

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM

=PP3V3_S0_MCP

=PP3V3R1V5_S0_MCP_HDA

=PP3V3_ENET_MCP_PLL_MAC

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM VOLTAGE=3.3V

PP3V3_ENET_MCP_PLL_MAC

SMC_N_FOLLOW

GND_SMC_AVSS

=PP0V9_ENET_MCP_RMGT

MIN_LINE_WIDTH=0.25 MM

GND_MCP_PLL_FSB

MIN_NECK_WIDTH=0.25 MM VOLTAGE=0V

SMC_P_FOLLOW

OPA_MIRROR_OUT

=PP0V9_S5_MCP_VDD_AUXC

=PP1V05_S0_MCP_PLL_UF

PP1V05_S0_MCP_PLL_CORE

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V

=PP3V3_S0_OPA330

SMC_P24

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM

PP3V3_S0_MCP_HVDD

GND_MCP_PLL_DP_USB

MIN_LINE_WIDTH=0.25 MM VOLTAGE=0V

MIN_NECK_WIDTH=0.25 MM

MCP_PLL_LD0_EN

=PP1V05_S0_MCP_SATA_DVDD

LDO_ADJ

=PP3V3_S0_OPA330

PP3V3_S0_LDO_R

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM VOLTAGE=3.3V

PP3V3_S0_LDO_R_BRDG

MIN_LINE_WIDTH=0.4 MM

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2 MM

=PPVCORE_S0_MCP

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM

PP3V3_S0_MCP_PLL_DP_USB

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