Apple MacBook Air 13'' 2020 A2179 Schematics

8

www.laptoprepairsecrets.com

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.

3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

7

6 5 4 3

X1783 MLB-TKSB

LAST_MODIFICATION=Mon Jul 29 19:28:46 2019

LAST_MODIFICATION=Mon Jul 29 19:28:46 2019

2 1

ECNREV DESCRIPTION OF REVISION

CK
APPD

DATE

2019-07-2900189634452 ENGINEERING RELEASED

D

1 1
2
3

2
3

5 5
6
7
8
9
10

6
7
8
9
10

11
12
13

13

14

BOM Configuration
BOM Configuration
PD Parts44
CPU GFX
CPU Misc/JTAG/CFG/RSVD
CPU LPDDR4 Interface
CPU Power
PCH Power
CPU & PCH Grounds
CPU Decoupling
PCH Decoupling
PCH ESPI/SMBUS/UART

LKS

MASTER
CPU_CARD_ICL_Y
CPU_CARD_ICL_Y
CPU_CARD_ICL_Y
CPU_CARD_ICL_Y
CPU_CARD_ICL_Y
CPU_CARD_ICL_Y
CPU_CARD_ICL_Y
CPU_CARD_ICL_Y

11/09/2018Table of Contents

06/08/2018
06/08/2018
06/08/2018
06/08/2018
06/08/2018
06/08/2018
06/08/201811
06/08/2018
06/08/2018

DATESYNCCONTENTSCSAPAGEDATESYNCCONTENTSCSAPAGE

51
52
53
54
55
56
57 06/29/2018
58
59
60
61
62 78
63

65
66
67

Keyboard Backlight 04/15/2019
Audio Connectors

Keyboard & Trackpad 1
68 Keyboard & Trackpad 2
69
70
71
72
74
76
77

DC-In & Battery Connectors

PBUS Supply & Battery Charger

IMVP9 IC

IMVP9 POWER BLOCK

VR: VCCIN_AUX ISL 06/08/2018

VR - 5V, 3V3

VR: VCCPRIM_1P8

PMIC BUCKS AND SWs
79

PMIC LDOs

X1032_MLB_P4BP
AHAAGE_AUD
X260_MLB
X589_CARD_IPD
psm
X1032_MLB_P4BP
J140 MLB (CNL-Y)
psm
CPU_CARD_ICL_Y
J140
psm
X589_BIGSUR
X589_BIGSUR

04/19/2017
02/16/2017
02/16/2017
10/18/2018
02/13/2017

10/18/2018

08/17/2018
10/18/2018
03/16/2017
03/16/2017

D

C

14 06/08/2018

16
17
18
19

21
22
23
24
25
26 USB-C CONNECTOR
27

15
16 PCH PCIe/USB/CLK15
18
19
20
23
25
28
29
30
31
32
33
34

PCH Power Management

CPU/PCH Merged XDP
Chipset Shared Support
Chipset Project Support
LPDDR4x Sub-Channels A & B
LPDDR4x Sub-Channels C & D
USB-C HIGH SPEED X (REAR)
USB-C HIGH SPEED T (FRONT)
USB-C Support
USB-C PORT CONTROLLER X (REAR)
USB-C PORT CONTROLLER T (FRONT)

USB-C DEV SUPPORT

CPU_CARD_ICL_Y
CPU_CARD_ICL_Y
X589_CPU_CNL_Y
CPU_CARD_ICL_Y
CARD_CPU_ICL_YN
J140
J140
CPU_CARD_ICL_Y
CPU_CARD_ICL_Y
CPU_CARD_ICL_Y
CPU_CARD_ICL_Y
CPU_CARD_ICL_Y
X1032_MLB_P4BP

06/08/2018
03/13/2017
06/08/2018
06/08/2018
08/23/2018
08/23/201820
06/08/2018
06/08/2018
06/08/2018
06/08/2018
06/08/2018
02/13/2017
06/11/2018

64
65
66
67
68
69
70
71
72
73
74

76
77

PMIC GPIOs & Control
81 POWER - MEMORY VRs
82
83
84

Power FETs

Power FETs TBT S0

LCD Backlight Driver
85
86
87
90
91

S4E<0> 09/27/2018

S4E<1>

NAND VCC VR

SSD Support
120 Power Aliases - 1
121
122

Power Aliases - 2

Signal Aliases

Memory Bit & Byte Swizzle123

X589_BIGSUR
X589_CPU_CNL_Y
X589_CPU_CNL_Y
CPU_CARD_ICL_Y
X1032_MLB_P4BP
X1032_MLB_P4BP
j213
j213
psm

X589_CPU_CNL_Y
X589_CPU_CNL_Y

J140

03/16/201780
10/12/2018
02/22/2017
06/08/2018
02/13/2017
12/06/2018eDP Display Connector

09/27/2018
10/18/2018

02/21/2017
02/21/201775

08/23/2018

C

B

28

31
32
33
34
35
36
37
38
39
40 SoC Project Support
41

36
3729
38
39
40
41
42

44
45
46
47
48
50

WIFI/BT Desense
WIFI/BT MODULE 1
WIFI/BT MODULE 230
SoC GPIO/SEP/USB/DDR/Test
SoC AOP/AON/SMC 03/16/2017
SoC ISP/I2C/UART/SPI/I2S
SoC PCIe
SoC Power 1
SoC Power 2 86 152 Power Block Diagram
SoC Power 3
SoC Ground
SoC Shared Support

Secure Element

j140
J213_METE
J213_METE
X589_BIGSUR
X589_BIGSUR
X589_BIGSUR
X589_BIGSUR
X589_BIGSUR
X589_BIGSUR
X589_BIGSUR
X589_BIGSUR
X589_BIGSUR
X589_BIGSUR
X941_MLB

09/20/2018
11/04/2018
10/17/2018
03/15/2017

03/15/2017
03/15/2017
02/13/201743
02/13/2017
02/13/2017
02/13/2017
03/16/2017
02/13/2017
03/10/2017

78
79
80
81
82

84

124
127
128
140
141
142
143
14585

ICT FCT

Desense Caps 1

Desense Caps 2

Dev Support

BOM Variants 1

BOM Variants 283

BOM Variants 3

BOM Alternates

X589_BIGSUR

04/12/2017

B

A

42
43
44
45
46
47 Thermal Sensors
48
49
50

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

SCH,MLB-TKSB,X1783051-05232 1 CRITICALSCH SCHEM

PCBF,MLB-TKSB,X1783820-01958 1 CRITICALMLB PCBF

J230GHUB = https://github.pie.apple.com/MobileMacIX/j230_hw/blob/master/

52
53
54
55
56
58
60
61
64

I2C Connections 1
I2C Connections 2
Power Sensors High Side

Power Sensors Extended

Fans
RIO Connector
Audio Speaker Amplifiers

BOM OPTIONCRITICAL

TABLE_5_HEAD

TABLE_5_ITEM

TABLE_5_ITEM

X589_BIGSUR
X589_BIGSUR
psm
X1032_MLB_P4BP

X1032_MLB_P4BP
X1032_MLB_P4BP

AHAAGE_AUD

RULER_RULE_SET=RIGID_2016

MULTIPLES

1,1.5,1.75,2.6,2-7,7.5,8,9,10

ISL2-ISL3,ISL6,ISL9,ISL12-ISL13 3.125 1.23.125

02/13/2017
02/13/2017
10/18/2018
02/14/2017Power Sensors Load Side

02/14/2017
02/13/2017

05/23/2017

MANUFACTURING CONFIGURATION

DIELECTRIC BASED SPACING RULES

SMDPIN2SMDPIN MAX(UM)MVIA MAX(UM)SMDPIN MAX(UM)

LAYERS

TOP,BOTTOM 2.82.8 1.0

ISL4,ISL11 3.125 1.23.125

ISL5,ISL10 1.22.2722.272

2.23ISL7,ISL8 1.32.23

MINIMUM CU SPACING RATIOMINIMUM TO DEFAULT RATIOMINIMUM CU WIDTH RATIO

DEFAULT SPACING

MULTIPLES

TABLE_REV_NUMBER=1

VOID SPACE

RATIO

2180 8080

DRAWING TITLE

SCHEM,MLB-TKSB,X1783

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

051-05232

REVISION

2.0.0

BRANCH

proto4b

PAGE

1 OF 152

SHEET

1 OF 86

A

SYNC_DATE=11/09/2018SYNC_MASTER=LKS

SIZEDRAWING NUMBER

D

8

3

124567

678

www.laptoprepairsecrets.com

3 245

1

D

C

B

A

Module Parts

CPU

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

1 CRITICAL337S00749

CPU,ICL-YN,QSLN,D1,64EU,1.0,1.1,BGA1044

1 CRITICALU0500337S00750

CPU,ICL-YN,QSLQ,D1,48EU,0.7,1.05,BGA1044

998-17650 1 U0500

337S00766 1 U0500 CRITICAL CPU_ICLY:BEST

337S00767 1 CRITICALU0500 CPU_ICLY:BEDRE

INTERPOSER,VTT ADAPTER,ICL-YN,BGA1044

CPU,ICLYN,QSEQ,EES,D2,1,1.1,BGA1044

CPU,ICLYN,QSES,EES,D2,.7,1.05,BGA1044

1 CRITICALU0500 CPU_ICLY:GOOD337S00765

CPU,ICLYN,QSVZ,EES,D2,1.1,.9,BGA1044

NOTE: BEDRE is Danish for BETTER.

TBT Burnside Bridge

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

IC,BURNSIDE BRIDGE,USB/TB RETIMER,BGA105

998-13316 U2800,U2900

2 TBT_BB:A0CRITICAL

IC,TBT,BURNSIDE BRDGE,QURW,ES2,A1,BGA105

2 U2800,U2900

IC,TBT,BURNSIDE BRDGE,ES2,QS,A1,BGA105

IC,TBT,BURNSIDE BRDGE,PRQ,A1,BGA105

U2800,U29002

CRITICAL TBT_BB:A1338S00503

Ace2

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

353S01826 CRITICALU3100,U32002

353S01960 2

353S02158 ACE2:B12_BGA

IC,CD3217,ACE2,B1,USB PWR SW W/HV,BGA123

IC,CD3217,ACE2,B2,USB PWR SW W/HV,BGA123

IC,CD3217,ACE2,B1,USB PWR SW W/HV,BGA123

CRITICAL ACE2:B2_BGAU3100,U3200

CRITICAL2 U3100,U3200

SOC

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

POP,GIBRALTAR+1GB 20NM,M,B0,SCK,CSP1406

PART NUMBER

U3900339S00370 1 SOC:B0_1GCRITICAL

TABLE_ALT_HEAD

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

TABLE_ALT_ITEM

Hynix 1GB SCKALLSOC:B0_1G339S00370339S00371

TABLE_ALT_ITEM

ALL Micron 1GB SCK339S00370339S00375 SOC:B0_1G

TABLE_ALT_ITEM

ALL Hynix 1GB ATK339S00370339S00376 SOC:B0_1G

POP,GIBRALTAR+2GB 20NM,M,B0,SCK,CSP1406

PART NUMBER

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

CRITICAL SOC:B0_2G339S00372 U39001

TABLE_ALT_HEAD

TABLE_ALT_ITEM

ALL339S00372339S00373 Hynix 2GB SCKSOC:B0_2G

TABLE_ALT_ITEM

Micron 2GB SCKALLSOC:B0_2G339S00372339S00377

TABLE_ALT_ITEM

Hynix 2GB ATKALLSOC:B0_2G339S00372339S00378

PMU

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

IC,PMU,CALPE,D2249A0,OTP-AI,CSP324,0.4P

Wireless

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

MODULE,WIFI/BT,SAPPORO,ES3.1,M,LGA451

1

PART NUMBER

998-16405 ALLWIRELESS:P0339S00616

339S00616 1 WIRELESS:P1U3701 CRITICAL

MODULE,WIFI/BT,SAPPORO,ES3.1,M,LGA451

PART NUMBER

339S00628 339S00616 ALLWIRELESS:P1

MODULE,WIFI/BT,SAPPORO,ES3.1,M,LGA451

PART NUMBER

339S00632 WIRELESS:P1B ALL339S00616

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

USI Wireless Module (ES2)

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

USI Wireless Module (ES2)

U3701

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

USI Wireless Module (ES3.1)

CRITICAL339S00616 WIRELESS:P0U3701

TABLE_ALT_HEAD

TABLE_ALT_ITEM

TABLE_ALT_HEAD

TABLE_ALT_ITEM

TABLE_ALT_HEAD

TABLE_ALT_ITEM

BOM OPTIONCRITICAL

CPU_ICLY_P2:BESTU0500

CPU_ICLY_P2:GOOD

CPU_ICLY:INTERPOSERCRITICAL

BOM OPTIONCRITICAL

TBT_BB:QSA1338S00508 2 CRITICALU2800,U2900

TBT_BB:PRQA1338S00561 CRITICAL

BOM OPTIONCRITICAL

ACE2:B1_BGA

BOM OPTIONCRITICAL

BOM OPTIONCRITICAL

PMU:A0_ACRITICALU78001338S00267

BOM OPTIONCRITICAL

WIRELESS:P1BCRITICAL1339S00616

TABLE_5_HEAD

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_HEAD

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_HEAD

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_HEAD

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_HEAD

TABLE_5_ITEM

TABLE_5_HEAD

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

NAND - Landing 0

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

NAND,3DV4,64GBT,S4E,256G,H,SUBX,SLGA110

TABLE_ALT_HEAD

PART NUMBER

998-17175998-17176

NAND,3DV4,64GBT,S4E,256G,T,SUB X,SLGA110

NAND_L0:ITLC_128G_HY

U8600

PART NUMBER

998-16395 U8600

335S00416 CRITICAL1

998-16396 NAND_L0:ITLC_256G_TO

998-16394

NAND,3DV5,64GBT,S4E,256G,SS,SLGA110

NAND,3DV4,128GBT,S4E,256G,T,SUBX,SLGA110

NAND_L0:ITLC_128G_TO

PART NUMBER

998-16396998-16397

NAND,3DV4,128GBT,S4E,256G,SD,SUBX,BGA110

NAND_L0:ITLC_256G_TO

U8600

PART NUMBER

998-16945998-16970

NAND,3DV4,128GBT,S4E,256G,H,SLGA110

NAND,3DV4,256GBT,S4E,256G,T,SUBX,SLGA110

NAND_L0:ITLC_256G_SD

U8600

PART NUMBER

998-16400 U8600998-16401

335S00397 1 U8600

335S00408 CRITICAL

335S00391 1

335S00380 CRITICAL

335S00433 CRITICALU8600

NAND,3DV4,320GBT,XXX,S4E,256G,T,SLGA110

NAND,3DV4,320GBT,XXX,S4E,256G,SD,SLGA110

NAND,3DV4,512GBT,XXX,S4E,256G,SD,SLGA110

NAND,3DV4,512GBT,S4E,256G,H,SLGA110

NAND,3DV4,1TBT,XXX,S4E,512G,SD,SLGA110

NAND,3DV5,1024GBT,S4E,512G,H,SLGA110

NAND_L0:ITLC_512G_TO

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

TABLE_ALT_ITEM

HY 64G Substrate 2 L0

CRITICAL1 U8600

TABLE_ALT_HEAD

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

TABLE_ALT_ITEM

TO 64G Substrate 2 L0

CRITICAL1 U8600

TABLE_ALT_HEAD

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

TABLE_ALT_ITEM

TO 128G Substrate 2 L0

U86001998-16945 CRITICAL NAND_L0:ITLC_256G_SD

TABLE_ALT_HEAD

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

TABLE_ALT_ITEM

SD 128G Substrate 2 L0

U8600

TABLE_ALT_HEAD

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

TABLE_ALT_ITEM

TO 256G Substrate 2 L0

CRITICAL

U86001 NAND_L0:ITLC_512G_SD

U86001 NAND_L0:ITLC_1P0T_HY

CRITICALU86001

BOM OPTIONCRITICAL

NAND_L0:ITLC_128G_HYCRITICALU86001998-17175

NAND_L0:ITLC_128G_TO998-16394

NAND_L0:ITLC_128G_SSU8600

NAND_L0:ITLC_256G_HY1 CRITICAL335S00378

NAND_L0:ITLC_512G_TOU8600998-16400 CRITICAL1

NAND_L0:ITLC_512G_TO_P1

NAND_L0:ITLC_1P0T_SDU8600 CRITICAL

NAND_L0:ITLC_2P0T_SD1

NAND_L0:ITLC_2P0T_HY335S00444

NAND - Landing 1

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

998-17175 NAND_L1:ITLC_128G_HYCRITICAL1 U8700

998-17176 998-17175

998-16394 NAND_L1:ITLC_128G_TO

998-16395 U8700

335S00416 CRITICAL

998-16396 1 NAND_L1:ITLC_256G_TO

998-16397 998-16396 U8700

998-16971 998-16946 U8700

335S00391 NAND_L1:ITLC_1P0T_SD

335S00444

NAND,3DV4,64GBT,S4E,256G,H,SUBX,SLGA110

PART NUMBER

NAND,3DV4,64GBT,S4E,256G,T,SUB X,SLGA110

PART NUMBER

998-16394

NAND,3DV5,64GBT,S4E,256G,SS,SLGA110

NAND,3DV4,128GBT,S4E,256G,T,SUBX,SLGA110

PART NUMBER

NAND,3DV4,128GBT,S4E,256G,SD,SUBX,BGA110

PART NUMBER

998-16945998-16970

NAND,3DV4,128GBT,S4E,256G,H,SLGA110

NAND,3DV4,256GBT,XXX,S4E,256G,T,SLGA110

1 CRITICALU8700335S00396

NAND,3DV4,256GBT,S4E,256G,SD,SUBX,BGA110

PART NUMBER

NAND,3DV4,512GBT,XXX,S4E,256G,SD,SLGA110

NAND,3DV4,512GBT,S4E,256G,H,SLGA110

1 U8700 CRITICAL NAND_L1:ITLC_1P0T_HY335S00380

NAND,3DV4,1TBT,XXX,S4E,512G,SD,SLGA110

NAND,3DV5,1024GBT,S4E,512G,H,SLGA110

NAND_L1:ITLC_128G_HY

NAND_L1:ITLC_128G_TO

NAND_L1:ITLC_256G_TO

NAND_L0:ITLC_256G_SD

NAND_L1:ITLC_512G_SD

U8700

U8700

TABLE_ALT_HEAD

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

TABLE_ALT_ITEM

HY 64G Substrate 2 L1

CRITICALU87001

TABLE_ALT_HEAD

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

TABLE_ALT_ITEM

TO 64G Substrate 2 L1

U87001 NAND_L1:ITLC_128G_SS

U8700 CRITICAL

TABLE_ALT_HEAD

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

TABLE_ALT_ITEM

TO 128G Substrate 2 L1

U87001998-16945

CRITICAL NAND_L1:ITLC_256G_SD

TABLE_ALT_HEAD

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

TABLE_ALT_ITEM

SD 128G Substrate 2 L1

CRITICAL1998-16946 U8700 NAND_L1:ITLC_512G_SD

TABLE_ALT_HEAD

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

TABLE_ALT_ITEM

SD 128G Substrate 2 L1

U87001 CRITICAL

U8700 NAND_L1:ITLC_2P0T_SD

CRITICAL1335S00433

BOM OPTIONCRITICAL

NAND_L1:ITLC_256G_HY335S00378 U87001 CRITICAL

NAND_L1:ITLC_512G_SSUB_TO

NAND_L1:ITLC_2P0T_HYU87001 CRITICAL

DRAM

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

IC,LPDDR4X-3733,32GBIT,18NM,S,BGA432

333S00138 U2300,U2500 DRAM:P1_SAMSUNG_16GB

333S00221

333S00222

2 CRITICAL

IC,LPDDR4X-3733,64GBIT,18NM,S,BGA432

IC,LPDDR4X-4266,32GBIT,16NM,S,BGA432

IC,LPDDR4X-4266,64GBIT,16NM,S,BGA432

2 U2300,U2500 DRAM:HYNIX_8GBCRITICAL333S00214

IC,LPDDR4X-4266,32GBIT,19NM,H,BGA432

IC,LPDDR4X-4266,64GBIT,19NM,H,BGA432

IC,LPDDR4X-3733,32GBIT,18NM,BGA432

IC,LPDDR4X-3733,64GBIT,18NM,BGA432

U2300,U25002 CRITICAL DRAM:HYNIX_16GB333S00215

U2300,U2500333S00170 2 DRAM:MICRON_8GBCRITICAL

U2300,U2500333S00171 2

CRITICAL2 U2300,U2500333S00137 DRAM:P1_SAMSUNG_8GB

CRITICAL2 DRAM:SAMSUNG_8GBU2300,U2500

CRITICAL DRAM:SAMSUNG_16GB2 U2300,U2500

CRITICAL DRAM:MICRON_16GB

BOM OPTIONCRITICAL

TABLE_5_HEAD

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_HEAD

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_HEAD

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

Programmables

TBT ROM

335S00232

341S01315

341S01337

341S01410

341S01450

341S01470

1 TBT_ROM:BLANKU3060 CRITICAL335S00133

IC,SPI SERIAL FLASH,8MBITS,3.0V,USON8

PART NUMBER

335S00133

1

IC,NVM (V14.1) PROTO-0,X1418

ROM,TBT (V14.1.1) PROTO-0-2,X1418

ROM,TBT (VXXXXXX) PROTO-0-3,X1418

ROM,TBT (V14.4) PROTO-1,X1418

1

ROM,BBR (VXXXX) PROTO-2,X1418

ROM,BBR,ACE (V18.9) PROTO-3,X1418

ROM,BBR,ACE (V29.3) PROTO-4A,X1783

ROM,BBR/ACE (VXXXX) PROTO-4,X1783

TBT_ROM:BLANK

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

U3060

TABLE_ALT_HEAD

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

TABLE_ALT_ITEM

rdar://problem/50598337

CRITICAL TBT_ROM:P1U3060

U3060

U30601 CRITICAL TBT_ROM:P3

U30601 TBT_ROM:P4ACRITICAL

CRITICAL1 U3060

BOM OPTIONCRITICAL

TBT_ROM:P0U3060 CRITICAL341S01282

TBT_ROM:P0A1 U3060 CRITICAL341S01314

TBT_ROM:P0B1 CRITICALU3060

TBT_ROM:P2CRITICAL1

TBT_ROM:P4B341S01515

BT ROM

341S01260

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

IC,SPI SERIAL FLASH,4M BIT,1.8V,USON8

1 CRITICAL335S00400 BT_ROM:BLANKU3750

ROM,BT SFLASH (VXX) PROTO-1,X1536

CRITICAL BT_ROM:P01 U3750

BOM OPTIONCRITICAL

Wifi ROM

1

IC,EEPROM,SER,UWIRE,16K,1.8V,DFN8

1

IC,WIFI ROM (V00) WW1,X1421

ROM,WIFI (VXX) (NEW FOR DVT) WW1,X1536

1 CRITICALU3710341S01394

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

CRITICALU3710 WIFI_ROM:BLANK335S00214

BOM OPTIONCRITICAL

WIFI_ROM:P0U3710 CRITICAL341S01087

WIFI_ROM:P2

SOC ROM

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

335S00203 U47701 CRITICAL SOC_ROM:BLANK

IC,FLASH,SERIAL,SPI,4MX8,1.8V,4X3MM,DFN8

PAGE TITLE

BOM OPTIONCRITICAL

BOM Configuration

DRAWING NUMBER

051-05232

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

REVISION

2.0.0

BRANCH

proto4b

PAGE

2 OF 152

SHEET

2 OF 86

TABLE_5_HEAD

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_HEAD

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_HEAD

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_HEAD

TABLE_5_ITEM

D

C

B

A

SIZE

D

8

67

35 4

2

1

678

www.laptoprepairsecrets.com

3 245

1

D

BOM Groups

BOM GROUP BOM OPTIONS

MLB_COMMON

MLB_PROGPARTS

MLB_POWER

MLB_MECH
MLB_MISC

MLB_TBT

MLB_TBT_OPTS

MLB_DESENSE DES:INTER

SCHEM,PCBF,ALTERNATE,COMMON,MLB_PROGPARTS,MLB_USBC,MLB_POWER,MLB_WIRELESS,MLB_MECH,MLB_MISC,MLB_TBT,MLB_TBT_OPTS,PROTO4

TBT_BB:PRQA1,ACE2:B12_BGAMLB_USBC

BT_ROM:P0,SOC_ROM:BLANK,TBT_ROM:P4B,WIFI_ROM:P2,SE:DEV_SW_N

WIRELESS:P1BMLB_WIRELESS

BRACKET,SHLD_CAN_DRAM,SHLD_CAN_BSB,SHLD_FNC_SOC

BOARDID0,BOARDID1,BOARDID2,BOARDID3,BOARDID4,BOARDID5,SYSDET:FET,BOOTCFG0,RAMCFG3_L,RAMCFG4_L

BSB_X_PWR:SWSW_VOUTLV,BSB_T_PWR:SWSW_VOUTLV,BSB_PERST:PLTRST

BSB_FORCE_PWR:ACE,BSB_GP6:BSB_S0

CPUCFG:STRAPSMLB_CPUCFG

See <rdar://problem/50175583> for BOARDID straps

PMU:A0_A

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_5_HEAD

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

CBOM CRITICAL CMN_PARTS_BOM685-00329 COMMON PARTS,MLB-TKSB,X17831

CRITICAL1 DEV_PARTS_BOMDEV1985-01143 DEV PARTS,MLB-TKSB,X1783

BOM OPTIONCRITICAL

TABLE_5_ITEM

TABLE_5_ITEM

D

C

https://confluence.sd.apple.com/display/EMBEDDEDPLATFORM/BOARD_ID+Allocation

Build Specific Groups

BOM GROUP BOM OPTIONS

PROTO4

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

BOARDREV0

C

B

NAND Configs

BOM GROUP BOM OPTIONS

NANDCFG:ITLC_S4E_128G_HY
NANDCFG:ITLC_S4E_128G_TO
NANDCFG:ITLC_S4E_128G_SS
NANDCFG:ITLC_S4E_256G_TO
NANDCFG:ITLC_S4E_256G_SD
NANDCFG:ITLC_S4E_256G_HY
NANDCFG:ITLC_S4E_512G_TO
NANDCFG:ITLC_S4E_512G_SD
NANDCFG:ITLC_S4E_1P0T_SD
NANDCFG:ITLC_S4E_1P0T_HY
NANDCFG:ITLC_S4E_2P0T_SD
NANDCFG:ITLC_S4E_2P0T_HY

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

NAND_L0:ITLC_128G_HY,NAND_L1:ITLC_128G_HY,SOC:B0_1G,S4E,SSD_PWR:S4E

TABLE_BOMGROUP_ITEM

NAND_L0:ITLC_128G_TO,NAND_L1:ITLC_128G_TO,SOC:B0_1G,S4E,SSD_PWR:S4E

TABLE_BOMGROUP_ITEM

NAND_L0:ITLC_128G_SS,NAND_L1:ITLC_128G_SS,SOC:B0_1G,S4E,SSD_PWR:S4E

TABLE_BOMGROUP_ITEM

NAND_L0:ITLC_256G_TO,NAND_L1:ITLC_256G_TO,SOC:B0_1G,S4E,SSD_PWR:S4E

TABLE_BOMGROUP_ITEM

NAND_L0:ITLC_256G_SD,NAND_L1:ITLC_256G_SD,SOC:B0_1G,S4E,SSD_PWR:S4E

TABLE_BOMGROUP_ITEM

NAND_L0:ITLC_256G_HY,NAND_L1:ITLC_256G_HY,SOC:B0_1G,S4E,SSD_PWR:S4E

TABLE_BOMGROUP_ITEM

NAND_L0:ITLC_512G_TO_P1,NAND_L1:ITLC_512G_SSUB_TO,SOC:B0_1G,S4E,SSD_PWR:S4E

TABLE_BOMGROUP_ITEM

NAND_L0:ITLC_512G_SD,NAND_L1:ITLC_512G_SD,SOC:B0_1G,S4E,SSD_PWR:S4E

TABLE_BOMGROUP_ITEM

NAND_L0:ITLC_1P0T_SD,NAND_L1:ITLC_1P0T_SD,SOC:B0_2G,S4E,SSD_PWR:S4E

TABLE_BOMGROUP_ITEM

B

NAND_L0:ITLC_1P0T_HY,NAND_L1:ITLC_1P0T_HY,SOC:B0_2G,S4E,SSD_PWR:S4E

TABLE_BOMGROUP_ITEM

NAND_L0:ITLC_2P0T_SD,NAND_L1:ITLC_2P0T_SD,SOC:B0_2G,S4E,SSD_PWR:S4E

TABLE_BOMGROUP_ITEM

NAND_L0:ITLC_2P0T_HY,NAND_L1:ITLC_2P0T_HY,SOC:B0_2G,S4E,SSD_PWR:S4E

A

CPU DRAM SPD Straps

BOM GROUP BOM OPTIONS

DRAMCFG:SAMSUNG_8GB

DRAMCFG:SAMSUNG_16GB

DRAMCFG:HYNIX_8GB
DRAMCFG:HYNIX_16GB
DRAMCFG:MICRON_8GB

DRAMCFG:MICRON_16GB

DRAM:SAMSUNG_8GB,RAMCFG0_L
DRAM:SAMSUNG_16GB,RAMCFG0_L,RAMCFG2_L
DRAM:HYNIX_8GB,RAMCFG0_L,RAMCFG1_L
DRAM:HYNIX_16GB,RAMCFG0_L,RAMCFG1_L,RAMCFG2_L
DRAM:MICRON_8GB
DRAM:MICRON_16GB,RAMCFG2_L

RAMCFGx strap is low if in table.

CPU DRAM CFG Chart

Vendor

Hynix
Samsung
Unused
Micron

CFG 1

0
1
0
1

CFG 0

0
0
1
1

Vendor

8GB
16GB

CFG 2

1
0

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

PAGE TITLE

BOM Configuration

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

051-05232

REVISION

2.0.0

BRANCH

proto4b

PAGE

3 OF 152

SHEET

3 OF 86

A

SIZE

D

8

67

35 4

2

1

678

www.laptoprepairsecrets.com

3 245

1

Shield Cans

D

Mounting Bracket

806-22435

BRKT,MOUNTING,MLB,NK,X1766

DRAM Shield Can

TABLE_5_HEAD

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

BOM OPTIONCRITICAL

TABLE_5_ITEM

SHIELD CAN,DRAM,X1030

BRACKETCRITICALBRKT11

1 CRITICALSHLD1 SHLD_CAN_DRAM806-12387

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

BOM OPTIONCRITICAL

TABLE_5_HEAD

TABLE_5_ITEM

D

Burnside Bridge Shield Can

TABLE_5_HEAD

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

806-19070 SHLD31 CRITICAL SHLD_CAN_BSB

SHIELD CAN,BURNSIDE BRIDGE,X1419

BOM OPTIONCRITICAL

TABLE_5_ITEM

C

Mounting Holes

998-19374

SH0400

TH-NSP

1

SL-3.41X2.0-5.91X4.5

SH0401

TH-NSP

1

SL-3.41X2.0-5.91X4.5

Heatsink Mounting Bosses

860-01043

SH0410

5.0OD1.85ID-1.5H-SM1

1

SH0411

5.0OD1.85ID-1.5H-SM1

1

SH0412

5.0OD1.85ID-1.5H-SM1

1

SOC/NAND Shield Fence

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

SHIELD FRAME,GIBRALTAR,X1419

TABLE_5_HEAD

BOM OPTIONCRITICAL

TABLE_5_ITEM

SHLD_FNC_SOCSHLD4 CRITICAL1806-19074

C

B

998-11114998-11113 860-00974

SH0402

4.6R1.7-NSP 4.6X5.2R1.7X2.3-NSP

1

SH0403

1

SH0413

5.0OD1.85ID-1.5H-SM1

1

Antenna Cowling Bosses

SH0420

5.25X2.8R-1.4ID-1.81H-SM

1

B

A

8

67

A

PAGE TITLE

PD Parts

DRAWING NUMBER

051-05232

Apple Inc.

REVISION

2.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=MECHANICALS

35 4

IV ALL RIGHTS RESERVED

2

BRANCH

proto4b

PAGE

4 OF 152

SHEET

4 OF 86

1

SIZE

D

D

www.laptoprepairsecrets.com

678

3 245

1

CRITICAL

OMIT_TABLE

D

C

eDP Port Assignment:

Internal panel

69

69

69

69

69

69

69

69

69

69

23 16 5

23 16 5

23 16 5

23 16 5

18

18 5

69 5

69 5

78 68 5

78 69

OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

BI
BI

OUT
IN

OUT
IN

IN
IN
IN

OUT
OUT
OUT

U0500

ICL_YN

BGA

SYM 1 OF 15

DP_INT_ML_C_P<3>
DP_INT_ML_C_N<3>
DP_INT_ML_C_P<2>
DP_INT_ML_C_N<2>
DP_INT_ML_C_P<1>
DP_INT_ML_C_N<1>
DP_INT_ML_C_P<0>
DP_INT_ML_C_N<0>

DP_INT_AUXCH_C_P USBC_HSX_AUXCH_C_P
DP_INT_AUXCH_C_N

XDP_LSX_TBTA_R2P
XDP_LSX_TBTA_P2R

XDP_LSX_TBTB_R2P
XDP_LSX_TBTB_P2R

XDP_LSX_TBTC_R2P

16

NC_LSX_TBTC_P2R
PCH_BT_AUDIO_SYNC

PCH_WLAN_AUDIO_SYNC
DP_INT_HPD

EDP_PANEL_PWR_EN
EDP_BKLT_EN
EDP_BKLT_PWM

NC_CPU_RSVD_H40
NC_DISP_UTILS

DISP_RCOMP

AF2
AE1
AH2
AG1
AF4
AE3
AG3
AH4

AJ3
AJ1

CN17
CR17

CM18
CL17

CL19
CN19

CP36
CN35
CL35

CR35
CN27
CR29

H40
BU1
AD2

DDIA_TXP_3
DDIA_TXN_3
DDIA_TXP_2
DDIA_TXN_2
DDIA_TXP_1
DDIA_TXN_1
DDIA_TXP_0
DDIA_TXN_0

DDIA_AUX_P
DDIA_AUX_N

GPP_E13/DDPA_CTRLCLK
GPP_E14/DDPA_CTRLDATA

GPP_E15/DPPB_CTRLCLK/TBT_LSX1_TXD
GPP_E16/DPPB_CTRLDATA/TBT_LSX1_RXD

GPP_E17/DPPC_CTRLCLK
GPP_E18/DPPC_CTRLDATA

GPP_A15/DDSP_HPDC/TIME_SYNC0
GPP_A16/DDSP_HPDB/TIME_SYNC1
GPP_A17/DDSP_HPDA

EDP_VDDEN
EDP_BKLTEN
EDP_BKLTCTL

RSVD_48
DISP_UTILS
DISP_RCOMP

TCP0_TX_P1
TCP0_TX_N1
TCP0_TX_P0

TCP0_TX_N0
TCP0_TXRX_P1
TCP0_TXRX_N1
TCP0_TXRX_P0
TCP0_TXRX_N0

TCP0_AUX_P

TCP0_AUX_N

TCP1_TX_P1

TCP1_TX_N1

TCP1_TX_P0

TCP1_TX_N0
TCP1_TXRX_P1
TCP1_TXRX_N1
TCP1_TXRX_P0
TCP1_TXRX_N0

TCP1_AUX_P

TCP1_AUX_N

TC_RCOMP_P

TC_RCOMP_N

BD4
BC3
BE3
BF4
BJ3
BH4
BM4
BN3

BK4
BL3

AM4
AL3
AP4
AN3
AT4
AU3
AY4
BA3

AV4
AW3

AW1
BA1

USBC_HSX_R2D_C_P<2>
USBC_HSX_R2D_C_N<2>
USBC_HSX_R2D_C_P<1>
USBC_HSX_R2D_C_N<1>
USBC_HSX_D2R_C_P<2>
USBC_HSX_D2R_C_N<2>
USBC_HSX_D2R_C_P<1>
USBC_HSX_D2R_C_N<1>

USBC_HSX_AUXCH_C_N

USBC_HST_R2D_C_P<2>
USBC_HST_R2D_C_N<2>
USBC_HST_R2D_C_P<1>
USBC_HST_R2D_C_N<1>
USBC_HST_D2R_C_P<2>
USBC_HST_D2R_C_N<2>
USBC_HST_D2R_C_P<1>
USBC_HST_D2R_C_N<1>

USBC_HST_AUXCH_C_P
USBC_HST_AUXCH_C_N

TC_RCOMP_P
TC_RCOMP_N

OUT
OUT
OUT
OUT

BI
BI
BI
BI

BI
BI

OUT
OUT
OUT
OUT

BI
BI
BI
BI

BI
BI

R0530

150

1%

1/20W

MF

201

Type-C Port Assignments:

21

21

21

21

21

21

21

21

23

23

22

22

22

22

22

22

22

22

23

23

21

USBC Sink 0

USBC Sink 1

C

B

R0531

150

1%

1/20W

MF

201

1

2

B

A

NOSTUFF

NOSTUFF

NOSTUFF
NOSTUFF
NOSTUFF

8

R0550
R0551
R0552
R0553
R0554
R0555
R0556
R0557

PP3V3_S5

100K
100K
100K
100K

10K

1K

10K

1K

21
21

21
21
21
21
21
21

13 14 17 18 42 74

5% 201MF

1/20W

MF 2015% 1/20W

1/20W

1/20W 201MF5%

5% 1/20W MF 201

MF 2015%

201MF1/20W5%

201MF1/20W5%

2015% 1/20W MF

EDP_BKLT_EN
EDP_PANEL_PWR_EN
DP_INT_HPD
PCH_WLAN_AUDIO_SYNC
XDP_LSX_TBTA_R2P
XDP_LSX_TBTA_P2R
XDP_LSX_TBTB_R2P
XDP_LSX_TBTB_P2R

78 68 5

69 5

69 5

18 5

23 16 5

23 16 5

23 16 5

23 16 5

67

SYNC_MASTER=MASTER SYNC_DATE=06/08/2018

PAGE TITLE

A

CPU GFX

DRAWING NUMBER

051-05232

Apple Inc.

REVISION

2.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=CPU & CHIPSET

35 4

IV ALL RIGHTS RESERVED

2

BRANCH

proto4b

PAGE

5 OF 152

SHEET

5 OF 86

1

SIZE

D

678

www.laptoprepairsecrets.com

64 57 39 14 8

PP1V05_VCCST_OUT

CRITICAL

OMIT_TABLE

3 245

1

D

17 16 11 8

PP1V05_VCCSTG_OUT

R0610

39

BI

PLACE_NEAR=U0500.CF56:2.54MM

CPU_PROCHOT_L

R0620

49.9

1

1%

1/20W

MF

201

2

PLACE_NEAR=U0500.CM2:2.54MM

1

1K

5%

1/20W

MF

201

2

R0621

49.9

1%

1/20W

MF

201

R0611

510

2 1

5%

1/20W

MF

201

200

1%

1/20W

MF

201

1

2

1

2

R0622

PLACE_NEAR=U0500.CG55:2.54MM

64

39

64 39

16

32

18

30 29 28 18

76

29 6

OUT
BI

OUT

OUT

BI
BI

OUT

BI

1%

1/20W

MF

201

1

2

R0613

49.9

CPU_CATERR_L
CPU_PECI
CPU_PROCHOT_R_L
PM_THRMTRIP_L

NC_PCH_GPP_A19
CPU_POPI_RCOMP

PCH_OPI_RCOMP
SD3_RCOMP
DBG_PMODE
SOC_PERST_L

PCH_WLAN_PERST_L
NC_HDMI_RESET_L
PCH_BT_ROM_BOOT_L

1

R0612

1K

5%
1/20W
MF
201

2

E41
B26
B30
C41

CL37

CF56

CM2

CG55

CN11

CH48
CN45
CR45
CP44

U0500

ICL_YN

SYM 4 OF 15
CATERR*
PECI
PROCHOT*
THRMTRIP*

GPP_A19/PCHHOT*

PROC_POPIRCOMP
PCH_OPIRCOMP

SD3_RCOMP

DBG_PMODE

GPP_B4/CPU_GP3
GPP_B3/CPU_GP2
GPP_A11/CPU_GP1
GPP_A10/CPU_GP0

BGA

PROC_TCK
PROC_TDI
PROC_TDO
PROC_TMS

PROC_TRST*

PCH_TRST*

PCH_TCK
PCH_TDI
PCH_TDO
PCH_TMS

PCH_JTAGX

PROC_PRDY*
PROC_PREQ*

D28
C29
A27
C27
A29

CM10
CM12
CM14
CL13
CN13
CL11

G35
G37

XDP_CPUPCH_TCK
XDP_CPUPCH_TDI
XDP_CPUPCH_TDO
XDP_CPUPCH_TMS
XDP_CPUPCH_TRST_L

XDP_CPUPCH_TRST_L
TP_XDP_PCH_TCK
XDP_CPUPCH_TDI
XDP_CPUPCH_TDO
XDP_CPUPCH_TMS
XDP_CPUPCH_TCK

XDP_PRDY_L
XDP_PREQ_L

IN
IN

OUT

IN
IN

IN
IN
IN

OUT

IN

BI

OUT

IN

D

16

16

16

16

16

16

16

16

16

16

16

16

16

C

B

PP1V8_PRIM_PCH

R0650

100K

13 15 75

21

CFG(4) EMBEDDED DISPLAY PORT:
0: ENABLED
1: DISABLED

R0640

49.9

1/20W

1/20W

1%
MF

201

C

201MF5%

CPU_CFG<15>
CPU_CFG<14>
CPU_CFG<13>
CPU_CFG<12>
CPU_CFG<11>
CPU_CFG<10>
CPU_CFG<9>
CPU_CFG<8>
CPU_CFG<7>
CPU_CFG<6>
CPU_CFG<5>
CPU_CFG<4>
CPU_CFG<3>
CPU_CFG<2>
CPU_CFG<1>
CPU_CFG<0>

CPU_CFG<19>
CPU_CFG<18>

CPU_CFG<17>
CPU_CFG<16>

16

BI

R0634

1K

5%

1/20W

MF

201

16

BI

16

BI

17 16

17 16

17 16

17 16

17 16

1

17 16

17 16

2

16

16

16

16

16

16

16

16

16

16

BI
BI
BI
BI
BI
BI
BI
BI
BI

BI
BI
BI
BI

BI
BI

BI
BI

CPU_CFG_RCOMP

PCH_BT_ROM_BOOT_L

16

BI

16

1

16

16

BI
BI
BI

XDP_BPM_L<3>
XDP_BPM_L<2>
XDP_BPM_L<1>
XDP_BPM_L<0>

NC_CPU_RSVD_BN9

2

NC_CPU_RSVD_BM8
TP_CPU_RSVD_AW7

29 6

CRITICAL

OMIT_TABLE

U0500

ICL_YN

BGA

SYM 15 OF 15

A35
B34
C33
D36
F34
G33
C35
E35
C37
E37
A37
C39
G39
D40
B38
A39

E33
F32

F38
E39

A33

E31
C31
A31
D32

BN9
BM8
AW7

CFG_15
CFG_14
CFG_13
CFG_12
CFG_11
CFG_10
CFG_9
CFG_8
CFG_7
CFG_6
CFG_5
CFG_4
CFG_3
CFG_2
CFG_1
CFG_0

CFG_19
CFG_18

CFG_17
CFG_16

CFG_RCOMP RSVD_TP_18

BPM_3*
BPM_2*
BPM_1*
BPM_0*

RSVD_1
RSVD_2
RSVD_TP_1

(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)

(IPU)
(IPU)

(IPU)
(IPU)

RSVD_TP_7
RSVD_TP_8

RSVD_TP_9

RSVD_TP_10

RSVD_TP_11
RSVD_TP_12

RSVD_9

RSVD_10

RSVD_TP_13
RSVD_TP_14

RSVD_11
RSVD_12

TP_1
TP_2

RSVD_TP_15

RSVD_TP_16
RSVD_TP_17

TP_3
TP_4

VSS_268

RSVD_13

B56
A55

BV44
BT44

BP10
BR11

G29
F28

CH14
CJ15

CN1
CR1

BP44
CJ11

U7

CH12
CG11

CJ13

CB44
CD44
BY44

E29

TP_CPU_RSVD_B56
TP_CPU_RSVD_A55

TP_CPU_RSVD_BV44
TP_CPU_RSVD_BT44

TP_CPU_RSVD_BP10
TP_CPU_RSVD_BR11

NC_CPU_RSVD_G29
NC_CPU_RSVD_F28

TP_CPU_RSVD_CH14
TP_CPU_RSVD_CJ15

NC_CPU_RSVD_CN1
NC_CPU_RSVD_CR1

TP_CPU_BP44
TP_CPU_CJ11

TP_CPU_RSVD_U7
TP_CPU_RSVD_CH12

TP_CPU_RSVD_CG11
TP_CPU_RSVD_CJ13
TP_CPU_CB44

TP_CPU_CD44
GND

NC_CPU_RSVD_E29

17

NC_CPU_RSVD_AN7
NC_CPU_RSVD_BD46
NC_CPU_RSVD_Y6
NC_CPU_RSVD_J39
NC_CPU_RSVD_BF46
NC_CPU_RSVD_J31
NC_CPU_RSVD_AJ7
NC_CPU_RSVD_J35

NC_CPU_RSVD_F30
NC_CPU_RSVD_BM44
NC_CPU_RSVD_H32
NC_CPU_RSVD_AL7
NC_CPU_RSVD_H30

NC_CPU_RSVD_CA45
NC_CPU_RSVD_BT46
NC_CPU_RSVD_BR45
NC_CPU_RSVD_BP46
NC_CPU_RSVD_BN45
NC_CPU_RSVD_BC55
NC_CPU_RSVD_N49

AN7

BD46

Y6

J39

BF46

J31
AJ7
J35

F30

BM44

H32
AL7
H30

CA45
BT46
BR45
BP46
BN45
BC55

N49

RSVD_17
RSVD_16
RSVD_15
RSVD_14
RSVD_18
RSVD_19
RSVD_20
RSVD_21

RSVD_22
RSVD_23
RSVD_24
RSVD_25
RSVD_26

RSVD_27
RSVD_28
RSVD_29
RSVD_30
RSVD_31
RSVD_32
RSVD_33

U0500

ICL_YN

BGA

SYM 14 OF 15

CRITICAL

OMIT_TABLE

RSVD_39
RSVD_40
RSVD_41
RSVD_42
RSVD_43

IST_TP_0

IST_TP_1
IST_TRIG_0
IST_TRIG_1

PCH_IST_TP_0
PCH_IST_TP_1

RSVD_44
RSVD_45

RSVD_46
RSVD_34
RSVD_35
RSVD_36
RSVD_37
RSVD_38

BL45
CH16
CF48
CG49
CF50

BG7
BE7
BL7
BJ7

CM56
CP54
CB48
CE51

CH30
CJ37
CJ39
CJ43
CJ45
CF46

NC_CPU_RSVD_BL45
NC_CPU_RSVD_CH16
NC_CPU_RSVD_CF48
NC_CPU_RSVD_CG49
NC_CPU_RSVD_CF50

TP_IST_0
TP_IST_1
TP_IST_TRIG_0
TP_IST_TRIG_1

TP_PCH_IST_0
TP_PCH_IST_1
NC_CPU_RSVD_CB48
NC_CPU_RSVD_CE51

NC_CPU_RSVD_CH30
NC_CPU_RSVD_CJ37
NC_CPU_RSVD_CJ39
NC_CPU_RSVD_CJ43
NC_CPU_RSVD_CJ45
NC_CPU_RSVD_CF46

DCDC IFDIM Support

TOP SIDE ONLY

R0660
R0661
R0662
R0663

R0664
R0665

1/20W 201

5%
5%1/20W MF 201

21

100K

MF

21

100K

21

100K

21

100K

21

100K

MF

21

100K

2015%1/20W
2015% MF1/20W
2015% MF1/20W
2015% MF1/20W

These resistors must be
on the top side and not
covered by glue.

B

NOSTUFF
NOSTUFF
NOSTUFF
NOSTUFF

NOSTUFF
NOSTUFF

TP_CPU_RSVD_AR7
TP_CPU_RSVD_AP6
TP_CPU_RSVD_AT6
TP_CPU_RSVD_AU7

TP_CPU_RSVD_AV6

AR7
AP6
AT6
AU7

AV6

RSVD_TP_2
RSVD_TP_3
RSVD_TP_4
RSVD_TP_5

RSVD_TP_6

A

BK46
BH46

67

CP2
CR3

AE7
AG7

CM4

RSVD_3
RSVD_4

RSVD_5
RSVD_6
RSVD_7
RSVD_8

SKTOCC*

NC_CPU_RSVD_CP2
NC_CPU_RSVD_CR3

NC_CPU_RSVD_AE7
NC_CPU_RSVD_AG7
NC_CPU_RSVD_BK46
NC_CPU_RSVD_BH46

NC_SKTOCC_L

8

SYNC_DATE=06/08/2018SYNC_MASTER=CPU_CARD_ICL_Y

PAGE TITLE

A

CPU Misc/JTAG/CFG/RSVD

DRAWING NUMBER

051-05232

Apple Inc.

REVISION

2.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=CPU & CHIPSET

35 4

IV ALL RIGHTS RESERVED

2

BRANCH

proto4b

PAGE

6 OF 152

SHEET

6 OF 86

1

SIZE

D

678

www.laptoprepairsecrets.com

3 245

1

D

C

B

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

MEM_A_DQ_0<7>
MEM_A_DQ_0<6>
MEM_A_DQ_0<5>
MEM_A_DQ_0<4>
MEM_A_DQ_0<3>
MEM_A_DQ_0<2>
MEM_A_DQ_0<1>
MEM_A_DQ_0<0>
MEM_A_DQ_1<7>
MEM_A_DQ_1<6>
MEM_A_DQ_1<5>
MEM_A_DQ_1<4>
MEM_A_DQ_1<3>
MEM_A_DQ_1<2>
MEM_A_DQ_1<1>
MEM_A_DQ_1<0>
MEM_A_DQ_2<7>
MEM_A_DQ_2<6>
MEM_A_DQ_2<5>
MEM_A_DQ_2<4>
MEM_A_DQ_2<3>
MEM_A_DQ_2<2>
MEM_A_DQ_2<1>
MEM_A_DQ_2<0>
MEM_A_DQ_3<7>
MEM_A_DQ_3<6>
MEM_A_DQ_3<5>
MEM_A_DQ_3<4>
MEM_A_DQ_3<3>
MEM_A_DQ_3<2>
MEM_A_DQ_3<1>
MEM_A_DQ_3<0>
MEM_B_DQ_0<7>
MEM_B_DQ_0<6>
MEM_B_DQ_0<5>
MEM_B_DQ_0<4>
MEM_B_DQ_0<3>
MEM_B_DQ_0<2>
MEM_B_DQ_0<1>
MEM_B_DQ_0<0>
MEM_B_DQ_1<7>
MEM_B_DQ_1<6>
MEM_B_DQ_1<5>
MEM_B_DQ_1<4>
MEM_B_DQ_1<3>
MEM_B_DQ_1<2>
MEM_B_DQ_1<1>
MEM_B_DQ_1<0>
MEM_B_DQ_2<7>
MEM_B_DQ_2<6>
MEM_B_DQ_2<5>
MEM_B_DQ_2<4>
MEM_B_DQ_2<3>
MEM_B_DQ_2<2>
MEM_B_DQ_2<1>
MEM_B_DQ_2<0>
MEM_B_DQ_3<7>
MEM_B_DQ_3<6>
MEM_B_DQ_3<5>
MEM_B_DQ_3<4>
MEM_B_DQ_3<3>
MEM_B_DQ_3<2>
MEM_B_DQ_3<1>
MEM_B_DQ_3<0>

CPU_DDR_RCOMP<2>
CPU_DDR_RCOMP<1>
CPU_DDR_RCOMP<0>

BT56
BU55
BU53
BW53
BT54
BY54
BW55
BY56
BY50
BY48
BW51
BU51
BW49
BT50
BU49
BT48
BL55
BL53
BM56
BP56
BM54
BP54
BR55
BR53
BR51
BR49
BP50
BM48
BP48
BL51
BM50
BL49
AU53
AU55
AV56
AY56
AV54
BA53
BA55
AY54
BA51
BA49
AY48
AU49
AY50
AU51
AV48
AV50
AM54
AM56
AN55
AR55
AN53
AR53
AT56
AT54
AT50
AT48
AR49
AN51
AR51
AM48
AN49
AM50

B44
A43

CD56

DDRA_DQ0_7
DDRA_DQ0_6
DDRA_DQ0_5
DDRA_DQ0_4
DDRA_DQ0_3
DDRA_DQ0_2
DDRA_DQ0_1
DDRA_DQ0_0
DDRA_DQ1_7
DDRA_DQ1_6
DDRA_DQ1_5
DDRA_DQ1_4
DDRA_DQ1_3
DDRA_DQ1_2
DDRA_DQ1_1
DDRA_DQ1_0
DDRA_DQ2_7
DDRA_DQ2_6
DDRA_DQ2_5
DDRA_DQ2_4
DDRA_DQ2_3
DDRA_DQ2_2
DDRA_DQ2_1
DDRA_DQ2_0
DDRA_DQ3_7
DDRA_DQ3_6
DDRA_DQ3_5
DDRA_DQ3_4
DDRA_DQ3_3
DDRA_DQ3_2
DDRA_DQ3_1
DDRA_DQ3_0
DDRB_DQ0_7
DDRB_DQ0_6
DDRB_DQ0_5
DDRB_DQ0_4
DDRB_DQ0_3
DDRB_DQ0_2
DDRB_DQ0_1
DDRB_DQ0_0
DDRB_DQ1_7
DDRB_DQ1_6
DDRB_DQ1_5
DDRB_DQ1_4
DDRB_DQ1_3
DDRB_DQ1_2
DDRB_DQ1_1
DDRB_DQ1_0
DDRB_DQ2_7
DDRB_DQ2_6
DDRB_DQ2_5
DDRB_DQ2_4
DDRB_DQ2_3
DDRB_DQ2_2
DDRB_DQ2_1
DDRB_DQ2_0
DDRB_DQ3_7
DDRB_DQ3_6
DDRB_DQ3_5
DDRB_DQ3_4
DDRB_DQ3_3
DDRB_DQ3_2
DDRB_DQ3_1
DDRB_DQ3_0

DDR_RCOMP_2
DDR_RCOMP_1
DDR_RCOMP_0

U0500

ICL_YN

BGA

SYM 2 OF 15

CRITICAL

OMIT_TABLE

DDRA_CLK_P
DDRA_CLK_N
DDRB_CLK_P
DDRB_CLK_N

DDRA_CKE0
DDRA_CKE1
DDRB_CKE0
DDRB_CKE1

DDRA_CS_0
DDRA_CS_1
DDRB_CS_0
DDRB_CS_1

DDRA_CA5
DDRA_CA4
DDRA_CA3
DDRA_CA2
DDRA_CA1
DDRA_CA0

DDRB_CA5
DDRB_CA4
DDRB_CA3
DDRB_CA2
DDRB_CA1
DDRB_CA0

DDRA_DQSP_3
DDRA_DQSN_3
DDRA_DQSP_2
DDRA_DQSN_2
DDRA_DQSP_1
DDRA_DQSN_1
DDRA_DQSP_0
DDRA_DQSN_0
DDRB_DQSP_3
DDRB_DQSN_3
DDRB_DQSP_2
DDRB_DQSN_2
DDRB_DQSP_1
DDRB_DQSN_1
DDRB_DQSP_0
DDRB_DQSN_0

DRAM_RESET*

BD54
BC53
BD50
BE51

BH54
BJ55
BE49
BF50

BF54
BE55
BC49
BD48

BG53
BE53
BC51
BG55
BJ53
BJ51

BH50
BJ49
BH48
BG51
BF48
BG49

BN49
BN51
BN55
BN53
BV48
BV50
BV56
BV54
AP50
AP48
AP56
AP54
AW49
AW51
AW55
AW53

CB52

MEM_A_CLK_P
MEM_A_CLK_N
MEM_B_CLK_P
MEM_B_CLK_N

MEM_A_CKE<0>
MEM_A_CKE<1>
MEM_B_CKE<0>
MEM_B_CKE<1>

MEM_A_CS_L<0>
MEM_A_CS_L<1>
MEM_B_CS_L<0>
MEM_B_CS_L<1>

MEM_A_CA<5>
MEM_A_CA<4>
MEM_A_CA<3>
MEM_A_CA<2>
MEM_A_CA<1>
MEM_A_CA<0>

MEM_B_CA<5>
MEM_B_CA<4>
MEM_B_CA<3>
MEM_B_CA<2>
MEM_B_CA<1>
MEM_B_CA<0>

MEM_A_DQS_P<3>
MEM_A_DQS_N<3>
MEM_A_DQS_P<2>
MEM_A_DQS_N<2>
MEM_A_DQS_P<1>
MEM_A_DQS_N<1>
MEM_A_DQS_P<0>
MEM_A_DQS_N<0>
MEM_B_DQS_P<3>
MEM_B_DQS_N<3>
MEM_B_DQS_P<2>
MEM_B_DQS_N<2>
MEM_B_DQS_P<1>
MEM_B_DQS_N<1>
MEM_B_DQS_P<0>
MEM_B_DQS_N<0>

PP1V1_S3

1

R0740

470

1%
1/20W
MF
201

2

MEM_RESET_R_L

77

OUT

77

OUT

77

OUT

77

OUT

77

OUT

77

OUT

77

OUT

77

OUT

77

OUT

77

OUT

77

OUT

77

OUT

77

OUT

77

OUT

77

OUT

77

OUT

77

OUT

77

OUT

77

OUT

77

OUT

77

OUT

77

OUT

77

OUT

77

OUT

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

75

R0741

0

5%

1/20W

MF

0201

21

MEM_RESET_L

NOSTUFF

1

C0741

0.1UF

10%
16V

2

X5R-CERM
0201

OUT

CRITICAL

OMIT_TABLE

U0500

ICL_YN

BGA

SYM 3 OF 15

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

20 19

77

77

77

77

77

77

77

77

77

77

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

MEM_C_DQ_0<7>
MEM_C_DQ_0<6>
MEM_C_DQ_0<5>
MEM_C_DQ_0<4>
MEM_C_DQ_0<3>
MEM_C_DQ_0<2>
MEM_C_DQ_0<1>
MEM_C_DQ_0<0>
MEM_C_DQ_1<7>

MEM_C_DQ_1<5>
MEM_C_DQ_1<4>
MEM_C_DQ_1<3>
MEM_C_DQ_1<2>
MEM_C_DQ_1<1>
MEM_C_DQ_1<0>
MEM_C_DQ_2<7>
MEM_C_DQ_2<6>
MEM_C_DQ_2<5>
MEM_C_DQ_2<4>
MEM_C_DQ_2<3>
MEM_C_DQ_2<2>
MEM_C_DQ_2<1>
MEM_C_DQ_2<0>
MEM_C_DQ_3<7>
MEM_C_DQ_3<6>
MEM_C_DQ_3<5>
MEM_C_DQ_3<4>
MEM_C_DQ_3<3>
MEM_C_DQ_3<2>
MEM_C_DQ_3<1>
MEM_C_DQ_3<0>
MEM_D_DQ_0<7>
MEM_D_DQ_0<6>
MEM_D_DQ_0<5>
MEM_D_DQ_0<4>
MEM_D_DQ_0<3>
MEM_D_DQ_0<2>
MEM_D_DQ_0<1>
MEM_D_DQ_0<0>
MEM_D_DQ_1<7>
MEM_D_DQ_1<6>
MEM_D_DQ_1<5>
MEM_D_DQ_1<4>
MEM_D_DQ_1<3>
MEM_D_DQ_1<2>
MEM_D_DQ_1<1>
MEM_D_DQ_1<0>
MEM_D_DQ_2<7>
MEM_D_DQ_2<6>
MEM_D_DQ_2<5>
MEM_D_DQ_2<4>
MEM_D_DQ_2<3>
MEM_D_DQ_2<2>
MEM_D_DQ_2<1>
MEM_D_DQ_2<0>
MEM_D_DQ_3<7>
MEM_D_DQ_3<6>
MEM_D_DQ_3<5>
MEM_D_DQ_3<4>
MEM_D_DQ_3<3>
MEM_D_DQ_3<2>
MEM_D_DQ_3<1>
MEM_D_DQ_3<0>

AF54
AF56
AG55
AJ53
AG53
AK56
AJ55
AK54
AK48
AK50
AJ49
AG49
AJ51
AF48
AG51
AF50
AA53
AA55
AB54
AD54
AB56
AE55
AD56
AE53
AE51
AE49
AD50
AB50
AD48
AA49
AB48
AA51

H54
G53
G55
K54
H56
L55
L53
K56
L51
L49
K50
H48
K48
G49
H50
G51
B52
C51
C53
E53
E51
F56
F54
E55
F48
E49
E47
C47
F46
B48
C49
B46

DDRC_DQ0_7
DDRC_DQ0_6
DDRC_DQ0_5
DDRC_DQ0_4
DDRC_DQ0_3
DDRC_DQ0_2
DDRC_DQ0_1
DDRC_DQ0_0
DDRC_DQ1_7
DDRC_DQ1_6
DDRC_DQ1_5
DDRC_DQ1_4
DDRC_DQ1_3
DDRC_DQ1_2
DDRC_DQ1_1
DDRC_DQ1_0
DDRC_DQ2_7
DDRC_DQ2_6
DDRC_DQ2_5
DDRC_DQ2_4
DDRC_DQ2_3
DDRC_DQ2_2
DDRC_DQ2_1
DDRC_DQ2_0
DDRC_DQ3_7
DDRC_DQ3_6
DDRC_DQ3_5
DDRC_DQ3_4
DDRC_DQ3_3
DDRC_DQ3_2
DDRC_DQ3_1
DDRC_DQ3_0
DDRD_DQ0_7
DDRD_DQ0_6
DDRD_DQ0_5
DDRD_DQ0_4
DDRD_DQ0_3
DDRD_DQ0_2
DDRD_DQ0_1
DDRD_DQ0_0
DDRD_DQ1_7
DDRD_DQ1_6
DDRD_DQ1_5
DDRD_DQ1_4
DDRD_DQ1_3
DDRD_DQ1_2
DDRD_DQ1_1
DDRD_DQ1_0
DDRD_DQ2_7
DDRD_DQ2_6
DDRD_DQ2_5
DDRD_DQ2_4
DDRD_DQ2_3
DDRD_DQ2_2
DDRD_DQ2_1
DDRD_DQ2_0
DDRD_DQ3_7
DDRD_DQ3_6
DDRD_DQ3_5
DDRD_DQ3_4
DDRD_DQ3_3
DDRD_DQ3_2
DDRD_DQ3_1
DDRD_DQ3_0

DDRC_CLK_P
DDRC_CLK_N
DDRD_CLK_P
DDRD_CLK_N

DDRC_CKE0
DDRC_CKE1
DDRD_CKE0
DDRD_CKE1

DDRC_CS_0
DDRC_CS_1
DDRD_CS_0
DDRD_CS_1

DDRC_CA5
DDRC_CA4
DDRC_CA3
DDRC_CA2
DDRC_CA1
DDRC_CA0

DDRD_CA5
DDRD_CA4
DDRD_CA3
DDRD_CA2
DDRD_CA1
DDRD_CA0

DDRC_DQSP_3
DDRC_DQSN_3
DDRC_DQSP_2
DDRC_DQSN_2
DDRC_DQSP_1
DDRC_DQSN_1
DDRC_DQSP_0
DDRC_DQSN_0
DDRD_DQSP_3
DDRD_DQSN_3
DDRD_DQSP_2
DDRD_DQSN_2
DDRD_DQSP_1
DDRD_DQSN_1
DDRD_DQSP_0
DDRD_DQSN_0

N53
P54
U51
U49

R55
T54
R49
T48

N55
R51
P48
T50

U53
R53
W55
U55
V54
W53

V50
W49
W51
V48
N51
P50

AC49
AC51
AC53
AC55
AH48
AH50
AH56
AH54
D48
D46
D52
D54
J49
J51
J53
J55

MEM_C_CLK_P
MEM_C_CLK_N
MEM_D_CLK_P
MEM_D_CLK_N

MEM_C_CKE<0>
MEM_C_CKE<1>
MEM_D_CKE<0>
MEM_D_CKE<1>

MEM_C_CS_L<0>MEM_C_DQ_1<6>
MEM_C_CS_L<1>
MEM_D_CS_L<0>
MEM_D_CS_L<1>

MEM_C_CA<5>
MEM_C_CA<4>
MEM_C_CA<3>
MEM_C_CA<2>
MEM_C_CA<1>
MEM_C_CA<0>

MEM_D_CA<5>
MEM_D_CA<4>
MEM_D_CA<3>
MEM_D_CA<2>
MEM_D_CA<1>
MEM_D_CA<0>

MEM_C_DQS_P<3>
MEM_C_DQS_N<3>
MEM_C_DQS_P<2>
MEM_C_DQS_N<2>
MEM_C_DQS_P<1>
MEM_C_DQS_N<1>
MEM_C_DQS_P<0>
MEM_C_DQS_N<0>
MEM_D_DQS_P<3>
MEM_D_DQS_N<3>
MEM_D_DQS_P<2>
MEM_D_DQS_N<2>
MEM_D_DQS_P<1>
MEM_D_DQS_N<1>
MEM_D_DQS_P<0>
MEM_D_DQS_N<0>

OUT
OUT
OUT
OUT

OUT
OUT
OUT
OUT

OUT
OUT
OUT
OUT

OUT
OUT
OUT
OUT
OUT
OUT

OUT
OUT
OUT
OUT
OUT
OUT

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

D

C

B

A

1

R0752

100

1%
1/20W
MF
201

2

PLACE_NEAR=U0500.B44:12.7mm

1

R0751

100

1%
1/20W
MF
201

2

PLACE_NEAR=U0500.CD56:12.7mm

PLACE_NEAR=U0500.A43:12.7mm

1

R0750

100

1%
1/20W
MF
201

2

BOM_COST_GROUP=CPU & CHIPSET

PAGE TITLE

CPU LPDDR4 Interface

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=06/08/2018SYNC_MASTER=CPU_CARD_ICL_Y

DRAWING NUMBER

051-05232

REVISION

2.0.0

BRANCH

proto4b

PAGE

7 OF 152

SHEET

7 OF 86

A

SIZE

D

8

67

35 4

2

1

678

www.laptoprepairsecrets.com

3 245

1

D

C

B

A

CNL CPU-Y current estimates from Cannon Lake Processor EDS Vol 1, doc #566214, v0.7.
IccMax totals include all pins of same name. Some pin groups are split, IccMax is only specified once.

64 57 39 14 8 6

PP1V05_VCCST_OUT

NOSTUFF

R0802

100

1%

1/20W

MF

201

1

2

1

R0801

43

1%
1/20W
MF
201

2

1

R0800

56

1%
1/20W
MF
201

2

R0810

0

57

57

57

IN

OUT

BI

CPU_VIDALERT_L

CPU_VIDSCLK

CPU_VIDSOUT

R0800.2:
R0801.2:
R0802.2:

PLACE_NEAR=U0500.F42:12.7mm
PLACE_NEAR=U0500.H42:12.7mm
PLACE_NEAR=U0500.G41:12.7mm

R0811

0

21

5%

1/20W

MF

0201

???MA MAX
???MA MAX

1/20W

0201

R0812

1/20W

0201

21
5%
MF

0

21
5%
MF

66 39 17 11

17 16 11 8 6

64 57 39 14 8 6

78

66 11

PP1V1_S3

8 11 75

???A MAX

PP1V05_S0_CPU_VCCST
PP1V05_S0_VCCSTG
PP1V05_VCCSTG_OUT
PP1V05_VCCST_OUT

PPVCC_S0_CPU

8 11 46 75

??A MAX

CPU_VIDALERT_R_L
CPU_VIDSCLK_R
CPU_VIDSOUT_R

VOLTAGE=1.05V

VOLTAGE=1.05V

CRITICAL

OMIT_TABLE

U0500

ICL_YN

BGA

SYM 9 OF 15

A13
A15
A19

AA1
AA3
AA5
AA7
AB2
AB4
AB6
AC5
AC7
AD6
AF6
AH6
AK6
AM6
B10
B12
B16
B18

C13
C15
C19

D10
D12
D16
D18

E11
E13
E15
E17
E19

F10
F12
F16

F42 B20
H42
G41

A7
A9

B4
B6
B8

C3
C5
C7
C9

E1

E3
E5
E7
E9

VCCIN_1
VCCIN_2
VCCIN_3
VCCIN_4
VCCIN_5
VCCIN_6
VCCIN_7
VCCIN_8
VCCIN_9
VCCIN_10
VCCIN_11
VCCIN_12
VCCIN_13
VCCIN_14
VCCIN_15
VCCIN_16
VCCIN_17
VCCIN_18
VCCIN_19
VCCIN_20
VCCIN_21
VCCIN_22
VCCIN_23
VCCIN_24
VCCIN_25
VCCIN_26
VCCIN_27
VCCIN_28
VCCIN_29
VCCIN_30
VCCIN_31
VCCIN_32
VCCIN_33
VCCIN_34
VCCIN_35
VCCIN_36
VCCIN_37
VCCIN_38
VCCIN_39
VCCIN_40
VCCIN_41
VCCIN_42
VCCIN_43
VCCIN_44
VCCIN_45
VCCIN_46
VCCIN_47
VCCIN_48
VCCIN_49
VCCIN_50

VIDALERT*
VIDSCK
VIDSOUT

VCCIN_51
VCCIN_52
VCCIN_53
VCCIN_54
VCCIN_55
VCCIN_56
VCCIN_57
VCCIN_58
VCCIN_59
VCCIN_60
VCCIN_61
VCCIN_62
VCCIN_63
VCCIN_64
VCCIN_65
VCCIN_66
VCCIN_67
VCCIN_68
VCCIN_69
VCCIN_70
VCCIN_71
VCCIN_72
VCCIN_73
VCCIN_74
VCCIN_75
VCCIN_76
VCCIN_77
VCCIN_78
VCCIN_79
VCCIN_80
VCCIN_81
VCCIN_82
VCCIN_83
VCCIN_84
VCCIN_85
VCCIN_86
VCCIN_87
VCCIN_88
VCCIN_89
VCCIN_90
VCCIN_91
VCCIN_92
VCCIN_93
VCCIN_94
VCCIN_95
VCCIN_96
VCCIN_97
VCCIN_98
VCCIN_99

VCCIN_100

VCCIN_SENSE
VSSIN_SENSE

CRITICAL

OMIT_TABLE

U0500

ICL_YN

BGA

SYM 10 OF 15

A45
A49

A53
AA47
AB46
AE47
AF46
AJ47
AK46
AL55
AN47
AP46
AU47
AV46
BA47
BB46
BB56
BD56
BH56
BK56

C55

H46

J47

K46

M56

BV2

BT2

B42

A41

VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8
VDDQ_9
VDDQ_10
VDDQ_11
VDDQ_12
VDDQ_13
VDDQ_14
VDDQ_15
VDDQ_16
VDDQ_17
VDDQ_18
VDDQ_19
VDDQ_20
VDDQ_21
VDDQ_22
VDDQ_23
VDDQ_24
VDDQ_25

VCCST

VCCSTG

VCCSTG_OUT

VCCST_OUT

VDDQ_26
VDDQ_27
VDDQ_28
VDDQ_29
VDDQ_30
VDDQ_31
VDDQ_32

VCC1P8A_1
VCC1P8A_2

VCCFPGM
VCCFPGM
VCCFPGM
VCCFPGM
VCCFPGM

VCCPLL

VCCPLL_OC

RSVD_47

VCCIO_OUT

F18
F2
F4
F6
F8
G13
G15
G19
G9
H10
H12
H16
H18
H2
H4
H6
H8
J1
J13
J15
J19
J3
J5
J7
J9
K4
L1
L3
L5
L7
M2
M4
M6
P2
P4
P6
R1
R3
R5
R7
T4
U1
U3
U5
V2
V4
V6
W5
Y2
Y4

A21

N47

P46
P56
U47
V46
V56
Y56

BR1

BR3

E43
D44
G43
C43
F44

BU5

CB56

BM46

H44

PPVCC_S0_CPU

PP1P05_S0_CPU_VCCPLL

PP1V1_S0SW_CPU_VCCPLL_OC

8 11 46 75

PLACE_NEAR=U0500.B20:50.8mm

R0820

100

5%

1/20W

MF

201

CPU_VCCSENSE_P
CPU_VCCSENSE_N

PLACE_NEAR=U0500.A21:50.8mm

R0821

100

5%

1/20W

MF

201

PP1V1_S3

PP1V8_S0SW_CPU

???MA MAX

PP1V05_VCCSTG_OUT

???MA MAX

NC_CPU_RSVD_BM46

PPVCCIO_OUT

VOLTAGE=1V

8 11 75

D

C

1

2

57

OUT

57

OUT

1

2

B

66 11

17 16 11 8 6

11 9

66 11

18 17

A

D

BOM_COST_GROUP=CPU & CHIPSET

PAGE TITLE

CPU Power

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=06/08/2018SYNC_MASTER=CPU_CARD_ICL_Y

DRAWING NUMBER

051-05232

REVISION

2.0.0

BRANCH

proto4b

PAGE

8 OF 152

SHEET

8 OF 86

SIZE

8

67

35 4

2

1

678

www.laptoprepairsecrets.com

3 245

1

D

CNL PCH-Y CURRENT ESTIMATES FROM CANNON LAKE PCH-U/Y EDS VOL 1, DOC #566439, V0.7.
ICCMAX TOTALS INCLUDE ALL PINS OF SAME NAME. SOME PIN GROUPS ARE SPLIT, ICCMAX IS ONLY SPECIFIED ONCE.

NOTE: ALIASES NOT USED ON CPU SUPPLY OUTPUTS
TO AVOID ANY EXTRANEOUS CONNECTIONS.

D

CRITICAL

OMIT_TABLE

C

59

59

OUT
OUT

PPVCCIN_AUX_PCH

75

?.???A MAX

PLACE_NEAR=U0500.BP4:50.8MM

1

R0920

100

5%
1/20W
MF
201

2

PCH_VCCINSENSE_P
PCH_VCCINSENSE_N

PLACE_NEAR=U0500.BR5:50.8MM

1

R0921

100

5%
1/20W
MF
201

2

A23
A25
AY6
BA7
BB6
BC1
BC7
BD6
BE1
BF6
BG1
BH6
BJ1
BK6
BL1
BM6
BN1
BN7
BP6
BP8
BR7
BR9
C23
C25
D22
E21
E23
E25
F22
F26
G21

BP4
BR5

VCCIN_AUX_1
VCCIN_AUX_2
VCCIN_AUX_3
VCCIN_AUX_4
VCCIN_AUX_5
VCCIN_AUX_6
VCCIN_AUX_7
VCCIN_AUX_8
VCCIN_AUX_9
VCCIN_AUX_10
VCCIN_AUX_11
VCCIN_AUX_12
VCCIN_AUX_13
VCCIN_AUX_14
VCCIN_AUX_15
VCCIN_AUX_16
VCCIN_AUX_17
VCCIN_AUX_18
VCCIN_AUX_19
VCCIN_AUX_20
VCCIN_AUX_21
VCCIN_AUX_22
VCCIN_AUX_23
VCCIN_AUX_24
VCCIN_AUX_25
VCCIN_AUX_26
VCCIN_AUX_27
VCCIN_AUX_28
VCCIN_AUX_29
VCCIN_AUX_30
VCCIN_AUX_31

VCCIN_AUX_VCCSENSE
VCCIN_AUX_VSSSENSE

U0500

ICL_YN

BGA

SYM 11 OF 15

VCCPRIM_3P3_4
VCCPRIM_3P3_5
VCCPRIM_3P3_6
VCCPRIM_3P3_7
VCCPRIM_3P3_8
VCCPRIM_3P3_9

VCCPRIM_1P8_4
VCCPRIM_1P8_5
VCCPRIM_1P8_6
VCCPRIM_1P8_7
VCCPRIM_1P8_8

VCCPRIM_1P8_9
VCCPRIM_1P8_10
VCCPRIM_1P8_11
VCCPRIM_1P8_12
VCCPRIM_1P8_13
VCCPRIM_1P8_14
VCCPRIM_1P8_15
VCCPRIM_1P8_16
VCCPRIM_1P8_17
VCCPRIM_1P8_18

VCCLDOSTD_0P85

VCCA_CLKLDO_1P8_1
VCCA_CLKLDO_1P8_2

VCCDPHY_1P24

VCCPRIM_1P05_1

VCCDSW_1P05

VCC1P05_1
VCC1P05_2
VCC1P05_3

CH42
CH40
CH38
CG43
CG41
CG39

CG21
CG23
CG27
CG29
CH18
CH20
CH22
CH24
CH26
CH28
CJ17
CJ19
CJ21
CJ23
CJ25

CR41

CR19
CR21

CR37

CB46

CR47

BT4
BU3
BV4

PP3V3_S5

???MA MAX

PP1V8_PRIM_PCH

???MA MAX

PP0V85_LDOSTD

PP1V8_PCH_CLKLDO

?MA MAX

PP1V24_S5_PCH_VCCDPHY

PP1V05_PCH_VCCPRIM

PP1V05_S5_PCH_VCCDSW

PP1V05_PCH_CPU

42 59 74

12 66 75

(BYPASS ONLY)

12

12

(BYPASS ONLY)

12

74

(BYPASS ONLY)

12

74

C

B

PP1V05_PCH_EXT

46 81

66 59

66 59

BI
BI

???MA MAX

PPVNN_PCH_EXT

46 81

?.???A MAX

PP3V3_S5

74

PP1V8_PRIM_PCH

75

PP1V8_PRIM_PCH

75

?MA MAX

PP1V8_PRIM_PCH

75

?MA MAX

PCH_CORE_VID0
PCH_CORE_VID1

BYPASS INPUT

BYPASS INPUT

NC_PCH_WLAN_DEV_WAKE

WiFi will be woken up by PCIe In-Band Signal and
therefore PCH_WLAN_DEV_WAKE will not be connected

CC11 BU7
CE11

BU11
BW11
CA11

CH46
CH44
CG45

CH36
CH34
CG35

CH32
CJ33

CJ31
CG31

CN47
CK48
CN53

VCC_V1P05EXT_1P05_1
VCC_V1P05EXT_1P05_2

VCC_VNNEXT_1P05_1
VCC_VNNEXT_1P05_2
VCC_VNNEXT_1P05_3

VCCPRIM_3P3_1
VCCPRIM_3P3_2
VCCPRIM_3P3_3

VCCPRIM_1P8_1
VCCPRIM_1P8_2
VCCPRIM_1P8_3

VCCSPI_1
VCCSPI_2

VCCPGPPR_1
VCCPGPPR_2

GPP_B0/CORE_VID0
GPP_B1/CORE_VID1
GPP_B2/VRALERT*

VCC1P05_OUTPUT_PLL

VCCPRIM_1P05_3
VCCPRIM_1P05_4

VCCPRIM_1P05_2

VCCRTC

VCCDSW_3P3_1
VCCDSW_3P3_2

CC45
CD46

CE45

CR51

BU45
BV46

PP1P05_S0_CPU_VCCPLL

VOLTAGE=1.05V

PP1V05_PCH_VCCPRIM

?.??A MAX

PP1V05_PCH_VCCPRIM

?.??A MAX

PP3V_G3H

?MA MAX

PP3V3_S5

?MA MAX

11 8

74

74

12 74

12 74

B

A

8

67

SYNC_DATE=06/08/2018SYNC_MASTER=CPU_CARD_ICL_Y

PAGE TITLE

A

PCH Power

DRAWING NUMBER

051-05232

Apple Inc.

REVISION

2.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=CPU & CHIPSET

35 4

IV ALL RIGHTS RESERVED

2

BRANCH

proto4b

PAGE

9 OF 152

SHEET

9 OF 86

1

SIZE

D

678

www.laptoprepairsecrets.com

3 245

1

D

C

B

CR55
CR53
CR15

CR9
CP56
CP50
CP46
CP42
CP38
CP34
CP30
CP26
CP22
CP18
CP14
CP12
CP10
CN55

CN9
CM54

CL9

CL7

CL5

CL1
CK54
CK50
CK46
CK44
CK42
CK40
CK38
CK36
CK34
CK32
CK30
CK28
CK26
CK24
CK22
CK20
CK18
CK16
CK14
CK12
CK10
CJ55
CJ47
CJ41
CJ35

CJ5
CH56
CH10
CG51
CG47
CG37
CG33
CG25
CG19
CG17
CG15
CG13

CG5
CF44
CF10
CE55
CE49
CE47

SYM 12 OF 15
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67

U0500

ICL_YN

BGA

VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98

VSS_99
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134

CRITICAL

OMIT_TABLE

CE5
CD52
CD10
CC47
CC5
CB10
CB8
CB6
CB4
CB2
CA55
CA53
CA51
CA49
CA47
BY52
BY10
BW47
BW5
BV52
BV10
BU47
BT52
BT10
BT8
BT6
BR47
BP52
BP2
BN47
BN5
BM52
BM2
BL47
BL5
BK54
BK52
BK50
BK48
BK2
BJ47
BJ5
BH52
BH2
BG47
BG5
BG3
BF56
BF52
BF2
BE47
BE5
BD52
BD2
BC47
BC5
BB54
BB52
BB50
BB48
BB4
BB2
BA5
AY52
AY46
AY2
AW47

AW5

AV52

AV2
AU5

AU1
AT52
AT46

AT2
AR47

AR5

AR3

AR1
AP52

AP2

AN5

AN1
AM52
AM46

AM2
AL53
AL51
AL49
AL47

AL5

AL1
AK52

AK4

AK2

AJ5
AH52
AH46
AG47

AG5
AF52

AE5
AD52
AD46

AD4
AC47

AC3

AC1
AB52

Y54

Y52

Y50

Y48

Y46

W47

W7
W3

W1
V52
T56
T52
T46

T6

T2
R47
P52

N7

N5

N3

N1
M54
M52
M50
M48

SYM 13 OF 15
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198
VSS_199
VSS_200
VSS_201

U0500

ICL_YN

BGA

VSS_202
VSS_203
VSS_204
VSS_205
VSS_206
VSS_207
VSS_208
VSS_209
VSS_210
VSS_211
VSS_212
VSS_213
VSS_214
VSS_215
VSS_216
VSS_217
VSS_218
VSS_219
VSS_220
VSS_221
VSS_222
VSS_223
VSS_224
VSS_225
VSS_226
VSS_227
VSS_228
VSS_229
VSS_230
VSS_231
VSS_232
VSS_233
VSS_234
VSS_235
VSS_236
VSS_237
VSS_238
VSS_239
VSS_240
VSS_241
VSS_242
VSS_243
VSS_244
VSS_245
VSS_246
VSS_247
VSS_248
VSS_249
VSS_250
VSS_251
VSS_252
VSS_253
VSS_254
VSS_255
VSS_256
VSS_257
VSS_258
VSS_259
VSS_260
VSS_261
VSS_262
VSS_263
VSS_264
VSS_265
VSS_266
VSS_267

CRITICAL

OMIT_TABLE

M46
L47
K52
K8
K6
K2
J45
J37
J33
J17
J11
H52
H38
H36
H34
H20
H14
G47
G45
G31
G17
G11
G7
G5
G3
G1
F52
F50
F40
F36
F24
F20
F14
E45
D56
D50
D42
D38
D34
D30
D26
D24
D20
D14
D8
D6
D4
D2
C45
C21
C17
C11
B54
B50
B40
B36
B32
B28
B24
B22
B14
A51
A47
A17
A11
A5

D

C

B

A

8

67

SYNC_DATE=06/08/2018SYNC_MASTER=CPU_CARD_ICL_Y

PAGE TITLE

A

CPU & PCH Grounds

DRAWING NUMBER

051-05232

Apple Inc.

REVISION

2.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=CPU & CHIPSET

35 4

IV ALL RIGHTS RESERVED

2

BRANCH

proto4b

PAGE

10 OF 152

SHEET

10 OF 86

1

SIZE

D

D

www.laptoprepairsecrets.com

Intel recommendations based on #572907, Ice Lake U/Y Platform Design Guide, rev 1.21

CPU VccIN Decoupling

INTEL RECOMMENDATION (TABLE 10-49): 8X 1UF 0402, 13X 22UF 0402, 1X 220UF D-CASE

PPVCC_S0_CPU

8 46 75

APPLE IMPLEMENTATION : 14x 1uF 0201, 30x 10uF 0402, 2x 180uF D1, 16x 10uF (NOSTUFF), 1x 180uF D1 (NOSTUFF)

CRITICAL

1

C1100

1UF

20%

6.3V

2

X6S-CERM
0201

CRITICAL

1

C1101

1UF

20%

6.3V

2

X6S-CERM
0201

CRITICAL

1

C1102

1UF

20%

6.3V

2

X6S-CERM
0201

CRITICAL

1

C1103

1UF

20%

6.3V

2

X6S-CERM
0201

1

2

678

CRITICAL

C1104

1UF

20%

6.3V
X6S-CERM
0201

CRITICAL

1

C1105

1UF

20%

6.3V

2

X6S-CERM
0201

CRITICAL

1

C1106

1UF

20% 20%

6.3V

2

X6S-CERM
0201

CRITICAL

1

C1107

1UF

6.3V

2

X6S-CERM
0201

CRITICAL

1

C1108

1UF 1UF

20%

6.3V

2

X6S-CERM
0201

1

2

CRITICAL

C1109

20%

6.3V
X6S-CERM
0201

CRITICAL

1

C110A

1UF

20%

6.3V

2

X6S-CERM
0201

CRITICAL

1

C110B

1UF

20%

6.3V

2

X6S-CERM
0201

CRITICAL

1

C110C

1UF

20%

6.3V

2

X6S-CERM
0201

CRITICAL

1

C110D

1UF

20%

6.3V

2

X6S-CERM
0201

3 245

NOSTUFF

1

C110E

10UF

20%

6.3V

2

CER-X6S
0402

NOSTUFF

CRITICAL

1

C110F

10UF

20%

6.3V

2

CER-X6S
0402

CRITICAL

1

C110G

10UF

20%

6.3V

2

CER-X6S
0402

CRITICAL

1

C110H

10UF

20%

6.3V

2

CER-X6S
0402 0402

1

2

CRITICAL

C110J

10UF

20%

6.3V
CER-X6S

CRITICAL

1

C110K

10UF

20%

6.3V

2

CER-X6S
0402

CRITICALCRITICAL

1

C110L

10UF

20%

6.3V

2

CER-X6S
0402

1

CRITICAL

1

C110M

10UF

20%

6.3V

2

CER-X6S
0402

D

CRITICAL

1

C1110

10UF

20%

6.3V

2

CER-X6S
0402

NOSTUFF

CRITICAL

1

C1150

10UF

20%

6.3V

2

CER-X6S
0402

CRITICAL

1

C1120

180UF

20%

2.5V

3 2

POLY-AL
SM

CRITICAL

1

C1111

10UF

20%

6.3V

2

CER-X6S
0402

NOSTUFF

CRITICAL

1

C1151

10UF

20%

6.3V

2

CER-X6S
0402

CRITICAL

1

C1121

180UF

20%

2.5V

3 2

POLY-AL
SM

CRITICAL

1

C1112

10UF

20%

6.3V

2

CER-X6S
0402

CRITICAL

1

C1152

10UF

20%

6.3V

2

CER-X6S
0402 0402

NOSTUFF

CRITICAL

1

C1122

180UF

20%

2.5V

3 2

POLY-AL
SM

CRITICAL

1

C1113

10UF

20%

6.3V

2

CER-X6S
0402

CRITICAL

1

C1153

10UF

20%

6.3V

2

CER-X6S

CRITICAL

1

C1114

10UF

20%

6.3V

2

CER-X6S
0402

CRITICAL

1

C1154

10UF

20%

6.3V

2

CER-X6S
0402

CRITICAL

1

C1115

10UF

20%

6.3V

2

CER-X6S
0402

CRITICAL

1

C1155

10UF

20%

6.3V

2

CER-X6S
0402

CRITICAL

1

C1116

10UF

20%

6.3V

2

CER-X6S
0402

CRITICAL

1

C1156

10UF

20%

6.3V

2

CER-X6S
0402

CRITICAL

1

C1117

10UF

20%

6.3V

2

CER-X6S
0402

CRITICAL

1

C1157

10UF

20%

6.3V

2

CER-X6S
0402

NOSTUFF

CRITICAL

1

C1118

10UF

20%

6.3V

2

CER-X6S
0402

CRITICAL

1

C1158

10UF

20%

6.3V

2

CER-X6S
0402

NOSTUFF

CRITICAL

1

C1119

10UF

20%

6.3V

2

CER-X6S
0402

CRITICAL

1

C1159

10UF

20%

6.3V

2

CER-X6S
0402

NOSTUFF

CRITICAL

1

C111A

10UF

20%

6.3V

2

CER-X6S
0402

CRITICAL

1

C115A

10UF

20%

6.3V

2

CER-X6S
0402

NOSTUFF

CRITICAL

1

C111B

10UF

20%

6.3V

2

CER-X6S
0402

CRITICAL

1

C115B

10UF

20%

6.3V

2

CER-X6S
0402

NOSTUFF

CRITICAL

1

C111C

10UF

20%

6.3V

2

CER-X6S
0402

CRITICAL

1

C115C

10UF

20%

6.3V

2

CER-X6S
0402

NOSTUFF

CRITICAL

1

C111D

10UF

20%

6.3V

2

CER-X6S
0402

CRITICAL

1

C115D

10UF

20%

6.3V

2

CER-X6S
0402

NOSTUFF

CRITICAL

1

C111E

10UF

20%

6.3V

2

CER-X6S
0402

CRITICAL

1

C115E

10UF 10UF

20%

6.3V

2

CER-X6S
0402

NOSTUFF

CRITICAL

1

C111F

2

CRITICAL

1

C115F

2

10UF

20%

6.3V
CER-X6S
0402

20%

6.3V
CER-X6S
0402

NOSTUFF

CRITICAL

1

C111G

10UF

20%

6.3V

2

CER-X6S
0402

CRITICAL

1

C115G

10UF

20%

6.3V

2

CER-X6S
0402

NOSTUFF

CRITICAL

1

C111H

10UF

20%

6.3V

2

CER-X6S
0402

CRITICAL

1

C115H

10UF

20%

6.3V

2

CER-X6S
0402

NOSTUFF

CRITICAL

1

C111J

10UF

20%

6.3V

2

CER-X6S
0402

NOSTUFF

CRITICAL

1

C111K

10UF

20%

6.3V

2

CER-X6S
0402

C

INTEL RECOMMENDATION (TABLE 10-50): 7x47uF 0805, 8x 10uF 0402, 7x 1uF 0402, 3x 47uF 0805 (placeholder), 3x 10uF 0402 (placeholder).
APPLE IMPLEMENTATION : 2x 180uF D1, 16x 10uF 0402, 12x 1uF 0201, 6x 10uF 0402 (NOSTUFF).

80 75 59

PPVCCIN_AUX_PCH

CRITICAL

1

C1130

1UF

20%

6.3V

2

X6S-CERM
0201

CRITICAL

1

C1140

10UF

20%

6.3V

2

CER-X6S
0402

CRITICAL

1

C1131

1UF

20%

6.3V

2

X6S-CERM
0201

CRITICAL

1

C1141

10UF

20%

6.3V

2

CER-X6S
0402

CRITICAL

1

C1132

1UF

20%

6.3V

2

X6S-CERM
0201

CRITICAL

1

C1142

10UF

20%

6.3V

2

CER-X6S
0402

CRITICAL

1

C1133

1UF

20%

6.3V

2

X6S-CERM
0201

CRITICAL

1

C1143

10UF

20%

6.3V

2

CER-X6S
0402

CRITICAL

1

C1134

1UF

20%

6.3V

2

X6S-CERM
0201

CRITICAL

1

C1144

10UF

20%

6.3V

2

CER-X6S
0402

CRITICAL

1

C1135

1UF

20%

6.3V

2

X6S-CERM
0201

CRITICAL

1

C1145

10UF

20%

6.3V

2

CER-X6S
0402

CRITICAL

1

C1136

1UF

20%

6.3V

2

X6S-CERM
0201

CRITICAL

1

C1146

10UF

20%

6.3V

2

CER-X6S
0402

CRITICAL

1

C1137

1UF

20%

6.3V

2

X6S-CERM
0201

CRITICAL

1

C1147

10UF

20%

6.3V

2

CER-X6S
0402

CRITICAL

1

C1138

1UF

20%

6.3V

2

X6S-CERM
0201

NOSTUFF

CRITICAL

1

C1148

10UF

20%

6.3V

2

CER-X6S
0402

CRITICAL

1

C1139

1UF

20%

6.3V

2

X6S-CERM
0201

NOSTUFF

CRITICAL

1

C1149

10UF

20%

6.3V

2

CER-X6S
0402

CRITICAL

1

C113A

1UF

20%

6.3V

2

X6S-CERM
0201

CRITICAL

1

C113B

1UF

20%

6.3V

2

X6S-CERM
0201

C

B

PP1V1_S3

8 75

CRITICAL

1

C1170

1UF

20%

6.3V

2

X6S-CERM
0201

CRITICAL

1

C1180

10UF

20%

6.3V

2

CER-X6S
0402

CRITICAL

1

C1171

1UF

20%

6.3V

2

X6S-CERM
0201

CRITICAL

1

C1181

10UF

20%

6.3V

2

CER-X6S
0402

CRITICAL

1

C1172

1UF

20%

6.3V

2

X6S-CERM
0201

CRITICAL

1

C1182

10UF

20%

6.3V

2

CER-X6S
0402

CRITICAL

1

C1173

1UF

20%

6.3V

2

X6S-CERM
0201

CRITICAL

1

C1183

10UF

20%

6.3V

2

CER-X6S
0402

CRITICAL

1

C1174

1UF

20%

6.3V

2

X6S-CERM
0201

CRITICAL

1

C1184

10UF

20%

6.3V

2

CER-X6S
0402

CRITICAL

1

C1175

1UF

20%

6.3V

2

X6S-CERM
0201

CRITICAL

1

C1185

10UF

20%

6.3V

2

CER-X6S
0402

CRITICAL

1

C1176

1UF

20%

6.3V

2

X6S-CERM
0201

CRITICAL

1

C1186

10UF

20%

6.3V

2

CER-X6S
0402

CRITICAL

1

C1177

1UF

20%

6.3V

2

X6S-CERM
0201

17 16 8 6

PP1V05_VCCSTG_OUT

C1198

1UF

20%

6.3V

X6S-CERM

0201

B

66 8

1

2

PP1V8_S0SW_CPU

1

C1195

10UF

20%

6.3V

2

CER-X6S
0402

CRITICAL

1

C1196

10UF

20%

6.3V

2

CER-X6S
0402

NOSTUFFCRITICAL

1

C1197

22UF

20%
4V

2

X5R
0402-1

A

PP1V05_S0_VCCSTG

66 8

NOSTUFF

C11A3

1UF

20%

6.3V

X6S-CERM

0201

67

NOSTUFF

1

C11A4

1UF

2

X6S-CERM

20%

6.3V
0201

1

C11A5

1UF

2

X6S-CERM

20%

6.3V
0201

1

2

8

C11A0

1UF

20%

6.3V

X6S-CERM

0201

1

2

NOSTUFF

C11A1

1UF

20%

6.3V

X6S-CERM

0201

20%

6.3V
0201

1

2

1

C11A2

1UF

2

X6S-CERM

SYNC_DATE=06/08/2018SYNC_MASTER=CPU_CARD_ICL_Y

PAGE TITLE

A

CPU Decoupling

PP1P05_S0_CPU_VCCPLLPP1V05_S0_CPU_VCCST PP1V1_S0SW_CPU_VCCPLL_OC

9 8 78 66 39 17 8 66 8

NOSTUFF

C11A6

1UF

20%

6.3V

X6S-CERM

0201

1

C11A7

1UF

2

X6S-CERM

20%

6.3V
0201

1

2

BOM_COST_GROUP=CPU & CHIPSET

35 4

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

2

Apple Inc.

DRAWING NUMBER

051-05232

REVISION

2.0.0

BRANCH

proto4b

PAGE

11 OF 152

SHEET

11 OF 86

1

SIZE

D

PP1V24_S5_PCH_VCCDPHY

www.laptoprepairsecrets.com

9

MIN_LINE_WIDTH=0.7000
MIN_NECK_WIDTH=0.0750

VOLTAGE=1.24V

678

3 245

1

D

PP0V85_LDOSTD

9

C1300

4.7UF

BYPASS=U0500.DA37::2.54MM

C1305

2.2UF

X6S-CERM

BYPASS=U0500.DA45::2.54MM

20%

6.3V
X6S

0402

20%

4V

0201

1

2

D

1

2

0.6UH-20%-2.8A-0.02OHM

NOSTUFF

L1350

21

XFL4012-SM

C

PP1V8_PRIM_PCH

9 66 75

C1310

X6S-CERM

BYPASS=U0500.CG30::2.54mm

BYPASS=U0500.CG30::2.54mm

PP1V05_S5_PCH_VCCDSW

9

BYPASS=U0500.CJ29::2.54mm

1UF

20%

6.3V
0201

75

1

C1311

1UF

2

6.3V

X6S-CERM

0201

1

20%

2

PP1V8_PRIM_PCH

PLACE_NEAR=U0500.CJ11:12.7mm

R1350

0.010

1%

1/6W

MF

0402

MIN_LINE_WIDTH=0.4500

21

5%
MF

0201

1

0

2

R1351

1/20W

MIN_NECK_WIDTH=0.0750
VOLTAGE=1.8V

PP1V8_PCH_CLKLDO

9

PP1V8_PCH_CLKLDO_R

C

C1315

1UF

20%

6.3V

X6S-CERM

0201

1

C1352

1UF

20%

6.3V

2

X6S-CERM
0201

20%
10V
X5R

0402

1

2

1

C1350

20UF

20%
10V
X5R

0402

1

2

BYPASS=U0500.CJ11::12.7mm

BYPASS=U0500.CJ11::12.7mm

BYPASS=U0500.CJ11::2.54mm

C1351

20UF

2

B

PCH VCCDSW_3P3 Bypass
(PCH 3.3V DSW Power)

PP3V3_S5

9 74

PCH VCCRTC Bypass
(PCH 3V RTC Power)

PP3V_G3H

9 74

C1325

0.1UF

X6S-CERM

10%
25V

0201

NOSTUFF

20%

6.3V

1

2

C1320

1UF

X6S-CERM

0201

B

1

C1326

1UF

2

6.3V

X6S-CERM

0201

1

20%

2

A

BYPASS=U0500.CB38::2.54mm

SYNC_MASTER=CPU_CARD_ICL_Y SYNC_DATE=06/08/2018

PAGE TITLE

A

8

67

PCH Decoupling

DRAWING NUMBER

051-05232

Apple Inc.

REVISION

2.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=CPU & CHIPSET

35 4

IV ALL RIGHTS RESERVED

2

BRANCH

proto4b

PAGE

13 OF 152

SHEET

12 OF 86

1

SIZE

D

D

www.laptoprepairsecrets.com

C

678

13

13

13

13

78 23 13

78 23 13

16

16 13

18 16 13

16

16 13

16

16

23 13

23 13

31 13

25 24 23 13

23 13

23 13

BI
BI
BI
BI

IN
OUT

BI
BI
BI
BI
BI

BI
BI

BI
BI
BI

BI

BI
BI

TP_PCH_GPP_D10
TP_PCH_GPP_D11
TP_PCH_GPP_D8
TP_PCH_GPP_D9

PCH_UART_DEBUG_D2R
PCH_UART_DEBUG_R2D

XDP_PCH_STRP_GPP_E0
XDP_PCH_STRP_CNV_DISABLE
XDP_MEM_OK
XDP_PCH_OBSDATA_B0
XDP_PCH_OBSDATA_B2

XDP_LSX_TBTD_R2P
XDP_LSX_TBTD_P2R
NC_PCH_GPP_E20
NC_PCH_GPP_E21
NC_PCH_GPP_E22
NC_PCH_GPP_E23

JTAG_ISP_TCK
JTAG_ISP_TDI
PCH_SOC_SYNC
NC_PCH_GPP_C8
NC_PCH_GPP_C9
NC_PCH_GPP_C10
PCH_BSB_FORCE_PWR

MLB_RAMCFG0

13

MLB_RAMCFG1

13

MLB_RAMCFG2

13

MLB_RAMCFG3

13

MLB_RAMCFG4

13

JTAG_TBT_X_TMS
JTAG_TBT_T_TMS

CL31
CM32
CR33
CP32

CR49
CP48

CL23
CM22
CP24
CN25
CR25

CN23
CM24
CM16
CP16
CL15
CN15

CM30
CN31
CL29
CM28
CN29
CL27
CP28

CJ51
CD48
BW45
CH50
CD50
BY46
CC49

CRITICAL

OMIT_TABLE

U0500

ICL_YN

BGA

SYM 5 OF 15
GPP_D10/UART0A_RST*
GPP_D11/UART0A_CTS*
GPP_D8/UART0A_RXD
GPP_D9/UART0A_TXD

GPP_B17/UART2A_RXD
GPP_B18/UART2A_TXD

GPP_E0
GPP_E1
GPP_E2
GPP_E4
GPP_E6

GPP_E11
GPP_E12
GPP_E20
GPP_E21
GPP_E22
GPP_E23

GPP_C1
GPP_C2
GPP_C7
GPP_C8 GPP_R6
GPP_C9
GPP_C10
GPP_C13

GPP_G0
GPP_G2
GPP_G3
GPP_G4
GPP_G5
GPP_G6
GPP_G7

GPP_A6/ESPI_RESET*

GPP_A7/SMBCLK

GPP_A8/SMBDATA

GPP_A9/SMBALERT*

GPP_E10/SML0DATA

GPP_E9/SML0CLK

GPP_B11/PMCALERT*

GPP_A5/ESPI_CLK
GPP_A0/ESPI_IO0
GPP_A1/ESPI_IO1
GPP_A2/ESPI_IO2
GPP_A3/ESPI_IO3
GPP_A4/ESPI_CS*

GPP_H3
GPP_H4
GPP_H5

GPP_H8
GPP_H21
GPP_H22

GPP_R5

CM46
CL47
CL45

CN21
CL21

CL53

CL41
CM44
CN43
CR43

CL43
CN41
CM42

CM36
CN33
CP40
CN37
CJ27
CJ29

CM34
CM38

SMBUS_PCH_CLK
SMBUS_PCH_DATA
NC_PCH_GPP_A9

XDP_PCH_I2C_UPC_SDA
XDP_PCH_I2C_UPC_SCL
PCH_UPC_I2C_INT_L

ESPI_CLK60M_R
ESPI_IO<0>
ESPI_IO<1>
ESPI_IO<2>
ESPI_IO<3>
ESPI_CS_L
ESPI_RESET_L

TBT_POC_RESET
JTAG_ISP_TDO
NC_SDCON_OC_L
PCH_GCON_INT_L
NC_PCH_GPP_H21
NC_PCH_GPP_H22

NC_PCH_GPP_R5
NC_PCH_GPP_R6

3 245

42

BI

42

BI

BI
BI

42

BI

R1410

32

BI

32

BI

32

BI

32

BI

32

OUT
OUT

BI
BI

BI

32 13

32

1

D

42 16

42 16

21

25 24 23 13

23 13

51

201

ESPI_CLK60M

OUT

32

C

B

A

NOSTUFF

R1451
R1452
R1453
R1454
R1455
R1456
R1457
R1458
R1459
R1460
R1461
R1467
R1462
R1463
R1464
R1465
R1466
R1468

PP1V8_PRIM_PCH

PP3V3_S5

47K

47K
100K
100K

47K

47K

47K

1K
100K
100K

10K
10K

100K

10K
100K
100K
100K
100K

6 15 75

5 14 17 18 42 74

21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21

1/20W MF5%
1/20W

5%

1/20W 201

5% MF

5% 1/20W MF

1/20W MF

1/20W5% 201MF
5%
5%

1/20W
5% 201MF1/20W

201
MF 2015%
MF5%
MF1/20W5%
MF1/20W 201

MF

2011/20W

201

2015% 1/20W

201

2015%

2015% 1/20W MF

201MF1/20W

2011/20W MF

201MF1/20W5%

2015% MF

201MF5% 1/20W

201MF1/20W5%

PCH_UART_DEBUG_D2R
PCH_UART_DEBUG_R2D

JTAG_ISP_TCK

JTAG_ISP_TDI
TP_PCH_GPP_D8
TP_PCH_GPP_D9

TP_PCH_GPP_D10
TP_PCH_GPP_D11

XDP_PCH_STRP_CNV_DISABLE

XDP_MEM_OK
JTAG_TBT_X_TMS
JTAG_TBT_T_TMS

TBT_POC_RESET

JTAG_ISP_TDO

XDP_PCH_OBSDATA_B2

ESPI_RESET_L

PCH_BSB_FORCE_PWR

PCH_SOC_SYNC

13

13

13

13

B

78 23 13

78 23 13

23 13

23 13

16 13

18 16 13

23 13

23 13

25 24 23 13

23 13

16 13

32 13

25 24 23 13

31 13

RAMCFG0_L

1

R1490

1K

5%
1/20W
MF
201

2

RAM Configuration Straps

MLB_RAMCFG0
MLB_RAMCFG1
MLB_RAMCFG2
MLB_RAMCFG3
MLB_RAMCFG4

RAMCFG1_L

1

R1491

1K

5%
1/20W
MF
201

2

RAMCFG2_L

1

R1492

1K

5%
1/20W
MF
201

2

RAMCFG3_L

1

R1493

1K

5%
1/20W
MF
201

2

RAMCFG4_L

1

R1494

1K

5%
1/20W
MF
201

2

13

13

13

13

13

BOM_COST_GROUP=CPU & CHIPSET

SYNC_MASTER=CPU_CARD_ICL_Y SYNC_DATE=06/08/2018

PAGE TITLE

PCH ESPI/SMBUS/UART

SIZE

D

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

051-05232

REVISION

2.0.0

BRANCH

proto4b

PAGE

14 OF 152

SHEET

13 OF 86

A

8

67

35 4

2

1

678

www.laptoprepairsecrets.com

3 245

1

D

D

C

14 78

14 78

14 17 64 66 78

14 17 18 61

14 17 78 81

17 18

39

14 18 39 78

17

17 18

39 78

OUT
OUT
OUT
OUT
OUT

IN
IN

OUT

IN
IN
IN

PM_SLP_S5_L
PM_SLP_S4_L
PM_SLP_S3_L
PM_SLP_SUS_L
PM_SLP_S0_L

PM_RSMRST_L
PM_SYSRST_L
PLT_RST_L

PM_PCH_DPWROK
PM_PCH_PWROK
PM_PCH_SYS_PWROK

CJ53
CH52
CK52
CC55
CM48

CC53
CR31
CN49

CE53
CB50
CR27

CRITICAL

OMIT_TABLE

U0500

ICL_YN

BGA

SYM 8 OF 15
GPD10/SLP_S5* GPD3/PWRBTN*
GPD5/SLP_S4*
GPD4/SLP_S3*
SLP_SUS*
GPP_B12/SLP_S0*

RSMRST*
SYS_RESET*
GPP_B13/PLTRST*

DSW_PWROK
PCH_PWROK
SYS_PWROK

GPP_H10/CPU_C10_GATE*

GPD0/BATLOW*

GPD7

WAKE*

GPD2/LAN_WAKE*

VCCST_OVERRIDE

VCCST_PWRGD

VCCSTPWRGOOD_TCSS

PROCPWRGD

DSWLDO_MON

CF52
CL33
CB54

CG53

CJ49
CC51

BV6
BU9
BV8
E27
CD54

PCH_PWRBTN_L
CPU_C10_GATE_L
PCH_BATLOW_L

PCH_STRP_GPD7
PCH_PCIE_WAKE_L

PCH_LAN_WAKE_L
VCCST_OVERRIDE

VCCST_PWRGD_R
VCCST_OVERRIDE
TP_CPU_PWRGD
TP_DSWLDO_MON

14

14

14

18

IN

OUT

BI

OUT

IN

14 64

14 17 66

14 23

14 66

14 66

R1511

62

5%

1/20W

MF

201

C

PP1V05_VCCST_OUT

NOSTUFF

1

R1510

1K

5%
1/20W
MF
201

2

21

VCCST_PWRGD

IN

17

6 8 39 57 64

B

A PM_SLP_S0_L NOTE

PM_SLP_S0_L has an intenral pull-up before RSMRST#
is released. This causes a voltage divider with
the pull-down R1553. The signal is driven high
after RSMRST# is released.

R1550
R1551
R1552
R1553

100K
100K
100K

100K

PP3V3_S5

21
21

21

21

13 74 42 18 17 5

1/20W

5% 201MF

1/20W
1/20W

5% 1/20W MF 201

MF5%

2015% MF

201

PLT_RST_L
PCH_PCIE_WAKE_L
PCH_LAN_WAKE_L
PM_SLP_S0_L

14 18 39 78

14

14

14 17 78 81

B

A

NOSTUFF

NOSTUFF

R1554
R1555
R1556
R1560
R1557
R1558
R1559
R1570

R1561
R1562

8

100K
100K
100K
100K

1K
100K
100K
100K

100K
100K

21
21
21
21
21
21
21
21

21
21

1/20W MF 2015%

5% 1/20W

1/20W5% MF
1/20W MF5%
1/20W MF5%
1/20W5%
1/20W5% 201MF

5%

1/20W
1/20W

5% 201

MF1/20W5%

MF 201

MF 201

MF
MF

PM_SLP_S3_L

201

PM_SLP_S4_L
PM_SLP_S5_L
PM_SLP_SUS_L

201

PCH_PWRBTN_L

201

PCH_BATLOW_L

201

CPU_C10_GATE_L

PCH_STRP_GPD7

201

VCCST_OVERRIDE

78 66 64 17 14

78 14

78 14

61 18 17 14

64 14

14

66 17 14

23 14

66 14

67

SYNC_DATE=06/08/2018SYNC_MASTER=CPU_CARD_ICL_Y

PAGE TITLE

A

PCH Power Management

DRAWING NUMBER

051-05232

Apple Inc.

REVISION

2.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=CPU & CHIPSET

35 4

IV ALL RIGHTS RESERVED

2

BRANCH

proto4b

PAGE

15 OF 152

SHEET

14 OF 86

1

SIZE

D

678

www.laptoprepairsecrets.com

3 245

1

CRITICAL

OMIT_TABLE

D

C

PCIe Port Assignments:

SOC lane 3

SOC lane 2

SOC lane 1

SOC lane 0

R1610

100

1%

1/20W

MF

201

U0500

USB3 Port Assignments:

PCIe Port Assignments:

ICL_YN

BGA

SYM 6 OF 15

34

34

40

40

34

34

40

40

34

34

40

40

34

34

40

40

16

16 15

16

18

18

18

18

16

1

PCIE_SOC_D2R_P<3>

IN

PCIE_SOC_D2R_N<3>

IN

PCIE_SOC_R2D_C_P<3>

OUT

PCIE_SOC_R2D_C_N<3>

OUT

PCIE_SOC_D2R_P<2>

IN

PCIE_SOC_D2R_N<2>

IN

PCIE_SOC_R2D_C_P<2>

OUT

PCIE_SOC_R2D_C_N<2>

OUT

PCIE_SOC_D2R_P<1>

IN

PCIE_SOC_D2R_N<1>

IN

PCIE_SOC_R2D_C_P<1>

OUT

PCIE_SOC_R2D_C_N<1>

OUT

PCIE_SOC_D2R_P<0>

IN

PCIE_SOC_D2R_N<0>

IN

PCIE_SOC_R2D_C_P<0>

OUT

PCIE_SOC_R2D_C_N<0>

OUT

XDP_PCH_OBSFN_C0

BI

XDP_PCH_STRP_SPIROM_SAF

BI

XDP_PCH_OBSDATA_B3

BI

USB_EXTA_OC_L

BI

USB_EXTD_OC_L

BI

USB_EXTC_OC_L

BI

USB_EXTB_OC_L

BI

XDP_PCH_OBSDATA_B1

BI

PCH_PCIE_RCOMP_P
PCH_PCIE_RCOMP_N

PLACE_NEAR=U0500.CG1:2.54mm

2

CG1
CG3
CH6
CH8

CH2
CH4
CG7
CG9

CF2
CF4
CF6
CF8

CE1
CE3
CE7
CE9

CR23

CM20
CP20

CN39
CR39
CM40
CL39

CM26

CN3
CL3

PCIE4_RXP
PCIE4_RXN
PCIE4_TXP
PCIE4_TXN

PCIE3_RXP
PCIE3_RXN
PCIE3_TXP
PCIE3_TXN

PCIE2_RXP
PCIE2_RXN
PCIE2_TXP
PCIE2_TXN

PCIE1_RXP
PCIE1_RXN
PCIE1_TXP
PCIE1_TXN

GPP_E8

GPP_E3
GPP_E7

GPP_A18/USB_OC0*
GPP_A12/USB_OC1*
GPP_A13/USB_OC2*
GPP_A14/USB_OC3*

GPP_E5

PCIE_RCOMPP
PCIE_RCOMPN

GPP_E19/IMGCLKOUT5/PCIE_LNK_DOWN

PCIE8_RXP
PCIE8_RXN
PCIE8_TXP
PCIE8_TXN

PCIE7_RXP
PCIE7_RXN
PCIE7_TXP
PCIE7_TXN

PCIE6_RXP
PCIE6_RXN
PCIE6_TXP
PCIE6_TXN

PCIE5_RXP
PCIE5_RXN
PCIE5_TXP
PCIE5_TXN

USB2P_3
USB2N_3

USB2P_2
USB2N_2

USB2P_1
USB2N_1

USB_ID

USB_VBUSSENSE

USB2_COMP

CC1
CC3
CD6
CD8

CD4
CD2
CC7
CC9

CK2
CK4
CK6
CK8

CJ1
CJ3
CJ7
CJ9

CM8
CP8

CM6
CP6

CR7
CN7

CR5

CN5

CP4

CL25

USB3_BSSB_D2R_P
USB3_BSSB_D2R_N
USB3_BSSB_R2D_C_P
USB3_BSSB_R2D_C_N

NC_PCIE_PCH_ENETSD_D2RP
NC_PCIE_PCH_ENETSD_D2RN
NC_PCIE_PCH_ENETSD_R2DCP
NC_PCIE_PCH_ENETSD_R2DCN

USB3_FCT_D2R_P
USB3_FCT_D2R_N
USB3_FCT_R2D_C_P
USB3_FCT_R2D_C_N

PCIE_PCH_WLAN_D2R_P
PCIE_PCH_WLAN_D2R_N
PCIE_PCH_WLAN_R2D_C_P
PCIE_PCH_WLAN_R2D_C_N

USB2_FCT_P
USB2_FCT_N

USB2_TBT_T_P
USB2_TBT_T_N

USB2_TBT_X_P
USB2_TBT_X_N

GND
GND
PCH_USB2_COMP
TP_PCH_PCIE_LINK_DOWN

18

18

IN

IN
OUT
OUT

IN

IN
OUT
OUT

IN

IN
OUT
OUT

IN

IN
OUT
OUT

BI
BI

BI
BI

BI
BI

23

23

23

23

76

76

76

76

78

78

78

78

29

29

29

29

78

78

25

25

24

24

BSSB

SPARE (SS)

USB2 PORT ASSIGNMENTS:
FIXTURE (LS/FS/HS)

USB-C T (LS/FS/HS)

USB-C X (LS/FS/HS)

PLACE_NEAR=U0500.CP4:2.54mm

1

R1622

113

1%
1/20W
MF
201

2

ENET/SD

WLAN

D

C

B

PP1V8_PRIM_PCH

R1650
R1651

1K
1K

6 13 15 75

21
21

5%

MF

PCH_STRP_NO_REBOOT

2011/20W5%

XDP_PCH_STRP_SPIROM_SAF

2011/20W MF

15

16 15

CRITICAL

OMIT_TABLE

U0500

ICL_YN

BGA

SYM 7 OF 15

76

76

76 18 15

29

29

29 15

76

76

OUT
OUT
BI

OUT
OUT
BI

OUT
OUT

NC_PCIE_CLK100M_DEBUGP
NC_PCIE_CLK100M_DEBUGN

DEBUG_CLKREQ_STRAP_L

PCIE_CLK100M_PCH_WLAN_P
PCIE_CLK100M_PCH_WLAN_N

PCH_WLAN_CLKREQ_L

TP_PCIE_CLK100M_PCH2P
TP_PCIE_CLK100M_PCH2N

PCH_STRP_NO_REBOOT

15

NC_PCIE_CLK100M_ENETSDP
NC_PCIE_CLK100M_ENETSDN

NC_PCH_ENETSD_CLKREQ_L

TP_PCIE_CLK100M_PCH4P
TP_PCIE_CLK100M_PCH4N

TP_GPU_CLKREQ_L

BY4
BY2

CP52

BY8
BY6

CN51

CA9
CA7

CM50

BW3
BW1

CM52

BW9
BW7

CL51

CLKOUT_PCIE_P0
CLKOUT_PCIE_N0
GPP_B5/SRCCLKREQ0*

CLKOUT_PCIE_P1
CLKOUT_PCIE_N1
GPP_B6/SRCCLKREQ1*

CLKOUT_PCIE_P2
CLKOUT_PCIE_N2
GPP_B7/SRCCLKREQ2*

CLKOUT_PCIE_P3
CLKOUT_PCIE_N3
GPP_B8/SRCCLKREQ3*

CLKOUT_PCIE_P4
CLKOUT_PCIE_N4
GPP_B9/SRCCLKREQ4*

CLKOUT_PCIE_P5
CLKOUT_PCIE_N5

GPP_B10/SRCCLKREQ5*

RTCX1
RTCX2

RTCRST*

SRTCRST*

XTAL_IN

XTAL_OUT

XCLK_BIASREF

CA3
CA1
CL49

CK56
CL55

CH54

CF54

CR11
CR13

CA5

PCIE_CLK100M_SOC_P
PCIE_CLK100M_SOC_N

SOC_CLKREQ_BUF_L

PMU_CLK32K_PCH_1V0

NC_PCH_CLK32K_XTALOUT

PCH_RTC_RESET_L
PCH_RTC_RESET_L

PCH_CLK38M4_XTALIN

PCH_CLK38M4_XTALOUT
PCH_DIFFCLK_BIASREF

34

OUT

34

OUT

BI

IN

IN

IN

OUT

PLACE_NEAR=U0500.CK4:2.54mm

1

R1670

60.4

1%
1/20W
MF
201

2

18 15

64 18

18

17

17

R1672

127K

1%

1/20W

MF

201

R1673

100K

1

2

1/20W

PLACE_NEAR=U0500.CL49:5mm
PLACE_NEAR=U0500.CL49:5mm

1%
MF

201

21

PMU_CLK32K_PCH

1.0V <- 1.8V

IN

B

64

A

PP1V8_PRIM_PCH

R1660
R1661
R1662

47K
47K
47K

8

NOSTUFF

6 13 15 75

21
21

5% MF1/20W 201

21

1/20W MF5% 201

MF5% 1/20W

SOC_CLKREQ_BUF_L

201

PCH_WLAN_CLKREQ_L
DEBUG_CLKREQ_STRAP_L

18 15

29 15

15 18 76

67

SYNC_DATE=06/08/2018SYNC_MASTER=CPU_CARD_ICL_Y

PAGE TITLE

A

PCH PCIe/USB/CLK

DRAWING NUMBER

051-05232

Apple Inc.

REVISION

2.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=CPU & CHIPSET

35 4

IV ALL RIGHTS RESERVED

2

BRANCH

proto4b

PAGE

16 OF 152

SHEET

15 OF 86

1

SIZE

D

678

www.laptoprepairsecrets.com

3 245

1

D

C

CPU_CFG<0>

17 6

CPU_CFG<1>

17 6

CPU_CFG<2>

6

CPU_CFG<3>

6

CPU_CFG<4>

6

CPU_CFG<5>

6

CPU_CFG<6>

6

CPU_CFG<7>

6

CPU_CFG<8>

17 6

CPU_CFG<9>

17 6

CPU_CFG<10>

17 6

CPU_CFG<11>

6

CPU_CFG<12>

17 6

CPU_CFG<13>

17 6

CPU_CFG<14>

6

CPU_CFG<15>

6

CPU_CFG<16>

6

CPU_CFG<17>

6

CPU_CFG<18>

6

CPU_CFG<19>

6

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

PP1800

PP

0.50MM

SM

P2MM

PP

PP1801

SM

P2MM

PP

PP1802

SM

P2MM

PP

PP1803

PP1804

PP

0.50MM

PP1805

PP

0.50MM

SM

P2MM

PP

PP1806

PP1807

PP

0.50MM

SM

P2MM

PP

PP1808

PP1809

PP

0.50MM

SM

P2MM

PP

PP1810

SM

P2MM

PP

PP1811

SM

P2MM

PP

PP1812

PP1813

PP

0.50MM

PP1814

PP

0.50MM

PP1815

PP

0.50MM

SM

P2MM

PP

PP1816

SM

P2MM

PP

PP1817

SM

P2MM

PP

PP1818

SM

P2MM

PP

PP1819

SM

SM

SM

SM

SM

SM

SM

SM

XDP_PREQ_L

6

XDP_PRDY_L

6

DBG_PMODE

6

XDP_BPM_L<0>

6

IFDIM Trigger for DCDC

XDP_BPM_L<1>

6

XDP_BPM_L<2>

6

XDP_BPM_L<3>

6

XDP_PRESENT_L

32

TP XDP Signals

NOSTUFF

R1895

100K

5%

1/20W

MF

201

NOSTUFF

R1894

100K

5%

1/20W

MF

201

D

SM

P2MM

1

PP

PP1820

SM

P2MM

1

PP

PP1821

SM

P2MM

1

PP

PP1822

SM

P2MM

1

PP

PP1823

1

2

SM

P2MM

1

PP

PP1824

SM

P2MM

1

PP

PP1825

SM

P2MM

1

PP

PP1826

79 78 75 59

PP1V8_PRIM_PCH

R1880

NOSTUFF

R1881

100K

5%

1/20W

MF

201

5%

1/20W

MF

0201

1

2

XDP_PRESET_L

1

OUT

66

0

2

C

1

2

B

A

PCH XDP Signals

These signals do not connect to the Primary (Merged) XDP connector in this architecture because it does not exist.
The PDG puts them on a secondary XDP connector that is only needed in some PCH debugging situation, but also does not exist.
They are listed here to show their secondary XDP functions and to provide test points for signals that are not used elsewhere.
Unused GPIOs have TPs.

PCH/XDP Signals

13 6

BI OUT

13

BI

18 13

42 13

42 13

15

13

15

13

15

15

13

13

23 5

23 5

23 5

23 5

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

5

BI

XDP_PCH_STRP_GPP_E0
XDP_PCH_STRP_CNV_DISABLE
XDP_MEM_OK
XDP_PCH_STRP_SPIROM_SAF
XDP_PCH_OBSDATA_B0
XDP_PCH_OBSDATA_B1
XDP_PCH_OBSDATA_B2
XDP_PCH_OBSDATA_B3
XDP_PCH_OBSFN_C0
XDP_PCH_I2C_UPC_SCL
XDP_PCH_I2C_UPC_SDA
XDP_LSX_TBTD_R2P
XDP_LSX_TBTD_P2R
XDP_LSX_TBTA_R2P
XDP_LSX_TBTA_P2R
XDP_LSX_TBTB_R2P
XDP_LSX_TBTB_P2R
XDP_LSX_TBTC_R2P

FN0

FN1

FN2

FN3

FN4

FN5

FN6

FN7

FN_CLK1

FN8

FN9

FN10

FN11

FN12

FN13

FN14

FN15

FN_CLK2

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

PP1868

PP

0.50MM

PP1869

PP

0.50MM

PP1870

PP

0.50MM

SM

P2MM

PP

PP1871

PP1872

PP

0.50MM

PP1873

PP

0.50MM

SM

P2MM

PP

PP1874

SM

P2MM

PP

PP1880

SM

P2MM

PP

PP1881

PP1882

PP

0.50MM

PP1883

PP

0.50MM

PP1875

PP

0.50MM

PP1876

PP

0.50MM

PP1877

PP

0.50MM

PP1878

PP

0.50MM

PP1884

PP

0.50MM

PP1885

PP

0.50MM

SM

P2MM

PP

PP1886

SM

SM

SM

SM

SM

SM

SM

SM

SM

SM

SM

SM

SM

Non-XDP Signals

PP1V05_VCCSTG_OUT

JTAG Chain for DCI Only Connectivity

6

IN

6

OUT

6

OUT

XDP_CPUPCH_TDO
XDP_CPUPCH_TDO

XDP_CPUPCH_TCK

MAKE_BASE=TRUE

MAKE_BASE=TRUE

XDP_CPUPCH_TDO

PLACE_NEAR=U0500.A27:28MM

XDP_CPUPCH_TCK

1

R1890

100

5%
1/20W
MF
201

2

PLACE_NEAR=U0500.D28:28MM

1

R1891

100

5%
1/20W
MF
201

2

PLACE_NEAR=U0500.CL13:28MM

17 11 8 6

XDP_CPUPCH_TCK

1

PP1890

6

OUT

6

OUT

6

OUT

6

OUT

6

OUT

6

OUT

6

OUT

XDP_CPUPCH_TRST_L
XDP_CPUPCH_TRST_L

XDP_CPUPCH_TMS
XDP_CPUPCH_TMS

XDP_CPUPCH_TDI
XDP_CPUPCH_TDI

TP_XDP_PCH_TCK

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

XDP_CPUPCH_TRST_L

XDP_CPUPCH_TMS

XDP_CPUPCH_TDI

TP_XDP_PCH_TCK

PAGE TITLE

1

TP-P5

PP1891

1

TP-P5

PP1892

1

TP-P5

PP1893

1

TP-P5

A

A

A

A

R1892

51

5%
1/20W
MF
201

2

SYNC_DATE=03/13/2017SYNC_MASTER=X589_CPU_CNL_Y

B

A

8

67

CPU/PCH Merged XDP

DRAWING NUMBER

051-05232

Apple Inc.

REVISION

2.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=DEBUG

35 4

IV ALL RIGHTS RESERVED

2

BRANCH

proto4b

PAGE

18 OF 152

SHEET

16 OF 86

1

SIZE

D

678

www.laptoprepairsecrets.com

3 245

1

D

B

PCH 38.4MHz Crystal

R1900

0

5%
MF

21

PCH_CLK38M4_XTALOUT_R

CRITICAL

Y1900

2.5X2.0-SM

38.4MHZ-10PPM-8PF-30OHM

1

3

15

PCH_CLK38M4_XTALOUT

IN

R1901

200K

1%

1/20W

MF

201

1/20W

0201

1

2

R1902

0

15

PCH_CLK38M4_XTALIN

OUT

5%

1/20W

MF

0201

21

PCH_CLK38M4_XTALIN_R

VCCIN VR EN and VCCST_PWRGD

CRITICAL

C1900

5.6PF

21

+/-0.1PF

25V

NP0-C0G

0201

2
4

CRITICAL

C1901

5.6PF

21

+/-0.1PF

25V

NP0-C0G

0201

EA

VCCSTG_OUT Discharge Circuit

Ensure VCCSTG_OUT <= VCCST during power-down (required at all times)

LTSpice Simulation

66

14 66

P1V05_VCCST_EN

IN

IN

CPU_C10_GATE_L

R1953

R1950

1/20W MF5%

NOSTUFF

0

NOSTUFF

0

21

02015% MF1/20W

21

PVCCSTG_DSCHG_EN_L

0201

DMN5L06VK-7

Q1950

SOT563

VER-3

2

PP3V3_G3H

75

PVCCSTG_DSCHG_EN

6

D

SG

1

R1951

100K

5%

1/20W

MF

201

PP1V05_VCCSTG_OUT

6 8 11 16

NOSTUFF

R1952

100K

1/20W

5%

MF

201

1

2

D

PVCCSTG_DSCHG

1

2

DMN5L06VK-7

NOSTUFF

1

C1950

47PF

5%
25V

2

C0G
0201

Q1950

SOT563

VER-3

5

3

D

SG

4

C

Generation

8 11 39 66 78

64

14 17 64 66 78

14 18

14 18 61

IN

IN

IN

IN

ALL_SYS_PWRGD

PM_SLP_S3_L

PM_RSMRST_L

1/20W 0201MF

PM_SLP_SUS_L

R1910

0

5%

21

R1911

0

5% 02011/20W MF

NOSTUFF

21

PP1V05_S0_CPU_VCCST

10%
16V

0201

1

2

1
3

B

6

C

GND

C1910

0.1UF

X5R-CERM

CPUVRENC

$J230GHUB/j230/mlb/sim/ltspice/vccstg_out_discharge_diodes_inc.asc

$J230GHUB/j230/mlb/sim/ltspice/vccstg_out_discharge_nxp.asc

F

52

VCCA

U1910

74AUP1G11

XSON6

4

Y

1

2

R1913

100K

5%
1/20W
MF
201

R1912

0

5%

1/20W

MF

0201

CPU_VR_EN

21

VCCST_PWRGD

OUT

OUT

57

14

SLP_S0# 1.8V Level Shifter

PP1V8_PRIM_PCH

75

BYPASS=U1930::5mm

10%

6.3V
0201

1

2

U1930

74AUP1G34GX

5

SOT1226

2

NC

1

NC

4

3

PM_SLP_S0_1V8_L

1

R1930

100K

5%
1/20W
MF
201

2

81 78 14

C1930

0.1UF

CERM-X5R

PM_SLP_S0_L

SoC Buffer Bypass

NOSTUFF

R1931

PM_SLP_S0_L

32

OUTIN

1/20W

5% MF 0201

21

PM_SLP_S0_1V8_L

0

C

B

C

PCH_PWROK Generation

74 42 18 14 13 5

14 17 64 66 78

39

IN

IN

PM_SLP_S3_L

PM_PCH_PWROK_SMC

PP3V3_S5

BYPASS=U1915::2MM

C1915

0.1UF

10%
16V

X5R-CERM

0201

1

2

NC

VCC

2

A Y

1

AND

B

5

NC

GND

U1915

74AUP1G08GF

6

SOT891

3

R1915

4

1

R1917

100K

5%
1/20W
MF
201

2

0

5%

1/20W

MF

0201

NOSTUFF

R1916

0

5%

1/20W

MF

0201

B

21

21

PM_PCH_PWROKPCHPWROK_R

OUT

14 18

G

VSS_268 GND Connection

6

IN

GND

A

D

32 14

DSW_PWROK 3.3V Level Shifter

PP3V3_S5

74

BYPASS=U1920::2MM

10%

6.3V
0201

1

2

1

2

U1920

74AUP1T97

5

SOT891

4

6

3

PM_PCH_DPWROK

1

R1920

100K

5%
1/20W
MF
201

2

SMC_DPWROK1V8

SMC_DPWROK1V8

MAKE_BASE=TRUE

1

2

C1920

0.1UF

CERM-X5R

R1922

100K

5%
1/20W
MF
201

OUTIN

CFG Boot StrapsH

CPU_CFG<13>

6 16

CPU_CFG<12>

6 16

CPU_CFG<10>

16 6

CPU_CFG<9>

6 16

CPU_CFG<8>

16 6

CPU_CFG<1>

16 6

CPU_CFG<0>

6 16

PPVCCIO_OUT

18 8

CPUCFG:STRAPS

1

R1976

1K

5%
1/20W
MF
201

2

CPUCFG:STRAPS

1

R1975

1K

5%
1/20W
MF
201

2

CPUCFG:STRAPS

1

R1974

1K

5%
1/20W
MF
201

2

CPUCFG:STRAPS

1

R1973

1K

5%
1/20W
MF
201

2

CPUCFG:STRAPS

1

R1972

1K

5%
1/20W
MF
201

2

CPUCFG:STRAPS

1

R1971

1K

5%
1/20W
MF
201

2

CPUCFG:STRAPS

1

R1970

1K

5%
1/20W
MF
201

2

BOM_COST_GROUP=CPU & CHIPSET

PAGE TITLE

Chipset Shared Support

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=06/08/2018SYNC_MASTER=CPU_CARD_ICL_Y

DRAWING NUMBER

051-05232

REVISION

2.0.0

BRANCH

proto4b

PAGE

19 OF 152

SHEET

17 OF 86

A

SIZE

D

8

67

35 4

2

1

678

www.laptoprepairsecrets.com

3 245

1

D

A E

PP3V3_S5

66 74

BYPASS=U2030::2MM

10%

6.3V

0201

1

2

1

2

U2030

74AUP1T97

5

SOT891

4

6

3

PLT_RST_3V3_LPLT_RST_L

1

R2030

100K

5%
1/20W
MF
201

2

23 78 39 18 14

OUTIN

C2030

0.1UF

CERM-X5R

SOC CLKREQ ControlPLTRST# 3.3V Level Shifter

17 14

18 17 14

PM_PCH_PWROK

IN

IN

PM_RSMRST_L

NOSTUFF

R2050

0

2 1

5% 1/20WMF

R2051

20K

2 1

5%MF 1/20W

0201

201

PP1V8_PRIM_PCH

32 75

PM_RSMRST_L_RC_SCB

1

C2051

0.022UF

10%

6.3V

2

X5R-CERM
0201

U2050

TS5A3166YZPR

C2

IN

XBGA

A2

V+

GND

C1

COM

NO

B1

A1

BYPASS=U2050::2MM

1

C2050

0.1UF

10%

35V

2

CER-X5R
0201

SOC_CLKREQ_BUF_L
SOC_CLKREQ_L

BI

BI

D

15

34

C

B

Miscellaneous Signal Aliases

32

IN

PCH_RTC_RESET_L

MAKE_BASE=TRUE

SMC_TOPBLK_SWP_L

GND

15

GND

15

NOSTUFF

R2008

1K

2 1

5%

1/20W

MF

201

DEBUG_CLKREQ_STRAP_L

DEBUG_CLKREQ_STRAP_L

DEBUG_CLKREQ_STRAP_L

GND

PCH_RTC_RESET_L

MAKE_BASE=TRUE

MAKE_BASE=TRUE

15 64 15

OUTIN

15 18 76

R2052

33

21

MF 2011/20W5%

SOC_CLKREQ_SW_EN_D

tau = RC = 20k * 0.022uF = 440us

F

MEM_OK Debug LED

16 13

IN

XDP_MEM_OK

DBG_LED

Debug LED Notes:

Q2060

2

G

S D

1

DMN5L06VK-7

SOT563

VER-5

D2050

SOD962-2

K A

PMEG3002ESF

MEM_YELLOW_LED

6

PP3V3_G3H

75 81

DBG_LED

R2061

261

1% 201MF1/20W

PCH latches SOC_CLKREQ_L boot strap 65us after RSMRST# de-assertion

R2060

0

21

1/20W 02015%

DBG_LED

PP3V3_G3H_DEBUGLED_MEM

MF

VOLTAGE=3.3V

A

DBG_LED

D2060

YEL-588NM-0.02A
LTST-C281KSKT-SM

K

21

MEM_YELLOW_LED_R

C

B

C

Miscellaneous Pull-Ups

78 39 18 14

5 13 14 17 42 74

PLT_RST_L

PP3V3_S5

R2010
R2011

R2016

R2012
R2013
R2014
R2015

100K
100K

100K

100K
100K
100K
100K

NOSTUFF

NOSTUFF

NOSTUFF

21
21

5% MF 2011/20W

21

21

5% 1/20W

21
21

5% 201MF1/20W

21

1/20W MF 2015%

1/20W MF 2015%

201MF5% 1/20W

MF1/20W 2015%

MF 201

PCH_WLAN_PERST_L

SOC_PERST_L

DEBUG_CLKREQ_STRAP_L

CPU Rev A only ??

USB_EXTA_OC_L
USB_EXTB_OC_L
USB_EXTC_OC_L
USB_EXTD_OC_L

OUT
OUT

OUT

OUT
OUT
OUT
OUT

15

15

15

15

Q2060

VF = 2.0V

IF = 20 mA
RLED = (VCC-VF)/IF
RLED = (3.3V-2.0V)/5mA = 261 Ohms

G H

BT Audio Sync Buf

NC

DBG_LED

NC

5

G

S D

4

WiFi Audio Sync Buf

DMN5L06VK-7

SOT563

VER-5

3

NC

B

30 29 28 6

32 6

76 18 15

PP1V8_PRIM_PCH

75

BYPASS=U2070::2MM

1

C2070

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

R2071

100K

5%
1/20W
MF
201

2

PP1V8_PRIM_PCH

75

BYPASS=U2070::2MM

1

C2080

0.1UF

10%

6.3V

2

U2070

74AUP1G126GX

5

X2SON5

2

A

OE

3

4

Y

1

1

R2072

100K

5%
1/20W
MF
201

2

5 30 29

OUTIN

78 30 29

IN

WLAN_AUDIO_SYNCBT_AUDIO_SYNC PCH_BT_AUDIO_SYNC

CERM-X5R
0201

1

R2081

100K

5%
1/20W
MF
201

2

2

A

U2080

74AUP1G126GX

5

X2SON5

4

Y

OE

1

3

PCH_WLAN_AUDIO_SYNC

1

R2082

100K

5%
1/20W
MF
201

2

OUT

5

A

D

PM_RSMRST Control

61 17 14

39

IN

IN

PM_SLP_SUS_L RSMRSTL_R
PM_RSMRST_R_L

NC

VCC

2

A Y

1

B

5

NC

GND

PP3V3_S5

74

U2001

74AUP1G08GF

6

SOT891

4

3

1

R2004

100K

5%
1/20W
MF
201

2

1/20W

R2001

0

5% 02011/20W

NOSTUFF

R2002

0

BYPASS=U2001::2MM

1

C2001

0.1UF

10%

35V

2

CER-X5R
0201

21

PM_RSMRST_L

MF

21

0201MF5%

OUT

78 39 18 14

PLT_RST_L

IN

78 39 18 14

IN

R2070

0

P3MM

SM
PP

P3MM

SM
PP

21

1

1

PPVCCIO_OUT

TP_CPU_PWRGD

17 8

14

BOM_COST_GROUP=CPU & CHIPSET

1/20W 5% 0201MF

I

18 17 14

Miscellaneous Probe Points

NOSTUFF

PP2000

PP2001

PLT_RST_L

R2080

0

21

0201

NOSTUFF

SYNC_MASTER=CARD_CPU_ICL_YN SYNC_DATE=06/08/2018

PAGE TITLE

MF5%1/20W

Chipset Project Support

SIZE

D

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

051-05232

REVISION

2.0.0

BRANCH

proto4b

PAGE

20 OF 152

SHEET

18 OF 86

A

8

67

35 4

2

1

678

www.laptoprepairsecrets.com

3 245

1

LPDDR4x Sub-Channels A & B

D

C

B

A

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

IN
IN

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

IN
IN

IN
IN

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

IN
IN

IN
IN

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

IN
IN

IN
IN

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

IN
IN

MEM_B_CKE<0>
MEM_B_CKE<1>

MEM_B_DQ_2<4>
MEM_B_DQ_2<5>
MEM_B_DQ_2<7>
MEM_B_DQ_2<6>
MEM_B_DQ_2<3>
MEM_B_DQ_2<1>
MEM_B_DQ_2<2>
MEM_B_DQ_2<0>
MEM_B_DQ_0<4>
MEM_B_DQ_0<0>
MEM_B_DQ_0<3>
MEM_B_DQ_0<7>
MEM_B_DQ_0<5>
MEM_B_DQ_0<1>
MEM_B_DQ_0<6>
MEM_B_DQ_0<2>

MEM_B_CLK_P
MEM_B_CLK_N

MEM_A_CKE<0>
MEM_A_CKE<1>

MEM_A_DQ_2<0>
MEM_A_DQ_2<3>
MEM_A_DQ_2<5>
MEM_A_DQ_2<6>
MEM_A_DQ_2<7>
MEM_A_DQ_2<1>
MEM_A_DQ_2<2>
MEM_A_DQ_2<4>
MEM_A_DQ_0<2>
MEM_A_DQ_0<5>
MEM_A_DQ_0<3>
MEM_A_DQ_0<7>
MEM_A_DQ_0<4>
MEM_A_DQ_0<0>
MEM_A_DQ_0<6>

MEM_A_CLK_P
MEM_A_CLK_N

MEM_B_CKE<0>
MEM_B_CKE<1>

MEM_B_DQ_3<0>
MEM_B_DQ_3<1>
MEM_B_DQ_3<2>
MEM_B_DQ_3<3>
MEM_B_DQ_3<4>
MEM_B_DQ_3<5>
MEM_B_DQ_3<6>
MEM_B_DQ_3<7>
MEM_B_DQ_1<0>
MEM_B_DQ_1<1>
MEM_B_DQ_1<2>
MEM_B_DQ_1<3>
MEM_B_DQ_1<4>
MEM_B_DQ_1<5>
MEM_B_DQ_1<6>
MEM_B_DQ_1<7>

MEM_B_CLK_P
MEM_B_CLK_N

MEM_A_CKE<0>
MEM_A_CKE<1>

MEM_A_DQ_3<6>
MEM_A_DQ_3<5>
MEM_A_DQ_3<4>
MEM_A_DQ_3<0>
MEM_A_DQ_3<3>
MEM_A_DQ_3<7>
MEM_A_DQ_3<1>
MEM_A_DQ_3<2>
MEM_A_DQ_1<0>
MEM_A_DQ_1<6>
MEM_A_DQ_1<5>
MEM_A_DQ_1<1>
MEM_A_DQ_1<3>
MEM_A_DQ_1<7>
MEM_A_DQ_1<4>
MEM_A_DQ_1<2>

MEM_A_CLK_P
MEM_A_CLK_N

F9
G8

B3
C2
E2
G2
D3
C4
E4

H5
B11
C12
E12
G12
D11
C10
E10

H9

E6

E8

Y9

W8

AD3
AC2
AA2

W2
AB3
AC4
AA4

V5

AD11
AC12
AA12

W12

AB11
AC10
AA10

V9

AA6
AA8

F23
G22

B17
C16
E16
G16
D17
C18
E18
H19
B25
C26
E26
G26
D25
C24
E24
H23

E20
E22

Y23
W22

AD17
AC16
AA16

W16

AB17
AC18
AA18

V19

AD25
AC26
AA26

W26

AB25
AC24
AA24

V23

AA20
AA22

CRITICAL

OMIT_TABLE

U2300

LPDDR4X-3200-64GBIT-18NM

FBGA

K3UH7H70MM-JGCJ

CKE0_A

CKE1_A

DQ0_A
DQ1_A
DQ2_A
DQ3_A
DQ4_A
DQ5_A
DQ6_A
DQ7_A
DQ8_A
DQ9_A
DQ10_A
DQ11_A
DQ12_A
DQ13_A
DQ14_A

CK_T_A
CK_C_A

CKE0_B

CKE1_B

DQ0_B
DQ1_B
DQ2_B
DQ3_B
DQ4_B
DQ5_B
DQ6_B
DQ7_B
DQ8_B
DQ9_B
DQ10_B
DQ11_B
DQ12_B
DQ13_B
DQ14_B
DQ15_B

CK_T_B
CK_C_B

CKE0_C

CKE1_C

DQ0_C
DQ1_C
DQ2_C
DQ3_C
DQ4_C
DQ5_C
DQ6_C
DQ7_C
DQ8_C
DQ9_C
DQ10_C
DQ11_C
DQ12_C
DQ13_C
DQ14_C

DQ15_C

CK_T_C
CK_C_C

CKE1_D

DQ0_D
DQ1_D
DQ2_D
DQ3_D
DQ4_D
DQ5_D
DQ6_D
DQ7_D
DQ8_D
DQ9_D
DQ10_D
DQ11_D
DQ12_D
DQ13_D
DQ14_D
DQ15_D

CK_T_D
CK_C_D

SYM 1 OF 4

DDRA

ODT_CA_A

DQS0_T_A

DQS0_C_A

DQS1_T_A

DQS1_C_ADQ15_A

DDRB

ODT_CA_B

DQS0_T_B

DQS0_C_B

DQS1_T_B
DQS1_C_B

DDRC

ODT_CA_C

DQS0_T_C

DQS0_C_C

DQS1_T_C
DQS1_C_C

DDRD

ODT_CA_D

DQS0_T_D

DQS0_C_D

DQS1_T_D
DQS1_C_D

CS0_A
CS1_A

DMI0_A
DMI1_A

CA0_A

CA1_A
CA2_A
CA3_A
CA4_A
CA5_A

ZQ0_A

ZQ1_A

CS0_B

CS1_B

DMI0_B
DMI1_B

CA0_B

CA1_B
CA2_B
CA3_B
CA4_B
CA5_B

RESET*

CS0_C

CS1_C

DMI0_C
DMI1_C

CA0_C

CA1_C
CA2_C
CA3_C
CA4_C
CA5_C

ZQ0_C

ZQ1_C

CS0_DCKE0_D

CS1_D

DMI0_D
DMI1_D

CA0_D

CA1_D
CA2_D
CA3_D
CA4_D
CA5_D

G6
F5

H3
H11

J4

B5
D5
C6
C8
B9
D9

F3
G4
F11
G10

J10
J12

W6
Y5

V3
V11

U4

AD5
AB5
AC6
AC8
AD9
AB9

Y3
W4
Y11
W10

U12

G20
F19

H17
H25

J18

B19
D19
C20
C22
B23
D23

F17
G18
F25
G24

J24
J26

W20
Y19

V17
V25

U18

AD19
AB19
AC20
AC22
AD23
AB23

Y17
W18
Y25
W24

MEM_B_CS_L<0>
MEM_B_CS_L<1>

MEM_B_CA<0>
MEM_B_CA<1>
MEM_B_CA<2>
MEM_B_CA<3>
MEM_B_CA<4>
MEM_B_CA<5>

MEM_B_DQS_P<2>
MEM_B_DQS_N<2>
MEM_B_DQS_P<0>
MEM_B_DQS_N<0>

MEM_1A_ZQ<0>
MEM_1A_ZQ<1>

MEM_A_CS_L<0>
MEM_A_CS_L<1>

MEM_A_CA<0>
MEM_A_CA<1>
MEM_A_CA<2>
MEM_A_CA<3>
MEM_A_CA<4>
MEM_A_CA<5>

MEM_A_DQS_P<2>
MEM_A_DQS_N<2>
MEM_A_DQS_P<0>
MEM_A_DQS_N<0>MEM_A_DQ_0<1>

MEM_RESET_L

MEM_B_CS_L<0>
MEM_B_CS_L<1>

MEM_B_CA<0>
MEM_B_CA<1>
MEM_B_CA<2>
MEM_B_CA<3>
MEM_B_CA<4>
MEM_B_CA<5>

MEM_B_DQS_P<3>
MEM_B_DQS_N<3>
MEM_B_DQS_P<1>
MEM_B_DQS_N<1>

MEM_1C_ZQ<0>
MEM_1C_ZQ<1>

MEM_A_CS_L<0>
MEM_A_CS_L<1>

MEM_A_CA<0>
MEM_A_CA<1>
MEM_A_CA<2>
MEM_A_CA<3>
MEM_A_CA<4>
MEM_A_CA<5>

MEM_A_DQS_P<3>
MEM_A_DQS_N<3>
MEM_A_DQS_P<1>
MEM_A_DQS_N<1>

IN
IN

IN
IN
IN
IN
IN
IN

BI
BI
BI
BI

IN
IN

IN
IN
IN
IN
IN
IN

BI
BI
BI
BI

IN

IN
IN

IN
IN
IN
IN
IN
IN

BI
BI
BI
BI

IN
IN

IN
IN
IN
IN
IN
IN

BI
BI
BI
BI

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

CRITICAL

OMIT_TABLE

U2300

LPDDR4X-3200-64GBIT-18NM

FBGA

PP1V8_S3

19 20 65 74

A2

VDD1

B2

VDD1

AD2

VDD1

AE2

VDD1

A12

VDD1

B12

VDD1

AD12
AE12

AD16
AE16

AD26
AE26

1

R2300

240

1%
1/20W
MF
201

2

PP0V6_S3

1

R2301

240

1%
1/20W
MF
201

2

19 20 65 75

NC
NC

PLACE_NEAR=U2300.J10:12.7mm
PLACE_NEAR=U2300.J12:12.7mm

NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC

20 7

1

R2350

240

1%
1/20W
MF
201

2

PP0V6_S3

1

R2351

240

1%
1/20W
MF
201

2

19 20 65 75

PP0V6_S3

19 20 65 75

A16
B16

A26
B26

J2
J3
J5
U5
J6
U6
J8
U8
J9

U9
J16
J17
J19
U19
J20
U20
J22
U22
J23
U23
U26

VDD1
VDD1
VDD1
VDD1
VDD1
VDD1
VDD1
VDD1
VDD1
VDD1

NC
NC

NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC

CRITICAL

20%

6.3V
X5R

1

2

PLACE_NEAR=U2300.J24:12.7mm
PLACE_NEAR=U2300.J26:12.7mm

PP1V1_S3

19 20 65 75

C2300

1.0UF

0201-1

CRITICAL

20%

6.3V
X5R

1

2

PP1V8_S3

19 20 65 74

C2320

1.0UF

0201-1

CRITICAL

20%

6.3V
X5R

1

2

C2340

1.0UF

0201-1

K3UH7H70MM-JGCJ

SYM 2 OF 4

CRITICAL

C2301

1.0UF

20%

6.3V
X5R

0201-1

CRITICAL

C2321

1.0UF

20%

6.3V
X5R

0201-1

CRITICAL

C2341

1.0UF

20%

6.3V
X5R

0201-1

CRITICAL

1

C2302

2

CRITICAL

1

C2322

2

CRITICAL

1

C2342

2

1.0UF

20%

6.3V
X5R

0201-1

1.0UF

20%

6.3V
X5R

0201-1

10UF

20%

6.3V

CERM
0402

VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2

CRITICAL

1

2

CRITICAL

1

2

CRITICAL

1

2

PP1V1_S3

A6
B6
D6
F6
H6
V6
Y6
AB6
AD6
AE6
A8
B8
D8
F8
H8
V8
Y8
AB8
AD8
AE8
A20
B20
D20
F20
H20
V20
Y20
AB20
AD20
AE20
A22
B22
D22
F22
H22
V22
Y22
AB22
AD22
AE22

C2303

1.0UF

20%

6.3V
X5R

0201-1

C2323

1.0UF

20%

6.3V
X5R

0201-1

C2343

10UF

20%

6.3V

CERM
0402

CRITICAL

1

C2304

1.0UF

2

CRITICAL

1

C2324

1.0UF

2

CRITICAL

1

C2344

2

20%

6.3V
X5R

0201-1

20%

6.3V
X5R

0201-1

10UF

20%

6.3V

CERM
0402

19 20 65 75

CRITICAL

1

C2305

1.0UF

2

CRITICAL

1

C2325

1.0UF

2

CRITICAL

1

C2345

2

AA3
AA5

AA9
AA11
AA17
AA19
AA23
AA25

AB2

AB4
AB10
AB12
AB16
AB18
AB24
AB26

AC3

AC5

AC9
AC11
AC17
AC19
AC23
AC25

AD4
AD10
AD18
AD24

B4
B10
B18
B24

C3

C5

C9
C11
C17
C19
C23
C25

D2

D4
D10
D12
D16
D18
D24
D26

E3

E5

E9
E11
E17
E19
E23
E25

F2

20%

6.3V
X5R

0201-1

20%

6.3V
X5R

0201-1

10UF

20%

6.3V

CERM
0402

LPDDR4X-3200-64GBIT-18NM

CRITICAL

1

C2306

1.0UF

2

CRITICAL

1

C2326

1.0UF

2

1

2

CRITICAL

OMIT_TABLE

U2300

FBGA

K3UH7H70MM-JGCJ

SYM 4 OF 4

CRITICAL

1

20%

6.3V
2

X5R

0201-1

CRITICAL

1

20%

6.3V
2

X5R

0201-1

C2307

1.0UF

20%

6.3V
X5R

0201-1

C2327

1.0UF

20%

6.3V
X5R

0201-1

VSSVSS

CRITICAL

1

C2308

2

CRITICAL

1

C2328

2

F4
F10
F12
F16
F18
F24
F26
G3
G5
G9
G11
G17
G19
G23
G25
H2
H4
H10
H12
H16
H18
H24
H26
J11
J25
U2
U3
U10
U11
U16
U17
U24
U25
V2
V4
V10
V12
V16
V18
V24
V26
W3
W5
W9
W11
W17
W19
W23
W25
Y2
Y4
Y10
Y12
Y16
Y18
Y24
Y26

10UF

20%

6.3V
CERM
0402

10UF

20%

6.3V
CERM
0402

PP0V6_S3

19 20 65 75

CRITICAL

1

C2309

2

CRITICAL

1

C2329

2

CRITICAL

1

C2310

10UF

20%

6.3V
2

CERM
0402

CRITICAL

1

C2330

10UF

20%

6.3V
2

CERM
0402

SYNC_MASTER=J140

PAGE TITLE

LPDDR4x Sub-Channels A & B

10UF

20%

6.3V
CERM
0402

10UF

20%

6.3V
CERM
0402

A1
B1
C1
D1
E1
F1
G1
H1
J1
U1
V1
W1

Y1
AA1
AB1
AC1
AD1
AE1

A3
AE3

A4
AE4

A5
AE5

A9
AE9
A10

AE10

A11

AE11

A13
B13
C13
D13
E13
F13
G13
H13
J13
U13
V13
W13
Y13

AA13
AB13
AC13
AD13
AE13

CRITICAL

1

2

CRITICAL

1

2

LPDDR4X-3200-64GBIT-18NM

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

C2311

10UF

20%

6.3V
CERM
0402

C2331

10UF

20%

6.3V
CERM
0402

Apple Inc.

CRITICAL

OMIT_TABLE

U2300

FBGA

K3UH7H70MM-JGCJ

SYM 3 OF 4

1

2

1

2

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

SYNC_DATE=08/23/2018

DRAWING NUMBER

051-05232

REVISION

A15
B15
C15
D15
E15
F15
G15
H15
J15
U15
V15
W15
Y15
AA15
AB15
AC15
AD15
AE15
A17
AE17
A18
AE18
A19
AE19
A23
AE23
A24
AE24
A25
AE25
A27
B27
C27
D27
E27
F27
G27
H27
J27
U27
V27
W27
Y27
AA27
AB27
AC27
AD27
AE27

D

C

B

A

SIZE

D

2.0.0

BRANCH

proto4b

PAGE

23 OF 152

SHEET

19 OF 86

BOM_COST_GROUP=DRAM

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

8

67

35 4

2

1

678

www.laptoprepairsecrets.com

3 245

1

LPDDR4x Sub-Channels C & D

D

C

B

A

CRITICAL

OMIT_TABLE

U2500

LPDDR4X-3200-64GBIT-18NM

FBGA

77

77

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

77

77

77

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

77

77

77

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

77

77

77

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77 77

BI IN

77

BI

77

BI

77

BI

77

BI

77

BI

77

77

MEM_D_CKE<0>

IN

MEM_D_CKE<1>

IN

MEM_D_DQ_0<5>
MEM_D_DQ_0<3>
MEM_D_DQ_0<4>
MEM_D_DQ_0<1>
MEM_D_DQ_0<7>
MEM_D_DQ_0<6>
MEM_D_DQ_0<0>
MEM_D_DQ_0<2>
MEM_D_DQ_2<6>
MEM_D_DQ_2<3>
MEM_D_DQ_2<5>
MEM_D_DQ_2<2>
MEM_D_DQ_2<7>
MEM_D_DQ_2<4>
MEM_D_DQ_2<0>

MEM_D_CLK_P

IN

MEM_D_CLK_N

IN

MEM_C_CKE<0>

IN

MEM_C_CKE<1>

IN

MEM_C_DQ_0<0>
MEM_C_DQ_0<1>
MEM_C_DQ_0<2>
MEM_C_DQ_0<3>
MEM_C_DQ_0<4>
MEM_C_DQ_0<5>
MEM_C_DQ_0<6>
MEM_C_DQ_0<7>
MEM_C_DQ_2<0>
MEM_C_DQ_2<1>
MEM_C_DQ_2<2>
MEM_C_DQ_2<3>
MEM_C_DQ_2<4>
MEM_C_DQ_2<5>
MEM_C_DQ_2<6>
MEM_C_DQ_2<7>

MEM_C_CLK_P

IN

MEM_C_CLK_N

IN

MEM_D_CKE<0>

IN

MEM_D_CKE<1>

IN

MEM_D_DQ_1<2>
MEM_D_DQ_1<3>
MEM_D_DQ_1<6>
MEM_D_DQ_1<7>
MEM_D_DQ_1<5>
MEM_D_DQ_1<0>
MEM_D_DQ_1<4>
MEM_D_DQ_1<1>
MEM_D_DQ_3<5>
MEM_D_DQ_3<4>
MEM_D_DQ_3<1>
MEM_D_DQ_3<3>
MEM_D_DQ_3<2>
MEM_D_DQ_3<0>
MEM_D_DQ_3<6>
MEM_D_DQ_3<7>

MEM_D_CLK_P

IN

MEM_D_CLK_N

IN

MEM_C_CKE<0>

IN

MEM_C_CKE<1>

IN

MEM_C_DQ_1<3>
MEM_C_DQ_1<4>
MEM_C_DQ_1<2>
MEM_C_DQ_1<0>
MEM_C_DQ_1<1>
MEM_C_DQ_1<5>
MEM_C_DQ_1<6>
MEM_C_DQ_1<7>
MEM_C_DQ_3<7>
MEM_C_DQ_3<5>
MEM_C_DQ_3<4>
MEM_C_DQ_3<2>
MEM_C_DQ_3<3>
MEM_C_DQ_3<6>
MEM_C_DQ_3<0>
MEM_C_DQ_3<1>

MEM_C_CLK_P

IN

MEM_C_CLK_N

IN

F9
G8

B3
C2
E2
G2
D3
C4
E4

H5
B11
C12
E12
G12
D11
C10
E10

H9

E6

E8

Y9

W8

AD3
AC2
AA2

W2
AB3
AC4
AA4

V5

AD11
AC12
AA12

W12

AB11
AC10
AA10

V9

AA6
AA8

F23
G22

B17
C16
E16
G16
D17
C18
E18
H19
B25
C26
E26
G26
D25
C24
E24
H23

E20
E22

Y23
W22

AD17
AC16
AA16

W16

AB17
AC18
AA18

V19

AD25
AC26
AA26

W26

AB25
AC24
AA24

V23

AA20
AA22

CKE0_A

CKE1_A

DQ0_A
DQ1_A
DQ2_A
DQ3_A
DQ4_A
DQ5_A
DQ6_A
DQ7_A
DQ8_A
DQ9_A
DQ10_A
DQ11_A
DQ12_A
DQ13_A
DQ14_A

CK_T_A
CK_C_A

CKE0_B

CKE1_B

DQ0_B
DQ1_B
DQ2_B
DQ3_B
DQ4_B
DQ5_B
DQ6_B
DQ7_B
DQ8_B
DQ9_B
DQ10_B
DQ11_B
DQ12_B
DQ13_B
DQ14_B
DQ15_B

CK_T_B
CK_C_B

CKE0_C

CKE1_C

DQ0_C
DQ1_C
DQ2_C
DQ3_C
DQ4_C
DQ5_C
DQ6_C
DQ7_C
DQ8_C
DQ9_C
DQ10_C
DQ11_C
DQ12_C
DQ13_C
DQ14_C

DQ15_C

CK_T_C
CK_C_C

CKE1_D

DQ0_D
DQ1_D
DQ2_D
DQ3_D
DQ4_D
DQ5_D
DQ6_D
DQ7_D
DQ8_D
DQ9_D
DQ10_D
DQ11_D
DQ12_D
DQ13_D
DQ14_D
DQ15_D

CK_T_D
CK_C_D

K3UH7H70MM-JGCJ

SYM 1 OF 4

DDRA

DDRB

DDRC

DDRD

CS0_A
CS1_A

DMI0_A
DMI1_A

ODT_CA_A

CA0_A

CA1_A
CA2_A
CA3_A
CA4_A
CA5_A

DQS0_T_A

DQS0_C_A

DQS1_T_A

DQS1_C_ADQ15_A

ZQ0_A

ZQ1_A

CS0_B

CS1_B

DMI0_B
DMI1_B

ODT_CA_B

CA0_B

CA1_B
CA2_B
CA3_B
CA4_B
CA5_B

DQS0_T_B

DQS0_C_B

DQS1_T_B
DQS1_C_B

RESET*

CS0_C

CS1_C

DMI0_C
DMI1_C

ODT_CA_C

CA0_C

CA1_C
CA2_C
CA3_C
CA4_C
CA5_C

DQS0_T_C

DQS0_C_C

DQS1_T_C
DQS1_C_C

ZQ0_C

ZQ1_C

CS0_DCKE0_D

CS1_D

DMI0_D
DMI1_D

ODT_CA_D

CA0_D

CA1_D
CA2_D
CA3_D
CA4_D
CA5_D

DQS0_T_D

DQS0_C_D

DQS1_T_D
DQS1_C_D

G6
F5

H3
H11

J4

B5
D5
C6
C8
B9
D9

F3
G4
F11
G10

J10
J12

W6
Y5

V3
V11

U4

AD5
AB5
AC6
AC8
AD9
AB9

Y3
W4
Y11
W10

U12

G20
F19

H17
H25

J18

B19
D19
C20
C22
B23
D23

F17
G18
F25
G24

J24
J26

W20
Y19

V17
V25

U18

AD19
AB19
AC20
AC22
AD23
AB23

Y17
W18
Y25
W24

MEM_D_CS_L<0>
MEM_D_CS_L<1>

MEM_D_CA<0>
MEM_D_CA<1>
MEM_D_CA<2>
MEM_D_CA<3>
MEM_D_CA<4>
MEM_D_CA<5>

MEM_D_DQS_P<0>
MEM_D_DQS_N<0>
MEM_D_DQS_P<2>
MEM_D_DQS_N<2>MEM_D_DQ_2<1>

MEM_2A_ZQ<0>
MEM_2A_ZQ<1>

MEM_C_CS_L<0>
MEM_C_CS_L<1>

MEM_C_CA<0>
MEM_C_CA<1>
MEM_C_CA<2>
MEM_C_CA<3>
MEM_C_CA<4>
MEM_C_CA<5>

MEM_C_DQS_P<0>
MEM_C_DQS_N<0>
MEM_C_DQS_P<2>
MEM_C_DQS_N<2>

MEM_RESET_L

MEM_D_CS_L<0>
MEM_D_CS_L<1>

MEM_D_CA<0>
MEM_D_CA<1>
MEM_D_CA<2>
MEM_D_CA<3>
MEM_D_CA<4>
MEM_D_CA<5>

MEM_D_DQS_P<1>
MEM_D_DQS_N<1>
MEM_D_DQS_P<3>
MEM_D_DQS_N<3>

MEM_2C_ZQ<0>
MEM_2C_ZQ<1>

MEM_C_CS_L<0>
MEM_C_CS_L<1>

MEM_C_CA<0>
MEM_C_CA<1>
MEM_C_CA<2>
MEM_C_CA<3>
MEM_C_CA<4>
MEM_C_CA<5>

MEM_C_DQS_P<1>
MEM_C_DQS_N<1>
MEM_C_DQS_P<3>
MEM_C_DQS_N<3>

IN
IN

IN
IN
IN
IN
IN
IN

BI
BI
BI
BI

IN
IN

IN
IN
IN
IN
IN
IN

BI
BI
BI
BI

IN

IN
IN

IN
IN
IN
IN
IN
IN

BI
BI
BI
BI

IN
IN

IN
IN
IN
IN
IN

BI
BI
BI
BI

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

CRITICAL

OMIT_TABLE

U2500

LPDDR4X-3200-64GBIT-18NM

FBGA

PP1V8_S3

19 20 65 74

A2

VDD1

B2

VDD1

AD2

VDD1

AE2

VDD1

A12

VDD1

B12

VDD1

AD12
AE12

AD16
AE16

AD26
AE26

1

R2500

240

1%
1/20W
MF
201

2

PP0V6_S3

1

R2501

240

1%
1/20W
MF
201

2

19 20 65 75

NC
NC

PLACE_NEAR=U2500.J10:12.7mm
PLACE_NEAR=U2500.J12:12.7mm

NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC

19 7

1

R2550

240

1%
1/20W
MF
201

2

PP0V6_S3

1

R2551

240

1%
1/20W
MF
201

2

19 20 65 75

PP0V6_S3

19 20 65 75

A16
B16

A26
B26

J2
J3
J5
U5
J6
U6
J8
U8
J9

U9
J16
J17
J19
U19
J20
U20
J22
U22
J23
U23
U26

VDD1
VDD1
VDD1
VDD1
VDD1
VDD1
VDD1
VDD1
VDD1
VDD1

NC
NC

NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC

CRITICAL

20%

6.3V
X5R

1

2

PLACE_NEAR=U2500.J24:12.7mm
PLACE_NEAR=U2500.J26:12.7mm

PP1V1_S3

19 20 65 75

C2500

1.0UF

0201-1

CRITICAL

20%

6.3V
X5R

1

2

PP1V8_S3

19 20 65 74

C2520

1.0UF

0201-1

CRITICAL

20%

6.3V
X5R

1

2

C2540

1.0UF

0201-1

K3UH7H70MM-JGCJ

SYM 2 OF 4

CRITICAL

C2501

1.0UF

20%

6.3V
X5R

0201-1

CRITICAL

C2521

1.0UF

20%

6.3V
X5R

0201-1

C2541

1.0UF

20%

6.3V
X5R

0201-1

CRITICAL

1

C2502

2

CRITICAL

1

C2522

2

CRITICALCRITICAL

1

C2542

2

1.0UF

20%

6.3V
X5R

0201-1

1.0UF

20%

6.3V
X5R

0201-1

10UF

20%

6.3V

CERM
0402

VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2

CRITICAL

1

2

CRITICAL

1

2

CRITICAL

1

2

PP1V1_S3

A6
B6
D6
F6
H6
V6
Y6
AB6
AD6
AE6
A8
B8
D8
F8
H8
V8
Y8
AB8
AD8
AE8
A20
B20
D20
F20
H20
V20
Y20
AB20
AD20
AE20
A22
B22
D22
F22
H22
V22
Y22
AB22
AD22
AE22

C2503

1.0UF

20%

6.3V
X5R

0201-1

C2523

1.0UF

20%

6.3V
X5R

0201-1

C2543

10UF

20%

6.3V

CERM
0402

1

C2504

1.0UF

2

CRITICAL

1

C2524

1.0UF

2

CRITICAL

1

C2544

2

20%

6.3V
X5R

0201-1

20%

6.3V
X5R

0201-1

10UF

20%

6.3V

CERM
0402

19 20 65 75

CRITICALCRITICAL

1

C2505

1.0UF

2

CRITICAL

1

C2525

1.0UF

2

CRITICAL

1

C2545

2

AA3
AA5

AA9
AA11
AA17
AA19
AA23
AA25

AB2

AB4
AB10
AB12
AB16
AB18
AB24
AB26

AC3

AC5

AC9
AC11
AC17
AC19
AC23
AC25

AD4
AD10
AD18
AD24

B4
B10
B18
B24

C3

C5

C9
C11
C17
C19
C23
C25

D2

D4
D10
D12
D16
D18
D24
D26

E3

E5

E9
E11
E17
E19
E23
E25

F2

20%

6.3V
X5R

0201-1

20%

6.3V
X5R

0201-1

10UF

20%

6.3V

CERM
0402

LPDDR4X-3200-64GBIT-18NM

CRITICAL

1

C2506

1.0UF

2

CRITICAL

1

C2526

1.0UF

2

1

2

CRITICAL

OMIT_TABLE

U2500

FBGA

K3UH7H70MM-JGCJ

SYM 4 OF 4

CRITICAL

1

20%

6.3V
2

X5R

0201-1

CRITICAL

1

20%

6.3V
2

X5R

0201-1

C2507

1.0UF

20%

6.3V
X5R

0201-1

C2527

1.0UF

20%

6.3V
X5R

VSSVSS

CRITICAL

1

C2508

2

CRITICAL

1

C2528

2

F4
F10
F12
F16
F18
F24
F26
G3
G5
G9
G11
G17
G19
G23
G25
H2
H4
H10
H12
H16
H18
H24
H26
J11
J25
U2
U3
U10
U11
U16
U17
U24
U25
V2
V4
V10
V12
V16
V18
V24
V26
W3
W5
W9
W11
W17
W19
W23
W25
Y2
Y4
Y10
Y12
Y16
Y18
Y24
Y26

10UF

20%

6.3V
CERM
0402

10UF

20%

6.3V
CERM
04020201-1

PP0V6_S3

19 20 65 75

CRITICAL

1

C2509

2

CRITICAL

1

C2529

2

CRITICAL

OMIT_TABLE

U2500

LPDDR4X-3200-64GBIT-18NM

FBGA

K3UH7H70MM-JGCJ

A1

VDDQ

B1

VDDQ

C1

VDDQ

D1

VDDQ

E1

VDDQ

F1

VDDQ

G1

VDDQ

H1

VDDQ

J1

VDDQ

U1

VDDQ

V1

VDDQ

W1

VDDQ

Y1

VDDQ

AA1

VDDQ

AB1

VDDQ

AC1

VDDQ

AD1

VDDQ

AE1

VDDQ

A3

VDDQ

AE3

VDDQ

A4

VDDQ

AE4

VDDQ

A5

VDDQ

AE5

VDDQ

A9

VDDQ

AE9

VDDQ

A10

VDDQ

AE10

AE11

AA13
AB13
AC13
AD13
AE13

CRITICAL

1

C2510

10UF

20%

6.3V
CERM
0402

2

10UF

20%

6.3V
CERM
0402

CRITICAL

1

C2530

10UF

20%

6.3V
2

CERM
0402

SYNC_MASTER=J140 SYNC_DATE=08/23/2018

PAGE TITLE

10UF

20%

6.3V
CERM
0402

VDDQ

A11

VDDQ
VDDQ

A13

VDDQ

B13

VDDQ

C13

VDDQ

D13

VDDQ

E13

VDDQ

F13

VDDQ

G13

VDDQ

H13

VDDQ

J13

VDDQ

U13

VDDQ

V13

VDDQ

W13

VDDQ

Y13

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

CRITICAL

1

C2511

2

CRITICAL

1

C2531

2

10UF

20%

6.3V
CERM
0402

10UF

20%

6.3V
CERM
0402

SYM 3 OF 4

1

2

1

2

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

A15
B15
C15
D15
E15
F15
G15
H15
J15
U15
V15
W15
Y15
AA15
AB15
AC15
AD15
AE15
A17
AE17
A18
AE18
A19
AE19
A23
AE23
A24
AE24
A25
AE25
A27
B27
C27
D27
E27
F27
G27
H27
J27
U27
V27
W27
Y27
AA27
AB27
AC27
AD27
AE27

LPDDR4x Sub-Channels C & D

SIZE

D

Apple Inc.

DRAWING NUMBER

051-05232

REVISION

D

C

B

A

2.0.0

BRANCH

proto4b

PAGE

25 OF 152

SHEET

20 OF 86

BOM_COST_GROUP=DRAM

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

8

67

35 4

2

1

D

www.laptoprepairsecrets.com

138S00035 4

CAP,CER,20UF,20%,2.5V,X6S,HRZTL,0402

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

C2862,C2863,C2864,C2865,C2866,C2867,C2868,C2869

CRITICAL

678

TABLE_5_HEAD

BOM OPTIONCRITICAL

TABLE_5_ITEM

3 245

1

U2800

BURNSIDE-BRIDGE

USBC_HSX_R2D_P<1>

21

USBC_HSX_R2D_N<1>

21

J1
J2

ASSRXP1
ASSRXN1

BGA

SYM 1 OF 2

BSSRXP1
BSSRXN1

J12
J11

USBC_X_D2R_P<1>

USBC_X_D2R_N<1>

BI
BI

26

26

CRITICAL

USBC_HSX_R2D_P<2>

21

USBC_HSX_R2D_N<2>

21

C1
C2

ASSRXP2
ASSRXN2

OMIT_TABLE

BSSRXP2
BSSRXN2

C12
C11

USBC_X_D2R_P<2>
USBC_X_D2R_N<2>

BI
BI

26

26

D

USBC_HSX_D2R_P<1>

21

USBC_HSX_D2R_N<1>

21

G1
G2

ASSTXP1
ASSTXN1

BSSTXP1
BSSTXN1

G12
G11

USBC_X_R2D_CR_P<1>

USBC_X_R2D_CR_N<1>

OUT
OUT

26

26

C

USBC_HSX_D2R_P<2>

21

USBC_HSX_D2R_N<2>

21

23

BI

23

BI

USBC HIGH-SPEED 1 AC COUPLING

GND_VOID=TRUE

5

IN

5

IN

5

BI

5

BI

USBC_HSX_R2D_C_P<1>

GND_VOID=TRUE

USBC_HSX_R2D_C_N<1>

GND_VOID=TRUE

USBC_HSX_D2R_C_P<1>

GND_VOID=TRUE

USBC_HSX_D2R_C_N<1>

C2820

0.22UF

C2821

0.22UF

C2822

0.22UF

C2823

0.22UF

GND_VOID=TRUE

5

IN

5

IN

5

BI

5

BI

USBC_HSX_R2D_C_P<2> USBC_HSX_R2D_P<2>

GND_VOID=TRUE

USBC_HSX_R2D_C_N<2>

GND_VOID=TRUE

USBC_HSX_D2R_C_P<2>

GND_VOID=TRUE

USBC_HSX_D2R_C_N<2>

C2824

0.22UF

C2825

0.22UF

C2826

0.22UF

C2827

0.22UF

21
X5R

21
20%

X5R
21

20%
X5R

21
20% 0201

X5R
21

20%
X5R

21
20% 0201

X5R
21

20%
X5R

21
20%

X5R

USBC_HSX_R2D_P<1>

020120%

6.3V

USBC_HSX_R2D_N<1>

0201

6.3V

USBC_HSX_D2R_P<1>

0201

6.3V

USBC_HSX_D2R_N<1>

6.3V

0201

6.3V

USBC_HSX_R2D_N<2>

6.3V

USBC_HSX_D2R_P<2>

0201

6.3V

USBC_HSX_D2R_N<2>

0201

6.3V

21

21

21

21

21

21

21

21

23

23

OUT

XDP_LSX_TBTA_R2P

IN

XDP_LSX_TBTA_P2R

NOSTUFF

R2808

20K

1/20W

5%
MF

201

24 23

24 23

24 23

23

47

IN

BI
BI

IN

OUT

1

2

R2809

20K

5%

1/20W

MF

201

1

2

USBC_HSX_AUXCH_C_P
USBC_HSX_AUXCH_C_N

I2C_UPC_X_INTM_L
I2C_UPC_X_SCLM

I2C_UPC_X_SDAM
TBT_X_GPIO_5

21

TBT_X_GPIO_6

21

TBT_X_FLASH_SHARE_EN

21

TBT_X_FLASH_MSTR_H_SLV_L
TBT_X_GPIO_12

21

TBT_X_THERM_D_P

TBT_X_XTAL25M_IN

21

TBT_X_XTAL25M_OUT

21

E1
E2

L8
M8

L7

A10

C9
E7

B9
A8
A4
A5
A6

M11

L9
M9

L12
A11

ASSTXP2
ASSTXN2

PA_AUX_P
PA_AUX_N

PA_LSTX_SBU1
PA_LSRX_SBU2

I2C_INT
I2C_SCL
I2C_SDA

POC_GPIO_5
POC_GPIO_6
POC_GPIO_10
POC_GPIO_11
POC_GPIO_12

THERMDA

XTAL_25_IN
XTAL_25_OUT

MONDC_SVR
MONDC

INTERNAL CAPS,

PU, PD

To SPI Flash

TEST_PWR_GOOD

BSSTXP2
BSSTXN2

BSBU1
BSBU2

PERST*
RESET*

TDI
TMS
TCK
TDO

EE_DI

EE_DO
EE_CS*
EE_CLK

TEST_EN

RBIAS
RSENSE

ATEST_P
ATEST_N

E12
E11

M10
L10

B8M7
L11

A3
C3
B5
C5

C6
B4
B6
C7

B11
B3

L4
L5

A1
A2

USBC_X_R2D_CR_P<2>
USBC_X_R2D_CR_N<2>

USBC_X_AUXLSX_P
USBC_X_AUXLSX_N

TBT_XT_PERST_L

USBC_X_RESET_L

JTAG_ISP_TDI

JTAG_TBT_X_TMS

JTAG_ISP_TCK
JTAG_ISP_TDO

SPI_TBT_X_MOSI
SPI_TBT_X_MISO
SPI_TBT_X_CS_L

SPI_TBT_X_CLK

TBT_X_TEST_PWR_GOOD

TBT_X_RBIAS

TBT_X_RSENSE

NC
NC

OUT
OUT

BI
BI

IN
IN

IN
IN
IN

OUT

OUT

IN
OUT
OUT

26

26

24

24

23

27

23

23

23

23

23

23

23

23

2 1

4.75K

0.5%
0201

PLACE_NEAR=U2800.L5:2MM
PLACE_NEAR=U2800.L4:2MM

1/20W TF

R2807

R2806

100

5%

1/20W

MF

201

1

C

2

B

A

PP0V9_TBT_X_SVR

21

CRITICAL

NOSTUFF

1

C2869

20UF

20%

2.5V

2

X6S-CERM
0402-1

NOSTUFF

TBT_X_XTAL25M_OUT_R

5%

25V

C0G

0201
0201

C0G

25V

5%

1

2

2

C2802

20PF

20PF

C2803

1

TBT_X_XTAL25M_IN_R

CRITICAL

NOSTUFF

1

C2868

20UF

20%

2.5V

2

X6S-CERM
0402-1

PP3V3_TBT_X_SX
PP3V3_TBT_X_S0

100K

21

5%

BSB_GP6:BSB_S0

100K
100K

NOSTUFF

100K

NOSTUFF

100K

21

5% 2011/20W MF

21

21

5% 201MF1/20W

21

31

CRITICAL

NOSTUFF

1

C2867

20UF

20%

2.5V

2

X6S-CERM
0402-1

21 23 27

21 23 27

R2850

1/20W MF 201

R2841
R2851

MF1/20W 2015%

R2843

R2845

1/20W5% 201MF

BB XTAL

R2802

0

2 1

0201

CRITICAL

42

5%

1/20WMF

Y2800

25MHZ-25PPM-20PF-50OHM

2.00X1.60-SM

R2803

0

2 1

0201 5%

MF 1/20W

CRITICAL

NOSTUFF

1

C2866

20UF

20%

2.5V

2

X6S-CERM
0402-1

TBT_X_FLASH_SHARE_EN

TBT_X_XTAL25M_OUT

TBT_X_XTAL25M_IN

CRITICAL

OMIT_TABLE

1

C2865

20UF

20%

2.5V

2

X6S-CERM
0402-1

TBT_X_GPIO_5

TBT_X_GPIO_6

TBT_X_GPIO_12

CRITICAL

OMIT_TABLE

1

C2864

20UF

20%

2.5V

2

X6S-CERM
0402-1

21

21

21

21

21

21

CRITICAL

OMIT_TABLE

1

C2863

20UF

20%

2.5V

2

X6S-CERM
0402-1

CRITICAL

OMIT_TABLE

1

C2862

20UF

20%

2.5V

2

X6S-CERM
0402-1

MIN_LINE_WIDTH=0.1400
MIN_NECK_WIDTH=0.0750

VOLTAGE=3.3V

1

C2861

4UF

20%

6.3V

2

CER-X5R
0201

1

C2860

4UF

20%

6.3V

2

CER-X5R
0201

C2854

10UF

CERM
0402

20%

6.3V

1

2

1

2

C2850

4UF

20%

6.3V

CER-X5R
0201

PP3V3_TBT_X_LC

1

C2856

2.2UF

20%

6.3V

2

X5R-CERM
0201

C2855

2.2UF

20%

X5R-CERM

6.3V

0201

1

C2851

4UF

20%

6.3V

2

CER-X5R
0201

1

2

1

2

1

C2857

2.2UF

20%

6.3V

2

X5R-CERM
0201

C2852

4UF

20%

6.3V

CER-X5R
0201

1

C2853

4UF

20%

6.3V

2

CER-X5R
0201

PP0V9_TBT_X_LVR

PP3V3_TBT_X_ANA

23

PP0V9_TBT_X_LC

1

C2858

2.2UF

20%

6.3V

2

X5R-CERM
0201

NC
NC
NC
NC

F6
G6
E9
G9

L6
M6

E5
L2
J3

F3
F5
G5

B1

B12

D1
D11
D12

D2

F1
F11
F12

F2

M12

A12

TEST_EDM

NC_A12

J6

NC_J6

L3

NC_L3

J5

NC_J5

VCC0P9_SVR_ANA

VCC0P9_SVR_PB_ANA

VCC0P9_LVR
VCC0P9_LVR_SENSE

VCC3P3_LC
VCC3P3_ANA
VCC0P9_LC

VSS

VSS_ANA

U2800

BURNSIDE-BRIDGE

BGA

SYM 2 OF 2

CRITICAL

OMIT_TABLE

FORCE_PWR

FLASH_BUSY*

FUSE_VQPS_64

SMBUS_SCL
SMBUS_SDA

VCC3P3_SX

VCC3P3A

VCC3P3_SVR

VCC0P9_SVR

SVR_IND

SVR_VSS

VSS_ANA

B10

A9
B2

A7
B7

E6

J7

M4
M5

E3
G3

L1
M1

M2
M3

F7
F9
G7
H1
H11
H12
H2
J9
K1
K11
K12
K2

TBT_X_FORCE_PWR

TBT_XT_FLASH_BUSY_L

TP_SMBUS_TBT_X_SCL
TP_SMBUS_TBT_X_SDA

PP3V3_TBT_X_VCCA

1

C2843

12PF

5%

25V

2

NP0-C0G
0201

1

C2832

10UF

20%

6.3V

2

CERM
0402

BYPASS=U2800.M4:M3:3MM

1

2

1

2

1

2

0.68UH-20%-4.3A-0.043OHM

PP0V9_TBT_X_SVR_IND

_

VOLTAGE=0.9V
DIDT=TRUE

XW2830

SM

21

TBT_X_THERM_D_N

PLACE_NEAR=U2800.K11:2MM

NO_XNET_CONNECTION=1

CONNECT TO GND PIN
CLOSEST TO THERMDA PIN

BOM_COST_GROUP=TBT

23

IN

23

BI

1

C2830

2.2UF

20%

6.3V

X5R-CERM
0201

C2831

10UF

20%

6.3V

2

CERM
0402

PP3V3_TBT_X_S0_SVR

C2833

10UF

20%

6.3V

CERM
0402

1

C2834

10UF

20%

6.3V

2

CERM
0402

P0V9_TBT_X_SVR_PGND

C2838

12PF

5%

25V

NP0-C0G
0201

1

C2839

4UF

20%

6.3V

2

CER-X5R
0201

CRITICAL

L2800

21

0805

47

OUT

R2800

0

21

5%

1/16W MF-LF

402

1

C2836

2.2UF

20%

6.3V

2

X5R-CERM
0201

R2801

0

21

402

1/16W

1

C2835

10UF

20%

6.3V

2

CERM
0402

1

C2841

4UF

20%

6.3V

2

CER-X5R
0201

PAGE TITLE

5%

MF-LF

PLACE_NEAR=C2832.2:2MM
NO_XNET_CONNECTION=1

1

2

XW2801

SM

21

NO_XNET_CONNECTION=1

XW2800

SM

21

C2840

47UF

20%

6.3V

CER-X5R
0603

USB-C HIGH SPEED X (REAR)

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

FROM USB-C PORT
CONTROLLER (UPC)

PP3V3_TBT_X_SX

1

C2837

2.2UF

20%

6.3V

2

X5R-CERM
0201

1

2

PP3V3_TBT_X_S0

PP0V9_TBT_X_SVR

VOLTAGE=0.9V
DIDT=TRUE

DRAWING NUMBER

051-05232

REVISION

BRANCH

PAGE

SHEET

21 23 27

NOSTUFF

C2842

47UF

20%

6.3V

CER-X5R
0603

21 23 27

21

SYNC_DATE=06/08/2018SYNC_MASTER=CPU_CARD_ICL_Y

2.0.0

proto4b

28 OF 152

21 OF 86

B

A

SIZE

D

8

67

35 4

2

1

D

www.laptoprepairsecrets.com

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

138S00035 4 CRITICAL

CAP,CER,20UF,20%,2.5V,X6S,HRZTL,0402

C2962,C2963,C2964,C2965,C2966,C2967,C2968,C2969

678

TABLE_5_HEAD

BOM OPTIONCRITICAL

TABLE_5_ITEM

3 245

1

U2900

BURNSIDE-BRIDGE

USBC_HST_R2D_P<1>

22

USBC_HST_R2D_N<1>

22

J1
J2

ASSRXP1
ASSRXN1

BGA

SYM 1 OF 2

BSSRXP1
BSSRXN1

J12
J11

USBC_T_D2R_P<1>

USBC_T_D2R_N<1>

BI
BI

26

26

CRITICAL

USBC_HST_R2D_P<2>

22

USBC_HST_R2D_N<2>

22

C1
C2

ASSRXP2
ASSRXN2

OMIT_TABLE

BSSRXP2
BSSRXN2

C12
C11

USBC_T_D2R_P<2>
USBC_T_D2R_N<2>

BI
BI

26

26

D

USBC_HST_D2R_P<1>

22

USBC_HST_D2R_N<1>

22

G1
G2

ASSTXP1
ASSTXN1

BSSTXP1
BSSTXN1

G12
G11

USBC_T_R2D_CR_P<1>

USBC_T_R2D_CR_N<1>

OUT
OUT

26

26

C

USBC_HST_D2R_P<2>

22

USBC_HST_D2R_N<2>

22

23

BI

23

BI

USBC HIGH-SPEED 1 AC COUPLING

GND_VOID=TRUE

5

IN

5

IN

5

BI

5

BI

USBC_HST_R2D_C_P<1>

GND_VOID=TRUE

USBC_HST_R2D_C_N<1>

GND_VOID=TRUE

USBC_HST_D2R_C_P<1>

GND_VOID=TRUE

USBC_HST_D2R_C_N<1>

C2920

0.22UF

C2921

0.22UF

C2922

0.22UF

C2923

0.22UF

GND_VOID=TRUE

5

IN

5

IN

5

BI

5

BI

USBC_HST_R2D_C_P<2>

GND_VOID=TRUE

USBC_HST_R2D_C_N<2>

GND_VOID=TRUE

USBC_HST_D2R_C_P<2>

GND_VOID=TRUE

USBC_HST_D2R_C_N<2>

C2924

0.22UF

C2925

0.22UF

C2926

0.22UF

C2927

0.22UF

21
20%

X5R
21
20%

X5R
21

20% 0201
X5R

21
X5R
21
X5R

21
20%

X5R
21
X5R

21
20%

X5R

USBC_HST_R2D_P<1>

0201

6.3V

USBC_HST_R2D_N<1>

0201

6.3V

USBC_HST_D2R_P<1>

6.3V

USBC_HST_D2R_N<1>

020120%

6.3V

USBC_HST_R2D_P<2>

020120%

6.3V

USBC_HST_R2D_N<2>

0201

6.3V

USBC_HST_D2R_P<2>

020120%

6.3V

USBC_HST_D2R_N<2>

0201

6.3V

22

22

22

22

22

22

22

22

23

23

OUT

XDP_LSX_TBTB_R2P

IN

XDP_LSX_TBTB_P2R

NOSTUFF

R2908

20K

1/20W

5%
MF

201

25 23

20K

5%

1/20W

MF

201

1

2

1

2

R2909

25 23

25 23

23

IN

BI
BI

IN

USBC_HST_AUXCH_C_P
USBC_HST_AUXCH_C_N

I2C_UPC_T_INTM_L
I2C_UPC_T_SCLM

I2C_UPC_T_SDAM
TBT_T_GPIO_5

22

TBT_T_GPIO_6

22

TBT_T_FLASH_SHARE_EN

22

TBT_T_FLASH_MSTR_H_SLV_L
TBT_T_GPIO_12

22

TBT_T_THERM_D_P

23

TBT_T_XTAL25M_IN

22

TBT_T_XTAL25M_OUT

22

E1
E2

L8
M8

L7

A10

C9
E7

B9
A8
A4
A5
A6

M11

L9
M9

L12
A11

ASSTXP2
ASSTXN2

PA_AUX_P
PA_AUX_N

PA_LSTX_SBU1
PA_LSRX_SBU2

I2C_INT
I2C_SCL
I2C_SDA

POC_GPIO_5
POC_GPIO_6
POC_GPIO_10
POC_GPIO_11
POC_GPIO_12

THERMDA

XTAL_25_IN
XTAL_25_OUT

MONDC_SVR
MONDC

INTERNAL CAPS,

PU, PD

To SPI Flash

TEST_PWR_GOOD

BSSTXP2
BSSTXN2

BSBU1
BSBU2

PERST*
RESET*

TDI
TMS
TCK
TDO

EE_DI

EE_DO
EE_CS*
EE_CLK

TEST_EN

RBIAS
RSENSE

ATEST_P
ATEST_N

E12
E11

M10
L10

B8M7
L11

A3
C3
B5
C5

C6
B4
B6
C7

B11
B3

L4
L5

A1
A2

USBC_T_R2D_CR_P<2>
USBC_T_R2D_CR_N<2>

USBC_T_AUXLSX_P
USBC_T_AUXLSX_N

TBT_XT_PERST_L

USBC_T_RESET_L

JTAG_ISP_TDI

JTAG_TBT_T_TMS

JTAG_ISP_TCK
JTAG_ISP_TDO

SPI_TBT_T_MOSI
SPI_TBT_T_MISO
SPI_TBT_T_CS_L

SPI_TBT_T_CLK

TBT_T_TEST_PWR_GOOD

TBT_T_RBIAS

TBT_T_RSENSE

NC
NC

OUT
OUT

BI
BI

IN
IN

IN
IN
IN

OUT

OUT

IN
OUT
OUT

26

26

25 23

25 23

23

27

23

23

23

23

23

23

23

23

2 1

4.75K

0.5%
0201

PLACE_NEAR=U2900.L5:2MM
PLACE_NEAR=U2900.L4:2MM

1/20W

R2907

TF

R2906

100

5%

1/20W

MF

201

1

C

2

B

A

PP0V9_TBT_T_SVR

22

CRITICAL

NOSTUFF

1

C2969

20UF

20%

2.5V

2

X6S-CERM
0402-1

NOSTUFF

TBT_T_XTAL25M_OUT_R

5%

25V

C0G

0201
0201

C0G

25V

5%

1

2

2

C2902

20PF

20PF

C2903

1

TBT_T_XTAL25M_IN_R

CRITICAL

NOSTUFF

1

C2968

20UF

20%

2.5V

2

X6S-CERM
0402-1

PP3V3_TBT_T_SX
PP3V3_TBT_T_S0

100K

R2950

21

5% 201MF

BSB_GP6:BSB_S0

100K
100K

NOSTUFF

100K

NOSTUFF

100K

R2941

21

5% 2011/20W MF

R2951

21

R2943

21

R2945

21

CRITICAL

NOSTUFF

1

C2967

20UF

20%

2.5V

2

X6S-CERM
0402-1

22 27

22 23 27

1/20W

1/20W 2015%

1/20W MF 2015%

MF

BB XTAL

R2902

0

2 1

0201

31

CRITICAL

42

MF

5%

1/20W

TBT_T_XTAL25M_OUT

22

Y2900

NC
NC
NC
NC

M12

A12

J6
L3
J5

TEST_EDM

NC_A12
NC_J6
NC_L3
NC_J5

FORCE_PWR

FLASH_BUSY*

FUSE_VQPS_64

SMBUS_SCL
SMBUS_SDA

B10

A9
B2

A7
B7

TBT_T_FORCE_PWR

TBT_XT_FLASH_BUSY_L

TP_SMBUS_TBT_T_SCL
TP_SMBUS_TBT_T_SDA

IN

BI

23

23

25MHZ-25PPM-20PF-50OHM

2.00X1.60-SM

R2903

2 1

0201

MF5%1/20W

CRITICAL

NOSTUFF

1

C2966

20UF

20%

2.5V

2

X6S-CERM
0402-1

0

1

2

TBT_T_XTAL25M_IN

CRITICAL

OMIT_TABLE

C2965

20UF

20%

2.5V

X6S-CERM
0402-1

CRITICAL

OMIT_TABLE

1

C2964

20UF

20%

2.5V

2

X6S-CERM
0402-1

TBT_T_GPIO_5

TBT_T_GPIO_6

TBT_T_FLASH_SHARE_EN

22

22

22

22

CRITICAL

OMIT_TABLE

1

C2963

20UF

20%

2.5V

2

X6S-CERM
0402-1

CRITICAL

OMIT_TABLE

1

C2962

20UF

20%

2.5V

2

X6S-CERM
0402-1

MIN_LINE_WIDTH=0.1400
MIN_NECK_WIDTH=0.0750

VOLTAGE=3.3V

1

C2961

4UF

20%

6.3V

2

CER-X5R
0201

1

C2960

4UF

20%

6.3V

2

CER-X5R
0201

C2954

10UF

CERM
0402

20%

6.3V

1

2

1

2

C2950

4UF

20%

6.3V

CER-X5R
0201

PP3V3_TBT_T_LC

1

C2956

2.2UF

20%

6.3V

2

X5R-CERM
0201

C2955

2.2UF

20%

X5R-CERM

6.3V

0201

1

C2951

4UF

20%

6.3V

2

CER-X5R
0201

1

2

1

2

1

C2957

2.2UF

20%

6.3V

2

X5R-CERM
0201

1

C2952

4UF

20%

6.3V

CER-X5R
0201

C2953

4UF

20%

6.3V

2

CER-X5R
0201

PP0V9_TBT_T_LVR

PP3V3_TBT_T_ANA
PP0V9_TBT_T_LC

1

C2958

2.2UF

20%

6.3V

2

X5R-CERM
0201

F6
G6
E9
G9

L6
M6

E5
L2
J3

F3
F5
G5

B1

B12

D1
D11
D12

D2

F1
F11
F12

F2

BURNSIDE-BRIDGE

VCC0P9_SVR_ANA

VCC0P9_SVR_PB_ANA

VCC0P9_LVR
VCC0P9_LVR_SENSE

VCC3P3_LC
VCC3P3_ANA
VCC0P9_LC

VSS

VSS_ANA

U2900

BGA

SYM 2 OF 2

CRITICAL

OMIT_TABLE

VCC3P3_SX

VCC3P3A

VCC3P3_SVR

VCC0P9_SVR

SVR_IND

SVR_VSS

VSS_ANA

E6

J7

M4
M5

E3
G3

L1
M1

M2
M3

F7
F9
G7
H1
H11
H12
H2
J9
K1
K11
K12
K2

PP3V3_TBT_T_VCCA

1

C2943

12PF

5%

25V

2

NP0-C0G
0201

1

C2932

10UF

20%

6.3V

2

CERM
0402

BYPASS=U2900.M4:M3:3MM

1

2

1

2

1

2

PP0V9_TBT_T_SVR_IND

VOLTAGE=0.9V
DIDT=TRUE

XW2930

SM

21

TBT_T_THERM_D_N

PLACE_NEAR=U2900.K11:2MM

NO_XNET_CONNECTION=1

CONNECT TO GND PIN
CLOSEST TO THERMDA PIN

C2930

2.2UF

20%

6.3V

X5R-CERM
0201

1

C2931

10UF

20%

6.3V

2

CERM
0402

PP3V3_TBT_T_S0_SVR

C2933

10UF

20%

6.3V

CERM
0402

1

C2934

10UF

20%

6.3V

2

CERM
0402

1

2

P0V9_TBT_T_SVR_PGND

C2938

12PF

5%

25V

NP0-C0G
0201

1

C2939

4UF

20%

6.3V

2

CER-X5R
0201

CRITICAL

1

C2941

4UF

20%

6.3V

2

CER-X5R
0201

L2900

0.68UH-20%-4.3A-0.043OHM

21

0805

23

R2900

0

21

402

5%

1/16W MF-LF

1

C2936

2.2UF

20%

6.3V

2

X5R-CERM
0201

R2901

0

21

1/16W MF-LF

4025%

C2935

10UF

20%

6.3V

CERM
0402

PLACE_NEAR=C2932.2:2MM
NO_XNET_CONNECTION=1

1

2

SYNC_MASTER=CPU_CARD_ICL_Y SYNC_DATE=06/08/2018

PAGE TITLE

XW2901

SM

21

NO_XNET_CONNECTION=1

XW2900

SM

21

C2940

47UF

20%

6.3V

CER-X5R
0603

USB-C HIGH SPEED T (FRONT)

Apple Inc.

FROM USB-C PORT
CONTROLLER (UPC)

PP3V3_TBT_T_SX

1

C2937

2.2UF

20%

6.3V

2

X5R-CERM
0201

PP3V3_TBT_T_S0

PP0V9_TBT_T_SVR

DIDT=TRUE
VOLTAGE=0.9V

DRAWING NUMBER

REVISION

22 27

NOSTUFF

1

C2942

47UF

20%

6.3V

2

CER-X5R
0603

22 23 27

22

051-05232

B

A

SIZE

D

2.0.0

201MF5% 1/20W

TBT_T_GPIO_12

22

BOM_COST_GROUP=TBT

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

BRANCH

proto4b

PAGE

29 OF 152

SHEET

22 OF 86

8

67

35 4

2

1

678

www.laptoprepairsecrets.com

3 245

1

D

C

1

R3060

3.3K

5%
1/20W
MF
201

2

TBT_XT_SPI_CLK

23

TBT_XT_SPI_CS_L

23

TBT_XT_ROM_WP_L

24

TBT_XT_ROM_HOLD_L

NOSTUFF

R3061

3.3K

5%

1/20W

MF

201

R3064

1

2

3.3K

5%

1/20W

MF

201

1

R3063

3.3K

5%
1/20W
MF
201

2

1

2

6

1

3

7

Left Front Port

R3022

1/20W MF5% 201

BOMOPTION=FANTACH:NODEBUG

R3023
R3024
R3025

78 32 23

78 32 23

78 13

78 13

78 31

78 31

AUXLSX Probe Points

SWD_SOC_SWCLK

BI

SWD_SOC_SWDIO

BI

PCH_UART_DEBUG_R2D

IN

PCH_UART_DEBUG_D2R

OUT

USB_SOC_P

BI

USB_SOC_N

BI

R301A

1/20W

R301B

U3060

8MBIT-3.0V

W25Q80DVUXIE

CLK

CS*

WP*(IO2)

HOLD*(IO3)

GND EPAD

21

21

MF5%1/20W 201

21

21

MF1/20W 5% 201

21

5% 2011/20W MF

21

PP3V3_UPC_X_LDO

8

VCC

USON

DI(IO0)
DO(IO1)

OMIT_TABLE

CRITICAL

9

4

100K

100K

100K

201MF5%1/20W

100K

100K

201MF5%

100K

5%
MF

201

1

2

1

2

TBT_XT_SPI_MOSI
TBT_XT_SPI_MISO

R3062

3.3K

1/20W

5
2

SPARE_UPC_T_DBG0_R

MAKE_BASE=TRUE

SPARE_UPC_T_DBG1_R

MAKE_BASE=TRUE

SPARE_UPC_T_DBG2_R

MAKE_BASE=TRUE

SPARE_UPC_T_DBG3_R

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

SPARE_UPC_T_USB3_RP

MAKE_BASE=TRUE

SPARE_UPC_T_USB3_RN

MAKE_BASE=TRUE

23

C3060

1UF

10%

6.3V
CERM
402

ROM

TBT_XT_SPI_CLK

23

TBT_XT_SPI_CS_L

23

TBT_XT_SPI_MOSI

23

TBT_XT_SPI_MISO

23

23

23

DEBUG/USB MUX ALIASES

SPARE_UPC_T_DBG0_R

SPARE_UPC_T_DBG1_R

SPARE_UPC_T_DBG2_R

SPARE_UPC_T_DBG3_R

SWD_SOC_SWCLK

SWD_SOC_SWDIO
PCH_UART_DEBUG_R2D
PCH_UART_DEBUG_D2R

USB_SOC_P

USB_SOC_N

SPARE_UPC_T_USB3_RP

SPARE_UPC_T_USB3_RN

IN

IN

OUT

OUT

BI

BI

BI

BI

BI

BI

BI

BI

25

25

25

25

25

25

25

25

25

25

25

48 25

R3094
R3095
R3096
R3097
R3098
R3090
R3091
R3092
R3093
R3099
R309A
R309B
R309C

NO_XNET_CONNECTION=1

100

15
15
15
15
15
15
15
15
15
15
15
15

21

5% 1/20W MF 201

21

21

5% 1/20W MF 201

21

21

5% 1/20W MF 201

21

21

5% 1/20W MF 201

21

21

5%

21

21

5% 1/20W MF 201

21

21

5% 1/20W MF 201

15

OUT

15

OUT

15

15

23

BI

23

BI

78 32

78 32

TBT_XT_SPI_CLK_DBG
UPC_X_SPI_CLK

201MF1/20W5%

UPC_X_SPI_CS_L
UPC_X_SPI_MOSI

201MF1/20W5%

UPC_X_SPI_MISO
SPI_TBT_X_CLK

201MF1/20W5%

SPI_TBT_X_CS_L
SPI_TBT_X_MOSI

201MF1/20W5%

SPI_TBT_X_MISO

1/20W MF 201

SPI_TBT_T_CLK

201MF1/20W5%

SPI_TBT_T_CS_L
SPI_TBT_T_MOSI

201MF1/20W5%

SPI_TBT_T_MISO

Left Rear Port

USB3_BSSB_D2R_P

USB3_BSSB_D2R_N

USB3_BSSB_R2D_C_P

IN

PCH USB3DCI

USB3_BSSB_R2D_C_N

IN

SWD_SOC_SWCLK_R
SWD_SOC_SWDIO_R
SMC_DEBUGPRT_TX

IN

SMC_DEBUGPRT_RX

OUT

23

24

IN

24

IN

Ace

24

IN

24

OUT

21
23

23 21

BB

23 21

23 21

23 22

23 22

BB

23 22

23 22

IN

IN

IN

OUT

IN

IN

IN

OUT

R3012
R3013

C3010

C3011

R3028
R3029

5% MF 2011/20W

R302A

1/20W 5% MF 201

R302B

21

21

21

21

MF5% 2011/20W

SPI_TBT_X_CLK

21 23

SPI_TBT_X_CS_L

21 23

SPI_TBT_X_MOSI

21 23

SPI_TBT_X_MISO

21 23

SPI_TBT_T_CLK

22 23

SPI_TBT_T_CS_L

22 23

SPI_TBT_T_MOSI

22 23

SPI_TBT_T_MISO

22 23

21

0

21

0

21

0.1UF

10%16V 0201X5R-CERM

21

0.1UF

100K

201MF1/20W 5%

100K

100K

100K

BB / ACE SPI ROM BUS

GND

25

GND

25

GND

25

GND

25

0201MF1/20W 5%

0201MF1/20W 5%

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

SPARE_UPC_X_USB2_RP

MAKE_BASE=TRUE

SPARE_UPC_X_USB2_RN

MAKE_BASE=TRUE

SPARE_UPC_X_USB3_RP

MAKE_BASE=TRUE

SPARE_UPC_X_USB3_RN

MAKE_BASE=TRUE

USB3_BSSB_D2R_R_P

MAKE_BASE=TRUE

USB3_BSSB_D2R_R_N

MAKE_BASE=TRUE

USB3_BSSB_R2D_P

MAKE_BASE=TRUE

USB3_BSSB_R2D_N

MAKE_BASE=TRUE

020116V X5R-CERM10%

MAKE_BASE=TRUE

SPI_TBT_X_CLK

MAKE_BASE=TRUE

SPI_TBT_X_CS_L

MAKE_BASE=TRUE

SPI_TBT_X_MOSI

MAKE_BASE=TRUE

SPI_TBT_X_MISO

MAKE_BASE=TRUE

SPI_TBT_T_CLK

MAKE_BASE=TRUE

SPI_TBT_T_CS_L

MAKE_BASE=TRUE

SPI_TBT_T_MOSI

MAKE_BASE=TRUE

SPI_TBT_T_MISO

MAKE_BASE=TRUE

USB3_BSSB_D2R_R_P

USB3_BSSB_D2R_R_N

USB3_BSSB_R2D_P

USB3_BSSB_R2D_N

SWD_SOC_SWCLK_R
SWD_SOC_SWDIO_R
SMC_DEBUGPRT_TX
SMC_DEBUGPRT_RX

SPARE_UPC_X_USB2_RP

SPARE_UPC_X_USB2_RN

SPARE_UPC_X_USB3_RP

SPARE_UPC_X_USB3_RN

OUT

IN

IN

IN

BI

BI

BI

BI

BI

BI

BI

BI

24

24

24

24

24

24

24

24

24

24

24

24

13

13

13

13

13

IN
IN
IN

OUT

IN

JTAG_ISP_TDI

JTAG_TBT_X_TMS

JTAG_ISP_TCK
JTAG_ISP_TDO

JTAG_TBT_T_TMS

MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE

MAKE_BASE=TRUE

JTAG_ISP_TDI

JTAG_TBT_X_TMS

JTAG_ISP_TCK
JTAG_ISP_TDO

JTAG_ISP_TDI

JTAG_TBT_T_TMS

JTAG_ISP_TCK
JTAG_ISP_TDO

IN
IN
IN

OUT

IN
IN
IN

OUT

21

21

21

21

22

22

22

22

SIGNAL ALIASES

25 81 78 64 31

OUT IN

25 78 32 23

IN OUT

25

OUT

25

IN

24

OUT

24

OUT

24

OUT

24

OUT

32

TP3008

A A

TP-P5 TP-P5

TP3009

21

A

TP-P5

TP3004

A

TP-P5

TP3005

22

A

TP-P5

IN

1

21 5

BI BI
BI

1

21

BI

21

BI

IN

1

22

BI
BI

1

22

BI

22

BI BI

25

IN OUT

25

BI

25

BI

24

OUT

25

OUT

24

OUT

25

OUT

PMU_ACTIVE_READY
SOC_DOCK_CONNECT
SOC_DFU_STATUS
SOC_FORCE_DFU

PD_UPC_X_GPIO1
SOC_DOCK_CONNECT
PD_UPC_X_GPIO9
PD_UPC_X_GPIO10

TP_TBT_WAKE_L

USBC_HSX_AUXCH_C_P
USBC_HSX_AUXCH_C_N
XDP_LSX_TBTA_P2R
XDP_LSX_TBTA_R2P

USBC_HST_AUXCH_C_P
USBC_HST_AUXCH_C_N
XDP_LSX_TBTB_P2R
XDP_LSX_TBTB_R2P
DP_T_HST_HPD

UPC_X_UART_TX
UPC_X_UART_RX

PP3V3_UPC_X_LDO
PP3V3_UPC_T_LDO
GND
NC_UPC_T_I2C_ADDR

MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE

PD_UPC_X_GPIO1

MAKE_BASE=TRUE

SOC_DOCK_CONNECT

MAKE_BASE=TRUE

PD_UPC_X_GPIO9

MAKE_BASE=TRUE

PD_UPC_X_GPIO10

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE

MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE

MAKE_BASE=TRUE
MAKE_BASE=TRUE

MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE

XDP_LSX_TBTA_P2R
XDP_LSX_TBTA_R2P

XDP_LSX_TBTB_P2R
XDP_LSX_TBTB_R2P

ACE A/B RPD STRAPPING

24

24

25

25

BI
BI
BI
BI

USBC_X_CC1
USBC_X_CC2
USBC_T_CC1
USBC_T_CC2

MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE

PMU_ACTIVE_READY

SOC_DOCK_CONNECT

SOC_DFU_STATUS

SOC_FORCE_DFU

R3071

R3074
R3075

5% MF1/20W

100K

100K
100K

TP_TBT_WAKE_L

USBC_HSX_AUXCH_C_P
USBC_HSX_AUXCH_C_N

USBC_HST_AUXCH_C_P
USBC_HST_AUXCH_C_N

DP_T_HST_HPD

R3073

1/20W MF5%

100K

UPC_X_UART_TX
UPC_X_UART_RX

PP3V3_UPC_X_LDO
PP3V3_UPC_T_LDO

NC_UPC_T_I2C_ADDR

USBC_X_CC1

USBC_X_CC2

USBC_T_CC1

USBC_T_CC2

IN

OUT

MF1/20W5% 201

OUT

2015% MF1/20W

201

201

BI
BI
BI

BI
BI
BI

OUT

IN

BI
BI
BI
BI

81 78 40 31

78 64 31

21

78 32 23

21

21

TP3006

1

TP3007

5

1

5

TP-P5

16

16 5

TP3002

1

5

TP-P5

TP3003

5

1

5

TP-P5

16

TP3011

5

1

16

TP-P5

21

24 23

24 23

24 23

25 23

26 24

26 24

26 25

26 25

D

A

A

A

A

C

B

Probe Points for Port X
were removed due to layout
disruption.

POWER ALIASES

PP3V3_UPC_X_LDO

23

PP3V3_UPC_X_LDO

23

PP3V3_UPC_T_LDO

23

PP20V_USBC_X_VBUS

24

PP20V_USBC_X_VBUS

24

PP20V_USBC_T_VBUS

25

PP20V_USBC_T_VBUS

25

MAKE_BASE=TRUE

PP3V3_UPC_X_LDO

MAKE_BASE=TRUE

PP3V3_UPC_T_LDO

MAKE_BASE=TRUE

PP20V_USBC_X_VBUS

MAKE_BASE=TRUE

PP20V_USBC_T_VBUS

PP3012

P3MM

SM

PP3013

P3MM

SM

PP

PP

NC_UPC_X_VDDIO_CFG

24

25

1

1

24 23

25 23

USBC_T_AUXLSX_P

USBC_T_AUXLSX_N

79 78 26

79 78 26

GND

24

GND

24

GND

24

GND

24

GND

25

GND

25

GND

25

GND

25

TBT_T_THERM_D_P

22

TBT_T_THERM_D_N

PLACE_NEAR=U3200.G16:2MM

22

25 22

25 22

BSB_FORCE_PWR:ACE

P3MM

1

P3MM

1

SM
PP

PP3000

SM
PP

PP3001

67 24

25 24 13

67 25

IN

IN

IN

UPC_X_FORCE_PWR

R3050

1/20W 5% MF 0201

BSB_FORCE_PWR:PCH

PCH_BSB_FORCE_PWR

R3051

5%1/20W MF 0201

BSB_FORCE_PWR:ACE

UPC_T_FORCE_PWR TBT_T_FORCE_PWR

R3052

5%1/20W MF 0201

BSB_FORCE_PWR:PCH

21

0

21

0

21

0

TBT_X_FORCE_PWR

OUT

OUT

23 21

23 22

25

IN

NC_UPC_T_VDDIO_CFG

UPC_X_RESET

24

UPC_T_RESET

25

UPC_XT_5V_EN

23

UPC_T_GPIO5

74

UPC_PMU_RESET

24

UPC_PMU_RESET

25

UPC_XT_5V_EN

24

UPC_XT_5V_EN

25

PP1V8_AWAKE

R3072

NC_UPC_X_VDDIO_CFG

MAKE_BASE=TRUE

NC_UPC_T_VDDIO_CFG

MAKE_BASE=TRUE

100K

1/20W MF5%

R3081

1/20W

201

0

R3032

5% MF

1/20W 201

R3033

R3034

1/20W5% MF 201

21

21

SOC_USB_VBUS

MF5% 0201

UPC_PMU_RESET

MAKE_BASE=TRUE

UPC_XT_5V_EN

MAKE_BASE=TRUE

2015% 1/20W MF

100K

100K

100K

21

21

21

B

OUT

23

78 31

64 55

A

PPDCIN_G3H

75

CRITICAL

0603-1

F3000

6A-32V

PLACE_NEAR=U3100:5MM

CRITICAL

0603-1

F3001

6A-32V

PLACE_NEAR=U3200:5MM

USBC_DBG

21

PPHV_INT_X_G3H

MAKE_BASE=TRUE

21

PPHV_INT_T_G3H

MAKE_BASE=TRUE

J3000

505070-1222

M-ST-SM

1413

FUSES FOR UPC

PPHV_INT_X_G3H

PPHV_INT_X_G3H

PPHV_INT_T_G3H

PPHV_INT_T_G3H

78 32 23

78 32 23

SWD_SOC_SWCLK
SWD_SOC_SWDIO

PLACE_NEAR=U3200.F15:2MM

Per Will Ferry, SI will determine R3026 and R3027

24

24

25

25

values during characterization.

SWD_SOC_SW* Placement Topology

SOC

U3900

R3027
R3026

SWD_SOC_SWCLK

Front
U3200
T

5%

21

R3027

BRIDGE ARKANOID CONNACE ARKANOID CONN

USBC_DBG

21

21

SWD_SOC_SWCLK_R

SWD_SOC_SWCLK_R

0

0201MF1/20W

SWD_SOC_SWDIO_R

0

0201MF1/20W 5%

505070-1222

Rear
U3100
X

J3001

M-ST-SM

23

23

BSB_PERST:PLTRST

R3055

18

IN

PLT_RST_3V3_L TBT_XT_PERST_L

100K

BSB_PERST:GPD_7

21

201MF5%1/20W

R3056

14

IN

1413

PCH_STRP_GPD7

5% MF 02011/20W

21

0

R3053

AARDVARKANOID CONN

USBC_DBG

5%1/20W

MAKE_BASE=TRUE

21

0

0201MF

J3002

505070-1222

M-ST-SM

1413

TBT_XT_PERST_L
TBT_XT_PERST_L

SPI ACE

25 24 13

42 32

42 32

42 32

TBT_POC_RESET

I2C_UPC_SCL
I2C_UPC_SDA

SMC

UPC_I2C_INT_L
TBT_XT_SPI_CLK_DBG UPC_T_SWD_DATA

23 25

UPC_X_UART_TX

15

21
43
65
87
109
1211

16

PCH_UPC_I2C_INT_L
XDP_PCH_I2C_UPC_SDA
XDP_PCH_I2C_UPC_SCL
UPC_X_SER_DBG
UPC_T_SER_DBG
UPC_X_UART_RX

PCH

24 42

23 24 42

23 24 42

24

25

24 23 24 23

23 21

21 27

21

21 23

22 27

25 22

TBT_X_FORCE_PWR
PP3V3_TBT_X_S0
PP0V9_TBT_X_LC
TBT_XT_PERST_L
PP3V3_TBT_T_S0
I2C_UPC_T_SDAM

15

21
43
65
87
109
1211

16

I2C_UPC_X_INTM_L
I2C_UPC_X_SCLM
I2C_UPC_X_SDAM
TBT_T_FORCE_PWR
I2C_UPC_T_INTM_L
I2C_UPC_T_SCLM

PP3V3_UPC_X_LDO

24 21

24 21

24 21

23 22

25 22

25 22

23

UPC_X_SWD_DATA

24

UPC_X_SWD_CLK

24

TBT_XT_SPI_MISO

23

XDP_PCH_I2C_UPC_SDA

23 24 42

XDP_PCH_I2C_UPC_SCL

23 24 42

15

21
43
65
87
109
1211

16

TBT_XT_SPI_CS_L
TBT_XT_SPI_CLK
TBT_XT_SPI_MOSI
UPC_T_SWD_CLK

PP3V3_UPC_T_LDO

UART ACE

23

23

23

25

23

OUT

OUT

22

23 21

BOM_COST_GROUP=TBT

PP3V3_TBT_X_SX

PP3V3_G3H_RTC

10K

NOSTUFF

100K

2.2K

21

21

SYNC_MASTER=CPU_CARD_ICL_Y SYNC_DATE=06/08/2018

PAGE TITLE

R3042

21

5%

R3044

1/20W MF5% 201

R3047

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

21 27

24 27 75

201MF1/20W

2015% 1/20W MF

TBT_XT_FLASH_BUSY_L

21

22

TBT_X_FLASH_MSTR_H_SLV_L

TBT_XT_FLASH_BUSY_L
TBT_XT_FLASH_BUSY_L

TBT_XT_FLASH_BUSY_L

24

TP3010

1

TP-P5

A

----

TBT_T_FLASH_MSTR_H_SLV_L

USB-C Support

Apple Inc.

MAKE_BASE=TRUE

21

22

DRAWING NUMBER

051-05232

REVISION

2.0.0

BRANCH

proto4b

PAGE

30 OF 152

SHEET

23 OF 86

A

SIZE

D

8

67

35 4

2

1

678

www.laptoprepairsecrets.com

PRIMARY ACE2 USB-C PORT CONTROLLER (UPC)

3 245

1

D

C

PP3V3_UPC_X_LDO

1M

1M

10K

1M

R3109

21

R3108

21

R3107

21

21

R3105

MF5% 1/20W

201MF5% 1/20W

24 23

I2C_UPC_X_SCLM

2011/20W5% MF

I2C_UPC_X_SDAM

201MF1/20W5%

I2C_UPC_X_INTM_L

201

UPC_X_UART_RX

Either a Testpoint or Arkanoid connector

must be present for GPIO0

(EVEN IN PRODUCTION)

24 23 21

24 23 21

24 23 21

24 23

CRITICAL

R3103

15K

0.1%
1/20W
TF-LF

0201

REAR PORT:

CONNECT UPC SPI TO ROM

FRONT PORT:

GROUND UPC SPI

C3101

1UF

10%

35V

X5R

0402

PP20V_USBC_X_VBUS

1

2

23

D

PPHV_INT_X_G3H

23

MAX 100uF TOTAL ON RAIL

C3100

10UF

PP5V_G3S

75

PP5V_G3S

75

CAP FOR PP_5V0 ON VR PAGE

N8

N6

M7

M5

L8

L6

K7

K5

J8

J6

H7

H5

G8

TYPE-C

G6

VBUS

CRITICAL
OMIT_TABLE

VIN_3V3

VDDIO

VDDIO_CFG

LDO_3V3

VIN_LV

VOUT_LV

VRET

SS

LDO_CORE

VBUS_OPT

PP_HV_OPT

C_CC1

C_CC2

RPD_G1
RPD_G2

C_USB_TP
C_USB_TN

C_USB_BP
C_USB_BN

C_SBU1
C_SBU2

C20

A12
D11

C22
D21

L20
L18

C16

L22

E22

D5

F5

M15
N16

M17
N18

L14
L16

K19
K21

J20
J22

J16
H15

C3102

1.0UF

0201-1

NC_UPC_X_VDDIO_CFG

UPC_X_VRET

UPC_X_SS

PP1V5_UPC_X_LDO_CORE
PP20V_USBC_X_VBUS
PPHV_INT_X_G3H

USBC_X_CC1

USBC_X_CC2

USBC_X_CC1
USBC_X_CC2

USBC_X_USB_TOP_P
USBC_X_USB_TOP_N

USBC_X_USB_BOT_P
USBC_X_USB_BOT_N

USBC_X_SBU1
USBC_X_SBU2

N4

N2

M3

M1

L4

L2

K3

K1

J4

J2

H3

H1

G4

G2

M13

N14

N12

M11

L12

K11

N10

M9

L10

K9

PP_5V0

PP_CABLE

PP_HV

U3100

23

IN

25 23 13

24 23 21

67 23

25 23 13

GND I2C_ADDR
PRIMARY ONLY

1

2

TO SMC

24 23 21

24 23 21

42 23

42 23

42 23

27

23

23

23

23

23

23

23

23

23

42

42

42

23

23

23

23

IN

OUT

IN

IN

IN
OUT
OUT
OUT

IN
OUT
OUT

IN
OUT

IN

BI
BI

BI
BI
OUT

BI
BI
OUT

OUT
OUT

IN
OUT

UPC_X_RESET
TBT_POC_RESET
USBC_X_RESET_L

UPC_X_SER_DBG

PD_UPC_X_GPIO1
I2C_UPC_X_INTM_L

UPC_XT_5V_EN
UPC_X_FORCE_PWR

TBT_XT_FLASH_BUSY_L

PCH_BSB_FORCE_PWR

SOC_DOCK_CONNECT

UPC_PMU_RESET
PD_UPC_X_GPIO9
PD_UPC_X_GPIO10

PP3V3_UPC_X_LDO
GND

23

UPC_X_R_OSC
I2C_UPC_X_SDAM

I2C_UPC_X_SCLM
XDP_PCH_I2C_UPC_SDA

XDP_PCH_I2C_UPC_SCL
PCH_UPC_I2C_INT_L

I2C_UPC_SDA
I2C_UPC_SCL
UPC_I2C_INT_L

UPC_X_SPI_CLK
UPC_X_SPI_MOSI
UPC_X_SPI_MISO
UPC_X_SPI_CS_L

B13
A14
B17

A2
B1

D1
F1
C2
E2
B3
C4
D3
E4
F3
F7

A18

M19
M21

A16
B15

B5
A4
D7

B7
A6
C8

B9
B11
A10

A8

HRESET
MRESET
RESET*

GPIO0

GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10

BUSPOWER

I2C_ADDR
R_OSC

I2CM_SDA_CNFG
I2CM_SCL_CNFG

I2C_SDA1
I2C_SCL1
I2C_IRQ1*

I2C_SDA2
I2C_SCL2
I2C_IRQ2*

SPI_CLK
SPI_MOSI
SPI_MISO
SPI_SSZ

IPU-BOOT

DIGITAL CORE I/O & CONTROL POWER

CD3217B12ACE

FCBGA

20%

6.3V

CERM
0402

20%

6.3V

X5R

1

2

1

2

23

0

R3120

21

1/20W5% MF 0201

VOLTAGE=1.5V

MIN_LINE_WIDTH=0.2800
MIN_NECK_WIDTH=0.0750

23

23

23

BI

23

BI

26

BI

26

BI

26

BI

26

BI

26

BI

26

BI

PP3V3_G3H_RTC

PP1V8_SLPS2R

1

C3105

10UF

20%

6.3V

2

CERM
0402

23 27 75

74

MIN_LINE_WIDTH=0.2800

MIN_NECK_WIDTH=0.0750

VOLTAGE=3.3V

PP3V3_UPC_X_LDO

PP3V3_UPC_X_VOUTLV

1

C3109

0.68UF

5%

6.3V

2

X6S
0402

MIN_LINE_WIDTH=0.4000
MIN_NECK_WIDTH=0.1500

MIN_LINE_WIDTH=0.4000
MIN_NECK_WIDTH=0.1500

1

C3106

1.0UF

20%

6.3V

2

X5R
0201-1

1

C3114

220PF

10%

16V

2

CER-X7R
0201

67 27

1

C3113

220PF

10%

16V

2

CER-X7R
0201

1

C3108

10UF

20%

6.3V

2

CERM
0402

BI

BI

23
24

C

26 23

26 23

B

15

15

BI

BI

USB2_TBT_X_P

USB2_TBT_X_N

L3100

90-OHM-0.1A

EXCX4CE

SYM_VER-1

1

PLACE_NEAR=U3100:5MM

4

32

23

23

24 23

23

23

23

23

23

21

21

23

23

23

23

23

23

23

23

23

BI
BI

IN

OUT

BI
BI
BI
BI

BI
BI

OUT

BI
BI
BI
BI
OUT
BI

IN

OUT

UPC_X_SWD_DATA
UPC_X_SWD_CLK

UPC_X_UART_RX
UPC_X_UART_TX

USB_UPC_X1_P
USB_UPC_X1_N

SPARE_UPC_X_USB2_RP
SPARE_UPC_X_USB2_RN
SPARE_UPC_X_USB3_RP
SPARE_UPC_X_USB3_RN

USBC_X_AUXLSX_P
USBC_X_AUXLSX_N

TBT_XT_ROM_WP_L
USB3_BSSB_D2R_R_P

USB3_BSSB_D2R_R_N
USB3_BSSB_R2D_P
USB3_BSSB_R2D_N
SWD_SOC_SWCLK_R

SWD_SOC_SWDIO_R
SMC_DEBUGPRT_TX
SMC_DEBUGPRT_RX

E20
E16

B19
A20

H19
H21
G20
G22
F19
F21

J12
H11

C12

G12
F11

E8
E12
G16
F15
D15
D19

SWD_DATA
SWD_CLK

UART_RX
UART_TX

USB_RP1_P
USB_RP1_N
USB_RP2_P
USB_RP2_N
USB_RP3_P
USB_RP3_N

AUX_P
AUX_N

HPD

DEBUG0
DEBUG1
DEBUG2
DEBUG3
DEBUG4
DEBUG5
DEBUG6
DEBUG7

IPU
IPU

B

C18
E18
D17
G18

GND
GND
GND
GND

23

23

23

23

GND_OPT
GND_OPT
GND_OPT

GNDPORT_MUX

GND

GND_OPT

A

8

67

A22

H9

N20

B21

K15

N22

BOM_COST_GROUP=USB-C

35 4

PAGE TITLE

USB-C PORT CONTROLLER X (REAR)

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

2

SYNC_DATE=06/08/2018SYNC_MASTER=CPU_CARD_ICL_Y

DRAWING NUMBER

051-05232

REVISION

2.0.0

BRANCH

proto4b

PAGE

31 OF 152

SHEET

24 OF 86

1

A

SIZE

D

678

www.laptoprepairsecrets.com

SECONDARY ACE2 USB-C PORT CONTROLLER (UPC)

3 245

1

D

C

PP3V3_UPC_T_LDO

VOLTAGE=3.3V

1M

1M

10K

R3209

21

5%

R3208

21

1/20W MF

5% 201

R3207

21

1/20W 201

5% MF

21

R3205

5%1M1/20W MF 201

MF1/20W 201

25 23

I2C_UPC_T_SCLM

I2C_UPC_T_SDAM

I2C_UPC_T_INTM_L

UPC_X_UART_TX

Either a Testpoint or Arkanoid connector

must be present for GPIO0

(EVEN IN PRODUCTION)

25 23 22

25 23 22

25 23 22

23 25

REAR PORT:
FRONT PORT:

CRITICAL

15K

0.1%
1/20W
TF-LF

0201

1

2

R3203

CONNECT UPC SPI TO ROM
GROUND UPC SPI

GND I2C_ADDR
PRIMARY ONLY

TO SMC

23

75

75

24 23 13

27

25 23 22

23

67 23

23

24 23 13

23

23

23

25 23 22

25 23 22

42

42

42

42

42

42

23

23

23

PPHV_INT_T_G3H

MAX 100uF TOTAL ON RAIL

PP5V_G3S
PP5V_G3S

CAP FOR PP_5V0 ON VR PAGE

23

23

23

23

23

IN
IN

OUT

IN

IN

IN
OUT
OUT
OUT

IN
OUT
OUT

IN
OUT

IN

UPC_T_RESET
TBT_POC_RESET
USBC_T_RST_L

UPC_T_SER_DBG

PMU_ACTIVE_READY
I2C_UPC_T_INTM_L

UPC_XT_5V_EN
UPC_T_FORCE_PWR

UPC_T_GPIO5

PCH_BSB_FORCE_PWR

SOC_DOCK_CONNECT

UPC_PMU_RESET
SOC_DFU_STATUS
SOC_FORCE_DFU

PP3V3_UPC_T_LDO

NC_UPC_T_I2C_ADDR

23

UPC_T_R_OSC
I2C_UPC_T_SDAM

I2C_UPC_T_SCLM
XDP_PCH_I2C_UPC_SDA

XDP_PCH_I2C_UPC_SCL
PCH_UPC_I2C_INT_L

I2C_UPC_SDA
I2C_UPC_SCL
UPC_I2C_INT_L

GND
GND
GND
GND

23

BI
BI

BI
BI
OUT

BI
BI
OUT

OUT
OUT

IN
OUT

B13
A14
B17

A2
B1

D1
F1
C2
E2
B3
C4
D3
E4
F3
F7

A18

M19
M21

A16
B15

B5
A4
D7

B7
A6
C8

B9
B11
A10

A8

N10

M9

L10

K9

HRESET
MRESET
RESET*

GPIO0

GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10

BUSPOWER

I2C_ADDR
R_OSC

I2CM_SDA_CNFG
I2CM_SCL_CNFG

I2C_SDA1
I2C_SCL1
I2C_IRQ1*

I2C_SDA2
I2C_SCL2
I2C_IRQ2*

SPI_CLK
SPI_MOSI
SPI_MISO
SPI_SSZ

IPU

N4

N2

M3

M1

L4

L2

K3

K1

J4

J2

H3

H1

G4

G2

M13

N14

N12

M11

L12

K11

PP_5V0

PP_CABLE

PP_HV

U3200

CD3217B12ACE

FCBGA

DIGITAL CORE I/O & CONTROL POWER

TYPE-C

G6

G8

H7

H5

CRITICAL
OMIT_TABLE

J6

J8

K5

K7

VBUS

L6

L8

M5

M7

N6

N8

VIN_3V3

VDDIO

VDDIO_CFG

LDO_3V3

VIN_LV

VOUT_LV

VRET

SS

LDO_CORE

VBUS_OPT

PP_HV_OPT

C_CC1

C_CC2

RPD_G1
RPD_G2

C_USB_TP
C_USB_TN

C_USB_BP
C_USB_BN

C_SBU1
C_SBU2

C20

A12
D11

C22
D21

L20
L18

C16

L22

E22

D5

F5

M15
N16

M17
N18

L14
L16

K19
K21

J20
J22

J16
H15

10%

35V

X5R

0402

20%

6.3V

20%

6.3V

X5R

1

2

1

2

1

2

C3201

1UF

C3200

10UF

CERM
0402

C3202

1.0UF

0201-1

NC_UPC_T_VDDIO_CFG

UPC_T_VRET

0

UPC_T_SS

PP1V5_UPC_T_LDO_CORE
PP20V_USBC_T_VBUS
PPHV_INT_T_G3H

USBC_T_CC1

USBC_T_CC2

USBC_T_CC1
USBC_T_CC2

USBC_T_USB_TOP_P
USBC_T_USB_TOP_N

USBC_T_USB_BOT_P
USBC_T_USB_BOT_N

USBC_T_SBU1
USBC_T_SBU2

21

R3220

PP20V_USBC_T_VBUS

PP3V3_G3H_RTC

PP1V8_SLPS2R

23

02015%

MF1/20W

VOLTAGE=1.5V

MIN_LINE_WIDTH=0.2800
MIN_NECK_WIDTH=0.0750

23

23

23

BI

23

BI

26

BI

26

BI

26

BI

26

BI

26

BI

26

BI

1

C3205

10UF

20%

6.3V

2

CERM
0402

23

27 75

74

MIN_LINE_WIDTH=0.2800
MIN_NECK_WIDTH=0.0750

PP3V3_UPC_T_LDO

PP3V3_UPC_T_VOUTLV

1

C3209

0.68UF

5%

6.3V

2

X6S
0402

MIN_LINE_WIDTH=0.4000
MIN_NECK_WIDTH=0.1500

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000

1

C3206

1.0UF

20%

6.3V

2

X5R
0201-1

1

C3214

220PF

10%

16V

2

CER-X7R
0201

67 27

1

C3213

220PF

10%

16V

2

CER-X7R
0201

1

C3208

10UF

20%

6.3V

2

CERM
0402

BI

BI

D

23
25

C

26 23

26 23

B

15

15

BI

BI

USB2_TBT_T_P

USB2_TBT_T_N

L3200

90-OHM-0.1A

EXCX4CE

SYM_VER-1

1

PLACE_NEAR=U3200:5MM

4

32

23

23

25 23

23

23

23

23

23

23 22

23 22

23

48 23

23

23

23

23

23

23

23

BI
BI

IN

OUT

BI
BI
BI
BI

BI
BI

OUT

BI
BI
BI
BI
OUT
BI

IN

OUT

UPC_T_SWD_DATA
UPC_T_SWD_CLK

UPC_X_UART_TX
UPC_X_UART_RX

USB_UPC_T1_P
USB_UPC_T1_N

USB_SOC_P
USB_SOC_N
SPARE_UPC_T_USB3_RP
SPARE_UPC_T_USB3_RN

USBC_T_AUXLSX_P
USBC_T_AUXLSX_N

DP_T_HST_HPD
SPARE_UPC_T_DBG0_R

SPARE_UPC_T_DBG1_R
SPARE_UPC_T_DBG2_R
SPARE_UPC_T_DBG3_R
SWD_SOC_SWCLK

SWD_SOC_SWDIO
PCH_UART_DEBUG_R2D
PCH_UART_DEBUG_D2R

E20
E16

B19
A20

H19
H21
G20
G22
F19
F21

J12
H11

C12

G12
F11

E8
E12
G16
F15
D15
D19

SWD_DATA
SWD_CLK

UART_RX
UART_TX

USB_RP1_P
USB_RP1_N
USB_RP2_P
USB_RP2_N
USB_RP3_P
USB_RP3_N

AUX_P
AUX_N

HPD

DEBUG0
DEBUG1
DEBUG2
DEBUG3
DEBUG4
DEBUG5
DEBUG6
DEBUG7

IPU
IPU

B

GND_OPT
GND_OPT
GND_OPT

GNDPORT_MUX

GND

GND_OPT

C18
E18
D17
G18

GND
GND
GND
GND

23

23

23

23

A

8

67

A22

H9

N20

B21

K15

N22

BOM_COST_GROUP=USB-C

35 4

SYNC_MASTER=CPU_CARD_ICL_Y SYNC_DATE=06/08/2018

PAGE TITLE

USB-C PORT CONTROLLER T (FRONT)

SIZE

D

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

2

DRAWING NUMBER

051-05232

REVISION

2.0.0

BRANCH

proto4b

PAGE

32 OF 152

SHEET

25 OF 86

1

A

678

www.laptoprepairsecrets.com

3 245

1

D

C

B

Left Rear Port

USBC_X_CC1

24 23

2

1

2

1

R3361
R3360

R3363
R3362

SLP0603P2X3-COMBO

GND_VOID=TRUE

CRITICAL

RCLAMP1031ZC

D3360

R3380
R3381

R3382
R3383

SLP0603P2X3-COMBO

GND_VOID=TRUE

CRITICAL

RCLAMP1031ZC

D3381

21

21

21

21

22

22

22

22

USBC_X_R2D_CR_N<1>

IN

USBC_X_R2D_CR_P<1>

IN

USBC_X_D2R_N<1> USBC_X_D2R_R_N<1>

OUT

USBC_X_D2R_P<1>

OUT

USBC_X_SBU2

24

USBC_X_USB_BOT_N

24

USBC_X_USB_BOT_P

24

SLP0603P2X3-COMBO

GND_VOID=TRUE

2

1

USBC_T_USB_BOT_N

25

USBC_T_USB_BOT_P

25

USBC_T_SBU1

25

USBC_T_R2D_CR_P<2>

IN

USBC_T_R2D_CR_N<2>

IN

USBC_T_D2R_P<2>

OUT

USBC_T_D2R_N<2>

OUT

USBC_T_CC2

25 23

2

1

CRITICAL

2

RCLAMP1031ZC

D3362

SLP0603P2X3-COMBO

GND_VOID=TRUE

CRITICAL

2

RCLAMP1031ZC

D3383

1

1

SLP0603P2X3-COMBO

GND_VOID=TRUE

CRITICAL

RCLAMP1031ZC

D3363

SLP0603P2X3-COMBO

GND_VOID=TRUE

CRITICAL

RCLAMP1031ZC

D3382

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

5%

5% 1/20W

2

5% 1/20W

5%

2

1

1/20W5%

1/20W

1

GND_VOID=TRUE

GND_VOID=TRUE

CRITICAL

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

CRITICAL

21

USBC_X_R2D_C_N<1>

2

MF5% 2011/20W

21

USBC_X_R2D_C_P<1>

2

201MF1/20W5%

21

2

MF 2011/20W

21

USBC_X_D2R_R_P<1>

2

MF 201

SLP0603P2X3-COMBO

2

RCLAMP1031ZC

D3361

SLP0603P2X3-COMBO

RCLAMP1031ZC

D3380

1

21

USBC_T_R2D_C_P<2>

2

MF 201

21

USBC_T_R2D_C_N<2>

2

201MF

21

USBC_T_D2R_R_P<2>

2

MF 2011/20W5%

21

USBC_T_D2R_R_N<2>

2

201MF

2

1

CRITICAL

2

X3DFN2

D3364

ESD8011-COMBO

CRITICAL

2

5.5V-6.2PF

0201-THICKSTNCL

D3386

1

1

CRITICAL

X3DFN2

D3365

ESD8011-COMBO

CRITICAL

5.5V-6.2PF

0201-THICKSTNCL

D3387

FOR POR, VERIFY 20% TOLERANCE ON 0.22UF AC COUPLING CAP IS OK

PLACE VBUS CAP NEAR EACH VBUS PIN

516S00457

Mates with:

x on y

BYPASS=J3300.57::10MM

BYPASS=J3300.57::10MM

CRITICAL

1

C3320

0.01UF

10%
25V

2

X5R-CERM
0201

BYPASS=J3300.57::10MM

CRITICAL

1

C3326

0.01UF

10%
25V

2

X5R-CERM
0201

CRITICAL

1

C3321

0.01UF

10%
25V

2

X5R-CERM
0201

BYPASS=J3300.57::10MM

CRITICAL

1

C3327

0.01UF

10%
25V

2

X5R-CERM
0201

BYPASS=J3300.57::10MM

CRITICAL

1

C3322

0.01UF

10%
25V

2

X5R-CERM
0201

BYPASS=J3300.57::10MM

CRITICAL

1

C3328

0.01UF

10%
25V

2

X5R-CERM
0201

BYPASS=J3300.57::10MM

CRITICAL

1

C3323

0.01UF

10%
25V

2

X5R-CERM
0201

BYPASS=J3300.57::10MM

CRITICAL

1

C3325

0.01UF

10%
25V

2

X5R-CERM
0201

PLACE_NEAR=J3300.58:5MM

D3322

TVS2200

WSON

4

IN

5

IN

6

IN

GND

GND

GND

1

2

EPAD

7

3

CRITICAL

K

D3320

X3-WLB1608-1

SDM2U40CSP

A

PP20V_USBC_X_VBUS

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000

VOLTAGE=20V

79 78 23

D

(NO LANE REVERSALS ALLOWED)

TP_USBC_PP20V_X

GND_VOID=TRUE

0.22UF

C3361

10%X5R

C3360

X5R 25V 020110%

GND_VOID=TRUE
GND_VOID=TRUE

C3363
C3362

CER-X5R

CRITICAL

2

1

2

5.5V-6.2PF

0201-THICKSTNCL

1

D3367

CRITICAL

D3366

10%

GND_VOID=TRUE

5.5V-6.2PF

0201-THICKSTNCL

GND_VOID=TRUE

C3380

10%

C3381

GND_VOID=TRUE
GND_VOID=TRUE

C3382

10% 25V 0201CER-X5R

C3383

GND_VOID=TRUE

2

1

CRITICAL

2

X3DFN2

1

D3384

ESD8011-COMBO

CRITICAL

X3DFN2

D3385

ESD8011-COMBO

21

0.22UF

21

0.33UF

21

0.33UF

21

0.22UF

21

0.22UF

21

0.33UF

21

0.33UF

21

020125V

020125VCER-X5R 10%

020125V

020125VX5R

020125VX5R 10%

020125V10%CER-X5R

201

220K

1

2

R3365

220K

1

2

R3384

220K

GND_VOID=TRUE

MF1/20W5%

R3364

201MF5% 1/20W

220K

GND_VOID=TRUE

R3385

GND_VOID=TRUE

1

1/20W MF 2015%

2

201MF1/20W5%

GND_VOID=TRUE

1

2

USBC_X_R2D_N<1>

USBC_X_R2D_P<1>

USBC_X_D2R_CR_N<1>

USBC_X_D2R_CR_P<1>

2011/20W MF5%

220K

1

2

R3367

220K

GND_VOID=TRUE

MF5% 2011/20W

R3366

GND_VOID=TRUE

1

2

USBC_T_R2D_P<2>

USBC_T_R2D_N<2>

USBC_T_D2R_CR_P<2>

USBC_T_D2R_CR_N<2>

2015% MF1/20W

220K

GND_VOID=TRUE

1

2

R3386

2011/20W5% MF

220K

GND_VOID=TRUE

1

2

R3387

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

J3300

20875-056E-01

F-ST-SM

PWR

SIGNAL

PWR

GND

5857

21
43
65
87
109
1211
1413
1615
1817
2019
2221
2423
2625
2827
3029
3231
3433
3635
3837
4039
4241
4443
4645
4847
5049
5251
5453
5655

6059

6261
6463
6665
6867
7069
7271
7473
7675
7877
8079
8281
8483
8685

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

USBC_X_R2D_N<2>

USBC_X_R2D_P<2>

USBC_X_D2R_CR_N<2>

USBC_X_D2R_CR_P<2>

USBC_T_R2D_P<1>

USBC_T_D2R_CR_P<1>

USBC_T_D2R_CR_N<1>

TP_USBC_PP20V_T

201MF1/20W5%

220K

1

2

R3396

220K

1

2

R3377

220K

GND_VOID=TRUE

R3397

220K

GND_VOID=TRUE

MF1/20W 2015%

R3376

GND_VOID=TRUE

1

1/20W MF 2015%

2

GND_VOID=TRUE

1

1/20W 2015% MF

2

0.22UF

X5R

0.22UF

0.33UF

0.33UF

CER-X5R

2015%

220K

1

2

R3394

220K

MF1/20W

GND_VOID=TRUE

R3395

0.22UF

0.22UF

0.33UF

0.33UF

CER-X5R

201MF

220K

1

2

R3375

220K

GND_VOID=TRUE

1/20W5%

R3374

GND_VOID=TRUE

1

2

GND_VOID=TRUE

1

2

GND_VOID=TRUE

21

10% 25V 0201

21

GND_VOID=TRUE

GND_VOID=TRUE

21

21

GND_VOID=TRUE

1/20W 201MF5%

GND_VOID=TRUE

21

21

10%X5R

GND_VOID=TRUE

GND_VOID=TRUE

21

10%CER-X5R 020125V

21

10% 25V 0201

GND_VOID=TRUE

1/20W MF5% 201

C3391
C3390

020125V10%X5R

C3393

25V 0201CER-X5R 10%

C3392

020125V10%

C3370

0201X5R 10%

25V

C3371

020125V

C3372
C3373

USBC_X_R2D_C_N<2>

USBC_X_D2R_R_N<2>

USBC_X_D2R_R_P<2>

2

1

CRITICAL

2

5.5V-6.2PF

0201-THICKSTNCL

D3396

1

CRITICAL

X3DFN2

D3394

ESD8011-COMBO

USBC_T_R2D_C_P<1>

USBC_T_R2D_C_N<1>

USBC_T_D2R_R_P<1>

USBC_T_D2R_R_N<1>

2

1

CRITICAL

2

5.5V-6.2PF

0201-THICKSTNCL

D3377

1

CRITICAL

X3DFN2

D3374

ESD8011-COMBO

GND_VOID=TRUE

R3391

5%

2

2

1/20W MF 2015%

GND_VOID=TRUE

21

MF1/20W 201

R3390

21

USBC_X_R2D_CR_N<2>

USBC_X_R2D_CR_P<2>USBC_X_R2D_C_P<2>

USBC_X_USB_TOP_P
USBC_X_USB_TOP_N

GND_VOID=TRUE

R3393

1/20W5% MF2201

2

1/20W

GND_VOID=TRUE

2

1

CRITICAL

2

X3DFN2

D3395

1

CRITICAL

D3397

21

R3392

21

201MF5%

GND_VOID=TRUE

2

5.5V-6.2PF

0201-THICKSTNCL

1

SLP0603P2X3-COMBO

CRITICAL

2

RCLAMP1031ZC

1

D3391

USBC_X_D2R_N<2>

USBC_X_D2R_P<2>

SLP0603P2X3-COMBO

GND_VOID=TRUE

CRITICAL

RCLAMP1031ZC

D3390

ESD8011-COMBO

GND_VOID=TRUE

R3370

2

2

GND_VOID=TRUE

21

201MF5% 1/20W

R3371

21

201MF5% 1/20W

USBC_T_R2D_CR_P<1>

USBC_T_R2D_CR_N<1>USBC_T_R2D_N<1>

USBC_T_USB_TOP_P
USBC_T_USB_TOP_N

GND_VOID=TRUE

R3372

2

2

GND_VOID=TRUE

2

1

CRITICAL

2

X3DFN2

D3375

1

CRITICAL

D3376

21

201MF5% 1/20W

R3373

21

201MF1/20W5%

GND_VOID=TRUE

2

5.5V-6.2PF

0201-THICKSTNCL

1

SLP0603P2X3-COMBO

CRITICAL

2

RCLAMP1031ZC

1

D3370

USBC_T_D2R_P<1>

USBC_T_D2R_N<1>

SLP0603P2X3-COMBO

CRITICAL

GND_VOID=TRUE

RCLAMP1031ZC

D3371

ESD8011-COMBO

USBC_X_CC2

USBC_X_SBU1

SLP0603P2X3-COMBO

GND_VOID=TRUE

1

CRITICAL

2

RCLAMP1031ZC

1

D3393

2

USBC_T_SBU2

USBC_T_CC1

SLP0603P2X3-COMBO

CRITICAL

GND_VOID=TRUE

2

1

2

RCLAMP1031ZC

1

D3372

24 23

IN

IN

24

24

OUT

OUT

24

SLP0603P2X3-COMBO

GND_VOID=TRUE

CRITICAL

RCLAMP1031ZC

D3392

25

IN

IN

25

25

OUT

OUT

25 23

SLP0603P2X3-COMBO

CRITICAL

GND_VOID=TRUE

RCLAMP1031ZC

D3373

21

21

21

21

C

22

22

22

22

B

A

79 78 23

PP20V_USBC_T_VBUS

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000

VOLTAGE=20V

SDM2U40CSP

Left Front Port

CRITICAL

D3300

X3-WLB1608-1

FOR POR, VERIFY 20% TOLERANCE ON 0.22UF AC COUPLING CAP IS OK

BYPASS=J3300.59::10MM

K

PLACE_NEAR=J3300.59:5MM

D3302

TVS2200

WSON

4

A

IN

5

IN

6

IN

GND

GND

GND

1

2

EPAD

7

3

CRITICAL

1

C3300

0.01UF

10%
25V

2

X5R-CERM
0201

BYPASS=J3300.59::10MM

CRITICAL

1

C3306

0.01UF

10%
25V

2

X5R-CERM
0201

BYPASS=J3300.59::10MM

CRITICAL

1

C3301

0.01UF

10%
25V

2

X5R-CERM
0201

BYPASS=J3300.59::10MM

CRITICAL

1

C3307

0.01UF

10%
25V

2

X5R-CERM
0201

PLACE VBUS CAP NEAR EACH VBUS PIN

BYPASS=J3300.59::10MM

CRITICAL

1

C3302

0.01UF

10%
25V

2

X5R-CERM
0201

BYPASS=J3300.59::10MM

CRITICAL

1

C3308

0.01UF

10%
25V

2

X5R-CERM
0201

BYPASS=J3300.59::10MM

CRITICAL

1

C3303

0.01UF

10%
25V

2

X5R-CERM
0201

BYPASS=J3300.59::10MM

CRITICAL

1

C3305

0.01UF

10%
25V

2

X5R-CERM
0201

Cowling Bosses

860-01443

SH3300

3.1OD1.65ID-1.12H-SM3.1OD1.65ID-1.12H-SM

1

SH3301

1

BOM_COST_GROUP=USB-C

DESIGN: J230/MLB
LAST CHANGE: Mon Oct 1 21:40:18 2018

SYNC_MASTER=X1032_MLB_P4BP SYNC_DATE=02/13/2017

PAGE TITLE

USB-C CONNECTOR

SIZE

D

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

051-05232

REVISION

2.0.0

BRANCH

proto4b

PAGE

33 OF 152

SHEET

26 OF 86

A

8

67

35 4

2

1