Apple MacBook Air 13'' 2020 A2179 Schematics

8

www.laptoprepairsecrets.com

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.

3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

7

6 5 4 3

X1783 MLB-TKSB

LAST_MODIFICATION=Mon Jul 29 19:28:46 2019

LAST_MODIFICATION=Mon Jul 29 19:28:46 2019

2 1

ECNREV DESCRIPTION OF REVISION

CK
APPD

DATE

2019-07-2900189634452 ENGINEERING RELEASED

D

1 1
2
3

2
3

5 5
6
7
8
9
10

6
7
8
9
10

11
12
13

13

14

BOM Configuration
BOM Configuration
PD Parts44
CPU GFX
CPU Misc/JTAG/CFG/RSVD
CPU LPDDR4 Interface
CPU Power
PCH Power
CPU & PCH Grounds
CPU Decoupling
PCH Decoupling
PCH ESPI/SMBUS/UART

LKS

MASTER
CPU_CARD_ICL_Y
CPU_CARD_ICL_Y
CPU_CARD_ICL_Y
CPU_CARD_ICL_Y
CPU_CARD_ICL_Y
CPU_CARD_ICL_Y
CPU_CARD_ICL_Y
CPU_CARD_ICL_Y

11/09/2018Table of Contents

06/08/2018
06/08/2018
06/08/2018
06/08/2018
06/08/2018
06/08/2018
06/08/201811
06/08/2018
06/08/2018

DATESYNCCONTENTSCSAPAGEDATESYNCCONTENTSCSAPAGE

51
52
53
54
55
56
57 06/29/2018
58
59
60
61
62 78
63

65
66
67

Keyboard Backlight 04/15/2019
Audio Connectors

Keyboard & Trackpad 1
68 Keyboard & Trackpad 2
69
70
71
72
74
76
77

DC-In & Battery Connectors

PBUS Supply & Battery Charger

IMVP9 IC

IMVP9 POWER BLOCK

VR: VCCIN_AUX ISL 06/08/2018

VR - 5V, 3V3

VR: VCCPRIM_1P8

PMIC BUCKS AND SWs
79

PMIC LDOs

X1032_MLB_P4BP
AHAAGE_AUD
X260_MLB
X589_CARD_IPD
psm
X1032_MLB_P4BP
J140 MLB (CNL-Y)
psm
CPU_CARD_ICL_Y
J140
psm
X589_BIGSUR
X589_BIGSUR

04/19/2017
02/16/2017
02/16/2017
10/18/2018
02/13/2017

10/18/2018

08/17/2018
10/18/2018
03/16/2017
03/16/2017

D

C

14 06/08/2018

16
17
18
19

21
22
23
24
25
26 USB-C CONNECTOR
27

15
16 PCH PCIe/USB/CLK15
18
19
20
23
25
28
29
30
31
32
33
34

PCH Power Management

CPU/PCH Merged XDP
Chipset Shared Support
Chipset Project Support
LPDDR4x Sub-Channels A & B
LPDDR4x Sub-Channels C & D
USB-C HIGH SPEED X (REAR)
USB-C HIGH SPEED T (FRONT)
USB-C Support
USB-C PORT CONTROLLER X (REAR)
USB-C PORT CONTROLLER T (FRONT)

USB-C DEV SUPPORT

CPU_CARD_ICL_Y
CPU_CARD_ICL_Y
X589_CPU_CNL_Y
CPU_CARD_ICL_Y
CARD_CPU_ICL_YN
J140
J140
CPU_CARD_ICL_Y
CPU_CARD_ICL_Y
CPU_CARD_ICL_Y
CPU_CARD_ICL_Y
CPU_CARD_ICL_Y
X1032_MLB_P4BP

06/08/2018
03/13/2017
06/08/2018
06/08/2018
08/23/2018
08/23/201820
06/08/2018
06/08/2018
06/08/2018
06/08/2018
06/08/2018
02/13/2017
06/11/2018

64
65
66
67
68
69
70
71
72
73
74

76
77

PMIC GPIOs & Control
81 POWER - MEMORY VRs
82
83
84

Power FETs

Power FETs TBT S0

LCD Backlight Driver
85
86
87
90
91

S4E<0> 09/27/2018

S4E<1>

NAND VCC VR

SSD Support
120 Power Aliases - 1
121
122

Power Aliases - 2

Signal Aliases

Memory Bit & Byte Swizzle123

X589_BIGSUR
X589_CPU_CNL_Y
X589_CPU_CNL_Y
CPU_CARD_ICL_Y
X1032_MLB_P4BP
X1032_MLB_P4BP
j213
j213
psm

X589_CPU_CNL_Y
X589_CPU_CNL_Y

J140

03/16/201780
10/12/2018
02/22/2017
06/08/2018
02/13/2017
12/06/2018eDP Display Connector

09/27/2018
10/18/2018

02/21/2017
02/21/201775

08/23/2018

C

B

28

31
32
33
34
35
36
37
38
39
40 SoC Project Support
41

36
3729
38
39
40
41
42

44
45
46
47
48
50

WIFI/BT Desense
WIFI/BT MODULE 1
WIFI/BT MODULE 230
SoC GPIO/SEP/USB/DDR/Test
SoC AOP/AON/SMC 03/16/2017
SoC ISP/I2C/UART/SPI/I2S
SoC PCIe
SoC Power 1
SoC Power 2 86 152 Power Block Diagram
SoC Power 3
SoC Ground
SoC Shared Support

Secure Element

j140
J213_METE
J213_METE
X589_BIGSUR
X589_BIGSUR
X589_BIGSUR
X589_BIGSUR
X589_BIGSUR
X589_BIGSUR
X589_BIGSUR
X589_BIGSUR
X589_BIGSUR
X589_BIGSUR
X941_MLB

09/20/2018
11/04/2018
10/17/2018
03/15/2017

03/15/2017
03/15/2017
02/13/201743
02/13/2017
02/13/2017
02/13/2017
03/16/2017
02/13/2017
03/10/2017

78
79
80
81
82

84

124
127
128
140
141
142
143
14585

ICT FCT

Desense Caps 1

Desense Caps 2

Dev Support

BOM Variants 1

BOM Variants 283

BOM Variants 3

BOM Alternates

X589_BIGSUR

04/12/2017

B

A

42
43
44
45
46
47 Thermal Sensors
48
49
50

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

SCH,MLB-TKSB,X1783051-05232 1 CRITICALSCH SCHEM

PCBF,MLB-TKSB,X1783820-01958 1 CRITICALMLB PCBF

J230GHUB = https://github.pie.apple.com/MobileMacIX/j230_hw/blob/master/

52
53
54
55
56
58
60
61
64

I2C Connections 1
I2C Connections 2
Power Sensors High Side

Power Sensors Extended

Fans
RIO Connector
Audio Speaker Amplifiers

BOM OPTIONCRITICAL

TABLE_5_HEAD

TABLE_5_ITEM

TABLE_5_ITEM

X589_BIGSUR
X589_BIGSUR
psm
X1032_MLB_P4BP

X1032_MLB_P4BP
X1032_MLB_P4BP

AHAAGE_AUD

RULER_RULE_SET=RIGID_2016

MULTIPLES

1,1.5,1.75,2.6,2-7,7.5,8,9,10

ISL2-ISL3,ISL6,ISL9,ISL12-ISL13 3.125 1.23.125

02/13/2017
02/13/2017
10/18/2018
02/14/2017Power Sensors Load Side

02/14/2017
02/13/2017

05/23/2017

MANUFACTURING CONFIGURATION

DIELECTRIC BASED SPACING RULES

SMDPIN2SMDPIN MAX(UM)MVIA MAX(UM)SMDPIN MAX(UM)

LAYERS

TOP,BOTTOM 2.82.8 1.0

ISL4,ISL11 3.125 1.23.125

ISL5,ISL10 1.22.2722.272

2.23ISL7,ISL8 1.32.23

MINIMUM CU SPACING RATIOMINIMUM TO DEFAULT RATIOMINIMUM CU WIDTH RATIO

DEFAULT SPACING

MULTIPLES

TABLE_REV_NUMBER=1

VOID SPACE

RATIO

2180 8080

DRAWING TITLE

SCHEM,MLB-TKSB,X1783

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

051-05232

REVISION

2.0.0

BRANCH

proto4b

PAGE

1 OF 152

SHEET

1 OF 86

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SYNC_DATE=11/09/2018SYNC_MASTER=LKS

SIZEDRAWING NUMBER

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3

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www.laptoprepairsecrets.com

3 245

1

D

C

B

A

Module Parts

CPU

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

1 CRITICAL337S00749

CPU,ICL-YN,QSLN,D1,64EU,1.0,1.1,BGA1044

1 CRITICALU0500337S00750

CPU,ICL-YN,QSLQ,D1,48EU,0.7,1.05,BGA1044

998-17650 1 U0500

337S00766 1 U0500 CRITICAL CPU_ICLY:BEST

337S00767 1 CRITICALU0500 CPU_ICLY:BEDRE

INTERPOSER,VTT ADAPTER,ICL-YN,BGA1044

CPU,ICLYN,QSEQ,EES,D2,1,1.1,BGA1044

CPU,ICLYN,QSES,EES,D2,.7,1.05,BGA1044

1 CRITICALU0500 CPU_ICLY:GOOD337S00765

CPU,ICLYN,QSVZ,EES,D2,1.1,.9,BGA1044

NOTE: BEDRE is Danish for BETTER.

TBT Burnside Bridge

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

IC,BURNSIDE BRIDGE,USB/TB RETIMER,BGA105

998-13316 U2800,U2900

2 TBT_BB:A0CRITICAL

IC,TBT,BURNSIDE BRDGE,QURW,ES2,A1,BGA105

2 U2800,U2900

IC,TBT,BURNSIDE BRDGE,ES2,QS,A1,BGA105

IC,TBT,BURNSIDE BRDGE,PRQ,A1,BGA105

U2800,U29002

CRITICAL TBT_BB:A1338S00503

Ace2

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

353S01826 CRITICALU3100,U32002

353S01960 2

353S02158 ACE2:B12_BGA

IC,CD3217,ACE2,B1,USB PWR SW W/HV,BGA123

IC,CD3217,ACE2,B2,USB PWR SW W/HV,BGA123

IC,CD3217,ACE2,B1,USB PWR SW W/HV,BGA123

CRITICAL ACE2:B2_BGAU3100,U3200

CRITICAL2 U3100,U3200

SOC

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

POP,GIBRALTAR+1GB 20NM,M,B0,SCK,CSP1406

PART NUMBER

U3900339S00370 1 SOC:B0_1GCRITICAL

TABLE_ALT_HEAD

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

TABLE_ALT_ITEM

Hynix 1GB SCKALLSOC:B0_1G339S00370339S00371

TABLE_ALT_ITEM

ALL Micron 1GB SCK339S00370339S00375 SOC:B0_1G

TABLE_ALT_ITEM

ALL Hynix 1GB ATK339S00370339S00376 SOC:B0_1G

POP,GIBRALTAR+2GB 20NM,M,B0,SCK,CSP1406

PART NUMBER

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

CRITICAL SOC:B0_2G339S00372 U39001

TABLE_ALT_HEAD

TABLE_ALT_ITEM

ALL339S00372339S00373 Hynix 2GB SCKSOC:B0_2G

TABLE_ALT_ITEM

Micron 2GB SCKALLSOC:B0_2G339S00372339S00377

TABLE_ALT_ITEM

Hynix 2GB ATKALLSOC:B0_2G339S00372339S00378

PMU

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

IC,PMU,CALPE,D2249A0,OTP-AI,CSP324,0.4P

Wireless

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

MODULE,WIFI/BT,SAPPORO,ES3.1,M,LGA451

1

PART NUMBER

998-16405 ALLWIRELESS:P0339S00616

339S00616 1 WIRELESS:P1U3701 CRITICAL

MODULE,WIFI/BT,SAPPORO,ES3.1,M,LGA451

PART NUMBER

339S00628 339S00616 ALLWIRELESS:P1

MODULE,WIFI/BT,SAPPORO,ES3.1,M,LGA451

PART NUMBER

339S00632 WIRELESS:P1B ALL339S00616

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

USI Wireless Module (ES2)

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

USI Wireless Module (ES2)

U3701

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

USI Wireless Module (ES3.1)

CRITICAL339S00616 WIRELESS:P0U3701

TABLE_ALT_HEAD

TABLE_ALT_ITEM

TABLE_ALT_HEAD

TABLE_ALT_ITEM

TABLE_ALT_HEAD

TABLE_ALT_ITEM

BOM OPTIONCRITICAL

CPU_ICLY_P2:BESTU0500

CPU_ICLY_P2:GOOD

CPU_ICLY:INTERPOSERCRITICAL

BOM OPTIONCRITICAL

TBT_BB:QSA1338S00508 2 CRITICALU2800,U2900

TBT_BB:PRQA1338S00561 CRITICAL

BOM OPTIONCRITICAL

ACE2:B1_BGA

BOM OPTIONCRITICAL

BOM OPTIONCRITICAL

PMU:A0_ACRITICALU78001338S00267

BOM OPTIONCRITICAL

WIRELESS:P1BCRITICAL1339S00616

TABLE_5_HEAD

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_HEAD

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_HEAD

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_HEAD

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_HEAD

TABLE_5_ITEM

TABLE_5_HEAD

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

NAND - Landing 0

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

NAND,3DV4,64GBT,S4E,256G,H,SUBX,SLGA110

TABLE_ALT_HEAD

PART NUMBER

998-17175998-17176

NAND,3DV4,64GBT,S4E,256G,T,SUB X,SLGA110

NAND_L0:ITLC_128G_HY

U8600

PART NUMBER

998-16395 U8600

335S00416 CRITICAL1

998-16396 NAND_L0:ITLC_256G_TO

998-16394

NAND,3DV5,64GBT,S4E,256G,SS,SLGA110

NAND,3DV4,128GBT,S4E,256G,T,SUBX,SLGA110

NAND_L0:ITLC_128G_TO

PART NUMBER

998-16396998-16397

NAND,3DV4,128GBT,S4E,256G,SD,SUBX,BGA110

NAND_L0:ITLC_256G_TO

U8600

PART NUMBER

998-16945998-16970

NAND,3DV4,128GBT,S4E,256G,H,SLGA110

NAND,3DV4,256GBT,S4E,256G,T,SUBX,SLGA110

NAND_L0:ITLC_256G_SD

U8600

PART NUMBER

998-16400 U8600998-16401

335S00397 1 U8600

335S00408 CRITICAL

335S00391 1

335S00380 CRITICAL

335S00433 CRITICALU8600

NAND,3DV4,320GBT,XXX,S4E,256G,T,SLGA110

NAND,3DV4,320GBT,XXX,S4E,256G,SD,SLGA110

NAND,3DV4,512GBT,XXX,S4E,256G,SD,SLGA110

NAND,3DV4,512GBT,S4E,256G,H,SLGA110

NAND,3DV4,1TBT,XXX,S4E,512G,SD,SLGA110

NAND,3DV5,1024GBT,S4E,512G,H,SLGA110

NAND_L0:ITLC_512G_TO

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

TABLE_ALT_ITEM

HY 64G Substrate 2 L0

CRITICAL1 U8600

TABLE_ALT_HEAD

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

TABLE_ALT_ITEM

TO 64G Substrate 2 L0

CRITICAL1 U8600

TABLE_ALT_HEAD

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

TABLE_ALT_ITEM

TO 128G Substrate 2 L0

U86001998-16945 CRITICAL NAND_L0:ITLC_256G_SD

TABLE_ALT_HEAD

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

TABLE_ALT_ITEM

SD 128G Substrate 2 L0

U8600

TABLE_ALT_HEAD

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

TABLE_ALT_ITEM

TO 256G Substrate 2 L0

CRITICAL

U86001 NAND_L0:ITLC_512G_SD

U86001 NAND_L0:ITLC_1P0T_HY

CRITICALU86001

BOM OPTIONCRITICAL

NAND_L0:ITLC_128G_HYCRITICALU86001998-17175

NAND_L0:ITLC_128G_TO998-16394

NAND_L0:ITLC_128G_SSU8600

NAND_L0:ITLC_256G_HY1 CRITICAL335S00378

NAND_L0:ITLC_512G_TOU8600998-16400 CRITICAL1

NAND_L0:ITLC_512G_TO_P1

NAND_L0:ITLC_1P0T_SDU8600 CRITICAL

NAND_L0:ITLC_2P0T_SD1

NAND_L0:ITLC_2P0T_HY335S00444

NAND - Landing 1

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

998-17175 NAND_L1:ITLC_128G_HYCRITICAL1 U8700

998-17176 998-17175

998-16394 NAND_L1:ITLC_128G_TO

998-16395 U8700

335S00416 CRITICAL

998-16396 1 NAND_L1:ITLC_256G_TO

998-16397 998-16396 U8700

998-16971 998-16946 U8700

335S00391 NAND_L1:ITLC_1P0T_SD

335S00444

NAND,3DV4,64GBT,S4E,256G,H,SUBX,SLGA110

PART NUMBER

NAND,3DV4,64GBT,S4E,256G,T,SUB X,SLGA110

PART NUMBER

998-16394

NAND,3DV5,64GBT,S4E,256G,SS,SLGA110

NAND,3DV4,128GBT,S4E,256G,T,SUBX,SLGA110

PART NUMBER

NAND,3DV4,128GBT,S4E,256G,SD,SUBX,BGA110

PART NUMBER

998-16945998-16970

NAND,3DV4,128GBT,S4E,256G,H,SLGA110

NAND,3DV4,256GBT,XXX,S4E,256G,T,SLGA110

1 CRITICALU8700335S00396

NAND,3DV4,256GBT,S4E,256G,SD,SUBX,BGA110

PART NUMBER

NAND,3DV4,512GBT,XXX,S4E,256G,SD,SLGA110

NAND,3DV4,512GBT,S4E,256G,H,SLGA110

1 U8700 CRITICAL NAND_L1:ITLC_1P0T_HY335S00380

NAND,3DV4,1TBT,XXX,S4E,512G,SD,SLGA110

NAND,3DV5,1024GBT,S4E,512G,H,SLGA110

NAND_L1:ITLC_128G_HY

NAND_L1:ITLC_128G_TO

NAND_L1:ITLC_256G_TO

NAND_L0:ITLC_256G_SD

NAND_L1:ITLC_512G_SD

U8700

U8700

TABLE_ALT_HEAD

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

TABLE_ALT_ITEM

HY 64G Substrate 2 L1

CRITICALU87001

TABLE_ALT_HEAD

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

TABLE_ALT_ITEM

TO 64G Substrate 2 L1

U87001 NAND_L1:ITLC_128G_SS

U8700 CRITICAL

TABLE_ALT_HEAD

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

TABLE_ALT_ITEM

TO 128G Substrate 2 L1

U87001998-16945

CRITICAL NAND_L1:ITLC_256G_SD

TABLE_ALT_HEAD

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

TABLE_ALT_ITEM

SD 128G Substrate 2 L1

CRITICAL1998-16946 U8700 NAND_L1:ITLC_512G_SD

TABLE_ALT_HEAD

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

TABLE_ALT_ITEM

SD 128G Substrate 2 L1

U87001 CRITICAL

U8700 NAND_L1:ITLC_2P0T_SD

CRITICAL1335S00433

BOM OPTIONCRITICAL

NAND_L1:ITLC_256G_HY335S00378 U87001 CRITICAL

NAND_L1:ITLC_512G_SSUB_TO

NAND_L1:ITLC_2P0T_HYU87001 CRITICAL

DRAM

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

IC,LPDDR4X-3733,32GBIT,18NM,S,BGA432

333S00138 U2300,U2500 DRAM:P1_SAMSUNG_16GB

333S00221

333S00222

2 CRITICAL

IC,LPDDR4X-3733,64GBIT,18NM,S,BGA432

IC,LPDDR4X-4266,32GBIT,16NM,S,BGA432

IC,LPDDR4X-4266,64GBIT,16NM,S,BGA432

2 U2300,U2500 DRAM:HYNIX_8GBCRITICAL333S00214

IC,LPDDR4X-4266,32GBIT,19NM,H,BGA432

IC,LPDDR4X-4266,64GBIT,19NM,H,BGA432

IC,LPDDR4X-3733,32GBIT,18NM,BGA432

IC,LPDDR4X-3733,64GBIT,18NM,BGA432

U2300,U25002 CRITICAL DRAM:HYNIX_16GB333S00215

U2300,U2500333S00170 2 DRAM:MICRON_8GBCRITICAL

U2300,U2500333S00171 2

CRITICAL2 U2300,U2500333S00137 DRAM:P1_SAMSUNG_8GB

CRITICAL2 DRAM:SAMSUNG_8GBU2300,U2500

CRITICAL DRAM:SAMSUNG_16GB2 U2300,U2500

CRITICAL DRAM:MICRON_16GB

BOM OPTIONCRITICAL

TABLE_5_HEAD

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_HEAD

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_HEAD

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

Programmables

TBT ROM

335S00232

341S01315

341S01337

341S01410

341S01450

341S01470

1 TBT_ROM:BLANKU3060 CRITICAL335S00133

IC,SPI SERIAL FLASH,8MBITS,3.0V,USON8

PART NUMBER

335S00133

1

IC,NVM (V14.1) PROTO-0,X1418

ROM,TBT (V14.1.1) PROTO-0-2,X1418

ROM,TBT (VXXXXXX) PROTO-0-3,X1418

ROM,TBT (V14.4) PROTO-1,X1418

1

ROM,BBR (VXXXX) PROTO-2,X1418

ROM,BBR,ACE (V18.9) PROTO-3,X1418

ROM,BBR,ACE (V29.3) PROTO-4A,X1783

ROM,BBR/ACE (VXXXX) PROTO-4,X1783

TBT_ROM:BLANK

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

U3060

TABLE_ALT_HEAD

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

TABLE_ALT_ITEM

rdar://problem/50598337

CRITICAL TBT_ROM:P1U3060

U3060

U30601 CRITICAL TBT_ROM:P3

U30601 TBT_ROM:P4ACRITICAL

CRITICAL1 U3060

BOM OPTIONCRITICAL

TBT_ROM:P0U3060 CRITICAL341S01282

TBT_ROM:P0A1 U3060 CRITICAL341S01314

TBT_ROM:P0B1 CRITICALU3060

TBT_ROM:P2CRITICAL1

TBT_ROM:P4B341S01515

BT ROM

341S01260

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

IC,SPI SERIAL FLASH,4M BIT,1.8V,USON8

1 CRITICAL335S00400 BT_ROM:BLANKU3750

ROM,BT SFLASH (VXX) PROTO-1,X1536

CRITICAL BT_ROM:P01 U3750

BOM OPTIONCRITICAL

Wifi ROM

1

IC,EEPROM,SER,UWIRE,16K,1.8V,DFN8

1

IC,WIFI ROM (V00) WW1,X1421

ROM,WIFI (VXX) (NEW FOR DVT) WW1,X1536

1 CRITICALU3710341S01394

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

CRITICALU3710 WIFI_ROM:BLANK335S00214

BOM OPTIONCRITICAL

WIFI_ROM:P0U3710 CRITICAL341S01087

WIFI_ROM:P2

SOC ROM

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

335S00203 U47701 CRITICAL SOC_ROM:BLANK

IC,FLASH,SERIAL,SPI,4MX8,1.8V,4X3MM,DFN8

PAGE TITLE

BOM OPTIONCRITICAL

BOM Configuration

DRAWING NUMBER

051-05232

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

REVISION

2.0.0

BRANCH

proto4b

PAGE

2 OF 152

SHEET

2 OF 86

TABLE_5_HEAD

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_HEAD

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_HEAD

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_HEAD

TABLE_5_ITEM

D

C

B

A

SIZE

D

8

67

35 4

2

1

678

www.laptoprepairsecrets.com

3 245

1

D

BOM Groups

BOM GROUP BOM OPTIONS

MLB_COMMON

MLB_PROGPARTS

MLB_POWER

MLB_MECH
MLB_MISC

MLB_TBT

MLB_TBT_OPTS

MLB_DESENSE DES:INTER

SCHEM,PCBF,ALTERNATE,COMMON,MLB_PROGPARTS,MLB_USBC,MLB_POWER,MLB_WIRELESS,MLB_MECH,MLB_MISC,MLB_TBT,MLB_TBT_OPTS,PROTO4

TBT_BB:PRQA1,ACE2:B12_BGAMLB_USBC

BT_ROM:P0,SOC_ROM:BLANK,TBT_ROM:P4B,WIFI_ROM:P2,SE:DEV_SW_N

WIRELESS:P1BMLB_WIRELESS

BRACKET,SHLD_CAN_DRAM,SHLD_CAN_BSB,SHLD_FNC_SOC

BOARDID0,BOARDID1,BOARDID2,BOARDID3,BOARDID4,BOARDID5,SYSDET:FET,BOOTCFG0,RAMCFG3_L,RAMCFG4_L

BSB_X_PWR:SWSW_VOUTLV,BSB_T_PWR:SWSW_VOUTLV,BSB_PERST:PLTRST

BSB_FORCE_PWR:ACE,BSB_GP6:BSB_S0

CPUCFG:STRAPSMLB_CPUCFG

See <rdar://problem/50175583> for BOARDID straps

PMU:A0_A

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_5_HEAD

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

CBOM CRITICAL CMN_PARTS_BOM685-00329 COMMON PARTS,MLB-TKSB,X17831

CRITICAL1 DEV_PARTS_BOMDEV1985-01143 DEV PARTS,MLB-TKSB,X1783

BOM OPTIONCRITICAL

TABLE_5_ITEM

TABLE_5_ITEM

D

C

https://confluence.sd.apple.com/display/EMBEDDEDPLATFORM/BOARD_ID+Allocation

Build Specific Groups

BOM GROUP BOM OPTIONS

PROTO4

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

BOARDREV0

C

B

NAND Configs

BOM GROUP BOM OPTIONS

NANDCFG:ITLC_S4E_128G_HY
NANDCFG:ITLC_S4E_128G_TO
NANDCFG:ITLC_S4E_128G_SS
NANDCFG:ITLC_S4E_256G_TO
NANDCFG:ITLC_S4E_256G_SD
NANDCFG:ITLC_S4E_256G_HY
NANDCFG:ITLC_S4E_512G_TO
NANDCFG:ITLC_S4E_512G_SD
NANDCFG:ITLC_S4E_1P0T_SD
NANDCFG:ITLC_S4E_1P0T_HY
NANDCFG:ITLC_S4E_2P0T_SD
NANDCFG:ITLC_S4E_2P0T_HY

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

NAND_L0:ITLC_128G_HY,NAND_L1:ITLC_128G_HY,SOC:B0_1G,S4E,SSD_PWR:S4E

TABLE_BOMGROUP_ITEM

NAND_L0:ITLC_128G_TO,NAND_L1:ITLC_128G_TO,SOC:B0_1G,S4E,SSD_PWR:S4E

TABLE_BOMGROUP_ITEM

NAND_L0:ITLC_128G_SS,NAND_L1:ITLC_128G_SS,SOC:B0_1G,S4E,SSD_PWR:S4E

TABLE_BOMGROUP_ITEM

NAND_L0:ITLC_256G_TO,NAND_L1:ITLC_256G_TO,SOC:B0_1G,S4E,SSD_PWR:S4E

TABLE_BOMGROUP_ITEM

NAND_L0:ITLC_256G_SD,NAND_L1:ITLC_256G_SD,SOC:B0_1G,S4E,SSD_PWR:S4E

TABLE_BOMGROUP_ITEM

NAND_L0:ITLC_256G_HY,NAND_L1:ITLC_256G_HY,SOC:B0_1G,S4E,SSD_PWR:S4E

TABLE_BOMGROUP_ITEM

NAND_L0:ITLC_512G_TO_P1,NAND_L1:ITLC_512G_SSUB_TO,SOC:B0_1G,S4E,SSD_PWR:S4E

TABLE_BOMGROUP_ITEM

NAND_L0:ITLC_512G_SD,NAND_L1:ITLC_512G_SD,SOC:B0_1G,S4E,SSD_PWR:S4E

TABLE_BOMGROUP_ITEM

NAND_L0:ITLC_1P0T_SD,NAND_L1:ITLC_1P0T_SD,SOC:B0_2G,S4E,SSD_PWR:S4E

TABLE_BOMGROUP_ITEM

B

NAND_L0:ITLC_1P0T_HY,NAND_L1:ITLC_1P0T_HY,SOC:B0_2G,S4E,SSD_PWR:S4E

TABLE_BOMGROUP_ITEM

NAND_L0:ITLC_2P0T_SD,NAND_L1:ITLC_2P0T_SD,SOC:B0_2G,S4E,SSD_PWR:S4E

TABLE_BOMGROUP_ITEM

NAND_L0:ITLC_2P0T_HY,NAND_L1:ITLC_2P0T_HY,SOC:B0_2G,S4E,SSD_PWR:S4E

A

CPU DRAM SPD Straps

BOM GROUP BOM OPTIONS

DRAMCFG:SAMSUNG_8GB

DRAMCFG:SAMSUNG_16GB

DRAMCFG:HYNIX_8GB
DRAMCFG:HYNIX_16GB
DRAMCFG:MICRON_8GB

DRAMCFG:MICRON_16GB

DRAM:SAMSUNG_8GB,RAMCFG0_L
DRAM:SAMSUNG_16GB,RAMCFG0_L,RAMCFG2_L
DRAM:HYNIX_8GB,RAMCFG0_L,RAMCFG1_L
DRAM:HYNIX_16GB,RAMCFG0_L,RAMCFG1_L,RAMCFG2_L
DRAM:MICRON_8GB
DRAM:MICRON_16GB,RAMCFG2_L

RAMCFGx strap is low if in table.

CPU DRAM CFG Chart

Vendor

Hynix
Samsung
Unused
Micron

CFG 1

0
1
0
1

CFG 0

0
0
1
1

Vendor

8GB
16GB

CFG 2

1
0

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

PAGE TITLE

BOM Configuration

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

051-05232

REVISION

2.0.0

BRANCH

proto4b

PAGE

3 OF 152

SHEET

3 OF 86

A

SIZE

D

8

67

35 4

2

1

678

www.laptoprepairsecrets.com

3 245

1

Shield Cans

D

Mounting Bracket

806-22435

BRKT,MOUNTING,MLB,NK,X1766

DRAM Shield Can

TABLE_5_HEAD

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

BOM OPTIONCRITICAL

TABLE_5_ITEM

SHIELD CAN,DRAM,X1030

BRACKETCRITICALBRKT11

1 CRITICALSHLD1 SHLD_CAN_DRAM806-12387

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

BOM OPTIONCRITICAL

TABLE_5_HEAD

TABLE_5_ITEM

D

Burnside Bridge Shield Can

TABLE_5_HEAD

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

806-19070 SHLD31 CRITICAL SHLD_CAN_BSB

SHIELD CAN,BURNSIDE BRIDGE,X1419

BOM OPTIONCRITICAL

TABLE_5_ITEM

C

Mounting Holes

998-19374

SH0400

TH-NSP

1

SL-3.41X2.0-5.91X4.5

SH0401

TH-NSP

1

SL-3.41X2.0-5.91X4.5

Heatsink Mounting Bosses

860-01043

SH0410

5.0OD1.85ID-1.5H-SM1

1

SH0411

5.0OD1.85ID-1.5H-SM1

1

SH0412

5.0OD1.85ID-1.5H-SM1

1

SOC/NAND Shield Fence

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

SHIELD FRAME,GIBRALTAR,X1419

TABLE_5_HEAD

BOM OPTIONCRITICAL

TABLE_5_ITEM

SHLD_FNC_SOCSHLD4 CRITICAL1806-19074

C

B

998-11114998-11113 860-00974

SH0402

4.6R1.7-NSP 4.6X5.2R1.7X2.3-NSP

1

SH0403

1

SH0413

5.0OD1.85ID-1.5H-SM1

1

Antenna Cowling Bosses

SH0420

5.25X2.8R-1.4ID-1.81H-SM

1

B

A

8

67

A

PAGE TITLE

PD Parts

DRAWING NUMBER

051-05232

Apple Inc.

REVISION

2.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=MECHANICALS

35 4

IV ALL RIGHTS RESERVED

2

BRANCH

proto4b

PAGE

4 OF 152

SHEET

4 OF 86

1

SIZE

D

D

www.laptoprepairsecrets.com

678

3 245

1

CRITICAL

OMIT_TABLE

D

C

eDP Port Assignment:

Internal panel

69

69

69

69

69

69

69

69

69

69

23 16 5

23 16 5

23 16 5

23 16 5

18

18 5

69 5

69 5

78 68 5

78 69

OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

BI
BI

OUT
IN

OUT
IN

IN
IN
IN

OUT
OUT
OUT

U0500

ICL_YN

BGA

SYM 1 OF 15

DP_INT_ML_C_P<3>
DP_INT_ML_C_N<3>
DP_INT_ML_C_P<2>
DP_INT_ML_C_N<2>
DP_INT_ML_C_P<1>
DP_INT_ML_C_N<1>
DP_INT_ML_C_P<0>
DP_INT_ML_C_N<0>

DP_INT_AUXCH_C_P USBC_HSX_AUXCH_C_P
DP_INT_AUXCH_C_N

XDP_LSX_TBTA_R2P
XDP_LSX_TBTA_P2R

XDP_LSX_TBTB_R2P
XDP_LSX_TBTB_P2R

XDP_LSX_TBTC_R2P

16

NC_LSX_TBTC_P2R
PCH_BT_AUDIO_SYNC

PCH_WLAN_AUDIO_SYNC
DP_INT_HPD

EDP_PANEL_PWR_EN
EDP_BKLT_EN
EDP_BKLT_PWM

NC_CPU_RSVD_H40
NC_DISP_UTILS

DISP_RCOMP

AF2
AE1
AH2
AG1
AF4
AE3
AG3
AH4

AJ3
AJ1

CN17
CR17

CM18
CL17

CL19
CN19

CP36
CN35
CL35

CR35
CN27
CR29

H40
BU1
AD2

DDIA_TXP_3
DDIA_TXN_3
DDIA_TXP_2
DDIA_TXN_2
DDIA_TXP_1
DDIA_TXN_1
DDIA_TXP_0
DDIA_TXN_0

DDIA_AUX_P
DDIA_AUX_N

GPP_E13/DDPA_CTRLCLK
GPP_E14/DDPA_CTRLDATA

GPP_E15/DPPB_CTRLCLK/TBT_LSX1_TXD
GPP_E16/DPPB_CTRLDATA/TBT_LSX1_RXD

GPP_E17/DPPC_CTRLCLK
GPP_E18/DPPC_CTRLDATA

GPP_A15/DDSP_HPDC/TIME_SYNC0
GPP_A16/DDSP_HPDB/TIME_SYNC1
GPP_A17/DDSP_HPDA

EDP_VDDEN
EDP_BKLTEN
EDP_BKLTCTL

RSVD_48
DISP_UTILS
DISP_RCOMP

TCP0_TX_P1
TCP0_TX_N1
TCP0_TX_P0

TCP0_TX_N0
TCP0_TXRX_P1
TCP0_TXRX_N1
TCP0_TXRX_P0
TCP0_TXRX_N0

TCP0_AUX_P

TCP0_AUX_N

TCP1_TX_P1

TCP1_TX_N1

TCP1_TX_P0

TCP1_TX_N0
TCP1_TXRX_P1
TCP1_TXRX_N1
TCP1_TXRX_P0
TCP1_TXRX_N0

TCP1_AUX_P

TCP1_AUX_N

TC_RCOMP_P

TC_RCOMP_N

BD4
BC3
BE3
BF4
BJ3
BH4
BM4
BN3

BK4
BL3

AM4
AL3
AP4
AN3
AT4
AU3
AY4
BA3

AV4
AW3

AW1
BA1

USBC_HSX_R2D_C_P<2>
USBC_HSX_R2D_C_N<2>
USBC_HSX_R2D_C_P<1>
USBC_HSX_R2D_C_N<1>
USBC_HSX_D2R_C_P<2>
USBC_HSX_D2R_C_N<2>
USBC_HSX_D2R_C_P<1>
USBC_HSX_D2R_C_N<1>

USBC_HSX_AUXCH_C_N

USBC_HST_R2D_C_P<2>
USBC_HST_R2D_C_N<2>
USBC_HST_R2D_C_P<1>
USBC_HST_R2D_C_N<1>
USBC_HST_D2R_C_P<2>
USBC_HST_D2R_C_N<2>
USBC_HST_D2R_C_P<1>
USBC_HST_D2R_C_N<1>

USBC_HST_AUXCH_C_P
USBC_HST_AUXCH_C_N

TC_RCOMP_P
TC_RCOMP_N

OUT
OUT
OUT
OUT

BI
BI
BI
BI

BI
BI

OUT
OUT
OUT
OUT

BI
BI
BI
BI

BI
BI

R0530

150

1%

1/20W

MF

201

Type-C Port Assignments:

21

21

21

21

21

21

21

21

23

23

22

22

22

22

22

22

22

22

23

23

21

USBC Sink 0

USBC Sink 1

C

B

R0531

150

1%

1/20W

MF

201

1

2

B

A

NOSTUFF

NOSTUFF

NOSTUFF
NOSTUFF
NOSTUFF

8

R0550
R0551
R0552
R0553
R0554
R0555
R0556
R0557

PP3V3_S5

100K
100K
100K
100K

10K

1K

10K

1K

21
21

21
21
21
21
21
21

13 14 17 18 42 74

5% 201MF

1/20W

MF 2015% 1/20W

1/20W

1/20W 201MF5%

5% 1/20W MF 201

MF 2015%

201MF1/20W5%

201MF1/20W5%

2015% 1/20W MF

EDP_BKLT_EN
EDP_PANEL_PWR_EN
DP_INT_HPD
PCH_WLAN_AUDIO_SYNC
XDP_LSX_TBTA_R2P
XDP_LSX_TBTA_P2R
XDP_LSX_TBTB_R2P
XDP_LSX_TBTB_P2R

78 68 5

69 5

69 5

18 5

23 16 5

23 16 5

23 16 5

23 16 5

67

SYNC_MASTER=MASTER SYNC_DATE=06/08/2018

PAGE TITLE

A

CPU GFX

DRAWING NUMBER

051-05232

Apple Inc.

REVISION

2.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=CPU & CHIPSET

35 4

IV ALL RIGHTS RESERVED

2

BRANCH

proto4b

PAGE

5 OF 152

SHEET

5 OF 86

1

SIZE

D

678

www.laptoprepairsecrets.com

64 57 39 14 8

PP1V05_VCCST_OUT

CRITICAL

OMIT_TABLE

3 245

1

D

17 16 11 8

PP1V05_VCCSTG_OUT

R0610

39

BI

PLACE_NEAR=U0500.CF56:2.54MM

CPU_PROCHOT_L

R0620

49.9

1

1%

1/20W

MF

201

2

PLACE_NEAR=U0500.CM2:2.54MM

1

1K

5%

1/20W

MF

201

2

R0621

49.9

1%

1/20W

MF

201

R0611

510

2 1

5%

1/20W

MF

201

200

1%

1/20W

MF

201

1

2

1

2

R0622

PLACE_NEAR=U0500.CG55:2.54MM

64

39

64 39

16

32

18

30 29 28 18

76

29 6

OUT
BI

OUT

OUT

BI
BI

OUT

BI

1%

1/20W

MF

201

1

2

R0613

49.9

CPU_CATERR_L
CPU_PECI
CPU_PROCHOT_R_L
PM_THRMTRIP_L

NC_PCH_GPP_A19
CPU_POPI_RCOMP

PCH_OPI_RCOMP
SD3_RCOMP
DBG_PMODE
SOC_PERST_L

PCH_WLAN_PERST_L
NC_HDMI_RESET_L
PCH_BT_ROM_BOOT_L

1

R0612

1K

5%
1/20W
MF
201

2

E41
B26
B30
C41

CL37

CF56

CM2

CG55

CN11

CH48
CN45
CR45
CP44

U0500

ICL_YN

SYM 4 OF 15
CATERR*
PECI
PROCHOT*
THRMTRIP*

GPP_A19/PCHHOT*

PROC_POPIRCOMP
PCH_OPIRCOMP

SD3_RCOMP

DBG_PMODE

GPP_B4/CPU_GP3
GPP_B3/CPU_GP2
GPP_A11/CPU_GP1
GPP_A10/CPU_GP0

BGA

PROC_TCK
PROC_TDI
PROC_TDO
PROC_TMS

PROC_TRST*

PCH_TRST*

PCH_TCK
PCH_TDI
PCH_TDO
PCH_TMS

PCH_JTAGX

PROC_PRDY*
PROC_PREQ*

D28
C29
A27
C27
A29

CM10
CM12
CM14
CL13
CN13
CL11

G35
G37

XDP_CPUPCH_TCK
XDP_CPUPCH_TDI
XDP_CPUPCH_TDO
XDP_CPUPCH_TMS
XDP_CPUPCH_TRST_L

XDP_CPUPCH_TRST_L
TP_XDP_PCH_TCK
XDP_CPUPCH_TDI
XDP_CPUPCH_TDO
XDP_CPUPCH_TMS
XDP_CPUPCH_TCK

XDP_PRDY_L
XDP_PREQ_L

IN
IN

OUT

IN
IN

IN
IN
IN

OUT

IN

BI

OUT

IN

D

16

16

16

16

16

16

16

16

16

16

16

16

16

C

B

PP1V8_PRIM_PCH

R0650

100K

13 15 75

21

CFG(4) EMBEDDED DISPLAY PORT:
0: ENABLED
1: DISABLED

R0640

49.9

1/20W

1/20W

1%
MF

201

C

201MF5%

CPU_CFG<15>
CPU_CFG<14>
CPU_CFG<13>
CPU_CFG<12>
CPU_CFG<11>
CPU_CFG<10>
CPU_CFG<9>
CPU_CFG<8>
CPU_CFG<7>
CPU_CFG<6>
CPU_CFG<5>
CPU_CFG<4>
CPU_CFG<3>
CPU_CFG<2>
CPU_CFG<1>
CPU_CFG<0>

CPU_CFG<19>
CPU_CFG<18>

CPU_CFG<17>
CPU_CFG<16>

16

BI

R0634

1K

5%

1/20W

MF

201

16

BI

16

BI

17 16

17 16

17 16

17 16

17 16

1

17 16

17 16

2

16

16

16

16

16

16

16

16

16

16

BI
BI
BI
BI
BI
BI
BI
BI
BI

BI
BI
BI
BI

BI
BI

BI
BI

CPU_CFG_RCOMP

PCH_BT_ROM_BOOT_L

16

BI

16

1

16

16

BI
BI
BI

XDP_BPM_L<3>
XDP_BPM_L<2>
XDP_BPM_L<1>
XDP_BPM_L<0>

NC_CPU_RSVD_BN9

2

NC_CPU_RSVD_BM8
TP_CPU_RSVD_AW7

29 6

CRITICAL

OMIT_TABLE

U0500

ICL_YN

BGA

SYM 15 OF 15

A35
B34
C33
D36
F34
G33
C35
E35
C37
E37
A37
C39
G39
D40
B38
A39

E33
F32

F38
E39

A33

E31
C31
A31
D32

BN9
BM8
AW7

CFG_15
CFG_14
CFG_13
CFG_12
CFG_11
CFG_10
CFG_9
CFG_8
CFG_7
CFG_6
CFG_5
CFG_4
CFG_3
CFG_2
CFG_1
CFG_0

CFG_19
CFG_18

CFG_17
CFG_16

CFG_RCOMP RSVD_TP_18

BPM_3*
BPM_2*
BPM_1*
BPM_0*

RSVD_1
RSVD_2
RSVD_TP_1

(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)

(IPU)
(IPU)

(IPU)
(IPU)

RSVD_TP_7
RSVD_TP_8

RSVD_TP_9

RSVD_TP_10

RSVD_TP_11
RSVD_TP_12

RSVD_9

RSVD_10

RSVD_TP_13
RSVD_TP_14

RSVD_11
RSVD_12

TP_1
TP_2

RSVD_TP_15

RSVD_TP_16
RSVD_TP_17

TP_3
TP_4

VSS_268

RSVD_13

B56
A55

BV44
BT44

BP10
BR11

G29
F28

CH14
CJ15

CN1
CR1

BP44
CJ11

U7

CH12
CG11

CJ13

CB44
CD44
BY44

E29

TP_CPU_RSVD_B56
TP_CPU_RSVD_A55

TP_CPU_RSVD_BV44
TP_CPU_RSVD_BT44

TP_CPU_RSVD_BP10
TP_CPU_RSVD_BR11

NC_CPU_RSVD_G29
NC_CPU_RSVD_F28

TP_CPU_RSVD_CH14
TP_CPU_RSVD_CJ15

NC_CPU_RSVD_CN1
NC_CPU_RSVD_CR1

TP_CPU_BP44
TP_CPU_CJ11

TP_CPU_RSVD_U7
TP_CPU_RSVD_CH12

TP_CPU_RSVD_CG11
TP_CPU_RSVD_CJ13
TP_CPU_CB44

TP_CPU_CD44
GND

NC_CPU_RSVD_E29

17

NC_CPU_RSVD_AN7
NC_CPU_RSVD_BD46
NC_CPU_RSVD_Y6
NC_CPU_RSVD_J39
NC_CPU_RSVD_BF46
NC_CPU_RSVD_J31
NC_CPU_RSVD_AJ7
NC_CPU_RSVD_J35

NC_CPU_RSVD_F30
NC_CPU_RSVD_BM44
NC_CPU_RSVD_H32
NC_CPU_RSVD_AL7
NC_CPU_RSVD_H30

NC_CPU_RSVD_CA45
NC_CPU_RSVD_BT46
NC_CPU_RSVD_BR45
NC_CPU_RSVD_BP46
NC_CPU_RSVD_BN45
NC_CPU_RSVD_BC55
NC_CPU_RSVD_N49

AN7

BD46

Y6

J39

BF46

J31
AJ7
J35

F30

BM44

H32
AL7
H30

CA45
BT46
BR45
BP46
BN45
BC55

N49

RSVD_17
RSVD_16
RSVD_15
RSVD_14
RSVD_18
RSVD_19
RSVD_20
RSVD_21

RSVD_22
RSVD_23
RSVD_24
RSVD_25
RSVD_26

RSVD_27
RSVD_28
RSVD_29
RSVD_30
RSVD_31
RSVD_32
RSVD_33

U0500

ICL_YN

BGA

SYM 14 OF 15

CRITICAL

OMIT_TABLE

RSVD_39
RSVD_40
RSVD_41
RSVD_42
RSVD_43

IST_TP_0

IST_TP_1
IST_TRIG_0
IST_TRIG_1

PCH_IST_TP_0
PCH_IST_TP_1

RSVD_44
RSVD_45

RSVD_46
RSVD_34
RSVD_35
RSVD_36
RSVD_37
RSVD_38

BL45
CH16
CF48
CG49
CF50

BG7
BE7
BL7
BJ7

CM56
CP54
CB48
CE51

CH30
CJ37
CJ39
CJ43
CJ45
CF46

NC_CPU_RSVD_BL45
NC_CPU_RSVD_CH16
NC_CPU_RSVD_CF48
NC_CPU_RSVD_CG49
NC_CPU_RSVD_CF50

TP_IST_0
TP_IST_1
TP_IST_TRIG_0
TP_IST_TRIG_1

TP_PCH_IST_0
TP_PCH_IST_1
NC_CPU_RSVD_CB48
NC_CPU_RSVD_CE51

NC_CPU_RSVD_CH30
NC_CPU_RSVD_CJ37
NC_CPU_RSVD_CJ39
NC_CPU_RSVD_CJ43
NC_CPU_RSVD_CJ45
NC_CPU_RSVD_CF46

DCDC IFDIM Support

TOP SIDE ONLY

R0660
R0661
R0662
R0663

R0664
R0665

1/20W 201

5%
5%1/20W MF 201

21

100K

MF

21

100K

21

100K

21

100K

21

100K

MF

21

100K

2015%1/20W
2015% MF1/20W
2015% MF1/20W
2015% MF1/20W

These resistors must be
on the top side and not
covered by glue.

B

NOSTUFF
NOSTUFF
NOSTUFF
NOSTUFF

NOSTUFF
NOSTUFF

TP_CPU_RSVD_AR7
TP_CPU_RSVD_AP6
TP_CPU_RSVD_AT6
TP_CPU_RSVD_AU7

TP_CPU_RSVD_AV6

AR7
AP6
AT6
AU7

AV6

RSVD_TP_2
RSVD_TP_3
RSVD_TP_4
RSVD_TP_5

RSVD_TP_6

A

BK46
BH46

67

CP2
CR3

AE7
AG7

CM4

RSVD_3
RSVD_4

RSVD_5
RSVD_6
RSVD_7
RSVD_8

SKTOCC*

NC_CPU_RSVD_CP2
NC_CPU_RSVD_CR3

NC_CPU_RSVD_AE7
NC_CPU_RSVD_AG7
NC_CPU_RSVD_BK46
NC_CPU_RSVD_BH46

NC_SKTOCC_L

8

SYNC_DATE=06/08/2018SYNC_MASTER=CPU_CARD_ICL_Y

PAGE TITLE

A

CPU Misc/JTAG/CFG/RSVD

DRAWING NUMBER

051-05232

Apple Inc.

REVISION

2.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=CPU & CHIPSET

35 4

IV ALL RIGHTS RESERVED

2

BRANCH

proto4b

PAGE

6 OF 152

SHEET

6 OF 86

1

SIZE

D

678

www.laptoprepairsecrets.com

3 245

1

D

C

B

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

MEM_A_DQ_0<7>
MEM_A_DQ_0<6>
MEM_A_DQ_0<5>
MEM_A_DQ_0<4>
MEM_A_DQ_0<3>
MEM_A_DQ_0<2>
MEM_A_DQ_0<1>
MEM_A_DQ_0<0>
MEM_A_DQ_1<7>
MEM_A_DQ_1<6>
MEM_A_DQ_1<5>
MEM_A_DQ_1<4>
MEM_A_DQ_1<3>
MEM_A_DQ_1<2>
MEM_A_DQ_1<1>
MEM_A_DQ_1<0>
MEM_A_DQ_2<7>
MEM_A_DQ_2<6>
MEM_A_DQ_2<5>
MEM_A_DQ_2<4>
MEM_A_DQ_2<3>
MEM_A_DQ_2<2>
MEM_A_DQ_2<1>
MEM_A_DQ_2<0>
MEM_A_DQ_3<7>
MEM_A_DQ_3<6>
MEM_A_DQ_3<5>
MEM_A_DQ_3<4>
MEM_A_DQ_3<3>
MEM_A_DQ_3<2>
MEM_A_DQ_3<1>
MEM_A_DQ_3<0>
MEM_B_DQ_0<7>
MEM_B_DQ_0<6>
MEM_B_DQ_0<5>
MEM_B_DQ_0<4>
MEM_B_DQ_0<3>
MEM_B_DQ_0<2>
MEM_B_DQ_0<1>
MEM_B_DQ_0<0>
MEM_B_DQ_1<7>
MEM_B_DQ_1<6>
MEM_B_DQ_1<5>
MEM_B_DQ_1<4>
MEM_B_DQ_1<3>
MEM_B_DQ_1<2>
MEM_B_DQ_1<1>
MEM_B_DQ_1<0>
MEM_B_DQ_2<7>
MEM_B_DQ_2<6>
MEM_B_DQ_2<5>
MEM_B_DQ_2<4>
MEM_B_DQ_2<3>
MEM_B_DQ_2<2>
MEM_B_DQ_2<1>
MEM_B_DQ_2<0>
MEM_B_DQ_3<7>
MEM_B_DQ_3<6>
MEM_B_DQ_3<5>
MEM_B_DQ_3<4>
MEM_B_DQ_3<3>
MEM_B_DQ_3<2>
MEM_B_DQ_3<1>
MEM_B_DQ_3<0>

CPU_DDR_RCOMP<2>
CPU_DDR_RCOMP<1>
CPU_DDR_RCOMP<0>

BT56
BU55
BU53
BW53
BT54
BY54
BW55
BY56
BY50
BY48
BW51
BU51
BW49
BT50
BU49
BT48
BL55
BL53
BM56
BP56
BM54
BP54
BR55
BR53
BR51
BR49
BP50
BM48
BP48
BL51
BM50
BL49
AU53
AU55
AV56
AY56
AV54
BA53
BA55
AY54
BA51
BA49
AY48
AU49
AY50
AU51
AV48
AV50
AM54
AM56
AN55
AR55
AN53
AR53
AT56
AT54
AT50
AT48
AR49
AN51
AR51
AM48
AN49
AM50

B44
A43

CD56

DDRA_DQ0_7
DDRA_DQ0_6
DDRA_DQ0_5
DDRA_DQ0_4
DDRA_DQ0_3
DDRA_DQ0_2
DDRA_DQ0_1
DDRA_DQ0_0
DDRA_DQ1_7
DDRA_DQ1_6
DDRA_DQ1_5
DDRA_DQ1_4
DDRA_DQ1_3
DDRA_DQ1_2
DDRA_DQ1_1
DDRA_DQ1_0
DDRA_DQ2_7
DDRA_DQ2_6
DDRA_DQ2_5
DDRA_DQ2_4
DDRA_DQ2_3
DDRA_DQ2_2
DDRA_DQ2_1
DDRA_DQ2_0
DDRA_DQ3_7
DDRA_DQ3_6
DDRA_DQ3_5
DDRA_DQ3_4
DDRA_DQ3_3
DDRA_DQ3_2
DDRA_DQ3_1
DDRA_DQ3_0
DDRB_DQ0_7
DDRB_DQ0_6
DDRB_DQ0_5
DDRB_DQ0_4
DDRB_DQ0_3
DDRB_DQ0_2
DDRB_DQ0_1
DDRB_DQ0_0
DDRB_DQ1_7
DDRB_DQ1_6
DDRB_DQ1_5
DDRB_DQ1_4
DDRB_DQ1_3
DDRB_DQ1_2
DDRB_DQ1_1
DDRB_DQ1_0
DDRB_DQ2_7
DDRB_DQ2_6
DDRB_DQ2_5
DDRB_DQ2_4
DDRB_DQ2_3
DDRB_DQ2_2
DDRB_DQ2_1
DDRB_DQ2_0
DDRB_DQ3_7
DDRB_DQ3_6
DDRB_DQ3_5
DDRB_DQ3_4
DDRB_DQ3_3
DDRB_DQ3_2
DDRB_DQ3_1
DDRB_DQ3_0

DDR_RCOMP_2
DDR_RCOMP_1
DDR_RCOMP_0

U0500

ICL_YN

BGA

SYM 2 OF 15

CRITICAL

OMIT_TABLE

DDRA_CLK_P
DDRA_CLK_N
DDRB_CLK_P
DDRB_CLK_N

DDRA_CKE0
DDRA_CKE1
DDRB_CKE0
DDRB_CKE1

DDRA_CS_0
DDRA_CS_1
DDRB_CS_0
DDRB_CS_1

DDRA_CA5
DDRA_CA4
DDRA_CA3
DDRA_CA2
DDRA_CA1
DDRA_CA0

DDRB_CA5
DDRB_CA4
DDRB_CA3
DDRB_CA2
DDRB_CA1
DDRB_CA0

DDRA_DQSP_3
DDRA_DQSN_3
DDRA_DQSP_2
DDRA_DQSN_2
DDRA_DQSP_1
DDRA_DQSN_1
DDRA_DQSP_0
DDRA_DQSN_0
DDRB_DQSP_3
DDRB_DQSN_3
DDRB_DQSP_2
DDRB_DQSN_2
DDRB_DQSP_1
DDRB_DQSN_1
DDRB_DQSP_0
DDRB_DQSN_0

DRAM_RESET*

BD54
BC53
BD50
BE51

BH54
BJ55
BE49
BF50

BF54
BE55
BC49
BD48

BG53
BE53
BC51
BG55
BJ53
BJ51

BH50
BJ49
BH48
BG51
BF48
BG49

BN49
BN51
BN55
BN53
BV48
BV50
BV56
BV54
AP50
AP48
AP56
AP54
AW49
AW51
AW55
AW53

CB52

MEM_A_CLK_P
MEM_A_CLK_N
MEM_B_CLK_P
MEM_B_CLK_N

MEM_A_CKE<0>
MEM_A_CKE<1>
MEM_B_CKE<0>
MEM_B_CKE<1>

MEM_A_CS_L<0>
MEM_A_CS_L<1>
MEM_B_CS_L<0>
MEM_B_CS_L<1>

MEM_A_CA<5>
MEM_A_CA<4>
MEM_A_CA<3>
MEM_A_CA<2>
MEM_A_CA<1>
MEM_A_CA<0>

MEM_B_CA<5>
MEM_B_CA<4>
MEM_B_CA<3>
MEM_B_CA<2>
MEM_B_CA<1>
MEM_B_CA<0>

MEM_A_DQS_P<3>
MEM_A_DQS_N<3>
MEM_A_DQS_P<2>
MEM_A_DQS_N<2>
MEM_A_DQS_P<1>
MEM_A_DQS_N<1>
MEM_A_DQS_P<0>
MEM_A_DQS_N<0>
MEM_B_DQS_P<3>
MEM_B_DQS_N<3>
MEM_B_DQS_P<2>
MEM_B_DQS_N<2>
MEM_B_DQS_P<1>
MEM_B_DQS_N<1>
MEM_B_DQS_P<0>
MEM_B_DQS_N<0>

PP1V1_S3

1

R0740

470

1%
1/20W
MF
201

2

MEM_RESET_R_L

77

OUT

77

OUT

77

OUT

77

OUT

77

OUT

77

OUT

77

OUT

77

OUT

77

OUT

77

OUT

77

OUT

77

OUT

77

OUT

77

OUT

77

OUT

77

OUT

77

OUT

77

OUT

77

OUT

77

OUT

77

OUT

77

OUT

77

OUT

77

OUT

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

75

R0741

0

5%

1/20W

MF

0201

21

MEM_RESET_L

NOSTUFF

1

C0741

0.1UF

10%
16V

2

X5R-CERM
0201

OUT

CRITICAL

OMIT_TABLE

U0500

ICL_YN

BGA

SYM 3 OF 15

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

20 19

77

77

77

77

77

77

77

77

77

77

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

MEM_C_DQ_0<7>
MEM_C_DQ_0<6>
MEM_C_DQ_0<5>
MEM_C_DQ_0<4>
MEM_C_DQ_0<3>
MEM_C_DQ_0<2>
MEM_C_DQ_0<1>
MEM_C_DQ_0<0>
MEM_C_DQ_1<7>

MEM_C_DQ_1<5>
MEM_C_DQ_1<4>
MEM_C_DQ_1<3>
MEM_C_DQ_1<2>
MEM_C_DQ_1<1>
MEM_C_DQ_1<0>
MEM_C_DQ_2<7>
MEM_C_DQ_2<6>
MEM_C_DQ_2<5>
MEM_C_DQ_2<4>
MEM_C_DQ_2<3>
MEM_C_DQ_2<2>
MEM_C_DQ_2<1>
MEM_C_DQ_2<0>
MEM_C_DQ_3<7>
MEM_C_DQ_3<6>
MEM_C_DQ_3<5>
MEM_C_DQ_3<4>
MEM_C_DQ_3<3>
MEM_C_DQ_3<2>
MEM_C_DQ_3<1>
MEM_C_DQ_3<0>
MEM_D_DQ_0<7>
MEM_D_DQ_0<6>
MEM_D_DQ_0<5>
MEM_D_DQ_0<4>
MEM_D_DQ_0<3>
MEM_D_DQ_0<2>
MEM_D_DQ_0<1>
MEM_D_DQ_0<0>
MEM_D_DQ_1<7>
MEM_D_DQ_1<6>
MEM_D_DQ_1<5>
MEM_D_DQ_1<4>
MEM_D_DQ_1<3>
MEM_D_DQ_1<2>
MEM_D_DQ_1<1>
MEM_D_DQ_1<0>
MEM_D_DQ_2<7>
MEM_D_DQ_2<6>
MEM_D_DQ_2<5>
MEM_D_DQ_2<4>
MEM_D_DQ_2<3>
MEM_D_DQ_2<2>
MEM_D_DQ_2<1>
MEM_D_DQ_2<0>
MEM_D_DQ_3<7>
MEM_D_DQ_3<6>
MEM_D_DQ_3<5>
MEM_D_DQ_3<4>
MEM_D_DQ_3<3>
MEM_D_DQ_3<2>
MEM_D_DQ_3<1>
MEM_D_DQ_3<0>

AF54
AF56
AG55
AJ53
AG53
AK56
AJ55
AK54
AK48
AK50
AJ49
AG49
AJ51
AF48
AG51
AF50
AA53
AA55
AB54
AD54
AB56
AE55
AD56
AE53
AE51
AE49
AD50
AB50
AD48
AA49
AB48
AA51

H54
G53
G55
K54
H56
L55
L53
K56
L51
L49
K50
H48
K48
G49
H50
G51
B52
C51
C53
E53
E51
F56
F54
E55
F48
E49
E47
C47
F46
B48
C49
B46

DDRC_DQ0_7
DDRC_DQ0_6
DDRC_DQ0_5
DDRC_DQ0_4
DDRC_DQ0_3
DDRC_DQ0_2
DDRC_DQ0_1
DDRC_DQ0_0
DDRC_DQ1_7
DDRC_DQ1_6
DDRC_DQ1_5
DDRC_DQ1_4
DDRC_DQ1_3
DDRC_DQ1_2
DDRC_DQ1_1
DDRC_DQ1_0
DDRC_DQ2_7
DDRC_DQ2_6
DDRC_DQ2_5
DDRC_DQ2_4
DDRC_DQ2_3
DDRC_DQ2_2
DDRC_DQ2_1
DDRC_DQ2_0
DDRC_DQ3_7
DDRC_DQ3_6
DDRC_DQ3_5
DDRC_DQ3_4
DDRC_DQ3_3
DDRC_DQ3_2
DDRC_DQ3_1
DDRC_DQ3_0
DDRD_DQ0_7
DDRD_DQ0_6
DDRD_DQ0_5
DDRD_DQ0_4
DDRD_DQ0_3
DDRD_DQ0_2
DDRD_DQ0_1
DDRD_DQ0_0
DDRD_DQ1_7
DDRD_DQ1_6
DDRD_DQ1_5
DDRD_DQ1_4
DDRD_DQ1_3
DDRD_DQ1_2
DDRD_DQ1_1
DDRD_DQ1_0
DDRD_DQ2_7
DDRD_DQ2_6
DDRD_DQ2_5
DDRD_DQ2_4
DDRD_DQ2_3
DDRD_DQ2_2
DDRD_DQ2_1
DDRD_DQ2_0
DDRD_DQ3_7
DDRD_DQ3_6
DDRD_DQ3_5
DDRD_DQ3_4
DDRD_DQ3_3
DDRD_DQ3_2
DDRD_DQ3_1
DDRD_DQ3_0

DDRC_CLK_P
DDRC_CLK_N
DDRD_CLK_P
DDRD_CLK_N

DDRC_CKE0
DDRC_CKE1
DDRD_CKE0
DDRD_CKE1

DDRC_CS_0
DDRC_CS_1
DDRD_CS_0
DDRD_CS_1

DDRC_CA5
DDRC_CA4
DDRC_CA3
DDRC_CA2
DDRC_CA1
DDRC_CA0

DDRD_CA5
DDRD_CA4
DDRD_CA3
DDRD_CA2
DDRD_CA1
DDRD_CA0

DDRC_DQSP_3
DDRC_DQSN_3
DDRC_DQSP_2
DDRC_DQSN_2
DDRC_DQSP_1
DDRC_DQSN_1
DDRC_DQSP_0
DDRC_DQSN_0
DDRD_DQSP_3
DDRD_DQSN_3
DDRD_DQSP_2
DDRD_DQSN_2
DDRD_DQSP_1
DDRD_DQSN_1
DDRD_DQSP_0
DDRD_DQSN_0

N53
P54
U51
U49

R55
T54
R49
T48

N55
R51
P48
T50

U53
R53
W55
U55
V54
W53

V50
W49
W51
V48
N51
P50

AC49
AC51
AC53
AC55
AH48
AH50
AH56
AH54
D48
D46
D52
D54
J49
J51
J53
J55

MEM_C_CLK_P
MEM_C_CLK_N
MEM_D_CLK_P
MEM_D_CLK_N

MEM_C_CKE<0>
MEM_C_CKE<1>
MEM_D_CKE<0>
MEM_D_CKE<1>

MEM_C_CS_L<0>MEM_C_DQ_1<6>
MEM_C_CS_L<1>
MEM_D_CS_L<0>
MEM_D_CS_L<1>

MEM_C_CA<5>
MEM_C_CA<4>
MEM_C_CA<3>
MEM_C_CA<2>
MEM_C_CA<1>
MEM_C_CA<0>

MEM_D_CA<5>
MEM_D_CA<4>
MEM_D_CA<3>
MEM_D_CA<2>
MEM_D_CA<1>
MEM_D_CA<0>

MEM_C_DQS_P<3>
MEM_C_DQS_N<3>
MEM_C_DQS_P<2>
MEM_C_DQS_N<2>
MEM_C_DQS_P<1>
MEM_C_DQS_N<1>
MEM_C_DQS_P<0>
MEM_C_DQS_N<0>
MEM_D_DQS_P<3>
MEM_D_DQS_N<3>
MEM_D_DQS_P<2>
MEM_D_DQS_N<2>
MEM_D_DQS_P<1>
MEM_D_DQS_N<1>
MEM_D_DQS_P<0>
MEM_D_DQS_N<0>

OUT
OUT
OUT
OUT

OUT
OUT
OUT
OUT

OUT
OUT
OUT
OUT

OUT
OUT
OUT
OUT
OUT
OUT

OUT
OUT
OUT
OUT
OUT
OUT

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

D

C

B

A

1

R0752

100

1%
1/20W
MF
201

2

PLACE_NEAR=U0500.B44:12.7mm

1

R0751

100

1%
1/20W
MF
201

2

PLACE_NEAR=U0500.CD56:12.7mm

PLACE_NEAR=U0500.A43:12.7mm

1

R0750

100

1%
1/20W
MF
201

2

BOM_COST_GROUP=CPU & CHIPSET

PAGE TITLE

CPU LPDDR4 Interface

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=06/08/2018SYNC_MASTER=CPU_CARD_ICL_Y

DRAWING NUMBER

051-05232

REVISION

2.0.0

BRANCH

proto4b

PAGE

7 OF 152

SHEET

7 OF 86

A

SIZE

D

8

67

35 4

2

1

678

www.laptoprepairsecrets.com

3 245

1

D

C

B

A

CNL CPU-Y current estimates from Cannon Lake Processor EDS Vol 1, doc #566214, v0.7.
IccMax totals include all pins of same name. Some pin groups are split, IccMax is only specified once.

64 57 39 14 8 6

PP1V05_VCCST_OUT

NOSTUFF

R0802

100

1%

1/20W

MF

201

1

2

1

R0801

43

1%
1/20W
MF
201

2

1

R0800

56

1%
1/20W
MF
201

2

R0810

0

57

57

57

IN

OUT

BI

CPU_VIDALERT_L

CPU_VIDSCLK

CPU_VIDSOUT

R0800.2:
R0801.2:
R0802.2:

PLACE_NEAR=U0500.F42:12.7mm
PLACE_NEAR=U0500.H42:12.7mm
PLACE_NEAR=U0500.G41:12.7mm

R0811

0

21

5%

1/20W

MF

0201

???MA MAX
???MA MAX

1/20W

0201

R0812

1/20W

0201

21
5%
MF

0

21
5%
MF

66 39 17 11

17 16 11 8 6

64 57 39 14 8 6

78

66 11

PP1V1_S3

8 11 75

???A MAX

PP1V05_S0_CPU_VCCST
PP1V05_S0_VCCSTG
PP1V05_VCCSTG_OUT
PP1V05_VCCST_OUT

PPVCC_S0_CPU

8 11 46 75

??A MAX

CPU_VIDALERT_R_L
CPU_VIDSCLK_R
CPU_VIDSOUT_R

VOLTAGE=1.05V

VOLTAGE=1.05V

CRITICAL

OMIT_TABLE

U0500

ICL_YN

BGA

SYM 9 OF 15

A13
A15
A19

AA1
AA3
AA5
AA7
AB2
AB4
AB6
AC5
AC7
AD6
AF6
AH6
AK6
AM6
B10
B12
B16
B18

C13
C15
C19

D10
D12
D16
D18

E11
E13
E15
E17
E19

F10
F12
F16

F42 B20
H42
G41

A7
A9

B4
B6
B8

C3
C5
C7
C9

E1

E3
E5
E7
E9

VCCIN_1
VCCIN_2
VCCIN_3
VCCIN_4
VCCIN_5
VCCIN_6
VCCIN_7
VCCIN_8
VCCIN_9
VCCIN_10
VCCIN_11
VCCIN_12
VCCIN_13
VCCIN_14
VCCIN_15
VCCIN_16
VCCIN_17
VCCIN_18
VCCIN_19
VCCIN_20
VCCIN_21
VCCIN_22
VCCIN_23
VCCIN_24
VCCIN_25
VCCIN_26
VCCIN_27
VCCIN_28
VCCIN_29
VCCIN_30
VCCIN_31
VCCIN_32
VCCIN_33
VCCIN_34
VCCIN_35
VCCIN_36
VCCIN_37
VCCIN_38
VCCIN_39
VCCIN_40
VCCIN_41
VCCIN_42
VCCIN_43
VCCIN_44
VCCIN_45
VCCIN_46
VCCIN_47
VCCIN_48
VCCIN_49
VCCIN_50

VIDALERT*
VIDSCK
VIDSOUT

VCCIN_51
VCCIN_52
VCCIN_53
VCCIN_54
VCCIN_55
VCCIN_56
VCCIN_57
VCCIN_58
VCCIN_59
VCCIN_60
VCCIN_61
VCCIN_62
VCCIN_63
VCCIN_64
VCCIN_65
VCCIN_66
VCCIN_67
VCCIN_68
VCCIN_69
VCCIN_70
VCCIN_71
VCCIN_72
VCCIN_73
VCCIN_74
VCCIN_75
VCCIN_76
VCCIN_77
VCCIN_78
VCCIN_79
VCCIN_80
VCCIN_81
VCCIN_82
VCCIN_83
VCCIN_84
VCCIN_85
VCCIN_86
VCCIN_87
VCCIN_88
VCCIN_89
VCCIN_90
VCCIN_91
VCCIN_92
VCCIN_93
VCCIN_94
VCCIN_95
VCCIN_96
VCCIN_97
VCCIN_98
VCCIN_99

VCCIN_100

VCCIN_SENSE
VSSIN_SENSE

CRITICAL

OMIT_TABLE

U0500

ICL_YN

BGA

SYM 10 OF 15

A45
A49

A53
AA47
AB46
AE47
AF46
AJ47
AK46
AL55
AN47
AP46
AU47
AV46
BA47
BB46
BB56
BD56
BH56
BK56

C55

H46

J47

K46

M56

BV2

BT2

B42

A41

VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8
VDDQ_9
VDDQ_10
VDDQ_11
VDDQ_12
VDDQ_13
VDDQ_14
VDDQ_15
VDDQ_16
VDDQ_17
VDDQ_18
VDDQ_19
VDDQ_20
VDDQ_21
VDDQ_22
VDDQ_23
VDDQ_24
VDDQ_25

VCCST

VCCSTG

VCCSTG_OUT

VCCST_OUT

VDDQ_26
VDDQ_27
VDDQ_28
VDDQ_29
VDDQ_30
VDDQ_31
VDDQ_32

VCC1P8A_1
VCC1P8A_2

VCCFPGM
VCCFPGM
VCCFPGM
VCCFPGM
VCCFPGM

VCCPLL

VCCPLL_OC

RSVD_47

VCCIO_OUT

F18
F2
F4
F6
F8
G13
G15
G19
G9
H10
H12
H16
H18
H2
H4
H6
H8
J1
J13
J15
J19
J3
J5
J7
J9
K4
L1
L3
L5
L7
M2
M4
M6
P2
P4
P6
R1
R3
R5
R7
T4
U1
U3
U5
V2
V4
V6
W5
Y2
Y4

A21

N47

P46
P56
U47
V46
V56
Y56

BR1

BR3

E43
D44
G43
C43
F44

BU5

CB56

BM46

H44

PPVCC_S0_CPU

PP1P05_S0_CPU_VCCPLL

PP1V1_S0SW_CPU_VCCPLL_OC

8 11 46 75

PLACE_NEAR=U0500.B20:50.8mm

R0820

100

5%

1/20W

MF

201

CPU_VCCSENSE_P
CPU_VCCSENSE_N

PLACE_NEAR=U0500.A21:50.8mm

R0821

100

5%

1/20W

MF

201

PP1V1_S3

PP1V8_S0SW_CPU

???MA MAX

PP1V05_VCCSTG_OUT

???MA MAX

NC_CPU_RSVD_BM46

PPVCCIO_OUT

VOLTAGE=1V

8 11 75

D

C

1

2

57

OUT

57

OUT

1

2

B

66 11

17 16 11 8 6

11 9

66 11

18 17

A

D

BOM_COST_GROUP=CPU & CHIPSET

PAGE TITLE

CPU Power

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=06/08/2018SYNC_MASTER=CPU_CARD_ICL_Y

DRAWING NUMBER

051-05232

REVISION

2.0.0

BRANCH

proto4b

PAGE

8 OF 152

SHEET

8 OF 86

SIZE

8

67

35 4

2

1

678

www.laptoprepairsecrets.com

3 245

1

D

CNL PCH-Y CURRENT ESTIMATES FROM CANNON LAKE PCH-U/Y EDS VOL 1, DOC #566439, V0.7.
ICCMAX TOTALS INCLUDE ALL PINS OF SAME NAME. SOME PIN GROUPS ARE SPLIT, ICCMAX IS ONLY SPECIFIED ONCE.

NOTE: ALIASES NOT USED ON CPU SUPPLY OUTPUTS
TO AVOID ANY EXTRANEOUS CONNECTIONS.

D

CRITICAL

OMIT_TABLE

C

59

59

OUT
OUT

PPVCCIN_AUX_PCH

75

?.???A MAX

PLACE_NEAR=U0500.BP4:50.8MM

1

R0920

100

5%
1/20W
MF
201

2

PCH_VCCINSENSE_P
PCH_VCCINSENSE_N

PLACE_NEAR=U0500.BR5:50.8MM

1

R0921

100

5%
1/20W
MF
201

2

A23
A25
AY6
BA7
BB6
BC1
BC7
BD6
BE1
BF6
BG1
BH6
BJ1
BK6
BL1
BM6
BN1
BN7
BP6
BP8
BR7
BR9
C23
C25
D22
E21
E23
E25
F22
F26
G21

BP4
BR5

VCCIN_AUX_1
VCCIN_AUX_2
VCCIN_AUX_3
VCCIN_AUX_4
VCCIN_AUX_5
VCCIN_AUX_6
VCCIN_AUX_7
VCCIN_AUX_8
VCCIN_AUX_9
VCCIN_AUX_10
VCCIN_AUX_11
VCCIN_AUX_12
VCCIN_AUX_13
VCCIN_AUX_14
VCCIN_AUX_15
VCCIN_AUX_16
VCCIN_AUX_17
VCCIN_AUX_18
VCCIN_AUX_19
VCCIN_AUX_20
VCCIN_AUX_21
VCCIN_AUX_22
VCCIN_AUX_23
VCCIN_AUX_24
VCCIN_AUX_25
VCCIN_AUX_26
VCCIN_AUX_27
VCCIN_AUX_28
VCCIN_AUX_29
VCCIN_AUX_30
VCCIN_AUX_31

VCCIN_AUX_VCCSENSE
VCCIN_AUX_VSSSENSE

U0500

ICL_YN

BGA

SYM 11 OF 15

VCCPRIM_3P3_4
VCCPRIM_3P3_5
VCCPRIM_3P3_6
VCCPRIM_3P3_7
VCCPRIM_3P3_8
VCCPRIM_3P3_9

VCCPRIM_1P8_4
VCCPRIM_1P8_5
VCCPRIM_1P8_6
VCCPRIM_1P8_7
VCCPRIM_1P8_8

VCCPRIM_1P8_9
VCCPRIM_1P8_10
VCCPRIM_1P8_11
VCCPRIM_1P8_12
VCCPRIM_1P8_13
VCCPRIM_1P8_14
VCCPRIM_1P8_15
VCCPRIM_1P8_16
VCCPRIM_1P8_17
VCCPRIM_1P8_18

VCCLDOSTD_0P85

VCCA_CLKLDO_1P8_1
VCCA_CLKLDO_1P8_2

VCCDPHY_1P24

VCCPRIM_1P05_1

VCCDSW_1P05

VCC1P05_1
VCC1P05_2
VCC1P05_3

CH42
CH40
CH38
CG43
CG41
CG39

CG21
CG23
CG27
CG29
CH18
CH20
CH22
CH24
CH26
CH28
CJ17
CJ19
CJ21
CJ23
CJ25

CR41

CR19
CR21

CR37

CB46

CR47

BT4
BU3
BV4

PP3V3_S5

???MA MAX

PP1V8_PRIM_PCH

???MA MAX

PP0V85_LDOSTD

PP1V8_PCH_CLKLDO

?MA MAX

PP1V24_S5_PCH_VCCDPHY

PP1V05_PCH_VCCPRIM

PP1V05_S5_PCH_VCCDSW

PP1V05_PCH_CPU

42 59 74

12 66 75

(BYPASS ONLY)

12

12

(BYPASS ONLY)

12

74

(BYPASS ONLY)

12

74

C

B

PP1V05_PCH_EXT

46 81

66 59

66 59

BI
BI

???MA MAX

PPVNN_PCH_EXT

46 81

?.???A MAX

PP3V3_S5

74

PP1V8_PRIM_PCH

75

PP1V8_PRIM_PCH

75

?MA MAX

PP1V8_PRIM_PCH

75

?MA MAX

PCH_CORE_VID0
PCH_CORE_VID1

BYPASS INPUT

BYPASS INPUT

NC_PCH_WLAN_DEV_WAKE

WiFi will be woken up by PCIe In-Band Signal and
therefore PCH_WLAN_DEV_WAKE will not be connected

CC11 BU7
CE11

BU11
BW11
CA11

CH46
CH44
CG45

CH36
CH34
CG35

CH32
CJ33

CJ31
CG31

CN47
CK48
CN53

VCC_V1P05EXT_1P05_1
VCC_V1P05EXT_1P05_2

VCC_VNNEXT_1P05_1
VCC_VNNEXT_1P05_2
VCC_VNNEXT_1P05_3

VCCPRIM_3P3_1
VCCPRIM_3P3_2
VCCPRIM_3P3_3

VCCPRIM_1P8_1
VCCPRIM_1P8_2
VCCPRIM_1P8_3

VCCSPI_1
VCCSPI_2

VCCPGPPR_1
VCCPGPPR_2

GPP_B0/CORE_VID0
GPP_B1/CORE_VID1
GPP_B2/VRALERT*

VCC1P05_OUTPUT_PLL

VCCPRIM_1P05_3
VCCPRIM_1P05_4

VCCPRIM_1P05_2

VCCRTC

VCCDSW_3P3_1
VCCDSW_3P3_2

CC45
CD46

CE45

CR51

BU45
BV46

PP1P05_S0_CPU_VCCPLL

VOLTAGE=1.05V

PP1V05_PCH_VCCPRIM

?.??A MAX

PP1V05_PCH_VCCPRIM

?.??A MAX

PP3V_G3H

?MA MAX

PP3V3_S5

?MA MAX

11 8

74

74

12 74

12 74

B

A

8

67

SYNC_DATE=06/08/2018SYNC_MASTER=CPU_CARD_ICL_Y

PAGE TITLE

A

PCH Power

DRAWING NUMBER

051-05232

Apple Inc.

REVISION

2.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=CPU & CHIPSET

35 4

IV ALL RIGHTS RESERVED

2

BRANCH

proto4b

PAGE

9 OF 152

SHEET

9 OF 86

1

SIZE

D

678

www.laptoprepairsecrets.com

3 245

1

D

C

B

CR55
CR53
CR15

CR9
CP56
CP50
CP46
CP42
CP38
CP34
CP30
CP26
CP22
CP18
CP14
CP12
CP10
CN55

CN9
CM54

CL9

CL7

CL5

CL1
CK54
CK50
CK46
CK44
CK42
CK40
CK38
CK36
CK34
CK32
CK30
CK28
CK26
CK24
CK22
CK20
CK18
CK16
CK14
CK12
CK10
CJ55
CJ47
CJ41
CJ35

CJ5
CH56
CH10
CG51
CG47
CG37
CG33
CG25
CG19
CG17
CG15
CG13

CG5
CF44
CF10
CE55
CE49
CE47

SYM 12 OF 15
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67

U0500

ICL_YN

BGA

VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98

VSS_99
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134

CRITICAL

OMIT_TABLE

CE5
CD52
CD10
CC47
CC5
CB10
CB8
CB6
CB4
CB2
CA55
CA53
CA51
CA49
CA47
BY52
BY10
BW47
BW5
BV52
BV10
BU47
BT52
BT10
BT8
BT6
BR47
BP52
BP2
BN47
BN5
BM52
BM2
BL47
BL5
BK54
BK52
BK50
BK48
BK2
BJ47
BJ5
BH52
BH2
BG47
BG5
BG3
BF56
BF52
BF2
BE47
BE5
BD52
BD2
BC47
BC5
BB54
BB52
BB50
BB48
BB4
BB2
BA5
AY52
AY46
AY2
AW47

AW5

AV52

AV2
AU5

AU1
AT52
AT46

AT2
AR47

AR5

AR3

AR1
AP52

AP2

AN5

AN1
AM52
AM46

AM2
AL53
AL51
AL49
AL47

AL5

AL1
AK52

AK4

AK2

AJ5
AH52
AH46
AG47

AG5
AF52

AE5
AD52
AD46

AD4
AC47

AC3

AC1
AB52

Y54

Y52

Y50

Y48

Y46

W47

W7
W3

W1
V52
T56
T52
T46

T6

T2
R47
P52

N7

N5

N3

N1
M54
M52
M50
M48

SYM 13 OF 15
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198
VSS_199
VSS_200
VSS_201

U0500

ICL_YN

BGA

VSS_202
VSS_203
VSS_204
VSS_205
VSS_206
VSS_207
VSS_208
VSS_209
VSS_210
VSS_211
VSS_212
VSS_213
VSS_214
VSS_215
VSS_216
VSS_217
VSS_218
VSS_219
VSS_220
VSS_221
VSS_222
VSS_223
VSS_224
VSS_225
VSS_226
VSS_227
VSS_228
VSS_229
VSS_230
VSS_231
VSS_232
VSS_233
VSS_234
VSS_235
VSS_236
VSS_237
VSS_238
VSS_239
VSS_240
VSS_241
VSS_242
VSS_243
VSS_244
VSS_245
VSS_246
VSS_247
VSS_248
VSS_249
VSS_250
VSS_251
VSS_252
VSS_253
VSS_254
VSS_255
VSS_256
VSS_257
VSS_258
VSS_259
VSS_260
VSS_261
VSS_262
VSS_263
VSS_264
VSS_265
VSS_266
VSS_267

CRITICAL

OMIT_TABLE

M46
L47
K52
K8
K6
K2
J45
J37
J33
J17
J11
H52
H38
H36
H34
H20
H14
G47
G45
G31
G17
G11
G7
G5
G3
G1
F52
F50
F40
F36
F24
F20
F14
E45
D56
D50
D42
D38
D34
D30
D26
D24
D20
D14
D8
D6
D4
D2
C45
C21
C17
C11
B54
B50
B40
B36
B32
B28
B24
B22
B14
A51
A47
A17
A11
A5

D

C

B

A

8

67

SYNC_DATE=06/08/2018SYNC_MASTER=CPU_CARD_ICL_Y

PAGE TITLE

A

CPU & PCH Grounds

DRAWING NUMBER

051-05232

Apple Inc.

REVISION

2.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=CPU & CHIPSET

35 4

IV ALL RIGHTS RESERVED

2

BRANCH

proto4b

PAGE

10 OF 152

SHEET

10 OF 86

1

SIZE

D

D

www.laptoprepairsecrets.com

Intel recommendations based on #572907, Ice Lake U/Y Platform Design Guide, rev 1.21

CPU VccIN Decoupling

INTEL RECOMMENDATION (TABLE 10-49): 8X 1UF 0402, 13X 22UF 0402, 1X 220UF D-CASE

PPVCC_S0_CPU

8 46 75

APPLE IMPLEMENTATION : 14x 1uF 0201, 30x 10uF 0402, 2x 180uF D1, 16x 10uF (NOSTUFF), 1x 180uF D1 (NOSTUFF)

CRITICAL

1

C1100

1UF

20%

6.3V

2

X6S-CERM
0201

CRITICAL

1

C1101

1UF

20%

6.3V

2

X6S-CERM
0201

CRITICAL

1

C1102

1UF

20%

6.3V

2

X6S-CERM
0201

CRITICAL

1

C1103

1UF

20%

6.3V

2

X6S-CERM
0201

1

2

678

CRITICAL

C1104

1UF

20%

6.3V
X6S-CERM
0201

CRITICAL

1

C1105

1UF

20%

6.3V

2

X6S-CERM
0201

CRITICAL

1

C1106

1UF

20% 20%

6.3V

2

X6S-CERM
0201

CRITICAL

1

C1107

1UF

6.3V

2

X6S-CERM
0201

CRITICAL

1

C1108

1UF 1UF

20%

6.3V

2

X6S-CERM
0201

1

2

CRITICAL

C1109

20%

6.3V
X6S-CERM
0201

CRITICAL

1

C110A

1UF

20%

6.3V

2

X6S-CERM
0201

CRITICAL

1

C110B

1UF

20%

6.3V

2

X6S-CERM
0201

CRITICAL

1

C110C

1UF

20%

6.3V

2

X6S-CERM
0201

CRITICAL

1

C110D

1UF

20%

6.3V

2

X6S-CERM
0201

3 245

NOSTUFF

1

C110E

10UF

20%

6.3V

2

CER-X6S
0402

NOSTUFF

CRITICAL

1

C110F

10UF

20%

6.3V

2

CER-X6S
0402

CRITICAL

1

C110G

10UF

20%

6.3V

2

CER-X6S
0402

CRITICAL

1

C110H

10UF

20%

6.3V

2

CER-X6S
0402 0402

1

2

CRITICAL

C110J

10UF

20%

6.3V
CER-X6S

CRITICAL

1

C110K

10UF

20%

6.3V

2

CER-X6S
0402

CRITICALCRITICAL

1

C110L

10UF

20%

6.3V

2

CER-X6S
0402

1

CRITICAL

1

C110M

10UF

20%

6.3V

2

CER-X6S
0402

D

CRITICAL

1

C1110

10UF

20%

6.3V

2

CER-X6S
0402

NOSTUFF

CRITICAL

1

C1150

10UF

20%

6.3V

2

CER-X6S
0402

CRITICAL

1

C1120

180UF

20%

2.5V

3 2

POLY-AL
SM

CRITICAL

1

C1111

10UF

20%

6.3V

2

CER-X6S
0402

NOSTUFF

CRITICAL

1

C1151

10UF

20%

6.3V

2

CER-X6S
0402

CRITICAL

1

C1121

180UF

20%

2.5V

3 2

POLY-AL
SM

CRITICAL

1

C1112

10UF

20%

6.3V

2

CER-X6S
0402

CRITICAL

1

C1152

10UF

20%

6.3V

2

CER-X6S
0402 0402

NOSTUFF

CRITICAL

1

C1122

180UF

20%

2.5V

3 2

POLY-AL
SM

CRITICAL

1

C1113

10UF

20%

6.3V

2

CER-X6S
0402

CRITICAL

1

C1153

10UF

20%

6.3V

2

CER-X6S

CRITICAL

1

C1114

10UF

20%

6.3V

2

CER-X6S
0402

CRITICAL

1

C1154

10UF

20%

6.3V

2

CER-X6S
0402

CRITICAL

1

C1115

10UF

20%

6.3V

2

CER-X6S
0402

CRITICAL

1

C1155

10UF

20%

6.3V

2

CER-X6S
0402

CRITICAL

1

C1116

10UF

20%

6.3V

2

CER-X6S
0402

CRITICAL

1

C1156

10UF

20%

6.3V

2

CER-X6S
0402

CRITICAL

1

C1117

10UF

20%

6.3V

2

CER-X6S
0402

CRITICAL

1

C1157

10UF

20%

6.3V

2

CER-X6S
0402

NOSTUFF

CRITICAL

1

C1118

10UF

20%

6.3V

2

CER-X6S
0402

CRITICAL

1

C1158

10UF

20%

6.3V

2

CER-X6S
0402

NOSTUFF

CRITICAL

1

C1119

10UF

20%

6.3V

2

CER-X6S
0402

CRITICAL

1

C1159

10UF

20%

6.3V

2

CER-X6S
0402

NOSTUFF

CRITICAL

1

C111A

10UF

20%

6.3V

2

CER-X6S
0402

CRITICAL

1

C115A

10UF

20%

6.3V

2

CER-X6S
0402

NOSTUFF

CRITICAL

1

C111B

10UF

20%

6.3V

2

CER-X6S
0402

CRITICAL

1

C115B

10UF

20%

6.3V

2

CER-X6S
0402

NOSTUFF

CRITICAL

1

C111C

10UF

20%

6.3V

2

CER-X6S
0402

CRITICAL

1

C115C

10UF

20%

6.3V

2

CER-X6S
0402

NOSTUFF

CRITICAL

1

C111D

10UF

20%

6.3V

2

CER-X6S
0402

CRITICAL

1

C115D

10UF

20%

6.3V

2

CER-X6S
0402

NOSTUFF

CRITICAL

1

C111E

10UF

20%

6.3V

2

CER-X6S
0402

CRITICAL

1

C115E

10UF 10UF

20%

6.3V

2

CER-X6S
0402

NOSTUFF

CRITICAL

1

C111F

2

CRITICAL

1

C115F

2

10UF

20%

6.3V
CER-X6S
0402

20%

6.3V
CER-X6S
0402

NOSTUFF

CRITICAL

1

C111G

10UF

20%

6.3V

2

CER-X6S
0402

CRITICAL

1

C115G

10UF

20%

6.3V

2

CER-X6S
0402

NOSTUFF

CRITICAL

1

C111H

10UF

20%

6.3V

2

CER-X6S
0402

CRITICAL

1

C115H

10UF

20%

6.3V

2

CER-X6S
0402

NOSTUFF

CRITICAL

1

C111J

10UF

20%

6.3V

2

CER-X6S
0402

NOSTUFF

CRITICAL

1

C111K

10UF

20%

6.3V

2

CER-X6S
0402

C

INTEL RECOMMENDATION (TABLE 10-50): 7x47uF 0805, 8x 10uF 0402, 7x 1uF 0402, 3x 47uF 0805 (placeholder), 3x 10uF 0402 (placeholder).
APPLE IMPLEMENTATION : 2x 180uF D1, 16x 10uF 0402, 12x 1uF 0201, 6x 10uF 0402 (NOSTUFF).

80 75 59

PPVCCIN_AUX_PCH

CRITICAL

1

C1130

1UF

20%

6.3V

2

X6S-CERM
0201

CRITICAL

1

C1140

10UF

20%

6.3V

2

CER-X6S
0402

CRITICAL

1

C1131

1UF

20%

6.3V

2

X6S-CERM
0201

CRITICAL

1

C1141

10UF

20%

6.3V

2

CER-X6S
0402

CRITICAL

1

C1132

1UF

20%

6.3V

2

X6S-CERM
0201

CRITICAL

1

C1142

10UF

20%

6.3V

2

CER-X6S
0402

CRITICAL

1

C1133

1UF

20%

6.3V

2

X6S-CERM
0201

CRITICAL

1

C1143

10UF

20%

6.3V

2

CER-X6S
0402

CRITICAL

1

C1134

1UF

20%

6.3V

2

X6S-CERM
0201

CRITICAL

1

C1144

10UF

20%

6.3V

2

CER-X6S
0402

CRITICAL

1

C1135

1UF

20%

6.3V

2

X6S-CERM
0201

CRITICAL

1

C1145

10UF

20%

6.3V

2

CER-X6S
0402

CRITICAL

1

C1136

1UF

20%

6.3V

2

X6S-CERM
0201

CRITICAL

1

C1146

10UF

20%

6.3V

2

CER-X6S
0402

CRITICAL

1

C1137

1UF

20%

6.3V

2

X6S-CERM
0201

CRITICAL

1

C1147

10UF

20%

6.3V

2

CER-X6S
0402

CRITICAL

1

C1138

1UF

20%

6.3V

2

X6S-CERM
0201

NOSTUFF

CRITICAL

1

C1148

10UF

20%

6.3V

2

CER-X6S
0402

CRITICAL

1

C1139

1UF

20%

6.3V

2

X6S-CERM
0201

NOSTUFF

CRITICAL

1

C1149

10UF

20%

6.3V

2

CER-X6S
0402

CRITICAL

1

C113A

1UF

20%

6.3V

2

X6S-CERM
0201

CRITICAL

1

C113B

1UF

20%

6.3V

2

X6S-CERM
0201

C

B

PP1V1_S3

8 75

CRITICAL

1

C1170

1UF

20%

6.3V

2

X6S-CERM
0201

CRITICAL

1

C1180

10UF

20%

6.3V

2

CER-X6S
0402

CRITICAL

1

C1171

1UF

20%

6.3V

2

X6S-CERM
0201

CRITICAL

1

C1181

10UF

20%

6.3V

2

CER-X6S
0402

CRITICAL

1

C1172

1UF

20%

6.3V

2

X6S-CERM
0201

CRITICAL

1

C1182

10UF

20%

6.3V

2

CER-X6S
0402

CRITICAL

1

C1173

1UF

20%

6.3V

2

X6S-CERM
0201

CRITICAL

1

C1183

10UF

20%

6.3V

2

CER-X6S
0402

CRITICAL

1

C1174

1UF

20%

6.3V

2

X6S-CERM
0201

CRITICAL

1

C1184

10UF

20%

6.3V

2

CER-X6S
0402

CRITICAL

1

C1175

1UF

20%

6.3V

2

X6S-CERM
0201

CRITICAL

1

C1185

10UF

20%

6.3V

2

CER-X6S
0402

CRITICAL

1

C1176

1UF

20%

6.3V

2

X6S-CERM
0201

CRITICAL

1

C1186

10UF

20%

6.3V

2

CER-X6S
0402

CRITICAL

1

C1177

1UF

20%

6.3V

2

X6S-CERM
0201

17 16 8 6

PP1V05_VCCSTG_OUT

C1198

1UF

20%

6.3V

X6S-CERM

0201

B

66 8

1

2

PP1V8_S0SW_CPU

1

C1195

10UF

20%

6.3V

2

CER-X6S
0402

CRITICAL

1

C1196

10UF

20%

6.3V

2

CER-X6S
0402

NOSTUFFCRITICAL

1

C1197

22UF

20%
4V

2

X5R
0402-1

A

PP1V05_S0_VCCSTG

66 8

NOSTUFF

C11A3

1UF

20%

6.3V

X6S-CERM

0201

67

NOSTUFF

1

C11A4

1UF

2

X6S-CERM

20%

6.3V
0201

1

C11A5

1UF

2

X6S-CERM

20%

6.3V
0201

1

2

8

C11A0

1UF

20%

6.3V

X6S-CERM

0201

1

2

NOSTUFF

C11A1

1UF

20%

6.3V

X6S-CERM

0201

20%

6.3V
0201

1

2

1

C11A2

1UF

2

X6S-CERM

SYNC_DATE=06/08/2018SYNC_MASTER=CPU_CARD_ICL_Y

PAGE TITLE

A

CPU Decoupling

PP1P05_S0_CPU_VCCPLLPP1V05_S0_CPU_VCCST PP1V1_S0SW_CPU_VCCPLL_OC

9 8 78 66 39 17 8 66 8

NOSTUFF

C11A6

1UF

20%

6.3V

X6S-CERM

0201

1

C11A7

1UF

2

X6S-CERM

20%

6.3V
0201

1

2

BOM_COST_GROUP=CPU & CHIPSET

35 4

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

2

Apple Inc.

DRAWING NUMBER

051-05232

REVISION

2.0.0

BRANCH

proto4b

PAGE

11 OF 152

SHEET

11 OF 86

1

SIZE

D

PP1V24_S5_PCH_VCCDPHY

www.laptoprepairsecrets.com

9

MIN_LINE_WIDTH=0.7000
MIN_NECK_WIDTH=0.0750

VOLTAGE=1.24V

678

3 245

1

D

PP0V85_LDOSTD

9

C1300

4.7UF

BYPASS=U0500.DA37::2.54MM

C1305

2.2UF

X6S-CERM

BYPASS=U0500.DA45::2.54MM

20%

6.3V
X6S

0402

20%

4V

0201

1

2

D

1

2

0.6UH-20%-2.8A-0.02OHM

NOSTUFF

L1350

21

XFL4012-SM

C

PP1V8_PRIM_PCH

9 66 75

C1310

X6S-CERM

BYPASS=U0500.CG30::2.54mm

BYPASS=U0500.CG30::2.54mm

PP1V05_S5_PCH_VCCDSW

9

BYPASS=U0500.CJ29::2.54mm

1UF

20%

6.3V
0201

75

1

C1311

1UF

2

6.3V

X6S-CERM

0201

1

20%

2

PP1V8_PRIM_PCH

PLACE_NEAR=U0500.CJ11:12.7mm

R1350

0.010

1%

1/6W

MF

0402

MIN_LINE_WIDTH=0.4500

21

5%
MF

0201

1

0

2

R1351

1/20W

MIN_NECK_WIDTH=0.0750
VOLTAGE=1.8V

PP1V8_PCH_CLKLDO

9

PP1V8_PCH_CLKLDO_R

C

C1315

1UF

20%

6.3V

X6S-CERM

0201

1

C1352

1UF

20%

6.3V

2

X6S-CERM
0201

20%
10V
X5R

0402

1

2

1

C1350

20UF

20%
10V
X5R

0402

1

2

BYPASS=U0500.CJ11::12.7mm

BYPASS=U0500.CJ11::12.7mm

BYPASS=U0500.CJ11::2.54mm

C1351

20UF

2

B

PCH VCCDSW_3P3 Bypass
(PCH 3.3V DSW Power)

PP3V3_S5

9 74

PCH VCCRTC Bypass
(PCH 3V RTC Power)

PP3V_G3H

9 74

C1325

0.1UF

X6S-CERM

10%
25V

0201

NOSTUFF

20%

6.3V

1

2

C1320

1UF

X6S-CERM

0201

B

1

C1326

1UF

2

6.3V

X6S-CERM

0201

1

20%

2

A

BYPASS=U0500.CB38::2.54mm

SYNC_MASTER=CPU_CARD_ICL_Y SYNC_DATE=06/08/2018

PAGE TITLE

A

8

67

PCH Decoupling

DRAWING NUMBER

051-05232

Apple Inc.

REVISION

2.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=CPU & CHIPSET

35 4

IV ALL RIGHTS RESERVED

2

BRANCH

proto4b

PAGE

13 OF 152

SHEET

12 OF 86

1

SIZE

D

D

www.laptoprepairsecrets.com

C

678

13

13

13

13

78 23 13

78 23 13

16

16 13

18 16 13

16

16 13

16

16

23 13

23 13

31 13

25 24 23 13

23 13

23 13

BI
BI
BI
BI

IN
OUT

BI
BI
BI
BI
BI

BI
BI

BI
BI
BI

BI

BI
BI

TP_PCH_GPP_D10
TP_PCH_GPP_D11
TP_PCH_GPP_D8
TP_PCH_GPP_D9

PCH_UART_DEBUG_D2R
PCH_UART_DEBUG_R2D

XDP_PCH_STRP_GPP_E0
XDP_PCH_STRP_CNV_DISABLE
XDP_MEM_OK
XDP_PCH_OBSDATA_B0
XDP_PCH_OBSDATA_B2

XDP_LSX_TBTD_R2P
XDP_LSX_TBTD_P2R
NC_PCH_GPP_E20
NC_PCH_GPP_E21
NC_PCH_GPP_E22
NC_PCH_GPP_E23

JTAG_ISP_TCK
JTAG_ISP_TDI
PCH_SOC_SYNC
NC_PCH_GPP_C8
NC_PCH_GPP_C9
NC_PCH_GPP_C10
PCH_BSB_FORCE_PWR

MLB_RAMCFG0

13

MLB_RAMCFG1

13

MLB_RAMCFG2

13

MLB_RAMCFG3

13

MLB_RAMCFG4

13

JTAG_TBT_X_TMS
JTAG_TBT_T_TMS

CL31
CM32
CR33
CP32

CR49
CP48

CL23
CM22
CP24
CN25
CR25

CN23
CM24
CM16
CP16
CL15
CN15

CM30
CN31
CL29
CM28
CN29
CL27
CP28

CJ51
CD48
BW45
CH50
CD50
BY46
CC49

CRITICAL

OMIT_TABLE

U0500

ICL_YN

BGA

SYM 5 OF 15
GPP_D10/UART0A_RST*
GPP_D11/UART0A_CTS*
GPP_D8/UART0A_RXD
GPP_D9/UART0A_TXD

GPP_B17/UART2A_RXD
GPP_B18/UART2A_TXD

GPP_E0
GPP_E1
GPP_E2
GPP_E4
GPP_E6

GPP_E11
GPP_E12
GPP_E20
GPP_E21
GPP_E22
GPP_E23

GPP_C1
GPP_C2
GPP_C7
GPP_C8 GPP_R6
GPP_C9
GPP_C10
GPP_C13

GPP_G0
GPP_G2
GPP_G3
GPP_G4
GPP_G5
GPP_G6
GPP_G7

GPP_A6/ESPI_RESET*

GPP_A7/SMBCLK

GPP_A8/SMBDATA

GPP_A9/SMBALERT*

GPP_E10/SML0DATA

GPP_E9/SML0CLK

GPP_B11/PMCALERT*

GPP_A5/ESPI_CLK
GPP_A0/ESPI_IO0
GPP_A1/ESPI_IO1
GPP_A2/ESPI_IO2
GPP_A3/ESPI_IO3
GPP_A4/ESPI_CS*

GPP_H3
GPP_H4
GPP_H5

GPP_H8
GPP_H21
GPP_H22

GPP_R5

CM46
CL47
CL45

CN21
CL21

CL53

CL41
CM44
CN43
CR43

CL43
CN41
CM42

CM36
CN33
CP40
CN37
CJ27
CJ29

CM34
CM38

SMBUS_PCH_CLK
SMBUS_PCH_DATA
NC_PCH_GPP_A9

XDP_PCH_I2C_UPC_SDA
XDP_PCH_I2C_UPC_SCL
PCH_UPC_I2C_INT_L

ESPI_CLK60M_R
ESPI_IO<0>
ESPI_IO<1>
ESPI_IO<2>
ESPI_IO<3>
ESPI_CS_L
ESPI_RESET_L

TBT_POC_RESET
JTAG_ISP_TDO
NC_SDCON_OC_L
PCH_GCON_INT_L
NC_PCH_GPP_H21
NC_PCH_GPP_H22

NC_PCH_GPP_R5
NC_PCH_GPP_R6

3 245

42

BI

42

BI

BI
BI

42

BI

R1410

32

BI

32

BI

32

BI

32

BI

32

OUT
OUT

BI
BI

BI

32 13

32

1

D

42 16

42 16

21

25 24 23 13

23 13

51

201

ESPI_CLK60M

OUT

32

C

B

A

NOSTUFF

R1451
R1452
R1453
R1454
R1455
R1456
R1457
R1458
R1459
R1460
R1461
R1467
R1462
R1463
R1464
R1465
R1466
R1468

PP1V8_PRIM_PCH

PP3V3_S5

47K

47K
100K
100K

47K

47K

47K

1K
100K
100K

10K
10K

100K

10K
100K
100K
100K
100K

6 15 75

5 14 17 18 42 74

21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21

1/20W MF5%
1/20W

5%

1/20W 201

5% MF

5% 1/20W MF

1/20W MF

1/20W5% 201MF
5%
5%

1/20W
5% 201MF1/20W

201
MF 2015%
MF5%
MF1/20W5%
MF1/20W 201

MF

2011/20W

201

2015% 1/20W

201

2015%

2015% 1/20W MF

201MF1/20W

2011/20W MF

201MF1/20W5%

2015% MF

201MF5% 1/20W

201MF1/20W5%

PCH_UART_DEBUG_D2R
PCH_UART_DEBUG_R2D

JTAG_ISP_TCK

JTAG_ISP_TDI
TP_PCH_GPP_D8
TP_PCH_GPP_D9

TP_PCH_GPP_D10
TP_PCH_GPP_D11

XDP_PCH_STRP_CNV_DISABLE

XDP_MEM_OK
JTAG_TBT_X_TMS
JTAG_TBT_T_TMS

TBT_POC_RESET

JTAG_ISP_TDO

XDP_PCH_OBSDATA_B2

ESPI_RESET_L

PCH_BSB_FORCE_PWR

PCH_SOC_SYNC

13

13

13

13

B

78 23 13

78 23 13

23 13

23 13

16 13

18 16 13

23 13

23 13

25 24 23 13

23 13

16 13

32 13

25 24 23 13

31 13

RAMCFG0_L

1

R1490

1K

5%
1/20W
MF
201

2

RAM Configuration Straps

MLB_RAMCFG0
MLB_RAMCFG1
MLB_RAMCFG2
MLB_RAMCFG3
MLB_RAMCFG4

RAMCFG1_L

1

R1491

1K

5%
1/20W
MF
201

2

RAMCFG2_L

1

R1492

1K

5%
1/20W
MF
201

2

RAMCFG3_L

1

R1493

1K

5%
1/20W
MF
201

2

RAMCFG4_L

1

R1494

1K

5%
1/20W
MF
201

2

13

13

13

13

13

BOM_COST_GROUP=CPU & CHIPSET

SYNC_MASTER=CPU_CARD_ICL_Y SYNC_DATE=06/08/2018

PAGE TITLE

PCH ESPI/SMBUS/UART

SIZE

D

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

051-05232

REVISION

2.0.0

BRANCH

proto4b

PAGE

14 OF 152

SHEET

13 OF 86

A

8

67

35 4

2

1

678

www.laptoprepairsecrets.com

3 245

1

D

D

C

14 78

14 78

14 17 64 66 78

14 17 18 61

14 17 78 81

17 18

39

14 18 39 78

17

17 18

39 78

OUT
OUT
OUT
OUT
OUT

IN
IN

OUT

IN
IN
IN

PM_SLP_S5_L
PM_SLP_S4_L
PM_SLP_S3_L
PM_SLP_SUS_L
PM_SLP_S0_L

PM_RSMRST_L
PM_SYSRST_L
PLT_RST_L

PM_PCH_DPWROK
PM_PCH_PWROK
PM_PCH_SYS_PWROK

CJ53
CH52
CK52
CC55
CM48

CC53
CR31
CN49

CE53
CB50
CR27

CRITICAL

OMIT_TABLE

U0500

ICL_YN

BGA

SYM 8 OF 15
GPD10/SLP_S5* GPD3/PWRBTN*
GPD5/SLP_S4*
GPD4/SLP_S3*
SLP_SUS*
GPP_B12/SLP_S0*

RSMRST*
SYS_RESET*
GPP_B13/PLTRST*

DSW_PWROK
PCH_PWROK
SYS_PWROK

GPP_H10/CPU_C10_GATE*

GPD0/BATLOW*

GPD7

WAKE*

GPD2/LAN_WAKE*

VCCST_OVERRIDE

VCCST_PWRGD

VCCSTPWRGOOD_TCSS

PROCPWRGD

DSWLDO_MON

CF52
CL33
CB54

CG53

CJ49
CC51

BV6
BU9
BV8
E27
CD54

PCH_PWRBTN_L
CPU_C10_GATE_L
PCH_BATLOW_L

PCH_STRP_GPD7
PCH_PCIE_WAKE_L

PCH_LAN_WAKE_L
VCCST_OVERRIDE

VCCST_PWRGD_R
VCCST_OVERRIDE
TP_CPU_PWRGD
TP_DSWLDO_MON

14

14

14

18

IN

OUT

BI

OUT

IN

14 64

14 17 66

14 23

14 66

14 66

R1511

62

5%

1/20W

MF

201

C

PP1V05_VCCST_OUT

NOSTUFF

1

R1510

1K

5%
1/20W
MF
201

2

21

VCCST_PWRGD

IN

17

6 8 39 57 64

B

A PM_SLP_S0_L NOTE

PM_SLP_S0_L has an intenral pull-up before RSMRST#
is released. This causes a voltage divider with
the pull-down R1553. The signal is driven high
after RSMRST# is released.

R1550
R1551
R1552
R1553

100K
100K
100K

100K

PP3V3_S5

21
21

21

21

13 74 42 18 17 5

1/20W

5% 201MF

1/20W
1/20W

5% 1/20W MF 201

MF5%

2015% MF

201

PLT_RST_L
PCH_PCIE_WAKE_L
PCH_LAN_WAKE_L
PM_SLP_S0_L

14 18 39 78

14

14

14 17 78 81

B

A

NOSTUFF

NOSTUFF

R1554
R1555
R1556
R1560
R1557
R1558
R1559
R1570

R1561
R1562

8

100K
100K
100K
100K

1K
100K
100K
100K

100K
100K

21
21
21
21
21
21
21
21

21
21

1/20W MF 2015%

5% 1/20W

1/20W5% MF
1/20W MF5%
1/20W MF5%
1/20W5%
1/20W5% 201MF

5%

1/20W
1/20W

5% 201

MF1/20W5%

MF 201

MF 201

MF
MF

PM_SLP_S3_L

201

PM_SLP_S4_L
PM_SLP_S5_L
PM_SLP_SUS_L

201

PCH_PWRBTN_L

201

PCH_BATLOW_L

201

CPU_C10_GATE_L

PCH_STRP_GPD7

201

VCCST_OVERRIDE

78 66 64 17 14

78 14

78 14

61 18 17 14

64 14

14

66 17 14

23 14

66 14

67

SYNC_DATE=06/08/2018SYNC_MASTER=CPU_CARD_ICL_Y

PAGE TITLE

A

PCH Power Management

DRAWING NUMBER

051-05232

Apple Inc.

REVISION

2.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=CPU & CHIPSET

35 4

IV ALL RIGHTS RESERVED

2

BRANCH

proto4b

PAGE

15 OF 152

SHEET

14 OF 86

1

SIZE

D

678

www.laptoprepairsecrets.com

3 245

1

CRITICAL

OMIT_TABLE

D

C

PCIe Port Assignments:

SOC lane 3

SOC lane 2

SOC lane 1

SOC lane 0

R1610

100

1%

1/20W

MF

201

U0500

USB3 Port Assignments:

PCIe Port Assignments:

ICL_YN

BGA

SYM 6 OF 15

34

34

40

40

34

34

40

40

34

34

40

40

34

34

40

40

16

16 15

16

18

18

18

18

16

1

PCIE_SOC_D2R_P<3>

IN

PCIE_SOC_D2R_N<3>

IN

PCIE_SOC_R2D_C_P<3>

OUT

PCIE_SOC_R2D_C_N<3>

OUT

PCIE_SOC_D2R_P<2>

IN

PCIE_SOC_D2R_N<2>

IN

PCIE_SOC_R2D_C_P<2>

OUT

PCIE_SOC_R2D_C_N<2>

OUT

PCIE_SOC_D2R_P<1>

IN

PCIE_SOC_D2R_N<1>

IN

PCIE_SOC_R2D_C_P<1>

OUT

PCIE_SOC_R2D_C_N<1>

OUT

PCIE_SOC_D2R_P<0>

IN

PCIE_SOC_D2R_N<0>

IN

PCIE_SOC_R2D_C_P<0>

OUT

PCIE_SOC_R2D_C_N<0>

OUT

XDP_PCH_OBSFN_C0

BI

XDP_PCH_STRP_SPIROM_SAF

BI

XDP_PCH_OBSDATA_B3

BI

USB_EXTA_OC_L

BI

USB_EXTD_OC_L

BI

USB_EXTC_OC_L

BI

USB_EXTB_OC_L

BI

XDP_PCH_OBSDATA_B1

BI

PCH_PCIE_RCOMP_P
PCH_PCIE_RCOMP_N

PLACE_NEAR=U0500.CG1:2.54mm

2

CG1
CG3
CH6
CH8

CH2
CH4
CG7
CG9

CF2
CF4
CF6
CF8

CE1
CE3
CE7
CE9

CR23

CM20
CP20

CN39
CR39
CM40
CL39

CM26

CN3
CL3

PCIE4_RXP
PCIE4_RXN
PCIE4_TXP
PCIE4_TXN

PCIE3_RXP
PCIE3_RXN
PCIE3_TXP
PCIE3_TXN

PCIE2_RXP
PCIE2_RXN
PCIE2_TXP
PCIE2_TXN

PCIE1_RXP
PCIE1_RXN
PCIE1_TXP
PCIE1_TXN

GPP_E8

GPP_E3
GPP_E7

GPP_A18/USB_OC0*
GPP_A12/USB_OC1*
GPP_A13/USB_OC2*
GPP_A14/USB_OC3*

GPP_E5

PCIE_RCOMPP
PCIE_RCOMPN

GPP_E19/IMGCLKOUT5/PCIE_LNK_DOWN

PCIE8_RXP
PCIE8_RXN
PCIE8_TXP
PCIE8_TXN

PCIE7_RXP
PCIE7_RXN
PCIE7_TXP
PCIE7_TXN

PCIE6_RXP
PCIE6_RXN
PCIE6_TXP
PCIE6_TXN

PCIE5_RXP
PCIE5_RXN
PCIE5_TXP
PCIE5_TXN

USB2P_3
USB2N_3

USB2P_2
USB2N_2

USB2P_1
USB2N_1

USB_ID

USB_VBUSSENSE

USB2_COMP

CC1
CC3
CD6
CD8

CD4
CD2
CC7
CC9

CK2
CK4
CK6
CK8

CJ1
CJ3
CJ7
CJ9

CM8
CP8

CM6
CP6

CR7
CN7

CR5

CN5

CP4

CL25

USB3_BSSB_D2R_P
USB3_BSSB_D2R_N
USB3_BSSB_R2D_C_P
USB3_BSSB_R2D_C_N

NC_PCIE_PCH_ENETSD_D2RP
NC_PCIE_PCH_ENETSD_D2RN
NC_PCIE_PCH_ENETSD_R2DCP
NC_PCIE_PCH_ENETSD_R2DCN

USB3_FCT_D2R_P
USB3_FCT_D2R_N
USB3_FCT_R2D_C_P
USB3_FCT_R2D_C_N

PCIE_PCH_WLAN_D2R_P
PCIE_PCH_WLAN_D2R_N
PCIE_PCH_WLAN_R2D_C_P
PCIE_PCH_WLAN_R2D_C_N

USB2_FCT_P
USB2_FCT_N

USB2_TBT_T_P
USB2_TBT_T_N

USB2_TBT_X_P
USB2_TBT_X_N

GND
GND
PCH_USB2_COMP
TP_PCH_PCIE_LINK_DOWN

18

18

IN

IN
OUT
OUT

IN

IN
OUT
OUT

IN

IN
OUT
OUT

IN

IN
OUT
OUT

BI
BI

BI
BI

BI
BI

23

23

23

23

76

76

76

76

78

78

78

78

29

29

29

29

78

78

25

25

24

24

BSSB

SPARE (SS)

USB2 PORT ASSIGNMENTS:
FIXTURE (LS/FS/HS)

USB-C T (LS/FS/HS)

USB-C X (LS/FS/HS)

PLACE_NEAR=U0500.CP4:2.54mm

1

R1622

113

1%
1/20W
MF
201

2

ENET/SD

WLAN

D

C

B

PP1V8_PRIM_PCH

R1650
R1651

1K
1K

6 13 15 75

21
21

5%

MF

PCH_STRP_NO_REBOOT

2011/20W5%

XDP_PCH_STRP_SPIROM_SAF

2011/20W MF

15

16 15

CRITICAL

OMIT_TABLE

U0500

ICL_YN

BGA

SYM 7 OF 15

76

76

76 18 15

29

29

29 15

76

76

OUT
OUT
BI

OUT
OUT
BI

OUT
OUT

NC_PCIE_CLK100M_DEBUGP
NC_PCIE_CLK100M_DEBUGN

DEBUG_CLKREQ_STRAP_L

PCIE_CLK100M_PCH_WLAN_P
PCIE_CLK100M_PCH_WLAN_N

PCH_WLAN_CLKREQ_L

TP_PCIE_CLK100M_PCH2P
TP_PCIE_CLK100M_PCH2N

PCH_STRP_NO_REBOOT

15

NC_PCIE_CLK100M_ENETSDP
NC_PCIE_CLK100M_ENETSDN

NC_PCH_ENETSD_CLKREQ_L

TP_PCIE_CLK100M_PCH4P
TP_PCIE_CLK100M_PCH4N

TP_GPU_CLKREQ_L

BY4
BY2

CP52

BY8
BY6

CN51

CA9
CA7

CM50

BW3
BW1

CM52

BW9
BW7

CL51

CLKOUT_PCIE_P0
CLKOUT_PCIE_N0
GPP_B5/SRCCLKREQ0*

CLKOUT_PCIE_P1
CLKOUT_PCIE_N1
GPP_B6/SRCCLKREQ1*

CLKOUT_PCIE_P2
CLKOUT_PCIE_N2
GPP_B7/SRCCLKREQ2*

CLKOUT_PCIE_P3
CLKOUT_PCIE_N3
GPP_B8/SRCCLKREQ3*

CLKOUT_PCIE_P4
CLKOUT_PCIE_N4
GPP_B9/SRCCLKREQ4*

CLKOUT_PCIE_P5
CLKOUT_PCIE_N5

GPP_B10/SRCCLKREQ5*

RTCX1
RTCX2

RTCRST*

SRTCRST*

XTAL_IN

XTAL_OUT

XCLK_BIASREF

CA3
CA1
CL49

CK56
CL55

CH54

CF54

CR11
CR13

CA5

PCIE_CLK100M_SOC_P
PCIE_CLK100M_SOC_N

SOC_CLKREQ_BUF_L

PMU_CLK32K_PCH_1V0

NC_PCH_CLK32K_XTALOUT

PCH_RTC_RESET_L
PCH_RTC_RESET_L

PCH_CLK38M4_XTALIN

PCH_CLK38M4_XTALOUT
PCH_DIFFCLK_BIASREF

34

OUT

34

OUT

BI

IN

IN

IN

OUT

PLACE_NEAR=U0500.CK4:2.54mm

1

R1670

60.4

1%
1/20W
MF
201

2

18 15

64 18

18

17

17

R1672

127K

1%

1/20W

MF

201

R1673

100K

1

2

1/20W

PLACE_NEAR=U0500.CL49:5mm
PLACE_NEAR=U0500.CL49:5mm

1%
MF

201

21

PMU_CLK32K_PCH

1.0V <- 1.8V

IN

B

64

A

PP1V8_PRIM_PCH

R1660
R1661
R1662

47K
47K
47K

8

NOSTUFF

6 13 15 75

21
21

5% MF1/20W 201

21

1/20W MF5% 201

MF5% 1/20W

SOC_CLKREQ_BUF_L

201

PCH_WLAN_CLKREQ_L
DEBUG_CLKREQ_STRAP_L

18 15

29 15

15 18 76

67

SYNC_DATE=06/08/2018SYNC_MASTER=CPU_CARD_ICL_Y

PAGE TITLE

A

PCH PCIe/USB/CLK

DRAWING NUMBER

051-05232

Apple Inc.

REVISION

2.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=CPU & CHIPSET

35 4

IV ALL RIGHTS RESERVED

2

BRANCH

proto4b

PAGE

16 OF 152

SHEET

15 OF 86

1

SIZE

D

678

www.laptoprepairsecrets.com

3 245

1

D

C

CPU_CFG<0>

17 6

CPU_CFG<1>

17 6

CPU_CFG<2>

6

CPU_CFG<3>

6

CPU_CFG<4>

6

CPU_CFG<5>

6

CPU_CFG<6>

6

CPU_CFG<7>

6

CPU_CFG<8>

17 6

CPU_CFG<9>

17 6

CPU_CFG<10>

17 6

CPU_CFG<11>

6

CPU_CFG<12>

17 6

CPU_CFG<13>

17 6

CPU_CFG<14>

6

CPU_CFG<15>

6

CPU_CFG<16>

6

CPU_CFG<17>

6

CPU_CFG<18>

6

CPU_CFG<19>

6

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

PP1800

PP

0.50MM

SM

P2MM

PP

PP1801

SM

P2MM

PP

PP1802

SM

P2MM

PP

PP1803

PP1804

PP

0.50MM

PP1805

PP

0.50MM

SM

P2MM

PP

PP1806

PP1807

PP

0.50MM

SM

P2MM

PP

PP1808

PP1809

PP

0.50MM

SM

P2MM

PP

PP1810

SM

P2MM

PP

PP1811

SM

P2MM

PP

PP1812

PP1813

PP

0.50MM

PP1814

PP

0.50MM

PP1815

PP

0.50MM

SM

P2MM

PP

PP1816

SM

P2MM

PP

PP1817

SM

P2MM

PP

PP1818

SM

P2MM

PP

PP1819

SM

SM

SM

SM

SM

SM

SM

SM

XDP_PREQ_L

6

XDP_PRDY_L

6

DBG_PMODE

6

XDP_BPM_L<0>

6

IFDIM Trigger for DCDC

XDP_BPM_L<1>

6

XDP_BPM_L<2>

6

XDP_BPM_L<3>

6

XDP_PRESENT_L

32

TP XDP Signals

NOSTUFF

R1895

100K

5%

1/20W

MF

201

NOSTUFF

R1894

100K

5%

1/20W

MF

201

D

SM

P2MM

1

PP

PP1820

SM

P2MM

1

PP

PP1821

SM

P2MM

1

PP

PP1822

SM

P2MM

1

PP

PP1823

1

2

SM

P2MM

1

PP

PP1824

SM

P2MM

1

PP

PP1825

SM

P2MM

1

PP

PP1826

79 78 75 59

PP1V8_PRIM_PCH

R1880

NOSTUFF

R1881

100K

5%

1/20W

MF

201

5%

1/20W

MF

0201

1

2

XDP_PRESET_L

1

OUT

66

0

2

C

1

2

B

A

PCH XDP Signals

These signals do not connect to the Primary (Merged) XDP connector in this architecture because it does not exist.
The PDG puts them on a secondary XDP connector that is only needed in some PCH debugging situation, but also does not exist.
They are listed here to show their secondary XDP functions and to provide test points for signals that are not used elsewhere.
Unused GPIOs have TPs.

PCH/XDP Signals

13 6

BI OUT

13

BI

18 13

42 13

42 13

15

13

15

13

15

15

13

13

23 5

23 5

23 5

23 5

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

5

BI

XDP_PCH_STRP_GPP_E0
XDP_PCH_STRP_CNV_DISABLE
XDP_MEM_OK
XDP_PCH_STRP_SPIROM_SAF
XDP_PCH_OBSDATA_B0
XDP_PCH_OBSDATA_B1
XDP_PCH_OBSDATA_B2
XDP_PCH_OBSDATA_B3
XDP_PCH_OBSFN_C0
XDP_PCH_I2C_UPC_SCL
XDP_PCH_I2C_UPC_SDA
XDP_LSX_TBTD_R2P
XDP_LSX_TBTD_P2R
XDP_LSX_TBTA_R2P
XDP_LSX_TBTA_P2R
XDP_LSX_TBTB_R2P
XDP_LSX_TBTB_P2R
XDP_LSX_TBTC_R2P

FN0

FN1

FN2

FN3

FN4

FN5

FN6

FN7

FN_CLK1

FN8

FN9

FN10

FN11

FN12

FN13

FN14

FN15

FN_CLK2

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

PP1868

PP

0.50MM

PP1869

PP

0.50MM

PP1870

PP

0.50MM

SM

P2MM

PP

PP1871

PP1872

PP

0.50MM

PP1873

PP

0.50MM

SM

P2MM

PP

PP1874

SM

P2MM

PP

PP1880

SM

P2MM

PP

PP1881

PP1882

PP

0.50MM

PP1883

PP

0.50MM

PP1875

PP

0.50MM

PP1876

PP

0.50MM

PP1877

PP

0.50MM

PP1878

PP

0.50MM

PP1884

PP

0.50MM

PP1885

PP

0.50MM

SM

P2MM

PP

PP1886

SM

SM

SM

SM

SM

SM

SM

SM

SM

SM

SM

SM

SM

Non-XDP Signals

PP1V05_VCCSTG_OUT

JTAG Chain for DCI Only Connectivity

6

IN

6

OUT

6

OUT

XDP_CPUPCH_TDO
XDP_CPUPCH_TDO

XDP_CPUPCH_TCK

MAKE_BASE=TRUE

MAKE_BASE=TRUE

XDP_CPUPCH_TDO

PLACE_NEAR=U0500.A27:28MM

XDP_CPUPCH_TCK

1

R1890

100

5%
1/20W
MF
201

2

PLACE_NEAR=U0500.D28:28MM

1

R1891

100

5%
1/20W
MF
201

2

PLACE_NEAR=U0500.CL13:28MM

17 11 8 6

XDP_CPUPCH_TCK

1

PP1890

6

OUT

6

OUT

6

OUT

6

OUT

6

OUT

6

OUT

6

OUT

XDP_CPUPCH_TRST_L
XDP_CPUPCH_TRST_L

XDP_CPUPCH_TMS
XDP_CPUPCH_TMS

XDP_CPUPCH_TDI
XDP_CPUPCH_TDI

TP_XDP_PCH_TCK

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

XDP_CPUPCH_TRST_L

XDP_CPUPCH_TMS

XDP_CPUPCH_TDI

TP_XDP_PCH_TCK

PAGE TITLE

1

TP-P5

PP1891

1

TP-P5

PP1892

1

TP-P5

PP1893

1

TP-P5

A

A

A

A

R1892

51

5%
1/20W
MF
201

2

SYNC_DATE=03/13/2017SYNC_MASTER=X589_CPU_CNL_Y

B

A

8

67

CPU/PCH Merged XDP

DRAWING NUMBER

051-05232

Apple Inc.

REVISION

2.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=DEBUG

35 4

IV ALL RIGHTS RESERVED

2

BRANCH

proto4b

PAGE

18 OF 152

SHEET

16 OF 86

1

SIZE

D

678

www.laptoprepairsecrets.com

3 245

1

D

B

PCH 38.4MHz Crystal

R1900

0

5%
MF

21

PCH_CLK38M4_XTALOUT_R

CRITICAL

Y1900

2.5X2.0-SM

38.4MHZ-10PPM-8PF-30OHM

1

3

15

PCH_CLK38M4_XTALOUT

IN

R1901

200K

1%

1/20W

MF

201

1/20W

0201

1

2

R1902

0

15

PCH_CLK38M4_XTALIN

OUT

5%

1/20W

MF

0201

21

PCH_CLK38M4_XTALIN_R

VCCIN VR EN and VCCST_PWRGD

CRITICAL

C1900

5.6PF

21

+/-0.1PF

25V

NP0-C0G

0201

2
4

CRITICAL

C1901

5.6PF

21

+/-0.1PF

25V

NP0-C0G

0201

EA

VCCSTG_OUT Discharge Circuit

Ensure VCCSTG_OUT <= VCCST during power-down (required at all times)

LTSpice Simulation

66

14 66

P1V05_VCCST_EN

IN

IN

CPU_C10_GATE_L

R1953

R1950

1/20W MF5%

NOSTUFF

0

NOSTUFF

0

21

02015% MF1/20W

21

PVCCSTG_DSCHG_EN_L

0201

DMN5L06VK-7

Q1950

SOT563

VER-3

2

PP3V3_G3H

75

PVCCSTG_DSCHG_EN

6

D

SG

1

R1951

100K

5%

1/20W

MF

201

PP1V05_VCCSTG_OUT

6 8 11 16

NOSTUFF

R1952

100K

1/20W

5%

MF

201

1

2

D

PVCCSTG_DSCHG

1

2

DMN5L06VK-7

NOSTUFF

1

C1950

47PF

5%
25V

2

C0G
0201

Q1950

SOT563

VER-3

5

3

D

SG

4

C

Generation

8 11 39 66 78

64

14 17 64 66 78

14 18

14 18 61

IN

IN

IN

IN

ALL_SYS_PWRGD

PM_SLP_S3_L

PM_RSMRST_L

1/20W 0201MF

PM_SLP_SUS_L

R1910

0

5%

21

R1911

0

5% 02011/20W MF

NOSTUFF

21

PP1V05_S0_CPU_VCCST

10%
16V

0201

1

2

1
3

B

6

C

GND

C1910

0.1UF

X5R-CERM

CPUVRENC

$J230GHUB/j230/mlb/sim/ltspice/vccstg_out_discharge_diodes_inc.asc

$J230GHUB/j230/mlb/sim/ltspice/vccstg_out_discharge_nxp.asc

F

52

VCCA

U1910

74AUP1G11

XSON6

4

Y

1

2

R1913

100K

5%
1/20W
MF
201

R1912

0

5%

1/20W

MF

0201

CPU_VR_EN

21

VCCST_PWRGD

OUT

OUT

57

14

SLP_S0# 1.8V Level Shifter

PP1V8_PRIM_PCH

75

BYPASS=U1930::5mm

10%

6.3V
0201

1

2

U1930

74AUP1G34GX

5

SOT1226

2

NC

1

NC

4

3

PM_SLP_S0_1V8_L

1

R1930

100K

5%
1/20W
MF
201

2

81 78 14

C1930

0.1UF

CERM-X5R

PM_SLP_S0_L

SoC Buffer Bypass

NOSTUFF

R1931

PM_SLP_S0_L

32

OUTIN

1/20W

5% MF 0201

21

PM_SLP_S0_1V8_L

0

C

B

C

PCH_PWROK Generation

74 42 18 14 13 5

14 17 64 66 78

39

IN

IN

PM_SLP_S3_L

PM_PCH_PWROK_SMC

PP3V3_S5

BYPASS=U1915::2MM

C1915

0.1UF

10%
16V

X5R-CERM

0201

1

2

NC

VCC

2

A Y

1

AND

B

5

NC

GND

U1915

74AUP1G08GF

6

SOT891

3

R1915

4

1

R1917

100K

5%
1/20W
MF
201

2

0

5%

1/20W

MF

0201

NOSTUFF

R1916

0

5%

1/20W

MF

0201

B

21

21

PM_PCH_PWROKPCHPWROK_R

OUT

14 18

G

VSS_268 GND Connection

6

IN

GND

A

D

32 14

DSW_PWROK 3.3V Level Shifter

PP3V3_S5

74

BYPASS=U1920::2MM

10%

6.3V
0201

1

2

1

2

U1920

74AUP1T97

5

SOT891

4

6

3

PM_PCH_DPWROK

1

R1920

100K

5%
1/20W
MF
201

2

SMC_DPWROK1V8

SMC_DPWROK1V8

MAKE_BASE=TRUE

1

2

C1920

0.1UF

CERM-X5R

R1922

100K

5%
1/20W
MF
201

OUTIN

CFG Boot StrapsH

CPU_CFG<13>

6 16

CPU_CFG<12>

6 16

CPU_CFG<10>

16 6

CPU_CFG<9>

6 16

CPU_CFG<8>

16 6

CPU_CFG<1>

16 6

CPU_CFG<0>

6 16

PPVCCIO_OUT

18 8

CPUCFG:STRAPS

1

R1976

1K

5%
1/20W
MF
201

2

CPUCFG:STRAPS

1

R1975

1K

5%
1/20W
MF
201

2

CPUCFG:STRAPS

1

R1974

1K

5%
1/20W
MF
201

2

CPUCFG:STRAPS

1

R1973

1K

5%
1/20W
MF
201

2

CPUCFG:STRAPS

1

R1972

1K

5%
1/20W
MF
201

2

CPUCFG:STRAPS

1

R1971

1K

5%
1/20W
MF
201

2

CPUCFG:STRAPS

1

R1970

1K

5%
1/20W
MF
201

2

BOM_COST_GROUP=CPU & CHIPSET

PAGE TITLE

Chipset Shared Support

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=06/08/2018SYNC_MASTER=CPU_CARD_ICL_Y

DRAWING NUMBER

051-05232

REVISION

2.0.0

BRANCH

proto4b

PAGE

19 OF 152

SHEET

17 OF 86

A

SIZE

D

8

67

35 4

2

1

678

www.laptoprepairsecrets.com

3 245

1

D

A E

PP3V3_S5

66 74

BYPASS=U2030::2MM

10%

6.3V

0201

1

2

1

2

U2030

74AUP1T97

5

SOT891

4

6

3

PLT_RST_3V3_LPLT_RST_L

1

R2030

100K

5%
1/20W
MF
201

2

23 78 39 18 14

OUTIN

C2030

0.1UF

CERM-X5R

SOC CLKREQ ControlPLTRST# 3.3V Level Shifter

17 14

18 17 14

PM_PCH_PWROK

IN

IN

PM_RSMRST_L

NOSTUFF

R2050

0

2 1

5% 1/20WMF

R2051

20K

2 1

5%MF 1/20W

0201

201

PP1V8_PRIM_PCH

32 75

PM_RSMRST_L_RC_SCB

1

C2051

0.022UF

10%

6.3V

2

X5R-CERM
0201

U2050

TS5A3166YZPR

C2

IN

XBGA

A2

V+

GND

C1

COM

NO

B1

A1

BYPASS=U2050::2MM

1

C2050

0.1UF

10%

35V

2

CER-X5R
0201

SOC_CLKREQ_BUF_L
SOC_CLKREQ_L

BI

BI

D

15

34

C

B

Miscellaneous Signal Aliases

32

IN

PCH_RTC_RESET_L

MAKE_BASE=TRUE

SMC_TOPBLK_SWP_L

GND

15

GND

15

NOSTUFF

R2008

1K

2 1

5%

1/20W

MF

201

DEBUG_CLKREQ_STRAP_L

DEBUG_CLKREQ_STRAP_L

DEBUG_CLKREQ_STRAP_L

GND

PCH_RTC_RESET_L

MAKE_BASE=TRUE

MAKE_BASE=TRUE

15 64 15

OUTIN

15 18 76

R2052

33

21

MF 2011/20W5%

SOC_CLKREQ_SW_EN_D

tau = RC = 20k * 0.022uF = 440us

F

MEM_OK Debug LED

16 13

IN

XDP_MEM_OK

DBG_LED

Debug LED Notes:

Q2060

2

G

S D

1

DMN5L06VK-7

SOT563

VER-5

D2050

SOD962-2

K A

PMEG3002ESF

MEM_YELLOW_LED

6

PP3V3_G3H

75 81

DBG_LED

R2061

261

1% 201MF1/20W

PCH latches SOC_CLKREQ_L boot strap 65us after RSMRST# de-assertion

R2060

0

21

1/20W 02015%

DBG_LED

PP3V3_G3H_DEBUGLED_MEM

MF

VOLTAGE=3.3V

A

DBG_LED

D2060

YEL-588NM-0.02A
LTST-C281KSKT-SM

K

21

MEM_YELLOW_LED_R

C

B

C

Miscellaneous Pull-Ups

78 39 18 14

5 13 14 17 42 74

PLT_RST_L

PP3V3_S5

R2010
R2011

R2016

R2012
R2013
R2014
R2015

100K
100K

100K

100K
100K
100K
100K

NOSTUFF

NOSTUFF

NOSTUFF

21
21

5% MF 2011/20W

21

21

5% 1/20W

21
21

5% 201MF1/20W

21

1/20W MF 2015%

1/20W MF 2015%

201MF5% 1/20W

MF1/20W 2015%

MF 201

PCH_WLAN_PERST_L

SOC_PERST_L

DEBUG_CLKREQ_STRAP_L

CPU Rev A only ??

USB_EXTA_OC_L
USB_EXTB_OC_L
USB_EXTC_OC_L
USB_EXTD_OC_L

OUT
OUT

OUT

OUT
OUT
OUT
OUT

15

15

15

15

Q2060

VF = 2.0V

IF = 20 mA
RLED = (VCC-VF)/IF
RLED = (3.3V-2.0V)/5mA = 261 Ohms

G H

BT Audio Sync Buf

NC

DBG_LED

NC

5

G

S D

4

WiFi Audio Sync Buf

DMN5L06VK-7

SOT563

VER-5

3

NC

B

30 29 28 6

32 6

76 18 15

PP1V8_PRIM_PCH

75

BYPASS=U2070::2MM

1

C2070

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

R2071

100K

5%
1/20W
MF
201

2

PP1V8_PRIM_PCH

75

BYPASS=U2070::2MM

1

C2080

0.1UF

10%

6.3V

2

U2070

74AUP1G126GX

5

X2SON5

2

A

OE

3

4

Y

1

1

R2072

100K

5%
1/20W
MF
201

2

5 30 29

OUTIN

78 30 29

IN

WLAN_AUDIO_SYNCBT_AUDIO_SYNC PCH_BT_AUDIO_SYNC

CERM-X5R
0201

1

R2081

100K

5%
1/20W
MF
201

2

2

A

U2080

74AUP1G126GX

5

X2SON5

4

Y

OE

1

3

PCH_WLAN_AUDIO_SYNC

1

R2082

100K

5%
1/20W
MF
201

2

OUT

5

A

D

PM_RSMRST Control

61 17 14

39

IN

IN

PM_SLP_SUS_L RSMRSTL_R
PM_RSMRST_R_L

NC

VCC

2

A Y

1

B

5

NC

GND

PP3V3_S5

74

U2001

74AUP1G08GF

6

SOT891

4

3

1

R2004

100K

5%
1/20W
MF
201

2

1/20W

R2001

0

5% 02011/20W

NOSTUFF

R2002

0

BYPASS=U2001::2MM

1

C2001

0.1UF

10%

35V

2

CER-X5R
0201

21

PM_RSMRST_L

MF

21

0201MF5%

OUT

78 39 18 14

PLT_RST_L

IN

78 39 18 14

IN

R2070

0

P3MM

SM
PP

P3MM

SM
PP

21

1

1

PPVCCIO_OUT

TP_CPU_PWRGD

17 8

14

BOM_COST_GROUP=CPU & CHIPSET

1/20W 5% 0201MF

I

18 17 14

Miscellaneous Probe Points

NOSTUFF

PP2000

PP2001

PLT_RST_L

R2080

0

21

0201

NOSTUFF

SYNC_MASTER=CARD_CPU_ICL_YN SYNC_DATE=06/08/2018

PAGE TITLE

MF5%1/20W

Chipset Project Support

SIZE

D

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

051-05232

REVISION

2.0.0

BRANCH

proto4b

PAGE

20 OF 152

SHEET

18 OF 86

A

8

67

35 4

2

1

678

www.laptoprepairsecrets.com

3 245

1

LPDDR4x Sub-Channels A & B

D

C

B

A

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

IN
IN

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

IN
IN

IN
IN

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

IN
IN

IN
IN

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

IN
IN

IN
IN

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

IN
IN

MEM_B_CKE<0>
MEM_B_CKE<1>

MEM_B_DQ_2<4>
MEM_B_DQ_2<5>
MEM_B_DQ_2<7>
MEM_B_DQ_2<6>
MEM_B_DQ_2<3>
MEM_B_DQ_2<1>
MEM_B_DQ_2<2>
MEM_B_DQ_2<0>
MEM_B_DQ_0<4>
MEM_B_DQ_0<0>
MEM_B_DQ_0<3>
MEM_B_DQ_0<7>
MEM_B_DQ_0<5>
MEM_B_DQ_0<1>
MEM_B_DQ_0<6>
MEM_B_DQ_0<2>

MEM_B_CLK_P
MEM_B_CLK_N

MEM_A_CKE<0>
MEM_A_CKE<1>

MEM_A_DQ_2<0>
MEM_A_DQ_2<3>
MEM_A_DQ_2<5>
MEM_A_DQ_2<6>
MEM_A_DQ_2<7>
MEM_A_DQ_2<1>
MEM_A_DQ_2<2>
MEM_A_DQ_2<4>
MEM_A_DQ_0<2>
MEM_A_DQ_0<5>
MEM_A_DQ_0<3>
MEM_A_DQ_0<7>
MEM_A_DQ_0<4>
MEM_A_DQ_0<0>
MEM_A_DQ_0<6>

MEM_A_CLK_P
MEM_A_CLK_N

MEM_B_CKE<0>
MEM_B_CKE<1>

MEM_B_DQ_3<0>
MEM_B_DQ_3<1>
MEM_B_DQ_3<2>
MEM_B_DQ_3<3>
MEM_B_DQ_3<4>
MEM_B_DQ_3<5>
MEM_B_DQ_3<6>
MEM_B_DQ_3<7>
MEM_B_DQ_1<0>
MEM_B_DQ_1<1>
MEM_B_DQ_1<2>
MEM_B_DQ_1<3>
MEM_B_DQ_1<4>
MEM_B_DQ_1<5>
MEM_B_DQ_1<6>
MEM_B_DQ_1<7>

MEM_B_CLK_P
MEM_B_CLK_N

MEM_A_CKE<0>
MEM_A_CKE<1>

MEM_A_DQ_3<6>
MEM_A_DQ_3<5>
MEM_A_DQ_3<4>
MEM_A_DQ_3<0>
MEM_A_DQ_3<3>
MEM_A_DQ_3<7>
MEM_A_DQ_3<1>
MEM_A_DQ_3<2>
MEM_A_DQ_1<0>
MEM_A_DQ_1<6>
MEM_A_DQ_1<5>
MEM_A_DQ_1<1>
MEM_A_DQ_1<3>
MEM_A_DQ_1<7>
MEM_A_DQ_1<4>
MEM_A_DQ_1<2>

MEM_A_CLK_P
MEM_A_CLK_N

F9
G8

B3
C2
E2
G2
D3
C4
E4

H5
B11
C12
E12
G12
D11
C10
E10

H9

E6

E8

Y9

W8

AD3
AC2
AA2

W2
AB3
AC4
AA4

V5

AD11
AC12
AA12

W12

AB11
AC10
AA10

V9

AA6
AA8

F23
G22

B17
C16
E16
G16
D17
C18
E18
H19
B25
C26
E26
G26
D25
C24
E24
H23

E20
E22

Y23
W22

AD17
AC16
AA16

W16

AB17
AC18
AA18

V19

AD25
AC26
AA26

W26

AB25
AC24
AA24

V23

AA20
AA22

CRITICAL

OMIT_TABLE

U2300

LPDDR4X-3200-64GBIT-18NM

FBGA

K3UH7H70MM-JGCJ

CKE0_A

CKE1_A

DQ0_A
DQ1_A
DQ2_A
DQ3_A
DQ4_A
DQ5_A
DQ6_A
DQ7_A
DQ8_A
DQ9_A
DQ10_A
DQ11_A
DQ12_A
DQ13_A
DQ14_A

CK_T_A
CK_C_A

CKE0_B

CKE1_B

DQ0_B
DQ1_B
DQ2_B
DQ3_B
DQ4_B
DQ5_B
DQ6_B
DQ7_B
DQ8_B
DQ9_B
DQ10_B
DQ11_B
DQ12_B
DQ13_B
DQ14_B
DQ15_B

CK_T_B
CK_C_B

CKE0_C

CKE1_C

DQ0_C
DQ1_C
DQ2_C
DQ3_C
DQ4_C
DQ5_C
DQ6_C
DQ7_C
DQ8_C
DQ9_C
DQ10_C
DQ11_C
DQ12_C
DQ13_C
DQ14_C

DQ15_C

CK_T_C
CK_C_C

CKE1_D

DQ0_D
DQ1_D
DQ2_D
DQ3_D
DQ4_D
DQ5_D
DQ6_D
DQ7_D
DQ8_D
DQ9_D
DQ10_D
DQ11_D
DQ12_D
DQ13_D
DQ14_D
DQ15_D

CK_T_D
CK_C_D

SYM 1 OF 4

DDRA

ODT_CA_A

DQS0_T_A

DQS0_C_A

DQS1_T_A

DQS1_C_ADQ15_A

DDRB

ODT_CA_B

DQS0_T_B

DQS0_C_B

DQS1_T_B
DQS1_C_B

DDRC

ODT_CA_C

DQS0_T_C

DQS0_C_C

DQS1_T_C
DQS1_C_C

DDRD

ODT_CA_D

DQS0_T_D

DQS0_C_D

DQS1_T_D
DQS1_C_D

CS0_A
CS1_A

DMI0_A
DMI1_A

CA0_A

CA1_A
CA2_A
CA3_A
CA4_A
CA5_A

ZQ0_A

ZQ1_A

CS0_B

CS1_B

DMI0_B
DMI1_B

CA0_B

CA1_B
CA2_B
CA3_B
CA4_B
CA5_B

RESET*

CS0_C

CS1_C

DMI0_C
DMI1_C

CA0_C

CA1_C
CA2_C
CA3_C
CA4_C
CA5_C

ZQ0_C

ZQ1_C

CS0_DCKE0_D

CS1_D

DMI0_D
DMI1_D

CA0_D

CA1_D
CA2_D
CA3_D
CA4_D
CA5_D

G6
F5

H3
H11

J4

B5
D5
C6
C8
B9
D9

F3
G4
F11
G10

J10
J12

W6
Y5

V3
V11

U4

AD5
AB5
AC6
AC8
AD9
AB9

Y3
W4
Y11
W10

U12

G20
F19

H17
H25

J18

B19
D19
C20
C22
B23
D23

F17
G18
F25
G24

J24
J26

W20
Y19

V17
V25

U18

AD19
AB19
AC20
AC22
AD23
AB23

Y17
W18
Y25
W24

MEM_B_CS_L<0>
MEM_B_CS_L<1>

MEM_B_CA<0>
MEM_B_CA<1>
MEM_B_CA<2>
MEM_B_CA<3>
MEM_B_CA<4>
MEM_B_CA<5>

MEM_B_DQS_P<2>
MEM_B_DQS_N<2>
MEM_B_DQS_P<0>
MEM_B_DQS_N<0>

MEM_1A_ZQ<0>
MEM_1A_ZQ<1>

MEM_A_CS_L<0>
MEM_A_CS_L<1>

MEM_A_CA<0>
MEM_A_CA<1>
MEM_A_CA<2>
MEM_A_CA<3>
MEM_A_CA<4>
MEM_A_CA<5>

MEM_A_DQS_P<2>
MEM_A_DQS_N<2>
MEM_A_DQS_P<0>
MEM_A_DQS_N<0>MEM_A_DQ_0<1>

MEM_RESET_L

MEM_B_CS_L<0>
MEM_B_CS_L<1>

MEM_B_CA<0>
MEM_B_CA<1>
MEM_B_CA<2>
MEM_B_CA<3>
MEM_B_CA<4>
MEM_B_CA<5>

MEM_B_DQS_P<3>
MEM_B_DQS_N<3>
MEM_B_DQS_P<1>
MEM_B_DQS_N<1>

MEM_1C_ZQ<0>
MEM_1C_ZQ<1>

MEM_A_CS_L<0>
MEM_A_CS_L<1>

MEM_A_CA<0>
MEM_A_CA<1>
MEM_A_CA<2>
MEM_A_CA<3>
MEM_A_CA<4>
MEM_A_CA<5>

MEM_A_DQS_P<3>
MEM_A_DQS_N<3>
MEM_A_DQS_P<1>
MEM_A_DQS_N<1>

IN
IN

IN
IN
IN
IN
IN
IN

BI
BI
BI
BI

IN
IN

IN
IN
IN
IN
IN
IN

BI
BI
BI
BI

IN

IN
IN

IN
IN
IN
IN
IN
IN

BI
BI
BI
BI

IN
IN

IN
IN
IN
IN
IN
IN

BI
BI
BI
BI

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

CRITICAL

OMIT_TABLE

U2300

LPDDR4X-3200-64GBIT-18NM

FBGA

PP1V8_S3

19 20 65 74

A2

VDD1

B2

VDD1

AD2

VDD1

AE2

VDD1

A12

VDD1

B12

VDD1

AD12
AE12

AD16
AE16

AD26
AE26

1

R2300

240

1%
1/20W
MF
201

2

PP0V6_S3

1

R2301

240

1%
1/20W
MF
201

2

19 20 65 75

NC
NC

PLACE_NEAR=U2300.J10:12.7mm
PLACE_NEAR=U2300.J12:12.7mm

NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC

20 7

1

R2350

240

1%
1/20W
MF
201

2

PP0V6_S3

1

R2351

240

1%
1/20W
MF
201

2

19 20 65 75

PP0V6_S3

19 20 65 75

A16
B16

A26
B26

J2
J3
J5
U5
J6
U6
J8
U8
J9

U9
J16
J17
J19
U19
J20
U20
J22
U22
J23
U23
U26

VDD1
VDD1
VDD1
VDD1
VDD1
VDD1
VDD1
VDD1
VDD1
VDD1

NC
NC

NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC

CRITICAL

20%

6.3V
X5R

1

2

PLACE_NEAR=U2300.J24:12.7mm
PLACE_NEAR=U2300.J26:12.7mm

PP1V1_S3

19 20 65 75

C2300

1.0UF

0201-1

CRITICAL

20%

6.3V
X5R

1

2

PP1V8_S3

19 20 65 74

C2320

1.0UF

0201-1

CRITICAL

20%

6.3V
X5R

1

2

C2340

1.0UF

0201-1

K3UH7H70MM-JGCJ

SYM 2 OF 4

CRITICAL

C2301

1.0UF

20%

6.3V
X5R

0201-1

CRITICAL

C2321

1.0UF

20%

6.3V
X5R

0201-1

CRITICAL

C2341

1.0UF

20%

6.3V
X5R

0201-1

CRITICAL

1

C2302

2

CRITICAL

1

C2322

2

CRITICAL

1

C2342

2

1.0UF

20%

6.3V
X5R

0201-1

1.0UF

20%

6.3V
X5R

0201-1

10UF

20%

6.3V

CERM
0402

VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2

CRITICAL

1

2

CRITICAL

1

2

CRITICAL

1

2

PP1V1_S3

A6
B6
D6
F6
H6
V6
Y6
AB6
AD6
AE6
A8
B8
D8
F8
H8
V8
Y8
AB8
AD8
AE8
A20
B20
D20
F20
H20
V20
Y20
AB20
AD20
AE20
A22
B22
D22
F22
H22
V22
Y22
AB22
AD22
AE22

C2303

1.0UF

20%

6.3V
X5R

0201-1

C2323

1.0UF

20%

6.3V
X5R

0201-1

C2343

10UF

20%

6.3V

CERM
0402

CRITICAL

1

C2304

1.0UF

2

CRITICAL

1

C2324

1.0UF

2

CRITICAL

1

C2344

2

20%

6.3V
X5R

0201-1

20%

6.3V
X5R

0201-1

10UF

20%

6.3V

CERM
0402

19 20 65 75

CRITICAL

1

C2305

1.0UF

2

CRITICAL

1

C2325

1.0UF

2

CRITICAL

1

C2345

2

AA3
AA5

AA9
AA11
AA17
AA19
AA23
AA25

AB2

AB4
AB10
AB12
AB16
AB18
AB24
AB26

AC3

AC5

AC9
AC11
AC17
AC19
AC23
AC25

AD4
AD10
AD18
AD24

B4
B10
B18
B24

C3

C5

C9
C11
C17
C19
C23
C25

D2

D4
D10
D12
D16
D18
D24
D26

E3

E5

E9
E11
E17
E19
E23
E25

F2

20%

6.3V
X5R

0201-1

20%

6.3V
X5R

0201-1

10UF

20%

6.3V

CERM
0402

LPDDR4X-3200-64GBIT-18NM

CRITICAL

1

C2306

1.0UF

2

CRITICAL

1

C2326

1.0UF

2

1

2

CRITICAL

OMIT_TABLE

U2300

FBGA

K3UH7H70MM-JGCJ

SYM 4 OF 4

CRITICAL

1

20%

6.3V
2

X5R

0201-1

CRITICAL

1

20%

6.3V
2

X5R

0201-1

C2307

1.0UF

20%

6.3V
X5R

0201-1

C2327

1.0UF

20%

6.3V
X5R

0201-1

VSSVSS

CRITICAL

1

C2308

2

CRITICAL

1

C2328

2

F4
F10
F12
F16
F18
F24
F26
G3
G5
G9
G11
G17
G19
G23
G25
H2
H4
H10
H12
H16
H18
H24
H26
J11
J25
U2
U3
U10
U11
U16
U17
U24
U25
V2
V4
V10
V12
V16
V18
V24
V26
W3
W5
W9
W11
W17
W19
W23
W25
Y2
Y4
Y10
Y12
Y16
Y18
Y24
Y26

10UF

20%

6.3V
CERM
0402

10UF

20%

6.3V
CERM
0402

PP0V6_S3

19 20 65 75

CRITICAL

1

C2309

2

CRITICAL

1

C2329

2

CRITICAL

1

C2310

10UF

20%

6.3V
2

CERM
0402

CRITICAL

1

C2330

10UF

20%

6.3V
2

CERM
0402

SYNC_MASTER=J140

PAGE TITLE

LPDDR4x Sub-Channels A & B

10UF

20%

6.3V
CERM
0402

10UF

20%

6.3V
CERM
0402

A1
B1
C1
D1
E1
F1
G1
H1
J1
U1
V1
W1

Y1
AA1
AB1
AC1
AD1
AE1

A3
AE3

A4
AE4

A5
AE5

A9
AE9
A10

AE10

A11

AE11

A13
B13
C13
D13
E13
F13
G13
H13
J13
U13
V13
W13
Y13

AA13
AB13
AC13
AD13
AE13

CRITICAL

1

2

CRITICAL

1

2

LPDDR4X-3200-64GBIT-18NM

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

C2311

10UF

20%

6.3V
CERM
0402

C2331

10UF

20%

6.3V
CERM
0402

Apple Inc.

CRITICAL

OMIT_TABLE

U2300

FBGA

K3UH7H70MM-JGCJ

SYM 3 OF 4

1

2

1

2

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

SYNC_DATE=08/23/2018

DRAWING NUMBER

051-05232

REVISION

A15
B15
C15
D15
E15
F15
G15
H15
J15
U15
V15
W15
Y15
AA15
AB15
AC15
AD15
AE15
A17
AE17
A18
AE18
A19
AE19
A23
AE23
A24
AE24
A25
AE25
A27
B27
C27
D27
E27
F27
G27
H27
J27
U27
V27
W27
Y27
AA27
AB27
AC27
AD27
AE27

D

C

B

A

SIZE

D

2.0.0

BRANCH

proto4b

PAGE

23 OF 152

SHEET

19 OF 86

BOM_COST_GROUP=DRAM

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

8

67

35 4

2

1

678

www.laptoprepairsecrets.com

3 245

1

LPDDR4x Sub-Channels C & D

D

C

B

A

CRITICAL

OMIT_TABLE

U2500

LPDDR4X-3200-64GBIT-18NM

FBGA

77

77

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

77

77

77

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

77

77

77

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

77

77

77

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77

BI

77 77

BI IN

77

BI

77

BI

77

BI

77

BI

77

BI

77

77

MEM_D_CKE<0>

IN

MEM_D_CKE<1>

IN

MEM_D_DQ_0<5>
MEM_D_DQ_0<3>
MEM_D_DQ_0<4>
MEM_D_DQ_0<1>
MEM_D_DQ_0<7>
MEM_D_DQ_0<6>
MEM_D_DQ_0<0>
MEM_D_DQ_0<2>
MEM_D_DQ_2<6>
MEM_D_DQ_2<3>
MEM_D_DQ_2<5>
MEM_D_DQ_2<2>
MEM_D_DQ_2<7>
MEM_D_DQ_2<4>
MEM_D_DQ_2<0>

MEM_D_CLK_P

IN

MEM_D_CLK_N

IN

MEM_C_CKE<0>

IN

MEM_C_CKE<1>

IN

MEM_C_DQ_0<0>
MEM_C_DQ_0<1>
MEM_C_DQ_0<2>
MEM_C_DQ_0<3>
MEM_C_DQ_0<4>
MEM_C_DQ_0<5>
MEM_C_DQ_0<6>
MEM_C_DQ_0<7>
MEM_C_DQ_2<0>
MEM_C_DQ_2<1>
MEM_C_DQ_2<2>
MEM_C_DQ_2<3>
MEM_C_DQ_2<4>
MEM_C_DQ_2<5>
MEM_C_DQ_2<6>
MEM_C_DQ_2<7>

MEM_C_CLK_P

IN

MEM_C_CLK_N

IN

MEM_D_CKE<0>

IN

MEM_D_CKE<1>

IN

MEM_D_DQ_1<2>
MEM_D_DQ_1<3>
MEM_D_DQ_1<6>
MEM_D_DQ_1<7>
MEM_D_DQ_1<5>
MEM_D_DQ_1<0>
MEM_D_DQ_1<4>
MEM_D_DQ_1<1>
MEM_D_DQ_3<5>
MEM_D_DQ_3<4>
MEM_D_DQ_3<1>
MEM_D_DQ_3<3>
MEM_D_DQ_3<2>
MEM_D_DQ_3<0>
MEM_D_DQ_3<6>
MEM_D_DQ_3<7>

MEM_D_CLK_P

IN

MEM_D_CLK_N

IN

MEM_C_CKE<0>

IN

MEM_C_CKE<1>

IN

MEM_C_DQ_1<3>
MEM_C_DQ_1<4>
MEM_C_DQ_1<2>
MEM_C_DQ_1<0>
MEM_C_DQ_1<1>
MEM_C_DQ_1<5>
MEM_C_DQ_1<6>
MEM_C_DQ_1<7>
MEM_C_DQ_3<7>
MEM_C_DQ_3<5>
MEM_C_DQ_3<4>
MEM_C_DQ_3<2>
MEM_C_DQ_3<3>
MEM_C_DQ_3<6>
MEM_C_DQ_3<0>
MEM_C_DQ_3<1>

MEM_C_CLK_P

IN

MEM_C_CLK_N

IN

F9
G8

B3
C2
E2
G2
D3
C4
E4

H5
B11
C12
E12
G12
D11
C10
E10

H9

E6

E8

Y9

W8

AD3
AC2
AA2

W2
AB3
AC4
AA4

V5

AD11
AC12
AA12

W12

AB11
AC10
AA10

V9

AA6
AA8

F23
G22

B17
C16
E16
G16
D17
C18
E18
H19
B25
C26
E26
G26
D25
C24
E24
H23

E20
E22

Y23
W22

AD17
AC16
AA16

W16

AB17
AC18
AA18

V19

AD25
AC26
AA26

W26

AB25
AC24
AA24

V23

AA20
AA22

CKE0_A

CKE1_A

DQ0_A
DQ1_A
DQ2_A
DQ3_A
DQ4_A
DQ5_A
DQ6_A
DQ7_A
DQ8_A
DQ9_A
DQ10_A
DQ11_A
DQ12_A
DQ13_A
DQ14_A

CK_T_A
CK_C_A

CKE0_B

CKE1_B

DQ0_B
DQ1_B
DQ2_B
DQ3_B
DQ4_B
DQ5_B
DQ6_B
DQ7_B
DQ8_B
DQ9_B
DQ10_B
DQ11_B
DQ12_B
DQ13_B
DQ14_B
DQ15_B

CK_T_B
CK_C_B

CKE0_C

CKE1_C

DQ0_C
DQ1_C
DQ2_C
DQ3_C
DQ4_C
DQ5_C
DQ6_C
DQ7_C
DQ8_C
DQ9_C
DQ10_C
DQ11_C
DQ12_C
DQ13_C
DQ14_C

DQ15_C

CK_T_C
CK_C_C

CKE1_D

DQ0_D
DQ1_D
DQ2_D
DQ3_D
DQ4_D
DQ5_D
DQ6_D
DQ7_D
DQ8_D
DQ9_D
DQ10_D
DQ11_D
DQ12_D
DQ13_D
DQ14_D
DQ15_D

CK_T_D
CK_C_D

K3UH7H70MM-JGCJ

SYM 1 OF 4

DDRA

DDRB

DDRC

DDRD

CS0_A
CS1_A

DMI0_A
DMI1_A

ODT_CA_A

CA0_A

CA1_A
CA2_A
CA3_A
CA4_A
CA5_A

DQS0_T_A

DQS0_C_A

DQS1_T_A

DQS1_C_ADQ15_A

ZQ0_A

ZQ1_A

CS0_B

CS1_B

DMI0_B
DMI1_B

ODT_CA_B

CA0_B

CA1_B
CA2_B
CA3_B
CA4_B
CA5_B

DQS0_T_B

DQS0_C_B

DQS1_T_B
DQS1_C_B

RESET*

CS0_C

CS1_C

DMI0_C
DMI1_C

ODT_CA_C

CA0_C

CA1_C
CA2_C
CA3_C
CA4_C
CA5_C

DQS0_T_C

DQS0_C_C

DQS1_T_C
DQS1_C_C

ZQ0_C

ZQ1_C

CS0_DCKE0_D

CS1_D

DMI0_D
DMI1_D

ODT_CA_D

CA0_D

CA1_D
CA2_D
CA3_D
CA4_D
CA5_D

DQS0_T_D

DQS0_C_D

DQS1_T_D
DQS1_C_D

G6
F5

H3
H11

J4

B5
D5
C6
C8
B9
D9

F3
G4
F11
G10

J10
J12

W6
Y5

V3
V11

U4

AD5
AB5
AC6
AC8
AD9
AB9

Y3
W4
Y11
W10

U12

G20
F19

H17
H25

J18

B19
D19
C20
C22
B23
D23

F17
G18
F25
G24

J24
J26

W20
Y19

V17
V25

U18

AD19
AB19
AC20
AC22
AD23
AB23

Y17
W18
Y25
W24

MEM_D_CS_L<0>
MEM_D_CS_L<1>

MEM_D_CA<0>
MEM_D_CA<1>
MEM_D_CA<2>
MEM_D_CA<3>
MEM_D_CA<4>
MEM_D_CA<5>

MEM_D_DQS_P<0>
MEM_D_DQS_N<0>
MEM_D_DQS_P<2>
MEM_D_DQS_N<2>MEM_D_DQ_2<1>

MEM_2A_ZQ<0>
MEM_2A_ZQ<1>

MEM_C_CS_L<0>
MEM_C_CS_L<1>

MEM_C_CA<0>
MEM_C_CA<1>
MEM_C_CA<2>
MEM_C_CA<3>
MEM_C_CA<4>
MEM_C_CA<5>

MEM_C_DQS_P<0>
MEM_C_DQS_N<0>
MEM_C_DQS_P<2>
MEM_C_DQS_N<2>

MEM_RESET_L

MEM_D_CS_L<0>
MEM_D_CS_L<1>

MEM_D_CA<0>
MEM_D_CA<1>
MEM_D_CA<2>
MEM_D_CA<3>
MEM_D_CA<4>
MEM_D_CA<5>

MEM_D_DQS_P<1>
MEM_D_DQS_N<1>
MEM_D_DQS_P<3>
MEM_D_DQS_N<3>

MEM_2C_ZQ<0>
MEM_2C_ZQ<1>

MEM_C_CS_L<0>
MEM_C_CS_L<1>

MEM_C_CA<0>
MEM_C_CA<1>
MEM_C_CA<2>
MEM_C_CA<3>
MEM_C_CA<4>
MEM_C_CA<5>

MEM_C_DQS_P<1>
MEM_C_DQS_N<1>
MEM_C_DQS_P<3>
MEM_C_DQS_N<3>

IN
IN

IN
IN
IN
IN
IN
IN

BI
BI
BI
BI

IN
IN

IN
IN
IN
IN
IN
IN

BI
BI
BI
BI

IN

IN
IN

IN
IN
IN
IN
IN
IN

BI
BI
BI
BI

IN
IN

IN
IN
IN
IN
IN

BI
BI
BI
BI

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

CRITICAL

OMIT_TABLE

U2500

LPDDR4X-3200-64GBIT-18NM

FBGA

PP1V8_S3

19 20 65 74

A2

VDD1

B2

VDD1

AD2

VDD1

AE2

VDD1

A12

VDD1

B12

VDD1

AD12
AE12

AD16
AE16

AD26
AE26

1

R2500

240

1%
1/20W
MF
201

2

PP0V6_S3

1

R2501

240

1%
1/20W
MF
201

2

19 20 65 75

NC
NC

PLACE_NEAR=U2500.J10:12.7mm
PLACE_NEAR=U2500.J12:12.7mm

NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC

19 7

1

R2550

240

1%
1/20W
MF
201

2

PP0V6_S3

1

R2551

240

1%
1/20W
MF
201

2

19 20 65 75

PP0V6_S3

19 20 65 75

A16
B16

A26
B26

J2
J3
J5
U5
J6
U6
J8
U8
J9

U9
J16
J17
J19
U19
J20
U20
J22
U22
J23
U23
U26

VDD1
VDD1
VDD1
VDD1
VDD1
VDD1
VDD1
VDD1
VDD1
VDD1

NC
NC

NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC

CRITICAL

20%

6.3V
X5R

1

2

PLACE_NEAR=U2500.J24:12.7mm
PLACE_NEAR=U2500.J26:12.7mm

PP1V1_S3

19 20 65 75

C2500

1.0UF

0201-1

CRITICAL

20%

6.3V
X5R

1

2

PP1V8_S3

19 20 65 74

C2520

1.0UF

0201-1

CRITICAL

20%

6.3V
X5R

1

2

C2540

1.0UF

0201-1

K3UH7H70MM-JGCJ

SYM 2 OF 4

CRITICAL

C2501

1.0UF

20%

6.3V
X5R

0201-1

CRITICAL

C2521

1.0UF

20%

6.3V
X5R

0201-1

C2541

1.0UF

20%

6.3V
X5R

0201-1

CRITICAL

1

C2502

2

CRITICAL

1

C2522

2

CRITICALCRITICAL

1

C2542

2

1.0UF

20%

6.3V
X5R

0201-1

1.0UF

20%

6.3V
X5R

0201-1

10UF

20%

6.3V

CERM
0402

VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2

CRITICAL

1

2

CRITICAL

1

2

CRITICAL

1

2

PP1V1_S3

A6
B6
D6
F6
H6
V6
Y6
AB6
AD6
AE6
A8
B8
D8
F8
H8
V8
Y8
AB8
AD8
AE8
A20
B20
D20
F20
H20
V20
Y20
AB20
AD20
AE20
A22
B22
D22
F22
H22
V22
Y22
AB22
AD22
AE22

C2503

1.0UF

20%

6.3V
X5R

0201-1

C2523

1.0UF

20%

6.3V
X5R

0201-1

C2543

10UF

20%

6.3V

CERM
0402

1

C2504

1.0UF

2

CRITICAL

1

C2524

1.0UF

2

CRITICAL

1

C2544

2

20%

6.3V
X5R

0201-1

20%

6.3V
X5R

0201-1

10UF

20%

6.3V

CERM
0402

19 20 65 75

CRITICALCRITICAL

1

C2505

1.0UF

2

CRITICAL

1

C2525

1.0UF

2

CRITICAL

1

C2545

2

AA3
AA5

AA9
AA11
AA17
AA19
AA23
AA25

AB2

AB4
AB10
AB12
AB16
AB18
AB24
AB26

AC3

AC5

AC9
AC11
AC17
AC19
AC23
AC25

AD4
AD10
AD18
AD24

B4
B10
B18
B24

C3

C5

C9
C11
C17
C19
C23
C25

D2

D4
D10
D12
D16
D18
D24
D26

E3

E5

E9
E11
E17
E19
E23
E25

F2

20%

6.3V
X5R

0201-1

20%

6.3V
X5R

0201-1

10UF

20%

6.3V

CERM
0402

LPDDR4X-3200-64GBIT-18NM

CRITICAL

1

C2506

1.0UF

2

CRITICAL

1

C2526

1.0UF

2

1

2

CRITICAL

OMIT_TABLE

U2500

FBGA

K3UH7H70MM-JGCJ

SYM 4 OF 4

CRITICAL

1

20%

6.3V
2

X5R

0201-1

CRITICAL

1

20%

6.3V
2

X5R

0201-1

C2507

1.0UF

20%

6.3V
X5R

0201-1

C2527

1.0UF

20%

6.3V
X5R

VSSVSS

CRITICAL

1

C2508

2

CRITICAL

1

C2528

2

F4
F10
F12
F16
F18
F24
F26
G3
G5
G9
G11
G17
G19
G23
G25
H2
H4
H10
H12
H16
H18
H24
H26
J11
J25
U2
U3
U10
U11
U16
U17
U24
U25
V2
V4
V10
V12
V16
V18
V24
V26
W3
W5
W9
W11
W17
W19
W23
W25
Y2
Y4
Y10
Y12
Y16
Y18
Y24
Y26

10UF

20%

6.3V
CERM
0402

10UF

20%

6.3V
CERM
04020201-1

PP0V6_S3

19 20 65 75

CRITICAL

1

C2509

2

CRITICAL

1

C2529

2

CRITICAL

OMIT_TABLE

U2500

LPDDR4X-3200-64GBIT-18NM

FBGA

K3UH7H70MM-JGCJ

A1

VDDQ

B1

VDDQ

C1

VDDQ

D1

VDDQ

E1

VDDQ

F1

VDDQ

G1

VDDQ

H1

VDDQ

J1

VDDQ

U1

VDDQ

V1

VDDQ

W1

VDDQ

Y1

VDDQ

AA1

VDDQ

AB1

VDDQ

AC1

VDDQ

AD1

VDDQ

AE1

VDDQ

A3

VDDQ

AE3

VDDQ

A4

VDDQ

AE4

VDDQ

A5

VDDQ

AE5

VDDQ

A9

VDDQ

AE9

VDDQ

A10

VDDQ

AE10

AE11

AA13
AB13
AC13
AD13
AE13

CRITICAL

1

C2510

10UF

20%

6.3V
CERM
0402

2

10UF

20%

6.3V
CERM
0402

CRITICAL

1

C2530

10UF

20%

6.3V
2

CERM
0402

SYNC_MASTER=J140 SYNC_DATE=08/23/2018

PAGE TITLE

10UF

20%

6.3V
CERM
0402

VDDQ

A11

VDDQ
VDDQ

A13

VDDQ

B13

VDDQ

C13

VDDQ

D13

VDDQ

E13

VDDQ

F13

VDDQ

G13

VDDQ

H13

VDDQ

J13

VDDQ

U13

VDDQ

V13

VDDQ

W13

VDDQ

Y13

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

CRITICAL

1

C2511

2

CRITICAL

1

C2531

2

10UF

20%

6.3V
CERM
0402

10UF

20%

6.3V
CERM
0402

SYM 3 OF 4

1

2

1

2

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

A15
B15
C15
D15
E15
F15
G15
H15
J15
U15
V15
W15
Y15
AA15
AB15
AC15
AD15
AE15
A17
AE17
A18
AE18
A19
AE19
A23
AE23
A24
AE24
A25
AE25
A27
B27
C27
D27
E27
F27
G27
H27
J27
U27
V27
W27
Y27
AA27
AB27
AC27
AD27
AE27

LPDDR4x Sub-Channels C & D

SIZE

D

Apple Inc.

DRAWING NUMBER

051-05232

REVISION

D

C

B

A

2.0.0

BRANCH

proto4b

PAGE

25 OF 152

SHEET

20 OF 86

BOM_COST_GROUP=DRAM

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

8

67

35 4

2

1

D

www.laptoprepairsecrets.com

138S00035 4

CAP,CER,20UF,20%,2.5V,X6S,HRZTL,0402

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

C2862,C2863,C2864,C2865,C2866,C2867,C2868,C2869

CRITICAL

678

TABLE_5_HEAD

BOM OPTIONCRITICAL

TABLE_5_ITEM

3 245

1

U2800

BURNSIDE-BRIDGE

USBC_HSX_R2D_P<1>

21

USBC_HSX_R2D_N<1>

21

J1
J2

ASSRXP1
ASSRXN1

BGA

SYM 1 OF 2

BSSRXP1
BSSRXN1

J12
J11

USBC_X_D2R_P<1>

USBC_X_D2R_N<1>

BI
BI

26

26

CRITICAL

USBC_HSX_R2D_P<2>

21

USBC_HSX_R2D_N<2>

21

C1
C2

ASSRXP2
ASSRXN2

OMIT_TABLE

BSSRXP2
BSSRXN2

C12
C11

USBC_X_D2R_P<2>
USBC_X_D2R_N<2>

BI
BI

26

26

D

USBC_HSX_D2R_P<1>

21

USBC_HSX_D2R_N<1>

21

G1
G2

ASSTXP1
ASSTXN1

BSSTXP1
BSSTXN1

G12
G11

USBC_X_R2D_CR_P<1>

USBC_X_R2D_CR_N<1>

OUT
OUT

26

26

C

USBC_HSX_D2R_P<2>

21

USBC_HSX_D2R_N<2>

21

23

BI

23

BI

USBC HIGH-SPEED 1 AC COUPLING

GND_VOID=TRUE

5

IN

5

IN

5

BI

5

BI

USBC_HSX_R2D_C_P<1>

GND_VOID=TRUE

USBC_HSX_R2D_C_N<1>

GND_VOID=TRUE

USBC_HSX_D2R_C_P<1>

GND_VOID=TRUE

USBC_HSX_D2R_C_N<1>

C2820

0.22UF

C2821

0.22UF

C2822

0.22UF

C2823

0.22UF

GND_VOID=TRUE

5

IN

5

IN

5

BI

5

BI

USBC_HSX_R2D_C_P<2> USBC_HSX_R2D_P<2>

GND_VOID=TRUE

USBC_HSX_R2D_C_N<2>

GND_VOID=TRUE

USBC_HSX_D2R_C_P<2>

GND_VOID=TRUE

USBC_HSX_D2R_C_N<2>

C2824

0.22UF

C2825

0.22UF

C2826

0.22UF

C2827

0.22UF

21
X5R

21
20%

X5R
21

20%
X5R

21
20% 0201

X5R
21

20%
X5R

21
20% 0201

X5R
21

20%
X5R

21
20%

X5R

USBC_HSX_R2D_P<1>

020120%

6.3V

USBC_HSX_R2D_N<1>

0201

6.3V

USBC_HSX_D2R_P<1>

0201

6.3V

USBC_HSX_D2R_N<1>

6.3V

0201

6.3V

USBC_HSX_R2D_N<2>

6.3V

USBC_HSX_D2R_P<2>

0201

6.3V

USBC_HSX_D2R_N<2>

0201

6.3V

21

21

21

21

21

21

21

21

23

23

OUT

XDP_LSX_TBTA_R2P

IN

XDP_LSX_TBTA_P2R

NOSTUFF

R2808

20K

1/20W

5%
MF

201

24 23

24 23

24 23

23

47

IN

BI
BI

IN

OUT

1

2

R2809

20K

5%

1/20W

MF

201

1

2

USBC_HSX_AUXCH_C_P
USBC_HSX_AUXCH_C_N

I2C_UPC_X_INTM_L
I2C_UPC_X_SCLM

I2C_UPC_X_SDAM
TBT_X_GPIO_5

21

TBT_X_GPIO_6

21

TBT_X_FLASH_SHARE_EN

21

TBT_X_FLASH_MSTR_H_SLV_L
TBT_X_GPIO_12

21

TBT_X_THERM_D_P

TBT_X_XTAL25M_IN

21

TBT_X_XTAL25M_OUT

21

E1
E2

L8
M8

L7

A10

C9
E7

B9
A8
A4
A5
A6

M11

L9
M9

L12
A11

ASSTXP2
ASSTXN2

PA_AUX_P
PA_AUX_N

PA_LSTX_SBU1
PA_LSRX_SBU2

I2C_INT
I2C_SCL
I2C_SDA

POC_GPIO_5
POC_GPIO_6
POC_GPIO_10
POC_GPIO_11
POC_GPIO_12

THERMDA

XTAL_25_IN
XTAL_25_OUT

MONDC_SVR
MONDC

INTERNAL CAPS,

PU, PD

To SPI Flash

TEST_PWR_GOOD

BSSTXP2
BSSTXN2

BSBU1
BSBU2

PERST*
RESET*

TDI
TMS
TCK
TDO

EE_DI

EE_DO
EE_CS*
EE_CLK

TEST_EN

RBIAS
RSENSE

ATEST_P
ATEST_N

E12
E11

M10
L10

B8M7
L11

A3
C3
B5
C5

C6
B4
B6
C7

B11
B3

L4
L5

A1
A2

USBC_X_R2D_CR_P<2>
USBC_X_R2D_CR_N<2>

USBC_X_AUXLSX_P
USBC_X_AUXLSX_N

TBT_XT_PERST_L

USBC_X_RESET_L

JTAG_ISP_TDI

JTAG_TBT_X_TMS

JTAG_ISP_TCK
JTAG_ISP_TDO

SPI_TBT_X_MOSI
SPI_TBT_X_MISO
SPI_TBT_X_CS_L

SPI_TBT_X_CLK

TBT_X_TEST_PWR_GOOD

TBT_X_RBIAS

TBT_X_RSENSE

NC
NC

OUT
OUT

BI
BI

IN
IN

IN
IN
IN

OUT

OUT

IN
OUT
OUT

26

26

24

24

23

27

23

23

23

23

23

23

23

23

2 1

4.75K

0.5%
0201

PLACE_NEAR=U2800.L5:2MM
PLACE_NEAR=U2800.L4:2MM

1/20W TF

R2807

R2806

100

5%

1/20W

MF

201

1

C

2

B

A

PP0V9_TBT_X_SVR

21

CRITICAL

NOSTUFF

1

C2869

20UF

20%

2.5V

2

X6S-CERM
0402-1

NOSTUFF

TBT_X_XTAL25M_OUT_R

5%

25V

C0G

0201
0201

C0G

25V

5%

1

2

2

C2802

20PF

20PF

C2803

1

TBT_X_XTAL25M_IN_R

CRITICAL

NOSTUFF

1

C2868

20UF

20%

2.5V

2

X6S-CERM
0402-1

PP3V3_TBT_X_SX
PP3V3_TBT_X_S0

100K

21

5%

BSB_GP6:BSB_S0

100K
100K

NOSTUFF

100K

NOSTUFF

100K

21

5% 2011/20W MF

21

21

5% 201MF1/20W

21

31

CRITICAL

NOSTUFF

1

C2867

20UF

20%

2.5V

2

X6S-CERM
0402-1

21 23 27

21 23 27

R2850

1/20W MF 201

R2841
R2851

MF1/20W 2015%

R2843

R2845

1/20W5% 201MF

BB XTAL

R2802

0

2 1

0201

CRITICAL

42

5%

1/20WMF

Y2800

25MHZ-25PPM-20PF-50OHM

2.00X1.60-SM

R2803

0

2 1

0201 5%

MF 1/20W

CRITICAL

NOSTUFF

1

C2866

20UF

20%

2.5V

2

X6S-CERM
0402-1

TBT_X_FLASH_SHARE_EN

TBT_X_XTAL25M_OUT

TBT_X_XTAL25M_IN

CRITICAL

OMIT_TABLE

1

C2865

20UF

20%

2.5V

2

X6S-CERM
0402-1

TBT_X_GPIO_5

TBT_X_GPIO_6

TBT_X_GPIO_12

CRITICAL

OMIT_TABLE

1

C2864

20UF

20%

2.5V

2

X6S-CERM
0402-1

21

21

21

21

21

21

CRITICAL

OMIT_TABLE

1

C2863

20UF

20%

2.5V

2

X6S-CERM
0402-1

CRITICAL

OMIT_TABLE

1

C2862

20UF

20%

2.5V

2

X6S-CERM
0402-1

MIN_LINE_WIDTH=0.1400
MIN_NECK_WIDTH=0.0750

VOLTAGE=3.3V

1

C2861

4UF

20%

6.3V

2

CER-X5R
0201

1

C2860

4UF

20%

6.3V

2

CER-X5R
0201

C2854

10UF

CERM
0402

20%

6.3V

1

2

1

2

C2850

4UF

20%

6.3V

CER-X5R
0201

PP3V3_TBT_X_LC

1

C2856

2.2UF

20%

6.3V

2

X5R-CERM
0201

C2855

2.2UF

20%

X5R-CERM

6.3V

0201

1

C2851

4UF

20%

6.3V

2

CER-X5R
0201

1

2

1

2

1

C2857

2.2UF

20%

6.3V

2

X5R-CERM
0201

C2852

4UF

20%

6.3V

CER-X5R
0201

1

C2853

4UF

20%

6.3V

2

CER-X5R
0201

PP0V9_TBT_X_LVR

PP3V3_TBT_X_ANA

23

PP0V9_TBT_X_LC

1

C2858

2.2UF

20%

6.3V

2

X5R-CERM
0201

NC
NC
NC
NC

F6
G6
E9
G9

L6
M6

E5
L2
J3

F3
F5
G5

B1

B12

D1
D11
D12

D2

F1
F11
F12

F2

M12

A12

TEST_EDM

NC_A12

J6

NC_J6

L3

NC_L3

J5

NC_J5

VCC0P9_SVR_ANA

VCC0P9_SVR_PB_ANA

VCC0P9_LVR
VCC0P9_LVR_SENSE

VCC3P3_LC
VCC3P3_ANA
VCC0P9_LC

VSS

VSS_ANA

U2800

BURNSIDE-BRIDGE

BGA

SYM 2 OF 2

CRITICAL

OMIT_TABLE

FORCE_PWR

FLASH_BUSY*

FUSE_VQPS_64

SMBUS_SCL
SMBUS_SDA

VCC3P3_SX

VCC3P3A

VCC3P3_SVR

VCC0P9_SVR

SVR_IND

SVR_VSS

VSS_ANA

B10

A9
B2

A7
B7

E6

J7

M4
M5

E3
G3

L1
M1

M2
M3

F7
F9
G7
H1
H11
H12
H2
J9
K1
K11
K12
K2

TBT_X_FORCE_PWR

TBT_XT_FLASH_BUSY_L

TP_SMBUS_TBT_X_SCL
TP_SMBUS_TBT_X_SDA

PP3V3_TBT_X_VCCA

1

C2843

12PF

5%

25V

2

NP0-C0G
0201

1

C2832

10UF

20%

6.3V

2

CERM
0402

BYPASS=U2800.M4:M3:3MM

1

2

1

2

1

2

0.68UH-20%-4.3A-0.043OHM

PP0V9_TBT_X_SVR_IND

_

VOLTAGE=0.9V
DIDT=TRUE

XW2830

SM

21

TBT_X_THERM_D_N

PLACE_NEAR=U2800.K11:2MM

NO_XNET_CONNECTION=1

CONNECT TO GND PIN
CLOSEST TO THERMDA PIN

BOM_COST_GROUP=TBT

23

IN

23

BI

1

C2830

2.2UF

20%

6.3V

X5R-CERM
0201

C2831

10UF

20%

6.3V

2

CERM
0402

PP3V3_TBT_X_S0_SVR

C2833

10UF

20%

6.3V

CERM
0402

1

C2834

10UF

20%

6.3V

2

CERM
0402

P0V9_TBT_X_SVR_PGND

C2838

12PF

5%

25V

NP0-C0G
0201

1

C2839

4UF

20%

6.3V

2

CER-X5R
0201

CRITICAL

L2800

21

0805

47

OUT

R2800

0

21

5%

1/16W MF-LF

402

1

C2836

2.2UF

20%

6.3V

2

X5R-CERM
0201

R2801

0

21

402

1/16W

1

C2835

10UF

20%

6.3V

2

CERM
0402

1

C2841

4UF

20%

6.3V

2

CER-X5R
0201

PAGE TITLE

5%

MF-LF

PLACE_NEAR=C2832.2:2MM
NO_XNET_CONNECTION=1

1

2

XW2801

SM

21

NO_XNET_CONNECTION=1

XW2800

SM

21

C2840

47UF

20%

6.3V

CER-X5R
0603

USB-C HIGH SPEED X (REAR)

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

FROM USB-C PORT
CONTROLLER (UPC)

PP3V3_TBT_X_SX

1

C2837

2.2UF

20%

6.3V

2

X5R-CERM
0201

1

2

PP3V3_TBT_X_S0

PP0V9_TBT_X_SVR

VOLTAGE=0.9V
DIDT=TRUE

DRAWING NUMBER

051-05232

REVISION

BRANCH

PAGE

SHEET

21 23 27

NOSTUFF

C2842

47UF

20%

6.3V

CER-X5R
0603

21 23 27

21

SYNC_DATE=06/08/2018SYNC_MASTER=CPU_CARD_ICL_Y

2.0.0

proto4b

28 OF 152

21 OF 86

B

A

SIZE

D

8

67

35 4

2

1

D

www.laptoprepairsecrets.com

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

138S00035 4 CRITICAL

CAP,CER,20UF,20%,2.5V,X6S,HRZTL,0402

C2962,C2963,C2964,C2965,C2966,C2967,C2968,C2969

678

TABLE_5_HEAD

BOM OPTIONCRITICAL

TABLE_5_ITEM

3 245

1

U2900

BURNSIDE-BRIDGE

USBC_HST_R2D_P<1>

22

USBC_HST_R2D_N<1>

22

J1
J2

ASSRXP1
ASSRXN1

BGA

SYM 1 OF 2

BSSRXP1
BSSRXN1

J12
J11

USBC_T_D2R_P<1>

USBC_T_D2R_N<1>

BI
BI

26

26

CRITICAL

USBC_HST_R2D_P<2>

22

USBC_HST_R2D_N<2>

22

C1
C2

ASSRXP2
ASSRXN2

OMIT_TABLE

BSSRXP2
BSSRXN2

C12
C11

USBC_T_D2R_P<2>
USBC_T_D2R_N<2>

BI
BI

26

26

D

USBC_HST_D2R_P<1>

22

USBC_HST_D2R_N<1>

22

G1
G2

ASSTXP1
ASSTXN1

BSSTXP1
BSSTXN1

G12
G11

USBC_T_R2D_CR_P<1>

USBC_T_R2D_CR_N<1>

OUT
OUT

26

26

C

USBC_HST_D2R_P<2>

22

USBC_HST_D2R_N<2>

22

23

BI

23

BI

USBC HIGH-SPEED 1 AC COUPLING

GND_VOID=TRUE

5

IN

5

IN

5

BI

5

BI

USBC_HST_R2D_C_P<1>

GND_VOID=TRUE

USBC_HST_R2D_C_N<1>

GND_VOID=TRUE

USBC_HST_D2R_C_P<1>

GND_VOID=TRUE

USBC_HST_D2R_C_N<1>

C2920

0.22UF

C2921

0.22UF

C2922

0.22UF

C2923

0.22UF

GND_VOID=TRUE

5

IN

5

IN

5

BI

5

BI

USBC_HST_R2D_C_P<2>

GND_VOID=TRUE

USBC_HST_R2D_C_N<2>

GND_VOID=TRUE

USBC_HST_D2R_C_P<2>

GND_VOID=TRUE

USBC_HST_D2R_C_N<2>

C2924

0.22UF

C2925

0.22UF

C2926

0.22UF

C2927

0.22UF

21
20%

X5R
21
20%

X5R
21

20% 0201
X5R

21
X5R
21
X5R

21
20%

X5R
21
X5R

21
20%

X5R

USBC_HST_R2D_P<1>

0201

6.3V

USBC_HST_R2D_N<1>

0201

6.3V

USBC_HST_D2R_P<1>

6.3V

USBC_HST_D2R_N<1>

020120%

6.3V

USBC_HST_R2D_P<2>

020120%

6.3V

USBC_HST_R2D_N<2>

0201

6.3V

USBC_HST_D2R_P<2>

020120%

6.3V

USBC_HST_D2R_N<2>

0201

6.3V

22

22

22

22

22

22

22

22

23

23

OUT

XDP_LSX_TBTB_R2P

IN

XDP_LSX_TBTB_P2R

NOSTUFF

R2908

20K

1/20W

5%
MF

201

25 23

20K

5%

1/20W

MF

201

1

2

1

2

R2909

25 23

25 23

23

IN

BI
BI

IN

USBC_HST_AUXCH_C_P
USBC_HST_AUXCH_C_N

I2C_UPC_T_INTM_L
I2C_UPC_T_SCLM

I2C_UPC_T_SDAM
TBT_T_GPIO_5

22

TBT_T_GPIO_6

22

TBT_T_FLASH_SHARE_EN

22

TBT_T_FLASH_MSTR_H_SLV_L
TBT_T_GPIO_12

22

TBT_T_THERM_D_P

23

TBT_T_XTAL25M_IN

22

TBT_T_XTAL25M_OUT

22

E1
E2

L8
M8

L7

A10

C9
E7

B9
A8
A4
A5
A6

M11

L9
M9

L12
A11

ASSTXP2
ASSTXN2

PA_AUX_P
PA_AUX_N

PA_LSTX_SBU1
PA_LSRX_SBU2

I2C_INT
I2C_SCL
I2C_SDA

POC_GPIO_5
POC_GPIO_6
POC_GPIO_10
POC_GPIO_11
POC_GPIO_12

THERMDA

XTAL_25_IN
XTAL_25_OUT

MONDC_SVR
MONDC

INTERNAL CAPS,

PU, PD

To SPI Flash

TEST_PWR_GOOD

BSSTXP2
BSSTXN2

BSBU1
BSBU2

PERST*
RESET*

TDI
TMS
TCK
TDO

EE_DI

EE_DO
EE_CS*
EE_CLK

TEST_EN

RBIAS
RSENSE

ATEST_P
ATEST_N

E12
E11

M10
L10

B8M7
L11

A3
C3
B5
C5

C6
B4
B6
C7

B11
B3

L4
L5

A1
A2

USBC_T_R2D_CR_P<2>
USBC_T_R2D_CR_N<2>

USBC_T_AUXLSX_P
USBC_T_AUXLSX_N

TBT_XT_PERST_L

USBC_T_RESET_L

JTAG_ISP_TDI

JTAG_TBT_T_TMS

JTAG_ISP_TCK
JTAG_ISP_TDO

SPI_TBT_T_MOSI
SPI_TBT_T_MISO
SPI_TBT_T_CS_L

SPI_TBT_T_CLK

TBT_T_TEST_PWR_GOOD

TBT_T_RBIAS

TBT_T_RSENSE

NC
NC

OUT
OUT

BI
BI

IN
IN

IN
IN
IN

OUT

OUT

IN
OUT
OUT

26

26

25 23

25 23

23

27

23

23

23

23

23

23

23

23

2 1

4.75K

0.5%
0201

PLACE_NEAR=U2900.L5:2MM
PLACE_NEAR=U2900.L4:2MM

1/20W

R2907

TF

R2906

100

5%

1/20W

MF

201

1

C

2

B

A

PP0V9_TBT_T_SVR

22

CRITICAL

NOSTUFF

1

C2969

20UF

20%

2.5V

2

X6S-CERM
0402-1

NOSTUFF

TBT_T_XTAL25M_OUT_R

5%

25V

C0G

0201
0201

C0G

25V

5%

1

2

2

C2902

20PF

20PF

C2903

1

TBT_T_XTAL25M_IN_R

CRITICAL

NOSTUFF

1

C2968

20UF

20%

2.5V

2

X6S-CERM
0402-1

PP3V3_TBT_T_SX
PP3V3_TBT_T_S0

100K

R2950

21

5% 201MF

BSB_GP6:BSB_S0

100K
100K

NOSTUFF

100K

NOSTUFF

100K

R2941

21

5% 2011/20W MF

R2951

21

R2943

21

R2945

21

CRITICAL

NOSTUFF

1

C2967

20UF

20%

2.5V

2

X6S-CERM
0402-1

22 27

22 23 27

1/20W

1/20W 2015%

1/20W MF 2015%

MF

BB XTAL

R2902

0

2 1

0201

31

CRITICAL

42

MF

5%

1/20W

TBT_T_XTAL25M_OUT

22

Y2900

NC
NC
NC
NC

M12

A12

J6
L3
J5

TEST_EDM

NC_A12
NC_J6
NC_L3
NC_J5

FORCE_PWR

FLASH_BUSY*

FUSE_VQPS_64

SMBUS_SCL
SMBUS_SDA

B10

A9
B2

A7
B7

TBT_T_FORCE_PWR

TBT_XT_FLASH_BUSY_L

TP_SMBUS_TBT_T_SCL
TP_SMBUS_TBT_T_SDA

IN

BI

23

23

25MHZ-25PPM-20PF-50OHM

2.00X1.60-SM

R2903

2 1

0201

MF5%1/20W

CRITICAL

NOSTUFF

1

C2966

20UF

20%

2.5V

2

X6S-CERM
0402-1

0

1

2

TBT_T_XTAL25M_IN

CRITICAL

OMIT_TABLE

C2965

20UF

20%

2.5V

X6S-CERM
0402-1

CRITICAL

OMIT_TABLE

1

C2964

20UF

20%

2.5V

2

X6S-CERM
0402-1

TBT_T_GPIO_5

TBT_T_GPIO_6

TBT_T_FLASH_SHARE_EN

22

22

22

22

CRITICAL

OMIT_TABLE

1

C2963

20UF

20%

2.5V

2

X6S-CERM
0402-1

CRITICAL

OMIT_TABLE

1

C2962

20UF

20%

2.5V

2

X6S-CERM
0402-1

MIN_LINE_WIDTH=0.1400
MIN_NECK_WIDTH=0.0750

VOLTAGE=3.3V

1

C2961

4UF

20%

6.3V

2

CER-X5R
0201

1

C2960

4UF

20%

6.3V

2

CER-X5R
0201

C2954

10UF

CERM
0402

20%

6.3V

1

2

1

2

C2950

4UF

20%

6.3V

CER-X5R
0201

PP3V3_TBT_T_LC

1

C2956

2.2UF

20%

6.3V

2

X5R-CERM
0201

C2955

2.2UF

20%

X5R-CERM

6.3V

0201

1

C2951

4UF

20%

6.3V

2

CER-X5R
0201

1

2

1

2

1

C2957

2.2UF

20%

6.3V

2

X5R-CERM
0201

1

C2952

4UF

20%

6.3V

CER-X5R
0201

C2953

4UF

20%

6.3V

2

CER-X5R
0201

PP0V9_TBT_T_LVR

PP3V3_TBT_T_ANA
PP0V9_TBT_T_LC

1

C2958

2.2UF

20%

6.3V

2

X5R-CERM
0201

F6
G6
E9
G9

L6
M6

E5
L2
J3

F3
F5
G5

B1

B12

D1
D11
D12

D2

F1
F11
F12

F2

BURNSIDE-BRIDGE

VCC0P9_SVR_ANA

VCC0P9_SVR_PB_ANA

VCC0P9_LVR
VCC0P9_LVR_SENSE

VCC3P3_LC
VCC3P3_ANA
VCC0P9_LC

VSS

VSS_ANA

U2900

BGA

SYM 2 OF 2

CRITICAL

OMIT_TABLE

VCC3P3_SX

VCC3P3A

VCC3P3_SVR

VCC0P9_SVR

SVR_IND

SVR_VSS

VSS_ANA

E6

J7

M4
M5

E3
G3

L1
M1

M2
M3

F7
F9
G7
H1
H11
H12
H2
J9
K1
K11
K12
K2

PP3V3_TBT_T_VCCA

1

C2943

12PF

5%

25V

2

NP0-C0G
0201

1

C2932

10UF

20%

6.3V

2

CERM
0402

BYPASS=U2900.M4:M3:3MM

1

2

1

2

1

2

PP0V9_TBT_T_SVR_IND

VOLTAGE=0.9V
DIDT=TRUE

XW2930

SM

21

TBT_T_THERM_D_N

PLACE_NEAR=U2900.K11:2MM

NO_XNET_CONNECTION=1

CONNECT TO GND PIN
CLOSEST TO THERMDA PIN

C2930

2.2UF

20%

6.3V

X5R-CERM
0201

1

C2931

10UF

20%

6.3V

2

CERM
0402

PP3V3_TBT_T_S0_SVR

C2933

10UF

20%

6.3V

CERM
0402

1

C2934

10UF

20%

6.3V

2

CERM
0402

1

2

P0V9_TBT_T_SVR_PGND

C2938

12PF

5%

25V

NP0-C0G
0201

1

C2939

4UF

20%

6.3V

2

CER-X5R
0201

CRITICAL

1

C2941

4UF

20%

6.3V

2

CER-X5R
0201

L2900

0.68UH-20%-4.3A-0.043OHM

21

0805

23

R2900

0

21

402

5%

1/16W MF-LF

1

C2936

2.2UF

20%

6.3V

2

X5R-CERM
0201

R2901

0

21

1/16W MF-LF

4025%

C2935

10UF

20%

6.3V

CERM
0402

PLACE_NEAR=C2932.2:2MM
NO_XNET_CONNECTION=1

1

2

SYNC_MASTER=CPU_CARD_ICL_Y SYNC_DATE=06/08/2018

PAGE TITLE

XW2901

SM

21

NO_XNET_CONNECTION=1

XW2900

SM

21

C2940

47UF

20%

6.3V

CER-X5R
0603

USB-C HIGH SPEED T (FRONT)

Apple Inc.

FROM USB-C PORT
CONTROLLER (UPC)

PP3V3_TBT_T_SX

1

C2937

2.2UF

20%

6.3V

2

X5R-CERM
0201

PP3V3_TBT_T_S0

PP0V9_TBT_T_SVR

DIDT=TRUE
VOLTAGE=0.9V

DRAWING NUMBER

REVISION

22 27

NOSTUFF

1

C2942

47UF

20%

6.3V

2

CER-X5R
0603

22 23 27

22

051-05232

B

A

SIZE

D

2.0.0

201MF5% 1/20W

TBT_T_GPIO_12

22

BOM_COST_GROUP=TBT

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

BRANCH

proto4b

PAGE

29 OF 152

SHEET

22 OF 86

8

67

35 4

2

1

678

www.laptoprepairsecrets.com

3 245

1

D

C

1

R3060

3.3K

5%
1/20W
MF
201

2

TBT_XT_SPI_CLK

23

TBT_XT_SPI_CS_L

23

TBT_XT_ROM_WP_L

24

TBT_XT_ROM_HOLD_L

NOSTUFF

R3061

3.3K

5%

1/20W

MF

201

R3064

1

2

3.3K

5%

1/20W

MF

201

1

R3063

3.3K

5%
1/20W
MF
201

2

1

2

6

1

3

7

Left Front Port

R3022

1/20W MF5% 201

BOMOPTION=FANTACH:NODEBUG

R3023
R3024
R3025

78 32 23

78 32 23

78 13

78 13

78 31

78 31

AUXLSX Probe Points

SWD_SOC_SWCLK

BI

SWD_SOC_SWDIO

BI

PCH_UART_DEBUG_R2D

IN

PCH_UART_DEBUG_D2R

OUT

USB_SOC_P

BI

USB_SOC_N

BI

R301A

1/20W

R301B

U3060

8MBIT-3.0V

W25Q80DVUXIE

CLK

CS*

WP*(IO2)

HOLD*(IO3)

GND EPAD

21

21

MF5%1/20W 201

21

21

MF1/20W 5% 201

21

5% 2011/20W MF

21

PP3V3_UPC_X_LDO

8

VCC

USON

DI(IO0)
DO(IO1)

OMIT_TABLE

CRITICAL

9

4

100K

100K

100K

201MF5%1/20W

100K

100K

201MF5%

100K

5%
MF

201

1

2

1

2

TBT_XT_SPI_MOSI
TBT_XT_SPI_MISO

R3062

3.3K

1/20W

5
2

SPARE_UPC_T_DBG0_R

MAKE_BASE=TRUE

SPARE_UPC_T_DBG1_R

MAKE_BASE=TRUE

SPARE_UPC_T_DBG2_R

MAKE_BASE=TRUE

SPARE_UPC_T_DBG3_R

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

SPARE_UPC_T_USB3_RP

MAKE_BASE=TRUE

SPARE_UPC_T_USB3_RN

MAKE_BASE=TRUE

23

C3060

1UF

10%

6.3V
CERM
402

ROM

TBT_XT_SPI_CLK

23

TBT_XT_SPI_CS_L

23

TBT_XT_SPI_MOSI

23

TBT_XT_SPI_MISO

23

23

23

DEBUG/USB MUX ALIASES

SPARE_UPC_T_DBG0_R

SPARE_UPC_T_DBG1_R

SPARE_UPC_T_DBG2_R

SPARE_UPC_T_DBG3_R

SWD_SOC_SWCLK

SWD_SOC_SWDIO
PCH_UART_DEBUG_R2D
PCH_UART_DEBUG_D2R

USB_SOC_P

USB_SOC_N

SPARE_UPC_T_USB3_RP

SPARE_UPC_T_USB3_RN

IN

IN

OUT

OUT

BI

BI

BI

BI

BI

BI

BI

BI

25

25

25

25

25

25

25

25

25

25

25

48 25

R3094
R3095
R3096
R3097
R3098
R3090
R3091
R3092
R3093
R3099
R309A
R309B
R309C

NO_XNET_CONNECTION=1

100

15
15
15
15
15
15
15
15
15
15
15
15

21

5% 1/20W MF 201

21

21

5% 1/20W MF 201

21

21

5% 1/20W MF 201

21

21

5% 1/20W MF 201

21

21

5%

21

21

5% 1/20W MF 201

21

21

5% 1/20W MF 201

15

OUT

15

OUT

15

15

23

BI

23

BI

78 32

78 32

TBT_XT_SPI_CLK_DBG
UPC_X_SPI_CLK

201MF1/20W5%

UPC_X_SPI_CS_L
UPC_X_SPI_MOSI

201MF1/20W5%

UPC_X_SPI_MISO
SPI_TBT_X_CLK

201MF1/20W5%

SPI_TBT_X_CS_L
SPI_TBT_X_MOSI

201MF1/20W5%

SPI_TBT_X_MISO

1/20W MF 201

SPI_TBT_T_CLK

201MF1/20W5%

SPI_TBT_T_CS_L
SPI_TBT_T_MOSI

201MF1/20W5%

SPI_TBT_T_MISO

Left Rear Port

USB3_BSSB_D2R_P

USB3_BSSB_D2R_N

USB3_BSSB_R2D_C_P

IN

PCH USB3DCI

USB3_BSSB_R2D_C_N

IN

SWD_SOC_SWCLK_R
SWD_SOC_SWDIO_R
SMC_DEBUGPRT_TX

IN

SMC_DEBUGPRT_RX

OUT

23

24

IN

24

IN

Ace

24

IN

24

OUT

21
23

23 21

BB

23 21

23 21

23 22

23 22

BB

23 22

23 22

IN

IN

IN

OUT

IN

IN

IN

OUT

R3012
R3013

C3010

C3011

R3028
R3029

5% MF 2011/20W

R302A

1/20W 5% MF 201

R302B

21

21

21

21

MF5% 2011/20W

SPI_TBT_X_CLK

21 23

SPI_TBT_X_CS_L

21 23

SPI_TBT_X_MOSI

21 23

SPI_TBT_X_MISO

21 23

SPI_TBT_T_CLK

22 23

SPI_TBT_T_CS_L

22 23

SPI_TBT_T_MOSI

22 23

SPI_TBT_T_MISO

22 23

21

0

21

0

21

0.1UF

10%16V 0201X5R-CERM

21

0.1UF

100K

201MF1/20W 5%

100K

100K

100K

BB / ACE SPI ROM BUS

GND

25

GND

25

GND

25

GND

25

0201MF1/20W 5%

0201MF1/20W 5%

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

SPARE_UPC_X_USB2_RP

MAKE_BASE=TRUE

SPARE_UPC_X_USB2_RN

MAKE_BASE=TRUE

SPARE_UPC_X_USB3_RP

MAKE_BASE=TRUE

SPARE_UPC_X_USB3_RN

MAKE_BASE=TRUE

USB3_BSSB_D2R_R_P

MAKE_BASE=TRUE

USB3_BSSB_D2R_R_N

MAKE_BASE=TRUE

USB3_BSSB_R2D_P

MAKE_BASE=TRUE

USB3_BSSB_R2D_N

MAKE_BASE=TRUE

020116V X5R-CERM10%

MAKE_BASE=TRUE

SPI_TBT_X_CLK

MAKE_BASE=TRUE

SPI_TBT_X_CS_L

MAKE_BASE=TRUE

SPI_TBT_X_MOSI

MAKE_BASE=TRUE

SPI_TBT_X_MISO

MAKE_BASE=TRUE

SPI_TBT_T_CLK

MAKE_BASE=TRUE

SPI_TBT_T_CS_L

MAKE_BASE=TRUE

SPI_TBT_T_MOSI

MAKE_BASE=TRUE

SPI_TBT_T_MISO

MAKE_BASE=TRUE

USB3_BSSB_D2R_R_P

USB3_BSSB_D2R_R_N

USB3_BSSB_R2D_P

USB3_BSSB_R2D_N

SWD_SOC_SWCLK_R
SWD_SOC_SWDIO_R
SMC_DEBUGPRT_TX
SMC_DEBUGPRT_RX

SPARE_UPC_X_USB2_RP

SPARE_UPC_X_USB2_RN

SPARE_UPC_X_USB3_RP

SPARE_UPC_X_USB3_RN

OUT

IN

IN

IN

BI

BI

BI

BI

BI

BI

BI

BI

24

24

24

24

24

24

24

24

24

24

24

24

13

13

13

13

13

IN
IN
IN

OUT

IN

JTAG_ISP_TDI

JTAG_TBT_X_TMS

JTAG_ISP_TCK
JTAG_ISP_TDO

JTAG_TBT_T_TMS

MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE

MAKE_BASE=TRUE

JTAG_ISP_TDI

JTAG_TBT_X_TMS

JTAG_ISP_TCK
JTAG_ISP_TDO

JTAG_ISP_TDI

JTAG_TBT_T_TMS

JTAG_ISP_TCK
JTAG_ISP_TDO

IN
IN
IN

OUT

IN
IN
IN

OUT

21

21

21

21

22

22

22

22

SIGNAL ALIASES

25 81 78 64 31

OUT IN

25 78 32 23

IN OUT

25

OUT

25

IN

24

OUT

24

OUT

24

OUT

24

OUT

32

TP3008

A A

TP-P5 TP-P5

TP3009

21

A

TP-P5

TP3004

A

TP-P5

TP3005

22

A

TP-P5

IN

1

21 5

BI BI
BI

1

21

BI

21

BI

IN

1

22

BI
BI

1

22

BI

22

BI BI

25

IN OUT

25

BI

25

BI

24

OUT

25

OUT

24

OUT

25

OUT

PMU_ACTIVE_READY
SOC_DOCK_CONNECT
SOC_DFU_STATUS
SOC_FORCE_DFU

PD_UPC_X_GPIO1
SOC_DOCK_CONNECT
PD_UPC_X_GPIO9
PD_UPC_X_GPIO10

TP_TBT_WAKE_L

USBC_HSX_AUXCH_C_P
USBC_HSX_AUXCH_C_N
XDP_LSX_TBTA_P2R
XDP_LSX_TBTA_R2P

USBC_HST_AUXCH_C_P
USBC_HST_AUXCH_C_N
XDP_LSX_TBTB_P2R
XDP_LSX_TBTB_R2P
DP_T_HST_HPD

UPC_X_UART_TX
UPC_X_UART_RX

PP3V3_UPC_X_LDO
PP3V3_UPC_T_LDO
GND
NC_UPC_T_I2C_ADDR

MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE

PD_UPC_X_GPIO1

MAKE_BASE=TRUE

SOC_DOCK_CONNECT

MAKE_BASE=TRUE

PD_UPC_X_GPIO9

MAKE_BASE=TRUE

PD_UPC_X_GPIO10

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE

MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE

MAKE_BASE=TRUE
MAKE_BASE=TRUE

MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE

XDP_LSX_TBTA_P2R
XDP_LSX_TBTA_R2P

XDP_LSX_TBTB_P2R
XDP_LSX_TBTB_R2P

ACE A/B RPD STRAPPING

24

24

25

25

BI
BI
BI
BI

USBC_X_CC1
USBC_X_CC2
USBC_T_CC1
USBC_T_CC2

MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE

PMU_ACTIVE_READY

SOC_DOCK_CONNECT

SOC_DFU_STATUS

SOC_FORCE_DFU

R3071

R3074
R3075

5% MF1/20W

100K

100K
100K

TP_TBT_WAKE_L

USBC_HSX_AUXCH_C_P
USBC_HSX_AUXCH_C_N

USBC_HST_AUXCH_C_P
USBC_HST_AUXCH_C_N

DP_T_HST_HPD

R3073

1/20W MF5%

100K

UPC_X_UART_TX
UPC_X_UART_RX

PP3V3_UPC_X_LDO
PP3V3_UPC_T_LDO

NC_UPC_T_I2C_ADDR

USBC_X_CC1

USBC_X_CC2

USBC_T_CC1

USBC_T_CC2

IN

OUT

MF1/20W5% 201

OUT

2015% MF1/20W

201

201

BI
BI
BI

BI
BI
BI

OUT

IN

BI
BI
BI
BI

81 78 40 31

78 64 31

21

78 32 23

21

21

TP3006

1

TP3007

5

1

5

TP-P5

16

16 5

TP3002

1

5

TP-P5

TP3003

5

1

5

TP-P5

16

TP3011

5

1

16

TP-P5

21

24 23

24 23

24 23

25 23

26 24

26 24

26 25

26 25

D

A

A

A

A

C

B

Probe Points for Port X
were removed due to layout
disruption.

POWER ALIASES

PP3V3_UPC_X_LDO

23

PP3V3_UPC_X_LDO

23

PP3V3_UPC_T_LDO

23

PP20V_USBC_X_VBUS

24

PP20V_USBC_X_VBUS

24

PP20V_USBC_T_VBUS

25

PP20V_USBC_T_VBUS

25

MAKE_BASE=TRUE

PP3V3_UPC_X_LDO

MAKE_BASE=TRUE

PP3V3_UPC_T_LDO

MAKE_BASE=TRUE

PP20V_USBC_X_VBUS

MAKE_BASE=TRUE

PP20V_USBC_T_VBUS

PP3012

P3MM

SM

PP3013

P3MM

SM

PP

PP

NC_UPC_X_VDDIO_CFG

24

25

1

1

24 23

25 23

USBC_T_AUXLSX_P

USBC_T_AUXLSX_N

79 78 26

79 78 26

GND

24

GND

24

GND

24

GND

24

GND

25

GND

25

GND

25

GND

25

TBT_T_THERM_D_P

22

TBT_T_THERM_D_N

PLACE_NEAR=U3200.G16:2MM

22

25 22

25 22

BSB_FORCE_PWR:ACE

P3MM

1

P3MM

1

SM
PP

PP3000

SM
PP

PP3001

67 24

25 24 13

67 25

IN

IN

IN

UPC_X_FORCE_PWR

R3050

1/20W 5% MF 0201

BSB_FORCE_PWR:PCH

PCH_BSB_FORCE_PWR

R3051

5%1/20W MF 0201

BSB_FORCE_PWR:ACE

UPC_T_FORCE_PWR TBT_T_FORCE_PWR

R3052

5%1/20W MF 0201

BSB_FORCE_PWR:PCH

21

0

21

0

21

0

TBT_X_FORCE_PWR

OUT

OUT

23 21

23 22

25

IN

NC_UPC_T_VDDIO_CFG

UPC_X_RESET

24

UPC_T_RESET

25

UPC_XT_5V_EN

23

UPC_T_GPIO5

74

UPC_PMU_RESET

24

UPC_PMU_RESET

25

UPC_XT_5V_EN

24

UPC_XT_5V_EN

25

PP1V8_AWAKE

R3072

NC_UPC_X_VDDIO_CFG

MAKE_BASE=TRUE

NC_UPC_T_VDDIO_CFG

MAKE_BASE=TRUE

100K

1/20W MF5%

R3081

1/20W

201

0

R3032

5% MF

1/20W 201

R3033

R3034

1/20W5% MF 201

21

21

SOC_USB_VBUS

MF5% 0201

UPC_PMU_RESET

MAKE_BASE=TRUE

UPC_XT_5V_EN

MAKE_BASE=TRUE

2015% 1/20W MF

100K

100K

100K

21

21

21

B

OUT

23

78 31

64 55

A

PPDCIN_G3H

75

CRITICAL

0603-1

F3000

6A-32V

PLACE_NEAR=U3100:5MM

CRITICAL

0603-1

F3001

6A-32V

PLACE_NEAR=U3200:5MM

USBC_DBG

21

PPHV_INT_X_G3H

MAKE_BASE=TRUE

21

PPHV_INT_T_G3H

MAKE_BASE=TRUE

J3000

505070-1222

M-ST-SM

1413

FUSES FOR UPC

PPHV_INT_X_G3H

PPHV_INT_X_G3H

PPHV_INT_T_G3H

PPHV_INT_T_G3H

78 32 23

78 32 23

SWD_SOC_SWCLK
SWD_SOC_SWDIO

PLACE_NEAR=U3200.F15:2MM

Per Will Ferry, SI will determine R3026 and R3027

24

24

25

25

values during characterization.

SWD_SOC_SW* Placement Topology

SOC

U3900

R3027
R3026

SWD_SOC_SWCLK

Front
U3200
T

5%

21

R3027

BRIDGE ARKANOID CONNACE ARKANOID CONN

USBC_DBG

21

21

SWD_SOC_SWCLK_R

SWD_SOC_SWCLK_R

0

0201MF1/20W

SWD_SOC_SWDIO_R

0

0201MF1/20W 5%

505070-1222

Rear
U3100
X

J3001

M-ST-SM

23

23

BSB_PERST:PLTRST

R3055

18

IN

PLT_RST_3V3_L TBT_XT_PERST_L

100K

BSB_PERST:GPD_7

21

201MF5%1/20W

R3056

14

IN

1413

PCH_STRP_GPD7

5% MF 02011/20W

21

0

R3053

AARDVARKANOID CONN

USBC_DBG

5%1/20W

MAKE_BASE=TRUE

21

0

0201MF

J3002

505070-1222

M-ST-SM

1413

TBT_XT_PERST_L
TBT_XT_PERST_L

SPI ACE

25 24 13

42 32

42 32

42 32

TBT_POC_RESET

I2C_UPC_SCL
I2C_UPC_SDA

SMC

UPC_I2C_INT_L
TBT_XT_SPI_CLK_DBG UPC_T_SWD_DATA

23 25

UPC_X_UART_TX

15

21
43
65
87
109
1211

16

PCH_UPC_I2C_INT_L
XDP_PCH_I2C_UPC_SDA
XDP_PCH_I2C_UPC_SCL
UPC_X_SER_DBG
UPC_T_SER_DBG
UPC_X_UART_RX

PCH

24 42

23 24 42

23 24 42

24

25

24 23 24 23

23 21

21 27

21

21 23

22 27

25 22

TBT_X_FORCE_PWR
PP3V3_TBT_X_S0
PP0V9_TBT_X_LC
TBT_XT_PERST_L
PP3V3_TBT_T_S0
I2C_UPC_T_SDAM

15

21
43
65
87
109
1211

16

I2C_UPC_X_INTM_L
I2C_UPC_X_SCLM
I2C_UPC_X_SDAM
TBT_T_FORCE_PWR
I2C_UPC_T_INTM_L
I2C_UPC_T_SCLM

PP3V3_UPC_X_LDO

24 21

24 21

24 21

23 22

25 22

25 22

23

UPC_X_SWD_DATA

24

UPC_X_SWD_CLK

24

TBT_XT_SPI_MISO

23

XDP_PCH_I2C_UPC_SDA

23 24 42

XDP_PCH_I2C_UPC_SCL

23 24 42

15

21
43
65
87
109
1211

16

TBT_XT_SPI_CS_L
TBT_XT_SPI_CLK
TBT_XT_SPI_MOSI
UPC_T_SWD_CLK

PP3V3_UPC_T_LDO

UART ACE

23

23

23

25

23

OUT

OUT

22

23 21

BOM_COST_GROUP=TBT

PP3V3_TBT_X_SX

PP3V3_G3H_RTC

10K

NOSTUFF

100K

2.2K

21

21

SYNC_MASTER=CPU_CARD_ICL_Y SYNC_DATE=06/08/2018

PAGE TITLE

R3042

21

5%

R3044

1/20W MF5% 201

R3047

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

21 27

24 27 75

201MF1/20W

2015% 1/20W MF

TBT_XT_FLASH_BUSY_L

21

22

TBT_X_FLASH_MSTR_H_SLV_L

TBT_XT_FLASH_BUSY_L
TBT_XT_FLASH_BUSY_L

TBT_XT_FLASH_BUSY_L

24

TP3010

1

TP-P5

A

----

TBT_T_FLASH_MSTR_H_SLV_L

USB-C Support

Apple Inc.

MAKE_BASE=TRUE

21

22

DRAWING NUMBER

051-05232

REVISION

2.0.0

BRANCH

proto4b

PAGE

30 OF 152

SHEET

23 OF 86

A

SIZE

D

8

67

35 4

2

1

678

www.laptoprepairsecrets.com

PRIMARY ACE2 USB-C PORT CONTROLLER (UPC)

3 245

1

D

C

PP3V3_UPC_X_LDO

1M

1M

10K

1M

R3109

21

R3108

21

R3107

21

21

R3105

MF5% 1/20W

201MF5% 1/20W

24 23

I2C_UPC_X_SCLM

2011/20W5% MF

I2C_UPC_X_SDAM

201MF1/20W5%

I2C_UPC_X_INTM_L

201

UPC_X_UART_RX

Either a Testpoint or Arkanoid connector

must be present for GPIO0

(EVEN IN PRODUCTION)

24 23 21

24 23 21

24 23 21

24 23

CRITICAL

R3103

15K

0.1%
1/20W
TF-LF

0201

REAR PORT:

CONNECT UPC SPI TO ROM

FRONT PORT:

GROUND UPC SPI

C3101

1UF

10%

35V

X5R

0402

PP20V_USBC_X_VBUS

1

2

23

D

PPHV_INT_X_G3H

23

MAX 100uF TOTAL ON RAIL

C3100

10UF

PP5V_G3S

75

PP5V_G3S

75

CAP FOR PP_5V0 ON VR PAGE

N8

N6

M7

M5

L8

L6

K7

K5

J8

J6

H7

H5

G8

TYPE-C

G6

VBUS

CRITICAL
OMIT_TABLE

VIN_3V3

VDDIO

VDDIO_CFG

LDO_3V3

VIN_LV

VOUT_LV

VRET

SS

LDO_CORE

VBUS_OPT

PP_HV_OPT

C_CC1

C_CC2

RPD_G1
RPD_G2

C_USB_TP
C_USB_TN

C_USB_BP
C_USB_BN

C_SBU1
C_SBU2

C20

A12
D11

C22
D21

L20
L18

C16

L22

E22

D5

F5

M15
N16

M17
N18

L14
L16

K19
K21

J20
J22

J16
H15

C3102

1.0UF

0201-1

NC_UPC_X_VDDIO_CFG

UPC_X_VRET

UPC_X_SS

PP1V5_UPC_X_LDO_CORE
PP20V_USBC_X_VBUS
PPHV_INT_X_G3H

USBC_X_CC1

USBC_X_CC2

USBC_X_CC1
USBC_X_CC2

USBC_X_USB_TOP_P
USBC_X_USB_TOP_N

USBC_X_USB_BOT_P
USBC_X_USB_BOT_N

USBC_X_SBU1
USBC_X_SBU2

N4

N2

M3

M1

L4

L2

K3

K1

J4

J2

H3

H1

G4

G2

M13

N14

N12

M11

L12

K11

N10

M9

L10

K9

PP_5V0

PP_CABLE

PP_HV

U3100

23

IN

25 23 13

24 23 21

67 23

25 23 13

GND I2C_ADDR
PRIMARY ONLY

1

2

TO SMC

24 23 21

24 23 21

42 23

42 23

42 23

27

23

23

23

23

23

23

23

23

23

42

42

42

23

23

23

23

IN

OUT

IN

IN

IN
OUT
OUT
OUT

IN
OUT
OUT

IN
OUT

IN

BI
BI

BI
BI
OUT

BI
BI
OUT

OUT
OUT

IN
OUT

UPC_X_RESET
TBT_POC_RESET
USBC_X_RESET_L

UPC_X_SER_DBG

PD_UPC_X_GPIO1
I2C_UPC_X_INTM_L

UPC_XT_5V_EN
UPC_X_FORCE_PWR

TBT_XT_FLASH_BUSY_L

PCH_BSB_FORCE_PWR

SOC_DOCK_CONNECT

UPC_PMU_RESET
PD_UPC_X_GPIO9
PD_UPC_X_GPIO10

PP3V3_UPC_X_LDO
GND

23

UPC_X_R_OSC
I2C_UPC_X_SDAM

I2C_UPC_X_SCLM
XDP_PCH_I2C_UPC_SDA

XDP_PCH_I2C_UPC_SCL
PCH_UPC_I2C_INT_L

I2C_UPC_SDA
I2C_UPC_SCL
UPC_I2C_INT_L

UPC_X_SPI_CLK
UPC_X_SPI_MOSI
UPC_X_SPI_MISO
UPC_X_SPI_CS_L

B13
A14
B17

A2
B1

D1
F1
C2
E2
B3
C4
D3
E4
F3
F7

A18

M19
M21

A16
B15

B5
A4
D7

B7
A6
C8

B9
B11
A10

A8

HRESET
MRESET
RESET*

GPIO0

GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10

BUSPOWER

I2C_ADDR
R_OSC

I2CM_SDA_CNFG
I2CM_SCL_CNFG

I2C_SDA1
I2C_SCL1
I2C_IRQ1*

I2C_SDA2
I2C_SCL2
I2C_IRQ2*

SPI_CLK
SPI_MOSI
SPI_MISO
SPI_SSZ

IPU-BOOT

DIGITAL CORE I/O & CONTROL POWER

CD3217B12ACE

FCBGA

20%

6.3V

CERM
0402

20%

6.3V

X5R

1

2

1

2

23

0

R3120

21

1/20W5% MF 0201

VOLTAGE=1.5V

MIN_LINE_WIDTH=0.2800
MIN_NECK_WIDTH=0.0750

23

23

23

BI

23

BI

26

BI

26

BI

26

BI

26

BI

26

BI

26

BI

PP3V3_G3H_RTC

PP1V8_SLPS2R

1

C3105

10UF

20%

6.3V

2

CERM
0402

23 27 75

74

MIN_LINE_WIDTH=0.2800

MIN_NECK_WIDTH=0.0750

VOLTAGE=3.3V

PP3V3_UPC_X_LDO

PP3V3_UPC_X_VOUTLV

1

C3109

0.68UF

5%

6.3V

2

X6S
0402

MIN_LINE_WIDTH=0.4000
MIN_NECK_WIDTH=0.1500

MIN_LINE_WIDTH=0.4000
MIN_NECK_WIDTH=0.1500

1

C3106

1.0UF

20%

6.3V

2

X5R
0201-1

1

C3114

220PF

10%

16V

2

CER-X7R
0201

67 27

1

C3113

220PF

10%

16V

2

CER-X7R
0201

1

C3108

10UF

20%

6.3V

2

CERM
0402

BI

BI

23
24

C

26 23

26 23

B

15

15

BI

BI

USB2_TBT_X_P

USB2_TBT_X_N

L3100

90-OHM-0.1A

EXCX4CE

SYM_VER-1

1

PLACE_NEAR=U3100:5MM

4

32

23

23

24 23

23

23

23

23

23

21

21

23

23

23

23

23

23

23

23

23

BI
BI

IN

OUT

BI
BI
BI
BI

BI
BI

OUT

BI
BI
BI
BI
OUT
BI

IN

OUT

UPC_X_SWD_DATA
UPC_X_SWD_CLK

UPC_X_UART_RX
UPC_X_UART_TX

USB_UPC_X1_P
USB_UPC_X1_N

SPARE_UPC_X_USB2_RP
SPARE_UPC_X_USB2_RN
SPARE_UPC_X_USB3_RP
SPARE_UPC_X_USB3_RN

USBC_X_AUXLSX_P
USBC_X_AUXLSX_N

TBT_XT_ROM_WP_L
USB3_BSSB_D2R_R_P

USB3_BSSB_D2R_R_N
USB3_BSSB_R2D_P
USB3_BSSB_R2D_N
SWD_SOC_SWCLK_R

SWD_SOC_SWDIO_R
SMC_DEBUGPRT_TX
SMC_DEBUGPRT_RX

E20
E16

B19
A20

H19
H21
G20
G22
F19
F21

J12
H11

C12

G12
F11

E8
E12
G16
F15
D15
D19

SWD_DATA
SWD_CLK

UART_RX
UART_TX

USB_RP1_P
USB_RP1_N
USB_RP2_P
USB_RP2_N
USB_RP3_P
USB_RP3_N

AUX_P
AUX_N

HPD

DEBUG0
DEBUG1
DEBUG2
DEBUG3
DEBUG4
DEBUG5
DEBUG6
DEBUG7

IPU
IPU

B

C18
E18
D17
G18

GND
GND
GND
GND

23

23

23

23

GND_OPT
GND_OPT
GND_OPT

GNDPORT_MUX

GND

GND_OPT

A

8

67

A22

H9

N20

B21

K15

N22

BOM_COST_GROUP=USB-C

35 4

PAGE TITLE

USB-C PORT CONTROLLER X (REAR)

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

2

SYNC_DATE=06/08/2018SYNC_MASTER=CPU_CARD_ICL_Y

DRAWING NUMBER

051-05232

REVISION

2.0.0

BRANCH

proto4b

PAGE

31 OF 152

SHEET

24 OF 86

1

A

SIZE

D

678

www.laptoprepairsecrets.com

SECONDARY ACE2 USB-C PORT CONTROLLER (UPC)

3 245

1

D

C

PP3V3_UPC_T_LDO

VOLTAGE=3.3V

1M

1M

10K

R3209

21

5%

R3208

21

1/20W MF

5% 201

R3207

21

1/20W 201

5% MF

21

R3205

5%1M1/20W MF 201

MF1/20W 201

25 23

I2C_UPC_T_SCLM

I2C_UPC_T_SDAM

I2C_UPC_T_INTM_L

UPC_X_UART_TX

Either a Testpoint or Arkanoid connector

must be present for GPIO0

(EVEN IN PRODUCTION)

25 23 22

25 23 22

25 23 22

23 25

REAR PORT:
FRONT PORT:

CRITICAL

15K

0.1%
1/20W
TF-LF

0201

1

2

R3203

CONNECT UPC SPI TO ROM
GROUND UPC SPI

GND I2C_ADDR
PRIMARY ONLY

TO SMC

23

75

75

24 23 13

27

25 23 22

23

67 23

23

24 23 13

23

23

23

25 23 22

25 23 22

42

42

42

42

42

42

23

23

23

PPHV_INT_T_G3H

MAX 100uF TOTAL ON RAIL

PP5V_G3S
PP5V_G3S

CAP FOR PP_5V0 ON VR PAGE

23

23

23

23

23

IN
IN

OUT

IN

IN

IN
OUT
OUT
OUT

IN
OUT
OUT

IN
OUT

IN

UPC_T_RESET
TBT_POC_RESET
USBC_T_RST_L

UPC_T_SER_DBG

PMU_ACTIVE_READY
I2C_UPC_T_INTM_L

UPC_XT_5V_EN
UPC_T_FORCE_PWR

UPC_T_GPIO5

PCH_BSB_FORCE_PWR

SOC_DOCK_CONNECT

UPC_PMU_RESET
SOC_DFU_STATUS
SOC_FORCE_DFU

PP3V3_UPC_T_LDO

NC_UPC_T_I2C_ADDR

23

UPC_T_R_OSC
I2C_UPC_T_SDAM

I2C_UPC_T_SCLM
XDP_PCH_I2C_UPC_SDA

XDP_PCH_I2C_UPC_SCL
PCH_UPC_I2C_INT_L

I2C_UPC_SDA
I2C_UPC_SCL
UPC_I2C_INT_L

GND
GND
GND
GND

23

BI
BI

BI
BI
OUT

BI
BI
OUT

OUT
OUT

IN
OUT

B13
A14
B17

A2
B1

D1
F1
C2
E2
B3
C4
D3
E4
F3
F7

A18

M19
M21

A16
B15

B5
A4
D7

B7
A6
C8

B9
B11
A10

A8

N10

M9

L10

K9

HRESET
MRESET
RESET*

GPIO0

GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10

BUSPOWER

I2C_ADDR
R_OSC

I2CM_SDA_CNFG
I2CM_SCL_CNFG

I2C_SDA1
I2C_SCL1
I2C_IRQ1*

I2C_SDA2
I2C_SCL2
I2C_IRQ2*

SPI_CLK
SPI_MOSI
SPI_MISO
SPI_SSZ

IPU

N4

N2

M3

M1

L4

L2

K3

K1

J4

J2

H3

H1

G4

G2

M13

N14

N12

M11

L12

K11

PP_5V0

PP_CABLE

PP_HV

U3200

CD3217B12ACE

FCBGA

DIGITAL CORE I/O & CONTROL POWER

TYPE-C

G6

G8

H7

H5

CRITICAL
OMIT_TABLE

J6

J8

K5

K7

VBUS

L6

L8

M5

M7

N6

N8

VIN_3V3

VDDIO

VDDIO_CFG

LDO_3V3

VIN_LV

VOUT_LV

VRET

SS

LDO_CORE

VBUS_OPT

PP_HV_OPT

C_CC1

C_CC2

RPD_G1
RPD_G2

C_USB_TP
C_USB_TN

C_USB_BP
C_USB_BN

C_SBU1
C_SBU2

C20

A12
D11

C22
D21

L20
L18

C16

L22

E22

D5

F5

M15
N16

M17
N18

L14
L16

K19
K21

J20
J22

J16
H15

10%

35V

X5R

0402

20%

6.3V

20%

6.3V

X5R

1

2

1

2

1

2

C3201

1UF

C3200

10UF

CERM
0402

C3202

1.0UF

0201-1

NC_UPC_T_VDDIO_CFG

UPC_T_VRET

0

UPC_T_SS

PP1V5_UPC_T_LDO_CORE
PP20V_USBC_T_VBUS
PPHV_INT_T_G3H

USBC_T_CC1

USBC_T_CC2

USBC_T_CC1
USBC_T_CC2

USBC_T_USB_TOP_P
USBC_T_USB_TOP_N

USBC_T_USB_BOT_P
USBC_T_USB_BOT_N

USBC_T_SBU1
USBC_T_SBU2

21

R3220

PP20V_USBC_T_VBUS

PP3V3_G3H_RTC

PP1V8_SLPS2R

23

02015%

MF1/20W

VOLTAGE=1.5V

MIN_LINE_WIDTH=0.2800
MIN_NECK_WIDTH=0.0750

23

23

23

BI

23

BI

26

BI

26

BI

26

BI

26

BI

26

BI

26

BI

1

C3205

10UF

20%

6.3V

2

CERM
0402

23

27 75

74

MIN_LINE_WIDTH=0.2800
MIN_NECK_WIDTH=0.0750

PP3V3_UPC_T_LDO

PP3V3_UPC_T_VOUTLV

1

C3209

0.68UF

5%

6.3V

2

X6S
0402

MIN_LINE_WIDTH=0.4000
MIN_NECK_WIDTH=0.1500

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000

1

C3206

1.0UF

20%

6.3V

2

X5R
0201-1

1

C3214

220PF

10%

16V

2

CER-X7R
0201

67 27

1

C3213

220PF

10%

16V

2

CER-X7R
0201

1

C3208

10UF

20%

6.3V

2

CERM
0402

BI

BI

D

23
25

C

26 23

26 23

B

15

15

BI

BI

USB2_TBT_T_P

USB2_TBT_T_N

L3200

90-OHM-0.1A

EXCX4CE

SYM_VER-1

1

PLACE_NEAR=U3200:5MM

4

32

23

23

25 23

23

23

23

23

23

23 22

23 22

23

48 23

23

23

23

23

23

23

23

BI
BI

IN

OUT

BI
BI
BI
BI

BI
BI

OUT

BI
BI
BI
BI
OUT
BI

IN

OUT

UPC_T_SWD_DATA
UPC_T_SWD_CLK

UPC_X_UART_TX
UPC_X_UART_RX

USB_UPC_T1_P
USB_UPC_T1_N

USB_SOC_P
USB_SOC_N
SPARE_UPC_T_USB3_RP
SPARE_UPC_T_USB3_RN

USBC_T_AUXLSX_P
USBC_T_AUXLSX_N

DP_T_HST_HPD
SPARE_UPC_T_DBG0_R

SPARE_UPC_T_DBG1_R
SPARE_UPC_T_DBG2_R
SPARE_UPC_T_DBG3_R
SWD_SOC_SWCLK

SWD_SOC_SWDIO
PCH_UART_DEBUG_R2D
PCH_UART_DEBUG_D2R

E20
E16

B19
A20

H19
H21
G20
G22
F19
F21

J12
H11

C12

G12
F11

E8
E12
G16
F15
D15
D19

SWD_DATA
SWD_CLK

UART_RX
UART_TX

USB_RP1_P
USB_RP1_N
USB_RP2_P
USB_RP2_N
USB_RP3_P
USB_RP3_N

AUX_P
AUX_N

HPD

DEBUG0
DEBUG1
DEBUG2
DEBUG3
DEBUG4
DEBUG5
DEBUG6
DEBUG7

IPU
IPU

B

GND_OPT
GND_OPT
GND_OPT

GNDPORT_MUX

GND

GND_OPT

C18
E18
D17
G18

GND
GND
GND
GND

23

23

23

23

A

8

67

A22

H9

N20

B21

K15

N22

BOM_COST_GROUP=USB-C

35 4

SYNC_MASTER=CPU_CARD_ICL_Y SYNC_DATE=06/08/2018

PAGE TITLE

USB-C PORT CONTROLLER T (FRONT)

SIZE

D

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

2

DRAWING NUMBER

051-05232

REVISION

2.0.0

BRANCH

proto4b

PAGE

32 OF 152

SHEET

25 OF 86

1

A

678

www.laptoprepairsecrets.com

3 245

1

D

C

B

Left Rear Port

USBC_X_CC1

24 23

2

1

2

1

R3361
R3360

R3363
R3362

SLP0603P2X3-COMBO

GND_VOID=TRUE

CRITICAL

RCLAMP1031ZC

D3360

R3380
R3381

R3382
R3383

SLP0603P2X3-COMBO

GND_VOID=TRUE

CRITICAL

RCLAMP1031ZC

D3381

21

21

21

21

22

22

22

22

USBC_X_R2D_CR_N<1>

IN

USBC_X_R2D_CR_P<1>

IN

USBC_X_D2R_N<1> USBC_X_D2R_R_N<1>

OUT

USBC_X_D2R_P<1>

OUT

USBC_X_SBU2

24

USBC_X_USB_BOT_N

24

USBC_X_USB_BOT_P

24

SLP0603P2X3-COMBO

GND_VOID=TRUE

2

1

USBC_T_USB_BOT_N

25

USBC_T_USB_BOT_P

25

USBC_T_SBU1

25

USBC_T_R2D_CR_P<2>

IN

USBC_T_R2D_CR_N<2>

IN

USBC_T_D2R_P<2>

OUT

USBC_T_D2R_N<2>

OUT

USBC_T_CC2

25 23

2

1

CRITICAL

2

RCLAMP1031ZC

D3362

SLP0603P2X3-COMBO

GND_VOID=TRUE

CRITICAL

2

RCLAMP1031ZC

D3383

1

1

SLP0603P2X3-COMBO

GND_VOID=TRUE

CRITICAL

RCLAMP1031ZC

D3363

SLP0603P2X3-COMBO

GND_VOID=TRUE

CRITICAL

RCLAMP1031ZC

D3382

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

5%

5% 1/20W

2

5% 1/20W

5%

2

1

1/20W5%

1/20W

1

GND_VOID=TRUE

GND_VOID=TRUE

CRITICAL

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

CRITICAL

21

USBC_X_R2D_C_N<1>

2

MF5% 2011/20W

21

USBC_X_R2D_C_P<1>

2

201MF1/20W5%

21

2

MF 2011/20W

21

USBC_X_D2R_R_P<1>

2

MF 201

SLP0603P2X3-COMBO

2

RCLAMP1031ZC

D3361

SLP0603P2X3-COMBO

RCLAMP1031ZC

D3380

1

21

USBC_T_R2D_C_P<2>

2

MF 201

21

USBC_T_R2D_C_N<2>

2

201MF

21

USBC_T_D2R_R_P<2>

2

MF 2011/20W5%

21

USBC_T_D2R_R_N<2>

2

201MF

2

1

CRITICAL

2

X3DFN2

D3364

ESD8011-COMBO

CRITICAL

2

5.5V-6.2PF

0201-THICKSTNCL

D3386

1

1

CRITICAL

X3DFN2

D3365

ESD8011-COMBO

CRITICAL

5.5V-6.2PF

0201-THICKSTNCL

D3387

FOR POR, VERIFY 20% TOLERANCE ON 0.22UF AC COUPLING CAP IS OK

PLACE VBUS CAP NEAR EACH VBUS PIN

516S00457

Mates with:

x on y

BYPASS=J3300.57::10MM

BYPASS=J3300.57::10MM

CRITICAL

1

C3320

0.01UF

10%
25V

2

X5R-CERM
0201

BYPASS=J3300.57::10MM

CRITICAL

1

C3326

0.01UF

10%
25V

2

X5R-CERM
0201

CRITICAL

1

C3321

0.01UF

10%
25V

2

X5R-CERM
0201

BYPASS=J3300.57::10MM

CRITICAL

1

C3327

0.01UF

10%
25V

2

X5R-CERM
0201

BYPASS=J3300.57::10MM

CRITICAL

1

C3322

0.01UF

10%
25V

2

X5R-CERM
0201

BYPASS=J3300.57::10MM

CRITICAL

1

C3328

0.01UF

10%
25V

2

X5R-CERM
0201

BYPASS=J3300.57::10MM

CRITICAL

1

C3323

0.01UF

10%
25V

2

X5R-CERM
0201

BYPASS=J3300.57::10MM

CRITICAL

1

C3325

0.01UF

10%
25V

2

X5R-CERM
0201

PLACE_NEAR=J3300.58:5MM

D3322

TVS2200

WSON

4

IN

5

IN

6

IN

GND

GND

GND

1

2

EPAD

7

3

CRITICAL

K

D3320

X3-WLB1608-1

SDM2U40CSP

A

PP20V_USBC_X_VBUS

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000

VOLTAGE=20V

79 78 23

D

(NO LANE REVERSALS ALLOWED)

TP_USBC_PP20V_X

GND_VOID=TRUE

0.22UF

C3361

10%X5R

C3360

X5R 25V 020110%

GND_VOID=TRUE
GND_VOID=TRUE

C3363
C3362

CER-X5R

CRITICAL

2

1

2

5.5V-6.2PF

0201-THICKSTNCL

1

D3367

CRITICAL

D3366

10%

GND_VOID=TRUE

5.5V-6.2PF

0201-THICKSTNCL

GND_VOID=TRUE

C3380

10%

C3381

GND_VOID=TRUE
GND_VOID=TRUE

C3382

10% 25V 0201CER-X5R

C3383

GND_VOID=TRUE

2

1

CRITICAL

2

X3DFN2

1

D3384

ESD8011-COMBO

CRITICAL

X3DFN2

D3385

ESD8011-COMBO

21

0.22UF

21

0.33UF

21

0.33UF

21

0.22UF

21

0.22UF

21

0.33UF

21

0.33UF

21

020125V

020125VCER-X5R 10%

020125V

020125VX5R

020125VX5R 10%

020125V10%CER-X5R

201

220K

1

2

R3365

220K

1

2

R3384

220K

GND_VOID=TRUE

MF1/20W5%

R3364

201MF5% 1/20W

220K

GND_VOID=TRUE

R3385

GND_VOID=TRUE

1

1/20W MF 2015%

2

201MF1/20W5%

GND_VOID=TRUE

1

2

USBC_X_R2D_N<1>

USBC_X_R2D_P<1>

USBC_X_D2R_CR_N<1>

USBC_X_D2R_CR_P<1>

2011/20W MF5%

220K

1

2

R3367

220K

GND_VOID=TRUE

MF5% 2011/20W

R3366

GND_VOID=TRUE

1

2

USBC_T_R2D_P<2>

USBC_T_R2D_N<2>

USBC_T_D2R_CR_P<2>

USBC_T_D2R_CR_N<2>

2015% MF1/20W

220K

GND_VOID=TRUE

1

2

R3386

2011/20W5% MF

220K

GND_VOID=TRUE

1

2

R3387

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

J3300

20875-056E-01

F-ST-SM

PWR

SIGNAL

PWR

GND

5857

21
43
65
87
109
1211
1413
1615
1817
2019
2221
2423
2625
2827
3029
3231
3433
3635
3837
4039
4241
4443
4645
4847
5049
5251
5453
5655

6059

6261
6463
6665
6867
7069
7271
7473
7675
7877
8079
8281
8483
8685

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

USBC_X_R2D_N<2>

USBC_X_R2D_P<2>

USBC_X_D2R_CR_N<2>

USBC_X_D2R_CR_P<2>

USBC_T_R2D_P<1>

USBC_T_D2R_CR_P<1>

USBC_T_D2R_CR_N<1>

TP_USBC_PP20V_T

201MF1/20W5%

220K

1

2

R3396

220K

1

2

R3377

220K

GND_VOID=TRUE

R3397

220K

GND_VOID=TRUE

MF1/20W 2015%

R3376

GND_VOID=TRUE

1

1/20W MF 2015%

2

GND_VOID=TRUE

1

1/20W 2015% MF

2

0.22UF

X5R

0.22UF

0.33UF

0.33UF

CER-X5R

2015%

220K

1

2

R3394

220K

MF1/20W

GND_VOID=TRUE

R3395

0.22UF

0.22UF

0.33UF

0.33UF

CER-X5R

201MF

220K

1

2

R3375

220K

GND_VOID=TRUE

1/20W5%

R3374

GND_VOID=TRUE

1

2

GND_VOID=TRUE

1

2

GND_VOID=TRUE

21

10% 25V 0201

21

GND_VOID=TRUE

GND_VOID=TRUE

21

21

GND_VOID=TRUE

1/20W 201MF5%

GND_VOID=TRUE

21

21

10%X5R

GND_VOID=TRUE

GND_VOID=TRUE

21

10%CER-X5R 020125V

21

10% 25V 0201

GND_VOID=TRUE

1/20W MF5% 201

C3391
C3390

020125V10%X5R

C3393

25V 0201CER-X5R 10%

C3392

020125V10%

C3370

0201X5R 10%

25V

C3371

020125V

C3372
C3373

USBC_X_R2D_C_N<2>

USBC_X_D2R_R_N<2>

USBC_X_D2R_R_P<2>

2

1

CRITICAL

2

5.5V-6.2PF

0201-THICKSTNCL

D3396

1

CRITICAL

X3DFN2

D3394

ESD8011-COMBO

USBC_T_R2D_C_P<1>

USBC_T_R2D_C_N<1>

USBC_T_D2R_R_P<1>

USBC_T_D2R_R_N<1>

2

1

CRITICAL

2

5.5V-6.2PF

0201-THICKSTNCL

D3377

1

CRITICAL

X3DFN2

D3374

ESD8011-COMBO

GND_VOID=TRUE

R3391

5%

2

2

1/20W MF 2015%

GND_VOID=TRUE

21

MF1/20W 201

R3390

21

USBC_X_R2D_CR_N<2>

USBC_X_R2D_CR_P<2>USBC_X_R2D_C_P<2>

USBC_X_USB_TOP_P
USBC_X_USB_TOP_N

GND_VOID=TRUE

R3393

1/20W5% MF2201

2

1/20W

GND_VOID=TRUE

2

1

CRITICAL

2

X3DFN2

D3395

1

CRITICAL

D3397

21

R3392

21

201MF5%

GND_VOID=TRUE

2

5.5V-6.2PF

0201-THICKSTNCL

1

SLP0603P2X3-COMBO

CRITICAL

2

RCLAMP1031ZC

1

D3391

USBC_X_D2R_N<2>

USBC_X_D2R_P<2>

SLP0603P2X3-COMBO

GND_VOID=TRUE

CRITICAL

RCLAMP1031ZC

D3390

ESD8011-COMBO

GND_VOID=TRUE

R3370

2

2

GND_VOID=TRUE

21

201MF5% 1/20W

R3371

21

201MF5% 1/20W

USBC_T_R2D_CR_P<1>

USBC_T_R2D_CR_N<1>USBC_T_R2D_N<1>

USBC_T_USB_TOP_P
USBC_T_USB_TOP_N

GND_VOID=TRUE

R3372

2

2

GND_VOID=TRUE

2

1

CRITICAL

2

X3DFN2

D3375

1

CRITICAL

D3376

21

201MF5% 1/20W

R3373

21

201MF1/20W5%

GND_VOID=TRUE

2

5.5V-6.2PF

0201-THICKSTNCL

1

SLP0603P2X3-COMBO

CRITICAL

2

RCLAMP1031ZC

1

D3370

USBC_T_D2R_P<1>

USBC_T_D2R_N<1>

SLP0603P2X3-COMBO

CRITICAL

GND_VOID=TRUE

RCLAMP1031ZC

D3371

ESD8011-COMBO

USBC_X_CC2

USBC_X_SBU1

SLP0603P2X3-COMBO

GND_VOID=TRUE

1

CRITICAL

2

RCLAMP1031ZC

1

D3393

2

USBC_T_SBU2

USBC_T_CC1

SLP0603P2X3-COMBO

CRITICAL

GND_VOID=TRUE

2

1

2

RCLAMP1031ZC

1

D3372

24 23

IN

IN

24

24

OUT

OUT

24

SLP0603P2X3-COMBO

GND_VOID=TRUE

CRITICAL

RCLAMP1031ZC

D3392

25

IN

IN

25

25

OUT

OUT

25 23

SLP0603P2X3-COMBO

CRITICAL

GND_VOID=TRUE

RCLAMP1031ZC

D3373

21

21

21

21

C

22

22

22

22

B

A

79 78 23

PP20V_USBC_T_VBUS

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000

VOLTAGE=20V

SDM2U40CSP

Left Front Port

CRITICAL

D3300

X3-WLB1608-1

FOR POR, VERIFY 20% TOLERANCE ON 0.22UF AC COUPLING CAP IS OK

BYPASS=J3300.59::10MM

K

PLACE_NEAR=J3300.59:5MM

D3302

TVS2200

WSON

4

A

IN

5

IN

6

IN

GND

GND

GND

1

2

EPAD

7

3

CRITICAL

1

C3300

0.01UF

10%
25V

2

X5R-CERM
0201

BYPASS=J3300.59::10MM

CRITICAL

1

C3306

0.01UF

10%
25V

2

X5R-CERM
0201

BYPASS=J3300.59::10MM

CRITICAL

1

C3301

0.01UF

10%
25V

2

X5R-CERM
0201

BYPASS=J3300.59::10MM

CRITICAL

1

C3307

0.01UF

10%
25V

2

X5R-CERM
0201

PLACE VBUS CAP NEAR EACH VBUS PIN

BYPASS=J3300.59::10MM

CRITICAL

1

C3302

0.01UF

10%
25V

2

X5R-CERM
0201

BYPASS=J3300.59::10MM

CRITICAL

1

C3308

0.01UF

10%
25V

2

X5R-CERM
0201

BYPASS=J3300.59::10MM

CRITICAL

1

C3303

0.01UF

10%
25V

2

X5R-CERM
0201

BYPASS=J3300.59::10MM

CRITICAL

1

C3305

0.01UF

10%
25V

2

X5R-CERM
0201

Cowling Bosses

860-01443

SH3300

3.1OD1.65ID-1.12H-SM3.1OD1.65ID-1.12H-SM

1

SH3301

1

BOM_COST_GROUP=USB-C

DESIGN: J230/MLB
LAST CHANGE: Mon Oct 1 21:40:18 2018

SYNC_MASTER=X1032_MLB_P4BP SYNC_DATE=02/13/2017

PAGE TITLE

USB-C CONNECTOR

SIZE

D

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

051-05232

REVISION

2.0.0

BRANCH

proto4b

PAGE

33 OF 152

SHEET

26 OF 86

A

8

67

35 4

2

1

678

www.laptoprepairsecrets.com

3 245

1

D

a

bi

bii

a

bi

bii

c

BOMOPTION

BSB XA SX Rail

VOUTLV_SW_CALPE

SWSW_VOUTLV

LD-SW

SWSW_FORCEPWR

BOMOPTION

BSB XA SX Rail

VOUTLV_SW_CALPE ACE2 VOUT_LV

SWSW_VOUTLV

SWSW_FORCEPWR

LD-SW

LD-SW

BSB XA S0 Rail

LD-SW

LD-SW

LD-SW

BSB XA S0 Rail

LD-SW

LD-SW ACE2 VOUT_LV

LD-SW

BSB_XA_PWR BSB XA SX Rail BSB XA S0 Rail

Load Switch Enable

CALPE/SMCACE2 VOUT_LV

ACE2 VOUT_LV

ACE2/PCH FORCEPWRLD-SW

Load Switch Enable

CALPE/SMC

ACE2/PCH FORCEPWR

---

113S0022 1

113S0022 1

113S0022 2

2113S0022

113S0022

113S0022

2

3

2113S0022

RES,MF,1A MAX,0OHM,5,0603,SMD,LF

RES,MF,1A MAX,0OHM,5,0603,SMD,LF

RES,MF,1A MAX,0OHM,5,0603,SMD,LF

RES,MF,1A MAX,0OHM,5,0603,SMD,LF

RES,MF,1A MAX,0OHM,5,0603,SMD,LF

RES,MF,1A MAX,0OHM,5,0603,SMD,LF

RES,MF,1A MAX,0OHM,5,0603,SMD,LF

R3412

R3411

R3411,R3412

R3415,R3416

R3414,R3416

R3414,R3415,R3416

R3417,R3442

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

BSB_X_PWR:VOUTLV_SW_CALPE

BSB_X_PWR:SWSW_VOUTLV

BSB_X_PWR:SWSW_FORCEPWR

BSB_X_PWR:VOUTLV_SW_CALPE

BSB_X_PWR:SWSW_VOUTLV

BSB_X_PWR:SWSW_FORCEPWR

BSB_T_PWR:BSB_X_PWR

117S0201

117S0201

1117S0201

1117S0201

1

1

RES,MF,1A MAX,0.0 OHM,5%,0201,BLACK

RES,MF,1A MAX,0.0 OHM,5%,0201,BLACK

RES,MF,1A MAX,0.0 OHM,5%,0201,BLACK

RES,MF,1A MAX,0.0 OHM,5%,0201,BLACK

R3440

R3440

R3440

R3441

BSB_T_PWR:VOUTLV_SW_CALPE

BSB_T_PWR:SWSW_VOUTLV

BSB_T_PWR:SWSW_FORCEPWR

BSB_T_PWR:BSB_X_PWR

D

C

79 78 67 27

67 24

23 24 75

PP3V3_G3H_RTC

PP3V3_TBT_X_S0_R

PP3V3_UPC_X_VOUTLV

OMIT_TABLE

R3411

0

21

5%
1/10W
MF-LF

603

OMIT_TABLE

NOSTUFF

R3410

0

5%
1/10W
MF-LF

603

R3412

0

5%
1/10W
MF-LF

603

NOSTUFF

21

PP3V3_TBT_X_SX

MAKE_BASE=TRUE

21

PP3V3_TBT_X_SX

21 23

OMIT_TABLE

1

R3442

0

5%
1/10W
MF-LF
603

2

C

B

67 27

67 25

79 78 67 27

25 75

PP3V3_TBT_T_S0_R

PP3V3_UPC_T_VOUTLV

PP3V3_TBT_X_S0_R

PP3V3_G3H_RTC

OMIT_TABLE

R3414

0

5%
1/10W
MF-LF

603

R3413

0

5%
1/10W
MF-LF

603

21

OMIT_TABLE

R3415

0

5%
1/10W
MF-LF

603

21

PP3V3_TBT_T_SX

MAKE_BASE=TRUE

21

PP3V3_TBT_T_SX

22

R3418

0

5%
1/10W
MF-LF

603

21

PP3V3_TBT_X_S0

79

MAKE_BASE=TRUE

PP3V3_TBT_X_S0

21 23

B

A

67 27

PP3V3_TBT_T_S0_R

24

IN

USBC_X_RESET_L

SPI ACE

25

IN

USBC_T_RST_L

UART ACE

OMIT_TABLE

R3416

0

21

5%
1/10W
MF-LF

603

MAKE_BASE=TRUE

OMIT_TABLE

1

R3417

0

5%
1/10W
MF-LF
603

2

MAKE_BASE=TRUE

OMIT_TABLE

R3440

0

5%

1/20W

MF

0201

PP3V3_TBT_T_S0

MAKE_BASE=TRUE

USBC_X_RESET_L

OUT

21

PP3V3_TBT_T_S0

22 23

OMIT_TABLE

1

R3441

0

5%
1/20W
MF
0201

21

2

USBC_T_RESET_LUSBC_T_RST_L

Bridges

OUT

22

PAGE TITLE

SYNC_DATE=06/11/2018

A

USB-C DEV SUPPORT

SIZE

D

BOM_COST_GROUP=USB-C

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

051-05232

REVISION

2.0.0

BRANCH

proto4b

PAGE

34 OF 152

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27 OF 86

8

67

35 4

2

1

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3 245

1

Wireless Desense CapacitorsA

D

30 29

64 30 29

64 30 29

BT_GPIO_1

IN

1

C3620

12PF

5%
25V

2

CERM
0201

WLAN_PWR_EN PCH_WLAN_CLKREQ_R_L

IN

1

C3624

12PF

5%
25V

2

CERM
0201

BT_PWR_EN

IN

1

C3634

12PF

5%
25V

2

CERM
0201

1

C3621

3PF

+/-0.1PF
25V

2

C0G
0201

1

C3625

3PF

+/-0.1PF
25V

2

C0G
0201

1

C3635

3PF

+/-0.1PF
25V

2

C0G
0201

30 29

30 29 18 6

OUT

IN

1

C3632

12PF

5%
25V

2

CERM
0201

PCH_WLAN_PERST_L

1

C3636

12PF

5%
25V

2

CERM
0201

1

C3633

3PF

+/-0.1PF
25V

2

C0G
0201

1

C3637

3PF

+/-0.1PF
25V

2

C0G
0201

D

C

30 29

PMU_CLK32K_WLANBT

OUT IN

R3629

33

21

201MF1/20W5%

PMU_CLK32K_WLANBT_R

64

C

B

B

A

8

67

A

SYNC_MASTER=j140

PAGE TITLE

SYNC_DATE=09/20/2018

WIFI/BT Desense

DRAWING NUMBER

051-05232

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=WIRELESS

35 4

IV ALL RIGHTS RESERVED

2

REVISION

2.0.0

BRANCH

proto4b

PAGE

36 OF 152

SHEET

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1

SIZE

D

678

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3 245

1

D

C

B

A

78 29

Bluetooth SPI Debug

SPI_BT_MISO

WIFI_DBG

SPI_BT_MOSI

78 29

WIFI_DBG

SPI_BT_CLK

78 29

WIFI_DBG

SPI_BT_CS_L

78 29

WIFI_DBG

B

Boot Straps

PP3V3_G3S_WLANBT

45 75

PLACE_NEAR=U3701.16:2MM

PLACE_NEAR=U3701.6:2MM

1

2

PLACE_NEAR=U3701.16:2MM

1

2

PLACE_NEAR=U3701.16:2MM

C3724

10UF

20%

6.3V
CERM
0402

PLACE_NEAR=U3701.6:2MM

C3713

12PF

5%
25V
CERM
0201

R3783

0

1/20W MF 02015%

21

SPI_BT_MISO_R

R3784

0

21

MF1/20W

SPI_BT_MOSI_R

02015%

R3781

0

1/20W

5% MF 0201

21

SPI_BT_CLK_R

R3782

0

21

MF 02015%1/20W

PP1V8_G3S

29 75

WLAN_SROM_STRAP BT_INTERFACE_SEL

29 29

WLAN_SROM_STRAP:
LOW: OTP
HIGH: SROM

TP_WLAN_JTAG_SEL

29

10K

5%

1/20W

MF

201

1

2

R3700

SPI_BT_CS_L_R

1

R3702

1K

0.5%
1/20W
MF
0201

2

WLAN_SROM_SIZE

29

NOSTUFF

BT_INTERFACE_SEL
LOW: (DEFAULT): PCIE
HIGH: UART

1

C3725

10UF 10UF

20%

6.3V

2

CERM
0402

1

C3714

3PF

+/-0.1PF
25V

2

C0G
0201

30

30

30

30

R3713

10K

1/20W

1

R3705

1K

0.5%
1/20W
MF
0201

2

PLACE_NEAR=U3701.76:2MM

1

C3721

10UF

20%

6.3V

2

CERM
0402

PLACE_NEAR=U3701.28:2MM

PLACE_NEAR=U3701.28:2MM

PLACE_NEAR=U3701.6:2MM

1

C3716

3PF

+/-0.1PF
25V

2

C0G
0201

29 75

5%
MF

201

1

C3715

12PF

5%
25V

2

CERM
0201

1

2

PLACE_NEAR=U3701.28:2MM

1

C3722

20%

6.3V

2

CERM
0402

1

C3717

12PF

5%
25V

2

CERM
0201

PP1V8_G3S

WLANBT_HOST_WAKE TOGGLES FOR
BOTH BT AND WLAN WAKE

33 30

33 30

33 30

33 30

C

66

65

64

PLACE_NEAR=U3701.76:2MM

IN
OUT
IN
OUT

1

C3718

3PF

+/-0.1PF
25V

2

C0G
0201

78 30 29 18

STRAP PINS

PLACE_NEAR=U3701.76:2MM

1

C3719

12PF

5%
25V

2

CERM
0201

30

BI

30

BI

1

R3715

100K

5%
1/20W
MF
201

2

30 29

30 29

33 30 29

OUT

IN
IN

IN

1

R3714

100K

5%
1/20W
MF
201

2

29

29

29

29

29

29

30 28

78 32 30

64 30 28

1

C3720

3PF

+/-0.1PF
25V

2

C0G
0201

50_ANT_C0
50_ANT_C1

WLAN_SROM_CLK
WLAN_SROM_CS_R

29

78 29

78 29

WLAN_SROM_DIN
WLAN_SROM_DOUT

UART_WLAN_R2D_RTS_L
UART_WLAN_D2R_CTS_L
UART_WLAN_R2D
UART_WLAN_D2R

WLAN_AUDIO_SYNC
WLAN_JTAG_TDI

WLAN_JTAG_TDO
TP_WLAN_JTAG_SEL

TP_WLAN_JTAG_TCK
WLAN_THROTTLE
TP_WLAN_JTAG_TRST_L

BT_INTERFACE_SEL
WLAN_SROM_STRAP
WLAN_SROM_SIZE

PMU_CLK32K_WLANBT

IN

WLANBT_HOST_WAKE

OUT

WLAN_PWR_EN

IN

NC

NC

24
80

141
142

68
69

46
43
44
45

121

57
59

70
143
132
133
131

136

60

61

120

109

56

110

ANT_C0
ANT_C1

SPROM_CLK
SPROM_CS
SPROM_MI
SPROM_MO

WL_FAST_UART_CTS
WL_FAST_UART_RTS
WL_FAST_UART_RX
WL_FAST_UART_TX

WLAN_TIME_SYNC

CXT_A/JTAG_TD1
CXT_B/JTAG_TDO
JTAG_SEL
JTAG_SEL_BS
JTAG_TCK
JTAG_TMS
JTAG_TRST*

GPIO_14
GPIO_17
GPIO_20

LHL_GPIO2

LPO_IN

WL_HOST_WAKE

WL_REG_ON

VBAT

VBAT

VBAT

GPIO13
GPIO15
GPIO18
GPIO19

DO NOT CONNECT
GPIO2 (HI-Z)
GPIO3 (HI-Z)
GPIO6 (HI-Z)

(HI-Z)
(HI-Z)
(HI-Z, WEAK PU <1SEC )

PD 50K

PCIe DC Blocking Caps

PLACE C3706 AND C3707 ON THE BOTTOM SIDE FOR PCIE PROBE ACCESS

PCIE_PCH_WLAN_D2R_C_N

29

PCIE_PCH_WLAN_D2R_C_P

29

PLACE C3708 AND C3709 ON THE BOTTOM SIDE FOR PCIE PROBE ACCESS

PCIE_PCH_WLAN_R2D_N

29

C3706

C3707

C3708

U3701.124:8MM

2 1

10%

U3701.49:8MM

2 1

U3701.126:8MM

2 1

10% 6.3V CERM-X5R 0201

0.1UF

6.3V 0201CERM-X5R

0.1UF

6.3V

0.1UF

PCIE_PCH_WLAN_D2R_N

PCIE_PCH_WLAN_D2R_P

0201CERM-X5R10%

PCIE_PCH_WLAN_R2D_C_N

29

28

7

6

17

16

139

138

137

VBAT

VBAT

VBAT

VBAT_5GHZ_C0

VBAT_2P4GHZ_BTPA

VBAT_2P4GHZ_C0C1

VBAT_2P4GHZ_C0C1

VBAT_2P4GHZ_BTPA

SAPPORO - ES3.X

U3701

LBEE5XV1SA-255

LGA

SYM 1 OF 4

OMIT_TABLE

CRITICAL

GPIO10 (HI-Z)
GPIO11 (HI-Z)
GPIO8 (HI-Z)
GPIO9 (HI-Z)

GPIO12 (HI-Z)

GPIO4 (HI-Z)
GPIO5 (HI-Z)

GPIO0 (HI-Z)

PU 50K
PU 50K
PU 50K
PU 50K

PD 50K
PD 50K
PU 50K
PU 50K

PD 50K
PD 50K
PD 50K
PD 50K

PD 50K

PD 50K

PD 50K

0.1UF SHUNT CAPACITORS FOR FEM BIAS PINS ARE INSIDE THE MODULE

144

71

77

76

VDDIO_1P8V

VBAT_5GHZ_C0

VBAT_5GHZ_C1

VBAT_5GHZ_C1

PCIE_REFCLK_N
PCIE_REFCLK_P

PCIE_RXD_N
PCIE_RXD_P
PCIE_TXD_N
PCIE_TXD_P

PCIE_CLKREQ*

PCIE_PERST*

PD 50K
PD 50K
PD 50K
PD 50K

BT_SF_CLK

BT_SF_CS*
BT_SF_MISO
BT_SF_MOSI

BT_UART_CTS*
BT_UART_RTS*

BT_UART_RX
BT_UART_TX

BT_GPIO_2
BT_GPIO_3
BT_GPIO_4
BT_GPIO_5

BT_I2S_CLK

BT_I2S_DI
BT_I2S_DO
BT_I2S_WS

BT_DEV_WAKE

BT_HOST_WAKE

BT_REG_ON

OUT

OUT

IN

PP1V8_G3S

VDDIO_1P8V

PCI_PME*

30 28

15

15

15

PLACE_NEAR=U3701.71:1MM

1

C3723

0.1UF

10%

6.3V

2

CERM-X5R
0201

128

PCIE_CLK100M_PCH_WLAN_N

53

PCIE_CLK100M_PCH_WLAN_P

126

PCIE_PCH_WLAN_R2D_N

51

PCIE_PCH_WLAN_R2D_P

124

PCIE_PCH_WLAN_D2R_C_N

49

PCIE_PCH_WLAN_D2R_C_P

135

PCIE_PME_L

58

PCH_WLAN_CLKREQ_R_L

134

PCH_WLAN_PERST_L

114
113
115
37

117
40
39
119

36
112
38
116

34
35
32
33

118

42

111

SPI_BT_CLK
SPI_BT_CS_L
SPI_BT_MISO
SPI_BT_MOSI

NC
NC
NC
NC

BT_GPIO_2

30

BT_AUDIO_SYNC
TP_BT_GPIO_4
TP_BT_GPIO_5

UART_BT_LH_D2R
NC_I2S_BT_R2D
NC_I2S_BT_D2R
UART_BT_LH_R2D

BT_GPIO_0

BT_DEV_WAKE NOT TOGGLED WHEN
BT OVER PCIE ENABLED

BT_GPIO_1

WLAN_HOST_WAKE TOGGLES FOR
BOTH BT AND WLAN WAKE

BT_PWR_EN_R

BT_PWR_EN DISCONNECTED FOR
BT OVER PCIE

29 75

1

C3700

12PF

5%
25V

2

CERM
0201

1

C3704

3PF

+/-0.1PF
25V

2

C0G
0201

D

TP3717

UART_BT_LH_D2R

29

UART_BT_LH_R2D

29

TP_BT_GPIO_5

IN
IN

29

29

29

29

29

R3711

1/20W 5% 201

IN

78 29

78 29

78 29

78 29

29 15

29 15

21

1K

MF

30 28 18 6

BT_SFLASH_STRAP
HIGH: SFLASH
LOW: NO SFLASH

PCH_WLAN_CLKREQ_L

15

BI

(TP_WLAN_JTAG_TMS)

R3706

0

21

29

29

OUT

OUT

IN

IN

OUT

29

29

30

1/20W

30 29 18

30 28

NOSTUFF

PCH_BT_ROM_BOOT_L

MF5% 0201

IN

6

29

TP_BT_GPIO_4

29

PCIE_PME_L

29

TP_WLAN_JTAG_TRST_L

29

WLAN_THROTTLE

TP_WLAN_JTAG_TCK

29

TP_WLAN_JTAG_SEL

29

(TP_WLAN_JTAG_TDO)

30 29

30 29

78 29

78 29

78 29

78 29

WLAN_JTAG_TDO

(TP_WLAN_JTAG_TDI)

WLAN_JTAG_TDI

WLAN_SROM_CLK

WLAN_SROM_CS

WLAN_SROM_DIN

WLAN_SROM_DOUT

R3716

0

21

1/20W MF

5% 0201

NOSTUFF

BT_PWR_EN

PLACE TP3701 AND TP3702 ON THE BOTTOM SIDE FOR PCIE PROBE ACCESS

IN

64 30 28

PCIE_CLK100M_PCH_WLAN_N

29 15

PCIE_CLK100M_PCH_WLAN_P

29 15

78 30 29 18

30 29 18

WLAN_AUDIO_SYNC

BT_AUDIO_SYNC

1

TP3716

1

TP3715

1

TP3714

1

TP3713

1

TP3712

1

TP3711

1

TP3710

1

TP3709

1

TP3708

1

TP3707

1

TP3706

1

TP3705

1

TP3704

1

TP3703

1

TP3701

TP3702

TP3718

1

TP3719

1

TP-P5

TP-P5

TP-P5

TP-P5

TP-P5

TP-P5

TP-P5

TP-P5

TP-P5

TP-P5

TP-P5

TP-P5

TP-P5

TP-P5

TP-P5

P2MM

SM

1

PP

P2MM

SM

1

PP

TP-P5

TP-P5

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

C

B

A

WLAN Serial EEPROM

WLAN_SROM_CS_R

29

10K

5%
MF

201

1

2

R3717

1/20W

WLAN_JTAG_SEL:
LOW: Some JTAG are GPIOs
HIGH: JTAG Enabled

PP1V8_G3S

29 75

R3718

1/20W1K0.5% MF 0201

2 1

78 29

78 29

WLAN_SROM_DOUT

78

WLAN_SROM_CS

29

WLAN_SROM_CLK

NC

WLAN_SROM_SIZE:
LOW: 16 KBIT
HIGH: 4 KBIT

8

VCC

U3710

CAS93C86B

UDFN8

1

CS

2

SK

7

PE

OMIT_TABLE

5

ORG

EPADGND

9

U3701.51:8MM

0.1UF

10% 0201

6.3V CERM-X5R

1

2

R3752

100K100K

1/20W

201

R3751

5%

1/20W

MF

201

5%
MF

1

2

BT_SFLASH_CS_LSPI_BT_CS_L
BT_SFLASH_WP_L
BT_SFLASH_HOLD_L

IN

6

SCLK

1

CS*

3

WP*/SIO2

7

HOLD*/SIO3

15

8

VCC

U3750

4MBIT-1.8V

MX25U4035FZUI

USON

OMIT_TABLE

GND

4

SI/SIO0

SO/SIO1

THRM

PAD

9

PLACE_NEAR=U3750.8:2.8MM

5

SPI_BT_MOSI

2

SPI_BT_MISO

PLACE_NEAR=U3750.8:4MM

1

C3710

0.1UF

10%

6.3V

2

CERM-X5R
0201

78 29

78 29

BOM_COST_GROUP=WIRELESS

1

C3712

10UF

20%

6.3V

2

CERM
0402

SYNC_MASTER=J213_METE

PAGE TITLE

WIFI/BT MODULE 1

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

051-05232

REVISION

2.0.0

BRANCH

proto4b

PAGE

37 OF 152

SHEET

29 OF 86

SYNC_DATE=11/04/2018

SIZE

D

A

10K

5%

1/20W

MF

201

21

2 1

1

2

PCIE_PCH_WLAN_R2D_P PCIE_PCH_WLAN_R2D_C_P

29

ED

PLACE_NEAR=U3710.8:2MM

1

C3711

0.1UF

10%

6.3V

2

CERM-X5R
0201

43

DODI

WLAN_SROM_DIN

6

WLAN_SROM_ORG

R3712

1/20W

78 29

10K

5%
MF

201

1

2

Bluetooth Serial Flash

29 75

78 29

78 29

SPI_BT_CLK

C3709

PP1V8_G3S

R3753

R3754

1K

1/20W MF5% 201

8

67

35 4

2

1

678

www.laptoprepairsecrets.com

3 245

1

D

C

B

A

10
11
12
13
14
15
18
19
20
21
22
23
25
26
27
30
31
41
47
48
50
52
54
55
62
63
67
72
73
74
75
78
79
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98

99
100
101
102
103
104
105
106
107
108
122
123
125
127
129
130
140
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159

U3701

LBEE5XV1SA-255

LGA

1

GND

2

GND

3

GND

4

GND

5

GND

8

GND

9

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

SYM 2 OF 4

OMIT_TABLE

CRITICAL

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249

250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

LBEE5XV1SA-255

U3701

LGA

SYM 3 OF 4

OMIT_TABLE

CRITICAL

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429

430
431
432
433
434
435
436
437
438
439
440
441
442

LBEE5XV1SA-255

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

U3701

LGA

SYM 4 OF 4

OMIT_TABLE

CRITICAL

GND
GND
GND
GND
GND
GND
GND
GND
GND

443
444
445
446
447
448
449
450
451

A

C

RF Connectors WiFi/BT Debug Connectors

CRITICAL

J3810

IR050D15010C

F-ST-SM

1

50_ANT_C0

4

3

2

BI

29

CRITICAL

J3820

IR050D15010C

F-ST-SM

1

50_ANT_C1

4

3

2

BI

29

WiFi/Bluetooth Straps

R3806

R3805

1/20W MF

R3804

R3803

1/20W MF

R3802

1/20W

R3801

1/20W 5%

201

21

MF1/20W 5%

201

21

201

21

MF 5%1/20W

201

21

201

21

MF 5%

201

21

MF

100K

100K

5%

100K

100K

5%

100K

NOSTUFF

100K

NOSTUFF

BT_GPIO_0

WLAN_THROTTLE

WLAN_JTAG_TDI

WLAN_JTAG_TDO

BT_GPIO_1

WLANBT_HOST_WAKE

29

B

J3850

505070-1222

M-ST-SM

1413

21

29

29

30 29

30 29 28

64 29 28

BI
BI
BI
BI
BI

SPI_BT_MISO_R
BT_GPIO_2
BT_GPIO_0
BT_GPIO_1
BT_PWR_EN

NC

15

WIFI_DBG

J3860

505070-1222

M-ST-SM

30 29 33 29

33 30 29

78 32 30 29

64 29 28

29 28 18 6

30 29

33 30 29

30 29

30 29 28

78 32 30 29

WLAN_JTAG_TDI UART_WLAN_R2D_RTS_L
WLAN_THROTTLE
WLANBT_HOST_WAKE
WLAN_PWR_EN
PCH_WLAN_PERST_L

15

WIFI_DBG

PLACE J3850 AND J3860 ON THE BOTTOM SIDE

PAGE TITLE

SPI_BT_MOSI_R

43

SPI_BT_CS_L_R

65

SPI_BT_CLK_R

87
109

BT_AUDIO_SYNC

1211

16

1413

21

UART_WLAN_D2RUART_WLAN_R2D

43
65

UART_WLAN_D2R_CTS_L

87

PCH_WLAN_CLKREQ_R_L

109

WLAN_AUDIO_SYNC

1211

PMU_CLK32K_WLANBT

16

NC

NC

BI
BI
BI

BI

29

29

29

29 18

WIFI/BT MODULE 2

Apple Inc.

33 29 33 29

33 29

29 28

78 29 18

29 28

DRAWING NUMBER

051-05232

REVISION

SYNC_DATE=10/17/2018SYNC_MASTER=J213_METE

D

C

B

A

SIZE

D

2.0.0

BRANCH

proto4b

PAGE

38 OF 152

SHEET

30 OF 86

BOM_COST_GROUP=WIRELESS

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

8

67

35 4

2

1

Note 1) IPU represents SW configured state, not HW default

www.laptoprepairsecrets.com

678

3 245

1

D

C

76

76

76

78 52 49

41

13

78 49

78 49 40

76

39

78 50 49

78 50 49

39

54

71 70

41

39

39

39

40

76

OUT
OUT
OUT

IN

OUT

IN

IN
OUT
OUT

IN

IN
OUT

IN
OUT
OUT
OUT

IN

IN

IN
OUT

IN

NC_PLCAM_TX_THROTTLE
NC_GNSS_HOST_TIME
NC_GNSS_DEV_WAKE
CODEC_INT_L
SE_CTLR_FW_DWLD
PCH_SOC_SYNC
MESA_INT
MESA_PWR_EN
NC_WLAN_DEV_WAKE
BOARD_REV0
SPKRAMP_INT_L
SPKRAMP_RESET_L
BOARD_REV1
TPAD_SPI_EN
SSD_BFH
SE_DEV_WAKE
BOOT_CONFIG0
BOOT_CONFIG1
BOOT_CONFIG2
SSD_PMU_RESET_L
NC_DFR_DISP_INT

A13
A12
B12

AJ36

R36
AB36
AC36

V34

V36
AA36

U36

U35

V32

R32

L36

M33

J33

P33

K32

J32
AA34

GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
GPIO20

(IPD)
(IPD)

(IPU)

(IPD)

OMIT_TABLE

CRITICAL

U3900

H9M

BGA

SYM 3 OF 18

GPIO/TEST/MISC

(IPD)

(IPD)

TMR32_PWM0
TMR32_PWM1
TMR32_PWM2

CFSB

FORCE_DFU

DFU_STATUS

HOLD_RESET

ANALOGMUX_OUT

TST_CLKOUT

TESTMODE

DROOP

SOCHOT

XO0
XI0

L33
L35
K36

K34

W32
V33

J34

AN36
P32
C12

L32
L34

AV23
AV24

NC_TMR32_PWM0
NC_TMR32_PWM1
SOC_KBD_BKLT_PWM

PMU_ACTIVE_READY
SOC_FORCE_DFU

SOC_DFU_STATUS
SOC_HOLD_RESET
TP_SOC_AMUXOUT

TP_SOC_TST_CLKOUT
SOC_TESTMODE

PMU_DROOP_L
SOC_SOCHOT_L

SOC_XTAL24M_OUT
SOC_XTAL24M_IN

51

OUT

IN

IN

OUT

40

IN

40

IN

64

IN

OUT

78

1

R3940

511K

1%
1/20W
MF
201

2

78 64 23

64 31

81 78 64 23

81 78 40 23

R3941

21

SOC_XTAL24M_OUT_R

0

24MHZ-30PPM-9.5PF-60OHM

02011/20W 5% MF

Y3940

1.60X1.20MM-SM

D

C

B

39

39

40

40

40

78 23

78 23

78 23

BI
OUT

OUT
OUT
OUT

BI
BI

IN

I2C_SEP_SDA
I2C_SEP_SCL

SEP_CAM_DISABLE_L
SEP_DMIC_DISABLE_L
SEP_DISABLE_STROBE

USB_SOC_P
USB_SOC_N

TP_SOC_USB_ID
SOC_USB_VBUS
SOC_USB_REXT

1

R3960

200

1%
1/20W
MF
201

2

AV8

SEP_I2C0_SDA

AT7

SEP_I2C0_SCL

AU9

SEP_SPI0_MISO

AV9

SEP_SPI0_MOSI

AT8

SEP_SPI0_SCLK

B23

USB_DP

A23

USB_DM

D23

USB_ID

E23

USB_VBUS

F22

USB_REXT

(IPD)

OMIT_TABLE

CRITICAL

U3900

H9M

BGA

SYM 7 OF 18
SEP/USB/DDR

DDR0_RREF
DDR1_RREF
DDR2_RREF
DDR3_RREF

DDR0_ZQ
DDR3_ZQ

DDR0_RET*
DDR1_RET*
DDR2_RET*
DDR3_RET*

DDR0_SYS_ALIVE
DDR1_SYS_ALIVE
DDR2_SYS_ALIVE
DDR3_SYS_ALIVE

H3
H35
AL3
AL35

N2
AF36

H4
H34
AL4
AL34

G3
G35
AM3
AM35

1%
MF

201

1

2

R3970

1/20W

SOC_DDR0_RREF
SOC_DDR1_RREF
SOC_DDR2_RREF
SOC_DDR3_RREF

SOC_DDR0_ZQ
SOC_DDR3_ZQ

AON_SLEEP1_RESET_L

PMU_SYS_ALIVE

R3971

240240

1%

1/20W

MF

IN

IN

1

2

32

C3940

R3972

240

1%

1/20W

MF

201201

73 64 32

12PF

CERM
0201

1

2

1

5%

25V

2

R3973

240

1/20W

1%
MF

201

NC GND

4312

1

R3974

2

1

2

240

1%

1/20W

MF

201

C3941

12PF

5%
25V
CERM
0201

1

R3975

2

240

1%

1/20W

MF

201

PP1V1_SLPDDR

1

2

74

B

A

PP1V8_SLPS2R

R3939

47K

8

21

5% 201

40 74

MF1/20W

SOC_SOCHOT_L

78 64 31

67

SYNC_MASTER=X589_BIGSUR SYNC_DATE=03/15/2017

PAGE TITLE

A

SoC GPIO/SEP/USB/DDR/Test

DRAWING NUMBER

051-05232

Apple Inc.

REVISION

2.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=T290

35 4

IV ALL RIGHTS RESERVED

2

BRANCH

proto4b

PAGE

39 OF 152

SHEET

31 OF 86

1

SIZE

D

D

www.laptoprepairsecrets.com

678

3 245

1

OMIT_TABLE

CRITICAL

U3900

H9M

BGA

SYM 6 OF 18

AOP

(IPU)
(IPU)
(IPU)

(IPD)
(IPD)

AOP_PDM_CLK0
AOP_PDM_CLK1
AOP_PDM_CLK2
AOP_PDM_CLK3
AOP_PDM_CLK4

AOP_PDM_DATA0
AOP_PDM_DATA1

AOP_SPI_MOSI
AOP_SPI_SCLK
AOP_SPI_MISO

P6
K2
J6
L6
L5

J5
K4

D2
F2
E2

PDM_DMIC_CLK0_R
PDM_DMIC_CLK1_R
TP_SMC_FIXTURE_MODE_L
NC_PLCAM_PROX_INT_L
NC_PLCAM_ROMEO_B2B_DETECT

PDM_DMIC_DATA0
PDM_DMIC_DATA1

NC_SPI_AOP_SENSOR_MOSI_R
NC_SPI_AOP_SENSOR_CLK_R
NC_SPI_AOP_SENSOR_MISO

OUT
OUT

IN
IN
IN

IN
IN

OUT
OUT

IN

40

40

78

76

76

52

52

D

40

18 6

76

76

43

43

OUT
OUT

IN
IN
IN
IN

IN
OUT
OUT

OUT
BI

NC_AOP_FUNC0
NC_AOP_FUNC1
NC_GYRO_INT1
NC_GYRO_INT2
SE_HOST_WAKE_R
SOC_PERST_L
NC_ALTIMETER_INT
NC_SPI_GYRO_CS_L
NC_SPI_ALTIMETER_CS_L

NC_I2C_AOP_SCL
NC_I2C_AOP_SDA

D3

AOP_FUNC[0]

F4

AOP_FUNC[1]

M6

AOP_FUNC[2]

D4

AOP_FUNC[3]

F3

AOP_FUNC[4]

K6

AOP_FUNC[5]

E4

AOP_FUNC[6]

J3

AOP_FUNC[7]

H6

AOP_FUNC[8]

N6

AOP_I2C0_SCL

G5

AOP_I2C0_SDA

(IPD)
(IPD)

(IPD)

C

64

64

OUT
BI

76

39

76

18

16

78 49

IN
IN
IN

OUT

IN

OUT

NC_DFR_TOUCH_INT_L
CPU_SMC_THRMTRIP_L
NC_SMC_GFX_SELF_THROTTLE
SMC_TOPBLK_SWP_L
XDP_PRESENT_L
CODEC_RESET_L
NC_AON_GPIO6_AR3

76

IN

76

OUT

40

IN

76

IN

76

IN

PLACE_NEAR=U3900.AD6:5MM
PLACE_NEAR=U7800.M7:5MM

SPMI_CLK
SPMI_DATA SPMI_DATA_R

R4036
R4037

20

21

5%

21

5%

MF202011/20W

64

IN

2011/20W MF

64

IN

NC_PCIEDN_WAKE_L
NC_ENET_LOW_PWR
TPAD_SPI_INT_L
NC_SDCONN_STATE_CHANGE_L
NC_ENET_MEDIA_SENSE
PMU_INT_L

SPMI_CLK_R

PMU_CLK32K_SOC
SOC_COLD_RESET_L

78

R4039

5%

64 40

IN

PMU_COLD_RESET_L

21

4.7K

201MF1/20W

AL6

AON_GPIO0

AE6

AON_GPIO1

AT5

AON_GPIO2

AN4

AON_GPIO3

AK4

AON_GPIO4

AV5

AON_GPIO5

AR3

AON_GPIO6

AG6

AON_GPIO7

AU5

AON_GPIO8

AP2

AON_GPIO9

AR4

AON_GPIO10

AN3

AON_GPIO11

AT6

AON_GPIO12

AD6

AON_SPMI_SCLK

AR2

AON_SPMI_SDATA

AR5

RT_CLK32768

AK2

COLD_RESET*

AK3

CFSB_AON

(IPD)

(IPU)

(IPU)
(IPD)
(IPU)

OMIT_TABLE

CRITICAL

U3900

H9M

BGA

SYM 5 OF 18

AON

(IPD)

(IPU)

AON_SLEEP1_RESET*

(IPU)
(IPU)
(IPU)

AON_SWD01_TCK

JTAG_TCK
JTAG_TMS
JTAG_TDI
JTAG_TDO

JTAG_TRST*

JTAG_SEL

DOCK_CONNECT

AON_SWD0_TMS
AON_SWD1_TMS

WDOG

AK6
AN5
AH6
AP4
AJ6
AC6

AN2

AJ4
AH4
AJ2

AJ5

AF6

SWD_SOC_SWCLK
SWD_SOC_SWDIO
TP_JTAG_SOC_TDI
TP_JTAG_SOC_TDO
TP_JTAG_SOC_TRST_L
SOC_JTAG_SEL

(DAP=0, TAP=1)

SOC_DOCK_CONNECT
TP_SWD_WLAN_SWDIO

NC_MESA_MENUKEY_L
TP_SWD_WLAN_SWCLK

SOC_WDOG
AON_SLEEP1_RESET_L

78

78

32

OUT

OUT

OUT

IN

BI

IN

BI

IN

76

76

76

64

31

78 23

78 23

78 32 23

C

B

A

PP1V8_PRIM_PCH

R4054
R4055
R4056
R4057
R4059

R4046
R4047

100K
100K
100K
100K
100K

10K

100K

18 75

21

5% 1/20W 201MF

21
21
21
21

21
21

5% 1/20W 201MF

OMIT_TABLE

CRITICAL

U3900

H9M

32 13

32 13

32 13

32 13

32 13

78 39

57 40 39

73 64 31

42 23

42 23

78 42

78 42

ESPI_IO<0>
ESPI_IO<1>

MF5% 2011/20W
MF5% 2011/20W
MF5% 2011/20W
MF5% 2011/20W

ESPI_IO<2>
ESPI_IO<3>
ESPI_CS_L

SOC_JTAG_SEL

2015% 1/20W MF

SOC_DOCK_CONNECT

32 13

32 13

32 13

32 13

32 13

32

78 32 23

13

13

39

39

39

39

39

17

42

42

42

42

42

42

42

42

42

42

BI
BI
BI
BI

IN
IN
IN

IN

OUT

OUT
OUT

OUT
OUT

IN

BI

IN

OUT
BI

OUT
BI

OUT
BI

OUT
BI

OUT
BI

OUT
BI

OUT
BI

ESPI_IO<0>
ESPI_IO<1>
ESPI_IO<2>
ESPI_IO<3>
ESPI_CLK60M
ESPI_CS_L
ESPI_RESET_L

SMC_PECI_RX
SMC_PECI_TX

SMC_PCH_PWROK
SMC_PCH_SYS_PWROK

SMC_RSMRST_L
SMC_SYSRST_L

PM_SLP_S0_1V8_L
SMC_PROCHOT_L

PMU_SYS_ALIVE
I2C_UPC_SCL

I2C_UPC_SDA
NC_I2C_SNS0_S0_SCL

NC_I2C_SNS0_S0_SDA
I2C_SNS1_S0_SCL

I2C_SNS1_S0_SDA
I2C_DISP_SCL

I2C_DISP_SDA
I2C_PWR_SCL

I2C_PWR_SDA
I2C_SNS_G3S_SCL

I2C_SNS_G3S_SDA
NC_I2C_SSD0_SCL

NC_I2C_SSD0_SDA

V2

SMC_ESPI_IO0

U3

SMC_ESPI_IO1

U4

SMC_ESPI_IO2

V8

SMC_ESPI_IO3

U2

SMC_ESPI_CLK

V7

SMC_ESPI_CS*

V6

SMC_ESPI_RESET*

M5

SMC_PECI_IN

T6

SMC_PECI_OUT

W7

PCH_PWROK

W8

SYS_PWROK

W6

RSMRST*

W4

SYS_RESET*

AA4

SLP_S0B

R5

PROCHOT*

AA6

SYS_ALIVE

M3

SMC_I2C0_SCL

J4

SMC_I2C0_SDA

N4

SMC_I2C1_SCL

P4

SMC_I2C1_SDA

U5

SMC_I2C2_SCL

M2

SMC_I2C2_SDA

U6

SMC_I2C3_SCL

R4

SMC_I2C3_SDA

P3

SMC_I2C4_SCL

T4

SMC_I2C4_SDA

R2

SMC_I2C5_SCL

P2

SMC_I2C5_SDA

R3

SMC_I2C6_SCL

T2

SMC_I2C6_SDA

(IPD)

(IPD)

(IPD)

BGA

SYM 9 OF 18

SMC

(IPU)

(IPD)
(IPD)

(IPD)

(IPU)

(IPU)
(IPU)
(IPD)

SMC_GPIO0
SMC_GPIO1
SMC_GPIO2
SMC_GPIO3
SMC_GPIO4
SMC_GPIO5
SMC_GPIO6
SMC_GPIO7
SMC_GPIO8

SMC_GPIO9
SMC_GPIO10
SMC_GPIO11
SMC_GPIO12
SMC_GPIO13
SMC_GPIO14
SMC_GPIO15

SMC_ADC0
SMC_ADC1
SMC_ADC2
SMC_ADC3
SMC_ADC4
SMC_ADC5
SMC_ADC6
SMC_ADC7

REFP_ADC
REFM_ADC

SMC_PWM0

SMC_TACH0

SMC_PWM1

SMC_TACH1

SMC_PWM2

SMC_UART0_RXD
SMC_UART0_TXD

SWD_OUT0_TCK
SWD_OUT0_TMS

SWD_OUT1_TCK
SWD_OUT1_TMS

Y4
Y8
Y5
AA2
Y7
Y6
AB2
AD5
AD2
AB4
AC2
AC3
AA8
AB3
AE2
L4

AG2
AC4
AH3
AD4
AB6
AH2
AG4
AC5

AF4
AG3

J2
L3

R6
L2

M4

V4
V5

AE3
AA5

AF2
AA7

CODEC_WAKE_L
NC_SMC_GPIO1_Y8
WLANBT_HOST_WAKE
NC_SMC_GFX_THROTTLE_L
LID_OPEN_RIGHT
NC_PCC_EVENT
NC_TPAD_VIBE_L
TPAD_KBD_WAKE_L
LID_OPEN_LEFT
SMC_DPWROK1V8
NC_DISP_GCON_INT_L
PCH_GCON_INT_L
NC_TPAD_ACTUATOR_DISABLE_L
TP_TBT_WAKE_L
UPC_I2C_INT_L
NC_GNSS_HOST_WAKE

SMC_DCIN_VSENSE
SMC_DCIN_ISENSE
SMC_PBUS_VSENSE
SMC_BMON_ISENSE
SMC_CPU_HS_ISENSE
SMC_3V3G3HMAIN_ISENSE
SMC_5VG3S_ISENSE
SMC_SSD0_ISENSE

PP1V25_SLPS2R_SMC_AVREF
GND_SMC_AVSS

SMC_FAN_0_PWM
SMC_FAN_0_TACH

NC_SMC_FAN_1_PWM
NC_SMC_FAN_1_TACH

NC_SMC_LED_ONEWIRE
SMC_DEBUGPRT_RX

SMC_DEBUGPRT_TX
SSD0_SWCLK_UART_R2D

SSD0_SWDIO_UART_D2R
NC_SSD1_SWCLK_UART_R2D

NC_SSD1_SWDIO_UART_D2R

IN

IN

76

OUT

40

IN

76

IN

76

OUT

40

IN

BI

17

OUT

76

IN

13

OUT

BI

23

IN
IN

76

IN

40

IN

40

IN

40

IN

40

IN

40

IN

40

IN

40

IN

40

IN

39

PLACE_NEAR=U3900.AG3:4MM

48

OUT

48

IN

76

OUT

76

IN

BI

IN

OUT

OUT

BI

76

OUT

BI

78 52 49

78 30 29

40

40

42 23

XW4089

SM

21

76

78 23

78 23

71 70

71 70

76

BOM_COST_GROUP=T290

SYNC_MASTER=X589_BIGSUR SYNC_DATE=03/16/2017

PAGE TITLE

SoC AOP/AON/SMC

SIZE

D

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

051-05232

REVISION

2.0.0

BRANCH

proto4b

PAGE

40 OF 152

SHEET

32 OF 86

B

A

8

67

35 4

2

1

D

www.laptoprepairsecrets.com

678

3 245

1

OMIT_TABLE

CRITICAL

U3900

H9M

BGA

SYM 4 OF 18

ISP

(IPD)

(IPD)

ISP_I2C0_SDA
ISP_I2C0_SCL

ISP_I2C1_SDA
ISP_I2C1_SCL

SENSOR0_CLK
SENSOR0_RST

SENSOR0_ISTRB

SENSOR1_CLK
SENSOR1_RST

SENSOR1_ISTRB

SENSOR2_CLK
SENSOR2_RST

SENSOR_INT

DISP_TE

DISP_VSYNC

CLK32K_OUT

AF32
AH36

AB32
AG32

AK35
AK34
AJ33

AD33
AC32
AC34

AD32
AJ32
AA33

H32

T36

AK33

I2C_FTCAM_SDA
I2C_FTCAM_SCL

NC_I2C_PLCAM_SDA
NC_I2C_PLCAM_SCL

NC_FTCAM_CLK12M_R
NC_FTCAM_RESET_L
NC_DFR_TOUCH_RESET_L

NC_PLCAM_RX_CLK12M_R
NC_PLCAM_RX_RESET_L
NC_DFR_DISP_RESET_L

NC_PLCAM_TX_CLK12M_R
NC_PLCAM_TX_RESET_L
NC_PLCAM_TX_INT

NC_DFR_DISP_TE
BOARD_REV2
NC_DFR_TOUCH_CLK32K_RESET_L

BI

OUT

BI

OUT

OUT
OUT
OUT

OUT
OUT
OUT

OUT
OUT

IN

IN

IN

OUT

43

43

76

76

76

76

76

76

76

76

76

76

39

76

43

43

D

69

69

76

76

69

69

76

76

76

76

76

76

76

76

76

76

IN
IN
IN
IN

IN
IN

IN
IN
IN
IN

IN
IN

OUT
OUT

OUT
OUT

MIPI_FTCAM_DATA_P<0>
MIPI_FTCAM_DATA_N<0>
GND
GND

MIPI_FTCAM_CLK_P
MIPI_FTCAM_CLK_N

GND
GND
GND
GND

GND
GND

NC_MIPI_DFR_DATAP
NC_MIPI_DFR_DATAN

NC_MIPI_DFR_CLKP
NC_MIPI_DFR_CLKN

SOC_MIPI0C_REXT
SOC_MIPI1C_REXT
SOC_MIPID_REXT

B27

MIPI0C_DATA0_P

A27

MIPI0C_DATA0_N

B25

MIPI0C_DATA1_P

A25

MIPI0C_DATA1_N

B26

MIPI0C_CLK_P

A26

MIPI0C_CLK_N

B28

MIPI1C_DATA0_P

A28

MIPI1C_DATA0_N

B30

MIPI1C_DATA1_P

A30

MIPI1C_DATA1_N

B29

MIPI1C_CLK_P

A29

MIPI1C_CLK_N

B33

MIPID_DATA0_P

A33

MIPID_DATA0_N

B32

MIPID_CLK_P

A32

MIPID_CLK_N

F23

MIPI0C_REXT

F26

MIPI1C_REXT

F27

MIPID_REXT

C

B

1

R4100

4.02K

1%
1/20W
MF
201

2

1

R4101

4.02K

1%
1/20W
MF
201

2

43

78 43

78 43

43

43

43

43

78 52 49

78 52

78

78

41

41

41

41

76

76

76

76

76

76

76

76

30 29

30 29

30 29

30 29

43

43

43

43

43

BI
OUT

BI
OUT

BI
OUT

BI
OUT

BI
OUT

BI
OUT

IN
IN

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

1

R4102

4.02K

1%
1/20W
MF
201

2

I2C_SPKRAMP_L_SDA
I2C_SPKRAMP_L_SCL

I2C_SPKRAMP_R_SDA
I2C_SPKRAMP_R_SCL

TP_I2C_CODEC_SDA
TP_I2C_CODEC_SCL

I2C_ALS_SDA
I2C_ALS_SCL

NC_I2C_DFR_SDA
NC_I2C_DFR_SCL

NC_I2C_SOC_5_SDA
NC_I2C_SOC_5_SCL

SPKR_ID1
SPKR_ID0

TP_SOC_DEBUGPRT_RX
TP_SOC_DEBUGPRT_TX

UART_SE_D2R
UART_SE_R2D
UART_SE_D2R_CTS_L
UART_SE_R2D_RTS_L

NC_UART_BT_D2R
NC_UART_BT_R2D
NC_UART_BT_D2R_CTS_L
NC_UART_BT_R2D_RTS_L

NC_UART_GNSS_D2R
NC_UART_GNSS_R2D
NC_UART_GNSS_D2R_CTS_L
NC_UART_GNSS_R2D_RTS_L

UART_WLAN_D2R
UART_WLAN_R2D
UART_WLAN_D2R_CTS_L
UART_WLAN_R2D_RTS_L

AE35
AD35

AF34
AG35

M34
R33

Y32

AE34

T34
U32

R35
U33

P34
R34

Y33
Y34

B15
A15
C15
D15

J36
J35
N32
M32

M36
N36
M35
U34

B14
A14
C14
C13

I2C0_SDA
I2C0_SCL

I2C1_SDA
I2C1_SCL

I2C2_SDA
I2C2_SCL

I2C3_SDA
I2C3_SCL

I2C4_SDA
I2C4_SCL

I2C5_SDA
I2C5_SCL

I2C6_SDA
I2C6_SCL

UART0_RXD
UART0_TXD

UART1_RXD
UART1_TXD
UART1_CTS*
UART1_RTS*

UART2_RXD
UART2_TXD
UART2_CTS*
UART2_RTS*

UART3_RXD
UART3_TXD
UART3_CTS*
UART3_RTS*

UART4_RXD
UART4_TXD
UART4_CTS*
UART4_RTS*

(IPU)
(IPU)

(IPU)

OMIT_TABLE

CRITICAL

U3900

H9M

BGA

SYM 2 OF 18

I2C/UART/SPI/I2S

(IPU)

(IPD)

(IPD)

(IPD)

(IPD)

SPI0_MISO
SPI0_MOSI
SPI0_SCLK
SPI0_SSIN

SPI1_MISO
SPI1_MOSI
SPI1_SCLK
SPI1_SSIN

SPI2_MISO
SPI2_MOSI
SPI2_SCLK
SPI2_SSIN

SPI3_MISO
SPI3_MOSI
SPI3_SCLK
SPI3_SSIN

I2S0_DIN
I2S0_DOUT
I2S0_BCLK
I2S0_LRCK

I2S0_MCK

I2S1_DIN
I2S1_DOUT
I2S1_BCLK
I2S1_LRCK

I2S1_MCK

I2S2_DIN
I2S2_DOUT
I2S2_BCLK
I2S2_LRCK

I2S2_MCK

I2S3_DIN
I2S3_DOUT
I2S3_BCLK
I2S3_LRCK

I2S3_MCK

AR9
AR7
AU7
AT9

P36
N34
P35
T32

A19
A20
C19
A18

C17
C18
B18
A17

AC33
AG34
AA32
AG33
AR35

B20
C20
C21
A21
D21

AH34
AB34
AF33
AH35
AR33

AD36
AB35
AE36
W34
AG36

SPI_SOCROM_MISO
SPI_SOCROM_MOSI_R
SPI_SOCROM_CLK_R
SPI_SOCROM_CS_L

SPI_TPAD_MISO
SPI_TPAD_MOSI_R
SPI_TPAD_CLK_R
SPI_TPAD_CS_L

SPI_MESA_MISO
SPI_MESA_MOSI_R
SPI_MESA_CLK_R
WLAN_THROTTLE

NC_SPI_DFR_MISO
NC_SPI_DFR_MOSI_R
NC_SPI_DFR_CLK_R
NC_SPI_DFR_CS_L

I2S_SPKRAMP_L_D2R
I2S_SPKRAMP_L_R2D_R
I2S_SPKRAMP_L_BCLK_R
I2S_SPKRAMP_L_LRCLK
NC_DFR_TOUCH_RSVD

I2S_SPKRAMP_R_D2R
I2S_SPKRAMP_R_R2D_R
I2S_SPKRAMP_R_BCLK_R
I2S_SPKRAMP_R_LRCLK
NC_PCHROM_SW_EN

I2S_CODEC_D2R
I2S_CODEC_R2D_R
I2S_CODEC_BCLK_R
I2S_CODEC_LRCLK
NC_I2S_CODEC_MCLK

NC_I2S_HAWKING_D2R
NC_I2S_CODEC1_R2D_R
NC_I2S_HAWKING_BCLK_R
NC_I2S_HAWKING_LRCLK
NC_I2S_CODEC1_MCLK

IN

OUT

IN
OUT
OUT
OUT

IN
OUT
OUT
OUT

IN
OUT
OUT
OUT

IN
OUT
OUT
OUT

BI

IN
OUT
OUT
OUT
OUT

IN
OUT
OUT
OUT
OUT

IN
OUT
OUT
OUT
OUT

39

40

40

54

40

40

76

76

76

76

40

40

40

52

40

40

40

76

40

40

76

76

76

76

76

76

76

C

PLACE_NEAR=U3900.AR7:5MM

40 39

R4171
R4172

54 39

78 49

30 29

PLACE_NEAR=U3900.AU7:5MM

20
20

21
21

5% MF1/20W

MF1/20W5% 201

201

SPI_SOCROM_MOSI
SPI_SOCROM_CLK

OUT
OUT

40 39

40 39

B

78 50 49

78 49

78 49

A

8

67

SYNC_MASTER=X589_BIGSUR

PAGE TITLE

SYNC_DATE=03/15/2017

A

SoC ISP/I2C/UART/SPI/I2S

DRAWING NUMBER

051-05232

Apple Inc.

REVISION

2.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=T290

35 4

IV ALL RIGHTS RESERVED

2

BRANCH

proto4b

PAGE

41 OF 152

SHEET

33 OF 86

1

SIZE

D

678

www.laptoprepairsecrets.com

3 245

1

OMIT_TABLE

CRITICAL

D

15

15

15

15

15

15

15

15

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

18

PCIE_SOC_D2R_P<0>
PCIE_SOC_D2R_N<0>

PCIE_SOC_D2R_P<1>
PCIE_SOC_D2R_N<1>

PCIE_SOC_D2R_P<2>
PCIE_SOC_D2R_N<2>

PCIE_SOC_D2R_P<3>
PCIE_SOC_D2R_N<3>

OUT

SOC_CLKREQ_L

(All Caps)

GND_VOID=TRUE

C4210

0.22UF

C4211

0.22UF

C4212

0.22UF

C4213

0.22UF

C4214

0.22UF

C4215

0.22UF

C4216

0.22UF

C4217

0.22UF

R4218

1K

21

6.3V X5R 0201

20%

21

X5R6.3V20% 0201

21
20% X5R6.3V 0201

21

20% 6.3V X5R 0201

21

X5R20% 02016.3V

21

X5R 02016.3V20%

21

6.3V20% 0201

21

21

X5R

X5R

020120% 6.3V

MF

U3900

H9M

PCIE_SOC_D2R_C_P<0>
PCIE_SOC_D2R_C_N<0>

40

40

IN
IN

PCIE_SOC_R2D_P<0>
PCIE_SOC_R2D_N<0>

PCIE_SOC_D2R_C_P<1>
PCIE_SOC_D2R_C_N<1>

40

40

IN
IN

PCIE_SOC_R2D_P<1>
PCIE_SOC_R2D_N<1>

PCIE_SOC_D2R_C_P<2>
PCIE_SOC_D2R_C_N<2>

40

40

IN
IN

PCIE_SOC_R2D_P<2>
PCIE_SOC_R2D_N<2>

PCIE_SOC_D2R_C_P<3>
PCIE_SOC_D2R_C_N<3>

40

40

IN
IN

PCIE_SOC_R2D_P<3>
PCIE_SOC_R2D_N<3>

SOC_CLKREQ_R_L

2011/20W5%

15

15

IN
IN

PCIE_CLK100M_SOC_P
PCIE_CLK100M_SOC_N

SOC_PCIE_UP_REXT

1

R4200

3.01K

1%
1/20W
MF
201

2

B10
C10
E10
F10

A9
B9
D9
E9

B8
C8
E8
F8

A7
B7
D7
E7

B21

G13
G12

G11

PCIE_UP_TX0_P
PCIE_UP_TX0_N
PCIE_UP_RX0_P
PCIE_UP_RX0_N

PCIE_UP_TX1_P
PCIE_UP_TX1_N
PCIE_UP_RX1_P
PCIE_UP_RX1_N

PCIE_UP_TX2_P
PCIE_UP_TX2_N
PCIE_UP_RX2_P
PCIE_UP_RX2_N

PCIE_UP_TX3_P
PCIE_UP_TX3_N
PCIE_UP_RX3_P
PCIE_UP_RX3_N

PCIE_UP_CLKREQ*

PCIE_UP_EXT_REFCLK_P
PCIE_UP_EXT_REFCLK_N

PCIE_UP_REXT

BGA

SYM 1 OF 18

PCIE UP/DN

PCIE_DN_TX0_P
PCIE_DN_TX0_N
PCIE_DN_RX0_P
PCIE_DN_RX0_N

PCIE_DN_TX1_P
PCIE_DN_TX1_N
PCIE_DN_RX1_P
PCIE_DN_RX1_N

PCIE_DN_TX2_P
PCIE_DN_TX2_N
PCIE_DN_RX2_P
PCIE_DN_RX2_N

PCIE_DN_TX3_P
PCIE_DN_TX3_N
PCIE_DN_RX3_P
PCIE_DN_RX3_N

PCIE_DN_REFCLK0_P
PCIE_DN_REFCLK0_N

PCIE_DN_CLKREQ0*

PCIE_DN_PERST0*

PCIE_DN_REFCLK1_P
PCIE_DN_REFCLK1_N

PCIE_DN_CLKREQ1*

PCIE_DN_PERST1*

PCIE_DN_REFCLK2_P
PCIE_DN_REFCLK2_N

PCIE_DN_CLKREQ2*

PCIE_DN_PERST2*

AV31
AU31
AR31
AP31

AU30
AT30
AP30
AN30

AV29
AU29
AR29
AP29

AU28
AT28
AP28
AN28

AP26
AR26
AM33
AN34

AN25
AP25
AN35
AK32

AU26
AV26
AH32
AE32

NC_PCIE_WLAN_R2D_CP
NC_PCIE_WLAN_R2D_CN
NC_PCIE_WLAN_D2RP
NC_PCIE_WLAN_D2RN

NC_PCIE_ENET_R2D_CP
NC_PCIE_ENET_R2D_CN
NC_PCIE_ENET_D2RP
NC_PCIE_ENET_D2RN

TP_PCIE_DN2_R2D_CP
TP_PCIE_DN2_R2D_CN
TP_PCIE_DN2_D2RP
TP_PCIE_DN2_D2RN

TP_PCIE_DN3_R2D_CP
TP_PCIE_DN3_R2D_CN
TP_PCIE_DN3_D2RP
TP_PCIE_DN3_D2RN

NC_PCIE_CLK100M_WLANP
NC_PCIE_CLK100M_WLANN
NC_WLAN_CLKREQ_L
NC_WLAN_PERST_L

NC_PCIE_CLK100M_ENETP
NC_PCIE_CLK100M_ENETN
ENET_CLKREQ_L
NC_ENET_RESET_L

TP_PCIE_CLK100M_DN2P
TP_PCIE_CLK100M_DN2N
TP_PCIEDN2_CLKREQ_L
TP_PCIEDN2_RESET_L

OUT
OUT

OUT
OUT

OUT
OUT

OUT

OUT
OUT

34

OUT

IN
IN

IN
IN

IN

76

76

76

76

76

76

76

76

76

76

76

76

76

76

76

D

(UID_MODE strap on A00)

C

B

73

73

70

70

73

73

71

71

73

73

73

73

73

73

73

73

OUT
OUT
IN
IN

OUT
OUT
IN
IN

OUT
OUT
IN
IN

OUT
OUT
IN
IN

PCIE_SSD0_R2D_C_P<0>
PCIE_SSD0_R2D_C_N<0>
PCIE_SSD0_D2R_P<0>
PCIE_SSD0_D2R_N<0>

PCIE_SSD0_R2D_C_P<1>
PCIE_SSD0_R2D_C_N<1>
PCIE_SSD0_D2R_P<1>
PCIE_SSD0_D2R_N<1>

NC_S4E3_PCIE_R2D_CP<2>
NC_S4E3_PCIE_R2D_CN<2>
NC_S4E3_PCIE_D2RP<2>
NC_S4E3_PCIE_D2RN<2>

NC_S4E3_PCIE_R2D_CP<3>
NC_S4E3_PCIE_R2D_CN<3>
NC_S4E3_PCIE_D2RP<3>
NC_S4E3_PCIE_D2RN<3>

AU11
AT11
AP11
AN11

AV12
AU12
AR12
AP12

AU13
AT13
AP13
AN13

AV14
AU14
AR14
AP14

PCIE_STG0_TX0_N
PCIE_STG0_RX0_P
PCIE_STG0_RX0_N

PCIE_STG0_TX1_P
PCIE_STG0_TX1_N
PCIE_STG0_RX1_P
PCIE_STG0_RX1_N

PCIE_STG0_TX2_P
PCIE_STG0_TX2_N
PCIE_STG0_RX2_P
PCIE_STG0_RX2_N

PCIE_STG0_TX3_P
PCIE_STG0_TX3_N
PCIE_STG0_RX3_P
PCIE_STG0_RX3_N

OMIT_TABLE

CRITICAL

U3900

H9M

BGA

SYM 8 OF 18PCIE_STG0_TX0_P

PCIE STG 0/1

PCIE_DN_REFCLK3_P
PCIE_DN_REFCLK3_N

PCIE_DN_CLKREQ3*

PCIE_DN_PERST3*

PCIE_DN_EXT_REFCLK_P
PCIE_DN_EXT_REFCLK_N

PCIE_DN_REXT

PCIE_STG1_TX0_P
PCIE_STG1_TX0_N
PCIE_STG1_RX0_P
PCIE_STG1_RX0_N

PCIE_STG1_TX1_P
PCIE_STG1_TX1_N
PCIE_STG1_RX1_P
PCIE_STG1_RX1_N

PCIE_STG1_TX2_P
PCIE_STG1_TX2_N
PCIE_STG1_RX2_P
PCIE_STG1_RX2_N

PCIE_STG1_TX3_P
PCIE_STG1_TX3_N
PCIE_STG1_RX3_P
PCIE_STG1_RX3_N

AT25
AU25
AJ34
AK36

AM27
AM26

AM25

AU16
AT16
AP16
AN16

AV17
AU17
AR17
AP17

AU18
AT18
AP18
AN18

AV19
AU19
AR19
AP19

TP_PCIE_CLK100M_DN3P
TP_PCIE_CLK100M_DN3N
TP_PCIEDN3_CLKREQ_L
TP_PCIEDN3_RESET_L

SOC_PCIE_DN_REXT

R4201

3.01K

1%

1/20W

MF

201

NC_PCIE_SSD1_R2D_CP<0>
NC_PCIE_SSD1_R2D_CN<0>
NC_PCIE_SSD1_D2RP<0>
NC_PCIE_SSD1_D2RN<0>

NC_PCIE_SSD1_R2D_CP<1>
NC_PCIE_SSD1_R2D_CN<1>
NC_PCIE_SSD1_D2RP<1>
NC_PCIE_SSD1_D2RN<1>

NC_PCIE_SSD1_R2D_CP<2>
NC_PCIE_SSD1_R2D_CN<2>
NC_PCIE_SSD1_D2RP<2>
NC_PCIE_SSD1_D2RN<2>

NC_PCIE_SSD1_R2D_CP<3>
NC_PCIE_SSD1_R2D_CN<3>
NC_PCIE_SSD1_D2RP<3>
NC_PCIE_SSD1_D2RN<3>

C

1

2

76

OUT

76

OUT

76

IN

76

IN

76

OUT

76

OUT

IN
IN

OUT
OUT

IN
IN

OUT
OUT

IN
IN

76

76

76

76

76

76

76

76

76

76

B

A

PP1V8_AWAKE

R4232

47K

71 70

71 70

70 40

71 40

73

73

40

40

71 70 40

40

OUT
OUT
IN
IN

OUT
OUT
IN
IN

OUT

OUT

PCIE_CLK100M_SSD0_01_P
PCIE_CLK100M_SSD0_01_N
SSD0_CLKREQ0_L
SSD0_CLKREQ1_L

NC_PCIE_CLK100M_SSD0_23P
NC_PCIE_CLK100M_SSD0_23N
SSD0_CLKREQ2_L
SSD0_CLKREQ3_L

SSD0_PCIE_RESET_L

SSD0_CLK24M_R

AP21
AR21
AT33
AR34

AN22
AP22
AP34
AN33

AR36

AP7

AM14
AM15

PCIE_STG0_REFCLK01_P
PCIE_STG0_REFCLK01_N
PCIE_STG0_CLKREQ0*
PCIE_STG0_CLKREQ1*

PCIE_STG0_REFCLK23_P
PCIE_STG0_REFCLK23_N
PCIE_STG0_CLKREQ2*
PCIE_STG0_CLKREQ3*

PCIE_STG0_PERST*

PCIE_STG0_NANDCLK

PCIE_STG0_EXT_REFCLK_P
PCIE_STG0_EXT_REFCLK_N

PCIE_STG1_REFCLK01_P
PCIE_STG1_REFCLK01_N

PCIE_STG1_CLKREQ0*
PCIE_STG1_CLKREQ1*

PCIE_STG1_REFCLK23_P
PCIE_STG1_REFCLK23_N

PCIE_STG1_CLKREQ2*
PCIE_STG1_CLKREQ3*

PCIE_STG1_PERST*

PCIE_STG1_NANDCLK

PCIE_STG1_EXT_REFCLK_P
PCIE_STG1_EXT_REFCLK_N

AU21
AV21
B17
D18

AT22
AU22
C16
A16

AP36

AV7

AM19
AM20

NC_PCIE_CLK100M_SSD1_01P
NC_PCIE_CLK100M_SSD1_01N
NC_SSD1_CLKREQ0_L
NC_SSD1_CLKREQ1_L

NC_PCIE_CLK100M_SSD1_23P
NC_PCIE_CLK100M_SSD1_23N
NC_SSD1_CLKREQ2_L
NC_SSD1_CLKREQ3_L

NC_SSD1_PCIE_RESET_L

NC_SSD1_CLK24M_R

OUT
OUT

IN
IN

OUT
OUT

IN
IN

OUT

OUT

76

76

76

76

76

76

76

76

76

76

SYNC_MASTER=X589_BIGSUR

PAGE TITLE

SYNC_DATE=03/15/2017

A

SoC PCIe

AM16

1

R4250

3.01K

1%
1/20W

39 40 74

21

1/20W

ENET_CLKREQ_L

201MF5%

34

MF
201

2

PCIE_STG0_REXT

PCIE_STG1_REXT

AM21

SOC_PCIE_STG1_REXTSOC_PCIE_STG0_REXT

DRAWING NUMBER

051-05232

R4251

3.01K

1%

1/20W

MF

201

1

NOTICE OF PROPRIETARY PROPERTY:

2

BOM_COST_GROUP=T290

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

Apple Inc.

REVISION

2.0.0

BRANCH

proto4b

PAGE

42 OF 152

SHEET

34 OF 86

SIZE

D

8

67

35 4

2

1

678

www.laptoprepairsecrets.com

3 245

1

D

C

Current estimates @ 105C & 2GB from Gibraltar Power Specification Rev 0.5.3

PPVDDCPU_AWAKE

74

0.625V - 1.06V

11.6A Max

CRITICAL

C4300

9.1UF

20%

4V
CERM
0402

1

3

4

2

CRITICAL

C4305

9.1UF

20%

4V
CERM
0402

1

3

4

2

CRITICAL

C4320

4.3UF

20%

4V
CERM
0402

1

3

4

2

C4330

4.3UF

20%

4V
CERM
0402

1

3

CRITICAL

C4301

9.1UF

20%

4V
CERM
0402

1

3

4

2

CRITICAL

C4306

9.1UF

20%

4V
CERM
0402

1

3

4

2

CRITICAL

C4321

4.3UF

20%

4V
CERM
0402

1

3

4

2

CRITICALCRITICAL

C4331

4.3UF

20%

4V
CERM
0402

1

3

CRITICAL

C4302

9.1UF

20%

4V
CERM
0402

1

3

4

2

CRITICAL

C4307

9.1UF

20%

4V
CERM
0402

1

3

4

2

CRITICAL

C4322

4.3UF

20%

4V
CERM
0402

1

3

4

2

CRITICAL

C4332

4.3UF

20%

4V
CERM
0402

1

3

CRITICAL

C4303

9.1UF

20%

4V
CERM
0402

1

3

4

2

CRITICAL

C4308

9.1UF

20%

4V
CERM
0402

1

3

4

2

CRITICAL

C4323

4.3UF

20%

4V
CERM
0402

1

3

4

2

CRITICAL

C4333

4.3UF

20%

4V
CERM
0402

1

3

CRITICAL

C4304

9.1UF

20%

4V
CERM
0402

1

3

4

2

CRITICAL

C4309

9.1UF

20%

4V
CERM
0402

1

3

4

2

CRITICAL

C4324

4.3UF

20%

4V
CERM
0402

1

3

4

2

CRITICAL

C4334

4.3UF

20%

4V
CERM
0402

1

3

AA12
AA14
AA16
AB11
AB13
AB15
AC12
AC14
AC16
AD11
AD13
AD15
AD17
AE10
AE12
AE14
AE16
AE18

P11
P13
P15
P17
R12
R14
R16
T11
T13
T15
U12
U14
U16
V17
W12
W14
W16
Y17

VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU

OMIT_TABLE

CRITICAL

U3900

H9M

BGA

SYM 10 OF 18

VDD_CPU_SRAM
VDD_CPU_SRAM
VDD_CPU_SRAM
VDD_CPU_SRAM
VDD_CPU_SRAM
VDD_CPU_SRAM
VDD_CPU_SRAM
VDD_CPU_SRAM
VDD_CPU_SRAM
VDD_CPU_SRAM
VDD_CPU_SRAM
VDD_CPU_SRAM
VDD_CPU_SRAM

VDD_CPU_SENSE

VSS_CPU_SENSE

AA10
AB17
AC10
R10
T17
U10
V11
V13
V15
W10
Y11
Y13
Y15

N18

N17

CRITICAL

C4350

9.1UF

20%

4V
CERM
0402

1

4

2

CRITICAL

C4355

4.3UF

20%

4V
CERM
0402

1

4

2

CRITICAL

3

CRITICAL

3

C4351

9.1UF

1

C4356

4.3UF

1

CRITICAL

C4360

4.3UF

20%

4V
CERM
0402

1

SOC_VDDCPU_SENSE
TP_SOC_VSSCPU_SENSE

3

4

2

20%

4V
CERM
0402

2

20%

4V
CERM
0402

2

3

CRITICAL

C4352

9.1UF

20%

4V
CERM
0402

1

3

CRITICAL

C4353

9.1UF

20%

4V
CERM
0402

1

3

CRITICAL

C4354

9.1UF

20%

4V
CERM
0402

1

3

CRITICAL

C4357

9.1UF

20%

4V
CERM
0402

1

3

PPVDDCPUSRAM_AWAKE

0.8V - 1.06V

0.9A Max

74

D

4

4

4

3

4

64

OUT

4

2

4

2

2

2

C

B

A

PP0V82_SLPDDR

74

5.6A Max

4

4

4

4

4

2

2

2

2

2

OMIT_TABLE

CRITICAL

U3900

H9M

BGA

SYM 11 OF 18

VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC

VDD_SOC_SENSE

VSS_SENSE

J22
J24
J26
J28
L10
L12
L14
L16
L18
L20
L22
L24
L26
L28
N10
N12
N14
N16
N20
N22
N24
N26
N28
R18
R20
R22
R24
R26
R28
U18
U20
U22
U24
U26
U28
W20
W22
W24
W26
W28

AD27

AD28

TP_SOC_VDDSOC_SENSE
TP_SOC_VSSSOC_SENSE

BOM_COST_GROUP=T290

SYNC_MASTER=X589_BIGSUR

PAGE TITLE

SoC Power 1

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=02/13/2017

DRAWING NUMBER

051-05232

REVISION

2.0.0

BRANCH

proto4b

PAGE

43 OF 152

SHEET

35 OF 86

B

A

SIZE

D

CRITICAL

C4370

9.1UF

20%

4V
CERM
0402

1

3

4

2

CRITICAL

C4380

4.3UF

20%

4V
CERM
0402

1

3

4

2

CRITICAL

C4385

4.3UF

20%

4V
CERM
0402

1

3

4

2

CRITICAL

C4371

9.1UF

20%

4V
CERM
0402

1

3

4

2

CRITICAL

C4381

4.3UF

20%

4V
CERM
0402

1

3

4

2

CRITICAL

C4386

4.3UF

20%

4V
CERM
0402

1

3

4

2

CRITICAL

C4372

9.1UF

20%

4V
CERM
0402

1

3

4

2

CRITICAL

C4373

9.1UF

20%

4V
CERM
0402

1

3

4

2

AA20
AA22
AA24
AA26
AA28
AC18
AC20
AC22
AC24
AC26
AC28
AE20
AE22
AE24
AE26
AE28
AG10
AG12
AG14
AG16
AG18
AG20
AG22
AG24
AG26
AG28
AJ10
AJ12
AJ14
AJ16
AJ18
AJ20
AJ22
AJ24
AJ26
AJ28

J10
J12
J14
J16
J18
J20

VDD_SOC VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC

8

67

35 4

2

1

678

www.laptoprepairsecrets.com

3 245

1

D

C

B

A

Current estimates @ 105C & 2GB from Gibraltar Power Specification Rev 0.5.3

PP1V1_SLPDDR

74

PP0V9_SLPDDR

74

1.9A Max

9mA Max

PP0V9_SLPDDR

74

PP0V9_SLPDDR

74

5mA Max

PP0V9_SLPDDR

74

25mA Max

PP0V8_SLPS2R

74

102mA Max

PP0V9_SLPDDR

36 74

330mA Max

CRITICAL

C4400

9.1UF

20%

4V
CERM
0402

1

3

4

2

CRITICAL

C4405

4.3UF

20%

4V
CERM
0402

1

3

4

2

C4410

4.3UF

20%

4V
CERM
0402

1

3

4

2

CRITICAL

C4401

9.1UF

20%

4V
CERM
0402

1

2

3

4

CRITICAL

C4406

4.3UF

20%

4V
CERM
0402

1

2

3

4

CRITICALCRITICAL

C4411

4.3UF

20%

4V
CERM
0402

1

2

3

4

CRITICAL

CRITICAL

C4425

4.3UF

20%

4V
CERM
0402

1

2

3

4

CRITICAL

C4402

9.1UF

20%

4V
CERM
0402

1

3

4

2

CRITICAL

C4420

4.3UF

20%

4V
CERM
0402

1

3

4

2

C4423

2.2UF

20%

X6S-CERM

4V

0201

CRITICAL

C4426

4.3UF

20%

4V
CERM
0402

1

3

4

2

0.86A Max

CRITICAL

C4450

2.2UF

20%

X6S-CERM

4V

0201

CRITICAL

C4454

2.2UF

20%

X6S-CERM

U3900

H9M

AB19
AB21
AB23
AB25
AB27
AD19
AD21
AD23
AD25
AF11
AF13
AF15
AF17
AF19
AF21
AF23
AF25
AF27
AH11
AH13
AH15
AH17
AH19
AH21
AH23
AH25
AH27
AK11

K11
K13
K15
K17

W18

G22

H23
H25
H27

AB9
AD9

1

2

H11
H13
H15

J15
J11
J13

VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED

VDD_FIXED_CPU

VDD_FIXED_USB

VDD_FIXED_MIPI
VDD_FIXED_MIPI
VDD_FIXED_MIPI

VDD_LOW
VDD_LOW

P9

VDD_LOW

T9

VDD_LOW

V9

VDD_LOW

Y9

VDD_LOW

VDD_FIXED_UP_PCIE_ANA
VDD_FIXED_UP_PCIE_ANA
VDD_FIXED_UP_PCIE_ANA

VDD_FIXED_UP_PCIE_CLK
VDD_FIXED_UP_PCIE_CLK
VDD_FIXED_UP_PCIE_CLK

OMIT_TABLE

BGA

SYM 12 OF 18

CRITICAL

VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED

VDD_FIXED_STG0_PCIE_ANA
VDD_FIXED_STG0_PCIE_ANA
VDD_FIXED_STG0_PCIE_ANA

VDD_FIXED_STG0_PCIE_CLK
VDD_FIXED_STG0_PCIE_CLK
VDD_FIXED_STG0_PCIE_CLK

VDD_FIXED_STG1_PCIE_ANA
VDD_FIXED_STG1_PCIE_ANA
VDD_FIXED_STG1_PCIE_ANA

VDD_FIXED_STG1_PCIE_CLK
VDD_FIXED_STG1_PCIE_CLK
VDD_FIXED_STG1_PCIE_CLK

VDD_FIXED_DN_PCIE_ANA
VDD_FIXED_DN_PCIE_ANA
VDD_FIXED_DN_PCIE_ANA

VDD_FIXED_DN_PCIE_CLK
VDD_FIXED_DN_PCIE_CLK
VDD_FIXED_DN_PCIE_CLK

VDD_FIXED_PCIE_REFBUF
VDD_FIXED_PCIE_REFBUF
VDD_FIXED_PCIE_REFBUF
VDD_FIXED_PCIE_REFBUF
VDD_FIXED_PCIE_REFBUF

4V

0201

K19
K21
K23
K25
K27
M11
M13
M15
M17
M19
M21
M23
M25
M27
P19
P21
P23
P25
P27
T19
T21
T23
T25
T27
V19
V21
V23
V25
V27
Y19
Y21
Y23
Y25
Y27

AL14
AL16
AL12

AK13
AK15
AK17

AL18
AL20
AL22

AK19
AK21
AL17

AL26
AL28

AL30

AK25
AK27
AK29

AK23
AJ15

AL24
AJ21
AJ27

CRITICAL

1

C4451

2.2UF

2

X6S-CERM

CRITICAL

1

C4455

2.2UF

2

X6S-CERM

20%

4V

0201

20%

4V

0201

CRITICAL

1

C4452

2.2UF

2

X6S-CERM

CRITICAL

1

C4456

2.2UF

2

X6S-CERM

CRITICAL

C4430

4.3UF

20%

4V
CERM
0402

1

3

4

2

CRITICAL

C4435

4.3UF

20%

4V
CERM
0402

1

3

4

2

CRITICAL

C4440

4.3UF

20%

4V
CERM
0402

1

3

4

2

CRITICAL

C4445

4.3UF

20%

4V
CERM
0402

1

3

4

2

CRITICAL

20%

4V

0201

1

2

C4453

2.2UF

X6S-CERM

20%

4V

0201

1

2

CRITICAL

20%

4V

0201

1

2

C4457

2.2UF

X6S-CERM

20%

4V

0201

1

2

AB37
AD30
AD37
AE29
AE37
AF30
AG29
AH30
AJ29
AM37
AP37
AT36

PP0V9_SLPDDR

CRITICAL

C4431

4.3UF

20%

4V
CERM
0402

1

2

3

4

PP0V9_SLPDDR

CRITICAL

C4436

4.3UF

20%

4V
CERM
0402

1

2

3

4

PP0V9_SLPDDR

CRITICAL

C4441

4.3UF

20%

4V
CERM
0402

1

2

PP0V9_SLPDDR_SOC_PCIEREFBUF

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000
VOLTAGE=0.9V

3

4

C2

VDDIO11_DDR0

E1

VDDIO11_DDR0

G1

VDDIO11_DDR0

H8

VDDIO11_DDR0

J9

VDDIO11_DDR0

K8

VDDIO11_DDR0

L9

VDDIO11_DDR0

M8

VDDIO11_DDR0

N9

VDDIO11_DDR0

P1

VDDIO11_DDR0

R1

VDDIO11_DDR0

U1

VDDIO11_DDR0

C36

VDDIO11_DDR1

E37

VDDIO11_DDR1

G37

VDDIO11_DDR1

H30

VDDIO11_DDR1

J29

VDDIO11_DDR1

K30

VDDIO11_DDR1

L29

VDDIO11_DDR1

M30

VDDIO11_DDR1

N29

VDDIO11_DDR1

P37

VDDIO11_DDR1

R37

VDDIO11_DDR1

U37

VDDIO11_DDR1

AB1

VDDIO11_DDR2

AD1

VDDIO11_DDR2

AE1

VDDIO11_DDR2

AF9

VDDIO11_DDR2

AG8

VDDIO11_DDR2

AH9

VDDIO11_DDR2

AJ8

VDDIO11_DDR2

AK9

VDDIO11_DDR2

AL8

VDDIO11_DDR2

AM1

VDDIO11_DDR2

AP1

VDDIO11_DDR2

AT2

VDDIO11_DDR2

VDDIO11_DDR3
VDDIO11_DDR3
VDDIO11_DDR3
VDDIO11_DDR3
VDDIO11_DDR3
VDDIO11_DDR3
VDDIO11_DDR3
VDDIO11_DDR3
VDDIO11_DDR3
VDDIO11_DDR3
VDDIO11_DDR3
VDDIO11_DDR3

OMIT_TABLE

CRITICAL

SYM 13 OF 18

330mA Max

330mA Max

330mA Max

R4445

0

2 1

5%

1/20W

MF

0201

U3900

H9M

BGA

36 74

36 74

36 74

PP0V9_SLPDDR

VDDIO11_PLL_DDR
VDDIO11_PLL_DDR
VDDIO11_PLL_DDR
VDDIO11_PLL_DDR

VDDIO11_RET_DDR
VDDIO11_RET_DDR
VDDIO11_RET_DDR
VDDIO11_RET_DDR

G9
G29
AM9
AK30

G4
G34
AM4
AM34

PP1V1_SLPDDR

74

CRITICAL

1

C4460

0.22UF

20%

6.3V

2

X6S-CERM
0201

CRITICAL

1

C4461

0.22UF

20%

6.3V

2

X6S-CERM
0201

CRITICAL CRITICAL

1

C4470

2.2UF

20%
4V

2

X6S-CERM
0201

36 74

1

C4471

2.2UF

20%
4V

2

X6S-CERM
0201

45mA Max

BOM_COST_GROUP=T290

8mA Max

R4460

5.1

1/20W MF1%

21

0201

L4460

120-OHM-25%-0.48A-0.21DCR

21

0201

PP1V1_SLPDDR_SOC_VDDIOPLLDDR_F

MIN_LINE_WIDTH=0.2000

CRITICAL

1

C4462

0.22UF

20%

6.3V

2

X6S-CERM
0201

CRITICAL

1

C4463

0.22UF

20%

6.3V

2

X6S-CERM
0201

MIN_NECK_WIDTH=0.0750
VOLTAGE=1.1V

Current included in VDD2

PP1V1_SLPS2R

CRITICAL

1

C4472

2.2UF

20%
4V

2

X6S-CERM
0201

SYNC_MASTER=X589_BIGSUR SYNC_DATE=02/13/2017

PAGE TITLE

CRITICAL

1

C4473

2.2UF

20%
4V

2

X6S-CERM
0201

74

SoC Power 2

DRAWING NUMBER

051-05232

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

REVISION

2.0.0

BRANCH

proto4b

PAGE

44 OF 152

SHEET

36 OF 86

D

C

B

A

SIZE

D

8

67

35 4

2

1

678

www.laptoprepairsecrets.com

Current estimates @ 105C & 2GB from Gibraltar Power Specification Rev 0.5.3

3 245

1

D

C

B

A

PP1V8_AWAKE

74

40mA Max

PP1V8_AWAKE

74

2mA Max

PP1V8_SLPS2R

74

1mA Max

PP1V8_SLPS2R

74

1mA Max

CRITICAL

PP1V8_SLPS2R

74

C4521

2.2UF

20%

X6S-CERM

4V

0201

PP1V8_SLPS2R

74

134mA Max

20mA Max

CRITICAL

1

2

C4522

X6S-CERM

R4530

2.2UF

20%

4V

0201

0

5%

1/20W

MF

0201

CRITICAL

C4510

R4515

49.9

1% MF 2011/20W

R4519

49.9

1% 1/20W MF 201

CRITICAL

1

2

21

CRITICAL

C4523

2.2UF

X6S-CERM

C4530

1UF

20%

6.3V

X6S-CERM

0201

PP1V8_AWAKE

74

20mA Max

0201

1

2

CRITICAL

C4500

2.2UF

X6S-CERM

2.2UF

20%

21

21

4V

4V

0201

PP1V8_SLPS2R_SOC_LPADC_RC

PP1V8_SLPS2R_SOC_LPOSC_RC

1

2

X6S-CERM

20%

20%

4V

0201

1

2

VOLTAGE=1.8V
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000

VOLTAGE=1.8V
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000

CRITICAL

C4524

1

CRITICAL

1

2

C4501

CRITICAL

C4511

4.3UF

20%

CERM
0402

1

2

4.3UF

20%

4V
CERM
0402

3

4

2

2.2UF

20%

X6S-CERM

0201

4V

3

4

CRITICAL

C4525

1

1

4V

2

CRITICAL

4.3UF

20%

4V
CERM
0402

2

PP1V8_AWAKE_SOC_TSADC_RC

VOLTAGE=1.8V
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.0750

PP1V8_AWAKE

74

7mA Max

CRITICAL

10%

6.3V
X6S

0201

1

2

C4540

0.1UF

CRITICAL

C4502

X6S-CERM

C4512

4.3UF

20%

4V
CERM
0402

1

4

2

CRITICAL

C4519

X6S-CERM

CRITICAL

3

4

CRITICAL

C4535

2.2UF

X6S-CERM

2.2UF

20%

4V

0201

CRITICAL

3

2.2UF

20%

4V

0201

C4526

4.3UF

20%

4V
CERM
0402

1

4

2

20%

4V

0201

C4513

1

2

CRITICAL

1

2

0.1UF

10%

6.3V
X6S

0201

CRITICAL

1

2

CRITICAL

3

CRITICAL

C4503

2.2UF

X6S-CERM

1

2

C4515

20UF

X6S-CERM

C4527

4.3UF

20%

CERM
0402

1

2

C4536

0.1UF

PP1V8_AWAKE_SOC_FMON_F

VOLTAGE=1.8V
MIN_LINE_WIDTH=0.0750
MIN_NECK_WIDTH=0.0750

0201

2.5V
0402

4V

6.3V
0201

20%

4V

20%

4

10%
X6S

D

OMIT_TABLE

CRITICAL

U3900

H9M

A4

VDD1 VDD12_CPU_UVD

1

2

1

2

3

1

2

AV34

AV4
B35

W1

W37

Y1

Y37

AA9

P8
R9
T8
U9
W9

AC9
AD8
AE9

AB8

AB10

AA29
AB30
AC29

P30
R29
T30

U29
V30
W29
Y30

G16

G18

G20
H17
H19
H21

AK31
AM31

AL11
AM10

AA18

P16

AD16
AF18

H28

G23
G25
G27

H22

AF12

AM30
AK12

VDD1
VDD1
VDD1
VDD1
VDD1
VDD1
VDD1

VDDIO18_AOP1
VDDIO18_AOP1
VDDIO18_AOP1
VDDIO18_AOP1
VDDIO18_AOP1
VDDIO18_AOP1

VDDIO18_AOP2
VDDIO18_AOP2
VDDIO18_AOP2

VDD18_LPADC

VDD18_LPOSC

VDDIO18_GRP1
VDDIO18_GRP1
VDDIO18_GRP1
VDDIO18_GRP1
VDDIO18_GRP1
VDDIO18_GRP1
VDDIO18_GRP1
VDDIO18_GRP1
VDDIO18_GRP1
VDDIO18_GRP1

VDDIO18_GRP2
VDDIO18_GRP2
VDDIO18_GRP2
VDDIO18_GRP2
VDDIO18_GRP2
VDDIO18_GRP2

VDDIO18_GRP3
VDDIO18_GRP3

VDDIO18_GRP4
VDDIO18_GRP4

VDD18_TSADC
VDD18_TSADC
VDD18_TSADC
VDD18_TSADC
VDD18_TSADC

VDD18_MIPI
VDD18_MIPI
VDD18_MIPI

VDD18_USB

VDD18_FMON

VDD18_EFUSE1
VDD18_EFUSE2

SYM 14 OF 18

BGA

VDD12_PLL_CPU

VDD12_PCIE_REFBUF
VDD12_PCIE_REFBUF

VDD12_DN_PCIE
VDD12_UP_PCIE

VDD12_STG0_PCIE
VDD12_STG1_PCIE

VDD12_PLL_SOC
VDD12_PLL_SOC
VDD12_PLL_SOC

VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2

VDD11_XTAL

VDD33_USB

Y18

V18

AK24
AM23

AM29
G14

AM13
AM18

AC23
AD24
AE23

AG1
AG37
AJ1
AJ37
AK1
AK37
AU3
AU34
AU35
AU4
B3
B4
C34
D34
J1
J37
K1
K37
M1
M37
W3
W35
Y3
Y35

AN23

F21

PP1V2_AWAKE

CRITICAL

1

C4550

2.2UF

20%
4V

2

X6S-CERM
0201

VOLTAGE=1.2V
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000

10mA Max

PP1V2_AWAKE_SOC_PLLCPU_F
PP1V2_AWAKE_SOC_PCIEREFBUF_F

VOLTAGE=1.2V
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000

CRITICAL

PP1V2_AWAKE_SOC_PCIEPLL_F

VOLTAGE=1.2V
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000

CRITICAL

PP1V2_AWAKE_SOC_PLLSOC_F

VOLTAGE=1.2V
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000

CRITICAL

PP1V1_SLPDDR_SOC_XTAL_F

VOLTAGE=1.1V
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.0750

PP3V3_AWAKE

CRITICAL

1

C4595

0.1UF

10%

6.3V

2

X6S
0201

12mA Max

74

74

C4560

0.1UF

10%

6.3V
X6S

0201

C4565

2.2UF

20%

X6S-CERM

4V

0201

C4570

0.1UF

10%

6.3V
X6S

0201

CRITICAL

C4590

1

2

1

2

1

2

CRITICAL

1

2

0.1UF

10%

6.3V
X6S

0201

CRITICAL

C4555

0.1UF

10%

6.3V
X6S

0201

R4560

0

21

5%

1/20W

MF

0201

C4566

2.2UF

20%

X6S-CERM

4V

0201

CRITICAL

C4571

0.1UF

10%

6.3V
X6S

0201

C4580

2.2UF

20%
4V
X6S-CERM
0201

R4590

1%

1/20W MF 0201

L4590

FERR-240OHM-25%-350MA

1

2

R4555

1

2

1

2

1/20W

0201

CRITICAL

1

C4561

0.1UF

10%

6.3V

2

X6S
0201

CRITICALCRITICAL

C4567

2.2UF

X6S-CERM

R4570

1

2

CRITICAL

1

2

5.1

0201

1/20W

0201

C4581

2.2UF

20%
4V
X6S-CERM
0201

21

0

5%
MF

0

5%
MF

21

21

1

20%

4V

2

0201

21

CRITICAL

1

2

CRITICAL

1

C4591

2.2UF

20%
4V

2

X6S-CERM
0201

PP1V2_AWAKE

PP1V2_AWAKE

CRITICAL

1

C4562

2.2UF

20%
4V

2

X6S-CERM
0201

CRITICAL

C4568

2.2UF

20%

X6S-CERM

PP1V2_AWAKE

CRITICAL

1

C4572

2.2UF

20%
4V

2

X6S-CERM
0201

C4582

2.2UF

20%
4V
X6S-CERM
0201

PP1V1_SLPDDR

4V

0201

1

2

13mA Max

80mA Max

R4565

0

5%

1

2

1/20W

MF

0201

PP1V1_SLPS2R

CRITICAL

C4583

2.2UF

20%
4V
X6S-CERM
0201

4mA Max

SYNC_MASTER=X589_BIGSUR

PAGE TITLE

74

37 74

21

PP1V2_AWAKE

31mA Max

74

74

1.74A Max

74

60mA Max

37 74

SYNC_DATE=02/13/2017

C

B

A

R4545

8

PP1V8_AWAKE

74

1mA Max

49.9

1/20W

1%
MF

201

21

CRITICAL

1

C4545

1UF

20%

6.3V

2

X6S-CERM
0201

67

SoC Power 3

DRAWING NUMBER

051-05232

Apple Inc.

REVISION

2.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=T290

35 4

IV ALL RIGHTS RESERVED

2

BRANCH

proto4b

PAGE

45 OF 152

SHEET

37 OF 86

1

SIZE

D

678

www.laptoprepairsecrets.com

3 245

1

D

C

B

A1
A10
A11

A2
A22
A24

A3
A31
A34
A35
A36
A37

A5

A6

A8
AA1

AA11
AA13
AA15
AA17
AA19
AA21
AA23
AA25
AA27

AA3

AA30
AA31
AA35
AA37
AB12
AB14
AB16
AB18
AB20
AB22
AB24
AB26
AB28
AB29
AB31
AB33

AB5
AB7
AC1

AC11
AC13
AC15
AC17
AC19
AC21
AC25
AC27
AC30
AC31
AC35
AC37

AC7
AC8

AD10
AD12
AD14
AD18
AD20
AD22
AD26
AD29

AD3

AD31
AD34

AD7

AE11
AE13
AE15
AE17
AE19
AE21
AE25
AE27
AE30
AE31
AE33

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

U3900

H9M

BGA

SYM 15 OF 18

OMIT_TABLE

CRITICAL

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

AE4
AE5
AE7
AE8
AF1
AF10
AF14
AF16
AF20
AF22
AF24
AF26
AF28
AF29
AF3
AF31
AF35
AF37
AF5
AF7
AF8
AG11
AG13
AG15
AG17
AG19
AG21
AG23
AG25
AG27
AG30
AG31
AG5
AG7
AG9
AH1
AH10
AH12
AH14
AH16
AH18
AH20
AH22
AH24
AH26
AH28
AH29
AH31
AH33
AH37
AH5
AH7
AH8
AJ11
AJ13
AJ17
AJ19
AJ23
AJ25
AJ3
AJ30
AJ31
AJ35
AJ7
AJ9
AK10
AK14
AK16
AK18
AK20
AK22
AK26
AK28
AK5
AK7
AK8
AL1
AL10
AL13
AL15
AL19
AL2

AL21
AL23
AL25
AL27
AL29
AL31
AL32
AL33
AL36
AL37

AL5
AL7

AL9
AM11
AM12
AM17

AM2
AM22
AM24
AM28
AM32
AM36

AM5

AM6

AM7

AM8

AN1
AN10
AN12
AN14
AN15
AN17
AN19
AN20
AN21
AN24
AN26
AN27
AN29
AN31
AN32
AN37

AN6

AN7

AN8

AN9
AP10
AP15
AP20
AP23
AP24
AP27

AP3
AP32
AP33
AP35

AP5

AP6

AP8

AP9

AR1
AR10
AR11
AR13
AR15
AR16
AR18
AR20
AR22
AR23
AR24
AR25
AR27
AR28
AR30
AR32
AR37

AR6

AR8

AT1
AT10
AT12
AT14
AT15
AT17

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

U3900

H9M

BGA

SYM 16 OF 18

OMIT_TABLE

CRITICAL

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

AT19
AT20
AT21
AT23
AT24
AT26
AT27
AT29
AT3
AT31
AT32
AT34
AT35
AT37
AT4
AU1
AU10
AU15
AU2
AU20
AU23
AU24
AU27
AU32
AU33
AU36
AU37
AU6
AU8
AV1
AV10
AV11
AV13
AV15
AV16
AV18
AV2
AV20
AV22
AV25
AV27
AV28
AV3
AV30
AV32
AV33
AV35
AV36
AV37
AV6
B1
B11
B13
B16
B19
B2
B22
B24
B31
B34
B36
B37
B5
B6
C1
C11
C22
C23
C24
C25
C26
C27
C28
C29
C3
C30
C31
C32
C33
C35
C37
C4
C5
C6

C7
C9

D1
D10
D11
D12
D13
D14
D16
D17
D19
D20
D22
D24
D25
D26
D27
D28
D29
D30
D31
D32
D33
D35
D36
D37

D5

D6

D8
E11
E12
E13
E14
E15
E16
E17
E18
E19
E20
E21
E22
E24
E25
E26
E27
E28
E29

E3
E30
E31
E32
E33
E34
E35
E36

E5

E6

F1
F11
F12
F13
F14
F15
F16
F17
F18
F19
F20
F24
F25
F28
F29
F30
F31
F32
F33
F34
F35
F36
F37

F5

F6

F7

F9

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

U3900

H9M

BGA

SYM 17 OF 18

OMIT_TABLE

CRITICAL

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

G10
G15
G17
G19
G2
G21
G24
G26
G28
G30
G31
G32
G33
G36
G6
G7
G8
H1
H10
H12
H14
H16
H18
H2
H20
H24
H26
H29
H31
H33
H36
H37
H5
H7
H9
J17
J19
J21
J23
J25
J27
J30
J31
J7
J8
K10
K12
K14
K16
K18
K20
K22
K24
K26
K28
K29
K3
K31
K33
K35
K5
K7
K9
L1
L11
L13
L15
L17
L19
L21
L23
L25
L27
L30
L31
L37
L7
L8
M10
M12
M14
M16
M18
M20

M22
M24
M26
M28
M29
M31

M7
M9

N1
N11
N13
N15
N19
N21
N23
N25
N27

N3
N30
N31
N33
N35
N37

N5

N7

N8
P10
P12
P14
P18
P20
P22
P24
P26
P28
P29
P31

P5

P7
R11
R13
R15
R17
R19
R21
R23
R25
R27
R30
R31

R7

R8

T1
T10
T12
T14
T16
T18
T20
T22
T24
T26
T28
T29

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

U3900

H9M

BGA

SYM 18 OF 18

OMIT_TABLE

CRITICAL

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

T3
T31
T33
T35
T37
T5
T7
U11
U13
U15
U17
U19
U21
U23
U25
U27
U30
U31
U7
U8

V1

V10
V12
V14
V16
V20
V22
V24
V26
V28
V29
V3
V31
V35
V37
W11
W13
W15
W17
W19
W2
W21
W23
W25
W27
W30
W31
W33
W36
W5
Y10
Y12
Y14
Y16
Y2
Y20
Y22
Y24
Y26
Y28
Y29
Y31
Y36

D

C

B

A

8

67

SYNC_MASTER=X589_BIGSUR

PAGE TITLE

SYNC_DATE=02/13/2017

A

SoC Ground

DRAWING NUMBER

051-05232

Apple Inc.

REVISION

2.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=T290

35 4

IV ALL RIGHTS RESERVED

2

BRANCH

proto4b

PAGE

46 OF 152

SHEET

38 OF 86

1

SIZE

D

678

www.laptoprepairsecrets.com

3 245

1

PECI Level Shifting

D

31

31

31

40 33

40 33

40 33

54 40

54 33

54 40

Boot Config

OUT
OUT
OUT

BOOT_CONFIG0
BOOT_CONFIG1
BOOT_CONFIG2

Board ID

OUT
OUT
OUT
OUT
OUT
OUT

SPI_SOCROM_CLK
SPI_SOCROM_MOSI
SPI_SOCROM_MISO
SPI_TPAD_MOSI
SPI_TPAD_MISO
SPI_TPAD_CLK

BOOTCFG0

1

R4700

1K

5%
1/20W
MF
201

2

BOARDID0

1

R4710

3.0K

5%
1/20W
MF
201

2

BOOTCFG1

1

R4701

1K

5%
1/20W
MF
201

2

BOARDID1

1

R4711

3.0K

5%
1/20W
MF
201

2

PP1V8_AWAKE

BOOTCFG2

1

R4702

1K

5%
1/20W
MF
201

2

BOARDID2

1

R4712

3.0K

5%
1/20W
MF
201

2

BOARDID3

1

R4713

3.0K

5%
1/20W
MF
201

2

34 39 40 74

BOOTCFG2

BOARDID4

1

R4714

3.0K

5%
1/20W
MF
201

2

0
0
1
1

BOOTCFG0

0
1

BOOTCFG1

0
1
0
1

PP1V8_AWAKE

BOARDID5

1

R4715

3.0K

5%
1/20W
MF
201

2

Test Mode

Disabled

Enabled

Frequency

40 MHz

6 MHz

24 MHz

Invalid

34 39 40
74

32

IN

PLACE_NEAR=U3900.T6:5MM

SMC_PECI_TX

BYPASS=U4750::5MM

R4750

0

21

PP1V8_PRIM_PCH

75

BYPASS=U4755::5MM

32

OUT

SMC_PECI_RX

10%
10V

0201

1

2

C4750

0.1UF

X5R-CERM

SMC_PECI_TX_R

0201MF1/20W5%

10%
10V

0201

1

2

C4755

0.1UF

X5R-CERM

B1

A

126

1

U4755

74AVC1T45

SOT886

A

5

DIR

CRITICAL

U4750

A2

74AUC1G126

BGA-YZP

Y

OE

CRITICAL

A1

C1

6

VCCBVCCA

GND

2

C2

B

PP1V05_VCCST_OUT

64 57 14 8 6

D

BYPASS=U4755::5MM

1

C4756

0.1UF

10%
10V

2

X5R-CERM
0201

43

330

5%
MF

201

1

2

R4755

1/20W

CPU_PECI

BI

6

C

31

31

33

PP1V8_AWAKE

74

Board Revision

BOARDREV0

1

R4720

1K

5%
1/20W
MF
201

2

OUT
OUT
OUT

BOARD_REV0
BOARD_REV1
BOARD_REV2

SEP EEPROM

BOARDREV1

1

R4721

1K

5%
1/20W
MF
201

2

See <rdar://problem/50175583> for J230k assignments

PP1V8_AWAKE

BOARDREV2

1

R4722

1K

5%
1/20W
MF
201

2

34 39 40 74

PCH PM Level Shifting

PP1V8_SLPS2R

74

BYPASS=U4760::5MM

PQFP

GND

10

2

11

VCCBVCCA

15

1B1

13

2B1

14

1B2

12

2B2

3

U4760

SN74AVC4T245RSV

CRITICAL

10%
10V

0201

1

2

1

2

6

1A1

8

2A1

4

1DIR

1

1OE*

7

1A2

9

2A2

5

2DIR

16

2OE*

C4760

0.1UF

X5R-CERM

32

78 32 78 14

32

32

SMC_SYSRST_L

IN

SMC_PCH_SYS_PWROK

IN OUT

SMC_PCH_PWROK

IN

SMC_RSMRST_L

IN

5%
MF

201

2

R4762

1

100K

5%

1/20W

MF

201

1

R4763

2

100K

5%

1/20W

MF

201

R4760

100K

5%

1/20W

MF

201

2

R4761

1

100K

1/20W

BYPASS=U4760::5MM

1

C4765

0.1UF

10%
10V

2

X5R-CERM
0201

1

R4765

100K

5%
1/20W
MF
201

2

1

R4767

100K

5%
1/20W
MF
201

2

1

R4766

100K

5%
1/20W
MF
201

2

PP3V3_S5

1

R4768

100K

5%
1/20W
MF
201

2

PM_SYSRST_R_L

1/20W

R4769

201MF5%

74

2.2K

21

PM_SYSRST_L
PM_PCH_SYS_PWROK

PM_PCH_PWROK_SMC
PM_RSMRST_R_L

OUT

OUT
OUT

14

17

18

C

B

A

5%
MF

201

1

2

I2C_SEP_SCL

R4730

2.2K

1/20W

31

IN BI

Swapped for non CSP package per

rdar://problem/33172008

SDA pull added per

rdar://problem/30924615

SMC AVREF Supply

Footprint supports 353S01042 alternate

PP1V8_SLPS2R

74

BYPASS=U4780::3MM

20%

6.3V
X5R

1

2

C4780

1.0UF

0201-1

VCC

U4730

M24128

EEPROM

3
2
1
7

E2
E1
E0
WC*

MLP

SCL SDA

VSS

4

U4780

REF3312AIRSE

UQFN-COMBO

5

IN

CRITICAL

4

8

THM_P

9

GND

OUT

NC0
NC1

NC2

NC3
NC4

BYPASS=U4730::3MM

1

C4730

0.1UF

10%
10V

2

X5R-CERM
0201

1

R4731

2.2K

5%
1/20W
MF
201

2

56

I2C_SEP_SDA

31

78 66 17 11 8

64 6

IN

78 18 14

IN

THRMTRIP# Isolation

PP1V05_S0_CPU_VCCST

BYPASS=U4740::3MM

10%
10V

1

2

U4740

8

1

3

7

5

4

2

74AXP1T57

SOT833

6

CPU_SMC_THRMTRIP_L

rdar://problem/33171763

C4740

0.1UF

X5R-CERM

PM_THRMTRIP_L

PLT_RST_L

PP1V8_PRIM_PCH

BYPASS=U4740::3MM

1

C4741

0.1UF

10%
10V

2

X5R-CERM
02010201

OUT

32

75

40

33

SoC ROM

PP1V8_AWAKE

74

OMIT_TABLE

10K

5%
MF

201

1

8

CRITICAL

VCC

U4770

2

SCLK SI/SIO0

4MX8-1.8V

USON

56

1

R4770

100K

5%

1/20W

MF

201

SPI_SOCROM_CLK SPI_SOCROM_MOSI

IN

R4771

1/20W

2

MX25U3235F

SPI_SOCROM_CS_L

IN

SPI_SOCROM_WP_L

1

CS*

3

WP*/SIO2

7

RESET*/SIO3

VER 2

GND

4

SO/SIO1

EPAD

EPAD

10

9

2

BYPASS=U4770::5MM

1

C4770

0.1UF

10%
10V

2

X5R-CERM
0201

SPI_SOCROM_MUX_MISO_R

R4773

20

21

SPI_SOCROM_MISO

PLACE_NEAR=U4770.2:5MM

B

40

IN

40

MF 1/20W 2015%

OUT

PROCHOT# Level Shifting

rdar://problem/34583713

PP1V8_PRIM_PCH

75

PP1V25_SLPS2R_SMC_AVREF

8

1

NC

2

NC

3

NC

6

NC

7

NC

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.0750
VOLTAGE=1.25V

BYPASS=U4780::3MM

1

C4781

1.0UF

20%

6.3V

2

X5R
0201-1

GND_SMC_AVSS

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000
VOLTAGE=0V

46 45 44 32

32

57 40 32

R4790

10K

1/20W

201

SMC_PROCHOT_L

1

5%
MF

2

6

VCC

U4790

74LVC1G07FW5

DFN1010

2

A

NC NC

1

GND

3

4

Y

5

NCNC

CRITICAL

BYPASS=U4790::3MM

1

C4790

0.1UF

10%
10V

2

X5R-CERM
0201

R4791

75

2 1

5%

1/20W

MF

201

SYNC_MASTER=X589_BIGSUR SYNC_DATE=03/16/2017

PAGE TITLE

A

SoC Shared Support

CPU_PROCHOT_LCPU_PROCHOT_RS_L

6

OUTIN

DRAWING NUMBER

051-05232

Apple Inc.

REVISION

2.0.0

BRANCH

proto4b

PAGE

47 OF 152

SHEET

39 OF 86

BOM_COST_GROUP=T290

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SIZE

D

8

67

35 4

2

1

678

www.laptoprepairsecrets.com

3 245

1

D

A

78 53 40

78 49 40

Lid Detect Logic

PP1V8_SLPS2R

49 74

1M

5%
MF

1

2

From Mic Flex

SMC_LID_LEFT

SMC_LID_RIGHT

R4804

5% 1/20W

R4805

5%

From RIO

10K

10K

21

MF 201

21

201MF1/20W

R4800

1/20W

Clamshell Open = High
Clamshell Closed = Low

1

R4801

1M

5%
1/20W
MF
201201

2

LID_OPEN_LEFT
LID_OPEN_LEFT

MAKE_BASE=TRUE

BYPASS=U4802::5MM

10%

6.3V
0201

1

2

2

1

C4802

0.1UF

CERM-X5R

LID_OPEN_RIGHT
LID_OPEN_RIGHT

MAKE_BASE=TRUE

NC

5 3

NC

U4802

6

74LVC1G32

SOT891

SSD Pull-Up/Downs

32

BI

PP1V8_SLPS2R
PP1V8_AWAKE

R4883

4

IPD_LID_OPEN SSD0_CLKREQ1_L

OUT

78 53

R4884
R4887
R4888

R4885
R4886
R4895

32

OUT

47K
47K
47K
47K

100K

47K

100K

21

5% 201

21

5% MF 2011/20W

21
21

21

5% MF 2011/20W

21
21

31 74

34 39 74

MF1/20W

2011/20W MF5%

MF5% 1/20W 201

201MF5% 1/20W

1/20W5% MF 201

SSD0_CLKREQ0_L

SSD0_CLKREQ2_L
SSD0_CLKREQ3_L

SSD0_PCIE_RESET_L
SSD0_CLK24M
SSD_PMU_RESET_L

70 34

71 34

34

34

71 70 34

73 40

31

G

H

SMC ADC AssignmentsD

44

44

44

44

44

44

44

46

IN

IN

IN

IN

IN

IN

IN

IN

SMC_DCIN_VSENSE

MAKE_BASE=TRUE

SMC_DCIN_ISENSE

MAKE_BASE=TRUE

SMC_PBUS_VSENSE

MAKE_BASE=TRUE

SMC_BMON_ISENSE

MAKE_BASE=TRUE

SMC_CPU_HS_ISENSE

MAKE_BASE=TRUE

SMC_3V3G3HMAIN_ISENSE

MAKE_BASE=TRUE

SMC_5VG3S_ISENSE

MAKE_BASE=TRUE

SMC_SSD0_ISENSE

MAKE_BASE=TRUE

SMC_DCIN_VSENSE
SMC_DCIN_ISENSE
SMC_PBUS_VSENSE
SMC_BMON_ISENSE
SMC_CPU_HS_ISENSE
SMC_3V3G3HMAIN_ISENSE
SMC_5VG3S_ISENSE
SMC_SSD0_ISENSE

PCIe Up R2D AC Caps

(All Caps)

GND_VOID=TRUE

21
20% X5R6.3V 0201

21

6.3V X5R20%

15

15

IN
IN

PCIE_SOC_R2D_C_P<0>
PCIE_SOC_R2D_C_N<0>

C4820

0.22UF

C4821

0.22UF

0201

32

OUT

32

OUT

32

OUT

32

OUT

32

OUT

32

OUT

32

OUT

32

OUT

PCIE_SOC_R2D_P<0>
PCIE_SOC_R2D_N<0>

OUT
OUT

D

34

34

C

B

31

31

31

64 32

IN

IN

IN

IN

78 49 40

78 53 40

C

Secure Disable SoC Pull-Up/Downs

PP1V8_SLPS2R

53 74

BYPASS=U4850::5MM

C4850

0.1UF

10%

6.3V

CERM-X5R

0201

1

2

1

R4850

1K

5%
1/20W
MF
201

2

1

VDD

EB

PP1V8_G3S

75

1

R4873

100K

5%
1/20W
MF
201

2

U4850

SEP_CAM_DISABLE_L
SEP_DMIC_DISABLE_L
SEP_DISABLE_STROBE
PMU_COLD_RESET_L
SMC_LID_RIGHT

SMC_LID_LEFT
LID_CTRL_DMIC

2

CAM_DIS*

3

DMIC_DIS*

4

DIS_STROBE

9

PMU_COLD_RST*

13

LID_RIGHT

14

LID_LEFT

6

SEL

SLG4AP41496V

STQFN

GND

8

CAM_DIS_OUT*

DMIC_DIS_OUT*

CAM_DIS_OUT

DMIC_DIS_OUT

RFU

12

SEP_CAM_DISABLE_OUT_L

7

SEP_DMIC_DISABLE_OUT_L

10

11

5

NC
NC

NC

OUT

OUT

69

52

78 49 31

81 78 31 23

MESA_PWR_EN

SOC_DFU_STATUS

SOC_HOLD_RESET

31

SOC_TESTMODE

31

1

R4871

10K

5%
1/20W
MF
201 201

2

1

R4872

10K

5%
1/20W
MF

2

1

R4874

47K

5%
1/20W
MF
201

2

SMC PROCHOT Control Circuit

PP3V3_S5

40 74

BYPASS=U4880::5MM

5%
MF

201

1

1

VDD

2

U4880

SLG4AP41473

STQFN

2 3

ENABLE

9

COMP_INPUT

DUMMY_OUTPU_COMP

VREF_1V2

10

NC

PBUS_DIVIDER_REF

76

IN

C4880

0.1UF

6.3V

CERM-X5R

0201

UVP_DIS_L

10%

1

2

R4880

100K

1/20W

I

21

6.3V 0201X5R20%

21

21
20% X5R 02016.3V

21

6.3V

21

6.3V 020120%

21

X5R 020120%

X5R

PCIE_SOC_R2D_P<1>
PCIE_SOC_R2D_N<1>

0201X5R20% 6.3V

PCIE_SOC_R2D_P<2>
PCIE_SOC_R2D_N<2>

PCIE_SOC_R2D_P<3>
PCIE_SOC_R2D_N<3>

02016.3V X5R20%

15

15

15

15

15

IN
IN

IN
IN

IN

PCIE_SOC_R2D_C_P<1>
PCIE_SOC_R2D_C_N<1>

PCIE_SOC_R2D_C_P<2>
PCIE_SOC_R2D_C_N<2>

PCIE_SOC_R2D_C_P<3>
PCIE_SOC_R2D_C_N<3>

C4822

0.22UF

C4823

0.22UF

C4824

0.22UF

C4825

0.22UF

C4826

0.22UF

C4827

0.22UF

GPIO Source Termination

I2S_SPKRAMP_L_R2D_R

PLACE_NEAR=U3900.AG34:5MM

I2S_SPKRAMP_L_BCLK_R

PLACE_NEAR=U3900.AA32:5MM

33

IN OUT

33

IN OUT

33

IN

33

IN OUT

33

IN

33

IN

33 54 39

IN OUT

33

IN OUT

33

IN OUT

33

IN

34

IN OUT

32

IN

32

IN

I2S_SPKRAMP_L_LRCLK

PLACE_NEAR=U3900.AG33:5MM

I2S_SPKRAMP_R_R2D_R

PLACE_NEAR=U3900.C20:5MM

I2S_SPKRAMP_R_BCLK_R

PLACE_NEAR=U3900.C21:5MM

I2S_SPKRAMP_R_LRCLK

PLACE_NEAR=U3900.A21:5MM

I2S_CODEC_R2D_R

PLACE_NEAR=U3900.AB34:5MM

I2S_CODEC_BCLK_R

PLACE_NEAR=U3900.AF33:5MM

SPI_TPAD_MOSI_R

PLACE_NEAR=U3900.N34:5MM

SPI_TPAD_CLK_R

PLACE_NEAR=U3900.P35:5MM

SPI_MESA_MOSI_R

PLACE_NEAR=U3900.A20:5MM

SPI_MESA_CLK_R

PLACE_NEAR=U3900.C19:5MM

SSD0_CLK24M_R

PLACE_NEAR=U3900.AP7:5MM

PDM_DMIC_CLK0_R

PLACE_NEAR=U3900.P6:5MM

PDM_DMIC_CLK1_R

PLACE_NEAR=U3900.K2:5MM

R4843
R4844
R4841
R4845
R4846
R4842
R4847
R4848
R4851
R4852
R4853
R4854
R4857
R4859
R4860

20
20
20
20
20
20

20
20
20
20
20
20
20
20

21

I2S_SPKRAMP_L_R2D

21

I2S_SPKRAMP_L_BCLK

21

I2S_SPKRAMP_L_LRCLK_R

5%

21

I2S_SPKRAMP_R_R2D

1/20W5% 201

21

I2S_SPKRAMP_R_BCLK

5% MF1/20W

21

I2S_SPKRAMP_R_LRCLK_R

21

I2S_CODEC_R2D

21

I2S_CODEC_BCLK

21

SPI_TPAD_MOSI

1/20W

21

SPI_TPAD_CLK

21

SPI_MESA_MOSI

21

SPI_MESA_CLK

21

SSD0_CLK24M

21

PDM_DMIC_CLK0

5% 1/20W

21

PDM_DMIC_CLK1

1/20W5% 201MF

MF

MF1/20W5% 201

MF

201MF1/20W5%

2015% 1/20W MF

201MF1/20W

201

201MF5%201/20W

201MF1/20W5%

201MF5%

201MF1/20W5%

201MF1/20W5%

2011/20W5% MF

2011/20W5%

201MF

OUTIN

OUTIN

OUT

OUT

OUT

OUT

OUT

OUT

50 33

50 33

50

OUT
OUT

OUT
OUT

OUT
OUTIN

78 49

78 49

78 49

78 49

78 49

54 39

78 49

78 49

73 40

78 53

78 53

34

34

34

34

34

34 15

C

B

A

11

5
8

NC

NC
NC
NC

PBUS_DIVIDER_OUT

CPU_THROTTLE*

GPU_THROTTLE*

THROTTLE*_TEST_OUTPUT

GND

7

12

6

4

40 74

SMC_PROCHOT_L

NC
NC

PP3V3_S5

BYPASS=U4885::5MM

C4885

0.1UF

10%

6.3V

CERM-X5R

0201

U4885

LMV331

1

2

4

SC70-5

5

VCC+

GND

2

OUT

3

1

PBUS_DIVIDER

57 39 32

1

C4881

0.1UF

10%

6.3V

2

CERM-X5R
0201

PPBUS_G3H

1

R4881

665K

0.1%
1/20W
TK
0201

2

1

R4882

127K

0.1%
1/20W
MF
0201

2

75

F

SE Host Wake

R4899

SE_HOST_WAKE

5%MF 1/20W 0201

21

0

J

Overloaded GPIOs

TPAD_KBD_WAKE_L

32

TPAD_SPI_INT_L

32

NC_TPAD_ACTUATOR_DISABLE_L

32

SPI_SOCROM_MOSI

39

SPI_SOCROM_CLK

39

SPI_SOCROM_MISO

39

SYNC_MASTER=X589_BIGSUR

PAGE TITLE

SE_HOST_WAKE_R

32 41

OUTIN

BOM_COST_GROUP=T290

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE

MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE

SoC Project Support

TPAD_KBD_WAKE_L
TPAD_SPI_INT_L

NC_TPAD_ACTUATOR_DISABLE_L

SPI_SOCROM_MOSI
SPI_SOCROM_CLK
SPI_SOCROM_MISO

DRAWING NUMBER

Apple Inc.

REVISION

BRANCH

PAGE

SHEET

78 54 53

54

39 33

39 33

39 33

SYNC_DATE=02/13/2017

SIZE

051-05232

D

2.0.0

proto4b

48 OF 152

40 OF 86

A

8

67

35 4

2

1

678

www.laptoprepairsecrets.com

3 245

1

Venus - Secure Element

PP1V8_G3S

41 75

D

C

PP3V3_G3S

75

Always On GPIOs

R5012
R5013

PP1V8_G3S

41 75

47K
47K

C5051

2.2UF

20%

6.3V
X5R

0201

21

5%

21

1

2

1

2

1/20W5%

R5015

22K

5%
1/20W
MF
201

C5052

2.2UF

20%

6.3V
X5R

0201

41 31

MF1/20W 201

201MF

41 33

41 33

41 33

41 33

40

41 31

1

2

C5014

1.0UF

20%

6.3V
X5R

C5053

1.0UF

20%

6.3V
X5R

0201-1

SE_CTLR_FW_DWLD

IN

SE_GPIO2_AO
SE_GPIO3_AO

UART_SE_R2D_RTS_L

IN

UART_SE_D2R_CTS_L

OUT

UART_SE_R2D

IN

UART_SE_D2R

OUT

SE_HOST_WAKE

OUT

IN

SE_DEV_WAKE

D

10%

6.3V
02010201-1

1

C5003

0.1UF

2

CERM-X5R

1

C5002

0.1UF

2

CERM-X5R

10%

6.3V
0201

1

2

VDDA_SN100V

20%

6.3V
X5R

0201

1

2

VDDC_SN100V

C5011

0.22UF

VDDNV_SN100V
VDDPLL_SN100V
VHV_SN100V
VREF_SN100V

1

NCNC

2

E5

C3

C1

C2

B1

H5

A3

E1

A8

A7

A6

B7

B6

B5

VDDA

VBATPWR

VDDC

VDDCIN

VDDBOOST

U5000

SN100VUK-B20191

WLCSP

OMIT_TABLE

DIS SEDIG NFC

VDDIO

VDDIO_SE

NC

NC
NC

NC
NC
NC

H8

NFC_CLK_REQ

J8

NFC_DWL_REQ

E4

NFC_GPIO0

F3

NFC_GPIO1

G6

NFC_GPIO2_AO

G5

NFC_GPIO3_AO

F2

NFC_HSU_CTS

F5

NFC_HSU_RTS

E3

NFC_HSU_RX

F4

NFC_HSU_TX

H7

NFC_IRQ

A5

NFC_SIM_SWIO1

B8

NFC_SIM_SWIO2

C8

NFC_SIM_SWIO3

G7

NFC_WKUP_REQ

G3

NFC_CLK_32K

PMUVCC3

PMUVCC2

PMUVCC1

SIMVCC1

SIMVCC2

SIMVCC3

VBAT

B3

VDDNV

NC NCNCNC

H2

VDDPA

F1

H3

VHV

VDDPLL

SE_I2C_SCL
SE_I2C_SDA

SE_ISO_CLK

SE_ISO_IO

SE_ISO_RST

SE_SPI_CLK

SE_SPI_CS
SE_SPI_MISO
SE_SPI_MOSI

G1

D2

VUP

VREF

SE_GPIO0
SE_GPIO1

BOOST_LX

F8
D4

G8
F7

D6
D7
D3

E8
E6
E7
D5

A1

NC
NC

NC
NC

NC
NC
NC

NC
NC
NC
NC

NC

1

C5004

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C5017

0.22UF

20%

6.3V

2

X5R
0201

1

C5008

0.22UF

20%

6.3V

2

X5R
0201

1

C5009

0.22UF

20%

6.3V

2

X5R

1

C5010

0.22UF

20%

6.3V

2

X5R
02010201

C

B

Avoid false wakeup

R5010
R5011

100K
100K

SE_XTAL1

NC
NC

NC

21

5%

21

1/20W5%

201MF1/20W
201MF

SE_RX_P
SE_RX_N

NC
NC

NC
NC

64

SE_PWR_EN

IN

NC

H6

NFC_XTAL1

B4

NFC_SIM_SWCTRL1

C6

NFC_SIM_SWCTRL2

J7

NFC_XTAL2

J5

RXP

J4

RXN

J1

TX1

J3

TX2

G2

TXVCASC

H1

TXVCM

C4

VEN

J6

RXVCM

ANALOG SIGNAL

VSS_DIG

VSS_DIG

VSS_DIG

D8

C7

C5

VSS_NFC

VSS_PA

J2

G4

VSS_PLL

VSS_PMU

D1

H4

VSS_PWR

VSS_PWR

B2

A2

VSS_SUB

VSS_REF

A4

E2

B

VSS_SUB

F6

A

PP1V8_G3S

R5001
R5002
R5003
R5004
R5000
R5006

100K
100K
100K
100K
100K
100K

75

21
21
21
21

5% 1/20W MF 201

21

5% 1/20W MF

21

MF1/20W5%

MF1/20W5% 201

UART_SE_R2D

201

UART_SE_D2R

2015% 1/20W MF

UART_SE_R2D_RTS_L

2015% 1/20W MF

UART_SE_D2R_CTS_L
SE_CTLR_FW_DWLD

201

SE_DEV_WAKE

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

998-15216 SE:DEV_SW_NU5000 CRITICAL1

IC,SN100V,VENUS,DEV KEY,B2,S/W-M,WLCSP72

IC,SN100V,VENUS,PROD KEY,B2,SW-N,WLCSP72

CRITICAL338S00445 U5000 SE:PROD_SW_N1

SYNC_MASTER=X941_MLB

PAGE TITLE

SYNC_DATE=03/10/2017

A

Secure Element

DRAWING NUMBER

41 33

41 33

41 33

41 33

41 31

41 31

<rdar://problem/45108950> Mac - Venus Reference guide and De-coupling requirements

BOM_COST_GROUP=T151

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

Apple Inc.

051-05232

REVISION

2.0.0

BRANCH

proto4b

PAGE

50 OF 152

SHEET

41 OF 86

SIZE

D

8

67

35 4

2

1

678

www.laptoprepairsecrets.com

3 245

1

D

ICL-LN PCH S0 "SMBUS 0" Connections

PP3V3_S5

9 59 74

ICL-LN PCH

U0500

(MASTER)

SMBUS_PCH_CLK

13

MAKE_BASE=TRUE

SMBUS_PCH_DATA

13

MAKE_BASE=TRUE

R5202

2.2K

5%

1/20W

MF

201 201

1

2

1

R5203

2.2K

5%
1/20W
MF

2

ICL-LN PCH S0 "SMLINK 0" Connections

5 13 14 17 18 74

PP3V3_S5

32 23

32 23

32 23

SMC I2C "0" G3H Connections

PP1V8_SLPS2R

74

SMC (SoC)

U3900

(MASTER)

I2C_UPC_SCL

MAKE_BASE=TRUE

I2C_UPC_SDA

MAKE_BASE=TRUE

UPC_I2C_INT_L

MAKE_BASE=TRUE

(IPU)

R5200

2.2K

5%

1/20W

MF

201 201

SMC I2C "4" G3H Connections

PP1V8_SLPS2R

55 74

UPC Port X

1

2

1

2.2K 4.7K

5%
1/20W
MF

2

R5201

(Ace X W:0x70 R:0x71)
(Ace T W:0x7E R:0x7F)
(All-Ace W:0xD6 R:0xD7)

I2C_UPC_SCL
I2C_UPC_SDA
UPC_I2C_INT_L

I2C_UPC_SCL
I2C_UPC_SDA
UPC_I2C_INT_L

J0500

24

24

24

25

25

25

78 32

78 32

SMC (SoC)

J3900

(MASTER)

I2C_PWR_SCL

MAKE_BASE=TRUE

I2C_PWR_SDA

MAKE_BASE=TRUE

R5240

4.7K

1/20W

1

5%
MF

2

1

R5241

5%
1/20W
MF
201201

2

Battery

J6950

(Write:0x16 Read:0x17)

I2C_PWR_SCL
I2C_PWR_SDA

Battery Charger

U7000

(Write:0x12 Read:0x13)

I2C_PWR_SCL

55

55

56

D

C

ICL-LN PCH

U0500

(MASTER)

16 13

16 13

XDP_PCH_I2C_UPC_SCL

MAKE_BASE=TRUE

XDP_PCH_I2C_UPC_SDA

MAKE_BASE=TRUE

PCH_UPC_I2C_INT_L

13

MAKE_BASE=TRUE

R5206

10K

5%

1/20W

MF

201

I2C_PWR_SDA

1

R5204

2.2K

1/20W

2

5%
MF

201

1

2

1

R5205

2.2K

5%
1/20W
MF
201

2

Ace2 (Port X, Rear)

U3100

(Write:0x70 Read:0x71)

XDP_PCH_I2C_UPC_SCL
XDP_PCH_I2C_UPC_SDA
PCH_UPC_I2C_INT_L

23 24

23 24

23 24

SMC I2C "1" S0 Connections

SMC (SoC)

U3900

UNUSED

PMU

J7800

(Write:0xE8 Read:0xE9)

I2C_PWR_SCL
I2C_PWR_SDA

56

64

64

(MASTER)

Ace2 (Port T, Front)

NC_I2C_SNS0_S0_SCL

32

NC_I2C_SNS0_S0_SDA

32

NC_I2C_SNS0_S0_SCL

MAKE_BASE=TRUE

NO_TEST=1

NC_I2C_SNS0_S0_SDA

MAKE_BASE=TRUE

NO_TEST=1

C

U3200

(Write:0x7E Read:0x7F)

XDP_PCH_I2C_UPC_SCL
XDP_PCH_I2C_UPC_SDA

25

25

SMC I2C "5" G3S Connections

PP1V8_G3S

75

B

PCH_UPC_I2C_INT_L

25

SMC I2C "2" S0 Connections

PP1V8_PRIM_PCH

75

SMC (SoC)

U3900

(MASTER)

I2C_SNS1_S0_SCL

32

MAKE_BASE=TRUE

I2C_SNS1_S0_SDA

32

MAKE_BASE=TRUE

5%
MF

201

1

2

R5220

2.2K 2.2K

1/20W

1

R5221

5%
1/20W
MF
201

2

SMC (SoC)

U3900

(MASTER)

I2C_SNS_G3S_SCL

32

MAKE_BASE=TRUE

I2C_SNS_G3S_SDA

32

MAKE_BASE=TRUE

R5250

2.2K

5%

1/20W

MF

201 201

1

2

1

R5251

2.2K

5%
1/20W
MF

2

Trackpad

J5200

(Write:0x98 Read:0x99)

I2C_SNS_G3S_SCL

(10K IPU)

I2C_SNS_G3S_SDA

(10K IPU)

54

54

Thermal Sensors

U5800

(See thermal sensor page)

I2C_SNS_G3S_SCL
I2C_SNS_G3S_SDA

47

47

B

A

SMC (SoC)

U3900

(MASTER)

I2C_DISP_SCL

32

I2C_DISP_SDA

32

PP1V8_PRIM_PCH

75

R5230

2.2K

5%

1/20W

MF

201 201

1

2

1

R5231

2.2K

5%
1/20W
MF

2

I2C_DISP_LS_EN

R5236

100K

5%

1/20W

MF

201

SMC I2C "3" S0 Connections

1

2

C5230

0.1UF

10%
16V

X5R-CERM

0201

1

1

2

8

VCCVL

U5200

NLSX4402

2
3

5

IO/VL1
IO/VL2

EN

UDFN

IO/VCC1
IO/VCC2

GND

4

1

C5231

0.1UF

10%
16V

2

X5R-CERM
0201

CKPLUS_WAIVE=I2C_PULLUP

7

I2C_TCON_SCL_R

6

I2C_TCON_SDA_R

CKPLUS_WAIVE=I2C_PULLUP

R5232

R5235

R5234

5% 1/20W 201MF

30

30

PP3V3_S0SW_LCD

1

2.2K 2.2K

5%

1/20W

MF

201

2

21

201MF1/20W5%

21

1

R5233

5%
1/20W
MF
201

2

69

Internal Display

(Write: 0x-- Read: 0x--)

I2C_TCON_SCL

J8500

I2C_TCON_SDA

69

69

SMC I2C "6" G3H Connections

SMC (SoC)

U3900

(MASTER)

NC_I2C_SSD0_SCL

32

NC_I2C_SSD0_SDA

32

BOM_COST_GROUP=SOC

UNUSED

NC_I2C_SSD0_SCL

MAKE_BASE=TRUE

NC_I2C_SSD0_SDA

MAKE_BASE=TRUE

SYNC_MASTER=X589_BIGSUR

PAGE TITLE

I2C Connections 1

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

NO_TEST=1

NO_TEST=1

SYNC_DATE=02/13/2017

DRAWING NUMBER

051-05232

REVISION

2.0.0

BRANCH

proto4b

PAGE

52 OF 152

SHEET

42 OF 86

A

SIZE

D

8

67

35 4

2

1

678

www.laptoprepairsecrets.com

3 245

1

D

AP I2C "0" G3S Connections

PP1V8_G3S

75

AP (SoC)

U3900 J8500U3900

(MASTER)

I2C_SPKRAMP_L_SCL

MAKE_BASE=TRUE

I2C_SPKRAMP_L_SDA

33

MAKE_BASE=TRUE

AP I2C "1" G3S Connections

PP1V8_G3S

75

R5300

2.2K

5%

1/20W

MF

201 201

ISP I2C "0" G3S Connections

PP1V8_G3S

69 75

1

2

1

R5301

2.2K 1K

5%
1/20W
MF

2

Left Speaker Amps

U6400

(See speaker amp card)
I2C_SPKRAMP_L_SCL

I2C_SPKRAMP_L_SDA

50

50

ISP (SoC)

(MASTER)

I2C_FTCAM_SCL

33 33

MAKE_BASE=TRUE

I2C_FTCAM_SDA

33

MAKE_BASE=TRUE

R5335

1/20W

5%
MF

201

1

2

1

R5336

1K

5%
1/20W
MF
201

2

FaceTime Camera

(See camera card)

I2C_FTCAM_SCL
I2C_FTCAM_SDA

69

69

TP_I2C_CODEC_SCL

33

TP_I2C_CODEC_SDA

33

AP I2C "2" Codec Connections

U3900

(MASTER)

TP_I2C_CODEC_SCL

MAKE_BASE=TRUE

TP_I2C_CODEC_SDA

MAKE_BASE=TRUE

UNUSEDAP (SoC)

D

AP I2C "4" DFR Connections

C

78 33

78 33

33

33

AP (SoC)

U3900

I2C_SPKRAMP_R_SCL

MAKE_BASE=TRUE

I2C_SPKRAMP_R_SDA

MAKE_BASE=TRUE

AP I2C "3" G3S Connections

PP1V8_G3S

75

AP (SoC)

U3900

(MASTER)

I2C_ALS_SCL

MAKE_BASE=TRUE

I2C_ALS_SDA

MAKE_BASE=TRUE

5%
MF

201

1K

5%
MF

201

1

2

1

2

R5305

2.2K 2.2K

1/20W

R5315

1/20W

1

2

1

2

R5306

5%
1/20W
MF
201

R5316

1K

5%
1/20W
MF
201

RIO Audio

Speaker Amp, Codec

(See RIO)(MASTER)

I2C_SPKRAMP_R_SCL
I2C_SPKRAMP_R_SDA

ALS

J8500

(See camera flex)

I2C_ALS_SCL
I2C_ALS_SDA

49

49

69

69

AP (SoC)

U3900

(MASTER)

NC_I2C_DFR_SCL

33

NC_I2C_DFR_SDA

33

AP I2C "5" Awake Connections

AP (SoC)

U3900

(MASTER)

NC_I2C_SOC_5_SCL

33

NC_I2C_SOC_5_SDA

33

UNUSED

NC_I2C_DFR_SCL

MAKE_BASE=TRUE

NO_TEST=1

NC_I2C_DFR_SDA

MAKE_BASE=TRUE

NO_TEST=1

UNUSED

NC_I2C_SOC_5_SCL

MAKE_BASE=TRUE

NC_I2C_SOC_5_SDA

MAKE_BASE=TRUE

NO_TEST=1

NO_TEST=1

C

B

ISP I2C "1" G3S Connections

ISP (SoC)

U3900

(MASTER)

NC_I2C_PLCAM_SCL

33

NC_I2C_PLCAM_SDA

33

NC_I2C_PLCAM_SCL

MAKE_BASE=TRUE

NC_I2C_PLCAM_SDA

MAKE_BASE=TRUE

AOP I2C G3H Connections

UNUSED

B

NO_TEST=1

NO_TEST=1

A

AOP (SoC)

U3900

(MASTER)

NC_I2C_AOP_SCL

32

NC_I2C_AOP_SDA

32

BOM_COST_GROUP=SOC

NC_I2C_AOP_SCL

MAKE_BASE=TRUE

NC_I2C_AOP_SDA

MAKE_BASE=TRUE

SYNC_MASTER=X589_BIGSUR

PAGE TITLE

I2C Connections 2

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

UNUSED

NO_TEST=1

NO_TEST=1

DRAWING NUMBER

051-05232

REVISION

BRANCH

PAGE

SHEET

SYNC_DATE=02/13/2017

2.0.0

proto4b

53 OF 152

43 OF 86

A

SIZE

D

8

67

35 4

2

1

678

www.laptoprepairsecrets.com

3 245

1

D

A

CPU High Side Current Sense (IC0R)

GAIN: 100X, EDP: 10.16 A
Rsense: 0.003 (R5400)
VSENSE: 30.475 mV, RANGE: 8.842 A
SMC ADC: 04

75

PPBUS_HS_CPU

CRITICAL

1%
1W

CYN

0612

1

432

R5400

0.003

NO_XNET_CONNECTION=1

75

$J230GHUB/j230/mlb/sim/ltspice/ic0r_smc_cpu_hs_isense.asc

PPBUS_G3H

PP3V3_G3SSW_SNS

44 45 46 75

ISNS_HS_COMPUTING_N

PLACE_NEAR=U5400.4:10MM

ISNS_HS_COMPUTING_P

PLACE_NEAR=U5400.5:10MM

3
V+

U5400

5

4

INA214-S

IN-

SC70

100X

IN+ REF

CRITICAL

GND

2

OUT

LTSpice Simulation

LTSpice Simulation

PBUS Voltage Sense & Enable (VP0R)

E

Gain: 0.089x
Vnominal: 13.05 V, Range: 14.05 V
SMC ADC: 02

BYPASS=U5400.3:2:5MM

1

C5401

0.1UF

10%
10V

2

X5R-CERM
0201

PLACE_NEAR=U3900.AB6:5.2MM

75

IN

R5409

6

1

ISNS_HS_COMPUTING_IOUT

PLACE_NEAR=U5400.6:5MM

1

R5405

15K

2

5%
1/20W
MF
201

PLACE_NEAR=U3900.AB6:5.2MM

10.2K

1%

1/20W

MF

201

21

SMC_CPU_HS_ISENSE

R5408

7.68K

1%

1/20W

MF

201

1

2

1

2

GND_SMC_AVSS

40

OUT

PLACE_NEAR=U3900.AB6:6.2MM

C5409

0.022UF

10%

6.3V
X5R-CERM
0201

PPBUS_G3H

75

46 45 44 39 32

PP3V3_G3SSW_SNS

Enables PBUS VSense
divider when sensor
rail is enabled.

XW5480

SM

21

PBUS_S0_VSENSE_IN

R5481

100K

1%

1/20W

MF

201

1

2

2

1

5

4

Q5480

NTUD3169CZ

SOT-963

N-CHANNEL

D

G

S

D

G

S

P-CHANNEL

CRITICAL

PBUSVSENS_EN_L_DIV

6

PBUSVSENS_EN_L

3

PBUS_S0_VSENSE

R5482

100K

1%

1/20W

MF

201

1

2

PLACE_NEAR=U3900.AH3:5MM

1%
MF

201

1

Rthevenin = 4573 Ohms

2

R5488

51.1K

1/20W

SMC_PBUS_VSENSE

PLACE_NEAR=U3900.AH3:5MM

1%
MF

201

1

2

1

C5489

0.022UF

10%

6.3V

2

X5R-CERM
0201

R5489

4.99K

1/20W

GND_SMC_AVSS

OUT

40

46 45 44 39 32

D

C

B

5V G3S High Side Current Sense (IO5R)

GAIN: 100X, EDP: 4.2 A
Rsense: 0.005 (R5410)

PP3V3_G3SSW_SNS

VSENSE: 21 mV, RANGE: 5 A
SMC ADC: 06

60 75

PPVIN_G3H_P5VG3S

CRITICAL

NO_XNET_CONNECTION=1

75

PPBUS_G3H

R5410

0.005

1%
1W
MF

0612-8

PLACE_NEAR=U5410.5:10MM

2

ISNS_5VG3S_N

ISNS_5VG3S_P

341

PLACE_NEAR=U5410.4:10MM

44 45 46 75

3
V+

U5410

5

INA214-S

IN-

SC70

100X

4

IN+ REF

CRITICAL

GND

2

OUT

6

1

BYPASS=U5410.3:2:5MM

1

C5411

0.1UF

10%
10V

2

X5R-CERM
0201

PLACE_NEAR=U3900.AG4:5.2MM

R5419

ISNS_5VG3S_IOUT SMC_5VG3S_ISENSE

PLACE_NEAR=U5410.6:5MM

1

R5415

15K

2

5%
1/20W
MF
201

PLACE_NEAR=U3900.AG4:5.2MM

9.09K

1%

1/20W

MF

201

21

R5418

9.09K

1/20W

1%
MF

201

$J230GHUB/j230/mlb/sim/ltspice/vp0r_smc_pbus_vsense.asc

LTSpice Simulation

F

40

OUT

PLACE_NEAR=U3900.AG4:6.2MM

1

2

1

C5419

0.022UF

10%

6.3V

2

X5R-CERM
0201

GND_SMC_AVSS

46 45 44 39 32

DC In Voltage Sense (VD0R)

Gain: 0.148x
Vnominal: 16.5 V, Range: 22.29 V
SMC ADC: 00

PPDCIN_G3H

75

PLACE_NEAR=U3900.AG2:5MM

PLACE_NEAR=U3900.AG2:5MM

R5498

78.7K

1%

1/20W

MF

201

R5499

4.87K

1%

1/20W

MF

201

1

Rthevenin = 4586 Ohms

2

SMC_DCIN_VSENSE

1

2

PLACE_NEAR=U3900.AG2:5MM

1

C5499

0.022UF

10%

6.3V

2

X5R-CERM
0201

GND_SMC_AVSS

PLACE_NEAR=U3900.AH3:5MM

40

OUT

46 45 44 39 32

C

B

$J230GHUB/j230/mlb/sim/ltspice/io5r_smc_5vg3s_isense.asc

C

3V3 G3H MAIN High Side Current Sense (IO3R)

GAIN: 100X, EDP: 4.702 A
Rsense: 0.005 (R5420)
VSENSE: 23.510 mV, RANGE: 5 A
SMC ADC: 05

60 75

PPVIN_G3H_P3V3G3H

CRITICAL

1%
1W
MF

1

75

R5420

0.005

NO_XNET_CONNECTION=1

0612-8

PPBUS_G3H

44 45 46 75

PLACE_NEAR=U5420.5:10MM

ISNS_3V3G3HMAIN_P

432

PLACE_NEAR=U5420.4:10MM

PP3V3_G3SSW_SNS

5

IN-

4

IN+ REF

3
V+

U5420

INA214-S

SC70

100X

CRITICAL

GND

2

OUT

G

LTSpice Simulation

BYPASS=U5420.3:2:5MM

1

C5421

0.1UF

10%
10V

2

X5R-CERM
0201

6

1

ISNS_3V3G3HMAIN_IOUTISNS_3V3G3HMAIN_N

PLACE_NEAR=U5420.6:5MM

1

R5425

15K

5%
1/20W
MF
201

2

PLACE_NEAR=U3900.AH2:5.2MM

PLACE_NEAR=U3900.AH2:5.2MM

R5429

9.09K

1/20W

1%
MF

201

21

SMC_3V3G3HMAIN_ISENSE

1%
MF

201

1

2

R5428

9.09K

1/20W

OUT

PLACE_NEAR=U3900.AH2:6.2MM

1

C5429

0.022UF

10%

6.3V

2

X5R-CERM
0201

GND_SMC_AVSS

40

46 45 44 39 32

DC-IN (AMON) Current Sense (ID0R)

Charger Gain: 20x, EDP: 3.0 A
RSENSE: 0.010 (R7020)
SMC ADC: 01

56

IN

CHGR_AMON

R5472

4.53K

1%

1/20W

MF

201

PLACE_NEAR=U3900.AC4:5MM

21

SMC_DCIN_ISENSE

PLACE_NEAR=U3900.AC4:5MM

1

C5473

0.022UF

10%

6.3V

2

X5R-CERM
0201

GND_SMC_AVSS

OUT

40

46 45 44 39 32

B

A

$J230GHUB/j230/mlb/sim/ltspice/io3r_smc_3v3g3hmain_isense.asc

D

Sensor Documentation

Sensor information can be found in the

ERS at the link below or by scanning the

QR Code image.

https://github.pie.apple.com/MobileMacIX/j230_hw/blob/master/j230/mlb/docs/sensor_ers/j230_sensor_ers.pdf

INA21X PARTS HAVE MINOR LEAKAGE PATH FROM INPUTS TO OUTPUT WHEN UNPOWERED.
PULL-DOWN RESISTERS ON INA OUTPUTS BLEED OFF THE LEAKAGE CURRENT TO PREVENT
SIGNAL PUMP-UP.

I

H

Charger (BMON) Current Sense (IPBR)

Charger Gain: 7.9x, EDP: 6.5 A
RSENSE: 0.005 (R7060)
SMC ADC: 03

78 56

IN

CHGR_BMON

R5470

4.53K

1%

1/20W

MF

201

Speaker Amp Sense (Ixxx)

RSENSE: 0.005
EDP: x A
SMC ADC: 03

50 75

75

PPBUS_G3H_SPKRL

NO_XNET_CONNECTION=1

PPBUS_G3H

CRITICAL

R5430

0.005

0612-8

1%
1W
MF

1

ISNS_SPKRL_N

ISNS_SPKRL_P

432

BOM_COST_GROUP=SENSORS

21

TP5431

1

TP-P5

TP5430

1

TP-P5

A

A

PLACE_NEAR=U3900.AD4:5MM

SMC_BMON_ISENSE

PLACE_NEAR=U3900.AD4:5MM

1

C5471

0.022UF

10%

6.3V

2

X5R-CERM
0201

GND_SMC_AVSS

DESIGN: J230/MLB
LAST CHANGE: Fri Sep 28 20:05:04 2018

SYNC_MASTER=psm

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

OUT

40

46 45 44 39 32

Power Sensors High Side

Apple Inc.

DRAWING NUMBER

051-05232

REVISION

2.0.0

BRANCH

proto4b

PAGE

54 OF 152

SHEET

44 OF 86

SYNC_DATE=10/18/2018

SIZE

D

A

8

67

35 4

2

1

678

www.laptoprepairsecrets.com

LTSpice Simulation

3 245

1

D

A

VDDMAIN 3.3V Current Sense (ISLC)

GAIN: 200X, EDP: 10.90 A
Rsense: 0.001 (R5500)
VSENSE: 10.90 mV, RANGE: 10.988 A
PMU AMUX: A0

62 75

PP3V3_G3H_PMU_VDDMAIN

CRITICAL

NO_XNET_CONNECTION=1

75

PP3V3_G3H

R5500

0.001

1%

1W
MF-3
0612

PLACE_NEAR=U5500.5:10MM

432

ISNS_VDDMAIN_N

ISNS_VDDMAIN_P

PLACE_NEAR=U5500.4:10MM

1

PP3V3_G3SSW_SNS

44 45 46 75

3
V+

U5500

5

4

INA210A

IN-

SC70

200X

IN+ REF

CRITICAL

GND

2

OUT

BYPASS=U5500.3:2:5MM

1

C5501

0.1UF

10%
10V

2

X5R-CERM
0201

6

1

ISNS_VDDMAIN_IOUT

PLACE_NEAR=U5500.6:5MM

1

R5505

15K

5%
1/20W
MF
201

2

PLACE_NEAR=U7800.A16:5.2MM

PLACE_NEAR=U7800.A16:5.2MM

R5509

6.65K

1%

1/20W

MF

201

21

PMU_VDDMAIN_ISENSE

PLACE_NEAR=U7800.A16:5.2MM

R5508

14.3K

1%

1/20W

MF

201

1

2

1

C5509

2.2UF

20%

6.3V

2

X5R-CERM
0201

GND_SMC_AVSS

OUT

45

B

46 45 44 39 32

PMU ADC AMUX_A ALIASES

45

45

IN

IN

PMU_VDDMAIN_ISENSE

MAKE_BASE=TRUE

PMU_MEM1V1_ISENSE

46

MAKE_BASE=TRUE

PMU_WLANBT_ISENSE

MAKE_BASE=TRUE

PMU_MEM0V6_ISENSE

45

MAKE_BASE=TRUE

PMU_LCDBKLT_ISENSE

46

MAKE_BASE=TRUE

PMU_CPU_VSENSE

46

MAKE_BASE=TRUE

PMU_NAND_VSENSE

46

MAKE_BASE=TRUE

PMU_VCCINAUX_VSENSE

46

MAKE_BASE=TRUE

PMU_VDDMAIN_ISENSE
PMU_MEM1V1_ISENSE
PMU_WLANBT_ISENSE
PMU_MEM0V6_ISENSE
PMU_LCDBKLT_ISENSE
PMU_CPU_VSENSE
PMU_NAND_VSENSE
PMU_VCCINAUX_VSENSE

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

64

64

64

64

64

64

64

64

D

C

$J230GHUB/j230/mlb/sim/ltspice/islc_pmu_vddmain_isense.asc

C

Wireless 3.3V Current Sense (IAPC)

GAIN: 200X, EDP: 1.5 A
Rsense: 0.010 (R5510)
VSENSE: 15 mV, RANGE: 1.5 A
PMU AMUX: A2

NO_XNET_CONNECTION=1

XW5510

29 75

75

PP3V3_G3S_WLANBT

NO_XNET_CONNECTION=1

PP3V3_G3S

CRITICAL

R5510

0.01

1%

1/3

MF

0402

1

NO_XNET_CONNECTION=1

XW5511

2

SM

SM

LTSpice Simulation

D

PP3V3_G3SSW_SNS

44 45 46 75

3
V+

21

U5510

ISNS_WLANBT_N

5

INA210A

IN-

SC70

OUT

200X

ISNS_WLANBT_P

21

4

IN+ REF

CRITICAL

GND

2

6

1

BYPASS=U5510.3:2:5MM

1

C5511

0.1UF

10%
10V

2

X5R-CERM
0201

ISNS_WLANBT_IOUT

PLACE_NEAR=U5510.6:5MM

1

R5515

15K

5%
1/20W
MF
201

2

PLACE_NEAR=U7800.A14:5.2MM

PLACE_NEAR=U7800.A14:5.2MM

R5519

10.2K

1%

1/20W

MF

201

21

PMU_WLANBT_ISENSE

R5518

9.09K

1%

1/20W

MF

201

1

2

1

2

GND_SMC_AVSS

45

OUT

PLACE_NEAR=U7800.A14:5.2MM

C5519

2.2UF

20%

6.3V
X5R-CERM
0201

46 45 44 39 32

PMU ADC AMUX_B ALIASES

NC_PMU_AMUX_B0

MAKE_BASE=TRUE

PMU_VCCINAUX_ISENSE

45

MAKE_BASE=TRUE

NC_PMU_AMUX_B2

MAKE_BASE=TRUE

NC_PMU_AMUX_B3

MAKE_BASE=TRUE

NC_PMU_AMUX_B4

MAKE_BASE=TRUE

NC_PMU_AMUX_B5

MAKE_BASE=TRUE

NC_PMU_AMUX_B6

MAKE_BASE=TRUE

NC_PMU_AMUX_B7

MAKE_BASE=TRUE

NC_PMU_AMUX_B0
PMU_VCCINAUX_ISENSE
NC_PMU_AMUX_B2
NC_PMU_AMUX_B3
NC_PMU_AMUX_B4
NC_PMU_AMUX_B5
NC_PMU_AMUX_B6
NC_PMU_AMUX_B7

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

64

64

64

64

64

64

64

64

C

B

$J230GHUB/j230/mlb/sim/ltspice/iapc_pmu_wlanbt_isense.asc

E

MEMORY 0.6V High-Side Current Sense (IM0C)

GAIN: 200X, EDP: 1.5 A
Rsense: 0.020 (R5520)
VSENSE: 15 mV, RANGE: 1.5 A
PMU AMUX: A3

65 75

75

PP1SR3V3_G3H_P0V6_S3_VIN

NO_XNET_CONNECTION=1

PP3V3_G3H

CRITICAL

R5520

0.02

1%

1/3

MF

0402

1

2

NO_XNET_CONNECTION=1

XW5520

SM

21

NO_XNET_CONNECTION=1

XW5521

SM

21

PP3V3_G3SSW_SNS

44 45 46 75

ISNS_MEM0V6_N

ISNS_MEM0V6_P

3
V+

U5520

5

IN-

4

IN+ REF

INA211

SC70

500X

CRITICAL

GND

2

OUT

LTSpice Simulation

F

Sensor Documentation

Sensor information can be found in the ERS by

BYPASS=U5510.3:2:5MM

1

C5521

0.1UF

10%
10V

2

X5R-CERM
0201

R5529

6

1

1

R5525

15K

5%
1/20W
MF
201

2

6.04K

1%

1/20W

MF

201

21

PMU_MEM0V6_ISENSEISNS_MEM0V6_IOUT

R5528

18.7K

1/20W

1%
MF

201

45

OUT

1

2

1

C5529

2.2UF

20%

6.3V

2

X5R-CERM
0201

GND_SMC_AVSS

46 45 44 39 32

scanning the QR Code image.

B

A

$J230GHUB/j230/mlb/sim/ltspice/im0c_pmu_mem0v6_isense.asc

G

VCCIN_AUX Current Sense (ICIC)

NO_XNET_CONNECTION=1

PLACE_NEAR=R7430.4:2MM

R5530

VCCINAUX_ISNS_N

59

10

1/20W

201

R5531

VCCINAUX_ISNS_P

59

PLACE_NEAR=R7430.3:2MM

NO_XNET_CONNECTION=1

10

1/20W

201

1%
MF

1%
MF

LTSpice Simulation

PP3V3_G3SSW_SNS

44 45 46 75

3
V+

21

U5530

5

IN-

INA211

SC70

OUT

500X

ISNS_VCCINAUX_P

21

4

IN+ REF

CRITICAL

GND

2

6

1

BYPASS=U5530.3:2:5MM

1

C5531

0.1UF

10%
10V

2

X5R-CERM
0201

ISNS_VCCINAUX_IOUTISNS_VCCINAUX_N

PLACE_NEAR=U5530.6:5MM

1

R5535

15K

5%
1/20W
MF
201

2

PLACE_NEAR=U7800.E13:5.2MMM

R5539

10K

1/20W

PLACE_NEAR=U7800.E13:5.2MMM

1%
MF

201

21

PMU_VCCINAUX_ISENSE

PLACE_NEAR=U7800.E13:5.2MMM

R5538

8.25K

1%

1/20W

MF

201

1

2

1

C5539

2.2UF

20%

6.3V

2

X5R-CERM
0201

GND_SMC_AVSS

OUT

45

DESIGN: J230/MLB
LAST CHANGE: Fri Sep 28 20:05:04 2018

SYNC_MASTER=X1032_MLB_P4BP

PAGE TITLE

SYNC_DATE=02/14/2017

A

Power Sensors Load Side

DRAWING NUMBER

051-05232

46 45 44 39 32

Apple Inc.

REVISION

SIZE

D

2.0.0

BRANCH

proto4b

PAGE

55 OF 152

SHEET

45 OF 86

BOM_COST_GROUP=SENSORS

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

8

67

35 4

2

1

678

www.laptoprepairsecrets.com

LTSpice Simulation

3 245

1

D

A

SSD High Side (IH0R)

GAIN: 500X, EDP: 0.654 A
Rsense: 0.010 (R5600)
VSENSE: 6.536 mV, RANGE: 1.8 A
SMC ADC: 07

72 75

75

PPBUS_G3H_SSD0

NO_XNET_CONNECTION=1

PPBUS_G3H

CRITICAL

R5600

0.01

0.5%

0.5W
0306

MA

PLACE_NEAR=U5400.5:10MM

2

ISNS_SSD0_N

ISNS_SSD0_P

341

PLACE_NEAR=U5400.4:10MM

PP3V3_G3SSW_SNS

44 45 46 75

3

V+

U5600

5

IN-

4

IN+ REF

INA211

SC70

500X

CRITICAL

GND

2

OUT

B PCH VNN BYPASS CURRENT SENSE

GAIN: 200X, EDP: 0.2 A

NO_XNET_CONNECTION=1

XW5631

2

21

MF

1%

1/3

0.02

0402

2

XW5630

NO_XNET_CONNECTION=1

SM

ISNS_P1V05_PCH_VNN_EXT_N

1

ISNS_P1V05_PCH_VNN_EXT_P

1

PP5630

1

TP-P5

PP5631

1

TP-P5

A

A

D

BYPASS=U5600.3:2:5MM

1

C5601

0.1UF

10%
10V

2

X5R-CERM
0201

PLACE_NEAR=U3900.AC5:5.2MM

PPVNN_PCH_EXT

9 81

PPVNN_PCH_EXT

MAKE_BASE=TRUE

R5609

6

1

ISNS_SSD0_IOUT

PLACE_NEAR=U5600.6:5MM

1

R5605

15K

5%
1/20W
MF
201

2

PLACE_NEAR=U3900.AC5:5.2MM

12.1K

1%

1/20W

MF

201

21

SMC_SSD0_ISENSE

1%
MF

201

1

2

R5608

7.32K

1/20W

PLACE_NEAR=U3900.AC5:6.2MM

1

C5609

0.022UF

10%

6.3V

2

X5R-CERM
0201

GND_SMC_AVSS

OUT

40

R5630

74

46 45 44 39 32

PPVNN_PCH_EXT_REG

C5631

1.0UF

20%

6.3V
X5R

0201-1

1

2

C

$J230GHUB/j230/mlb/sim/ltspice/ih0r_smc_ssd0_isense.asc

C

Memory 1.1V High Side Current Sense (IM1C)

GAIN: x, EDP: 2.3 A
Rsense: 0.010 (R5610)
VSENSE: 23 mV, RANGE: 2.344 A
PMU AMUX: Ax

65 75

PPVIN_G3H_P1V1_S3

CRITICAL

R5610

0.01

0.5%
1W
MF

75

NO_XNET_CONNECTION=1

0612-1-COMBO

PPBUS_HS_CPU

ISNS_MEM1V1_N

4

ISNS_MEM1V1_P

3

1 2

PP3V3_G3SSW_SNS

44 45 46 75

3

V+

U5610

5

IN-

4

IN+ REF

INA211

SC70

500X

CRITICAL

GND

2

OUT

D

LTSpice Simulation

BYPASS=U5600.3:2:5MM

1

C5611

0.1UF

10%
10V

2

X5R-CERM
0201

R5619

6

1

ISNS_MEM1V1_IOUT

1

R5615

15K

5%
1/20W
MF
201

2

12.1K

1%

1/20W

MF

201

21

PMU_MEM1V1_ISENSE

1%
MF

201

1

2

R5618

7.32K

1/20W

1

C5619

0.022UF

10%

6.3V

2

X5R-CERM
0201

GND_SMC_AVSS

OUT

45

46 45 44 39 32

9 81

74

PCH 1.05V BYPASS CURRENT SENSE

GAIN: 200X, EDP: 0.2 A

NO_XNET_CONNECTION=1

PP1V05_PCH_EXT

PP1V05_PCH_EXT

PP1V05_PCH_EXT_REG

C5641

MAKE_BASE=TRUE

1.0UF

20%

6.3V
X5R

0201-1

R5640

1

2

XW5641

2

SM SM

21

1%

MF

1/3

0.02

0402

2

SM

XW5640

NO_XNET_CONNECTION=1

ISNS_P1V05_PCH_EXT_N

1

ISNS_P1V05_PCH_EXT_P

1

PP5640

1

TP-P5

PP5641

1

TP-P5

A

A

C

B

$J230GHUB/j230/mlb/sim/ltspice/im1c_pmu_mem1v1_isense.asc

LTSpice Simulation

E Sensor Docs

68

68

LCD Backlight (IBLR)

GAIN: 100X, EDP: 0.902 A
Rsense: 0.025 (R8400)
VSENSE: 22.549 mV, RANGE: 0.902 A
PMU AMUX: A4

PP3V3_G3SSW_SNS

IN

IN

44 45 46 75

ISNS_LCDBKLT_N

ISNS_LCDBKLT_P

3

V+

U5620

5

4

INA214-S

IN-

SC70

100X

IN+ REF

CRITICAL

GND

2

OUT

6

1

BYPASS=U5620.3:2:5MM

1

C5621

0.1UF

10%
10V

2

X5R-CERM
0201

ISNS_LCDBKLT_IOUT

PLACE_NEAR=U5620.6:5MM

1

R5625

15K

5%
1/20W
MF
201

2

PLACE_NEAR=U7800.C14:5.2MM

PLACE_NEAR=U7800.C14:5.2MM

R5629

7.15K

1%

1/20W

MF

201

21

PMU_LCDBKLT_ISENSE

PLACE_NEAR=U7800.C14:5.2MM

R5628

12.7K

1%

1/20W

MF

201

1

2

1

C5629

2.2UF

20%

6.3V

2

X5R-CERM
0201

GND_SMC_AVSS

45

F

46 45 44 39 32

CPU VCCIN VOLTAGE SENSE (VCAC)

PMU AMUX: A5

PPVCC_S0_CPU

8 11 75

XW5680

SM

21

PLACE_NEAR=R7210.1:7 MM

CPUVSENSE_IN

PLACE_NEAR=U7800.D15:5MM
PLACE_NEAR=U7800.D15:5MM

R5680

5.76K

1%

1/20W

MF

201

21

1

R5681

22.1K

1%
1/20W
MF
201

2

PMU_CPU_VSENSE

PLACE_NEAR=U7800.D15:5MM

1

C5680

2.2UF

20%

6.3V

2

X5R-CERM
0201

45

GND_SMC_AVSS

46 45 44 39 32

G

Scan the QR Code

for sensor info.

B

A

$J230GHUB/j230/mlb/sim/ltspice/iblr_pmu_lcdbklt_isense.asc

H I

NAND 2V5 VOLTAGE SENSE (VHNC)

PMU AMUX: A6

PPVCC_NAND_SSD0

75

XW5660

SM

21

NANDVSENSE_IN

PLACE_NEAR=R7210.1:7 MM

PLACE_NEAR=U7800.E14:5MM
PLACE_NEAR=U7800.E14:5MM

R5660

8.25K

1%

1/20W

MF

201

21

1

R5661

10.2K

1%
1/20W
MF
201

2

PMU_NAND_VSENSE

PLACE_NEAR=U7800.E14:5MM

1

C5660

2.2UF

20%

6.3V

2

X5R-CERM
0201

GND_SMC_AVSS

45

46 45 44 39 32

VCCIN_AUX VOLTAGE SENSE (VCIC)

PMU AMUX: A7

PPVCCIN_AUX_PCH

75

XW5670

SM

21

PLACE_NEAR=R7210.1:7 MM

VCCINAUXVSENSE_IN

PLACE_NEAR=U7800.F14:5MM

R5670

4.53K

1%

1/20W

MF

201

21

PMU_VCCINAUX_VSENSE

PLACE_NEAR=U7800.F14:5MM

1

C5670

2.2UF

20%

6.3V

2

X5R-CERM
0201

GND_SMC_AVSS

45

DESIGN: J230/MLB

LAST CHANGE: Fri Sep 28 20:05:04 2018

A

PAGE TITLE

46 45 44 39 32

Power Sensors Extended

DRAWING NUMBER

051-05232

Apple Inc.

REVISION

SIZE

D

2.0.0

BRANCH

proto4b

PAGE

56 OF 152

SHEET

46 OF 86

BOM_COST_GROUP=SENSORS

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

8

67

35 4

2

1

678

www.laptoprepairsecrets.com

3 245

1

D

(TC0P)

CPU SENSOR

Location:

Top, Opposite CPU

(TM0P)

DRAM SENSOR

Location:

Bottom, Opposite U2300

Q5810

SNST3904MX

X2DFN3

CRITICAL

Q5820

SNST3904MX

X2DFN3

CRITICAL

THMSNS_CPU_D1_P

3

1

2

NO_XNET_CONNECTION=1

C5810

100PF

5%
25V
C0G

0201

PLACE_NEAR=U5800.A1:5MM

1

2

PLACE_NEAR=U5800.A3:5MM

THMSNS_CPU_D1_N

NO_XNET_CONNECTION=1

THMSNS_DRAM_D2_P

3

1

2

NO_XNET_CONNECTION=1

C5820

100PF

5%
25V
C0G

0201

PLACE_NEAR=U5800.B1:5MM

1

2

PLACE_NEAR=U5800.A3:5MM

THMSNS_DRAM_D2_N

NO_XNET_CONNECTION=1

47

XW5810

SM

21

47

XW5820

SM

21

PLACE_NEAR=U5800.A3:5MM

D

PLACE_NEAR=U5800.A3:5MM

C

(TSMP)

SoC SENSOR

Location:

Top, Opposite SOC

(TCaP)

PMIC SENSOR

Location:

Top, Opposite PMIC

(TH0a)

NAND SENSOR

Location:

Top, Opposite U8700

Q5830

SNST3904MX

X2DFN3

CRITICAL

Q5840

SNST3904MX

X2DFN3

CRITICAL

Q5850

SNST3904MX

X2DFN3

CRITICAL

THMSNS_SOC_D3_P

3

1

2

NO_XNET_CONNECTION=1 PLACE_NEAR=U5800.C1:5MM

5%
25V
C0G

0201

1

2

PLACE_NEAR=U5800.A3:5MM

C5830

100PF

THMSNS_SOC_D3_N

NO_XNET_CONNECTION=1

THMSNS_PMIC_D4_P

3

1

2

NO_XNET_CONNECTION=1

C5840

100PF

5%
25V
C0G

0201

PLACE_NEAR=U5800.D1:5MM

1

2

PLACE_NEAR=U5800.A3:5MM

THMSNS_PMIC_D4_N

NO_XNET_CONNECTION=1

THMSNS_NAND_D5_P

3

1

2

NO_XNET_CONNECTION=1

C5850

100PF

5%
25V
C0G

0201

PLACE_NEAR=U5800.A2:5MM

1

2

PLACE_NEAR=U5800.A3:5MM

THMSNS_NAND_D5_N

NO_XNET_CONNECTION=1

47

XW5830

SM

21

47

XW5840

SM

21

47

XW5850

SM

21

PLACE_NEAR=U5800.A3:5MM

PLACE_NEAR=U5800.A3:5MM

PLACE_NEAR=U5800.A3:5MM

PP1V8_G3S

75

THMSNS_CPU_D1_P

47

THMSNS_DRAM_D2_P

47

THMSNS_SOC_D3_P

47

THMSNS_PMIC_D4_P

47

THMSNS_NAND_D5_P

47

THMSNS_CHGR_D6_P

47

THMSNS_WLAN_D7_P

47

47 21

TBT_X_THERM_D_P
THMSNS_DN

R5810

100K

1%

1/20W

MF

201

THMSNS_ADDR

1

2

R5800

0

5%

1/20W

MF

0201

21

PP1V8_G3S_THMSNS_R

MIN_LINE_WIDTH=0.2500
MIN_NECK_WIDTH=0.1500

VOLTAGE=1.8V

D3

V+

1

C5800

0.1UF

10%
16V

2

X7R-CERM
0402

C

U5800

TMP468

A1
B1
C1
D1
A2
B2
C2
D2

A3

B4

D1+
D2+
D3+
D4+
D5+
D6+
D7+
D8+

D-

ADD

DSBGA

CRITICAL

GND

A4

SCL

SDA

THERM2*

THERM*

D4

C4

C3

B3

NC
NC

I2C_SNS_G3S_SCL
I2C_SNS_G3S_SDA

IN

BI

42

42

B

(TCHP)

Charger SENSOR

Location:

Bottom, Between Q7030 and Q7040

(TW0P)

Wireless SENSOR

Location:

Top, Near wireless module

Q5860

SNST3904MX

X2DFN3

CRITICAL

Q5870

SNST3904MX

X2DFN3

CRITICAL

THMSNS_CHGR_D6_P

3

1

2

C5860

100PF

5%
25V
C0G

0201

PLACE_NEAR=U5800.B2:5MMNO_XNET_CONNECTION=1

1

2

PLACE_NEAR=U5800.A3:5MM

THMSNS_CHGR_D6_N

NO_XNET_CONNECTION=1

THMSNS_WLAN_D7_P

3

1

2

C5870

100PF

5%
25V
C0G

0201

PLACE_NEAR=U5800.C2:5MMNO_XNET_CONNECTION=1

1

2

PLACE_NEAR=U5800.A3:5MM

THMSNS_WLAN_D7_N

NO_XNET_CONNECTION=1

47

XW5860

SM

21

47

XW5870

SM

21

PLACE_NEAR=U5800.A3:5MM

PLACE_NEAR=U5800.A3:5MM

U5800 I2C Address:

Write: 0x90
Read: 0x91

(Tm0P)

Ambient SENSOR

INTERNAL (U5800)

B

TBT_X_THERM_D_P

PLACE_NEAR=U5800.D2:5MM

1

2

PLACE_NEAR=U5800.A3:5MM

TBT_X_THERM_D_N

XW5880

SM

NO_XNET_CONNECTION=1

PLACE_NEAR=U5800.A3:5MM

21

A

8

(TUDD)

TBT SENSOR

INTERNAL (U2800)

47 21

21

IN

IN

NO_XNET_CONNECTION=1

C5880

100PF

5%
25V
C0G

0201

67

DESIGN: J230/MLB
LAST CHANGE: Fri Sep 28 20:05:04 2018

SYNC_MASTER=X1032_MLB_P4BP

PAGE TITLE

SYNC_DATE=02/14/2017

A

Thermal Sensors

DRAWING NUMBER

051-05232

Apple Inc.

REVISION

2.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=SENSORS

35 4

IV ALL RIGHTS RESERVED

2

BRANCH

proto4b

PAGE

58 OF 152

SHEET

47 OF 86

1

SIZE

D

678

www.laptoprepairsecrets.com

3 245

1

D

A

48 75

78 48

78 48

PP5V_G3S
FAN_LT_PWM

FAN_LT_TACH
TP_FAN_OTP1
TP_FAN_OTP2

518S0818

J6000

FF14A-6C-R11DL-B-3H

F-RT-SM

7

1
2
3
4
5
6

8

D FAN SupportFAN Connector

PP1V8_G3S

75

47K

5%
MF

201

1

D

2

78 48

48 32

OUT

SMC_FAN_0_TACH

NOSTUFF

R6001

100K

1/20W

5%
MF

201

R6000

1/20W

R6005

47K

1/20W

1

1

GS

2

21

FAN_LT_TACH

5%
MF

201

Q6000

DMN32D2LFB4

DFN1006H4-3

SYM_VER_3

C

B

FAN Bypass Capacitors

PP5V_G3S

48 75

10%
16V

0402

1

2

C6070

0.1UF

X7R-CERM CERM

1

C6071

12PF

5%
25V

2

0201

1

C6072

3PF

+/-0.1PF
25V

2

C0G
0201

32

IN

SMC_FAN_0_PWM

R6002

100K

5%

1/20W

MF

201

D

2

1

2

FAN_LT_PWM

3

78 48

C

B

C

CRITICAL

DZ6005

ESD8472MUT5G

21

X3DFN2-1

CRITICAL

DZ6007

ESD8472MUT5G

21

X3DFN2-1

FAN_LT_PWM

FAN_LT_TACH

EFAN Protection Diodes

<rdar://problem/47292431> J230 MLB route Fan TACH signals to ACE

78 48

48 32

FAN Debug

R6060

0

21

1/20W

BOMOPTION=FANTACH:DEBUG

PLACE_NEAR=U3900.L3:10MM

SMC_FAN_0_TACH_RSMC_FAN_0_TACH

MF 02015%

R6061

0

21

5%

BOMOPTION=FANTACH:DEBUG

PLACE_NEAR=U3200.G12:4MM

SPARE_UPC_T_DBG0_R

02011/20W MF

OUT

25 23

B

78 48

SMC_FAN_0_TACH Placement Topology

UPC_T_DBG0

Front
U3200
T

2

R6061

1

SMC_FAN_0_TACH_R

2

R6060

1

SOC

U3900

SMC_FAN_0_TACH

Fan
Conn
J6000

A

8

67

SYNC_MASTER=X1032_MLB_P4BP

PAGE TITLE

SYNC_DATE=02/13/2017

A

Fans

DRAWING NUMBER

051-05232

Apple Inc.

REVISION

2.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=FAN

35 4

IV ALL RIGHTS RESERVED

2

BRANCH

proto4b

PAGE

60 OF 152

SHEET

48 OF 86

1

SIZE

D

D

www.laptoprepairsecrets.com

A

RIO Flex Connector

J6100

502250-8045

F-RT-SM

48
46

1
3
5

49

50 52 75

78 52 49 31

78 52 33

43

78 40

78 40

78 33

78 49

78 40

78 40

78 40

78 40

78 50 49 31

49 75

49 75

49 75

PP3V3_G3S_G3H_RIO
PP1V8_G3S
CODEC_INT_L
SPKR_ID1
I2C_SPKRAMP_R_SCL
I2S_CODEC_BCLK
I2S_CODEC_R2D
SPI_MESA_MISO
PMU_ONOFF_R_L_CONN
SPI_MESA_CLK
SMC_LID_RIGHT
I2S_SPKRAMP_R_BCLK
I2S_SPKRAMP_R_LRCLK_R
SPKRAMP_RESET_L
PPBUS_G3H
PPBUS_G3H
PPBUS_G3H

7

9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44

PP1V8_SLPS2R
PP3V3_G3S_G3H_RIO
CODEC_RESET_L
CODEC_WAKE_L
I2C_SPKRAMP_R_SDA
I2S_CODEC_D2R
AUD_PWR_EN
I2S_CODEC_LRCLK
MESA_INT
SPI_MESA_MOSI
MESA_PWR_EN
I2S_SPKRAMP_L_D2R
I2S_SPKRAMP_R_R2D
SPKRAMP_INT_L

NC

PPBUS_G3H
PPBUS_G3H

678

3 245

1

On RIO Board:

AMR

D

PMU_ONOFF_L Level Shifter

CODEC
MESA
SPKR AMP

PP3V3_G3H_RTC

75

10%

10V

0201

1

2

2

D

U6150

74AUP1T97

5

SOT891

1

2

4

6

3

3 4

PMU_ONOFF_BUF_L

R6151

0

5%

1/20W

MF

0201

21

PMU_ONOFF_L

Vmax

3.3V

U6150 Output Range

PMU_ONOFF_BUF_L

0V

OUTIN

Tamb = 25 C
I_O = 2.7 mA

78 64 55 78 49

3

VOH = +2.72V

VOL = +0.31V

40 74

49

78 32

43

78 33

78 64

78 33

78 40

78 40

49 75

49 75

C6150

0.1UF

PP1V8_SLPS2R

74

1

R6152

100K

5%
1/20W
MF
201

78 52 49 32

PMU_ONOFF_R_L_CONN PMU_ONOFF_R_L

1/20W

R6150

0

2

21

MF5% 0201

81

X5R-CERM

1

78 49 31

Vmax

78 40 31

78 50 33

78 50 49 31

1.8V

MESA/RIO Output Range

J6100.23

PMU_ONOFF_R_L_CONN

0V

1

VOH = +1.35V

VOL = +0.45V

C

B

47
49

RIO P3V3_G3H Connection

R6101

0

PP3V3_G3H

75

5% 0201MF1/20W

21

PP3V3_G3S_G3H_RIO

VOLTAGE=3.3V

49

518S00155
Mates with 998-11285

on X1032 RIO Flex J0200

Vmax

3.3V

0V

U6150 Input Range
PMU_ONOFF_R_L

Tamb = 25 C
VT+ Max = VIH Min
VT- Min = VIL Max

VIH = +1.16V

VIL = +0.5V

2

LTSpice Simulation

$J230GHUB/j230/mlb/sim/ltspice/pmu_onoff_level_shifter.asc

Vmax

5V

0V

Calpe Input Range

U7800.N7

PMU_ONOFF_L

I_I = 1 uA

VIH = +2.64V

VIL = +0.35V

4

C

B

C RIO Control Signals

1

C6100

100PF

5%
25V

2

C0G
0201

1

C6101

100PF

5%
25V

2

C0G
0201

1

C6102

100PF

5%
25V

2

C0G
0201

1

C6103

100PF

5%
25V

2

C0G
0201

1

C6104

100PF

5%
25V

2

C0G
0201

MESA_INT
CODEC_INT_L
CODEC_WAKE_L
SPKRAMP_INT_L
SPKRAMP_RESET_L

B

78 49 31

78 52 49 31

78 52 49 32

78 50 49 31

78 50 49 31

A

8

67

A

PAGE TITLE

RIO Connector

DRAWING NUMBER

051-05232

Apple Inc.

REVISION

2.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=AUDIO

35 4

IV ALL RIGHTS RESERVED

2

BRANCH

proto4b

PAGE

61 OF 152

SHEET

49 OF 86

1

SIZE

D

1X MONO SPEAKER AMPLIFIER

www.laptoprepairsecrets.com

APN: 353S01629
GAIN: 0DBFS = 6.31 VRMS

678

3 245

1

D

C

LEFT AMPLIFIER

78 49 31

40

78 49 33

40

40

PP1V8_G3S

49 52 75

SPKRAMP_INT_L

OUT

I2S_SPKRAMP_L_R2D

IN

I2S_SPKRAMP_L_D2R

OUT

I2S_SPKRAMP_L_LRCLK_R

IN

IN

I2S_SPKRAMP_L_BCLK

NOSTUFF

1

R6400

47K

5%
1/20W
MF
201

2

R6401

1/20W5%

SHORT-8L-0.25MM-SM

XW6410

78 50 49 31

33

21

I2S_SPKRAMP_L_D2R_R

201MF

43

43

IN

BI

IN

PLACE_NEAR=U6400.C1:5 MM

VOLTAGE=1.8V

21

PP1V8_S0_SPKRAMP_AVDD

CRITICAL

1

C6400

1UF

10%

10V

2

X5R
402-1

SPKRAMP_RESET_L

I2C_SPKRAMP_L_SDA
I2C_SPKRAMP_L_SCL

SPKRAMP_L_MODE

50

PLACE_NEAR=U6400.D2:5 MM

CRITICAL

1

C6402

1UF

10%

10V

2

X5R
402-1

PLACE_NEAR=U6400.D2:3 MM

CRITICAL

1

C6403

0.1UF

10%

25V

2

X5R
0201

PLACE_NEAR=U6400.C1:3 MM

CRITICAL

1

C6401

0.1UF

10%

25V

2

X5R
0201

C3

SDZ*

F3

SDA

F4

SCL

D4

IRQZ

MODE

F2

SDIN

E1

SDOUT

E2

FSYNC

F1

SBCLK

E4

PDMD0

E3

PDMCK0

E5

PDMD1

F5

PDMCK1

C1

AVDD IOVDD

D2

U6400

TAS5770LC0YFF

DSBGA

GND

C2

PGND

A4

B4

C5

C4

VBAT

VSNS_P

VSNS_N

BST_P
OUT_P
OUT_P

BST_N
OUT_N
OUT_N

AREG

DREG

PLACE_NEAR=U6400.C4:3 MM

CRITICAL

1

C6404

0.1UF

10%

25V

2

X5R
0201

B2

SPKRAMP_L_BSTP

A3

SPKRAMP_L_OUTP

DIDT=TRUE

B3
A1

SPKRAMP_L_SNSP

A2

SPKRAMP_L_BSTN

A5D3

DIDT=TRUE

B5

SPKRAMP_L_OUTN

B1

SPKRAMP_L_SNSN

D5

D1

SPKRAMP_L_AREG

SPKRAMP_L_DREG

PLACE_NEAR=U6400.D1:3 MM

CRITICAL

1

C6407

0.1UF

10%

25V

2

X5R
0201

PLACE_NEAR=U6400.C4:10 MM

CRITICAL

1

C6405

10UF

20%

25V

2

X5R-CERM
0603

PLACE_NEAR=U6400.C4:10 MM

CRITICAL

1

C6406

10UF

20%

25V

2

X5R-CERM
0603

C6411

0.1UF

10%

25V

X5R

0201

C6412

0.1UF

10%

25V

X5R

0201

PLACE_NEAR=U6400.D1:5 MM

CRITICAL

1

C6408

1UF

10%

10V

2

X5R
402-1

PLACE_NEAR=U6400.D5:3 MM

CRITICAL

1

C6409

0.1UF

10%

25V

2

X5R
0201

PLACE_NEAR=U6400.C4:10 MM

CRITICAL

1

C6415

10UF

20%

25V

2

X5R-CERM
0603

CRITICAL

BYPASS=U6400.B2:B3:5 MM

NO_XNET_CONNECTION=1

21

L6400

180OHM-3.4A

CRITICAL

BYPASS=U6400.A2:A5:5 MM

NO_XNET_CONNECTION=1

21

L6401

180OHM-3.4A

PLACE_NEAR=U6400.D5:5 MM

CRITICAL

1

C6410

1UF

10%

10V

2

X5R
402-1

PLACE_NEAR=U6400.C4:10 MM

CRITICAL

1

C6416

10UF

20%

25V

2

X5R-CERM
0603

CRITICAL

PLACE_NEAR=U6400.A3:10 MM

NO_XNET_CONNECTION=1

21

0806

21

SHORT-8L-0.25MM-SM

XW6400

PLACE_NEAR=J6620.1:3 MM

CRITICAL

PLACE_NEAR=U6400.A5:10 MM

NO_XNET_CONNECTION=1

21

0806

SHORT-8L-0.25MM-SM

PLACE_NEAR=J6620.4:3 MM

XW6401

21

NOSTUFF

CRITICAL

C6413

220PF

10%

25V

X7R-CERM

201

D

PPBUS_G3H_SPKRL

SPKRCONN_L_OUTP

OUT

44 50 75

78 52

C

SPKRCONN_L_OUTN

NOSTUFF

OUT

CRITICAL

1

2

1

C6414

220PF

10%

25V

2

X7R-CERM
201

78 52

B

A

LEFT BULK CAPACITANCE

CRITICAL

1

C6481

68UF

20%
16V

2

POLY-TANT
CASE-D2E-SM

CAPMAT=POLY-TANT

CRITICAL

1

C6482

68UF

20%
16V

2

POLY-TANT
CASE-D2E-SM

CRITICAL

1

C6483

68UF

20%
16V

2

POLY-TANT
CASE-D2E-SM

PPBUS_G3H_SPKRL

44 50 75

78 50 49 31

50

SPKRAMP_RESET_L

SPKRAMP_L_MODE

R6402

100K

5%

1/20W

MF

201

R6480

0

5%

1/20W

MF

0201

B

21

DESIGN: J230/MLB

MODE PIN

GND

21

470 to GND
470 to IOVDD
2k2 to GND
2k2 to IOVDD
10k to GND
10k to IOVDD 0x37
47k to IOVDD

I2C ADDR

0x31
0x32
0x33
0x34
0x35
0x36

0x38

CHANNEL

LEFT

RIGHT

BOM_COST_GROUP=AUDIO

LAST CHANGE: Fri Sep 28 20:05:04 2018

SYNC_MASTER=AHAAGE_AUD

PAGE TITLE

Audio Speaker Amplifiers

DRAWING NUMBER

051-05232

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

REVISION

BRANCH

proto4b

PAGE

64 OF 152

SHEET

50 OF 86

2.0.0

SYNC_DATE=05/23/2017

SIZE

D

A

8

67

35 4

2

1

A

www.laptoprepairsecrets.com

678

Keyboard Backlight LED Driver

3 245

PART# DESCRIPTIONQTY

114S0023 2

RES,MTL FLM,1/16W,10 OHM,1,0402,SMD,LF

R6544, R6545

1

TABLE_5_HEAD

BOM OPTIONREFERENCE DESIGNATOR(S)

TABLE_5_ITEM

D

C

PP5V_G3S

51 75

R6545

R6544

GND_KBD_BKLT_SGND

51

21

0

OMIT_TABLE

21

5%1/16W 402

OMIT_TABLE

PLACE_NEAR=U6500.5:5MM

MF-LF

4025% MF-LF1/16W

0

C6540

GND_KBD_BKLT_SGND

51

1

R6540

1M 100K

5%
1/20W
MF
201

2

1

R6542

5%
1/20W
MF
201

2

4.7UF

20%

25V

X5R

0402

PP5V_S0_KBD_BKLT_A

MIN_LINE_WIDTH=2.0000
MIN_NECK_WIDTH=0.2000

VOLTAGE=5V

PP5V_S0_KBD_BKLT_D

MIN_LINE_WIDTH=2.0000
MIN_NECK_WIDTH=0.2000

VOLTAGE=5V

PLACE_NEAR=U6500.18:5MM

1

2

1

C6541

4.7UF

20%

25V

2

X5R
0402

KBD_BKLT_SENSE_OUT
UNUSED_BKLT_EN

KBD_BKLT_PWM

51

NC
NC
NC

NC
NC

5

VDDD

U6500

LP8548B1SQ_-04

11

SD

9

VSENSE_N

10

VSENSE_P

19

SENSE_OUT

17
12

15
16

EN
PWM_KEYB

SCL

(IPU)

SDA

(IPU)

CRITICAL

GND_SW

24

ISET_KEYB

353S4160

GND_SW

GND_SW2

3

7

23

18

VDDA

LLP

GNDA

GNDD

22

SW
SW
FB
GD

KEYB1
KEYB2

SW2
FB2

THRM

PAD

25

2
1
21
4

20

KBDBKLT_ISET

13

KBDBKLT_KEYB1

14

KBDBKLT_KEYB2

6

PP5V_S0_KBDBKLT_SW2

8

KBDBKLT_FB2

NC
NC
NC
NC

51

51

1

R6541

31.6K

1%
1/20W
MF
201

2

R6520
R6521

D

21

10

2011% 1/20W MF

21

10

2011/20W1% MF

KBDLED_CATHODE1

KBDLED_CATHODE2

OUT

OUT

53

53

C

B

B

51 75

XW6500

SM

21

GND_KBD_BKLT_SGND

51

MIN_LINE_WIDTH=0.4000
MIN_NECK_WIDTH=0.1000

VOLTAGE=0V

Keyboard Boost Converter Support Keyboard PWM Level Shifter

KBDBKLT_FB2

51

PP5V_S0_KBDBKLT_SW2

51

2

PP5V_G3S

1

C6510

12PF

2%

100V

2

CERM
0402

1

C6520

2.2UF

10%

25V

2

X5R-CERM
603

1

C6521

2.2UF

10%

25V

2

X5R-CERM
603

152S1701

L6520

10UH-20%-1.4A-0.17OHM

21

PST041H-SM

1

C6522

0.1UF

10%

2

X5R-CERM
0201

XW6520

PLACE_NEAR=D6520::2MM

371S00079

D6520

SOD123W

PMEG6010ER/S500

SM

1

R6553 is a placeholder for desense
to add a ferrite bead if needed.

R6553

KA

VOLTAGE=40V

1

2

C6523

2.2UF

10%

50V16V

X5R
0603

1

C6524

2.2UF

10%

50V

2

X5R
0603

1

C6525

2.2UF

10%

50V

2

X5R
0603

PPVOUT_S0_KBDBKLT_R

1

C6526

2.2UF

10%

50V

2

X5R
0603

1

C6530

2.2UF

10%

50V

2

X5R
0603

1

C6531

2.2UF

10%

50V

2

X5R
0603

0

21

PPVOUT_S0_KBDBKLT

MF-LF

4025%1/16W

VOLTAGE=40VVOLTAGE=40V

53

C

31

PP3V3_G3S

75

GND_KBD_BKLT_SGND

51

R6557

0

SOC_KBD_BKLT_PWM SOC_KBD_BKLT_PWM_R

IN

5%1/20W MF 0201

21

1

R6551

100K

1/20W

C6550

0.1UF

10%

10V

X5R-CERM

0201

1

5%
MF

201

2

1

2

2

U6550

74AUP1T97

5

SOT891

1

2

4

6

3

3

SMC_KBD_BKLT_PWM

1

R6552

100K

5%
1/20W
MF
201

2

GND_KBD_BKLT_SGND

51

R6547

0

5%

1/20W

MF

0201

B

21

1

2

KBD_BKLT_PWM

NO STUFF

C6547

33PF

5%

25V

NP0-C0G
0201

51

4

A

D

Keyboard Probe Points

PP6500

P3MM

SM

PP6501

P3MM

SM

PP6502

P3MM

SM

PP6503

P3MM

SM

PP

PP

PP

PP

1

1

1

1

PP5V_S0_KBDBKLT_SW2

KBDBKLT_FB2

KBD_BKLT_PWM

GND_KBD_BKLT_SGND

51

51

51

51

1

C6527

0.001UF

10%

50V

2

X7R-CERM
0402

1

C6528

12PF

2%

100V

2

CERM
0402

1

C6529

12PF

2%

100V

2

CERM
0402

1

C6532

2.2UF

10%

50V

2

X5R
0603

1

C6533

2.2UF

10%

50V

2

X5R
0603

Vmax

1.8V

0V

Vmax

3.3V

0V

H9M PWM Output Range

U3900.L33

SOC_KBD_BKLT_PWM

VOH = +1.44V

VOL = +0.36V

U6550 Input Range
SOC_KBD_BKLT_PWM

Tamb = 25 C
VT+ Max = VIH Min
VT- Min = VIL Max

VIH = +1.16V

VIL = +0.5V

1

2

Vmax

3.3V

0V

Vmax

5V

0V

U6550 Output Range

SMC_KBD_BKLT_PWM

Tamb = 25 C
I_O = 2.7 mA

VOH = +2.72V

VOL = +0.31V

LP8548 Input Range

U6500.12

KBD_BKLT_PWM

I_I = 1 uA

VIH = +1.7V

VIL = +0.4V

BOM_COST_GROUP=DISPLAY

LTSpice Simulation

3

$J230GHUB/j230/mlb/sim/ltspice/keyboard_pwm_level_shifter.asc

4

SYNC_MASTER=X1032_MLB_P4BP SYNC_DATE=04/15/2019

PAGE TITLE

Keyboard Backlight

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

051-05232

REVISION

2.0.0

BRANCH

proto4b

PAGE

65 OF 152

SHEET

51 OF 86

A

SIZE

D

8

67

35 4

2

1

678

www.laptoprepairsecrets.com

3 245

1

D

A

DMIC Secure Disable

PP1V8_G3S

52 53 75

40

IN

SEP_DMIC_DISABLE_OUT_L

78 53

IN

PDM_DMIC_DATA0_ISOL

BYPASS=U8515::2MM

C6615

0.1UF

10%

6.3V

CERM-X5R

0201

CRITICAL

U6615

74AUP1G08GF

6

SOT891

VCC

2

A Y

AND

1

B

5

NC

1

2

NC

GND

3

4

R6615

33

5%

1/20W

MF

201

21

PDM_DMIC_DATA0PDM_DMIC_DATA0_R

OUT

32

D

C

78 53

PP1V8_G3S

52 53 75

IN

PDM_DMIC_DATA1_ISOL

BYPASS=U8518::2MM

C6618

0.1UF

10%

6.3V

CERM-X5R

0201

CRITICAL

U6618

74AUP1G08GF

6

SOT891

VCC

2

A Y

AND

1

B

5

NC

1

2

NC

GND

3

4

PDM_DMIC_DATA1_R

R6618

33

5%

1/20W

MF

201

21

PDM_DMIC_DATA1

OUT

32

C

B

Left Speaker ConnectorB

APN: 518S0521

PP1V8_G3S

49 50 52 75

NOSTUFF

J6620

78171-0004

M-RT-SM

5

1
2
3
4

6

B

78 33

OUT

SPKR_ID0

R6620

47K

5%

1/20W

MF

201

1

2

78 50

78 50

IN

IN

SPKRCONN_L_OUTP

SPKRCONN_L_OUTN

1

C6620

3PF

+/-0.1PF +/-0.1PF
25V

2

C0G
0201

1

C6621

3PF

25V

2

C0G
0201

A

C D Audio Codec Pull-Ups

Right Speaker ID

PP1V8_G3S

49 50 52 75

NOSTUFF

47K

5%
MF

201

1

2

78 49 33

OUT

R6630

1/20W

SPKR_ID1

PP1V8_G3S

1

R6640

5%
1/20W
MF
201

2

1

R6641

47K47K

5%
1/20W
MF
201

2

CODEC_WAKE_L
CODEC_INT_L

49 50 52 75

IN
IN

78 49 32

78 49 31

DESIGN: J230/MLB
LAST CHANGE: Fri Sep 28 20:05:04 2018

PAGE TITLE

A

SYNC_DATE=04/19/2017SYNC_MASTER=AHAAGE_AUD

E

Speaker Amp Control

R6650

0

8

5%

1/20W

MF

0201

21

I2S_SPKRAMP_R_D2R

33

67

Audio Connectors

DRAWING NUMBER

051-05232

Apple Inc.

REVISION

2.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT

BOM_COST_GROUP=AUDIO

35 4

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

2

BRANCH

proto4b

PAGE

66 OF 152

SHEET

52 OF 86

1

SIZE

D

678

www.laptoprepairsecrets.com

3 245

1

D

C

IPD B2B CONNECTOR

Bottom side contacts used
Pinout reversed from flex

PPBUS_G3H

75

78 53

53 51

78 53

78 54

78 54

78 54 78 54

78 54

78 54 40

78 53

PP3V3_G3H_IPD_F
KBDLED_CATHODE1

51

PPVOUT_S0_KBDBKLT
KBDLED_CATHODE2

51

PP3V3_G3S_IPD_F
I2C_TPAD_3V3_SCL

SPI_TPAD_3V3_MISO
SPI_TPAD_3V3_CS_L SPI_TPAD_3V3_MOSI

TPAD_SPI_3V3_EN
TPAD_KBD_WAKE_L

PP5V_G3S_IPD_F

CRITICAL

L6700

30-OHM-5A

0603

C6700

21

0.1UF

10%
25V
X5R

0201

1

2

NC

NC
NC

PPBUS_G3H_TPAD_FLT

MIN_LINE_WIDTH=0.6000
MIN_NECK_WIDTH=0.1000

VOLTAGE=13.1V

516S0784

CRITICAL

J6700

AA03-S042VA1

F-ST-SM

4443

21
43
65
87
109
1211
1413
1615
1817
2019
2221
2423
2625
2827
3029
3231
3433
3635
3837
4039
4241

4645

78

PMU_RSLOC_RST_L

PPVOUT_S0_KBDBKLT

PP3V3_G3S_IPD_F
I2C_TPAD_3V3_SDA
SPI_TPAD_3V3_CLK

TPAD_SPI_3V3_INT_L

NC

IPD_LID_OPEN

IPD Power Filters

IPD DesenseCBA

CRITICAL

L6701

FERR-120-OHM-1.5A

78 53

PP3V3_G3H_IPD_F

MIN_LINE_WIDTH=0.5000
MIN_NECK_WIDTH=0.2000

VOLTAGE=3.3V

C6701

0.1UF

X5R-CERM

10%
10V

0201

2 1

0402-LF

1

2

PP3V3_G3H

53 75

CRITICAL

81 78 64 55 53

53 51

78 53

78 54

78 54

78 54

78 53

PP3V3_G3S_IPD_F

MIN_LINE_WIDTH=0.5000
MIN_NECK_WIDTH=0.2000

VOLTAGE=3.3V

C6702

0.1UF

X5R-CERM

0201

FERR-120-OHM-1.5A

1

10%
10V

2

L6702

2 1

0402-LF

CRITICAL

L6703

PP3V3_G3S

53 75

D

FERR-120-OHM-1.5A

78 53

78 53 40

PP5V_G3S_IPD_F

MIN_LINE_WIDTH=0.0750
MIN_NECK_WIDTH=0.0750

VOLTAGE=5V

C6703

0.1UF

10%
10V

X5R-CERM

0201

2 1

0402-LF

1

2

PP5V_G3S

75

PP3V3_G3S

53 75

PP3V3_G3H

53 75

C6775

12PF

5%

25V
CERM
0201 0201

IPD Control

PMU_RSLOC_RST_L

IPD_LID_OPEN

BYPASS=J6700.2::1.5MM

1

C6710

100PF

5%
25V

2

C0G
0201

BYPASS=J6700.30::1.5MM

1

C6712

100PF

5%
25V

2

C0G
0201

D

1

2

1

C6776

3PF

+/-0.1PF 5%
25V

2

C0G

C6777

81 78 64 55 53

78 53 40

1

1

12PF

25V

2

CERM
0201 0201

2

C6778

3PF

+/-0.1PF
25V
C0G

C

B

E Microphone Connector

J6750

78 40

78 52

78 40

78 52

IN
BI

52 75

40 74

78 40

IN
BI

FF18-8A-R11AD-B-3H

PDM_DMIC_CLK1
PDM_DMIC_DATA1_ISOL
PP1V8_G3S
PP1V8_SLPS2R
SMC_LID_LEFT

PDM_DMIC_CLK0
PDM_DMIC_DATA0_ISOL

F-RT-SM1
1
2
3
4
5
6
7
8

518S00170

F

IPD Connector Bosses

SH6700

BOSS-3.05OD1.15ID-1.11H-SM

1

SH6701

BOSS-3.05OD1.15ID-1.11H-SM

1

B

A

8

67

SYNC_MASTER=X260_MLB

PAGE TITLE

SYNC_DATE=02/16/2017

A

Keyboard & Trackpad 1

DRAWING NUMBER

051-05232

Apple Inc.

REVISION

2.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT

BOM_COST_GROUP=TRACKPAD

35 4

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

2

BRANCH

proto4b

PAGE

67 OF 152

SHEET

53 OF 86

1

SIZE

D

678

www.laptoprepairsecrets.com

3 245

1

D

A

Trackpad SPI Bus Level Shifter (+1.8V to +3.3V)

PP1V8_AWAKE

74

33

40 39

40 39

39 33

IN

IN

IN

OUT

SPI_TPAD_MISO

5%
MF

201

1

2

R6803

100K

1/20W

R6804

20

21

5%1/20W 201

PLACE_NEAR=U6860.5:2MM

MF

BYPASS=U6860::5MM

C6860

0.1UF

X5R-CERM

SPI_TPAD_CS_L

SPI_TPAD_MOSI

SPI_TPAD_MISO_R

10%
10V

0201

1

14

2

13

VCCBVCCA

U6860

SN74AVC4T774-COMBO

15

16

1

A1
DIR1

2

A2
DIR2

3

A3

5

DIR3

4

A4

6

DIR4

7

OE*

QFN

GND

8

B1

B2

B3

B4

12

11

10

9

BYPASS=U6860::5MM

1

C6861

0.1UF

10%
10V

2

X5R-CERM
0201

SPI_TPAD_3V3_CS_L

SPI_TPAD_3V3_CLK_R

SPI_TPAD_3V3_MOSI_R SPI_TPAD_3V3_MOSI

SPI_TPAD_3V3_MISO

R6874

100K

1/20W

NOSTUFF

R6870

100K

1/20W

201

201

5%
MF

5%
MF

PP3V3_G3S

NOSTUFF

1

R6871

100K

1/20W

2

IN

1

2

R6880

1

5%
MF

201 201

2

R6872

100K

1/20W

5%
MF

201

1

R6873

100K

1/20W

2

R6875

PLACE_NEAR=U6860.9:2MM

R6876

PLACE_NEAR=U6860.8:2MM

78 53

1

100K

5%

1/20W

MF

201

2

1

5%
MF

2

20

5% MF 2011/20W

20

5%1/20W 201MF

21

21

SPI_TPAD_3V3_CLKSPI_TPAD_CLK

54 75

OUT

OUT

OUT

D

78 53

78 53

78 53

C

J230k = 0x3F PROJECT
B RESISTOR
BOARDID[5] = SPI_TPAD_CLK 1 pull-down

BOARDID[4] = SPI_TPAD_MISO* 1 pull-up
BOARDID[3] = SPI_TPAD_MOSI 1 pull-up
BOARDID[2] = SPI_SOCROM_MISO 1
BOARDID[1] = SPI_SOCROM_MOSI 1
BOARDID[0] = SPI_SOCROM_CLK 1

SPI_TPAD_CLK, SPI_TPAD_MOSI, and SPI_TPAD_CLK are shared signals with BOARDID on CSA 47.
Ensure signals that drive from +3.3V to +1.8V (i.e., towards Gibraltar) are properly strapped based on the desired BOARDID.

SN74AVC4T774 Truth Table

CTRL INPUTS

OUTPUT CIRCUITS

OPERATION

/OE
L
L
H Isolation

DIR
L
H
X

A PORT
Enabled
Hi-Z
Hi-Z

B PORT
Hi-Z
Enabled
Hi-Z

B data to A data
A data to B data

C

B

B

Trackpad I2C Bus Level Shifter

PP1V8_G3S

54 75

1

R6813

4.7K

5%
1/20W
MF
201

2

42

42

IN

BI

I2C_SNS_G3S_SCL

I2C_SNS_G3S_SDA

R6879

30

21

5%1/20W

PLACE_NEAR=Q6861.4:2MM

I2C_TPAD_SDA_R

MF

CKPLUS_WAIVE=I2C_PULLUP

201

5%
MF

201

1

2

R6812

4.7K

VER-2

SG

12

VER-2

DMN33D9LV

SG

45

Q6861

SOT563

DMN33D9LV

D

I2C_TPAD_3V3_SCL_R

6

Q6861

SOT563

D

I2C_TPAD_3V3_SDA_R

3

1/20W

PP3V3_G3S

R6877

30

21

5% MF 2011/20W

PLACE_NEAR=Q6861.6:2MM

I2C_TPAD_3V3_SCL

R6878

30

21

5%1/20W 201

PLACE_NEAR=Q6861.3:2MM

I2C_TPAD_3V3_SDA

MF

54 75

CKPLUS_WAIVE=I2C_PULLUP

CKPLUS_WAIVE=I2C_PULLUP

OUT

BI

C

78 53

78 53

Trackpad Control Level Shifter

PP1V8_G3S

54 75

DMN33D9LV

10K

5%
MF

201

1

2

SG

45

NC

SG

12

R6863

1/20W

40 78 53

OUT IN

TPAD_SPI_INT_L

Q6862

SOT563

VER-2

D
3

DMN33D9LV

Q6862

SOT563

VER-2

D
6

TPAD_SPI_3V3_INT_L

NCNC

PP3V3_G3S

54 75

78 53 40

OUT

PP1V8_G3S

54 75

TPAD_KBD_WAKE_L

1

R6864

100K

5%
1/20W
MF
201

2

R6865

10K

5%

1/20W

MF

201

B

1

2

A

D

Trackpad SPI Enable Level Shifter

PP1V8_G3S

54 75

BYPASS=U6855::5MM

10%
10V

0201

1

2

NC

VCC_A

U6855

SN74AUP1T34-COMBO

A

5

NC

1

SON

GND

3

6

VCC_B

42

B

C6855

0.1UF

X5R-CERM

31

TPAD_SPI_EN

IN OUT

5%
MF

201

1

2

R6852

100K

1/20W

BYPASS=U6855::5MM

1

C6856

0.1UF

10%
10V

2

X5R-CERM
0201

1

2

PP3V3_G3S

NOSTUFF

1

R6854

100K

5%
1/20W
MF
201

2

R6853

100K

5%
1/20W
MF
201

TPAD_SPI_3V3_EN

54 75

SYNC_MASTER=X589_CARD_IPD SYNC_DATE=02/16/2017

PAGE TITLE

78 53

Keyboard & Trackpad 2

DRAWING NUMBER

SIZE

051-05232

Apple Inc.

REVISION

A

D

2.0.0

BRANCH

proto4b

PAGE

68 OF 152

SHEET

54 OF 86

BOM_COST_GROUP=TRACKPAD

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

8

67

35 4

2

1

678

www.laptoprepairsecrets.com

3 245

1

D

DC-In & Battery ConnectorA

518-00030

Mates with x

CRITICAL

J6950

RCPT-BMU

F-RT-TH-1

10
8

1
2
3
4
5
6
7

9
11

1

C6950

0.1UF

10%
25V

2

X7R-CERM-1
0402

1

C6951

1.0UF

10%

25V

2

X6S
0402

R6951

4.7K

1/20W

1

3

RCLAMP2402B

5%
MF

201

2

1

2

D6950

SC-75

PP3V3_G3H

1

R6952

4.7K

5%
1/20W
MF
201

2

PPVBAT_G3H_CONN
SMBUS_3V3_BATT_SCL

78

SMBUS_3V3_BATT_SDA

78

SYS_DETECT_L

SYSDET:AON

1

2

R6950

10K

5%
1/20W
MF
201

3

D

S G

2

75

78 56

78

SYSDET:FET

Q6955

DMN32D2LFB4

DFN1006H4-3

SYM_VER_2

1

SYS_DETECT

78

Q6950

SOT563

DMN33D9LV

Q6950

SOT563

DMN33D9LV

SW6955

SOX-152HNT

SM

B

PP1V8_SLPS2R

VER-2

D
6

VER-2

D
3

S G

1 2

S G

4 5

I2C_PWR_SCL

I2C_PWR_SDA

PP3V3_G3H_RTC

75

SYSDET:FET

1

R6955

10K

5%
1/20W
MF
201

2

1

R6959

1M

5%
1/20W
MF
201

2

Copied from J212:
DIM LED always lit
when AON is energeized

IN

BI

42 74

42

42

Charger Reset Circuit

PP3V3_G3H_RTC

75

1

VDD

U6940

STQFN

CRITICAL

GND

7

RESET

NC
NC
NC
NC
NC
NC
NC

10

2
5
6
8
9
11
12

CHGR_RST_IN_R

NC
NC
NC
NC
NC
NC
NC

78 64 49

81 78 64 53

IN
IN

BYPASS=U6940::3MM

C6940

0.1UF

0201

PMU_ONOFF_L
PMU_RSLOC_RST_L

10%

25V

X5R

1

2

SLG4AP41183

3

BTN1

4

BTN2

R6941

1K

5%

1/20W

MF

201

R6940

1K

5%

1/20W

MF

201

21

UPC_PMU_RESET

21

CHGR_RST_IN

OUT

OUT

D

64 23

56

SYS_DETECT_LED

A

D6959

WHITE-140MCD-0.005A-2.7V

0402

21

K

C

B

C

3.3V G3H RTC Voltage Regulator

R6961

0

PPBUS_G3H

75

1/4W 0603MF0%

21

PPVIN_G3H_P3V3G3HRTC

56

IN

CRITICAL

1

C6960

68UF

20%
16V

2

POLY-TANT
CASE-D2E-SM

CHGR_EN_MVR

CRITICAL

1

C6961

2.2UF

20%
25V

2

X6S-CERM

CRITICAL

1

C6962

2.2UF

20%
25V

2

X6S-CERM
04020402

R6960

0

5%

1/20W

MF

0201

21

SYSDET:FET

2

R6965

10

5%
1/20W
MF
201

1

P3V3RTC_AVIN

CHGR_EN_MVR_R

CRITICAL

1

C6965

0.1UF

10%
25V

2

X6S-CERM
0201

10

AVIN

8

DEF

13

EN

7

FSW

XW6960

SM

21

12

11

PVIN

PVIN

U6960

TPS62130B-S

VQFN

CRITICAL

353S00897

PAD

THRM

PGND

16

AGND

6

17

PGND

15

SW
SW
SW

VOS

FB

PG

SS/TR

1
2
3

14

5

4

9

P3V3RTC_PHASE

DIDT=TRUE

P3V3RTC_VOS
P3V3RTC_FB
P3V3RTC_PGOOD
P3V3RTC_SS

10%
10V

0201

1

2

C6968

0.01UF

X7R-CERM

PP3V3_G3H_RTC_R

1

R6967

100K

5%
1/20W
MF
201

2

2.2UH-20%-3.4A-0.066OHM

152S00477

CRITICAL

P3V3RTC_FB_TOP

1

C6969

27PF

5%

25V

2

C0G
0201

55

L6960

1210

21

XW6970

SM

R6970

10

5%

1/20W

MF

201

R6971

2.8K

1%

1/20W

MF

201

<Ra>

R6973

82.5K

0.1%

1/20W

MF

0201-1

2

1

1

CRITICAL

1

C6970

10UF

20%

6.3V

2

CER-X6S
0402

Vout = 0.8 * (1 + <Ra>/<Rb>) = 3.299V

2

1

2

P3V3RTC_FB_R

1

CRITICAL

2

CRITICAL

1

C6971

10UF

20%

6.3V

2

CER-X6S
0402

CRITICAL

1

C6972

150UF

20%

6.3V

2

TANT
CASE-B-SM

CAPMAT=POLY-TANT

PP3V3_G3H_RTC_R

55

VOLTAGE=3.3V

NOSTUFF

CRITICAL

1

C6973

100UF

20%

6.3V

2

POLY-TANT
CASE-A3

Vout = 3.3V
Iout Max = 2.08A
f = 1.25 MHZ

R6979

0

21

0%1/4W MF 0603

PP3V3_G3H_RTC

C

75

B

A

GND_P3V3RTC_AGND

VOLTAGE=0V

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000

R6972

27.4K

<Rb>

0.1%

1/20W

0201

MF

1

CRITICAL

2

BOM_COST_GROUP=PLATFORM POWER

PAGE TITLE

DC-In & Battery Connectors

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=10/18/2018SYNC_MASTER=psm

DRAWING NUMBER

051-05232

REVISION

2.0.0

BRANCH

proto4b

PAGE

69 OF 152

SHEET

55 OF 86

A

SIZE

D

8

67

35 4

2

1

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3 245

1

D

79 78

PPDCIN_G3H_CHGR_AMON

MIN_LINE_WIDTH=0.6000

MIN_NECK_WIDTH=0.1800

VOLTAGE=20V

FROM USB-C SOURCE

PPDCIN_G3H

75

CRITICAL

1

C7025

6.8UF

20%
35V-0.09OHM

2

POLY-TANT
CASE-B1-2-SM

CRITICAL

1

C7026

6.8UF

20%
35V-0.09OHM

2

POLY-TANT
CASE-B1-2-SM

CRITICAL

1

C7024

6.8UF

20%
35V-0.09OHM

2

POLY-TANT
CASE-B1-2-SM

CRITICAL

1

C7027

6.8UF

20%
35V-0.09OHM

2

POLY-TANT
CASE-B1-2-SM

PLACE_NEAR=C7036.1:3MM

CRITICAL

1

C7034

2.2UF

20%

35V

2

X5R-CERM
0402

CRITICAL

1

C7035

2.2UF

20%

35V

2

X5R-CERM
0402

(AMON)

CRITICAL

R7020

0.01

0.5%
1W
MF

0612-1-COMBO

PLACE_NEAR=Q7030.2:2MM

CRITICAL

1

C7036

2.2UF

20%

35V

2

X5R-CERM
0402

21
43

CRITICAL

1

C7037

2.2UF

20%

35V

2

X5R-CERM
0402

TO SYSTEM

PPBUS_G3H

152S00730

CRITICAL

CRITICAL

1

C7050

33UF

20%
16V

2

TANT
CASED12-SM

CAPMAT=POLY-TANT

CRITICAL

1

C7053

2.2UF

20%

25V

2

X5R-CERM
0402-1

CRITICAL

1

C7054

2.2UF

20%

25V

2

X5R-CERM
0402-1

1

C7055

1000PF

10%
25V

2

X7R
0201

L7030

2.7UH-20%-8.7A-0.025OHM

CHGR_PHASE1

DIDT=TRUE
SWITCH_NODE=TRUE

7

6

10

4

3

2

5

PIMA062D

79

21

CHGR_PHASE2

DIDT=TRUE
SWITCH_NODE=TRUE

7

6

CRITICAL

1

C7056

33UF

20%
16V

2

TANT
CASED12-SM

5

1043

2

CAPMAT=POLY-TANT

56 75

D

C

R7021

1.00

CRITICAL

C7021

0.047UF

10%

CER-X7R

0402

1%
1/20W
MF-LF

1

2

1

2

CRITICAL

C7023

0.47UF

CHGR_CSI_NCHGR_CSI_P

D1

Q7030

SIZ342DT

PWRPAIR-3X3-COMBO

S2

S1/D2G1G2

9

1

8

S2

CRITICALCRITICAL

G2

S1/D2

981

G1

D1

Q7040

SIZ342DT

PWRPAIR-3X3-COMBO

CHGR_GATE_Q3CHGR_GATE_Q2

DIDT=TRUE
GATE_NODE=TRUE

XW7030

SM

2

1

2

XW7031

SM

1

1

R7022

1.00

1%
1/20W
MF-LF
02010201

2

CHGR_CSIR_NCHGR_CSIR_P

CRITICAL

1

C7022

0.047UF

10%

50V50V

2

CER-X7R
0402

CHGR_GATE_Q1

DIDT=TRUE
GATE_NODE=TRUE

CHGR_LX1

DIDT=TRUE
SWITCH_NODE=TRUE

CRITICAL

1

C7030

0.1UF

10%

25V

2

X7R-CERM-1
0402

CHGR_BOOT1_RC

DIDT=TRUE
SWITCH_NODE=TRUE

1

R7030

0

5%
1/16W
MF-LF
402

2

CHGR_BOOT1

DIDT=TRUE
SWITCH_NODE=TRUE

21

DIDT=TRUE

GATE_NODE=TRUE

CHGR_LX2

SWITCH_NODE=TRUE

CRITICAL

C7040

X7R-CERM-1

CHGR_BOOT2_RC

SWITCH_NODE=TRUE

CHGR_BOOT2

SWITCH_NODE=TRUE

DIDT=TRUE

0.1UF

10%

25V

0402

DIDT=TRUE

R7040

0

5%
1/16W
MF-LF

402

DIDT=TRUE

CHGR_GATE_Q4

DIDT=TRUE
GATE_NODE=TRUE

(BMON)

1

CRITICAL

2

1

PLACE_NEAR=Q7040.10:2MM

XW7060

SM

21

(PBUS)

R7060

0.005

1%
1W
MF

0612-8

12
34

CHGR_CSO_P CHGR_CSO_N

2

CRITICAL

C7065

2.2UF

20%

25V

X5R-CERM

0402-1

PPVBAT_G3H_CHGR_R

78

MIN_LINE_WIDTH=0.6000

MIN_NECK_WIDTH=0.1500

VOLTAGE=13.05V

CRITICAL

1

2

C7066

2.2UF

20%

25V

X5R-CERM

0402-1

CRITICAL

1

C7067

0.1UF

10%

2

25V

X5R

0201

CRITICAL

Q7065

SI7655DN-COMBO

PWRPK-1212-8

SYM-VER-2

3

S
2
1

G

4

CRITICAL

1

C7068

0.01UF

2

79

D

X5R-CERM

5

1

10%

25V

2

0201

PPVBAT_G3H_FUSE

MIN_LINE_WIDTH=0.6000

MIN_NECK_WIDTH=0.1500

VOLTAGE=13.05V

CRITICAL

F7000

12A-32V-0.0045OHM

21

1206

TO/FROM BATTERY

PPVBAT_G3H_CONN

MIN_LINE_WIDTH=0.6000

MIN_NECK_WIDTH=0.1500

VOLTAGE=13.05V

55
78

C

B

A

NOSTUFF

C7016

0.01UF

10%

25V

X5R-CERM

0201

PP1V8_SLPS2R

74

1

R7015

750K

1%
1/20W
MF
201

2

1

2

PPBUS_G3H

56 75

CHGR_AUX_DET

1

R7016

255K

1%
1/20W
MF
201

2

CRITICAL

20%

6.3V
X5R

1

2

C7080

1.0UF

0201-1

R7073

1/20W

0201

CRITICAL

C7078

X5R-CERM

1

0

5%
MF

2

2.2UF

20%

35V

0402

CRITICAL

C7070

0.12UF

1

2

10%
10V
X5R

0402

20%

4V

CERM-X5R-1

201

NO_XNET_CONNECTION=1

VOLTAGE=5V

PPCHGR_VDDA

CRITICAL

1

C7075

20%

25V

2

X5R-CERM
0402-1

B5

P_IN

C5

CSIN

D5

CSIP

A5

PBUS_PWR

D3

AUX_DET

F5

VDDIO1P8

42

BI

42

IN

55

IN

NOSTUFF

I2C_PWR_SDA
I2C_PWR_SCL
CHGR_RST_IN

78

CHGR_HPWR_EN_L

CHGR_COMP

H: 3-CELL
L: 2-CELL

G5

SDA

H5

SCL

G2

SMC_RST_IN

G3

HPWR_EN*

E5

COMP

G4

CELL

B2

NC0

C2

NC1

E4

CRITICAL

10%
10V
X5R

0402

1

2

1

C7071

0.12UF

2

R7075

4.7

1/20W

A2

21

5%
MF

VOLTAGE=5V

201

PPCHGR_VDDP

CRITICAL

D2

VDDA

VDDP

U7000

ISL9240HI

WCSP

CRITICAL

353S01525

AGND

PGND

E2

E3

C7077

10UF2.2UF

20%

10V

X5R

0603-1

GATE_Q1

BOOT1

GATE_Q2
GATE_Q3

BOOT2

GATE_Q4

PBUS
CSOP
CSON

BGATE

VBAT

EN_VR1

SMC_RST*

IRQ*
CBC_ON
EN_MVR
AUX_OK

AMON

BMONNC2

1

2

LX1

LX2

H1
F1
G1
E1
D1
B1
C1
A1
A3
A4
B4
B3
C3
F2
H4
H3
H2
F4
F3
D4
C4

PBUS_SNS

MIN_LINE_WIDTH=0.1000

CHGR_BGATE
CHGR_VBAT

NC_CHGR_EN_VR1

TP_CHGR_SMC_RST_L

CHGR_INT_L

CHGR_CBC_ON
CHGR_EN_MVR
NC_CHGR_AUX_OK
CHGR_AMON
CHGR_BMON

OUT

OUT
OUT
OUT
OUT
OUT
OUT

76

64

64

55

76

44

1

C7060

0.1UF

10%

25V

2

X5R
0201

D

Q7070

DMN32D2LFB4

DFN1006H4-3

SYM_VER_2

S G

1

B

PLACE_NEAR=D7070.K:5MM

R7061

1.00

1%
1/20W
MF-LF

10%

50V

0402

0201

1

2

PLACE_NEAR=U7000.A4:2mm

CHGR_CSOR_P

CRITICAL

C7061

0.047UF

CER-X7R

1

C7064

1000PF

10%

25V

2

X7R
0201

1

2

1

R7062

1.00

1%
1/20W
MF-LF
0201

2

PLACE_NEAR=U7000.B4:2mm

MIN_LINE_WIDTH=0.2000

MIN_NECK_WIDTH=0.1000

CHGR_CSOR_N

1

C7063

4700PF

10%

25V

2

CER-X5R
0201

3

CRITICAL

1

C7062

0.047UF

10%

50V

2

CER-X7R
0402

2

R7071

SAVE_BAT_S

SAVE_BAT_G

200K

CRITICAL

C7020

1/20W

0.47UF

21

20%

CERM-X5R-1

NO_XNET_CONNECTION=1

78 44

4V

201

1

R7063

1K

1%
1/20W
MF
201

2

1

R7070

24K

1%
1/20W
MF
201

2

KA

D7070

DFN0201

GDZ5V6LP3-55

DESIGN: J230/MLB
LAST CHANGE: Fri Sep 28 20:05:04 2018

PAGE TITLE

1%
MF

201

21

PPDCIN_G3H

79 78 75

SYNC_DATE=02/13/2017SYNC_MASTER=X1032_MLB_P4BP

A

PBUS Supply & Battery Charger

SIZE

D

BOM_COST_GROUP=PLATFORM POWER

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

051-05232

REVISION

2.0.0

BRANCH

proto4b

PAGE

70 OF 152

SHEET

56 OF 86

8

67

35 4

2

1

678

www.laptoprepairsecrets.com

3 245

1

D

A

CPU Core IMVP9 PWM Controller

R7101

10

5%
MF

201

21

MIN_NECK_WIDTH=0.0750
VOLTAGE=13.1V

41

1

C7101

0.22UF

10%
25V

2

X7R
0402

CRITICAL

U7100

42

VIN

PP5V_COREVR_VCCPPVIN_S0_CPUVR_VIN

57

MIN_LINE_WIDTH=0.1800MIN_LINE_WIDTH=0.1400
MIN_NECK_WIDTH=0.0750
VOLTAGE=5V

VCC

ISL95828B3

11 24

NC
NC

NC

NC
NC

NC

NC

FCCM_B

12 25

PWM1_B

13 26

PWM2_B

7 19

ISUMP_B

8 20

ISUMN_B

9 21

ISEN1_B

10 22

ISEN2_B

4 16

COMP_B

5 17

FB_B

6 18

RTN_B

2 14

IMON_B

TQFN

CRITICAL

FCCM_A

PWM1_A
PWM2_A
PWM3_A

ISUMP_A
ISUMN_A

ISEN1_A
ISEN2_A
ISEN3_A

COMP_A

FB_A

RTN_A

IMON_A

27

23

CPUCORE_FCCM
CPUCORE_PWM1

CPUCORE_PWM2
CPUCORE_PWM3

CPUCORE_ISUMP
CPUCORE_ISUMN_R

CPUCORE_ISEN1
CPUCORE_ISEN2
CPUCORE_ISEN3

COMP_A_CPUCORE
FB_A_CPUCORE
RTN_A_CPUCORE
IMON_A_CPUCORE

PPBUS_HS_CPU

75

PP5V_COREVR_VCC

57

1/20W 1/20W

R7100

1

C7100

1.0UF

10%
25V

2

X6S
0402

CRITICAL

1

5%
MF

201

D

21

PP5V_G3S

58

OUT

58

OUT

58

OUT

58

OUT

IN

57

IN
IN
IN

57

57

57

57

58 57

58 57

58 57

58 57

58 75

E

CPU VCC Core

CPU Core Comp Network

NOSTUFF

2 1

2 1

10%25V X7R-CERM 0201

51.1K

201MF1%1/20W

150PF

R7161

2 1

1.5K

1%

1/20W

MF

201

COMP_A_CPUCORE

57

C7161

6800PF

2 1

10V 10%

X7R-CERM

R7162

C7162

COMP_A_CPUCORE_L

0201

CPU Core Prog Options

1

R7111

34K

1%
1/20W
MF
201 201

2

PROG1_CPUCOREVR

PROG2_CPUCOREVR

NOSTUFF

1

R7112

63.4K

1%
1/20W
MF

2

1

R7113

100K

1%
1/20W
MF
201

2

57

57

PROG3_CPUCOREVR

PROG4_CPUCOREVR

NOSTUFF

1

R7114

182K

1%
1/20W
MF
201

2

1

R7115

100K

1%
1/20W
MF
201

2

57

57

PROG5_CPUCOREVR

D

57

C

PROG1_CPUCOREVR

57

PROG2_CPUCOREVR

57

PROG3_CPUCOREVR

57

PROG4_CPUCOREVR

57

PROG5_CPUCOREVR

57

NC

NC
NC

NC

NC

3 15

34

35

32
33

29

30

28

40
39
38
37
36

NTC_B

FCCM_C

PWM_C

ISUMP_C
ISUMN_C

COMP_C

FB_C

RTN_C

IMON_C

PROG1
PROG2
PROG3
PROG4
PROG5

THRM_PAD

49

NTC_A

VR_HOT*

VR_READY

VR_ENABLE

SDA

ALERT*

SCLK

PSYS

46

47

48

43

44

4531

1

NTC_A_CPUCORE

CPU_VR_PROCHOT_L
CPUVR_PGOOD
CPU_VR_EN_R

CPUVR_VIDSOUT_R
CPUVR_VIDALERT_L_R
CPUVR_VIDSCLK_R

OUT

57

64 57

R7103

0

21

5%

1/20W

MF

0201

PLACE_NEAR=U7100.43:2MM

R7104

5% MF 02011/20W

PLACE_NEAR=U7100.44:2MM

R7105

PLACE_NEAR=U7100.45:2MM

R7106

5%1/20W

R7102

100

5%

1/20W

MF

201

21

21

MF1/20W 5%

21

C

21

0

0

0201

0

0201MF

SMC_PROCHOT_L

CPU_VR_EN

PP1V05_VCCST_OUT

NOSTUFF

1

R7110

45.3

1%
1/20W
MF
201

2

PLACE_NEAR=R7106.2:2MM

1

R7108

100

1%
1/20W
MF
201

2

PLACE_NEAR=R7105.2:2MM

OUT

IN

40 39 32

17

1

R7109

100

1%
1/20W
MF
201

2

PLACE_NEAR=R7104.2:2MM

64 39 14 8 6

CPU_VIDSOUT

CPU_VIDALERT_L

CPU_VIDSCLK

BI

IN

IN

F

CPU Core IMON Network

R7160

2 1

1%1/20W MF 201

73.2K

IMON_A_CPUCORE

57

C7160

2 1

8

8

G

8

CPU Core Power Good

150PF

0201X7R-CERM25V 10%

B

A

58 57

58

58 57

58 57

58 57

IN

IN

IN
IN
IN

CPUCORE_ISUMP

CPUCORE_ISUMN

CPUCORE_ISEN1
CPUCORE_ISEN2
CPUCORE_ISEN3

C7155

0.022UF

10%

6.3V
X6S

0201-1

PP1V8_PRIM_PCH

75

H

1

R7163

100K

5%
1/20W
MF
201

2

64 57

CPUVR_PGOOD

CPU Core Thermistor

rdar://problem/47518316

B

R7120

CB

2%
50V
C0G

0201

10%

6.3V
X6S

0201-1

1

2

8

R7150

340

2 1

1%1/20W MF

R7151

1K

21

1

2

1

2

1%

1/20W

MF

201

CORE_ISUMN_R

CPUCORE_ISUMN_R

201

C7150

3300PF

21

10%
10V

X7R-CERM

0201

57

8

C7151

220PF

1

C7154

0.022UF

2

0201-1

10%

6.3V
X6S

1

2

C7153

0.022UF

10%

6.3V
X6S

0201-1

C7152

0.022UF

IN

IN

CPU Core Feedback NetworkCPU Core ISUM Network

NO_XNET_CONNECTION=1

R7143

2K

2 1

1%

1/20W

MF

201

R7144

1.5K

2 1

1%

1/20W

MF

201

57

NOSTUFF

R7145

NOSTUFF

1

R7146

330K

1%
1/20W
MF
201

2

1K

1%

1/20W

MF

201

FB_A_CPUCORE

21

FB_A_CORE_RC

NOSTUFF

C7143

X5R-X7R-CERM

470PF

10%
16V

0201

57

1

2

C7141

330PF

10%
16V
X7R

0201

R7142

0

21

5%

1/20W

MF

0201

NO_XNET_CONNECTION=1

XW7140

1

2

1

C7142

330PF

10%
16V

2

X7R
0201

FB_CORE_RCPU_VCCSENSE_P

C7144

470PF

2 1

10%
16V

X5R-X7R-CERM

0201

SM

21

FB_A_CORE_R

RTN_A_CPUCORECPU_VCCSENSE_N

NTC_A_CPUCORE

57

BOM_COST_GROUP=CPU & CHIPSET

12.1K

21

NTC_A_CPUCORE_RP

201MF1/20W 1%

1

CRITICAL

ALERT=99C
HOT=105C

SYNC_MASTER=J140 MLB (CNL-Y) SYNC_DATE=06/29/2018

PAGE TITLE

R7123

220KOHM-3%

0201

2

NTC_A_CPUCORE_RN

XW7123

SM

21

IMVP9 IC

DRAWING NUMBER

051-05232

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

REVISION

2.0.0

BRANCH

proto4b

PAGE

71 OF 152

SHEET

57 OF 86

A

SIZE

D

8

67

35 4

2

1

678

www.laptoprepairsecrets.com

3 245

1

Vout = 0.55 - 1.8V

D

PPBUS_HS_CPU

58 75

PP5V_G3S

57 58 75

R7215

1

5%
1/16W
MF-LF

402

58 57

57

IN

IN

CPUCORE_FCCM
CPUCORE_PWM1

CPU VCC Phase 1

CPUCORE_CGND1

21

CRITICAL

C7217

2.2UF

20%
25V

X6S-CERM

0402

PP5V_MAIN_VCORE1

1

2

NC

PLACE_NEAR=U7210.7:2MM

VOLTAGE=5V

6

VIN

1

ZCD_EN*

12

PWM

3

NC

XW7210

SM

21

2

11

VCIN

VDRV

U7210

SIC535CD

MLP4535

CRITICAL

PGND

PGND

CGND

7

10

13

BOOT

PHASE

VSWH

GL
GL

4

5

8

9
14

NC
NC

CRITICAL

1

C7216

2.2UF

20%
25V

2

X6S-CERM
0402

CPUCORE_SW1

79

MIN_LINE_WIDTH=0.0750
MIN_NECK_WIDTH=0.0750
DIDT=TRUE
SWITCH_NODE=TRUE

CPUCORE_BOOT1

MIN_LINE_WIDTH=0.2500
MIN_NECK_WIDTH=0.2000
DIDT=TRUE

R7219

MIN_LINE_WIDTH=0.2500
MIN_NECK_WIDTH=0.2000

CPUCORE_BP1

DIDT=TRUE

CRITICAL

C7219

0.22UF

MIN_LINE_WIDTH=0.2500
MIN_NECK_WIDTH=0.2000
DIDT=TRUE

CPUCORE_PHASE1

5%
1/16W
MF-LF

402

10%
25V
X7R

0402

CRITICAL

L7210

0.33UH-20%-24A-0.007OHM

21

PIMS052T-SM

NOSTUFF

1

R7218

2.2

5%
1/10W
MF-LF

1

0

2

1

2

603

2

CPUCORE_SW1_SNUB

DIDT=TRUE

1

C7218

0.001UF

10%
50V

2

X7R-CERM
0402

NOSTUFF

PPVCC_CPU_PH1

MIN_LINE_WIDTH=9.0000
MIN_NECK_WIDTH=0.0750

VOLTAGE=1.5V

NO_XNET_CONNECTION=1

1K

1%

1/20W

MF

201

1

2

R7212

CRITICAL

R7210

0.001

1%

1W
MF-3
0612

21
43

1

2

NO_XNET_CONNECTION=1

1

R7213

100K

1%
1/20W
MF
201

2

CRITICAL

1

C7210

33UF

20%
16V

2

TANT
CASED12-SM

NO_XNET_CONNECTION=1

R7211

2.2

1%
1/20W
MF
201

NO_XNET_CONNECTION=1

CRITICAL

1

C7211

33UF

20%
16V

2

TANT
CASED12-SM

CPUCORE_ISNS1_P
CPUCORE_ISNS1_N

CPUCORE_ISUMN

CPUCORE_ISEN1

CPUCORE_ISUMP

OUT
OUT

OUT

OUT

OUT

58

57

IccMax = 49A

CRITICAL

1

C7213

2.2UF

20%
25V

2

X6S-CERM
0402

CRITICAL

1

C7214

2.2UF

20%
25V

2

X6S-CERM
0402

TDC = 18A
DCLL = 2mOhm
ACLL3 = 4.7mOhm
F = 750kHz

D

PPVCC_S0_CPU

58 57

NO_XNET_CONNECTION=1

R7214

100K

2 1

1%

1/20W

MF

201

NO_XNET_CONNECTION=1

CPUCORE_ISNS2_N

58

R7216

100K

2 1

58 57

1%

1/20W

MF

201

CPUCORE_ISNS3_N

58

75

C

B

PPBUS_HS_CPU

58 75

PP5V_G3S

57 58 75

R7225

1

5%
1/16W
MF-LF

402

58 57

57

IN

IN

CPUCORE_FCCM
CPUCORE_PWM2

CPU VCC Phase 2

21

CRITICAL

C7227

2.2UF

20%
25V

X6S-CERM

0402

PLACE_NEAR=U7220.7:2MM

CRITICAL

1

VOLTAGE=5V

PP5V_MAIN_VCORE2

1

2

11

2

VCIN

VDRV

U7220

SIC535CD

21

MLP4535

CRITICAL

PGND

PGND

CGND

7

10

13

BOOT

PHASE

VSWH

GL
GL

4

5

8

9
14

NC
NC

6

1

12

3

NC

XW7220

VIN

ZCD_EN*

PWM

NC

SM

C7226

2.2UF

20%
25V

2

X6S-CERM
0402

CPUCORE_SW2

79

MIN_LINE_WIDTH=0.1000
MIN_NECK_WIDTH=0.0750
DIDT=TRUE
SWITCH_NODE=TRUE

CPUCORE_BOOT2

MIN_LINE_WIDTH=0.2500
MIN_NECK_WIDTH=0.2000
DIDT=TRUE

R7229

MIN_LINE_WIDTH=0.2500
MIN_NECK_WIDTH=0.2000

CPUCORE_BP2

DIDT=TRUE

CRITICAL

C7229

0.22UF

MIN_LINE_WIDTH=0.2500
MIN_NECK_WIDTH=0.2000
DIDT=TRUE

5%
1/16W
MF-LF

402

10%
25V
X7R

0402

CRITICAL

L7220

0.33UH-20%-24A-0.007OHM

21

PIMS052T-SM

1

R7228

2.2

5%
1/10W
MF-LF

1

0

2

1

2

603

2

NOSTUFF

CPUCORE_SW2_SNUB

DIDT=TRUE

1

C7228

0.001UF

10%
50V

2

X7R-CERM
0402

NOSTUFF

PPVCC_CPU_PH2

MIN_LINE_WIDTH=9.0000
MIN_NECK_WIDTH=0.0750

VOLTAGE=1.5V

NO_XNET_CONNECTION=1

1K

1%

1/20W

MF

201

1

2

R7222

CRITICAL

R7220

0.001

1%

1W
MF-3
0612

21
43

1

2

NO_XNET_CONNECTION=1

1

R7223

100K

1%
1/20W
MF
201

2

NO_XNET_CONNECTION=1

R7221

2.2

1%
1/20W
MF
201

CRITICAL

1

C7220

33UF

20%
16V

2

TANT
CASED12-SM

CPUCORE_ISNS2_P
CPUCORE_ISNS2_N

NO_XNET_CONNECTION=1

CPUCORE_ISUMN

CPUCORE_ISEN2

CPUCORE_ISUMPCPUCORE_CGND2

OUT
OUT

OUT

OUT

OUT

58

57

58 57

R7224

R7226

58 57

CRITICAL

1

C7223

2.2UF

20%
25V

2

X6S-CERM
0402

NO_XNET_CONNECTION=1

100K

2 1

1%

1/20W

MF

201

NO_XNET_CONNECTION=1

100K

2 1

1%

1/20W

MF

201

CPUCORE_ISNS1_N

CPUCORE_ISNS3_N

CRITICAL

1

C7224

2.2UF

20%
25V

2

X6S-CERM
0402

C

58

58

B

CPUCORE_PHASE2

A

PPBUS_HS_CPU

58 75

PP5V_G3S

57 58 75

R7235

1

5%
1/16W
MF-LF

402

58 57

57

IN

IN

CPUCORE_FCCM
CPUCORE_PWM3

CPU VCC Phase 3

CPUCORE_CGND3

21

CRITICAL

C7237

2.2UF

20%
25V

X6S-CERM

0402

VOLTAGE=5V

PP5V_MAIN_VCORE3

1

2

12

NC

XW7230

PLACE_NEAR=U7230.7:2MM

6

VIN

1

ZCD_EN*

PWM

3

NC

SM

2

VCIN

U7230

SIC535CD

MLP4535

CRITICAL

PGND

PGND

7

10

21

11

VDRV

CGND

13

BOOT

PHASE

VSWH

GL
GL

4

5

8

9
14

NC
NC

CRITICAL

1

C7236

2.2UF

20%
25V

2

X6S-CERM
0402

CPUCORE_SW3

79

MIN_LINE_WIDTH=0.1000
MIN_NECK_WIDTH=0.0750
DIDT=TRUE
SWITCH_NODE=TRUE

CPUCORE_BOOT3

MIN_LINE_WIDTH=0.2500
MIN_NECK_WIDTH=0.2000
DIDT=TRUE

R7239

MIN_LINE_WIDTH=0.2500
MIN_NECK_WIDTH=0.2000

CPUCORE_BP3

DIDT=TRUE

CRITICAL

C7239

0.22UF

MIN_LINE_WIDTH=0.2500
MIN_NECK_WIDTH=0.2000
DIDT=TRUE

CPUCORE_PHASE3

5%
1/16W
MF-LF

402

10%
25V
X7R

0402

CRITICAL

L7230

0.33UH-20%-24A-0.007OHM

21

PIMS052T-SM

1

R7238

2.2

5%
1/10W
MF-LF

1

0

2

1

2

603

2

NOSTUFF

CPUCORE_SW3_SNUB

DIDT=TRUE

1

C7238

0.001UF

10%
50V

2

X7R-CERM
0402

NOSTUFF

PPVCC_CPU_PH3

MIN_LINE_WIDTH=9.0000
MIN_NECK_WIDTH=0.0750

VOLTAGE=1.5V

NO_XNET_CONNECTION=1

1K

1%

1/20W

MF

201

1

2

R7232

CRITICAL

R7230

0.001

1%

1W
MF-3
0612

21
43

1

2

NO_XNET_CONNECTION=1

1

R7233

100K

1%
1/20W
MF
201

2

CPUCORE_ISEN3

CPUCORE_ISUMP

CRITICAL

1

C7230

33UF

20%
16V

2

TANT
CASED12-SM

NO_XNET_CONNECTION=1

R7231

2.2

1%
1/20W
MF
201

NO_XNET_CONNECTION=1

CPUCORE_ISNS3_P
CPUCORE_ISNS3_N

CPUCORE_ISUMN

NO_XNET_CONNECTION=1

R7234

100K

2 1

1%

1/20W

MF

201

NO_XNET_CONNECTION=1

57

OUT

OUT

58 57

R7236

100K

2 1

1%

1/20W

MF

201

CRITICAL

1

C7233

2.2UF

20%
25V

2

X6S-CERM
0402

OUT

58

OUT

OUT

CPUCORE_ISNS1_N

CPUCORE_ISNS2_N

58 57

58

58

BOM_COST_GROUP=CPU & CHIPSET

CRITICAL

1

C7234

2.2UF

20%
25V

2

X6S-CERM
0402

PAGE TITLE

IMVP9 POWER BLOCK

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=10/18/2018SYNC_MASTER=psm

DRAWING NUMBER

051-05232

REVISION

2.0.0

BRANCH

proto4b

PAGE

72 OF 152

SHEET

58 OF 86

A

SIZE

D

8

67

35 4

2

1

678

www.laptoprepairsecrets.com

3 245

1

D

C

A

VCCIN_AUX Voltage Regulator

9

9

PCH_VCCINSENSE_P

IN

PCH_VCCINSENSE_N

IN

VCCINAUX_AGND

59

MIN_LINE_WIDTH=0.0900
MIN_NECK_WIDTH=0.0750

VOLTAGE=0V

5%
25V
C0G

0201

1

2

C7430

100PF 100PF

1

C7431

5%
25V

2

C0G
0201

NO_XNET_CONNECTION=1

1

R7408

51.1

1%
1/20W
MF
201

2

PCH_VCCINSENSE_P_R

NO_XNET_CONNECTION=1

5%
MF

0201

1

0

2

R7403

1/20W

CRITICAL

1

R7405

2.8K

0.1%
1/20W
MF
0201

2

R7416

4.99K

1/20W

0.1%
MF

0201

1

2

C7406

47PF

5%
25V
C0G

0201

C7423

6800PF

X7R-CERM

1

2

10%
10V

0201

CRITICAL

1

R7417

200K

0.1%
1/20W
TF
0201

2

1

2

1

R7418

33.2K

1%
1/20W
MF
201

2

CRITICAL

1

R7400

357K

0.1%
1/20W
MF
0201

2

VCCINAUX_SET1_R

PPVCCINAUX_VCC

MIN_LINE_WIDTH=0.0900
MIN_NECK_WIDTH=0.0750
VOLTAGE=5V

VCCINAUX_PROG1

NOSTUFF

1

C7417

22PF

5%
50V

2

C0G
0201

1

R7412

9.76K

1%
1/20W
MF
201

2

CRITICAL

1

R7413

324K

0.1%
1/20W
MF
0201

2

Must be 0.1%

VCCINAUX_EN_R

59

VCCINAUX_FB
VCCINAUX_SREF
VCCINAUX_VO
VCCINAUX_OCSET

64 59

VCCINAUX_PGOOD
VCCINAUX_RTN
VCCINAUX_PROG
VCCINAUX_SET0
VCCINAUX_SET1
VCCINAUX_VID0

59

VCCINAUX_VID1

59

CRITICAL

1

R7414

158K

0.1%
1/20W
MF
0201

2

Must be 0.1%

VCCINAUX_PROG2

79 78 75 60

CRITICAL

PP5V_G3S

C7422

10UF

20%
10V

X5R-CERM

0402-7

1

2

R7401

CRITICAL

C7421

10UF

20%
10V

X5R-CERM

0402-7

2.2

5%

1/20W

MF

201

1

2

1

2

19

1

2

20

VINVCC

U7400

ISL95878A3

15 18

EN

10

FB

7

SREF

12

VO

11

OCSET

14

PGOOD

4

RTN

13

PROG

8

SET0

9

SET1

6

VID0

5

VID1

UTQFN

CRITICAL

353S02011

PGNDGND

3

2

NOSTUFF

R7406

2.2

5%
1/20W
MF
201

PPVCCINAUX_PVCC

CRITICAL

1

C7424

2.2UF

20%
25V

2

X6S-CERM
0402

BOOT

UGATE

PHASE

LGATE

PPBUS_HS_CPU

1

R7407

2.2

5%
1/20W
MF
201

2

MIN_LINE_WIDTH=0.0900
MIN_NECK_WIDTH=0.0750
VOLTAGE=13.1V

1

C7425

2.2UF

20%
25V

2

X6S-CERM
0402

CRITICAL

VCCINAUX_VBST

MIN_LINE_WIDTH=0.1000
MIN_NECK_WIDTH=0.2000
DIDT=TRUE
SWITCH_NODE=TRUE

DIDT=TRUE
SWITCH_NODE=TRUE
MIN_NECK_WIDTH=0.2000
MIN_LINE_WIDTH=0.1000

17

16

1

VCCINAUX_DRVH VCCINAUX_DRVH_R
VCCINAUX_SW

59

MIN_LINE_WIDTH=0.0750
MIN_NECK_WIDTH=0.0750
SWITCH_NODE=TRUE
DIDT=TRUE

VCCINAUX_DRVL

MIN_LINE_WIDTH=0.1000
MIN_NECK_WIDTH=0.2000
GATE_NODE=TRUE
DIDT=TRUE

R7409

1

5%
1/16W
MF-LF

402

R7450

0.100

1%

1/4W

MF

0402

59 75

VCCINAUX_BOOT_RC

MIN_LINE_WIDTH=0.1000
MIN_NECK_WIDTH=0.2000
DIDT=TRUE

1

2

SWITCH_NODE=TRUE

CRITICAL

1

C7416

0.22UF

10%
25V

2

X7R
0402

R7439

1.5

1

2

VCCINAUX_DRVL_R

MIN_LINE_WIDTH=0.1000
MIN_NECK_WIDTH=0.2000
GATE_NODE=TRUE
DIDT=TRUE

21

MF-LF 4025%1/16W

DIDT=TRUE
SWITCH_NODE=TRUE
MIN_NECK_WIDTH=0.2000
MIN_LINE_WIDTH=0.1000

VCCINAUX_DRVL_R2

MIN_LINE_WIDTH=0.1000
MIN_NECK_WIDTH=0.2000
DIDT=TRUE
GATE_NODE=TRUE

2

0402
MF
1/4W
1%

0.100

R7451

1

1

2

7

59 75

CRITICAL

Q7401

FDPC1012S

LLP

HSG

SW

LSG

VER-2

PPBUS_HS_CPU

V+

8

V+

9

3

SW

4

SW

VCCINAUX_SW

59

GND

GND

GND

6

5

10

Vout = 1.8V, 1.65V, 1.1V, 0V
Iout Max = 15A

TDC = 8.5A
ACLL3 = 9.4mOhm
ACLL2 = 8.5mOhm
F = 750kHz

1

C7400

2.2UF

20%
25V

2

X6S-CERM
0402

CRITICAL

L7400

0.33UH-20%-24A-0.007OHM

21

VCCINAUX_R

NO_XNET_CONNECTION=1

PIMS052T-SM

NOSTUFF

1

R7498

2.2

5%
1/10W
MF-LF
603

2

VCCINAUX_SW_SNUB

NOSTUFF

1

C7498

0.001UF

10%
50V

2

X7R-CERM
0402

MIN_LINE_WIDTH=0.1000
MIN_NECK_WIDTH=0.0750

VOLTAGE=5V

NO_XNET_CONNECTION=1

R7421

2.74K

1%

1/20W

MF

201

1

C7401

2.2UF

20%
25V

2

X6S-CERM
0402

CRITICAL

R7430

45

1

C7470

2

470PF

2 1

10%
16V

X5R-X7R-CERM

NO_XNET_CONNECTION=1

C7471

22PF

5%

50V

CRITICAL

1

C7402

33UF

20%
16V

2

TANT
CASED12-SM

POLY-TANT

0.001

1%

1W
MF-3
0612

VCCINAUX_ISNS_P

0201

21

C0G

0201

21

PPVCCIN_AUX_PCH

43

VCCINAUX_ISNS_N

45

1

R7422

2.74K

1%
1/20W
MF
201

2

1

2

NO_XNET_CONNECTION=1

CRITICAL

C7403

33UF

20%
16V
TANT
CASED12-SM

POLY-TANT

D

59 75

C

B

B

66 9

66 9

NOSTUFF

5%
50V
C0G

0201

1

2

C7426

10PF

VID Control

9 42 74

IN

IN

PCH_CORE_VID0

PCH_CORE_VID1

R7488
R7487

NOSTUFF

R7402

4.99K

1%

1/20W

MF

201

0

0

NOSTUFF
CRITICAL

1

2

1

R7404

4.99K

0.1%
1/20W
MF
0201

2

NOSTUFF

1

C7415

10PF

5%
50V

2

C0G
0201

1

R7419

9.53K

1%
1/20W
MF
201

2

1

R7415

8.87K

1%
1/20W
MF
201

2

VCCINAUX_AGND

59

MIN_LINE_WIDTH=0.0900
MIN_NECK_WIDTH=0.0750

VOLTAGE=0V

XW7400

SM

21

PLACE_NEAR=U7400.3:1mm

D

VCCIN_AUX Notes

MPN ISL95878A3S2378, config. 13 (of 1 to 32), Fsw=750kHz, Vref=0.7V, Decay=on, EA=A
R7412=9.76k/1%, R7413=324k/0.1%, R7414=158k/0.1%, R7415=8.87k/1%

MPN ISL95878A3S2378, config. 9 (of 1 to 32), Fsw=750kHz, Vref=0.7V, Decay=off, EA=A
R7412=47.5k/1%, R7413=324k/0.1%, R7414=127k/0.1%, R7415=1.58k/1%

C

PP3V3_S5

1

R7481

100K

5%
1/20W
MF
201

21

21

02015%1/20W MF

02015% MF1/20W

2

NOSTUFF

1

R7480

100K

5%
1/20W
MF
201

2

1

R7485

100K

5%
1/20W
MF
201

2

VCCINAUX_VID0
VCCINAUX_VID1

NOSTUFF

1

R7484

100K

5%
1/20W
MF
201

2

59

59

Additional output caps are on the CPU decoupling page.

VCCIN_AUX BHC Caps G

CRITICAL

1

C7450

10UF

20% 20%

6.3V

2

CER-X6S
0402

CRITICAL

1

C7454

10UF

20%

6.3V

2

CER-X6S
0402

CRITICAL

1

C7451

10UF

6.3V

2

CER-X6S
0402

CRITICAL

1

C7455

10UF

20%

6.3V

2

CER-X6S
0402

1

3 2

1

2

CRITICAL

C7452

180UF

20%

2.5V
POLY-AL
SM

CRITICAL

C7456

10UF

20%

6.3V
CER-X6S
0402

1

3 2

1

2

CRITICAL

C7453

180UF

20%

2.5V
POLY-AL
SM

CRITICAL

C7457

10UF

20%

6.3V
CER-X6S
0402

CRITICAL

1

C7458

10UF

20%

6.3V

2

CER-X6S
0402

CRITICAL

1

C7459

10UF

20%

6.3V

2

CER-X6S
0402

CRITICAL

1

C7460

10UF

20%

6.3V

2

CER-X6S
0402

NOSTUFF

PPVCCIN_AUX_PCH

CRITICAL

1

C7461

10UF

20%

6.3V

2

CER-X6S
0402

NOSTUFF

59
75

P1V8PRIM_PGOOD

61 59

Ensure VCCIN_AUX decays below 200mV
within 100 ms (see PDG tPCH35).

VCCIN_AUX Discharge

PPVCCIN_AUX_PCH

PP3V3_G3H_RTC

PVCCINAUX_DSCHG_EN

Q7490

SOT563

VER-3

2

6

D

SG

1

1/16W 402MF-LF

1/20W

R7490

0

21

PVCCINAUX_DSCHG_EN_L

MF5%1/20W

0201

80 75 11

78 75

DMN5L06VK-7

R7492

47

5%

R7491

100K

21

PVCCINAUX_DSCHG

5%
25V
C0G

0201

Q7490

SOT563

VER-3

5

1

2

DMN5L06VK-7

21

201MF5%

NOSTUFF

C7490

100PF

3

D

SG

4

B

A

E

VR Enable

P1V8PRIM_PGOOD

8

61 59

IN

R7440

0

5%

1/20W

MF

0201

21

NOSTUFF

1

C7440

0.1UF

10%
25V

2

X6S-CERM
0201

VCCINAUX_EN_R

1

R7444

510K

5%
1/20W
MF
201

2

59

67

F

79 78 75 16

VR PGOOD

PP1V8_PRIM_PCH

1

R7441

100K

5%
1/20W
MF
201

2

VCCINAUX_PGOOD

OUT

VID[1]
Pin State

0
0
1
1

VID[0]
Pin State

0
1
0
1

VCCIN_AUX

(V)

0

1.1

1.65

1.8

USAGE

Power Saving State
Power Saving State
Full Current, ICL-Y
Initial boot for ICL-U/Y

Full Current, ICL-U

64 59

BOM_COST_GROUP=PLATFORM POWER

35 4

SYNC_MASTER=CPU_CARD_ICL_Y SYNC_DATE=06/08/2018

PAGE TITLE

VR: VCCIN_AUX ISL

SIZE

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

2

DRAWING NUMBER

051-05232

REVISION

2.0.0

BRANCH

proto4b

PAGE

74 OF 152

SHEET

59 OF 86

1

A

D

678

www.laptoprepairsecrets.com

3 245

1

D

5V G3S

PP5V_G3S

60 75

CRITICAL

C7671

2.2UF

X6S-CERM

1

20%
25V

2

0402

CRITICAL

1

C7675

220UF-25MOHM

20%

6.3V

2

POLY-TANT
CASE-B2-SM

CRITICAL

1

C7677

220UF-25MOHM

20%

6.3V

2

POLY-TANT
CASE-B2-SM

Vout = 5.1V
Iout Max = 6.41A
F = 500 KHZ

CRITICAL

1

C7670

2.2UF

20%
25V

2

X6S-CERM
0402

CRITICAL

1

C7676

220UF-25MOHM

20%

6.3V

2

POLY-TANT
CASE-B2-SM

PPVIN_G3H_P5VG3S

44 75

CRITICAL

1

C7665

33UF

20%
16V

2

TANT
CASED12-SM

POLY-TANT POLY-TANT

CRITICAL

1

C7666

33UF

20%
16V

2

TANT
CASED12-SM

CRITICAL

1

C7660

2.2UF

20%
25V

2

X6S-CERM
0402

CRITICAL

1

C7661

2.2UF

20%
25V

2

X6S-CERM
0402

PP5V_G3S

60 75

100MA MAX OUTPUT

PP5V_S5_LDO

CRITICAL

1

C7651

10UF

20%
16V

2

X6S-CERM
0603

P5VP3V3_VREG3

VOUT = 5V

75

PPVIN_G3H_P3V3G3H

44 75

CRITICAL

1

C7650

2.2UF

20%
25V

2

X6S-CERM
0402

1

2

CRITICAL

C7680

2.2UF

20%
25V
X6S-CERM
0402

CRITICAL

1

C7681

2.2UF

20%
25V

2

X6S-CERM
0402

CRITICAL

1

C7685

33UF

20%
16V

2

TANT
CASED12-SM

POLY-TANT

CRITICAL

1

C7686

33UF

20%
16V

2

TANT
CASED12-SM

POLY-TANT

CRITICAL

C7690

2.2UF

20%
25V

X6S-CERM

0402

CRITICAL

C7695

150UF

20%

6.3V
TANT

CASE-B-SM

POLY-TANT

CRITICAL

C7611

150UF

20%

6.3V
TANT

CASE-B-SM

POLY-TANT

3V3 G3H

Vout = 3.3V
Iout Max = 9.56A
F = 500 KHZ

CRITICAL

1

2

1

2

1

2

C7691

2.2UF

X6S-CERM

CRITICAL

C7696

150UF

CASE-B-SM

POLY-TANT

CRITICAL

C7697

150UF

CASE-B-SM

POLY-TANT

20%
25V

0402

20%

6.3V
TANT

20%

6.3V
TANT

PP3V3_G3H

1

2

60
75

D

CRITICAL

1

C7613

150UF

2

CASE-B-SM

POLY-TANT

20%

6.3V
TANT

1

2

CRITICAL

20%

6.3V
TANT

1

2

1

C7612

150UF

2

CASE-B-SM

POLY-TANT

C

B

1.5UH-20%-12.5A-0.017OHM

PLACE_NEAR=C7675.1:5.3MM

2

XW7675

SM

1

P5VG3S_VFB1_R

1

R7671

10

5%
1/20W
MF
201

2

2

XW7671

SM

NO_XNET_CONNECTION=1

P5VG3S_VFB1_R2

1

R7677

6.34K

1%
1/20W
MF
201

2

P5VG3S_VFB1_RR

1

R7678

34.8K

0.1%
1/20W
MF
0201-1

2

1

R7679

10K

0.1%
1/20W
MF
0201-1

2

CRITICAL

CRITICAL

1

CRITICAL

L7670

21

P5VG3S_VSW

79

PIMB062D-SM

152S00268

MIN_LINE_WIDTH=0.1160
MIN_NECK_WIDTH=0.0750

PLACE_NEAR=L7670.1:3MM

PLACE_NEAR=L7670.2:3MM

2

XW7670

SM

NO_XNET_CONNECTION=1

1

DIDT=TRUE

P5VG3S_CS1_L_P

P5VG3S_CS1_L_N

1

VIN

6
7
8

NOSTUFF

1

R7674

2.2

5%
1/10W
MF-LF
603

2

P5VG3S_SNUBR

DIDT=TRUE

SWITCH_NODE=TRUE

NOSTUFF

1

C7674

0.001UF

10%
50V

2

X7R-CERM
0402

CRITICAL

Q7660

CSD58873Q3D

Q3D

VSW

PGND

9

TGR

376S1038

MIN_LINE_WIDTH=0.1000
MIN_NECK_WIDTH=0.2000

NO_XNET_CONNECTION=1

MIN_LINE_WIDTH=0.1000
MIN_NECK_WIDTH=0.2000
GATE_NODE=TRUE
DIDT=TRUE

3

TG

BG

GATE_NODE=TRUE

P5VG3S_DRVH

4

5

P5VG3S_DRVL P3V3G3H_DRVL

DIDT=TRUE

R7672

4.22K

2 1

1%
1/16W
MF-LF

402

R7666

2 1

1/16W
MF-LF

R7664

0

2 1

5%
1/16W
MF-LF

402

P5VG3S_VBST_R

MIN_LINE_WIDTH=0.2500
MIN_NECK_WIDTH=0.2000
SWITCH_NODE=TRUE

DIDT=TRUE

CRITICAL

1

C7669

0.1UF

1

5%

402

MIN_LINE_WIDTH=0.1000
MIN_NECK_WIDTH=0.1500

MIN_LINE_WIDTH=0.1000
MIN_NECK_WIDTH=0.2000

MIN_LINE_WIDTH=0.1000
MIN_NECK_WIDTH=0.2000

10%
25V

2

X7R-CERM-1
0402

MIN_LINE_WIDTH=0.2500
MIN_NECK_WIDTH=0.2000

CRITICAL

NO_XNET_CONNECTION=1

C7673

0.1UF

21

10%
25V

X6S-CERM

0201

R7673

1.24K

1/20W

NO_XNET_CONNECTION=1

1%
MF

201

21

AUDIBLE SKIPPING

R7651

1/20W

0201

R7665

1/16W
MF-LF

C7678

560PF

1

0

5%

402

2

GATE_NODE=TRUE DIDT=TRUE MIN_LINE_WIDTH=0.1000

SWITCH_NODE=TRUE DIDT=TRUE

GATE_NODE=TRUE DIDT=TRUE

64 60

1

5%

25V

2

C0G

0201

INAUDIBLE SKIPPING

NOSTUFF

1

R7650

0

5%
1/20W
MF
0201

2

5%
MF

1

0

2

P5VP3V3_SKIPSEL

P5VG3S_VBST P3V3G3H_VBST

SWITCH_NODE=TRUEDIDT=TRUE

P5VG3S_DRVH_R P3V3G3H_DRVH_R
P5VG3S_SW
P5VG3S_DRVL_R
P5VG3S_CSP1

P5VG3S_COMP1
P5VG3S_EN_DLY TP_P3V3G3H_EN2

60

OUT

P5VG3S_PGOOD P3V3MAIN_PGOOD

NOSTUFF

1

R7676

10K

1%
1/20W
MF
201

2

P5VG3S_COMP1_R

1

C7679

4700PF

10%
10V

2

X7R
201

(P5VP3V3_VREF2)

6
19
14

31

1

32

30

7

8

11

9
10

4

5

1%
MF

201

1

2

R7675

5.49K

1/20W

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1500

VOLTAGE=0V

GND_5V3V3_AGND

2

V5SW

SKIPSEL1
SKIPSEL2
OCSEL

VBST1 VBST2

DRVH1 DRVH2

SW1 SW2

DRVL1

CSP1
CSN1 CSN2

MODE

COMP1 COMP2

EN1 EN2
PGOOD1 PGOOD2

23

VIN

GND

28

XW7650

29

VREG5

CRITICAL

U7650

QFN

353S01936

PLACE_NEAR=U7650.28:1MM

2

SM

1

22

VREG3

TPS51980B

THRM_PAD

13

VREF2

EN

DRVL2

CSP2

RF

VFB2VFB1

33

P5VP3V3_VREF2

CRITICAL

C7652

12

26

24

25

27

18
17

3
16
15

21
20

0.22UF 2.2UF

P5VXX_EN

DIDT=TRUE

P3V3G3H_SW

DIDT=TRUE

P3V3G3H_DRVL_R

DIDT=TRUE

P3V3G3H_CSP2

P3V3G3H_RF
P3V3G3H_VFB2P5VG3S_VFB1
P3V3G3H_COMP2

10%
25V
X7R

0402

1

R7695

5.49K

1%
1/20W
MF
201

2

P3V3G3H_COMP2_R

(P5VP3V3_VREF2)

CRITICAL

1

2

SWITCH_NODE=TRUE

GATE_NODE=TRUEDIDT=TRUE

1

C7653

20%
25V

2

X6S-CERM
0402

60

OUT

NOSTUFF

R7696

10K

1/20W

201

C7699

2700PF

1

10%
16V

2

X7R

0201 0201-1

1%
MF

CRITICAL

P3V3G3H_VBST_R

MIN_LINE_WIDTH=0.2500
MIN_NECK_WIDTH=0.2000

1

R7685

0

5%
1/16W
MF-LF
402

2

MIN_NECK_WIDTH=0.2000
MIN_LINE_WIDTH=0.1000SWITCH_NODE=TRUE

MIN_NECK_WIDTH=0.2000
MIN_LINE_WIDTH=0.1000GATE_NODE=TRUE

MIN_NECK_WIDTH=0.2000

SWITCH_NODE=TRUEDIDT=TRUE

C7689

0.1UF

X7R-CERM-1

CRITICAL

10%
25V

0402

1

2

MIN_LINE_WIDTH=0.1000
MIN_NECK_WIDTH=0.2000
GATE_NODE=TRUE
DIDT=TRUE

R7686

1

2 1

5%
1/16W
MF-LF

402

P3V3G3H_DRVH

3

4

5

R7684

0

CRITICAL

NO_XNET_CONNECTION=1

C7693

0.1UF

21

10%
25V

X6S-CERM

0201

R7693

1.37K

1%

1/20W

MF

201

21

NO_XNET_CONNECTION=1

1%
MF

201

1

2

NO_XNET_CONNECTION=1

R7655

64 60

1

2

1

2

200K

1/20W

C7698

270PF

10%
16V
X7R-CERM

2 1

5%
1/16W
MF-LF

402

R7692

3.83K

1%
1/16W
MF-LF

402

DIDT=TRUE

GATE_NODE=TRUE
MIN_LINE_WIDTH=0.1000
MIN_NECK_WIDTH=0.2000

21

Q7680

CSD58873Q3D

Q3D

TG

TGR

BG

VSW

9

P3V3G3H_CS2_L_P

P3V3G3H_CS2_L_N

1

VIN

6

79

P3V3G3H_VSW

7
8

NOSTUFF

R7694

PGND

376S1038

P3V3G3H_SNUBR

MIN_LINE_WIDTH=0.6000
MIN_NECK_WIDTH=0.2000
DIDT=TRUE

SWITCH_NODE=TRUE

NOSTUFF

1/10W
MF-LF

C7694

0.001UF

X7R-CERM

CRITICAL

L7690

1.0UH-20%-14A-0.0107OHM

2 1

PIMB062D-SM

152S00269

1

2.2

5%

603

10%
50V

0402

2

1

2

DIDT=TRUE

NO_XNET_CONNECTION=1
NO_XNET_CONNECTION=1

2

XW7690

SM

1

2

XW7691

SM

1

PLACE_NEAR=L7690.2:3MM

PLACE_NEAR=L7690.1:3MM

PLACE_NEAR=C7695.1:6.6MM

2

XW7695

SM

1

P3V3G3H_VFB2_R

10

5%
MF

201

1

2

R7691

1/20W

P3V3G3H_VFB2_R2

1%
MF

201

1

2

R7697

3.09K

1/20W

P3V3G3H_VFB2_RR

CRITICAL

0.1%
MF

47K

0.1%
MF

0201

1

2

1

2

R7698

105K

1/20W

0201-1

CRITICAL

R7699

1/20W

C

B

A

PP1V8_G3S

75

PP3V3_G3H

60
75

1

R7600

100K

5%
1/20W
MF
201

2

P5VG3S_PGOOD

1

R7601

100K

5%
1/20W
MF
201

2

P3V3MAIN_PGOOD

79 78 75 59

64 60

64 60

PP5V_G3S

P5VG3S_DSCHRG_R

DLLFSD01LP3

P5VG3S_DSCHRG_EN

DMN5L06VK-7

64 60

P5VG3S_EN

R7620

220K

1/20W

201

D7620

X3-DFN0603-2

Q7620

SOT563

VER-3

2

5%
MF

PMU_PVDDMAIN_EN

IN

47K

5%
MF

201

1

2

R7661

1/20W

VR - 5V, 3V3

Apple Inc.

60

64

SYNC_MASTER=J140

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

1

2

K A

R7622

1/16W
MF-LF

620

5%

402

1

2

R7623

1/16W
MF-LF

620

5%

402

1

2

R7624

1/16W
MF-LF

DMN5L06VK-7

R7621

10

21

5%

6

D

SG

1

1/20W

MF

201

P5VG3S_DSCHRG_RC

1

C7620

0.047UF

10%
16V

2

X5R
0201

5%

402

1

2

Q7620

SOT563

VER-3

5

R7625

1/16W
MF-LF

D

SG

620620

5%

402

3

4

1

2

P5V_G3S_DISCHARGE

64 60

IN

P5VG3S_EN

R7613

0

5%

1/20W

MF

0201

PP3V3_G3H

75

BYPASS=U7610::5mm

10%
10V

0201

1

2

C7610

0.1UF

X5R-CERM

U7610

74AUP1T97

5

SOT891

21

P5VG3S_EN_R P5VG3S_EN_DLY

47K

5%
MF

201

1

2

R7610

1/20W

1

2

4

6

3

1

R7611

47K

5%
1/20W
MF
201

2

BOM_COST_GROUP=PLATFORM POWER

R7660

3.3K

5%

1/20W

MF

201

21

1

C7664

1000PF

10%
16V

2

X7R-1
0201

DRAWING NUMBER

REVISION

P5VXX_EN

SYNC_DATE=08/17/2018

60

051-05232

A

SIZE

D

2.0.0

BRANCH

proto4b

PAGE

76 OF 152

SHEET

60 OF 86

8

67

35 4

2

1

A

www.laptoprepairsecrets.com

678

VCCPRIM_1P8 Voltage Regulator

3 245

1

1.8 VOutput voltage:

Iout Max:

2.07 A

D

75

18 17 14

PPBUS_HS_CPU

PM_SLP_SUS_L

IN

POLY-TANT

CAPDERATE

CRITICAL

1

C7702

33UF

20%
16V

2

TANT
CASED12-SM

CRITICAL

1

C7703

2.2UF

20%
25V

2

X6S-CERM
0402

CRITICAL

1

C7704

2.2UF

20%
25V

2

X6S-CERM
0402

R7715

0

2 1

5%

1/20W

MF

0201

R7700

10

2 1

5%

1/20W

MF

201

MIN_LINE_WIDTH=0.1400
MIN_NECK_WIDTH=0.0750

VOLTAGE=12.8V

P1V8PRIM_AVIN

P1V8PRIM_EN

10

13

Switching freq:

PP3V3_S5

74

1

R7716

100K

5%
1/20W
MF
201

2

P1V8PRIM_PGOOD

12

11

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200

SW
SW
SW

FB

PG

DIDT=TRUE

1

P1V8PRIM_PHASE

2
3

14

P1V8PRIM_VOS

5

P1V8PRIM_FB

4

1.5UH-20%-3.9A-0.048OHM

PVIN

PVIN

U7700

TPS62130B-S

AVIN

8

DEF

EN

353S00897

7

FSW

VQFN

CRITICAL

VOS

CRITICAL

L7700

1210

21

P1V8PRIM_PHASE_B

CRITICAL

L7701

0.68UH-20%-6.1A-0.020OHM

21

1210

2

XW7701

SM

1

P1V8PRIM_FB_TOP

OUT

59

1

3 2

CRITICAL

C7707

180UF

20%

2.5V
POLY-AL
SM

CRITICAL

1

C7710

20%

6.3V

2

CER-X6S
0402

CRITICAL

1

C7711

10UF10UF

20%

6.3V

2

CER-X6S
0402

PP1V8_PRIM_PCH

1250 kHz

D

61 75

C

NOSTUFF

1

C7715

0.1UF

10%
25V

2

X6S-CERM
0201

CRITICAL

1

C7705

0.1UF

10%
25V

2

X6S
0402

XW7700

SM

21

PGND

15

PGND

16

9

SS/TR

PAD

THRM

AGND

6

17

AGND_P1V8PRIM

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200

P1V8PRIM_SS

C7706

4700PF

10%
10V
X7R
201

1

R7701

10

5%
1/20W
MF
201

1

2

1

C7701

100PF

5%
25V

2

C0G
0201

2

1

R7702

1.78K

1%
1/20W
MF
201

2

<Ra>

CRITICAL

1

R7722

27.4K

0.1%
1/20W
MF
0201

2

CRITICAL

1

R7703

23.2K

0.1%
1/20W
MF
0201

2

P1V8PRIM_FB_R

NOSTUFF

R7720

10

21

5%

1/20W

MF

201

P1V8PRIM_FB_TOP2

XW7720

SM

21

PP1V8_PRIM_PCH

61 75

C

<Rb>

B

B

A

8

67

SYNC_DATE=10/18/2018SYNC_MASTER=psm

PAGE TITLE

A

VR: VCCPRIM_1P8

DRAWING NUMBER

051-05232

Apple Inc.

REVISION

2.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

BOM_COST_GROUP=GRAPHICS

35 4

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

2

BRANCH

proto4b

PAGE

77 OF 152

SHEET

61 OF 86

1

SIZE

D

D

www.laptoprepairsecrets.com

C

B

Vout = 0.9V
Iout Max = 1.4A
F = 3MHz

A

Vout = 1.8V
Iout Max = 1.3A
F = 3MHz

PPVCCQ_ANI_SSD0

74

Note : Design based on Calpe ERS - D2449-A0-110-00_0v3.pdf (Radar# 24696002)
System Block Diagram - T290 Power System Architecture . v9
Optimize componentS for individual projects based on EDP(A)

PP3V3_G3H_PMU_VDDMAIN

45 75

CRITICAL

1

C7801

10UF

20%

6.3V

2

CER-X6S
0402

CRITICAL

1

C7810

10UF

20%

6.3V

2

CER-X6S
0402

CRITICAL

1

C78B0

1UF

20%

6.3V

2

X6S-CERM
0201

CRITICAL

1

C78B9

1UF

20%

6.3V

2

X6S-CERM
0201

BYPASS=U7800.D10::5mm

CRITICAL

1

C78BA

1UF

20%

6.3V

2

X6S-CERM
0201

CRITICAL

1

C7802

10UF

20%

6.3V

2

CER-X6S
0402

CRITICAL

1

C7809

10UF

20%

6.3V

2

CER-X6S
0402

CRITICAL

1

C78B1

1UF

20%

6.3V

2

X6S-CERM
0201

CRITICAL

1

C78B8

1UF

20%

6.3V

2

X6S-CERM
0201

BYPASS=U7800.K14::5mm

CRITICAL

1

C78BB

1UF

20%

6.3V

2

X6S-CERM
0201

CRITICAL

1

C7803

10UF

20%

6.3V

2

CER-X6S
0402

CRITICAL

1

C7808

10UF

20%

6.3V

2

CER-X6S
0402

CRITICAL

1

C78B2

1UF

20%

6.3V

2

X6S-CERM
0201

CRITICAL

1

C78B7

1UF

20%

6.3V

2

X6S-CERM
0201

BYPASS=U7800.P5::5mm

CRITICAL

1

C78BC

1UF

20%

6.3V

2

X6S-CERM
0201

CRITICAL

1

C7804

10UF

20%

6.3V

2

CER-X6S
0402

CRITICAL

1

C7807

10UF

20%

6.3V

2

CER-X6S
0402

CRITICAL

1

C78B3

1UF

20%

6.3V

2

X6S-CERM
0201

CRITICAL

1

C78B6

1UF

20%

6.3V

2

X6S-CERM
0201

BYPASS=U7800.P9::5mm

CRITICAL

1

C78BD

1UF

20%

6.3V

2

X6S-CERM
0201

CRITICAL

1

C7805

10UF

20%

6.3V

2

CER-X6S
0402

CRITICAL

1

C7806

10UF

20%

6.3V

2

CER-X6S
0402

CRITICAL

1

C78B4

1UF

20%

6.3V

2

X6S-CERM
0201

CRITICAL

1

C78B5

1UF

20%

6.3V

2

X6S-CERM
0201

CRITICAL

1

C78BG

0.1UF

10%

6.3V

2

X6S
0201

CRITICAL

1

C78BE

10UF

20%

6.3V

2

CER-X6S
0402

CRITICAL

1

C78BF

10UF

20%

6.3V

2

CER-X6S
0402

CRITICAL

1

C78AE

10UF

20%

6.3V

2

CER-X6S
0402

CRITICAL

1

C78AF

10UF

20%

6.3V

2

CER-X6S
0402

1

C78BH

0.1UF

10%

6.3V

2

X6S
0201

Note : All Bucks are default Local Sense

Buck 0,2,7,9 and 10 need to have option for Remote Sense for Future Use.

VOUT = 1.05V (0.76V in LPM)
Iout Max = 0.2A
F = 3MHz

PPVNN_PCH_EXT_REG

74

Vout = 1.05V

CRITICAL

1

C7865

20UF

20%

2.5V

2

X6S-CERM
0402

CRITICAL

1

C7862

20UF

20%

2.5V

2

X6S-CERM
0402

CRITICAL

1

C7866

20UF

20%

2.5V

2

X6S-CERM
0402

CRITICAL

1

C7861

20UF

20%

2.5V

2

X6S-CERM
0402

CRITICAL

1

C7867

20UF

20%

2.5V

2

X6S-CERM
0402

CRITICAL

1

C7860

20UF

20%

2.5V

2

X6S-CERM
0402

NOSTUFF

CRITICAL

1

C7858

20UF

20%

2.5V

2

X6S-CERM
0402

CRITICAL

1

C7868

20UF

20%

2.5V

2

X6S-CERM
0402

CRITICAL

1

C7889

20UF

20%

2.5V

2

X6S-CERM
0402

NOSTUFF

CRITICAL

1

C7857

20UF

20%

2.5V

2

X6S-CERM
0402

CRITICAL

1

C7869

20UF

20%

2.5V

2

X6S-CERM
0402

CRITICAL

1

C7890

20UF

20%

2.5V

2

X6S-CERM
0402

CRITICAL

1

C7864

20UF

20%

2.5V

2

X6S-CERM
0402

CRITICAL

1

C7870

20UF

20%

2.5V

2

X6S-CERM
0402

CRITICAL

1

C7871

20UF

20%

2.5V

2

X6S-CERM
0402

CRITICAL

1

C7863

20UF

20%

2.5V

2

X6S-CERM
0402

Iout Max = 0.2A
F = 3MHz

PP1V05_PCH_EXT_REG

74

PP0V9_SSD0

74

CRITICAL

1

C78A0

20UF

20%

2.5V

2

X6S-CERM
0402

CRITICAL

1

C7872

20UF

20%

2.5V

2

X6S-CERM
0402

CRITICAL

1

C7878

20UF

20%

2.5V

2

X6S-CERM
0402

CRITICAL

1

C78A2

20UF

20%

2.5V 2.5V

2

X6S-CERM
0402

CRITICAL

1

C7891

20UF

20%

2.5V

2

X6S-CERM
0402

CRITICAL

1

C78A1

20UF

20%

2.5V

2

X6S-CERM
0402

1

2

1

2

1

2

1

2

1

2

CRITICAL

C7873

20UF

20%

2.5V
X6S-CERM
0402

CRITICAL

C7879

20UF

20%

2.5V
X6S-CERM
0402

CRITICAL CRITICAL

C78A3

20UF

20%
X6S-CERM

0402

CRITICAL

C7820

20UF

20%

2.5V
X6S-CERM
0402

CRITICAL

C7894

20UF

20%

2.5V
X6S-CERM
0402

CRITICAL

1

C7874

20UF

20%

2.5V

2

X6S-CERM
0402

CRITICAL

1

C7880

20UF

20%

2.5V

2

X6S-CERM
0402

1

C7897

20UF

20%

2.5V

2

X6S-CERM
0402

CRITICAL

1

C7882

20UF

20%

2.5V

2

X6S-CERM
0402

CRITICAL

1

C7896

20UF

20%

2.5V

2

X6S-CERM
0402

CRITICAL

1

C7895

20UF

20%

2.5V

2

X6S-CERM
0402

CRITICAL

1

C7875

20UF

20%

2.5V

2

X6S-CERM
0402

CRITICAL

1

C7881

20UF

20%

2.5V

2

X6S-CERM
0402

CRITICAL

1

C7859

20UF

20%

2.5V

2

X6S-CERM
0402

CRITICAL

1

C7883

20UF

20%

2.5V

2

X6S-CERM
0402

CRITICAL

1

C7892

20UF

20%

2.5V

2

X6S-CERM
0402

CRITICAL

1

C7886

20UF

20%

2.5V

2

X6S-CERM
0402

CRITICAL

1

C7876

20UF

20%

2.5V

2

X6S-CERM
0402

CRITICAL

1

C7898

20UF

20%

2.5V

2

X6S-CERM
0402

CRITICAL

1

C7832

20UF

20%

2.5V

2

X6S-CERM
0402

CRITICAL

1

C7884

20UF

20%

2.5V

2

X6S-CERM
0402

XW7824

SM

2 1

CRITICAL

1

C7887

20UF

20%

2.5V

2

X6S-CERM
0402

CRITICAL

1

C7877

20UF

20%

2.5V

2

X6S-CERM
0402

CRITICAL

1

C7899

20UF

20%

2.5V

2

X6S-CERM
0402

CRITICAL

1

C7831

20UF

20%

2.5V

2

X6S-CERM
0402

CRITICAL

1

C7885

20UF

20%

2.5V

2

X6S-CERM
0402

P0V9SSD_FB_N_GND

CRITICAL

1

C7888

20UF

20%

2.5V

2

X6S-CERM
0402

678

64

IN

CRITICALCRITICAL

1

C78BJ

100PF

5%
25V

2

C0G
0201

0.47UH-20%-4.8A-0.034OHM

CRITICAL

0.47UH-20%-4.8A-0.034OHM

CRITICAL

PLACE_NEAR=L7819.1:5MM

PLACE_NEAR=U7800.N15:5MM

CRITICAL

0.47UH-20%-4.8A-0.034OHM

0.47UH-20%-4.8A-0.034OHM

CRITICAL

PLACE_NEAR=L7822.1:5MM

0.47UH-20%-4.8A-0.034OHM

CRITICAL

PLACE_NEAR=L7823.1:5MM

PLACE_NEAR=U7800.N15:10MM

0.47UH-20%-4.8A-0.034OHM

CRITICAL

CRITICAL

1

C7893

20UF

20%

2.5V

2

X6S-CERM
0402

PLACE_NEAR=L7824.1:5MM

PMU_VDD_HI
PP1V8_SLPS2R_PMUVDDGPIO

62

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.0800

VOLTAGE=1.8V

CRITICAL

1

C78BK

100PF

5%
25V

2

C0G
0201

L7819

0806-COMBO

L7820

0806-COMBO

R7819
R7821

0201 MF5% 1/20W

0806-COMBO

L7821
L7822

0806-COMBO

R7820

L7823

0806-COMBO

R7822
R7824

L7824

0806-COMBO

Resistor Divider from PBUS
VDD_HI < 3.1V

C7800

0.1UF

CRITICAL

21

PVNN_PCH_EXT_SW0

21

PVNN_PCH_EXT_SW1

NOSTUFF

0

21

PVNN_PCH_EXT_FB_P

5% 1/20W MF 0201

0

21

PVNN_PCH_EXT_FB_N

NOSTUFF

21

P1V05_PCH_EXT_SW0

21

P1V05_PCH_EXT_SW1

NOSTUFF

0

21

P1V05_PCH_EXT_FB

PP1V05_PCH_EXT_REG

74

21

P0V9SSD_SW0

0

21

P0V9SSD_FB_P

0

1/20W

21

P0V9SSD_FB_N

21

P1V8SSD_SW0

1

10%

6.3V

2

X6S

0201

MIN_LINE_WIDTH=0.6000
MIN_NECK_WIDTH=0.0750

SWITCH_NODE=TRUE

MIN_LINE_WIDTH=0.6000
MIN_NECK_WIDTH=0.0750

SWITCH_NODE=TRUE

MIN_LINE_WIDTH=0.6000
MIN_NECK_WIDTH=0.0750

SWITCH_NODE=TRUE

MIN_LINE_WIDTH=0.6000
MIN_NECK_WIDTH=0.0750

SWITCH_NODE=TRUE

02011/20W5% MF

MIN_LINE_WIDTH=0.6000
MIN_NECK_WIDTH=0.0750

SWITCH_NODE=TRUE

MF5% 0201

0201MF1/20W5%

MIN_LINE_WIDTH=0.6000
MIN_NECK_WIDTH=0.0750

SWITCH_NODE=TRUE

R7823

0

21

P1V8SSD_FB

1/20W 0201MF5%

NC
NC

NC

DIDT=TRUE

DIDT=TRUE

DIDT=TRUE

DIDT=TRUE

DIDT=TRUE

DIDT=TRUE

P5

D10

P9

K14

K13

J11

C1
C2
C3

G1
G2
G3

R1
R2

L1
L2
L3

B16
B17
B18

A7
B7

A11
B11

F17
F18

K16
K17
K18

P16
P17
P18

T1
T2

R7

T4

E17
E18

G17
G18

F15

G15

L16
L17
L18

J16
J17
J18

L14

P12
R12
T12
U12
V12

N16
N17
N18

P14

N14

R16
R17
R18

R14

VDD_MAIN_E
VDD_MAIN_N
VDD_MAIN_S
VDD_MAIN_W

VDD_HI

VDD_GPIO

VDD_BUCK0_01

VDD_BUCK0_23

VDD_BUCK16

VDD_BUCK2

VDD_BUCK3

VDD_BUCK4

VDD_BUCK5

VDD_BUCK7

VDD_BUCK8

VDD_BUCK910

BUCK6_LX0

BUCK6_IN

BUCK6_FB

BUCK7_LX0

BUCK7_LX1

BUCK7_RTP

BUCK7_RTN

BUCK8_LX0

BUCK8_LX1

BUCK8_FB

BUCK8_IN

BUCK9_LX0

BUCK9_RTP

BUCK9_RTN

BUCK10_LX0

BUCK10_FB

U7800

CALPE-PMU

BGA

SYM 2 OF 4

CRITICAL
OMIT_TABLE

BUCK0_LX0

BUCK0_LX1

BUCK0_LX2

BUCK0_LX3

BUCK0_FB

BUCK1_LX0

BUCK1_FB

BUCK2_LX0

BUCK2_LX1

BUCK2_FB

BUCK3_LX0

BUCK3_FB

BUCK3_IN

BUCK4_LX0

BUCK4_LX1

BUCK4_FB

BUCK4_IN

BUCK5_LX0

BUCK5_LX1

BUCK5_FB

BUCK3_SW1
BUCK3_SW2
BUCK3_SW3
BUCK3_SW4
BUCK3_SW5

BUCK4_SW1

BUCK6_SW1

BUCK8_SW1
BUCK8_SW2

81

B1
B2
B3

PVDDCPUAWAKE_SW0

SWITCH_NODE=TRUE
MIN_NECK_WIDTH=0.0750
MIN_LINE_WIDTH=0.6000
DIDT=TRUE

0.22UH-20%-6.7A-0.023OHM

D1
D2
D3

PVDDCPUAWAKE_SW1

SWITCH_NODE=TRUE
MIN_NECK_WIDTH=0.0750
MIN_LINE_WIDTH=0.6000
DIDT=TRUE

0.22UH-20%-6.7A-0.023OHM

F1
F2
F3

PVDDCPUAWAKE_SW2

SWITCH_NODE=TRUE
MIN_NECK_WIDTH=0.0750
MIN_LINE_WIDTH=0.6000
DIDT=TRUE

0.22UH-20%-6.7A-0.023OHM

H1
H2
H3

G5

P1
P2

R4

K1
K2
K3

M1
M2
M3

L5

C16
C17
C18

D14

R9
T10
T9
U10
U9
V10
V9

A8
B8

A6
B6

D7

P7

A10
B10

PVDDCPUAWAKE_SW3

SWITCH_NODE=TRUE
MIN_NECK_WIDTH=0.0750
MIN_LINE_WIDTH=0.6000
DIDT=TRUE

PVDDCPUAWAKE_FB

MIN_LINE_WIDTH=0.1000
MIN_NECK_WIDTH=0.1000

PVDDCPUSRAMAWAKE_SW0

SWITCH_NODE=TRUE
MIN_NECK_WIDTH=0.0750
MIN_LINE_WIDTH=0.6000
DIDT=TRUE

PVDDCPUSRAMAWAKE_FB

P0V8SLPDDR_SW0

SWITCH_NODE=TRUE
MIN_NECK_WIDTH=0.0750
MIN_LINE_WIDTH=0.6000
DIDT=TRUE

P0V8SLPDDR_SW1

SWITCH_NODE=TRUE
MIN_NECK_WIDTH=0.0750
MIN_LINE_WIDTH=0.6000
DIDT=TRUE

P0V8SLPDDR_FB

81

P1V8SLPS2R_SW0

SWITCH_NODE=TRUE
MIN_NECK_WIDTH=0.0750
MIN_LINE_WIDTH=0.6000
DIDT=TRUE

P1V8SLPS2R_FB

PP1V8_SLPS2R

P1V1SLPS2R_SW0

MIN_LINE_WIDTH=0.6000
MIN_NECK_WIDTH=0.0750
SWITCH_NODE=TRUE
DIDT=TRUE

P1V1SLPS2R_SW1

MIN_LINE_WIDTH=0.6000
MIN_NECK_WIDTH=0.0750
SWITCH_NODE=TRUE
DIDT=TRUE

P1V1SLPS2R_FB

P0V9SLPDDR_SW0

MIN_LINE_WIDTH=0.6000
MIN_NECK_WIDTH=0.0750
SWITCH_NODE=TRUE
DIDT=TRUE

0.47UH-20%-4.8A-0.034OHM

A12
B12

D12

T8
T11
V11
V8
R8

P6

R6

P13
R13

P0V9SLPDDR_SW1

MIN_LINE_WIDTH=0.6000
MIN_NECK_WIDTH=0.0750
SWITCH_NODE=TRUE
DIDT=TRUE

P0V9SLPDDR_FB

3 245

L7806

1UH-20%-3.8A-0.055OHM

CRITICAL

21

2016-COMBO

L7807

CRITICAL

21

PINA20121T-SM

L7808

CRITICAL

21

PINA20121T-SM

L7809

CRITICAL

21

PINA20121T-SM

R7806
R7807

NOSTUFF

L7810

1.0UH-20%-2.6A-0.095OHM

0805-COMBO

R7811

L7811

1UH-20%-4.7A-0.04OHM

2520

L7812

0.47UH-20%-4.8A-0.034OHM

0806-COMBO

R7812

0

L7813

1UH-20%-3.8A-0.055OHM

2016-COMBO

R7813

0

PLACE_NEAR=L7813.2:5MM

74

L7814

1UH-20%-3.8A-0.055OHM

2016-COMBO

L7815

0.47UH-20%-4.8A-0.034OHM

0806-COMBO

R7814

0

L7816

2016-COMBO

1UH-20%-3.8A-0.055OHM

L7817

0806-COMBO

R7816

0

NOSTUFF

PP1V8_AWAKE
PP1V8_SLPS2R_PMUVDDGPIO
TP_PMU_BUCK3SW3
TP_PMU_BUCK3SW4
PP1V8SW_VCCQIO_SSD0

TP_PP1V1_PMU_BUCK4SW1
TP_PMU_BUCK6SW1
TP_PMU_BUCK8SW1

TP_PMU_BUCK8SW2

0

0

PLACE_NEAR=L7810.2:5MM

21

1/20W0MF5% 0201

NOSTUFF

PLACE_NEAR=L7812.2:5MM

21

5% MF 02011/20W

21

5% 1/20W MF 0201

PLACE_NEAR=L7815.2:5MM

21

1/20W5% MF

PLACE_NEAR=L7816.2:5MM

21

5%

PLACE_NEAR=L7806.2:5MM

21

5% 1/20W

21

CRITICAL

21

CRITICAL

21

CRITICAL

21

CRITICAL

21

CRITICAL

21

CRITICAL

21

CRITICAL

21

CRITICAL

21

MF 02011/20W

CRITICAL

C7821

20UF

20%

2.5V

X6S-CERM

0402

CRITICAL

C7812

20UF

20%

2.5V

X6S-CERM

0402

MF 0201

PVDDCPUAWAKE_FB_XW

1/20W5%

MF 0201

CRITICAL

C7829

10UF

6.3V

CER-X6S

0402

CRITICAL

C7833

20UF

20%

2.5V

X6S-CERM

0402

CRITICAL

C7814

20UF

20%

2.5V

X6S-CERM

0402 0402

CRITICAL

C7839

20UF

20%

2.5V

X6S-CERM

0402

CRITICAL

C7845

20UF

20%

2.5V

X6S-CERM

0402

CRITICAL

C7846

20UF

20%

2.5V

X6S-CERM

0402

CRITICAL

C7816

20UF

0201

CRITICAL

20%

2.5V

X6S-CERM

0402

C7852

20UF

20%

2.5V

X6S-CERM

0402

CRITICAL

C7819

20UF

20%

2.5V

X6S-CERM

0402

Supplied Current

74 81

62

72 74

0.3A

0.3A

0.3A

BOM_COST_GROUP=T290

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

CRITICAL

C7822

20UF

20%

2.5V

X6S-CERM

0402

CRITICAL

C7811

20UF

20%

2.5V

X6S-CERM

0402

SM

CRITICAL

C7830

10UF

20%20%

6.3V

CER-X6S

0402

CRITICAL

C7834

20%

2.5V

X6S-CERM

0402

CRITICAL

C7815

20UF

20%

2.5V

X6S-CERM

CRITICAL

C7840

20UF

20%

2.5V

X6S-CERM

0402

CRITICAL

C78C2

20UF

20%

2.5V

X6S-CERM

0402

CRITICAL

C7847

20UF

20%

2.5V

X6S-CERM

0402

CRITICAL

C7817

20UF

20%

2.5V

X6S-CERM

0402

CRITICAL

C7853

20UF

20%

2.5V

X6S-CERM

0402

CRITICAL

C78C1

20UF

20%

2.5V

X6S-CERM

0402

CRITICAL

1

2

CRITICAL

1

2

XW7807

21

1

2

CRITICAL

1

2

CRITICAL

1

2

CRITICAL

1

2

1

2

CRITICAL

1

2

1

2

CRITICAL

1

2

1

2

CRITICAL

20%

2.5V
0402

20%

2.5V
0402

20%

2.5V
0402

20%

2.5V
0402

20%

2.5V
0402

20%

2.5V
0402

20%

2.5V
0402

1

2

1

2

1

2

1

2

1

2

1

2

1

2

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

C7855

C7823

20UF

X6S-CERM

C7827

20UF

X6S-CERM

C7835

20UF20UF

X6S-CERM

C78C3

20UF

X6S-CERM

C7841

20UF

X6S-CERM

C7848

20UF

X6S-CERM

C7854

20UF 20UF

X6S-CERM

SYNC_MASTER=X589_BIGSUR SYNC_DATE=03/16/2017

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

C7824

20UF

20%

2.5V

X6S-CERM

0402

C7828

20UF

20%

2.5V

X6S-CERM

0402

C7836

20UF

20%

2.5V

X6S-CERM

0402

C78C4

20UF

20%

2.5V

X6S-CERM

0402

C7842

20UF

20%

2.5V

X6S-CERM

0402

C7849

20UF

20%

2.5V

X6S-CERM

0402

20%

2.5V

X6S-CERM

0402

PMIC BUCKS AND SWs

Vout = 0.625V - 1.06V
Iout Max = 12.5A
F = 2MHz & 4MHz

PPVDDCPU_AWAKE

CRITICAL

1

C7825

20UF

20%

2

CRITICAL

1

2

2.5V

X6S-CERM

0402

C7813

20UF

20%

2.5V

X6S-CERM

0402

1

2

1

2

CRITICAL

C7826

20UF

20%

2.5V

X6S-CERM

0402

CRITICAL

C78C0

20UF

20%

2.5V

X6S-CERM

0402

Vout = 0.8V - 1.06V
Iout Max = 0.923A
F = 3MHz

PPVDDCPUSRAM_AWAKE

Vout = 0.82V
Iout Max = 3.93A
F = 3MHz

PP0V82_SLPDDR

CRITICAL

1

C7837

20UF

20%

2

1

2

2.5V

X6S-CERM

0402

PP1V8_SLPS2R

CRITICAL

1

C7843

20UF

20%

2

2.5V

X6S-CERM

0402

1

2

1

2

CRITICAL

C7838

20UF

20%

2.5V

X6S-CERM

0402

CRITICAL

C7844

20UF

20%

2.5V

X6S-CERM

0402

Vout = 1.8V
Iout Max = 1.5A
F = 3MHz

Vout = 1.1V
Iout Max = 1.4A
F = 3MHz

PP1V1_SLPS2R

CRITICAL

1

C7850

20UF

20%

2

2.5V

X6S-CERM

0402

1

2

CRITICAL

C7851

20UF

20%

2.5V

X6S-CERM

0402

Vout = 0.9V
Iout Max = 2.64A
F = 3MHz

PP0V9_SLPDDR

CRITICAL

1

C7856

20UF

20%

2

2.5V

X6S-CERM

0402

1

2

CRITICAL

C7818

20UF

20%

2.5V

X6S-CERM

0402

Apple Inc.

1

1

2

1

2

1

2

1

2

1

2

1

2

DRAWING NUMBER

051-05232

REVISION

BRANCH

PAGE

SHEET

74

D

74

74

C

74 81

B

74

74

A

SIZE

D

2.0.0

proto4b

78 OF 152

62 OF 86

8

67

35 4

2

1

D

www.laptoprepairsecrets.com

PP3V3_G3H

75

PP1V1_SLPS2R

74

PP3V3_G3H

75

PP1V8_SLPS2R

74

CRITICAL

1

C7903

0.1UF

10%

6.3V

2

X6S
0201

CRITICAL

1

C7904

0.1UF

10%

6.3V

2

X6S
0201

678

3 245

1

CRITICAL

OMIT_TABLE

U7800

CALPE-PMU

BGA

D

CRITICAL

1

C7909

0.1UF

10%

6.3V

2

X6S
0201

N11
N12

V3P3

LDO1_IN
LDO2_IN

SYM 1 OF 4

LDO_CORE

LDO0
LDO1LDO0_IN
LDO2
LDO3

HIO_SW_EN

HIO_SW

L8

V15
U15V14
U17U14
P8U16

N6

T13
U13
V13

LDO_CORE

PMU_LDO3_OUT

PD_HIO_PWR_EN

NC
NC
NC

PP0V8_SLPS2R
PP3V_G3H
PP1V2_AWAKE

1

C7914

2.2UF

20%

25V

2

X6S-CERM
0402

CRITICAL

1

C7906

2.2UF

20%

25V

2

X6S-CERM
0402

CRITICAL

1

C7905

2.2UF

20%

25V

2

X6S-CERM
0402

CRITICAL

LDO0 EDC = 110mA

74

LDO1 EDC = 2mA

74

LDO2 EDC = 200mA

74

C

B

A

PP3V3_G3H_RTC

75

PLACE_NEAR=U7800.V5:1MM

XW7903

SHORT-14L-0.1MM-SM

21

GND_PMU_VSS_RTC

MIN_LINE_WIDTH=0.4000
MIN_NECK_WIDTH=0.1000
VOLTAGE=0V

PP7902

P3MM

SM

1

PP

PLACE_NEAR=U7800.E4:1MM

XW7902

SHORT-14L-0.1MM-SM

21

GND_PMU_AVSS_B0

MIN_LINE_WIDTH=0.4000
MIN_NECK_WIDTH=0.1000
VOLTAGE=0V

PLACE_NEAR=U7800.J15:1MM

XW7901

SHORT-14L-0.1MM-SM

21

GND_PMU_AVSS_B8

MIN_LINE_WIDTH=0.4000
MIN_NECK_WIDTH=0.1000
VOLTAGE=0V

PP7901

P3MM

SM

1

PP

VIN RTC implementation
may change between
Desktops and Portables

A1
E1
E2

VSS_BUCK0

E3
A2
A3
J1
J2

VSS_BUCK02

J3
B5
A5

VSS_BUCK4
A13
B13

T16
T17
T18

D16
D17
D18

H16
H17
H18
M16
M17
M18

R11

E11
U11

V16

C13
C10

H15
J15
M15
T14

VSS_BUCK5

U1
U2

VSS_BUCK6

VSS_BUCK10

N1
N2

VSS_BUCK21

N3

VSS_BUCK37

B9
A9

VSS_BUCK45

VSS_BUCK78

VSS_BUCK89

V5

VSS_RTC

M9

AVSS_C
AVSS_S

PVSS_N
PVSS_S

T5

PVSS_SE
PVSS_SW

E4

VSSA_BUCK0

R5

VSSA_BUCK1_6/AVSS_SE

M4

VSSA_BUCK2
VSSA_BUCK3
VSSA_BUCK4_5
VSSA_BUCK7
VSSA_BUCK8/AVSS_W
VSSA_BUCK9
VSSA_BUCK10/AVSS_SW

XW7905

SM

21

U7800

CALPE-PMU

SYM 4 OF 4

PP3V3_G3H_PMU_VINRTC_R

CRITICAL

1

C7907

10UF

20%

6.3V

2

CER-X6S
0402

CRITICAL

OMIT_TABLE

BGA

VSS

CRITICAL

1

C7908

10UF

20%

6.3V

2

CER-X6S
0402

A4
A17
A18
B4
B15
C4
C5
C6
C7
C8
C9
C12
C15
D4
E15
E16
F4
F12
F16
G4
G12
G16
H4
H12
J4
J12
K4
K15
L15
N4
N15
P3
P4
P11
P15
R3
R15
T3
T15
U18
U3
U4
U5
U8
V1
V2
V17
V18

GND_CALPE_AVSS

CRITICAL

1

C7912

1UF

20%

6.3V

2

X6S-CERM
0201

MIN_LINE_WIDTH=0.6000
MIN_NECK_WIDTH=0.1000
VOLTAGE=3.3V

CRITICAL

1

C7913

1UF

20%

6.3V

2

X6S-CERM
0201

PLACE_NEAR=U7800.J12:1MM

XW7900

SHORT-14L-0.1MM-SM

2 1

T6
U6

H5
D11
P10
M14

81 78 64

VIN_RTC

VIN_RTC_E
VIN_RTC_N
VIN_RTC_S
VIN_RTC_W

IN

1

C7920

1500PF

10%

10V

2

X7R
0201

LDO_RTC

VOUT_RTC

VPUMP

V3P3_SW1
V3P3_SW2

PP3V3_G3H

75

1

C7921

0.1UF

10%

6.3V

2

X6S
0201

P1V1SLPDDR_RAMP
P1V1_SLPDDR_SOCFET_EN

V7

T7
U7

R10

N13
N10

LDO_RTC

PMU_VPUMP

U7901

SLG5AP1668V

CAP

ON S

1

VDD

TDFN8

GND

8

NOSTUFF

1

R7900

100K

5%
1/20W
MF
201

2

CRITICAL

1

C7902

0.01UF

10%

10V

2

X5R-CERM
0201

1.1V SLPDDR SWITCH

37

D

PP1V1_SLPS2R

52

Part : SLG5AP1668V
R(ON) : 7.8 mohm (Typical) , 9.6 mohm (max)
Current: 5.3A Max

CRITICAL

1

C7901

0.1UF

10%

6.3V

2

X6S
0201

PP1V1_SLPDDR

CRITICAL

1

C7911

0.1UF

10%

6.3V

2

X6S
0201

74

PP3V3_G3H

PP3V3_AWAKE
PP3V3_S5

CRITICAL

1

C7910

0.1UF

10%

6.3V

2

X6S
0201

74

BOM_COST_GROUP=T290

75

Max Current = 300mA

74

Max Current = 500mA

74

PAGE TITLE

PMIC LDOs

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=03/16/2017SYNC_MASTER=X589_BIGSUR

DRAWING NUMBER

051-05232

REVISION

2.0.0

BRANCH

proto4b

PAGE

79 OF 152

SHEET

63 OF 86

C

B

A

SIZE

D

8

67

35 4

2

1

D

www.laptoprepairsecrets.com

C

B

32

15

78 31 23

42

42

OUT

OUT

OUT

IN

BI

PMU_CLK32K_SOC
PMU_CLK32K_PCH

SOC_FORCE_DFU

I2C_PWR_SCL
I2C_PWR_SDA

Caution : AMUX programmed with Gain 1
should not have inputs greater than 1.5V

PP1V05_VCCST_OUT

1

R8012

R8010

33 33

5%

1/20W

MF

201

2.2K

1

R8011

5%
1/20W
MF

2

201

2

81 78 64 31 23

21

Use SOC's Internal Pull Up

R8080
R8081

0
0

21

1/20W

21

1/20W MF5%

PMU_XTAL1_R

CRITICAL

Y8001

32.768KHZ-20PPM-12.5PF

1

C8002

18PF

5%
25V

2

C0G-CERM
0201

57 39 14 8 6

1.60X1.00-SM

21

78 31

55 23

39 6

64 40 32

78 66 17 14

28

76

73 64 32 31

201 MF5%1/20W

32

0201

32

32

64 17

14

R8013

0

5%

1/20W

MF

0201

1

2

32

IN
IN
IN
IN

76

IN

OUT

IN

OUT

OUT
OUT

OUT

OUT

MF5%0201

IN
BI
OUT
OUT

PMU_VDDMAIN_ISENSE

45

PMU_MEM1V1_ISENSE

45

PMU_WLANBT_ISENSE

45

PMU_MEM0V6_ISENSE

45

PMU_LCDBKLT_ISENSE

45

PMU_CPU_VSENSE

45

PMU_NAND_VSENSE

45

PMU_VCCINAUX_VSENSE

45

TP_PMU_AMUX_AY
NC_PMU_AMUX_B0

45

PMU_VCCINAUX_ISENSE

45

NC_PMU_AMUX_B2

45

NC_PMU_AMUX_B3

45

NC_PMU_AMUX_B4

45

NC_PMU_AMUX_B5

45

NC_PMU_AMUX_B6

45

NC_PMU_AMUX_B7

45

TP_PMU_AMUX_BY

21

NOSTUFF

C8003

18PF

5%
25V
C0G-CERM
0201

678

SOC_WDOG
SOC_SOCHOT_L
UPC_PMU_RESET
PM_THRMTRIP_L
NC_GPU_THRMTRIP
PMU_COLD_RESET_L

PM_SLP_S3_L
PMU_ACTIVE_READY
PMU_CLK32K_SOC_R

PMU_CLK32K_PCH_R
PMU_CLK32K_WLANBT_R
NC_PMU_CLK32K_GNSS_R
TP_PMU_CLK32K

PMU_SYS_ALIVE
PMU_FORCE_DFU

PMU_INT_L
I2C_PMU_SCL_R

I2C_PMU_SDA_R

SPMI_CLK
SPMI_DATA
ALL_SYS_PWRGD
PCH_PWRBTN_L

1

R8018

1M

5%
1/20W
MF
201

2

CKPLUS_WAIVE=I2C_PULLUP
CKPLUS_WAIVE=I2C_PULLUP

PMU_XTAL1
PMU_XTAL2

64 6

CRITICAL

1

C8004

0.1UF

10%

6.3V

2

X6S
0201

IN

CPU_CATERR_L

PMU_VDD_MAX

NC
NC

F5

RESET_IN1

E5

RESET_IN2

K5

RESET_IN3

K6

RESET_IN4

N5

RESET_IN5

L13

RESET*

M12

SYS_SLEEP*

J5

ACTIVE_RDY

H6

CLKOUT0_32K

H7

CLKOUT1_32K

J7

CLKOUT2_32K

K7

CLKOUT3_32K

K8

CLKOUT4_32K

L11

SYS_ALIVE

D6

FORCE_DFU

L9

IRQ*

M11

SCL

L10

SDA

M8

SCLK

M7

SDATA

K11

SYS_ACTIVE

C11

SYS_BTN

A16

AMUX_A0

A15

AMUX_A1

A14

AMUX_A2

B14

AMUX_A3

C14

AMUX_A4

D15

AMUX_A5

E14

AMUX_A6

F14

AMUX_A7

J14

AMUX_AY

D13

AMUX_B0

E13

AMUX_B1

E12

AMUX_B2

F13

AMUX_B3

G13

AMUX_B4

G14

AMUX_B5

H14

AMUX_B6

H13

AMUX_B7

J13

AMUX_BY

N9

LS_BID1

M10

LS_BID2

V3

XTAL1

V4

XTAL2

L6

SYS_ERR*

N8

VDD_MAX

E6

VDD_OTP

(IPD)

(IPD)

(IPD)

(IPU)
(IPU)

CRITICAL

OMIT_TABLE

U7800

CALPE-PMU

BGA

SYM 3 OF 4

(IPU)
(IPU)

IREF

VREF

VDROOP

VDROOP_DET

CHG_CBC_ON

NCHG_INT

CHG_POK

VPWR_EN

LDO1_POK

PFN

VIN_BBAT

BUTTON1
BUTTON2

GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8

GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
GPIO20
GPIO21
GPIO22
GPIO23
GPIO24
GPIO25

L12

K12

L7

M5

D9
J6
L4

D5

M13

D8

V6

N7
M6

E9
E8
E7
F6
F7
F8
F9
F10
G10
G9
G8
G7
G6
H8
H9
J9
J8
K9
K10
J10
H10
H11
G11
F11
E10

PMU_IREF

PMU_VREF

CRITICAL

1

C8001

0.1UF

10%

6.3V

2

X6S
0201

PMU_DROOP_L

SOC_VDDCPU_SENSE
CHGR_CBC_ON

CHGR_INT_L
GND

PMU_PVDDMAIN_EN
PCH_RTC_RESET_L

NC

GND

PMU_ONOFF_L
PMU_RSLOC_RST_L

P3V3MAIN_PGOOD
NC_P3V3G3W_EN
NAND_MODE_1V2_EN
P5VG3S_EN
P5VG3S_PGOOD
P3V3G3S_EN
P1V8G3S_EN
CPUVR_PGOOD
VCCINAUX_PGOOD
PVCCST_EN
PVDDQ_EN
PVDDQ_PGOOD
AUD_PWR_EN
WLAN_PWR_EN
BT_PWR_EN
SE_PWR_EN
SENSOR_PWR_EN
PD_PVCCPLLOC_EN

PVCCNAND_EN
NAND_DISCHARGE_EN
NAND_RESET_L
UVP_DIS_L
TBT_PWR_EN
P1V1_SLPDDR_SOCFET_EN

1

R8001

200K

1%
1/20W
MF
201

2

OUT

IN

IN
IN
IN

OUT

OUT

75

IN
IN

3 245

64 31

35

56

56

76

60

18 15

To be Grounded on Portables Only, RC on Coin Cell on Desktops

78 64 55 49

81 78 64 55 53

PP3V3_G3H_RTC

64 75

NAND_MODE_1V2

1

R8040

100K

5%
1/20W

IN

OUT

OUT

IN
OUT
OUT

IN

IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

IN
OUT
OUT
OUT
OUT
OUT
OUT

60

76

60

60

66 64

81 78 66 64

57

59

66

81 78 66 65 64

78 65

78 49

30 29 28

30 29 28

41

66

76 64

76

76

76

76

76

67 64

81 78 63

MF
201

2

76 64

IN

PD_PVCCPLLOC_ENPVCCNAND_PGOOD

67 64

NOSTUFF

R8065

TBT_PWR_EN

IN

47K

5%

1/20W

MF

201

1

2

66 64

IN

P3V3G3S_EN

R8060

47K

5%

1/20W

MF

201

1

1

2

R8061

47K

5%

1/20W

MF

201

D

C

B

1

2

A

PP3V3_G3H_RTC

PP1V8_AWAKE
PP1V8_PRIM_PCH

PP1V8_SLPS2R

R8002
R8003

R8005
R8006
R8015
R8014
R8017

10K
10K

1K

10K
10K
10K

51

NOSTUFF

64 75

74

75

74

21

1/20W 5%201

21

21

21

1/20W 201 5%

21

21

1/20W MF5%201

21

1/20W

81 78 66 64

PMU_ACTIVE_READY

IN

81 78 66 65 64

81 78 64 31 23

PVDDQ_EN

IN

NOSTUFF

47K

5%
MF

201

1

2

R8062

1/20W

PPBUS_G3H

75

0.1%
TK

0201

0.1%
MF

0201

1

2

PMU_VDD_HI

1

2

OUT

62

BOM_COST_GROUP=T290

SYNC_MASTER=X589_BIGSUR

PAGE TITLE

PMIC GPIOs & Control

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

R8050

PMU_COLD_RESET_L

MF

2011/20W

201 MF5%1/20W

PMU_SYS_ALIVE

5% MF

ALL_SYS_PWRGD
PMU_DROOP_L

MF

PMU_ONOFF_L

5%2011/20W MF

PMU_RSLOC_RST_L
CPU_CATERR_L

MF201 5%

64 40 32

73 64 32 31

64 17

64 31

78 64 55 49

81 78 64 55 53

64 6

NOSTUFF

C8051

220PF

50V
C0G

0201

1

2%

2

887K

1/20W

R8051

357K

1/20W

IN

NOSTUFF

R8063

P1V8G3S_EN

1

47K

5%

1/20W

MF

201

2

DRAWING NUMBER

051-05232

REVISION

BRANCH

PAGE

80 OF 152

SHEET

64 OF 86

NOSTUFF

47K

5%
MF

201

1

2

R8064

1/20W

SYNC_DATE=03/16/2017

2.0.0

proto4b

A

SIZE

D

8

67

35 4

2

1

678

www.laptoprepairsecrets.com

3 245

1

D

C

A

VDD2 1.1V S3 Voltage Regulator

75

66

BYPASS=U8100.6::1mm

CRITICAL

10%
25V

0201

1

2

C8115

0.1UF

X6S-CERM

PP5V_G3S

P1V1_S3_EN

IN

1

R8111

3.57K

1%
1/20W
MF
201

2

PLACE_NEAR=U8100.19:3mm

P1V1REG_VREF_R

1

R8117

27.4K

0.1%
1/20W
MF
0201

2

CRITICAL

PLACE_NEAR=U8100.8:5mm

1

R8112

48.7K

0.1%
1/20W
MF
0201

2

CRITICAL

R8103

2.2

1/16W
MF-LF

21

5%

402

R8104

0

1/20W

5% 0201MF

MIN_LINE_WIDTH=0.1160
MIN_NECK_WIDTH=0.0750

21

R8115

BYPASS=U8100.8::1mm

1

C8116

0.01UF

10%

10V

2

X7R-CERM
0201

P1V1REG_AGND

MIN_LINE_WIDTH=0.1000
MIN_NECK_WIDTH=0.0750

PP1V1_S3

65 75

PP5V_G3S_P1V1REG

CRITICAL

C8103

2.2UF

20%
25V

X6S-CERM

0402

1

1K

5%

1/20W

MF

201

2

PLACE_NEAR=U8100.17:3mm

BYPASS=U8100.12::1mm

1

2

MIN_LINE_WIDTH=0.1160
MIN_NECK_WIDTH=0.0750

PLACE_NEAR=U8100.19:3mm

PD_P1V1_S3_EN
P1V1_S3_EN_R

P1V1REG_VREF

P1V1REG_REFIN
P1V1REG_MODE

P1V1REG_TRIP

1

R8113

47K

1%
1/20W
MF
201

2

1

R8114

40.2K

1%
1/20W
MF
201

2

PLACE_NEAR=U8100.18:3mm

CRITICAL

BYPASS=U8100.2::1mm

20%

6.3V
0402

V5IN

S3
S5

VREF

REFIN

MODE
TRIP

1

2

PGND GND

C8102

10UF

CER-X6S

17
16

6

8

19
18

2

VLDOIN

U8100

TPS51916

QFN

CRITICAL

7

10

SW

VTT

1512
14
13

11
20
9
3
1

5

VDDQSNS

VTTSNS

VTTREF

VTT THRM

GND PAD

4

21

VBST
DRVH

DRVL

PGOOD

PPVTT_VTTREF

2

XW8100

SM

1

PLACE_NEAR=U8100.21:1mm

MIN_LINE_WIDTH=0.1160
MIN_NECK_WIDTH=0.2000
DIDT=TRUE

2.2

5%

1/20W

MF

201

1

2

R8130

P1V1_VBST

MIN_LINE_WIDTH=0.1000
MIN_NECK_WIDTH=0.2000
DIDT=TRUE

P1V1_DRVH

MIN_LINE_WIDTH=0.1000
MIN_NECK_WIDTH=0.2000
GATE_NODE=TRUE
DIDT=TRUE

P1V1_SW

MIN_LINE_WIDTH=0.1000
MIN_NECK_WIDTH=0.2000
SWITCH_NODE=TRUE
DIDT=TRUE

MIN_LINE_WIDTH=0.1000
MIN_NECK_WIDTH=0.2000
GATE_NODE=TRUE
DIDT=TRUE

P1V1_S3_PGOOD

PVTT_S0_DDR_LDO

CRITICAL

1

C8140

0.22UF

10%

25V

2

X7R
0402

P1V1_BOOT_RC

65

CRITICAL

1

C8130

0.1UF

10%

25V

2

X6S-CERM
0201

R8133

1

5%
1/16W
MF-LF

402

R8132

1

5%
1/16W
MF-LF

402

P1V1_DRVH_R

21

MIN_LINE_WIDTH=0.1000
MIN_NECK_WIDTH=0.2000
GATE_NODE=TRUE
DIDT=TRUE

21

P1V1_DRVL_RP1V1_DRVL

MIN_LINE_WIDTH=0.1000
MIN_NECK_WIDTH=0.2000
GATE_NODE=TRUE
DIDT=TRUE

PPVIN_G3H_P1V1_S3

46 75

CSD58873Q3D

3

TG

4

TGR

5

BG

P1V1_SNS

CRITICAL

Q8100

Q3D

VSW

9

R8141

VIN

PGND

C8110

0.001UF

10

5%

1/20W

MF

201

1

6
7
8

NOSTUFF

10%

50V

X7R-CERM

0402

21

P1V1_SNS_R

MIN_LINE_WIDTH=0.1160
MIN_NECK_WIDTH=0.0600

P1V1_PHASE

MIN_LINE_WIDTH=0.1000
MIN_NECK_WIDTH=0.0750

NOSTUFF

1

R8110

2.2

5%
1/16W
MF-LF
402

2

P1V1_LL_SNUB

DIDT=TRUE

1

2

CRITICAL

1

C8100

33UF

20%
16V

2

TANT
CASED12-SM

CRITICAL

1

C8101

2.2UF

20%
25V

2

X6S-CERM
0402

152S00239

CRITICAL

L8100

0.68UH-20%-14.5A-0.009OHM

PILA052D-SM

XW8110

SM

21

PLACE_NEAR=C8107.1:1mm

E

Bleeder Circuits

CRITICAL

1

C8104

2.2UF

20%
25V

2

X6S-CERM
0402

D

Vout = 1.1V
Iout Max = 5.01A
F = 400 KHZ

21

CRITICAL

1

C8105

330UF

20%

2.5V

2

TANT
CASE-B2-SM1

CRITICAL

1

C8106

330UF

20%

2.5V

2

TANT
CASE-B2-SM1

CRITICAL

1

C8107

330UF

20%

2.5V

2

TANT
CASE-B2-SM1

PP1V1_S3

CRITICAL

1

C8112

10UF

20%

6.3V

2

CER-X6S
0402 0402

1

2

CRITICAL

C8113

10UF

20%

6.3V
CER-X6S

65 75

C

B

B

78 66 65 64

81

65

VDDQ 0.6V S3 Voltage Regulator

PP1SR3V3_G3H_P0V6_S3_VIN

45 75

PVDDQ_EN

1

R8191

10K

5%
1/20W
MF
201

2

R8154

0

P1V1_S3_PGOOD P0V6_S3_EN

1/20W5% 0201

21

MF

R8155

0

21

P0V6_S3_SKIP

0201MF1/20W5%

P0V6_S3_SS
P0V6_S3_FB

65

P0V6_S3_COMP

1%

1/20W

MF

201

10%
16V
X7R

0201

1

2

P0V6_S3_COMP_RC

1

2

C8154

0.015UF

10%
16V

X7R-CERM

0402

R8153

6.81K

5%
25V
C0G

0201

1

2

C8152

2700PF

C8153

47PF

1

2

B2

B3

C2

C1

B1

SKIP

EN

SS/REFIN

FB

COMP

U8150

MAX15053B

BGA

CRITICAL

GND

A1

A3

IN

LX

PGOOD

A2

C3

P0V6_S3_SW
PVDDQ_PGOOD

Vout = 0.6*(1+Ra/Rb) = 0.606V

CRITICAL

1

C8150

10UF

20%

6.3V

2

CER-X6S
0402

DIDT=TRUE

OUT

P0V6_S3_SNUB

CRITICAL

1

C8151

10UF

20%

6.3V

2

CER-X6S
0402

78 65 64

1

R8159

1

2

1

2

NOSTUFF

5%
1/16W
MF-LF
402

NOSTUFF

C8159

0.001UF

10%
50V
X7R-CERM
0402

CRITICAL

1

C8160

10UF

20%

6.3V

2

CER-X6S CER-X6S
0402

CRITICAL

1

C8161

10UF

20%

6.3V

2

0402

CRITICAL

L8150

1UH-20%-4.7A-0.04OHM

21

2520

152S00344

XW8150

P0V6_S3_FB_TOP

P0V6_S3_FB_R

P0V6_S3_FB

65

1

2

SM

R8150

10

5%

1/20W

MF

201

<Ra>

R8151

90.9

1%

1/20W

MF

201

<Rb>

R8152

10K

1%

1/20W

MF

201

CRITICAL

C8163

10UF

20%

6.3V
CER-X6S
0402

2

1

1

2

1

2

1

2

CRITICAL

1

C8164

10UF

20%

6.3V

2

CER-X6S
0402

CRITICAL

1

C8155

330UF

20%

2.5V

2

TANT
CASE-B2-SM1

NOSTUFF

CRITICAL

1

C8162

100UF

20%

6.3V

2

POLY-TANT
CASE-A3

CRITICAL

1

C8156

10UF

20%

6.3V

2

CER-X6S
0402

Vout = 0.6V
Iout Max = 0.52A
F = 1 MHZ

PP0V6_S3

CRITICAL

1

C8157

10UF

20%

6.3V

2

CER-X6S
0402

65 75

81
66

PVDDQ_EN

64
65
78

79 78 75

R8171

1/20W5%

65 75

PP3V3_G3H

0

21

MF 0201

PP1V1_S3

1

2

R8170

100K

1/20W5%

MEM_BLDR_EN

R8194

10

1/8W
TF
0402

DMN5L06VK-7

1

2

21

201MF

DMN5L06VK-7

Q8170

SOT563

VER-3

2

R8195

10

5%5%
1/8W
TF

Q8180

SOT563

VER-3

2

D

SG

PP0V6_S3

65 75

6

D

SG

1

1

R8196

10

5%
1/8W
TF
04020402

2

P1V1_BLDR_L

6

1

MEM_BLDR

65

1

R8197

10

5%
1/8W
TF
0402

2

DMN5L06VK-7

1

2

DMN5L06VK-7

Q8170

SOT563

VER-3

5

1

R8198

1K

1%
1/16W
MF-LF
402

2

Q8180

SOT563

VER-3

5

R8175

10

5%
1/8W
TF
0402

MEM_BLDR_L

3

D

SG

4

PP1V8_S3

1

2

P1V8_BLDR_L

3

D

SG

4

1

R8176

10

5%
1/8W
TF
0402

2

R8199

1K

1%
1/16W
MF-LF
402

65
19
20
74

B

A

Protection DiodesC

To ensure higher voltage rails
remain above lower voltage rails

PP1V1_S3

19 20 65 75

8

CRITICAL

K

D8100

PMEG3010EB/S500

A

PP1V8_S3

CRITICAL

K

D8101

SOD523SOD523

PMEG3010EB/S500

A

19 20 65 74

PP0V6_S3

19 20 75

CRITICAL

K

D8102

SOD523

PMEG3010EB/S500

A

67

PP1V1_S3

CRITICAL

K

D8103

SOD523

PMEG3010EB/S500

A

19 20 65 75

D

PVDDQ PGOOD

PP1V8_S3

19 20 65 74

1

R8190

100K

5%
1/20W
MF
201

2

PVDDQ_PGOOD

OUT

MEM_BLDR

65

78 65 64

BOM_COST_GROUP=PLATFORM POWER

35 4

SYNC_MASTER=X589_CPU_CNL_Y

PAGE TITLE

POWER - MEMORY VRs

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

2

SYNC_DATE=10/12/2018

DRAWING NUMBER

051-05232

REVISION

2.0.0

BRANCH

proto4b

PAGE

81 OF 152

SHEET

65 OF 86

1

A

SIZE

D

678

www.laptoprepairsecrets.com

3 245

1

D

A 3.3V G3 Standby Switch

PP3V3_G3H

75

BYPASS=U8210::5mm

1

C8211

0.1UF

10%

10V

2

X5R-CERM
0201

PP3V3_G3H_RTC
PP3V3_G3S

Part
R(on)

@ 3.6V 8.5 mOhm Max

C8210

4700PF

10%

10V

X7R
201

1

VDD

U8210

SLG5AP1445V

P3V3G3S_SS

64

IN

1

2

P3V3G3S_EN

CAP

ON S

TDFN8

GND

8

37

D

52

75

75

SLG5AP1445V

7.8 mOhm Typ

B C

1.8V G3 Standby Switch

PP3V3_G3H

75

BYPASS=U8220::5mm

1

C8221

1

VDD

U8220

0.1UF

10%

10V

2

X5R-CERM
0201

SLG5AP1445V

C8220

4700PF

10%

10V

X7R
201

P1V8G3S_SS

64 66 78 81

IN

1

2

P1V8G3S_EN

CAP

ON S

TDFN8

GND

8

37

D

52

PP1V8_SLPS2R
PP1V8_G3S

Part
R(on)

@ 3.6V

74

75 66

SLG5AP1445V

7.8 mOhm Typ

8.5 mOhm Max

3.3V Sensors Switch

PP3V3_G3H

75

1

1

2

PP3V3_G3H
PP3V3_G3SSW_SNS

C8225

4700PF

10%

10V

X7R
201

VDD

U8225

SLG5AP1445V

P3V3SEN_SS

64

IN

1

2

SENSOR_PWR_EN

CAP

ON S

TDFN8

GND

8

37

D

52

BYPASS=U8225::5mm

C8226

0.1UF

10%

10V

X5R-CERM
0201

Part
R(on)

@ 3.6V

D

75

75

SLG5AP1445V

7.8 mOhm Typ

8.5 mOhm Max

C

B

EG: Check load current & shrink switch?

D

1.8V S3 Switch

U8250

TPS22916

DSBGA

75 12 9

64 65 66
78 81

IN

PP1V8_PRIM_PCH
PVDDQ_EN

A2

B2

VIN

ON

GND

B1

1.05V VCCST Switch ControlG

74 66

PP1V05_PCH_CPU

14

IN

1 2

10%

6.3V

0201

1

2

C8237

0.1UF

CERM-X5R

VCCST_OVERRIDE

NC

VCCA

SN74AUP1T34

A

5

NC

PP3V3_S5

6

1

VCCB

U8236

SON

GND

3

C8236

0.1UF

CERM-X5R

42

B

A1

VOUT

10%

6.3V

0201

1

2

PP1V8_S3_FET_R

VOLTAGE=1.8V

16

IN

64

IN

14 17 64 66 78

IN

VCCST_OVERRIDE_3V3

9 59

IN

9 59

IN

R8250

1/4W
0603

74 66 18

74 66 18

XDP_PRESET_L

PVCCST_EN

PM_SLP_S3_L

PCH_CORE_VID0

PCH_CORE_VID1

1/20W MF5% 0201

1/20W 02015%

74 66 18

Current

0

21

PP1V8_S3

0%
MF

PP3V3_S5

NOSTUFF

R8233

0

R8231

0

PP3V3_S5

4A Max

C8231

0.1UF

CERM-X5R

21

21

MF

C8232

0.1UF

CERM-X5R

66
74

1

10%

6.3V

2

0201

3

PVCCST_EN_R

1

10%

6.3V

2

0201

6

1

561

3

E 1.1V S3 En

PP3V3_G3H

75

5

64 65 66 78
81

74 66

U8231

74AUP1T97

SOT891

4

2

U8232

5

74AUP1T97

SOT891

4

2

PVDDQ_EN

PP1V8_S3

VCCST_EN_B

VCCST_EN_C

6

132

U8235

5

3

B

1

A

6

C

74LVC1G332

SOT891

Y

2

U8251

74AUP1T97

SOT891

4

P1V1_S3_EN

PLACE_NEAR=U8235.5:2MM

1

C8235

0.1UF

10%

6.3V

2

CERM-X5R
0201

4

P1V05_VCCST_EN

Vmax

1.05V

F CPU Switches

74

65

OUT

14 17 64 66

IN

78

14 17

IN

VCCSTGH

PP1V05_PCH_CPU

66

17
66

ICL-Y PCH Output Range

U0500.BV6

VCCST_OVERRIDE

74

VOH = +0.85V

Current

PP3V3_S5

BYPASS=U8245::2MM

PM_SLP_S3_L

CPU_C10_GATE_L

Vmax

3.6V

1

4A Max

VCCPLL_OC has turn-on requirement of
11uS min and 240uS max
from EN to 1.1V

10%

6.3V

0201

1

2

NC

VCC

2

A Y

AND

1

B

5

NC

GND

U8243

74AUP1G08GF

6

SOT891

3

4

P1V1S0SW_FET_EN_R

NOSTUFF

1

R8243

100K

5%
1/20W
MF
201

2

R8241

C8243

0.1UF

CERM-X5R

R8242

R8256

0

21

5%1/20W MF

NOSTUFF

PP1V05_S0_VCCSTG

0201

8 11

U8236 A Input Range

VCCST_OVERRIDE

2

VIH = +0.6825V

Current

1.1V S0SW VCCPLL_OC Switch

PP3V3_S5

74

0

5%

1/20W

MF

0201

0

5%

1/20W

MF

0201

BYPASS=U8240::2MM

10%

6.3V

0201

1

1

2

VDD

U8240

C8240

0.1UF

CERM-X5R

SLG5AP1635V

P1V1S0SW_RAMP
P1V1S0SW_FET_EN

1

2

1

C8242

100PF

5%

25V

2

C0G
0201

CAP

ON

STDFN

CRITICAL

GND

8

37

D

52

S

Part
Type

2

R(on)
@ 3.3V

1

Current

PP1V1_S3

BYPASS=U8240::2MM

1

C8241

1.0UF

20%

6.3V

2

X5R
0201-1

PP1V1_S0SW_CPU_VCCPLL_OC

MIN_LINE_WIDTH=0.7000
VOLTAGE=1.1V

EDP: 90MA

U8240

SLG5AP1635V
Load Switch

27.5 mOhm Typ
31 mOhm Max

2.5A Max

1.8V S0 CPU Switch

PP1V8_PRIM_PCH

75

U8245

TPS22930

CSP

NOSTUFF

C8244

0.1UF

10%
X6S

0402

25V

BYPASS=U8210::2MM

1

2

C8245

1.0UF

20%

6.3V

X5R

0201-1

A2

VIN

B2

ON

1

2

VOUT

GND

B1

A1

PP1V8_S0SW_CPU

MIN_LINE_WIDTH=0.4000
MIN_NECK_WIDTH=0.0750
VOLTAGE=1.8V

MAKE_BASE=TRUE

EDP: 500mA

Part
Type
R(on)

@ 1.8V
Current

8 11

U8245

TPS22930
Load Switch
49 mOhm Typ

62 mOhm Max
2A Max

4A Max

75

C

8 11

B

A

I 1.05V VCCST Switch

U8230

TPS22924B

CSP

VIN

GND

C1

P1V05_VCCST_EN

17 66

74 66

R8230

5% MF002011/20W

PP1V05_PCH_CPU

21

P1V05_VCCST_EN_R

10%

25V

X6S

0402

1

2

C8238

0.1UF

BYPASS=U8210::2MM

C8230

1.0UF

20%

6.3V

X5R

0201-1

A2
B2

C2

ON

1

2

VOUT

VOLTAGE=1.05V

A1

PP1V05_S0_CPU_VCCST

B1

EDP: 300MA

8 11 17 39 78

U8230

Part
Type
R(on)

@ 2.5V
Current 2A Max

TPS22924
Load Switch

18.5 mOhm Typ

25.8 mOhm Max

J

VOL = +0.21V

0V

0V

PP1V8_G3S Discharge

PP3V3_G3H

75

1

R8271

100K

5%
1/20W
MF
201

2

R8270

0

64 66 78 81

P1V8G3S_EN

IN

21

0201MF1/20W 5%

DMN5L06VK-7

P1V8G3S_DSCHG_EN_L

Q8270

SOT563

VER-3

2

6

D

SG

1

VIL = +0.3675V

NOSTUFF

1

C8270

47PF

5%
25V

2

C0G
0201

DMN5L06VK-7

Q8270

SOT563

VER-3

P1V8G3S_DSCHG_EN

PP1V8_G3S

1

R8272

10

5%
1/16W
MF-LF
402

2

75 66

P1V8_G3S_DSCHG

3

D

5

SG

4

BOM_COST_GROUP=PLATFORM POWER

This discharge circuit was added to enforce timing
compliance to a spec for Venus (SE) that NXP
provided that would confirm a hardware reset
sequence will be power down compliant..

SYNC_MASTER=X589_CPU_CNL_Y SYNC_DATE=02/22/2017

PAGE TITLE

Power FETs

DRAWING NUMBER

051-05232

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

REVISION

2.0.0

BRANCH

proto4b

PAGE

82 OF 152

SHEET

66 OF 86

A

SIZE

D

8

67

35 4

2

1

678

www.laptoprepairsecrets.com

3 245

1

3.3V S0SW TBT Switch

BSB_X_PWR:VOUTLV_SW_CALPE

D

C

PP3V3_G3H

67 75

67 64

24 23

IN

27 24

IN

TBT_PWR_EN

PP3V3_UPC_X_VOUTLV

UPC_X_FORCE_PWR

78 27

PP3V3_TBT_X_SX

BSB_X_PWR:VOUTLV_SW_CALPE

BSB_X_PWR:SWSW_VOUTLV

(Bii)

BSB_X_PWR:SWSW_FORCEPWR

R8308

0

21

5%

1/20W

MF

0201

(A)

R8306

0

5%

1/20W

MF

0201

(Bi)

R8307

0

5%

1/20W

MF

0201

R8300

0

5%

1/20W

MF

0201

21

OMIT_TABLE

PP3V3_TBT_X_SW

R8301

0

21

5%

1/20W

MF

0201

117S0201 BSB_X_PWR:SWSW_VOUTLV

1
1117S0201

RES,MF,1A MAX,0.0 OHM,5%,0201,BLACK

RES,MF,1A MAX,0.0 OHM,5%,0201,BLACK

R8301
R8301

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

BSB_X_PWR:SWSW_FORCEPWR

Pin 1 on SLG5AP1756V is a comparator input.

20%

6.3V
X5R

1

2

7

1

U8300

SLG5AP1756V

CAP

ON

CMP

TDFN

CRITICAL

GND

8

3

D

52

S

PP3V3_TBT_X_S0_R

C8300

1.0UF

0201-1

P3V3TBT_X_RAMP

21

21

TBT_X_S0_PWR_EN

R8302

100K

5%

1/20W

MF

201

1

2

1

C8301

4700PF

10%
10V

2

X7R
201

It is used to sense the presense of the SX rail.

79 78 27

U8200

Part
Type
R(on)

Current

SLG5AP1756V
Load Switch

7.8 mOhm Typ
TBD mOhm Max@ 4A

4A Max

D

C

B

PP3V3_G3H

67 75

(C)

PP3V3_TBT_T_SX

27

3.3V S0SW TBT Switch

BSB_T_PWR:VOUTLV_SW_CALPE

R8320

0

5%

1/20W

MF

0201

21

OMIT_TABLE

PP3V3_TBT_T_SW

R8321

0

5%

1/20W

MF

0201

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

117S0201

21

117S0201 BSB_T_PWR:SWSW_FORCEPWR1

RES,MF,1A MAX,0.0 OHM,5%,0201,BLACK

RES,MF,1A MAX,0.0 OHM,5%,0201,BLACK

R8321
R8321

BSB_T_PWR:SWSW_VOUTLV1

B

67 64

25 23

IN

27 25

IN

TBT_PWR_EN

PP3V3_UPC_T_VOUTLV

UPC_T_FORCE_PWR

BSB_T_PWR:VOUTLV_SW_CALPE

BSB_T_PWR:SWSW_VOUTLV

(Bii)

BSB_T_PWR:SWSW_FORCEPWR

R8328

0

21

5%

1/20W

MF

0201

(A)

R8326

0

5%

1/20W

MF

0201

(Bi)

R8327

0

5%

1/20W

MF

0201

20%

6.3V
X5R

1

Pin 1 on SLG5AP1756V is a comparator input.

2

7

1

U8320

SLG5AP1756V

CAP

ON

CMP

TDFN

CRITICAL

GND

8

3

D

52

S

It is used to sense the presense of the SX rail.

PP3V3_TBT_T_S0_R

27

U8220

Part
Type
R(on)

SLG5AP1756V
Load Switch

7.8 mOhm Typ

@ 4A TBD mOhm Max
Current

4A Max

C8320

1.0UF

0201-1

P3V3TBT_T_RAMP

21

21

TBT_T_S0_PWR_EN

R8322

100K

5%

1/20W

MF

201

1

2

1

C8321

4700PF

10%
10V

2

X7R
201

A

8

67

(C)

SYNC_MASTER=CPU_CARD_ICL_Y

PAGE TITLE

SYNC_DATE=06/08/2018

A

Power FETs TBT S0

DRAWING NUMBER

051-05232

Apple Inc.

REVISION

2.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=PLATFORM POWER

35 4

IV ALL RIGHTS RESERVED

2

BRANCH

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PAGE

83 OF 152

SHEET

67 OF 86

1

SIZE

D

678

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3 245

1

D

C

Page Notes

Power aliases required by this page:

- =PPVIN_S0SW_LCDBKLTFET (9-12.6V LCD BACKLIGHT INPUT)

- =PP5V_S0_BKLT (5V BACKLIGHT DRIVER INPUT)

CRITICAL

F8400

3AMP-32V

PPBUS_G3H

75

PLATFORM_RESET NO LONGER GATES THE BKLT_EN AS BOTH COME FROM PCH NOW

740S0159

68

0603

21

PPVIN_S0SW_LCDBKLT_F

46

46

OUT

OUT

ISNS_LCDBKLT_P

ISNS_LCDBKLT_N

78 5

IN

107S00034

R8400

0.025

1%
1W
MF

0612-1

2 1

4

EDP_BKLT_EN

78

PPVIN_S0SW_LCDBKLT_R

68

3

1

C8400

1000PF

10%

16V

2

X7R-1
0201

1

R8402

63.4K

1%
1/16W
MF-LF
402

2

GND_BKLT_SGND

68

CRITICAL

Q8400

FDC638APZ_SBMS001

SSOT6-HF

4

1

R8401

80.6K

1%
1/16W
MF-LF
402

2

68 75

PP5V_G3S

3

R8444

10

1%
1/16W
MF-LF

PLACE_NEAR=U8400.5:5MM

C8440

GND_BKLT_SGND

68

1

R8440

1M

5%
1/20W
MF
201

2

BKLT_SENSE_OUT

R8442

0

5%

1/20W

MF

0201

21

BKLT_EN_R

NOSTUFF

1

C8442

33PF

5%

25V

2

NP0-C0G
0201

6
5
2
1

LCDBKLT_EN_L

1

2

402-1

1UF

10%
X5R

1

2

68

68

PPVIN_S0SW_LCDBKLT

68

MIN_LINE_WIDTH=2.0000
MIN_NECK_WIDTH=0.2000

VOLTAGE=12.9V

MAKE_BASE=TRUE

NOSTUFF

1

C8401

0.001UF

10%

50V

2

X7R-CERM
0402

1

R8445

10

1%
1/16W
MF-LF
402402

2

PP5V_S0_BKLT_A
PP5V_S0_BKLT_D

1

C8441

1UF

10%

10V10V

2

X5R
402-1

PLACE_NEAR=U8400.18:5MM

LP8548B1SQ_-04

BKLT_SD

11

9

10

19

17
12

15
16

SD
VSENSE_N
VSENSE_P

SENSE_OUT

EN
PWM_KEYB

SCL

(IPU)

SDA

(IPU)

CRITICAL

5

18

VDDA

VDDD

U8400

LLP

ISET_KEYB

KEYB1
KEYB2

353S4160

SW
SW
FB
GD

SW2
FB2

1

C8413

12PF

5%

25V

2

CERM
0201

CRITICAL

1

C8410

4.7UF

10%

25V

2

X6S-CERM
0603

PLACEMENT_NOTE:

SANDWICH C8410 AND C8411

PLACE_NEAR=L8410.1:5MM

SANDWICH C8410 AND C8411

PLACE_NEAR=L8410.1:5MM

R8410

DIDT=TRUE
SWITCH_NODE=TRUE

VOLTAGE=55V

MIN_NECK_WIDTH=0.2000
MIN_LINE_WIDTH=2.0000

2

LCDBKLT_SW

1
21

LCDBKLT_FB

4

LCDBKLT_FET_DRV

20

13
14

6
8

GATE_NODE=TRUE
DIDT=TRUE

NC
NC

NC
NC

NC

10

5%
1/16W
MF-LF

402

1

C8414

3PF

+/-0.1PF

25V

2

C0G
0201

152S00253

CRITICAL

15UH-20%-1.9A-0.24OHM

PIME062D-SM

CRITICAL

1

C8411

4.7UF

10%

25V

2

X6S-CERM
0603

PLACE_NEAR=L8410.1:5MM

21

LCDBKLT_FET_DRV_R

GATE_NODE=TRUE
DIDT=TRUE

68

1

C8412

0.1UF

10%

25V

2

X5R
402

L8410

PLACE_NEAR=Q8401.5:3MM

21

PPVIN_SW_LCDBKLT_SW

68

NOSTUFF

1

C8402

12PF

5%

100V

2

C0G
0201

5

CRITICAL

Q8401

4

SI7812DN

PWRPK-1212-8

PLACE_NEAR=U8400.1:3MM

321

PLACE_NEAR=L8410.2:3MM

371S00077

CRITICAL

D8410

SOD123-COMBO

KA

PMEG10020ELR-DFLS2100

XW8410

PLACE_NEAR=D8410::2MM

PPVOUT_S0_LCDBKLT_F

68

PLACE_NEAR=D8410.K:5MM

CRITICAL

1

C8460

2.2UF

10%

100V

2

X5R-CERM
1206

PLACE_NEAR=D8410.K:5MM

CRITICAL

1

C8465

2.2UF

10%

100V

2

X5R-CERM
1206

2

SM

1

PLACE_NEAR=D8410.K:5MM

CRITICAL

1

C8470

2.2UF

10%

100V

2

X5R-CERM
1206

LCDBKLT_TB_XWR

1

R8431

18.2K

1%
1/16W
MF-LF
402

2

1

R8432

150K

1%
1/16W
MF-LF
402

2

FERR-470-OHM-0.2A

PLACE_NEAR=D8410.K:5MM

CRITICAL

1

C8461

2.2UF

10%

100V

2

X5R-CERM
1206

PLACE_NEAR=D8410.K:5MM

CRITICAL

1

C8466

2.2UF

10%

100V

2

X5R-CERM
1206

PLACE_NEAR=D8410.K:5MM

CRITICAL

1

C8471

2.2UF

10%

100V

2

X5R-CERM
1206

1

C8476

3PF

+/-0.1PF

100V

2

C0G
0201

PLACE_NEAR=D8410.K:5MM

CRITICAL

1

C8462

2.2UF

10%

100V

2

X5R-CERM
1206

PLACE_NEAR=D8410.K:5MM

CRITICAL

1

C8467

2.2UF

10%

100V

2

X5R-CERM
1206

PLACE_NEAR=D8410.K:5MM

CRITICAL

1

C8472

2.2UF

10%

100V

2

X5R-CERM
1206

1

C8477

12PF

5%

100V

2

C0G
0201

NOSTUFF

1

C8432

100PF

5%

100V

2

C0G-CERM
0603

L8420

21

0402

OMIT_TABLE

PLACE_NEAR=D8410.K:5MM

CRITICAL

1

C8463

2.2UF

10%

100V

2

X5R-CERM
1206

PLACE_NEAR=D8410.K:5.1MM

CRITICAL

1

C8468

2.2UF

10%

100V

2

X5R-CERM
1206

PLACE_NEAR=D8410.K:5MM

CRITICAL

1

C8473

2.2UF

10%

100V

2

X5R-CERM
1206

1

C8478

3PF

+/-0.1PF

100V

2

C0G
0201

PPVOUT_S0_LCDBKLT

PLACE_NEAR=D8410.K:5MM

CRITICAL

1

C8464

2.2UF

10%

100V

2

X5R-CERM
1206

PLACE_NEAR=D8410.K:5.1MM

CRITICAL

1

C8469

2.2UF

10%

100V

2

X5R-CERM
1206

PLACE_NEAR=D8410.K:6.1MM

1

C8474

12PF

5%

100V

2

CERM
0402

1

C8479

12PF

5%

100V

2

C0G
0201

PLACE_NEAR=D8410.K:6.1MM

1

C8475

12PF

5%

100V

2

CERM
0402

Vout = 46V Typ, 55V Max
Iout = 0.12A Typ, 0.15A Max
Fs = 625kHz Typ (+/- 7%)

78 69 68

D

C

B

GND_BKLT_SGND

68

PP5V_G3S

68 75

1

R8452

1.8K

5%
1/20W
MF
201

2

78 69

78 69

I2C ID DEDICATED.ONLY CONNECTS TO JERRY

IN

BI

I2C_BKLT_SCL

I2C_BKLT_SDA

1

R8453

1.8K

5%
1/20W
MF
201

2

R8451

1/20W

0201

0

5%
MF

UNUSED_LP8548_PWM

1

R8447

10K

5%
1/20W
MF
201

2

PLACE_NEAR=U8400.15:10MM

R8450

0

5%

1/20W

MF

0201

21

PLACE_NEAR=U8400.16:10MM

CKPLUS_WAIVE=I2C_PULLUP

I2C_BKLT_SCL_R

21

CKPLUS_WAIVE=I2C_PULLUP

I2C_BKLT_SDA_R

GND_SW

GND_SW

GND_SW2

7

24

23

XW8400

SM

GNDD

3

THRM

GNDA

22

21

PAD

25

GND_BKLT_SGND

MIN_LINE_WIDTH=0.4000
MIN_NECK_WIDTH=0.2000

VOLTAGE=0V

68

116S0004

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

RES,MTL FILM,0 OHM,1A MAX,0402,SMD

1 L8420

B

TABLE_5_HEAD

BOM OPTIONCRITICAL

TABLE_5_ITEM

A

8

LINE WIDTHS

PP5V_S0_BKLT_A

MIN_LINE_WIDTH=0.0750
MIN_NECK_WIDTH=0.0750

VOLTAGE=5V

PP5V_S0_BKLT_D

MIN_LINE_WIDTH=0.0750
MIN_NECK_WIDTH=0.0750

VOLTAGE=5V

68

68

67

PBUS LINE WIDTHS

MIN_LINE_WIDTH=2.0000
MIN_NECK_WIDTH=0.2000

VOLTAGE=12.9V

PPVIN_S0SW_LCDBKLT_R

MIN_LINE_WIDTH=2.0000
MIN_NECK_WIDTH=0.2000

VOLTAGE=12.9V

PPVIN_S0SW_LCDBKLT

MIN_LINE_WIDTH=2.0000
MIN_NECK_WIDTH=0.2000

VOLTAGE=12.9V

68

68

LCDBKLT_FET_DRVPPVIN_S0SW_LCDBKLT_F

MIN_LINE_WIDTH=0.6000
MIN_NECK_WIDTH=0.2000

VOLTAGE=5V

78 68

GATE_NODE=TRUE

DIDT=TRUE

LCD BKLT LINE WIDTHS

PPVIN_SW_LCDBKLT_SW

MIN_LINE_WIDTH=2.0000
MIN_NECK_WIDTH=0.1200

VOLTAGE=55V

SWITCH_NODE=TRUE

PPVOUT_S0_LCDBKLT

MIN_LINE_WIDTH=0.5000
MIN_NECK_WIDTH=0.1500

VOLTAGE=55V

I351

PPVOUT_S0_LCDBKLT_F

MIN_LINE_WIDTH=0.5000
MIN_NECK_WIDTH=0.1500

VOLTAGE=55V

DIDT=TRUE

68 68

68

SYNC_MASTER=X1032_MLB_P4BP

PAGE TITLE

SYNC_DATE=02/13/2017

A

LCD Backlight Driver

78 69 68

DRAWING NUMBER

051-05232

Apple Inc.

REVISION

2.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=DISPLAY

35 4

IV ALL RIGHTS RESERVED

2

BRANCH

proto4b

PAGE

84 OF 152

SHEET

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1

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D

678

www.laptoprepairsecrets.com

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C

LCD PANEL INTERFACE (eDP) + Camera (MIPI)

1%
MF

201

1%
MF

201

C8518

0.1UF

21

10%
10V

X5R-CERM

0201

3

912

NC

6

NC

10

NC

5

NC

11

NC

21

21

D8517

SOD962-2

KA

PMEG3002ESF

D8518

SOD962-2

K A

PMEG3002ESF

EDP_PANEL_PWR_BUF_EN

PP5V_G3S

75

LCD_PWR_SLEW

PANEL_P5V_EN

1

C8515

0.1UF

10%
10V

2

X5R-CERM
0201

PP3V3_G3H

69 75

LCD_PWR_SLEW_3V3

PANEL_P3V3_EN

1

C8516

0.47UF

10%

6.3V

2

CERM-X5R
0201

69

CRITICAL

SLG5AP1443V

CAP

ON S

1

C8509

2200PF

10%
10V

2

X7R-CERM
0201

CRITICAL

SLG5AP1443V

CAP

ON S

1

C8513

2200PF

10%
10V

2

X7R-CERM
0201

1

VDD

U8500

TDFN

GND

8

1

VDD

U8501

TDFN

GND

8

5

IN

PP3V3_G3H

69 75

R8510

2 1

R8511

2 1

PP3V3_G3H

69 75

EDP_PANEL_PWR_EN

100K

5%

1/20W

MF

201

100K

5%

1/20W

MF

201

PU_U8510_4

PU_U8510_12

EDP_PANEL_PWR_DLY_EN

1

VDD

SLG4AP4998

2

EDP_PANEL_PWR_EN

4 8

PM_SLP_S3_L

SMC_RESET_INPUT_L

U8510

PANEL_FET_EN_DLY

PANEL_PWR_EN_CONN

STQFN

SMC_RESET_OUTPUT_L

X604_DISP_PWR_EN

X604_DISP_SMC_RST_L

GND

7

NC0
NC1

R8517

330

1/20W

5%
MF

201

21

PANEL_P5V_EN_D

R8515

150K

1/20W

R8516

200K

1/20W

R8518

330

1/20W

5%
MF

201

21

PANEL_P3V3_EN_D

CRITICAL

L8509

2.4GHZ

0.65X0.5X0.3MM-SM

4

SYM_VER-1

1

MIPI_FTCAM_CLK_CONN_N

69

MIPI_FTCAM_CLK_ISOL_N

69

L8580

27NH-3%-0.140A-2.3OHM

2 1

0201

MIPI_FTCAM_CLK_F_N

L8581

27NH-3%-0.140A-2.3OHM

MIPI_FTCAM_CLK_ISOL_P

69

1

C8582

7PF

+/-0.1PF
25V

2

CERM

MUX

37

D

52

1

2

37

D

52

VOLTAGE=5V

PP5V_S0SW_LCD

C8511

0.1UF

10%
10V
X5R-CERM
0201

1

C8510

1.0UF

20%

6.3V

2

X5R
0201-1

CRITICAL

1

C8512

10UF

20%
10V

2

X5R-CERM
0402-7

1

C8560

12PF

5%
25V

2

CERM
0201

MIN_NECK_WIDTH=0.1000
MIN_LINE_WIDTH=0.1000

VOLTAGE=3.3V

1

C8561

3PF

+/-0.1PF
25V

2

C0G
0201

PP3V3_S0SW_LCD

1

C8562

12PF

5%
25V

2

CERM
0201

1

C8563

3PF

+/-0.1PF
25V

2

C0G
0201

69

MIPI_FTCAM_DATA_ISOL_N<0>

69

MIPI_FTCAM_DATA_ISOL_P<0>

69

PP5V_G3S

75

77.2 mA nominal max

69 42

96.2 mA peak

0201

1

C8586

7PF

+/-0.1PF
25V

2

CERM
0201

1

C8583

7PF

+/-0.1PF
25V

2

CERM
0201

27NH-3%-0.140A-2.3OHM

27NH-3%-0.140A-2.3OHM

1

C8587

7PF

+/-0.1PF
25V

2

CERM
0201

2 1

0201

L8584

2 1

0201

L8585

2 1

0201

L8570

FERR-120-OHM-1.5A

0402A

CRITICAL

MIPI_FTCAM_CLK_F_P

7PF

25V
CERM
0201

1

2

C8581

7PF

+/-0.1PF

25V
CERM
0201

1

2

C8580

+/-0.1PF

MIPI_FTCAM_DATA_F_N<0>

MIPI_FTCAM_DATA_F_P<0>

7PF

25V
CERM
0201

1

2

C8585

7PF

+/-0.1PF

25V
CERM
0201

21

1

2

1

2

C8584

+/-0.1PF

C8577

0.1UF

10%
16V
X7R-CERM
0402

CRITICAL

PP5V_MAIN_ALSCAM_F

MIN_LINE_WIDTH=0.5000
MIN_NECK_WIDTH=0.1500

J8500

20759-042E-02

78 69 68 69 42

PPVOUT_S0_LCDBKLT PP3V3_S0SW_LCD

F-ST-SM

PWR

4443

3 2

PLACE_NEAR=J8500.37:2.54MM

MIPI_FTCAM_CLK_CONN_P

CRITICAL

L8507

2.4GHZ

0.65X0.5X0.3MM-SM

4

3 2

SYM_VER-1

1

MIPI_FTCAM_DATA_CONN_N<0>

MIPI_FTCAM_DATA_CONN_P<0>

PLACE_NEAR=J8500.33:2.54MM

69

VOLTAGE=5V

516S00266

CONNECTOR

69

D

69

69

C

B

A

FTCAM Secure Disable

PP3V3_G3S

75

MIPI_FTCAM_CLK_P

33

MIPI_FTCAM_CLK_N

33

MIPI_FTCAM_DATA_P<0>

33

MIPI_FTCAM_DATA_N<0>

33

I2C_FTCAM_SDA

I2C_FTCAM_SCL

SEP_CAM_DISABLE_OE_L
SEP_CAM_DISABLE_OUT_L

S

Output

H

Cam Enable
Cam Disable

L

PLACE_NEAR=J8500:5MM

5%

100V

C0G

0201

1

2

C8501

12PF

69

78 69 68

78 69 68

EDP_PANEL_PWR_BUF_EN
I2C_BKLT_SDA

PPVOUT_S0_LCDBKLT

100V

C0G

0201

1

C8503

12PF

2

100V

C0G

0201

C8504

3PF

+/-0.1PF

5%

43

BI

43

BI

40

IN

PLACE_NEAR=J8500:5MM

1

2

C8502

+/-0.1PF

3PF

100V

C0G

0201

1

2

BYPASS=U8570::3MM

C8595

0.1UF

X5R-CERM

R8589

100K

5%

1/20W

MF

201

PLACE_NEAR=J8500:5MM

10%

100V

X7R

0402

1

2

C8500

1000PF

10%
10V

0201

1

2

1

2

NOSTUFF

C8573

1

2

3

4

5

6

8

11

CLKP

CLKN

D1P

D1N

D2P

D2N

OE*

SEL

12PF

5%

25V
CERM
0201

10

VCC

U8595

FSA642S

UMLP-COMBO

CLKAP

CLKBP
CLKAN

CLKBN

SWITCH

CONTROL

GND

9

1

C8570

2

DA1P

DB1P
DA1N

DB1N
DA2P

DB2P
DA2N

DB2N

NC
NC

12PF

25V
CERM
0201

5%

17

22

16

23

15

20

14

21

13

19

12

18

7
24

1

2

MIPI_FTCAM_CLK_ISOL_P

MIPI_FTCAM_CLK_ISOL_N

MIPI_FTCAM_DATA_ISOL_P<0>

MIPI_FTCAM_DATA_ISOL_N<0>

NC

I2C_FTCAM_ISOL_SDA

NC

I2C_FTCAM_ISOL_SCL

NC
NC

43

43

42

42

BI

BI

BI

BI

I2C_ALS_SDA

I2C_ALS_SCL

I2C_FTCAM_ISOL_SDA

69

I2C_FTCAM_ISOL_SCL

69

I2C_TCON_SDA

I2C_TCON_SCL

69

69

69

69

R8595

100K

5%

1/20W

MF

201

R8556

R8558

R8560

R8562

R8572

R8568

PP1V8_G3S

1

2

1

R8596

100K

5%
1/20W
MF
201

2

2 1

1/20W 5%

201 MF

2 1

1/20W 5%

201 MF

2 1

1/20W 5%

201 MF

2 1

1/20W 5%

201 MF

33

33

33

33

33

33

69

69

PLACE_NEAR=J8500:5MM

PLACE_NEAR=J8500:5MM

PLACE_NEAR=J8500:5MM

PLACE_NEAR=J8500:5MM

PLACE_NEAR=J8500:5MM

21

1/20W5%

201MF

PLACE_NEAR=J8500:5MM

21

1/20W5%

201MF

1

C8550

12PF

5%
25V

2

CERM
0201

43 75

1

C8551

12PF

5%
25V

2

CERM
0201

1

C8552

12PF

5%
25V

2

CERM
0201

1

C8553

12PF

5%
25V

2

CERM
0201

DP_INT_AUXCH_C_N

69 5

DP_INT_AUXCH_C_P

69 5

DP_INT_ML_C_N<0>

5

DP_INT_ML_C_P<0>

5

DP_INT_ML_C_N<1>

5

DP_INT_ML_C_P<1>

5

DP_INT_ML_C_N<2>

5

DP_INT_ML_C_P<2>

5

DP_INT_ML_C_N<3>

5

DP_INT_ML_C_P<3>

5

MIPI_FTCAM_DATA_CONN_N<0>

69

MIPI_FTCAM_DATA_CONN_P<0>

69

MIPI_FTCAM_CLK_CONN_N

69

MIPI_FTCAM_CLK_CONN_P

69

PP5V_S0SW_LCD

69

COWLING BOSES

860-00974

SH8501

2.7X1.8R-1.4ID-0.91H-SM-X1030

1

SH8502

2.7X1.8R-1.4ID-0.91H-SM-X1030

1

CKPLUS_WAIVE=I2C_PULLUP

I2C_ALS_SDA_CONN

CKPLUS_WAIVE=I2C_PULLUP

I2C_ALS_SCL_CONN

CKPLUS_WAIVE=I2C_PULLUP

I2C_FTCAM_SDA_CONN

CKPLUS_WAIVE=I2C_PULLUP

I2C_FTCAM_SCL_CONN

CKPLUS_WAIVE=I2C_PULLUP

I2C_TCON_SDA_CONN

CKPLUS_WAIVE=I2C_PULLUP

I2C_TCON_SCL_CONN

1

C8554

12PF

5%
25V

2

CERM
0201

1

C8555

12PF

5%
25V

2

CERM
0201

BOM_COST_GROUP=DISPLAY

69

69

69

69

69

69

SIGNAL

PWR

GND

21
43
65
87
109
1211
1413
1615
1817
2019
2221
2423
2625
2827
3029
3231
3433
3635
3837
4039
4241

4645

4847
5049
5251
5453
5655
5857
6059
6261
6463
6665
6867

NC

NC

EDP_PANEL_PWR_BUF_EN
DP_INT_HPD

TP_LCD_IRQ_L

P0: J8500.14 was TCON_BKLT_PWM on J130

EDP_BKLT_PWM

I2C_BKLT_SDA
I2C_BKLT_SCL
I2C_TCON_SDA_CONN
I2C_TCON_SCL_CONN

I2C_ALS_SDA_CONN
I2C_ALS_SCL_CONN
I2C_FTCAM_SCL_CONN
I2C_FTCAM_SDA_CONN

PP5V_MAIN_ALSCAM_F

1

C8564

12PF

5%
25V

2

CERM
0201

LCD Panel AUX strapping

PP3V3_S0SW_LCD

R8503

R8502

PAGE TITLE

2 1

2 1

eDP Display Connector

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

1M

1M

69

5

OUT

IN

BI

BI

69

69

69

69

69

69

69

69 42

DP_INT_AUXCH_C_N

201MF1/20W5%

NO_XNET_CONNECTION=1

DP_INT_AUXCH_C_P

201MF1/20W5%

NO_XNET_CONNECTION=1

DRAWING NUMBER

PD on PCH page
(CSA5)

78 5

78 69 68

78 68

SYNC_DATE=12/06/2018SYNC_MASTER=X1032_MLB_P4BP

051-05232

REVISION

2.0.0

BRANCH

proto4b

PAGE

85 OF 152

SHEET

69 OF 86

B

69 5

69 5

A

SIZE

D

8

67

35 4

2

1

678

www.laptoprepairsecrets.com

3 245

1

A SSD External VREF

D

C

72

PP1V8_VCCQIO_SSD0

70
71

1

R8602

47K

1%
1/20W
MF
201

2

R8608

100K

1%

1/20W

MF

201

1

2

R8609

100K

1%

1/20W

MF

201

79 78 74 73 71 70

S4E0

72 71 70

79 78 74 73 71 70

79 78 75 71 70

PP1V8_VCCQIO_SSD0
PPVCCQ_ANI_SSD0
PPVCC_NAND_SSD0

SSD0_S4E0_ANI1_VREF
SSD0_S4E0_ANI0_VREF

PP0V9_SSD0_S4E0_VDD_PLL

70

PP1V8_SSD0_S4E0_AVDD18_PLL
PP1V8_SSD0_S4E0_PCI_AVDD_H

PPVPP_SSD0_S4E0

NOSTUFF

1

R8630

0

5%
1/20W
MF
0201

2

SSD0_LPB_L

71

71 31

73 71

SSD_BFH
SSD0_S4E_BOOT2
SSD0_S4E0_SWD_UID0
SSD0_S4E0_UART_RX

73

SSD0_S4E0_SWD_UID1
TP_SSD0_S4E0_UART_TX

1

2

78

73 71

71 40 34

71 32

71 32

71

78

71

PMU_SYS_ALIVE_R
SSD0_PCIE_RESET_L
SSD0_SWDIO_UART_D2R
SSD0_SWCLK_UART_R2D
SSD0_S4E0_JTAG_TDO
TP_SSD0_S4E0_JTAG_TDI
SSD0_S4E_JTAG_SEL
SSD0_S4E0_DROOP_L

73 71

SSD0_WP_L

B3
C4
B5
C6
B7
C8
B9

B11

E8

D7

E6

E4

D5

D9

T3

G2

EXT_D0/BOOT0
EXT_D1/BOOT1
EXT_D2/BOOT2/SPINAND_SCLK
EXT_D3/SWD_UID0/SPINAND_MISO
EXT_D4/UART_RX
EXT_D5/SWD_UID1/SPINAND_MOSI
EXT_D6/UART_TX
EXT_D7/SPF

EXT_NCE/PERST*

EXT_NRE/JTAG_TMS

EXT_NWE/JTAG_TCK

EXT_RNB/JTAG_TDO

EXT_CLE/JTAG_TDI

EXT_ALE/JTAG_SEL

DROOP_N

WP_N

U12

U8U6U4

U10

U2

T9T7T1

T13

R10

P13

VPP

P7P3P1

P11

F3

VDD_PLL

R2

L12G4E12

VCC

P9N2E10E2T5K9J2R4R8R6L8L6G8

D3

VDDIO_2/NAND

VDDIO_1/GPIO

U8600

NAND-S4E-S5E-MCP-STUDY-COMBO

OMIT_TABLE

N10N4M13

M7M5M1

L10

K7K5K1

K13

LGA

VSS

J10

H13

H11

VDD

H9H5H3

H1

G6

ANI1_VREF

F13

F11

J4

F9F7F5

L2

G12

ANI0_VREF

AVDD18_PLL

J8

N8H7J6

PCI_VDD_1

PCI_VDD_2

F1

PCI_AVDD_H

D13

D11D1C12C2B13B1A12

PP0V9_SSD0

PP0V9_SSD0

M9

N6

PCI_AVDD_CLK_1

PCI_AVDD_CLK_2

PCIE_REFCLK_P
PCIE_REFCLK_M

PCIE_CLKREQ_N

PCI_RESREF

PCIE_RX0_P
PCIE_RX0_M

PCIE_TX0_P
PCIE_TX0_M

A10

CLK_IN

RESET*

TRST*

ZQ_C
ZQ_N

A8A6A4

79 78 74 71 70

70

70

70

70

79 78 74 71 70

M3

K11
J12

P5

SSD0_CLK24M
PCIE_CLK100M_SSD0_01_P

PCIE_CLK100M_SSD0_01_N
SSD0_CLKREQ0_L
SSD0_S4E0_PCIE_RESREF

M11

GND_VOID=TRUE

N12

GND_VOID=TRUE

R12

GND_VOID=TRUE

T11

GND_VOID=TRUE

L4

G10

K3
C10

PLACE_NEAR=U8600.C10:15MM

A2

PCIE_SSD0_R2D_P<0>
PCIE_SSD0_R2D_N<0>

PCIE_SSD0_D2R_C_P<0>

PCIE_SSD0_D2R_C_N<0>

SSD0_RESET_L
SSD0_S4E_JTAG_TRST_L
SSD0_S4E0_ZQ_C

SSD0_S4E0_ZQ_L

1

R8605

300

1%
1/20W
MF
201

2

71 73

71 34

71 34

40 34

73

73

C8601

0201 10%6.3V

C8602

0201 6.3V 10%

73 71

73 71

PLACE_NEAR=U8600.K3:15MM

1

R8606

100

2

SSD0_S4E0_ANI1_VREF

70

See Section 7.4.2.2 of the S4E MCP Product Spec (v1.3)

0.22UF

X5R-CERM

0.22UF

X5R-CERM

1%
1/20W
MF
201

OMIT_TABLE

2 1

2 1

PCIE_SSD0_D2R_P<0>

PCIE_SSD0_D2R_N<0>

PPVCCQ_ANI_SSD0

NOSTUFF

R8680

0

21

5%

1/20W

MF

0201

34

34

NOSTUFF

1

R8681

2K

1%
1/20W
MF
201

2

SSD0_S4E0_ANI0_VREF

NOSTUFF

1

R8682

2K

1%
1/20W
MF
201

2

1

R8604

3.01K

1%
1/20W
MF
201

2

OMIT_TABLE

NOSTUFF

1

C8681

0.01UF

10%
10V

2

X7R
0201-1

NOSTUFF

1

C8682

0.01UF

10%
10V

2

X7R
0201-1

1

C8685

10PF

5%
25V

2

C0G
0201

S5E

D

70

C

B

B

79

PP0V9_SSD0

71 70
78 74

C

S4E VDD Decoupling S4E VDDIO_1

1

C8610

20UF

20%
10V

2

X5R
0402

1

C8616

20UF

20%
10V

2

X5R
0402

1

C8611

2.2UF

20%

6.3V

2

X5R
0201

1

C8612

2.2UF

20%

6.3V

2

X5R
0201

1

C8613

0.1UF

10%
16V

2

X5R-CERM
0201

1

C8614

0.1UF

10%
16V

2

X5R-CERM
0201

1

C8615

0.1UF

10%
16V

2

X5R-CERM
0201

D

E

72 71 70

S4E VDDIO_2S4E VCC Decoupling

PP1V8_VCCQIO_SSD0

1

C8684

2.2UF

20%

6.3V

2

X5R
0201

1

2

C8687

2.2UF

20%

6.3V
X5R
0201

F S4E AVDD_H/AVDD18_PLL

R8610

0

72 71 70

PP1V8_VCCQIO_SSD0

21

5%

1/20W

MF

0201

OMIT_TABLE

PP1V8_SSD0_S4E0_PCI_AVDD_H

1

C8644

0.1UF

10%
16V

2

X5R-CERM CER-X5R
0201

1

C8645

4.7UF

20%
4V

2

0201

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

R8604 S4E1118S0279 CRITICALRES,3.01KOHM,1%,1/20W,0201

R86041103S00429 CRITICAL S5ERES,200OHM,0.1%,1/20W,0201

118S0011 R8606RES,100OHM,1%,1/20W,02011 S4ECRITICAL

118S0273 R8606RES,300OHM,1%,1/20W,02011 S5ECRITICAL

117S0201 RES,0OHM,1/20W,02012 CRITICAL S4ER8683,R8610,R8611

155S00161 FERR BD,10OHM,0.05 DCR,0201 R8683,R86102 CRITICAL S5E

1 CRITICAL S5ERES,MF,2OHM,1%,1/20W,0201 R8611118S0794

G

S4E VDD_PLL

R8683

0

70

79 78 74 71 70

PLACE_NEAR=R8683.1:10MM

PP0V9_SSD0

C8683

4.7UF

CER-X5R

20%

4V

0201

21

5%

1

2

1/20W

MF

0201

OMIT_TABLE

PP0V9_SSD0_S4E0_VDD_PLL

TABLE_5_HEAD

BOM OPTIONCRITICAL

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

70

B

A

79 78 75 71 70

PPVCC_NAND_SSD0

1

2

8

C8651

20UF

20%
10V
X5R
0402

1

C8648

10UF

20%
10V

2

X5R-CERM
0402-7 0201

1

2

C8649

2.2UF

20%

6.3V
X5R

1

C8650

2.2UF

20%

6.3V

2

X5R
0201

74 73 71 70

79 78

67

PPVCCQ_ANI_SSD0

20%
10V

1

2

C8632

10UF

X5R-CERM

0402-7

C8636

4.3UF

20%

4V
CERM
0402

432

1

C8635

2.2UF

20%

6.3V

2

X5R

1

0201

R8611

0

21

5%

1/20W

MF

0201

OMIT_TABLE

PP1V8_SSD0_S4E0_AVDD18_PLL

1

C8646

0.1UF

10%
16V

2

X5R-CERM
0201

1

C8647

2.2UF

20%

6.3V

2

X5R
0201

35 4

70

BOM_COST_GROUP=SSD

SYNC_MASTER=j213 SYNC_DATE=09/27/2018

PAGE TITLE

S4E<0>

SIZE

D

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

2

DRAWING NUMBER

051-05232

REVISION

2.0.0

BRANCH

proto4b

PAGE

86 OF 152

SHEET

70 OF 86

1

A

678

www.laptoprepairsecrets.com

3 245

1

A SSD External VREF

D

C

72 71 70

PP1V8_VCCQIO_SSD0

1

R8702

47K

1%
1/20W
MF
201

2

R8709

100K

1%

1/20W

MF

201

1

R8708

100K

2

1

2

1%
1/20W
MF
201

70

70 31

73 70

73

78

73 70

70 40 34

70 32

70 32

78

70

70

73 70

79 78 74 73 71 70

79 78 75 71 70

1

2

SSD0_LPB_L
SSD_BFH
SSD0_S4E_BOOT2
SSD0_S4E1_SWD_UID0
SSD0_S4E1_UART_RX
SSD0_S4E1_SWD_UID1
TP_SSD0_S4E1_UART_TX
PMU_SYS_ALIVE_R

SSD0_PCIE_RESET_L
SSD0_SWDIO_UART_D2R
SSD0_SWCLK_UART_R2D
TP_SSD0_S4E1_JTAG_TDO
SSD0_S4E0_JTAG_TDO
SSD0_S4E_JTAG_SEL
SSD0_S4E1_DROOP_L
SSD0_WP_L

72 71 70

NOSTUFF

R8730

0

5%
1/20W
MF
0201

B3
C4
B5
C6
B7
C8
B9

B11

E8

D7

E6

E4

D5

D9

T3

G2

PP1V8_VCCQIO_SSD0
PPVCCQ_ANI_SSD0
PPVCC_NAND_SSD0

PP0V9_SSD0_S4E1_VDD_PLL

71

PPVPP_SSD0_S4E1

EXT_D0/BOOT0
EXT_D1/BOOT1
EXT_D2/BOOT2/SPINAND_SCLK
EXT_D3/SWD_UID0/SPINAND_MISO
EXT_D4/UART_RX
EXT_D5/SWD_UID1/SPINAND_MOSI
EXT_D6/UART_TX
EXT_D7/SPF

EXT_NCE/PERST*

EXT_NRE/JTAG_TMS

EXT_NWE/JTAG_TCK

EXT_RNB/JTAG_TDO

EXT_CLE/JTAG_TDI

EXT_ALE/JTAG_SEL

DROOP_N

WP_N

U12

U8U6U4

U10

U2

T9T7T1

T13

R10

P13

VPP

P7P3P1

P11

F3

VDD_PLL

S4E1

R2

L12G4E12

VCC

NAND-S4E-S5E-MCP-STUDY-COMBO

N10N4M13

M7M5M1

P9N2E10E2T5K9J2R4R8R6L8L6G8

D3

VDDIO_2/NAND

VDDIO_1/GPIO

U8700

LGA

OMIT_TABLE

VSS

K7K5K1

L10

K13

J10

H13

H11

VDD

H9H5H3

H1

G6

ANI1_VREF

F13

F11

SSD0_S4E1_ANI1_VREF
SSD0_S4E1_ANI0_VREF

PP1V8_SSD0_S4E1_AVDD18_PLL
PP1V8_SSD0_S4E1_PCI_AVDD_H

J8

J4

F9F7F5

L2

G12

ANI0_VREF

AVDD18_PLL

N8H7J6

PCI_VDD_1

PCI_VDD_2

F1

D13

D11D1C12C2B13B1A12

M9

PCI_AVDD_H

PCI_AVDD_CLK_2

PP0V9_SSD0

PP0V9_SSD0

N6

PCI_AVDD_CLK_1

CLK_IN

PCIE_REFCLK_P
PCIE_REFCLK_M

PCIE_CLKREQ_N

PCI_RESREF

PCIE_RX0_P
PCIE_RX0_M

PCIE_TX0_P
PCIE_TX0_M

RESET*

TRST*

A8A6A4

A10

ZQ_C
ZQ_N

79 78 74 71 70

71

71

71

71

79 78 74 71 70

M3

K11
J12

P5

SSD0_CLK24M
PCIE_CLK100M_SSD0_01_P

PCIE_CLK100M_SSD0_01_N
SSD0_CLKREQ1_L
SSD0_S4E1_PCIE_RESREF

M11

GND_VOID=TRUE

N12

GND_VOID=TRUE

R12

GND_VOID=TRUE

T11

GND_VOID=TRUE

L4

G10

K3
C10

PLACE_NEAR=U8700.C10:15MM

A2

PCIE_SSD0_R2D_P<1>
PCIE_SSD0_R2D_N<1>

PCIE_SSD0_D2R_C_P<1>

PCIE_SSD0_D2R_C_N<1>

SSD0_RESET_L
SSD0_S4E_JTAG_TRST_L
SSD0_S4E1_ZQ_C

SSD0_S4E1_ZQ_L

1

R8705

300

1%
1/20W
MF
201

2

70 73

70 34

70 34

40 34

73

73

C8701

6.3V0201

C8702

6.3V

73 70

73 70

79 78 74 73 71 70

PPVCCQ_ANI_SSD0

NOSTUFF

1

R8781

2K

1%
1/20W
MF
201

NOSTUFF

2

R8780

0

21

5%

1/20W

MF

0201

See Section 7.4.2.2 of the S4E MCP Product Spec (v1.3)

1

2

0.22UF

X5R-CERM10%

0.22UF

10%0201 X5R-CERM

PLACE_NEAR=U8700.K3:15MM

1

R8706

100

1%
1/20W
MF
201

2

OMIT_TABLE

2 1

2 1

PCIE_SSD0_D2R_P<1>

PCIE_SSD0_D2R_N<1>

34

34

SSD0_S4E1_ANI0_VREFSSD0_S4E1_ANI1_VREF

NOSTUFF

1

R8782

2K

1%
1/20W
MF
201

2

R8704

3.01K

1%
1/20W
MF
201

OMIT_TABLE

NOSTUFF

1

C8781

0.01UF

10%
10V

2

X7R
0201-1

NOSTUFF

1

C8782

0.01UF

10%
10V

2

X7R
0201-1

1

C8785

10PF

5%
25V

2

C0G
0201

S5E

D

71 71

C

B

B

79

PP0V9_SSD0

71 70
78 74

C

S4E VDD Decoupling

1

C8710

20UF

20%
10V

2

X5R
0402

1

C8716

20UF

20%
10V

2

X5R
0402

1

C8711

2.2UF

20%

6.3V

2

X5R
0201

1

C8712

2.2UF

20%

6.3V

2

X5R
0201

1

C8713

0.1UF

10%
16V

2

X5R-CERM
0201

1

C8714

0.1UF

10%
16V

2

X5R-CERM
0201

S4E VCC Decoupling

1

C8715

0.1UF

10%
16V

2

X5R-CERM
0201

D

E

S4E VDDIO_1

72 71 70

PP1V8_VCCQIO_SSD0

1

C8784

2.2UF

20%

6.3V

2

X5R
0201

S4E VDDIO_2

1

C8787

2.2UF

20%

6.3V

2

X5R
0201

F

72 71 70

PP1V8_VCCQIO_SSD0

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

RES,200OHM,0.1%,1/20W,0201 S5ECRITICAL1 R8704103S00429

FERR BD,10OHM,0.05 DCR,0201 S5ECRITICAL2 R8783,R8710155S00161

1 S5ECRITICAL118S0794 RES,MF,2OHM,1%,1/20W,0201 R8711

G

R8710

0

21

5%

1/20W

MF

0201

OMIT_TABLE OMIT_TABLE

PP1V8_SSD0_S4E1_PCI_AVDD_H

1

C8744

0.1UF

10%
16V

2

X5R-CERM
0201

1

C8745

4.7UF

20%
4V

2

CER-X5R
0201

71

79 78 74 71 70 71

S4E VDD_PLLS4E AVDD_H/AVDD18_PLL

R8783

0

PP0V9_SSD0 PP0V9_SSD0_S4E1_VDD_PLL

PLACE_NEAR=R8783.1:10MM

20%

4V

0201

1

2

C8783

4.7UF

CER-X5R

1/20W

0201

21
5%
MF

TABLE_5_HEAD

BOM OPTIONCRITICAL

TABLE_5_ITEM

CRITICAL S4E1 RES,3.01KOHM,1%,1/20W,0201 R8704118S0279

TABLE_5_ITEM

TABLE_5_ITEM

S4ECRITICAL1118S0011 R8706RES,100OHM,1%,1/20W,0201

TABLE_5_ITEM

S5ECRITICAL1118S0273 R8706RES,300OHM,1%,1/20W,0201

TABLE_5_ITEM

S4ECRITICAL2117S0201 R8783,R8710,R8711RES,0OHM,1/20W,0201

TABLE_5_ITEM

TABLE_5_ITEM

B

A

79 78 75 71 70

PPVCC_NAND_SSD0

1

2

8

C8751

20UF

20%
10V
X5R
0402

1

C8748

10UF

20%
10V

2

X5R-CERM
0402-7

1

C8749

2.2UF

20%

6.3V

2

X5R
0201

1

C8750

2.2UF

20%

6.3V

2

X5R
0201

74 73 71 70

79 78

67

PPVCCQ_ANI_SSD0

20%
10V

1

2

C8732

10UF

X5R-CERM

0402-7

C8736

4.3UF

20%

4V
CERM
0402

432

1

C8735

2.2UF

20%

6.3V

2

X5R

1

0201

R8711

0

21

5%

1/20W

MF

0201

OMIT_TABLE

PP1V8_SSD0_S4E1_AVDD18_PLL

1

C8746

0.1UF

10%
16V

2

X5R-CERM
0201

1

C8747

2.2UF

20%

6.3V

2

X5R
0201

35 4

71

BOM_COST_GROUP=SSD

SYNC_MASTER=j213 SYNC_DATE=09/27/2018

PAGE TITLE

S4E<1>

SIZE

D

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

2

DRAWING NUMBER

051-05232

REVISION

2.0.0

BRANCH

proto4b

PAGE

87 OF 152

SHEET

71 OF 86

1

A

678

www.laptoprepairsecrets.com

3 245

1

D

A

NAND VCC (PPVCC_NAND_SSD0) Voltage Regulator

PPBUS_G3H_SSD0

46 75

76

IN

CRITICAL

1

C9058

68UF

20%
16V

2

POLY-TANT
CASE-D2E-SM

R9060

0

5%

1/20W

MF

0201

21

CRITICAL CRITICAL

1

C9061

2.2UF

20%
25V

2

X6S-CERM
0402

1

C9062

2.2UF

20%
25V

2

X6S-CERM
0402

1

R9062

47K

5%
1/20W
MF
201

2

2

R9065

10

5%
1/20W
MF
201

1

PVCCSSD0_AVIN

PVCCSSD0_ENPVCCNAND_EN

CRITICAL

1

C9065

0.1UF

10%
25V

2

X6S-CERM
0201

10

AVIN

8

DEF

13

EN

7

FSW

XW9060

SM

21

12

11

PVIN

PVIN

U9060

TPS62130B-S

VQFN

CRITICAL

353S00897

PAD

THRM

PGND

16

AGND

6

17

PGND

15

SW
SW
SW

VOS

FB

PG

SS/TR

1
2
3

14

5

4

9

R9067

PVCCSSD0_PHASE

DIDT=TRUE

PVCCSSD0_VOS
PVCCSSD0_FB
PVCCNAND_PGOOD
PVCCSSD0_SS

C9068

1500PF

100K

5%

1/20W

MF

201

10%
10V
X7R

0201

PPVCC_NAND_SSD0

1

2

1

2

2.2UH-20%-5.5A-0.043OHM

76

152S00703

CRITICAL

L9060

MHCI04020C-COMBO

PVCCSSD0_FB_TOP

1

C9069

100PF

5%
25V

2

C0G
0201

72 75

21

<Ra>

XW9070

SM

R9070

10

5%

1/20W

MF

201

R9071

1K

1%

1/20W

MF

201

CRITICAL

R9073

48.7K

0.1%

1/20W

MF

0201

2

1

1

2

1

2

PVCCSSD0_FB_R

1

2

Vout = 2.5V
Iout Max = 2.4A
F = 1.25 MHZ

Vout = 0.8 * (1 + <Ra>/<Rb>) = 2.701V

NOSTUFF

CRITICAL

1

C9070

10UF

20%

6.3V

2

CER-X6S
0402

CRITICAL

1

C9071

10UF

20%

6.3V

2

CER-X6S
0402

CRITICAL

1

C9072

150UF

20%

6.3V

2

TANT
CASE-B-SM

CRITICAL

1

C9073

100UF

20%

6.3V

2

POLY-TANT
CASE-A3

Caps below are placed close to the load.

CRITICAL

1

C9080

10UF

20%
10V

2

X5R-CERM
0402-7

CRITICAL

1

C9081

10UF

20%
10V

2

X5R-CERM
0402-7

CRITICAL

1

C9082

10UF

20%
10V

2

X5R-CERM
0402-7

CRITICAL

1

C9083

10UF

20%
10V

2

X5R-CERM
0402-7

PPVCC_NAND_SSD0

1

2

CRITICAL

C9084

10UF

20%
10V
X5R-CERM
0402-7

CRITICAL

1

C9085

10UF

20%
10V

2

X5R-CERM
0402-7

D

72 75

C

B

NAND VCCQ I/O Selector

GND_PVCCSSD0_AGND

VOLTAGE=0V

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000

CRITICAL

R9072

23.2K

<Rb>

0.1%

1/20W

0201

MF

1

2

CRITICAL

1

C9086

10UF

20%
10V

2

X5R-CERM
0402-7

CRITICAL

1

C9087

10UF

20%
10V

2

X5R-CERM
0402-7

CRITICAL

1

C9088

10UF

20%
10V

2

X5R-CERM
0402-7

CRITICAL

1

C9089

10UF

20%
10V

2

X5R-CERM
0402-7

CRITICAL

1

C9090

10UF

20%
10V

2

X5R-CERM
0402-7

CRITICAL

1

C9091

10UF

20%
10V

2

X5R-CERM
0402-7

C

B

PPVCCQ_ANI_SSD0

74

PP1V8SW_VCCQIO_SSD0

62 74

SSD_PWR:S5E

R9011

0

21

5%
1/16W
MF-LF

402

SSD_PWR:S4E

1

R9010

0

5%
1/16W
MF-LF
402

2

PP1V8_VCCQIO_SSD0

71 70

B

A

8

67

SYNC_MASTER=psm

PAGE TITLE

SYNC_DATE=10/18/2018

A

NAND VCC VR

SIZE

D

Apple Inc.

DRAWING NUMBER

051-05232

REVISION

2.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=SSD

35 4

IV ALL RIGHTS RESERVED

2

BRANCH

proto4b

PAGE

90 OF 152

SHEET

72 OF 86

1

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www.laptoprepairsecrets.com

3 245

1

D

C

B

C

SSD PCIE AC Coupling Caps SSD Discharge CircuitA

(All Caps)

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

34

34

34

34

OUT

OUT

OUT

OUT

PCIE_SSD0_R2D_C_P<0>

PCIE_SSD0_R2D_C_N<0>

PCIE_SSD0_R2D_C_P<1>

PCIE_SSD0_R2D_C_N<1>

C9110

0.22UF

C9111

0.22UF

C9112

0.22UF

C9113

0.22UF

21
20% 6.3V

21

20% X5R6.3V
21

X5R6.3V 020120%

21

20% 02016.3V X5R

0201X5R

0201

PCIE_SSD0_R2D_P<0>

PCIE_SSD0_R2D_N<0>

PCIE_SSD0_R2D_P<1>

PCIE_SSD0_R2D_N<1>

SSD PCIE Net Aliases

34

34

34

34

34

34

34

34

34

34

OUT
OUT

IN

IN
OUT
OUT

IN

IN

IN

IN

NC_S4E3_PCIE_R2D_CP<2>
NC_S4E3_PCIE_R2D_CN<2>
NC_S4E3_PCIE_D2RP<2>
NC_S4E3_PCIE_D2RN<2>
NC_S4E3_PCIE_R2D_CP<3>
NC_S4E3_PCIE_R2D_CN<3>
NC_S4E3_PCIE_D2RP<3>
NC_S4E3_PCIE_D2RN<3>
NC_PCIE_CLK100M_SSD0_23N
NC_PCIE_CLK100M_SSD0_23P

MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE

NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1

NC_S4E3_PCIE_R2D_CP<2>
NC_S4E3_PCIE_R2D_CN<2>
NC_S4E3_PCIE_D2RP<2>
NC_S4E3_PCIE_D2RN<2>
NC_S4E3_PCIE_R2D_CP<3>
NC_S4E3_PCIE_R2D_CN<3>
NC_S4E3_PCIE_D2RP<3>
NC_S4E3_PCIE_D2RN<3>
NC_PCIE_CLK100M_SSD0_23N
NC_PCIE_CLK100M_SSD0_23P

SSD Write Protect Control

70

70

71

71

G

PPVCC_NAND_SSD0

75

NAND_DISCHARGE_EN

76

1

R9106

10K

5%
1/20W
MF
201

2

R9105

10K

5%

1/20W

MF

201

1

R9120

15.4

1%
1/10W
MF-LF
603

2

21

1

R9121

2

1

C9105

33000PF

10%

6.3V

2

X5R
201

1

R9122

15.4

1%
1/10W
MF-LF
603

15.4

1%
1/10W
MF-LF
603

2

P2V7_SSD_DISCHARGE

4

D

G

1

S

32

NAND_DISCHARGE_EN_RC

1

R9123

15.4

1%
1/10W
MF-LF
603

2

Q9120

DMN2044UCB4

BGA

1

R9124

15.4

1%
1/10W
MF-LF
603

2

1

1

R9125

15.4

1%
1/10W

2

4

D

MF-LF
603

D

Q9121

G

S

32

DMN2044UCB4

BGA

C

D

79 78 74 71 70

PPVCCQ_ANI_SSD0

1

R9110

100

1%
1/20W
MF
201

2

SSD0_WP_L

71 70

SSD Miscellaneous Control

H SSD UART Test Points

PP9100

P3MM

SM

SSD0_S4E0_UART_RX

70

SSD0_S4E1_UART_RX

71

1

PP

PP9101

P3MM

SM

1

PP

B

76

64 32 31

NAND_RESET_L

PMU_SYS_ALIVE

R9115

R9117

0

5%1/20W MF

21

0

21

E S4E Pull-Downs

SSD0_S4E_JTAG_TRST_L
SSD0_S4E_BOOT2

R9130

100K

1%

1/20W

MF

201 201

1

R9131

100K

1/20W

2

1

1%
MF

2

0201

02011/20W 5% MF

SSD0_RESET_L

71 70

B

PMU_SYS_ALIVE_R

71 70

71 70

71 70

A

F

S4E Control Aliases

SSD0_CLK24M

40

MAKE_BASE=TRUE

8

SSD0_CLK24M

70 71

67

A

PAGE TITLE

SSD Support

DRAWING NUMBER

051-05232

Apple Inc.

REVISION

2.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=SSD

35 4

IV ALL RIGHTS RESERVED

2

BRANCH

proto4b

PAGE

91 OF 152

SHEET

73 OF 86

1

SIZE

D

678

www.laptoprepairsecrets.com

3 245

1

D

C

PMIC Buck0 - SoC VDD_CPU

PPVDDCPU_AWAKE

62

Sourced from 3V3 G3H
Enabled by

PMIC Buck1 - SoC VDD_CPU_SRAM

PPVDDCPUSRAM_AWAKE

62

Sourced from 3V3 G3H
Enabled by

PMIC Buck2 - SoC VDD_SOC

PP0V82_SLPDDR

62

Sourced from 3V3 G3H
Enabled by

PMIC BUCK3 - SoC AOP/SMC/VDD1

PP1V8_SLPS2R

62 81

Sourced from 3V3 G3H
Enabled by

PMIC BUCK3 SW 4 - VDD1

PPVDDCPU_AWAKE

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.0750
VOLTAGE=1.06V VOLTAGE=1.8V
MAKE_BASE=TRUE MAKE_BASE=TRUE

PPVDDCPU_AWAKE

78 78

35

PP1V8_S3

66

Sourced from PP1V8_PRIM_PCH
Enabled by PVDDQ_EN

PP1V8_S3

MIN_LINE_WIDTH=0.1000
MIN_NECK_WIDTH=0.0750

PP1V8_S3

PMIC BUCK3 SW 5 - SSD VCCQIO

PPVDDCPUSRAM_AWAKE

MIN_LINE_WIDTH=0.4000
MIN_NECK_WIDTH=0.0750
VOLTAGE=1.06V
MAKE_BASE=TRUE

PPVDDCPUSRAM_AWAKE

35

PP1V8SW_VCCQIO_SSD0

62 72 74

Sourced from PP1V8_SLPS2R
Enabled by

PP1V8SW_VCCQIO_SSD0

MIN_LINE_WIDTH=0.1000
MIN_NECK_WIDTH=0.0750
VOLTAGE=1.8V
MAKE_BASE=TRUE

PP1V8SW_VCCQIO_SSD0

PMIC Buck4 - SDRAM VDD2

PP0V82_SLPDDR

MIN_LINE_WIDTH=0.7000
MIN_NECK_WIDTH=0.0750
VOLTAGE=0.82V
MAKE_BASE=TRUE

PP0V82_SLPDDR
PP0V82_SLPDDR

PP1V8_SLPS2R

MIN_LINE_WIDTH=0.1000
MIN_NECK_WIDTH=0.0750
VOLTAGE=1.8V
MAKE_BASE=TRUE

PP1V8_SLPS2R
PP1V8_SLPS2R
PP1V8_SLPS2R
PP1V8_SLPS2R
PP1V8_SLPS2R
PP1V8_SLPS2R
PP1V8_SLPS2R
PP1V8_SLPS2R
PP1V8_SLPS2R
PP1V8_SLPS2R
PP1V8_SLPS2R
PP1V8_SLPS2R
PP1V8_SLPS2R

PP1V8_SLPS2R
PP1V8_SLPS2R

PP1V8_SLPS2R
PP1V8_SLPS2R
PP1V8_SLPS2R
PP1V8_SLPS2R

78

35

81

79 78

62

66

63

49

39

64

40 53

39

31 40

37

37

37

37

56

42 55

42

40 49

24

25

PP1V1_SLPS2R

62

Sourced from 3V3_G3H
Enabled by

U7901 - VDDIO_DDR & PLL

PP1V1_SLPDDR

63

Sourced from
Enabled by

PMIC Buck5 - VDD_FIXED

PP0V9_SLPDDR

62

Sourced from 3V3_G3H
Enabled by

PP1V1_SLPS2R

MIN_LINE_WIDTH=0.5000
MIN_NECK_WIDTH=0.0750
VOLTAGE=1.1V
MAKE_BASE=TRUE

PP1V1_SLPS2R
PP1V1_SLPS2R

PP1V1_SLPS2R
PP1V1_SLPS2R

PP1V1_SLPDDR

MIN_LINE_WIDTH=0.1000
MIN_NECK_WIDTH=0.0750
VOLTAGE=1.1V
MAKE_BASE=TRUE

PP1V1_SLPDDR
PP1V1_SLPDDR
PP1V1_SLPDDR
PP1V1_SLPDDR

PP0V9_SLPDDR

MIN_LINE_WIDTH=0.3000
MIN_NECK_WIDTH=0.0750
VOLTAGE=0.9V
MAKE_BASE=TRUE

PP0V9_SLPDDR
PP0V9_SLPDDR
PP0V9_SLPDDR
PP0V9_SLPDDR
PP0V9_SLPDDR
PP0V9_SLPDDR

19 20 65

62 72 74

63

63

36

37

78

31

36

36

37

36

36

36

36

36

81

PMIC Buck9 - 0V9 SSD

PP0V9_SSD0

62

Sourced from 3V3 G3H
Enabled by

PMIC Buck10 - 1V8 SSD

PPVCCQ_ANI_SSD0

62

Sourced from 3V3 G3H
Enabled by

PMIC LDO0 - VDD_LOW

PP0V8_SLPS2R

63

Sourced from PP1V1_SLP2R
Enabled by

PMIC LDO1 - PCH VCCRTC

PP3V_G3H

63

Sourced from PP3V3_G3H
Enabled by

PMIC LDO2 - PCIE_REFBUF/PLL

PP0V9_SSD0

MIN_LINE_WIDTH=0.4000
MIN_NECK_WIDTH=0.0750
VOLTAGE=0.9V
MAKE_BASE=TRUE

PP0V9_SSD0

PPVCCQ_ANI_SSD0

MIN_LINE_WIDTH=0.4000
MIN_NECK_WIDTH=0.0750
VOLTAGE=1.8V
MAKE_BASE=TRUE

PPVCCQ_ANI_SSD0
PPVCCQ_ANI_SSD0

PP0V8_SLPS2R

MIN_LINE_WIDTH=0.1000
MIN_NECK_WIDTH=0.0750
VOLTAGE=0.8V
MAKE_BASE=TRUE

PP0V8_SLPS2R

PP3V_G3H

MIN_LINE_WIDTH=0.1000
MIN_NECK_WIDTH=0.0750
VOLTAGE=3V
MAKE_BASE=TRUE

PP3V_G3H

D

79 78 71 70

81

79 78 73 71 70

72

81

C

36

78

9 12

B

PMIC BUCK3 SW 1

PP1V8_AWAKE

62 81

Sourced from PP1V8_SLPS2R
Enabled by

PP1V8_AWAKE

MIN_LINE_WIDTH=0.0900
MIN_NECK_WIDTH=0.0750
VOLTAGE=1.8V
MAKE_BASE=TRUE

PP1V8_AWAKE
PP1V8_AWAKE
PP1V8_AWAKE
PP1V8_AWAKE
PP1V8_AWAKE
PP1V8_AWAKE
PP1V8_AWAKE
PP1V8_AWAKE
PP1V8_AWAKE
PP1V8_AWAKE
PP1V8_AWAKE

78

64

39

37

37

37

37

37

34 39 40

39

54

23

PMIC Buck7 - VCCPRIM_CORE

PPVNN_PCH_EXT_REG

62

Sourced from 3V3_G3H
Enabled by

PMIC Buck8 - VCCPRIM_1P0

PP1V05_PCH_EXT_REG

62

Sourced from 3V3_G3H

Enabled by

PP1V05_PCH_VCCPRIM

9

PPVNN_PCH_EXT_REG

MIN_LINE_WIDTH=0.0900
MIN_NECK_WIDTH=0.0750
VOLTAGE=1.0V
MAKE_BASE=TRUE

PPVNN_PCH_EXT_REG

PP1V05_PCH_EXT_REG

MIN_LINE_WIDTH=4.5000
MIN_NECK_WIDTH=0.0750
VOLTAGE=1.05V
MAKE_BASE=TRUE

PP1V05_PCH_EXT_REG

PP1V05_PCH_EXT_REG

PP1V05_PCH_VCCPRIM

MIN_LINE_WIDTH=0.7000
MIN_NECK_WIDTH=0.0750

VOLTAGE=1.05V

MAKE_BASE=TRUE

78

46

78

62

46

PP1V2_AWAKE

63

Sourced from PP1V8_SLPS2R
Enabled by

PP1V2_AWAKE

MIN_LINE_WIDTH=0.1000
MIN_NECK_WIDTH=0.0750
VOLTAGE=1.2V
MAKE_BASE=TRUE

PP1V2_AWAKE
PP1V2_AWAKE
PP1V2_AWAKE
PP1V2_AWAKE

PMIC V3P3 SW 1 - USB

PP3V3_AWAKE

63

Sourced from 3V3_G3H
Enabled by

PP3V3_AWAKE

MIN_LINE_WIDTH=0.1000
MIN_NECK_WIDTH=0.0750
VOLTAGE=3.3V
MAKE_BASE=TRUE

PP3V3_AWAKE

PMIC V3P3 SW 2 - VCCDSW_3P3, VCCPRIM_3P3

PP3V3_S5

63

Sourced from 3V3_G3H
Enabled by

PP3V3_S5

MIN_LINE_WIDTH=0.1500
MIN_NECK_WIDTH=0.0750
VOLTAGE=3.3V
MAKE_BASE=TRUE

PP3V3_S5
PP3V3_S5
PP3V3_S5
PP3V3_S5
PP3V3_S5

PP3V3_S5

PP3V3_S5
PP3V3_S5
PP3V3_S5
PP3V3_S5
PP3V3_S5

PP3V3_S5

78

37

37

37

37

B

37

61

66

66

18 66 74

17

18 66 74

18

39

5 13 14 17 18 42

9 42 59

9

9 12

40

PP1V05_PCH_VCCPRIM

A

PP1V05_PCH_VCCPRIM

9

PP1V05_PCH_CPU

MIN_LINE_WIDTH=2.7000
MIN_NECK_WIDTH=0.0750
VOLTAGE=1.05V
MAKE_BASE=TRUE

PP1V05_PCH_CPU

PP1V05_PCH_CPU

8

67

9

9

66

SYNC_DATE=02/21/2017SYNC_MASTER=X589_CPU_CNL_Y

PAGE TITLE

A

Power Aliases - 1

DRAWING NUMBER

051-05232

Apple Inc.

REVISION

2.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

35 4

2

BRANCH

proto4b

PAGE

120 OF 152

SHEET

74 OF 86

1

SIZE

D

678

www.laptoprepairsecrets.com

3 245

1

D

C

PBUS Rails

U7000 - PBUS

56

44

23

60

PPBUS_G3H

PPBUS_HS_CPU

PPDCIN_G3H

U7550 - 5V G3S

PP5V_G3S

Sourced from PBus
Enabled by P5VG3S_EN

PPBUS_G3H

MIN_LINE_WIDTH=0.1000
MIN_NECK_WIDTH=0.2000
VOLTAGE=13.1V
MAKE_BASE=TRUE

PPBUS_G3H
PPBUS_G3H
PPBUS_G3H
PPBUS_G3H
PPBUS_G3H

PPBUS_G3H
PPBUS_G3H
PPBUS_G3H
PPBUS_G3H
PPBUS_G3H
PPBUS_G3H

PPBUS_G3H

PPBUS_HS_CPU

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.0750
VOLTAGE=13.1V
MAKE_BASE=TRUE

PPBUS_HS_CPU
PPBUS_HS_CPU
PPBUS_HS_CPU
PPBUS_HS_CPU
PPBUS_HS_CPU

PPDCIN_G3H

MIN_LINE_WIDTH=0.0900
MIN_NECK_WIDTH=0.0750
VOLTAGE=20V
MAKE_BASE=TRUE

PPDCIN_G3H
PPDCIN_G3H

PP5V_G3S

MIN_LINE_WIDTH=0.0900
MIN_NECK_WIDTH=0.0750
VOLTAGE=5V
MAKE_BASE=TRUE

PP5V_G3S
PP5V_G3S
PP5V_G3S
PP5V_G3S
PP5V_G3S
PP5V_G3S
PP5V_G3S
PP5V_G3S

PP5V_G3S
PP5V_G3S
PP5V_G3S
PP5V_G3S

44

44

55

68

44

44

49

46

53 75

44

64

40

79

57

58

59

61

46

56

44

53

65

69

68

48

69

57 58

51

24

24

25

25

3V3 Rails

U6960 - 3V3_G3H_RTC

79 78

PP3V3_G3H_RTC

55

Sourced from PBus
Enabled by CHGR_EN_MVR

PP3V3_G3H_RTC

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.0750
VOLTAGE=3.3V
MAKE_BASE=TRUE

PP3V3_G3H_RTC
PP3V3_G3H_RTC
PP3V3_G3H_RTC

PP3V3_G3H_RTC
PP3V3_G3H_RTC
PP3V3_G3H_RTC
PP3V3_G3H_RTC
PP3V3_G3H_RTC

78 59

66

63

49

55

64

55

23 24 27

25 27

U7550 - 3V3_G3H VDD_MAIN

PP3V3_G3H

60

PP3V3_G3H

63

Sourced from PBus
Enabled by PMU_VDDMAIN_EN

VOUT_RTC sourced from

PP3V3_G3H_RTC input to PMIC

79 78 56

79 78 60 59

PP3V3_G3H

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.0750
VOLTAGE=3.3V
MAKE_BASE=TRUE

PP3V3_G3H
PP3V3_G3H
PP3V3_G3H
PP3V3_G3H
PP3V3_G3H
PP3V3_G3H
PP3V3_G3H

PP3V3_G3H
PP3V3_G3H
PP3V3_G3H
PP3V3_G3H
PP3V3_G3H
PP3V3_G3H
PP3V3_G3H
PP3V3_G3H
PP3V3_G3H
PP3V3_G3H

PP3V3_G3H
PP3V3_G3H

79 78 65

45

66

63

63

45

66

66

63

66

66

66

60

17

18 81

55

53

49

69

67

U8225 - 3V3 Sensors

PP3V3_G3SSW_SNS

66

Sourced from 3V3_G3H_RTC
Enabled by SENSOR_PWR_EN

PP3V3_G3SSW_SNS

MIN_LINE_WIDTH=0.0900
MIN_NECK_WIDTH=0.0750
VOLTAGE=3.3V
MAKE_BASE=TRUE

PP3V3_G3SSW_SNS
PP3V3_G3SSW_SNS

44

44 45 46

U8210 - 3V3_G3S

U8220 - 1V8_G3S

PP1V8_G3S

66

Sourced from 1V8 SLEEPS2R
Enabled by P1V8G3S_EN

CPU/PCH Rails

U7210, U7230 - VCCIN

PPVCC_S0_CPU

58

Sourced from PBus
Enabled by CPU_VR_EN

U7400 - VCCIN_AUX

PPVCCIN_AUX_PCH

59

Sourced from PBus
Enabled by P1V8PRIM_PGOOD

U7700 - VCCPRIM_1P8

PP1V8_PRIM_PCH

61

Sourced from PBus
Enabled by PM_SLP_SUS_L

1V8 Rails

PP1V8_G3S

MIN_LINE_WIDTH=0.0800
MIN_NECK_WIDTH=0.2000
VOLTAGE=1.8V
MAKE_BASE=TRUE

PP1V8_G3S
PP1V8_G3S
PP1V8_G3S
PP1V8_G3S
PP1V8_G3S
PP1V8_G3S
PP1V8_G3S

PP1V8_G3S
PP1V8_G3S
PP1V8_G3S
PP1V8_G3S
PP1V8_G3S
PP1V8_G3S

PP1V8_G3S
PP1V8_G3S

PPVCC_S0_CPU

MIN_LINE_WIDTH=9.0000
MIN_NECK_WIDTH=0.0750
VOLTAGE=1.8V
MAKE_BASE=TRUE

PPVCC_S0_CPU

PPVCCIN_AUX_PCH

MIN_LINE_WIDTH=9.0000
MIN_NECK_WIDTH=0.0750
VOLTAGE=1.8V
MAKE_BASE=TRUE

PPVCCIN_AUX_PCH
PPVCCIN_AUX_PCH

MIN_LINE_WIDTH=0.1000
MIN_NECK_WIDTH=0.2000
VOLTAGE=1.8V
MAKE_BASE=TRUE

PP1V8_PRIM_PCH
PP1V8_PRIM_PCH
PP1V8_PRIM_PCH
PP1V8_PRIM_PCH
PP1V8_PRIM_PCH

PP1V8_PRIM_PCH
PP1V8_PRIM_PCH
PP1V8_PRIM_PCH

PP1V8_PRIM_PCH

PP1V8_PRIM_PCH

79 78

48

43

43 69

43

42

43

40

60

41

52 53

47

54

29

41

49 50 52

79 78

8 11 46

80 59 11

9

46

9 12 66

D

C

79 78 59 16

18 32

9

12

9

9

64

6 13 15

42

B

A

U7550 - 5V LDO - UNUSED

PP5V_S5_LDO

60

Sensed Rails

PPVIN_G3H_P5VG3S

44 60

PPVIN_G3H_P3V3G3H

44 60

PPVIN_G3H_P3V3G3HRTC

55

PP3V3_G3H_PMU_VDDMAIN

45 62

PP3V3_G3S_WLANBT

29 45

PP1SR3V3_G3H_P0V6_S3_VIN

45 65

PPBUS_G3H_SSD0

46 72

PPBUS_G3H

53 75

PPVIN_G3H_P1V1_S3

46 65

Digital Ground

GND

VOLTAGE=0V
MIN_LINE_WIDTH=0.0900
MIN_NECK_WIDTH=0.0750

PP5V_S5_LDO

MIN_LINE_WIDTH=0.0900
MIN_NECK_WIDTH=0.0750
VOLTAGE=5V
MAKE_BASE=TRUE

PPVIN_G3H_P5VG3S

MIN_LINE_WIDTH=0.1000
MIN_NECK_WIDTH=0.2000
VOLTAGE=13.1V
MAKE_BASE=TRUE

PPVIN_G3H_P3V3G3H

MIN_LINE_WIDTH=0.1000
MIN_NECK_WIDTH=0.2000
VOLTAGE=13.1V
MAKE_BASE=TRUE

PPVIN_G3H_P3V3G3HRTC

MIN_LINE_WIDTH=0.1000
MIN_NECK_WIDTH=0.2000
VOLTAGE=13.1V
MAKE_BASE=TRUE

PP3V3_G3H_PMU_VDDMAIN

MIN_LINE_WIDTH=0.1000
MIN_NECK_WIDTH=0.2000
VOLTAGE=3.3V
MAKE_BASE=TRUE

PP3V3_G3S_WLANBT

MIN_LINE_WIDTH=0.1000
MIN_NECK_WIDTH=0.2000
VOLTAGE=3.3V
MAKE_BASE=TRUE

PP1SR3V3_G3H_P0V6_S3_VIN

MIN_LINE_WIDTH=0.1000
MIN_NECK_WIDTH=0.2000
VOLTAGE=3.3V
MAKE_BASE=TRUE

PPBUS_G3H_SSD0

MIN_LINE_WIDTH=0.1000
MIN_NECK_WIDTH=0.2000
VOLTAGE=13.1V
MAKE_BASE=TRUE

PPBUS_G3H

MIN_LINE_WIDTH=0.1000
MIN_NECK_WIDTH=0.2000
VOLTAGE=13.1V
MAKE_BASE=TRUE

PPVIN_G3H_P1V1_S3

MIN_LINE_WIDTH=0.1000
MIN_NECK_WIDTH=0.2000
VOLTAGE=13.1V
MAKE_BASE=TRUE

79

79

79

78

79

PP3V3_G3S

66

Sourced from 3V3_G3H_RTC
Enabled by P3V3G3S_EN

PPBUS_G3H_SPKRL

44 50

U9080 - NAND 2V7

PPVCC_NAND_SSD0

72

Sourced from PBUS
Enabled by VR_P2V7_EN

GND

64

PP3V3_G3S

MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.0750
VOLTAGE=3.3V
MAKE_BASE=TRUE

PP3V3_G3S
PP3V3_G3S
PP3V3_G3S
PP3V3_G3S
PP3V3_G3S
PP3V3_G3S

PPBUS_G3H_SPKRL

MIN_LINE_WIDTH=0.1000
MIN_NECK_WIDTH=0.2000
VOLTAGE=13.1V
MAKE_BASE=TRUE

PPVCC_NAND_SSD0

MIN_LINE_WIDTH=0.0900
MIN_NECK_WIDTH=0.0750
VOLTAGE=2.7V
MAKE_BASE=TRUE

PPVCC_NAND_SSD0

PPVCC_NAND_SSD0

51

53

41

69

54

45

46

73

79 78

PP1V8_PRIM_PCH
PP1V8_PRIM_PCH
PP1V8_PRIM_PCH

66

18

18

The power nets below were transferred

B

from Calpe BUCK3 SW3

PP1V8_PRIM_PCH
PP1V8_PRIM_PCH
PP1V8_PRIM_PCH
PP1V8_PRIM_PCH
PP1V8_PRIM_PCH
PP1V8_PRIM_PCH

42

17

57

39

39

39

Memory Rails

U8100 - Memory VDD2, VDDCA, VDDQ; CPU VDDQ

65

PP1V1_S3

Sourced from PBUS
Enabled by P1V1_S3_EN

1.1V Rails

79 78 71 70

PP1V1_S3

MIN_NECK_WIDTH=0.0750
VOLTAGE=1.1V
MAKE_BASE=TRUE

PP1V1_S3
PP1V1_S3
PP1V1_S3
PP1V1_S3

79 78

7

8 11

66

19 20 65

0.6V Rails

65

PP0V6_S3

Sourced from PP3V3_G3H
Enabled by P1V1_S3_PGOOD

PP0V6_S3

MIN_LINE_WIDTH=2.7000
MIN_NECK_WIDTH=0.0750
VOLTAGE=0.6V
MAKE_BASE=TRUE

PP0V6_S3

80

19 20 65

SYNC_MASTER=X589_CPU_CNL_Y SYNC_DATE=02/21/2017

PAGE TITLE

Power Aliases - 2

SIZE

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

051-05232

REVISION

2.0.0

BRANCH

proto4b

PAGE

121 OF 152

SHEET

75 OF 86

A

D

8

67

35 4

2

1

678

www.laptoprepairsecrets.com

3 245

1

D

Unused CPU/PCH Signals

15

15

15

15

15

15

15

15

IN
IN

IN
IN
IN
IN
IN
IN

NC_PCIE_CLK100M_DEBUGP
NC_PCIE_CLK100M_DEBUGN

NC_PCIE_PCH_ENETSD_D2RP
NC_PCIE_PCH_ENETSD_D2RN
NC_PCIE_PCH_ENETSD_R2DCP
NC_PCIE_PCH_ENETSD_R2DCN
NC_PCIE_CLK100M_ENETSDP
NC_PCIE_CLK100M_ENETSDN

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

NO_TEST=1
NO_TEST=1

NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1

NC_PCIE_CLK100M_DEBUGP
NC_PCIE_CLK100M_DEBUGN

NC_PCIE_PCH_ENETSD_D2RP
NC_PCIE_PCH_ENETSD_D2RN
NC_PCIE_PCH_ENETSD_R2DCP
NC_PCIE_PCH_ENETSD_R2DCN
NC_PCIE_CLK100M_ENETSDP
NC_PCIE_CLK100M_ENETSDN

Unused SoC Signals

NC_ALTIMETER_INT

32

NC_DFR_DISP_INT

31

NC_DFR_DISP_RESET_L

33

NC_DFR_DISP_TE

33

NC_DFR_TOUCH_CLK32K_RESET_L

33

NC_DFR_TOUCH_INT_L

32

NC_DFR_TOUCH_RESET_L

33

NC_DFR_TOUCH_RSVD

33

NC_DISP_GCON_INT_L

32

NC_ENET_LOW_PWR

32

NC_ENET_MEDIA_SENSE

32

NC_ENET_RESET_L

34

NC_FTCAM_CLK12M_R

33

NC_FTCAM_RESET_L

33

NC_GNSS_DEV_WAKE

31

NC_GNSS_HOST_TIME

31

NC_GNSS_HOST_WAKE

32

NC_I2S_CODEC_MCLK

33

NC_I2S_CODEC1_MCLK

33

NC_I2S_CODEC1_R2D_R

33

NC_I2S_HAWKING_BCLK_R

33

NC_I2S_HAWKING_D2R

33

NC_I2S_HAWKING_LRCLK

33

NC_MESA_MENUKEY_L

32

NC_MIPI_DFR_CLKN

33

NC_MIPI_DFR_CLKP

33

NC_MIPI_DFR_DATAN

33

NC_MIPI_DFR_DATAP

33

NC_PCC_EVENT

32

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1

NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1

NC_ALTIMETER_INT
NC_DFR_DISP_INT
NC_DFR_DISP_RESET_L
NC_DFR_DISP_TE

NC_DFR_TOUCH_CLK32K_RESET_L
NC_DFR_TOUCH_INT_L
NC_DFR_TOUCH_RESET_L
NC_DFR_TOUCH_RSVD
NC_DISP_GCON_INT_L
NC_ENET_LOW_PWR
NC_ENET_MEDIA_SENSE
NC_ENET_RESET_L
NC_FTCAM_CLK12M_R
NC_FTCAM_RESET_L
NC_GNSS_DEV_WAKE
NC_GNSS_HOST_TIME
NC_GNSS_HOST_WAKE
NC_I2S_CODEC_MCLK
NC_I2S_CODEC1_MCLK
NC_I2S_CODEC1_R2D_R
NC_I2S_HAWKING_BCLK_R
NC_I2S_HAWKING_D2R
NC_I2S_HAWKING_LRCLK
NC_MESA_MENUKEY_L
NC_MIPI_DFR_CLKN
NC_MIPI_DFR_CLKP
NC_MIPI_DFR_DATAN
NC_MIPI_DFR_DATAP
NC_PCC_EVENT

DEBUG_CLKREQ_STRAP_L

15 18

TP_SWD_WLAN_SWDIO

32

TP_SWD_WLAN_SWCLK

32

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

DEBUG_CLKREQ_STRAP_L
TP_SWD_WLAN_SWDIO
TP_SWD_WLAN_SWCLK

D

C

B

A

Unused Misc Signals

NC_PMU_CLK32K_GNSS_R

64

NC_GPU_THRMTRIP

64

NC_P3V3G3W_EN

64

NC_CHGR_EN_VR1

56

NC_CHGR_AUX_OK

56

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1

NC_PMU_CLK32K_GNSS_R
NC_GPU_THRMTRIP
NC_P3V3G3W_EN
NC_CHGR_EN_VR1
NC_CHGR_AUX_OK

NC_PCIE_CLK100M_ENETN

34

NC_PCIE_CLK100M_ENETP

34

NC_PCIE_CLK100M_SSD1_01N

34

NC_PCIE_CLK100M_SSD1_01P

34

NC_PCIE_CLK100M_SSD1_23N

34

NC_PCIE_CLK100M_SSD1_23P

34

NC_PCIE_CLK100M_WLANN

34

NC_PCIE_CLK100M_WLANP

34

NC_PCIE_ENET_D2RN

34

NC_PCIE_ENET_D2RP

34

NC_PCIE_ENET_R2D_CN

34

NC_PCIE_ENET_R2D_CP

34

NC_PCIE_SSD1_D2RN<3..0>

34

NC_PCIE_SSD1_D2RP<3..0>

34

NC_PCIE_SSD1_R2D_CN<3..0>

34

NC_PCIE_SSD1_R2D_CP<3..0>

34

NC_PCIE_WLAN_D2RN

34

NC_PCIE_WLAN_D2RP

34

NC_PCIE_WLAN_R2D_CN

34

NC_PCIE_WLAN_R2D_CP

34

NC_PCIEDN_WAKE_L

32

NC_PLCAM_PROX_INT_L

32

NC_PLCAM_ROMEO_B2B_DETECT

32

NC_PLCAM_RX_CLK12M_R

33

NC_PLCAM_RX_RESET_L

33

NC_PLCAM_TX_CLK12M_R

33

NC_PLCAM_TX_INT

33

NC_PLCAM_TX_RESET_L

33

NC_PLCAM_TX_THROTTLE

31

NC_SDCONN_STATE_CHANGE_L

32

NC_SMC_FAN_1_PWM

32

NC_SMC_FAN_1_TACH

32

NC_SMC_GFX_SELF_THROTTLE

32

NC_SMC_GFX_THROTTLE_L

32

NC_SMC_LED_ONEWIRE

32

NC_SPI_ALTIMETER_CS_L

32

NC_SSD1_CLK24M_R

34

NC_SSD1_CLKREQ0_L

34

NC_SSD1_CLKREQ1_L

34

NC_SSD1_CLKREQ2_L

34

NC_SSD1_CLKREQ3_L

34

NC_SSD1_PCIE_RESET_L

34

NC_SSD1_SWCLK_UART_R2D

32

NC_SSD1_SWDIO_UART_D2R

32

NC_TPAD_VIBE_L

32

NC_UART_GNSS_D2R_CTS_L

33

NC_UART_GNSS_R2D_RTS_L

33

NC_UART_GNSS_R2D

33

NC_UART_GNSS_D2R

33

NC_WLAN_CLKREQ_L

34

NC_WLAN_DEV_WAKE

31

NC_WLAN_PERST_L

34

NC_SPI_DFR_CS_L

33

NC_SPI_DFR_CLK_R

33

NC_SPI_DFR_MOSI_R

33

NC_SPI_DFR_MISO

33

NC_PCHROM_SW_EN

33

NC_HDMI_RESET_L

6

NC_UART_BT_D2R

33

NC_UART_BT_R2D

33

NC_UART_BT_R2D_RTS_L

33

NC_UART_BT_D2R_CTS_L

33

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

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MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1

NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1

NC_PCIE_CLK100M_ENETN
NC_PCIE_CLK100M_ENETP
NC_PCIE_CLK100M_SSD1_01N
NC_PCIE_CLK100M_SSD1_01P
NC_PCIE_CLK100M_SSD1_23N
NC_PCIE_CLK100M_SSD1_23P
NC_PCIE_CLK100M_WLANN
NC_PCIE_CLK100M_WLANP
NC_PCIE_ENET_D2RN
NC_PCIE_ENET_D2RP
NC_PCIE_ENET_R2D_CN
NC_PCIE_ENET_R2D_CP
NC_PCIE_SSD1_D2RN<3..0>
NC_PCIE_SSD1_D2RP<3..0>
NC_PCIE_SSD1_R2D_CN<3..0>
NC_PCIE_SSD1_R2D_CP<3..0>
NC_PCIE_WLAN_D2RN
NC_PCIE_WLAN_D2RP
NC_PCIE_WLAN_R2D_CN
NC_PCIE_WLAN_R2D_CP
NC_PCIEDN_WAKE_L
NC_PLCAM_PROX_INT_L
NC_PLCAM_ROMEO_B2B_DETECT
NC_PLCAM_RX_CLK12M_R
NC_PLCAM_RX_RESET_L
NC_PLCAM_TX_CLK12M_R
NC_PLCAM_TX_INT
NC_PLCAM_TX_RESET_L
NC_PLCAM_TX_THROTTLE
NC_SDCONN_STATE_CHANGE_L
NC_SMC_FAN_1_PWM
NC_SMC_FAN_1_TACH
NC_SMC_GFX_SELF_THROTTLE
NC_SMC_GFX_THROTTLE_L
NC_SMC_LED_ONEWIRE
NC_SPI_ALTIMETER_CS_L
NC_SSD1_CLK24M_R
NC_SSD1_CLKREQ0_L
NC_SSD1_CLKREQ1_L
NC_SSD1_CLKREQ2_L
NC_SSD1_CLKREQ3_L
NC_SSD1_PCIE_RESET_L
NC_SSD1_SWCLK_UART_R2D
NC_SSD1_SWDIO_UART_D2R
NC_TPAD_VIBE_L
NC_UART_GNSS_D2R_CTS_L
NC_UART_GNSS_R2D_RTS_L
NC_UART_GNSS_R2D
NC_UART_GNSS_D2R
NC_WLAN_CLKREQ_L
NC_WLAN_DEV_WAKE
NC_WLAN_PERST_L
NC_SPI_DFR_CS_L
NC_SPI_DFR_CLK_R
NC_SPI_DFR_MOSI_R
NC_SPI_DFR_MISO
NC_PCHROM_SW_EN
NC_HDMI_RESET_L

NC_UART_BT_D2R
NC_UART_BT_R2D
NC_UART_BT_R2D_RTS_L
NC_UART_BT_D2R_CTS_L

Grounded Signals

GND

33

GND

33

GND

33

GND

33

GND

33

GND

33

GND

33

GND

33

GND

64

PMIC GPIO Config Select

PVCCNAND_PGOOD

64

PVCCNAND_EN

64

NAND_DISCHARGE_EN

64

NAND_RESET_L

64

UVP_DIS_L

64

PD_PVCCPLLOC_EN

64

PAGE TITLE

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

PVCCNAND_PGOOD
PVCCNAND_EN
NAND_DISCHARGE_EN
NAND_RESET_L
UVP_DIS_L
PD_PVCCPLLOC_EN

Signal Aliases

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:

DRAWING NUMBER

051-05232

REVISION

2.0.0

BRANCH

proto4b

PAGE

122 OF 152

SHEET

76 OF 86

C

B

72

72

73

73

40

A

SIZE

D

8

67

35 4

2

1

678

www.laptoprepairsecrets.com

3 245

1

Memory Bit & Byte Swizzle

D

77 7

77 7

77 7

77 7

77 7

77 7

77 7

77 7

77 7

77 7

77 7

77 7

MEM_A_CS_L<0>

IN

MEM_A_CS_L<1>

IN

MEM_A_CLK_P

IN

MEM_A_CLK_N

IN

MEM_A_CKE<0>

IN

MEM_A_CKE<1>

IN

MEM_A_CA<0>

IN

MEM_A_CA<1>

IN

MEM_A_CA<2>

IN

MEM_A_CA<3>

IN

MEM_A_CA<4>

IN

MEM_A_CA<5>

IN

MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE

MEM_A_CS_L<0>
MEM_A_CS_L<1>
MEM_A_CLK_P
MEM_A_CLK_N
MEM_A_CKE<0>
MEM_A_CKE<1>
MEM_A_CA<0>
MEM_A_CA<1>
MEM_A_CA<2>
MEM_A_CA<3>
MEM_A_CA<4>
MEM_A_CA<5>

OUT
OUT

OUT
OUT
OUT

OUT
OUT
OUT
OUT
OUT
OUT
OUT

19

19

19

19

19

19

19

19

19

19

19

19

DRAM Pins

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

MEM_A_DQ_0<0>
MEM_A_DQ_0<1>
MEM_A_DQ_0<2>
MEM_A_DQ_0<3>
MEM_A_DQ_0<4>
MEM_A_DQ_0<5>
MEM_A_DQ_0<6>
MEM_A_DQ_0<7>
MEM_A_DQS_N<0>
MEM_A_DQS_P<0>

MEM_A_DQ_1<0>
MEM_A_DQ_1<1>
MEM_A_DQ_1<2>
MEM_A_DQ_1<3>
MEM_A_DQ_1<4>
MEM_A_DQ_1<5>
MEM_A_DQ_1<6>
MEM_A_DQ_1<7>
MEM_A_DQS_N<1>
MEM_A_DQS_P<1>

MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE

MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE

MEM_A_DQ_0<0>
MEM_A_DQ_0<1>
MEM_A_DQ_0<2>
MEM_A_DQ_0<3>
MEM_A_DQ_0<4>
MEM_A_DQ_0<5>
MEM_A_DQ_0<6>
MEM_A_DQ_0<7>
MEM_A_DQS_N<0>
MEM_A_DQS_P<0>

MEM_A_DQ_1<0>
MEM_A_DQ_1<1>
MEM_A_DQ_1<2>
MEM_A_DQ_1<3>
MEM_A_DQ_1<4>
MEM_A_DQ_1<5>
MEM_A_DQ_1<6>
MEM_A_DQ_1<7>
MEM_A_DQS_N<1>
MEM_A_DQS_P<1>

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

CPU PinsCPU Pins DRAM Pins

MEM_C_DQ_0<0>
MEM_C_DQ_0<1>
MEM_C_DQ_0<2>
MEM_C_DQ_0<3>
MEM_C_DQ_0<4>
MEM_C_DQ_0<5>
MEM_C_DQ_0<6>
MEM_C_DQ_0<7>
MEM_C_DQS_N<0>
MEM_C_DQS_P<0>

MEM_C_DQ_1<0>
MEM_C_DQ_1<1>
MEM_C_DQ_1<2>
MEM_C_DQ_1<3>
MEM_C_DQ_1<4>
MEM_C_DQ_1<5>
MEM_C_DQ_1<6>
MEM_C_DQ_1<7>
MEM_C_DQS_N<1>
MEM_C_DQS_P<1>

MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE

MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE

MEM_C_DQ_0<0>
MEM_C_DQ_0<1>
MEM_C_DQ_0<2>
MEM_C_DQ_0<3>
MEM_C_DQ_0<4>
MEM_C_DQ_0<5>
MEM_C_DQ_0<6>
MEM_C_DQ_0<7>
MEM_C_DQS_N<0>
MEM_C_DQS_P<0>

MEM_C_DQ_1<0>
MEM_C_DQ_1<1>
MEM_C_DQ_1<2>
MEM_C_DQ_1<3>
MEM_C_DQ_1<4>
MEM_C_DQ_1<5>
MEM_C_DQ_1<6>
MEM_C_DQ_1<7>
MEM_C_DQS_N<1>
MEM_C_DQS_P<1>

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

20

20

20

20

20

20

20

20

20

20

20

20

20

20

20

20

20

20

20

20

77 7

77 7

77 7

77 7

77 7

77 7

77 7

77 7

77 7

77 7

77 7

77 7

MEM_C_CS_L<0>

IN

MEM_C_CS_L<1>

IN

MEM_C_CLK_P

IN

MEM_C_CLK_N

IN

MEM_C_CKE<0>

IN

MEM_C_CKE<1>

IN

MEM_C_CA<0>

IN

MEM_C_CA<1>

IN

MEM_C_CA<2>

IN

MEM_C_CA<3>

IN

MEM_C_CA<4>

IN

MEM_C_CA<5>

IN

MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE

MEM_C_CS_L<0>
MEM_C_CS_L<1>
MEM_C_CLK_P
MEM_C_CLK_N
MEM_C_CKE<0>
MEM_C_CKE<1>
MEM_C_CA<0>
MEM_C_CA<1>
MEM_C_CA<2>
MEM_C_CA<3>
MEM_C_CA<4>
MEM_C_CA<5>

OUT
OUT

OUT
OUT
OUT

OUT
OUT
OUT
OUT
OUT
OUT
OUT

20

20

20

20

20

20

20

20

20

20

20

20

D

C

77 7

77 7

77 7

77 7

77 7

77 7

77 7

77 7

77 7

77

77 7

77 7

7

BI

7

BI

7

BI

7

MEM_A_CS_L<0>

IN

MEM_A_CS_L<1>

IN

MEM_A_CLK_P

IN

MEM_A_CLK_N

IN

MEM_A_CKE<0>

IN

MEM_A_CKE<1>

IN

MEM_A_CA<0>

IN

MEM_A_CA<1>

IN

MEM_A_CA<2>

IN

7

MEM_A_CA<3>

IN

MEM_A_CA<4>

IN

MEM_A_CA<5>

IN

MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE

MEM_A_CS_L<0>
MEM_A_CS_L<1>
MEM_A_CLK_P
MEM_A_CLK_N
MEM_A_CKE<0>
MEM_A_CKE<1>
MEM_A_CA<0>
MEM_A_CA<1>
MEM_A_CA<2>
MEM_A_CA<3>
MEM_A_CA<4>
MEM_A_CA<5>

OUT
OUT

OUT
OUT
OUT

OUT
OUT
OUT
OUT
OUT
OUT
OUT

19

19

19

19

19

19

19

19

19

19

19

19

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

MEM_A_DQ_2<0>
MEM_A_DQ_2<1>
MEM_A_DQ_2<2>
MEM_A_DQ_2<3>
MEM_A_DQ_2<4>
MEM_A_DQ_2<5>
MEM_A_DQ_2<6>
MEM_A_DQ_2<7>
MEM_A_DQS_N<2>
MEM_A_DQS_P<2>

MEM_A_DQ_3<0>
MEM_A_DQ_3<1>
MEM_A_DQ_3<2>
MEM_A_DQ_3<3>
MEM_A_DQ_3<4>
MEM_A_DQ_3<5>
MEM_A_DQ_3<6>
MEM_A_DQ_3<7>
MEM_A_DQS_N<3>
MEM_A_DQS_P<3>

MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE

MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE

MEM_A_DQ_2<0>
MEM_A_DQ_2<1>
MEM_A_DQ_2<2>
MEM_A_DQ_2<3>
MEM_A_DQ_2<4>
MEM_A_DQ_2<5>
MEM_A_DQ_2<6>
MEM_A_DQ_2<7>
MEM_A_DQS_N<2>
MEM_A_DQS_P<2>

MEM_A_DQ_3<0>
MEM_A_DQ_3<1>
MEM_A_DQ_3<2>
MEM_A_DQ_3<3>
MEM_A_DQ_3<4> MEM_C_DQ_3<4>
MEM_A_DQ_3<5>
MEM_A_DQ_3<6>
MEM_A_DQ_3<7>
MEM_A_DQS_N<3>
MEM_A_DQS_P<3>

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

MEM_C_DQ_2<0>
MEM_C_DQ_2<1>
MEM_C_DQ_2<2>
MEM_C_DQ_2<3>
MEM_C_DQ_2<4>
MEM_C_DQ_2<5>
MEM_C_DQ_2<6>
MEM_C_DQ_2<7>
MEM_C_DQS_N<2>
MEM_C_DQS_P<2>

MEM_C_DQ_3<0>
MEM_C_DQ_3<1>
MEM_C_DQ_3<2>
MEM_C_DQ_3<3>
MEM_C_DQ_3<4>
MEM_C_DQ_3<5>
MEM_C_DQ_3<6>
MEM_C_DQ_3<7>
MEM_C_DQS_N<3>
MEM_C_DQS_P<3>

MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE

MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUEMAKE_BASE=TRUE

MEM_C_DQ_2<0>
MEM_C_DQ_2<1>
MEM_C_DQ_2<2>
MEM_C_DQ_2<3>
MEM_C_DQ_2<4>
MEM_C_DQ_2<5>
MEM_C_DQ_2<6>
MEM_C_DQ_2<7>
MEM_C_DQS_N<2>
MEM_C_DQS_P<2>

MEM_C_DQ_3<0>
MEM_C_DQ_3<1>
MEM_C_DQ_3<2>
MEM_C_DQ_3<3>

MEM_C_DQ_3<5>
MEM_C_DQ_3<6>
MEM_C_DQ_3<7>
MEM_C_DQS_N<3>
MEM_C_DQS_P<3>

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

20

20

20

20

20

20

20

20

20

20

20

20

20

20

20

20

20

20

20

20

77 7

77 7

77 7

77 7

77 7

77 7

77 7

77 7

77 7

77 7

77 7

77 7

MEM_C_CS_L<0>

IN

MEM_C_CS_L<1>

IN

MEM_C_CLK_P

IN

MEM_C_CLK_N

IN

MEM_C_CKE<0>

IN

MEM_C_CKE<1>

IN

MEM_C_CA<0>

IN

MEM_C_CA<1>

IN

MEM_C_CA<2>

IN

MEM_C_CA<3>

IN

MEM_C_CA<4>

IN

MEM_C_CA<5>

IN

MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE

MEM_C_CS_L<0>
MEM_C_CS_L<1>
MEM_C_CLK_P
MEM_C_CLK_N
MEM_C_CKE<0>
MEM_C_CKE<1>
MEM_C_CA<0>
MEM_C_CA<1>
MEM_C_CA<2>
MEM_C_CA<3>
MEM_C_CA<4>
MEM_C_CA<5>

OUT
OUT

OUT
OUT
OUT

OUT
OUT
OUT
OUT
OUT
OUT
OUT

20

20

20

20

20

20

20

20

20

20

20

20

C

B

A

77 7

77 7

77 7

77 7

77 7

77 7

77 7

77 7

77 7

77 7

77 7

77 7

77 7

77 7

77 7

77 7

77 7

77 7

77 7

77 7

77 7

77 7

77 7

77 7

MEM_B_CS_L<0>

IN

MEM_B_CS_L<1>

IN

MEM_B_CLK_P

IN

MEM_B_CLK_N

IN

MEM_B_CKE<0>

IN

MEM_B_CKE<1>

IN

MEM_B_CA<0>

IN

MEM_B_CA<1>

IN

MEM_B_CA<2>

IN

MEM_B_CA<3>

IN

MEM_B_CA<4>

IN

MEM_B_CA<5>

IN

MEM_B_CS_L<0>

IN

MEM_B_CS_L<1>

IN

MEM_B_CLK_P

IN

MEM_B_CLK_N

IN

MEM_B_CKE<0>

IN

MEM_B_CKE<1>

IN

MEM_B_CA<0>

IN

MEM_B_CA<1>

IN

MEM_B_CA<2>

IN

MEM_B_CA<3>

IN

MEM_B_CA<4>

IN

MEM_B_CA<5>

IN

MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE

MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE

MEM_B_CS_L<0>
MEM_B_CS_L<1>
MEM_B_CLK_P
MEM_B_CLK_N
MEM_B_CKE<0>
MEM_B_CKE<1>
MEM_B_CA<0>
MEM_B_CA<1>
MEM_B_CA<2>
MEM_B_CA<3>
MEM_B_CA<4>
MEM_B_CA<5>

MEM_B_CS_L<0>
MEM_B_CS_L<1>
MEM_B_CLK_P
MEM_B_CLK_N
MEM_B_CKE<0>
MEM_B_CKE<1>
MEM_B_CA<0>
MEM_B_CA<1>
MEM_B_CA<2>
MEM_B_CA<3>
MEM_B_CA<4>
MEM_B_CA<5>

OUT
OUT

OUT
OUT
OUT

OUT
OUT
OUT
OUT
OUT
OUT
OUT

OUT
OUT

OUT

OUT

OUT

OUT
OUT
OUT
OUT
OUT
OUT
OUT

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

MEM_B_DQ_0<0>
MEM_B_DQ_0<1>
MEM_B_DQ_0<2>
MEM_B_DQ_0<3>
MEM_B_DQ_0<4>
MEM_B_DQ_0<5>
MEM_B_DQ_0<6>
MEM_B_DQ_0<7>
MEM_B_DQS_N<0>
MEM_B_DQS_P<0>

MEM_B_DQ_1<0>
MEM_B_DQ_1<1>
MEM_B_DQ_1<2>
MEM_B_DQ_1<3>
MEM_B_DQ_1<4>
MEM_B_DQ_1<5>
MEM_B_DQ_1<6>
MEM_B_DQ_1<7>
MEM_B_DQS_N<1>
MEM_B_DQS_P<1>

MEM_B_DQ_2<0>
MEM_B_DQ_2<1>
MEM_B_DQ_2<2>
MEM_B_DQ_2<3>
MEM_B_DQ_2<4>
MEM_B_DQ_2<5>
MEM_B_DQ_2<6>
MEM_B_DQ_2<7>
MEM_B_DQS_N<2>
MEM_B_DQS_P<2>

MEM_B_DQ_3<0>
MEM_B_DQ_3<1>
MEM_B_DQ_3<2>
MEM_B_DQ_3<3>
MEM_B_DQ_3<4>
MEM_B_DQ_3<5>
MEM_B_DQ_3<6>
MEM_B_DQ_3<7>
MEM_B_DQS_N<3>
MEM_B_DQS_P<3>

MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE

MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE

MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE

MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE

MEM_B_DQ_0<0>
MEM_B_DQ_0<1>
MEM_B_DQ_0<2>
MEM_B_DQ_0<3>
MEM_B_DQ_0<4>
MEM_B_DQ_0<5>
MEM_B_DQ_0<6>
MEM_B_DQ_0<7>
MEM_B_DQS_N<0>
MEM_B_DQS_P<0>

MEM_B_DQ_1<0>
MEM_B_DQ_1<1>
MEM_B_DQ_1<2>
MEM_B_DQ_1<3>
MEM_B_DQ_1<4>
MEM_B_DQ_1<5>
MEM_B_DQ_1<6>
MEM_B_DQ_1<7>
MEM_B_DQS_N<1>
MEM_B_DQS_P<1>

MEM_B_DQ_2<0>
MEM_B_DQ_2<1>
MEM_B_DQ_2<2>
MEM_B_DQ_2<3>
MEM_B_DQ_2<4>
MEM_B_DQ_2<5>
MEM_B_DQ_2<6>
MEM_B_DQ_2<7>
MEM_B_DQS_N<2>
MEM_B_DQS_P<2>

MEM_B_DQ_3<0>
MEM_B_DQ_3<1>
MEM_B_DQ_3<2>
MEM_B_DQ_3<3>
MEM_B_DQ_3<4>
MEM_B_DQ_3<5>
MEM_B_DQ_3<6>
MEM_B_DQ_3<7>
MEM_B_DQS_N<3>
MEM_B_DQS_P<3>

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

MEM_D_DQ_0<0>
MEM_D_DQ_0<1>
MEM_D_DQ_0<2>
MEM_D_DQ_0<3>
MEM_D_DQ_0<4>
MEM_D_DQ_0<5>
MEM_D_DQ_0<6>
MEM_D_DQ_0<7>
MEM_D_DQS_N<0>
MEM_D_DQS_P<0>

MEM_D_DQ_1<0>
MEM_D_DQ_1<1>
MEM_D_DQ_1<2>
MEM_D_DQ_1<3>
MEM_D_DQ_1<4>
MEM_D_DQ_1<5>
MEM_D_DQ_1<6>
MEM_D_DQ_1<7>
MEM_D_DQS_N<1>
MEM_D_DQS_P<1>

MEM_D_DQ_2<0>
MEM_D_DQ_2<1>
MEM_D_DQ_2<2>
MEM_D_DQ_2<3>
MEM_D_DQ_2<4>
MEM_D_DQ_2<5>
MEM_D_DQ_2<6>
MEM_D_DQ_2<7>
MEM_D_DQS_N<2>
MEM_D_DQS_P<2>

MEM_D_DQ_3<0>
MEM_D_DQ_3<1>
MEM_D_DQ_3<2>
MEM_D_DQ_3<3>
MEM_D_DQ_3<4>
MEM_D_DQ_3<5>
MEM_D_DQ_3<6>
MEM_D_DQ_3<7>
MEM_D_DQS_N<3>
MEM_D_DQS_P<3>

MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE

MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE

MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE

MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE

MEM_D_DQ_0<0>
MEM_D_DQ_0<1>
MEM_D_DQ_0<2>
MEM_D_DQ_0<3>
MEM_D_DQ_0<4>
MEM_D_DQ_0<5>
MEM_D_DQ_0<6>
MEM_D_DQ_0<7>
MEM_D_DQS_N<0>
MEM_D_DQS_P<0>

MEM_D_DQ_1<0>
MEM_D_DQ_1<1>
MEM_D_DQ_1<2>
MEM_D_DQ_1<3>
MEM_D_DQ_1<4>
MEM_D_DQ_1<5>
MEM_D_DQ_1<6>
MEM_D_DQ_1<7>
MEM_D_DQS_N<1>
MEM_D_DQS_P<1>

MEM_D_DQ_2<0>
MEM_D_DQ_2<1>
MEM_D_DQ_2<2>
MEM_D_DQ_2<3>
MEM_D_DQ_2<4>
MEM_D_DQ_2<5>
MEM_D_DQ_2<6>
MEM_D_DQ_2<7>
MEM_D_DQS_N<2>
MEM_D_DQS_P<2>

MEM_D_DQ_3<0>
MEM_D_DQ_3<1>
MEM_D_DQ_3<2>
MEM_D_DQ_3<3>
MEM_D_DQ_3<4>
MEM_D_DQ_3<5>
MEM_D_DQ_3<6>
MEM_D_DQ_3<7>
MEM_D_DQS_N<3>
MEM_D_DQS_P<3>

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

20

20

20

20

20

20

20

20

20

20

20

20

20

20

20

20

20

20

20

20

20

20

20

20

20

20

20

20

20

20

20

20

20

20

20

20

20

20

20

20

77 7

77 7

77 7

77 7

77 7

77 7

77 7

77 7

77 7

77 7

77 7

77 7

77 7

77 7

77 7

77 7

77 7

77 7

77 7

77 7

77 7

77 7

77 7

77 7

MEM_D_CS_L<0>

IN

MEM_D_CS_L<1>

IN

MEM_D_CLK_P

IN

MEM_D_CLK_N

IN

MEM_D_CKE<0>

IN

MEM_D_CKE<1>

IN

MEM_D_CA<0>

IN

MEM_D_CA<1>

IN

MEM_D_CA<2>

IN

MEM_D_CA<3>

IN

MEM_D_CA<4>

IN

MEM_D_CA<5>

IN

MEM_D_CS_L<0>

IN

MEM_D_CS_L<1>

IN

MEM_D_CLK_P

IN

MEM_D_CLK_N

IN

MEM_D_CKE<0>

IN

MEM_D_CKE<1>

IN

MEM_D_CA<0>

IN

MEM_D_CA<1>

IN

MEM_D_CA<2>

IN

MEM_D_CA<3>

IN

MEM_D_CA<4>

IN

MEM_D_CA<5>

IN

MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE

MEM_D_CS_L<1>
MEM_D_CLK_P
MEM_D_CLK_N
MEM_D_CKE<0>
MEM_D_CKE<1>
MEM_D_CA<0>
MEM_D_CA<1>
MEM_D_CA<2>
MEM_D_CA<3>
MEM_D_CA<4>
MEM_D_CA<5>

MEM_D_CS_L<0>

MEM_D_CS_L<0>

MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE

SYNC_MASTER=J140

PAGE TITLE

MEM_D_CS_L<1>
MEM_D_CLK_P
MEM_D_CLK_N
MEM_D_CKE<0>
MEM_D_CKE<1>
MEM_D_CA<0>
MEM_D_CA<1>
MEM_D_CA<2>
MEM_D_CA<3>
MEM_D_CA<4>
MEM_D_CA<5>

Memory Bit & Byte Swizzle

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

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SYNC_DATE=08/23/2018

DRAWING NUMBER

051-05232

REVISION

2.0.0

BRANCH

proto4b

PAGE

123 OF 152

SHEET

77 OF 86

20

20

20

20

20

20

20

20

20

20

20

20

20

20

20

20

20

20

20

20

20

20

20

20

B

A

SIZE

D

8

67

35 4

2

1

678

www.laptoprepairsecrets.com

3 245

1

D

C

B

15

15

15

15

15

15

31 23

64 31 23

31 23

31 23

81 40 31 23

32 23

32

23 13

23 13

32 23

32 23

33

33

32

32

42 32

42 32

32 23

32 23

DFU/SoC/SWDL

BI
BI
BI
BI

BI
BI

USB3_FCT_D2R_N
USB3_FCT_D2R_P
USB3_FCT_R2D_C_N
USB3_FCT_R2D_C_P

USB2_FCT_N
USB2_FCT_P

BI
BI
BI
BI
BI
BI
BI

SOC_USB_VBUS
SOC_FORCE_DFU
USB_SOC_N
USB_SOC_P
SOC_DFU_STATUS
SOC_DOCK_CONNECT
SOC_COLD_RESET_L
GND

Debug

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

PCH_UART_DEBUG_D2R
PCH_UART_DEBUG_R2D
SWD_SOC_SWCLK
SWD_SOC_SWDIO
TP_SOC_DEBUGPRT_RX
TP_SOC_DEBUGPRT_TX
TP_JTAG_SOC_TDI
TP_JTAG_SOC_TDO
I2C_PWR_SCL
I2C_PWR_SDA
SMC_DEBUGPRT_RX
SMC_DEBUGPRT_TX

MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE

MAKE_BASE=TRUE
MAKE_BASE=TRUE

FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE

FUNC_TEST=TRUE

FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE

FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE

FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE

GND_VOID=TRUE

2

1

FUNC_TEST=TRUE
FUNC_TEST=TRUE

7x

MAKE_BASE=TRUE
MAKE_BASE=TRUE

MAKE_BASE=TRUE
MAKE_BASE=TRUE

USB3_FCT_D2R_N
USB3_FCT_D2R_P
USB3_FCT_R2D_C_N
USB3_FCT_R2D_C_P

SLP0603P2X3-COMBO

CRITICAL

2

RCLAMP1031ZC

1

DC4B0

SLP0603P2X3-COMBO

GND_VOID=TRUE

CRITICAL

2

RCLAMP1031ZC

1

DC4B1

GND_VOID=TRUE

CRITICAL

USB2_FCT_N
USB2_FCT_P

1

CRITICAL

DC450

2

FUNC_TEST=TRUE
FUNC_TEST=TRUE

FUNC_TEST=TRUE
FUNC_TEST=TRUE

1

TP

1

TP

1

TP

1

TP

1

TP

1

TP

1

TP

1

TP

1

TP

1

TP

SLP0603P2X3-COMBO

2

RCLAMP1031ZC

1

DC4B2

2

X3DFN2

1

ESD8011-COMBO

SLP0603P2X3-COMBO

GND_VOID=TRUE

CRITICAL

RCLAMP1031ZC

DC4B3

CRITICAL

X3DFN2

DC451

ESD8011-COMBO

TP-P5
TP-P5
TP-P5
TP-P5

TP-P5
TP-P5

TP-P5
TP-P5
TP-P5
TP-P5

TP_SOC_DEBUGPRT_RX
TP_SOC_DEBUGPRT_TX

SMC_DEBUGPRT_RX
SMC_DEBUGPRT_TX

TPDC4B3
TPDC4B2
TPDC4B1
TPDC4B0

TPDC450
TPDC451

TPDC4B7
TPDC4B6
TPDC4B5
TPDC4B4

68 5

69 5

68

69 68

69 68

69 68

79 26 23

79 26 23

79 75 56

79 56

79 78 75

79 78 74

74

74

75 59

79 75 65

74

79 78 75 60 59

79 78 75

79 78 75

79 75 59 16

74

79 75

79 75 71 70

79 74 73 71 70

79 74 71 70

79 67 27

67 27

66 39 17 11 8

74

74

74

74

74

79 75

32

Display

To be probed at connector

Backlight

BI
BI
BI
BI

BI
BI

EDP_BKLT_EN
EDP_BKLT_PWM
PPVIN_S0SW_LCDBKLT_R
PPVOUT_S0_LCDBKLT

I2C_BKLT_SCL
I2C_BKLT_SDA
GND

Power

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

BI
BI
BI
BI
BI

BI
BI

BI
BI
BI
BI
BI
BI

PP20V_USBC_X_VBUS
PP20V_USBC_T_VBUS
PPDCIN_G3H
PPDCIN_G3H_CHGR_AMON
PPBUS_G3H
PP1V8_SLPS2R
PP1V1_SLPDDR
PP1V8_AWAKE
PP3V3_G3H_RTC
PP3V3_G3H
PP3V_G3H
PP5V_G3S
PP3V3_G3S
PP1V8_G3S
PP1V8_PRIM_PCH
PP1V8_S3
PP1V1_S3

PPVCC_NAND_SSD0
PPVCCQ_ANI_SSD0
PP0V9_SSD0
PP3V3_TBT_X_S0_R
PP3V3_TBT_X_SX

PP1V05_S0_CPU_VCCST
PP1V05_PCH_EXT_REG

PP1V2_AWAKE
PP0V82_SLPDDR
PPVDDCPU_AWAKE
PPVNN_PCH_EXT_REG
PPVCC_S0_CPU
TP_SMC_FIXTURE_MODE_L

MAKE_BASE=TRUE

GND

FUNC_TEST=TRUE

FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE

FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE

FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE

FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE

FUNC_TEST=TRUE
FUNC_TEST=TRUE

FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE

TP_SMC_FIXTURE_MODE_L

FUNC_TEST=TRUE

5x

49 40

49 33

49 40

49 31

49 40 31

49

64 49

49 33

49 40

49 33

49 40

52 49 31

52 49 32

49 32

50 49 31

50 49 31

43 33

43 33

49 40

50 49 33

49 40

49 40

52 49 33

49 40

79 78 75

79 78 75

79 78 75

79 78 74

53 40

53 52

53 40

53 52

53 40

79 78 75

79 78 74

52 50

52 50

52 33

48

48

79 78 75 60 59

RIO ­Speaker (R), Mesa, Headphone

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

SPI_MESA_CLK
SPI_MESA_MISO
SPI_MESA_MOSI
MESA_INT
MESA_PWR_EN
PMU_ONOFF_R_L_CONN
AUD_PWR_EN
I2S_CODEC_LRCLK
I2S_CODEC_R2D
I2S_CODEC_D2R
I2S_CODEC_BCLK
CODEC_INT_L
CODEC_WAKE_L
CODEC_RESET_L
SPKRAMP_RESET_L
SPKRAMP_INT_L
I2C_SPKRAMP_R_SDA
I2C_SPKRAMP_R_SCL
I2S_SPKRAMP_R_R2D
I2S_SPKRAMP_L_D2R
I2S_SPKRAMP_R_LRCLK_R
I2S_SPKRAMP_R_BCLK
SPKR_ID1
SMC_LID_RIGHT
PPBUS_G3H
PP3V3_G3S
PP1V8_G3S
PP1V8_SLPS2R
GND

FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE

FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE

FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE

FUNC_TEST=TRUE

FUNC_TEST=TRUE

FUNC_TEST=TRUE

FUNC_TEST=TRUE

FUNC_TEST=TRUE
FUNC_TEST=TRUE

AMR/Mic

BI
BI
BI
BI
BI
BI
BI

PDM_DMIC_CLK0
PDM_DMIC_DATA0_ISOL
PDM_DMIC_CLK1
PDM_DMIC_DATA1_ISOL
SMC_LID_LEFT
PP1V8_G3S
PP1V8_SLPS2R
GND

FUNC_TEST=TRUE

FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE

FUNC_TEST=TRUE

FUNC_TEST=TRUE

FUNC_TEST=TRUE
FUNC_TEST=TRUE

Speaker (L)

BI
BI
BI

SPKRCONN_L_OUTP
SPKRCONN_L_OUTN
SPKR_ID0
GND

FUNC_TEST=TRUE

FUNC_TEST=TRUE

FUNC_TEST=TRUE
FUNC_TEST=TRUE

Fan

BI
BI
BI

FAN_LT_PWM
FAN_LT_TACH
PP5V_G3S
GND

FUNC_TEST=TRUE

FUNC_TEST=TRUE

FUNC_TEST=TRUE
FUNC_TEST=TRUE

x

1x

1x

1x

64 55 49

53 40

81 64 55 53

54 53

54 53

54 53

54 53

54 53

54 53

54 53

54 53

54 53 40

53

53

53

53

30 29 18

29

29

29

29

29

29

29

29

32 30 29

75

39 18 14

39 14

81 17 14

66 64 17 14

14

14

65 64

81 66 65 64

81 64 31 23

81 64 63

PMU_ONOFF_L Level Shifter

BI

PMU_ONOFF_L

IPD

BI
BI
BI
BI
BI
BI
BI
BI

BI
BI
BI
BI
BI
BI
BI

IPD_LID_OPEN
PMU_RSLOC_RST_L
I2C_TPAD_3V3_SCL
I2C_TPAD_3V3_SDA
SPI_TPAD_3V3_CLK
SPI_TPAD_3V3_CS_L
SPI_TPAD_3V3_MISO
SPI_TPAD_3V3_MOSI

TPAD_SPI_3V3_EN
TPAD_SPI_3V3_INT_L
TPAD_KBD_WAKE_L
PPBUS_G3H_TPAD_FLT
PP5V_G3S_IPD_F
PP3V3_G3H_IPD_F
PP3V3_G3S_IPD_F
GND

Wireless

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

BI

WLAN_AUDIO_SYNC
WLAN_SROM_CLK
WLAN_SROM_CS
WLAN_SROM_DIN
WLAN_SROM_DOUT
SPI_BT_CLK
SPI_BT_CS_L
SPI_BT_MOSI
SPI_BT_MISO
WLANBT_HOST_WAKE

PP3V3_G3S_WLANBT
GND

Power Sequencing

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

PLT_RST_L
PM_PCH_SYS_PWROK
PM_SLP_S0_L
PM_SLP_S3_L
PM_SLP_S4_L
PM_SLP_S5_L
PVDDQ_PGOOD
PVDDQ_EN
PMU_ACTIVE_READY
P1V1_SLPDDR_SOCFET_EN

FUNC_TEST=TRUE

FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE

FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE

FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE

FUNC_TEST=TRUE
FUNC_TEST=TRUE

FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE

D

2x

C

B

A

71

70

70

71

BI

BI
BI
BI

SSD

TP_SSD0_S4E1_UART_TX

TP_SSD0_S4E0_UART_TX
TP_SSD0_S4E0_JTAG_TDI
TP_SSD0_S4E1_JTAG_TDO

MAKE_BASE=TRUE

MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE

FUNC_TEST=TRUE
FUNC_TEST=TRUE

TP_SSD0_S4E1_UART_TX

TP_SSD0_S4E0_UART_TX
TP_SSD0_S4E0_JTAG_TDI
TP_SSD0_S4E1_JTAG_TDO

56

55

55

55

55

56 44

56

56 55

BI
BI
BI
BI
BI
BI
BI
BI

Battery

CHGR_HPWR_EN_L
SMBUS_3V3_BATT_SCL
SMBUS_3V3_BATT_SDA
SYS_DETECT
SYS_DETECT_L
CHGR_BMON
PPVBAT_G3H_CHGR_R
PPVBAT_G3H_CONN
GND

FUNC_TEST=TRUE

FUNC_TEST=TRUE

FUNC_TEST=TRUE

FUNC_TEST=TRUE

FUNC_TEST=TRUE

FUNC_TEST=TRUE

FUNC_TEST=TRUE

FUNC_TEST=TRUE

5x
5x

BOM_COST_GROUP=DEBUG

81 66 64

39 32

64 31

BI
BI
BI

PAGE TITLE

P1V8G3S_EN
SMC_PCH_SYS_PWROK
SOC_SOCHOT_L

ICT FCT

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE

DRAWING NUMBER

051-05232

REVISION

BRANCH

proto4b

PAGE

124 OF 152

SHEET

78 OF 86

A

SIZE

D

2.0.0

8

67

35 4

2

1

678

www.laptoprepairsecrets.com

3 245

1

D

78 75

PPVCC_S0_CPU

DES:INTER

1

CC740

12PF

5%
25V

2

CERM
0201

DES:INTER

1

CC741

3PF

+/-0.1PF
25V

2

C0G
0201

1

CC7G0

12PF

5%
25V

2

CERM
0201

DES:INTER

1

CC742

3PF

+/-0.1PF
25V

2

C0G
0201

DES:INTER

1

CC743

12PF

5%
25V

2

CERM
0201

NOSTUFF

1

CC7G2

3PF

+/-0.1PF
25V

2

C0G
0201

DES:INTER

1

CC744

3PF

+/-0.1PF
25V

2

C0G
0201

DES:INTER

1

CC745

12PF

5%
25V

2

CERM
0201

1

CC7G4

3PF

+/-0.1PF
25V

2

C0G
0201

DES:INTER

1

CC746

3PF

+/-0.1PF
25V

2

C0G
0201

DES:INTER

1

CC747

12PF

5%
25V

2

CERM
0201

NOSTUFF

1

CC7G6

3PF

+/-0.1PF
25V

2

C0G
0201

DES:INTER

1

CC748

3PF

+/-0.1PF
25V

2

C0G
0201

DES:INTER

1

CC749

12PF

5%
25V

2

CERM
0201

1

CC7G8

12PF

5%
25V

2

CERM
0201

DES:INTER

1

CC750

3PF

+/-0.1PF
25V

2

C0G
0201

DES:INTER

1

CC751

12PF

5%
25V

2

CERM
0201

NOSTUFF

1

CC7H0

3PF

+/-0.1PF
25V

2

C0G
0201

DES:INTER

1

CC752

3PF

+/-0.1PF
25V

2

C0G
0201

DES:INTER

1

CC753

12PF

5%
25V

2

CERM
0201

1

CC7H2

3PF

+/-0.1PF
25V

2

C0G
0201

DES:INTER

1

CC754

12PF

5%
25V

2

CERM
0201

DES:INTER

1

CC755

3PF

+/-0.1PF
25V

2

C0G
0201

1

CC7H4

3PF

+/-0.1PF
25V

2

C0G
0201

1

CC756

3PF

+/-0.1PF
25V

2

C0G
0201

1

CC757

12PF

5%
25V

2

CERM
0201

1

CC7H6

3PF

+/-0.1PF
25V

2

C0G
0201

1

CC758

3PF

+/-0.1PF
25V

2

C0G
0201

1

CC759

12PF

5%
25V

2

CERM
0201

1

CC7H8

3PF

+/-0.1PF
25V

2

C0G
0201

1

CC7I0

3PF

+/-0.1PF
25V

2

C0G
0201

78 67 27

27

PP3V3_TBT_X_S0_R

1

CC721

12PF

5%
25V

2

CERM
0201

PP3V3_TBT_X_S0

1

CC762

3PF

+/-0.1PF
25V

2

C0G
0201

PPVIN_G3H_P3V3G3H

75

1

CC720

3PF

+/-0.1PF
25V

2

C0G
0201

1

CC763

12PF

5%
25V

2

CERM
0201

1

CC786

3PF

+/-0.1PF
25V

2

C0G
0201

1

CC7D4

3PF

+/-0.1PF
25V

2

C0G
0201

79 78 75 59 16

75

PP1V8_PRIM_PCH

1

CC722

3PF

+/-0.1PF
25V

2

C0G
0201

1

CC723

12PF

5%
25V

2

CERM
0201

PPVIN_G3H_P5VG3S

1

CC788

3PF

+/-0.1PF
25V

2

C0G
0201

1

CC724

3PF

+/-0.1PF
25V

2

C0G
0201

1

CC725

12PF

5%
25V

2

CERM
0201

1

CC7D6

3PF

+/-0.1PF
25V

2

C0G
0201

78 75 65

PP3V3_G3H

1

CC730

3PF

+/-0.1PF
25V

2

C0G
0201

1

CC731

12PF

5%
25V

2

CERM
0201

1

CC760

3PF

+/-0.1PF
25V

2

C0G
0201

1

CC761

12PF

5%
25V

2

CERM
0201

D

78 74 73 71 70

C

1

CC7G1

3PF

+/-0.1PF
25V

2

C0G
0201

PPVCCQ_ANI_SSD0

1

CC7A8

3PF

+/-0.1PF
25V

2

C0G
0201

1

CC7A9

12PF

5%
25V

2

CERM
0201

NOSTUFF

1

CC7G3

12PF

5%
25V

2

CERM
0201

1

CC7B0

3PF

+/-0.1PF
25V

2

C0G
0201

1

CC7B1

12PF

5%
25V

2

CERM
0201

1

CC7G5

12PF

5%
25V

2

CERM
0201

1

CC7B2

3PF

+/-0.1PF
25V

2

C0G
0201

1

CC7B3

12PF

5%
25V

2

CERM
0201

NOSTUFF

1

CC7G7

12PF

5%
25V

2

CERM
0201

1

CC7B4

3PF

+/-0.1PF
25V

2

C0G
0201

1

CC7B5

12PF

5%
25V

2

CERM
0201

1

CC7G9

3PF

+/-0.1PF
25V

2

C0G
0201 0201

78 75

1

CC7B6

3PF

+/-0.1PF
25V

2

C0G
0201

1

CC7B7

12PF

5%
25V

2

CERM
0201

1

2

NOSTUFF

CC7H1

12PF

5%
25V
CERM

PPBUS_G3H

1

CC7H3

12PF

5%
25V

2

CERM
0201

1

CC700

3PF

+/-0.1PF
25V

2

C0G
0201

1

CC701

12PF

5%
25V

2

CERM
0201

1

CC7H5

12PF

5%
25V

2

CERM
0201

1

CC702

3PF

+/-0.1PF
25V

2

C0G
0201

1

CC703

12PF

5%
25V

2

CERM
0201

1

CC7H7

12PF

5%
25V

2

CERM
0201

1

CC704

3PF

+/-0.1PF
25V

2

C0G
0201

1

CC705

12PF

5%
25V

2

CERM
0201

1

CC7H9

12PF

5%
25V

2

CERM
0201

1

CC706

3PF

+/-0.1PF
25V

2

C0G
0201

1

CC707

12PF

5%
25V

2

CERM
0201

1

CC7I1

2

1

CC772

3PF

+/-0.1PF
25V

2

C0G
0201

1

CC773

12PF

5%
25V

2

CERM
0201

12PF

5%
25V
CERM
0201

1

CC778

3PF

+/-0.1PF
25V

2

C0G
0201

1

CC779

12PF

5%
25V

2

CERM
0201

78 26 23

78 26 23

1

CC787

12PF

5%
25V

2

CERM
0201

PP20V_USBC_X_VBUS

1

CC710

3PF

+/-0.1PF
100V

2

C0G
0201

PP20V_USBC_T_VBUS

1

CC712

3PF

+/-0.1PF
100V

2

C0G
0201

1

CC7D5

12PF

5%
25V

2

CERM
0201

1

CC711

12PF

5%
100V

2

C0G
0201

1

CC713

12PF

5%
100V

2

C0G
0201

75

79 56

1

CC789

12PF

5%
25V

2

CERM
0201

PPBUS_G3H

1

CC776

3PF

+/-0.1PF
25V

2

C0G
0201

PPVBAT_G3H_FUSE

1

CC784

3PF

+/-0.1PF
25V

2

C0G
0201

1

CC7D7

12PF

5%
25V

2

CERM
0201

1

CC777

12PF

5%
25V

2

CERM
0201

1

CC785

12PF

5%
25V

2

CERM
0201

CHGR_PHASE1

56

CHGR_PHASE2

56

1

CC794

3PF

+/-0.1PF
100V

2

C0G
0201

1

CC796

3PF

+/-0.1PF
100V

2

C0G
0201

1

CC795

12PF

5%
100V

2

C0G
0201

1

CC797

12PF

5%
100V

2

C0G
0201

C

B

78 75 71 70

PPVCC_NAND_SSD0

1

CC7B8

3PF

+/-0.1PF
25V

2

C0G
0201

1

CC7B9

12PF

5%
25V

2

CERM
0201

1

CC7A2

3PF

+/-0.1PF
25V

2

C0G
0201

1

CC7C0

3PF

+/-0.1PF
25V

2

C0G
0201

1

CC7C1

12PF

5%
25V

2

CERM
0201

1

CC7A4

3PF

+/-0.1PF
25V

2

C0G
0201

1

CC7C2

3PF

+/-0.1PF
25V

2

C0G
0201

1

CC7C3

12PF

5%
25V

2

CERM
0201

1

CC7A6

3PF

+/-0.1PF
25V

2

C0G
0201

1

CC7C4

3PF

+/-0.1PF
25V

2

C0G
0201

1

CC7C5

12PF

5%
25V

2

CERM
0201

1

CC732

3PF

+/-0.1PF
25V

2

C0G
0201

78 74 71 70

1

CC7J0

3PF

+/-0.1PF
25V

2

C0G
0201 0201

PP0V9_SSD0

1

CC7J2

3PF

+/-0.1PF
25V

2

C0G
0201

1

CC7C6

3PF

+/-0.1PF
25V

2

C0G
0201

1

CC7C7

12PF

5%
25V

2

CERM
0201

1

CC7J4

3PF

+/-0.1PF
25V

2

C0G
0201

1

CC7C8

3PF

+/-0.1PF
25V

2

C0G
0201

1

CC7C9

12PF

5%
25V

2

CERM
0201

1

CC7J6

3PF

+/-0.1PF
25V

2

C0G
0201

1

CC7D0

3PF

+/-0.1PF
25V

2

C0G
0201

1

CC7D1

12PF

5%
25V

2

CERM
0201

78 75 60 59 75

PP5V_G3SPPBUS_HS_CPU

1

CC7D2

3PF

+/-0.1PF
25V

2

C0G
0201

1

CC7D3

12PF

5%
25V

2

CERM
0201

1

2

CC714

3PF

+/-0.1PF
25V
C0G

1

CC716

3PF

+/-0.1PF
25V

2

C0G
0201

1

CC774

3PF

+/-0.1PF
25V

2

C0G
0201

79 78 75

78 75

78 74

PP1V1_S3

PP1V8_G3S

PP1V8_SLPS2R

1

CC726

3PF

+/-0.1PF
25V

2

C0G
0201

1

CC766

3PF 12PF

+/-0.1PF
25V

2

C0G
0201

1

CC768

3PF

+/-0.1PF
25V

2

C0G
0201

1

CC727

2

1

CC767

2

1

CC769

2

12PF

5%
25V
CERM
0201

5%
25V
CERM
0201

12PF

5%
25V
CERM
0201

CPUCORE_SW1

58

CPUCORE_SW2

58

CPUCORE_SW3

58

1

CC790

3PF

+/-0.1PF
100V

2

C0G
0201

1

CC792

3PF

+/-0.1PF
100V

2

C0G
0201

1

CC7F8

3PF

+/-0.1PF
100V

2

C0G
0201

1

CC791

12PF

5%
100V

2

C0G
0201

1

CC793

12PF

5%
100V

2

C0G
0201

1

CC7F9

12PF

5%
100V

2

C0G
0201

60

60

78 56

P3V3G3H_VSW

1

CC798

3PF

+/-0.1PF
100V

2

C0G
0201

P5VG3S_VSW

1

CC7A0

3PF

+/-0.1PF
100V

2

C0G
0201

PPDCIN_G3H_CHGR_AMON

1

CC7D8

3PF

+/-0.1PF
100V

2

C0G
0201

1

CC799

12PF

5%
100V

2

C0G
0201

1

CC8A1

12PF

5%
100V

2

C0G
0201

1

CC7D9

12PF

5%
100V

2

C0G
0201

B

A

79 78 75

PP1V1_S3

1

CC7A3

12PF

5%
25V

2

CERM
0201

1

CC728

3PF

+/-0.1PF
25V

2

C0G
0201

1

CC729

12PF

5%
25V

2

CERM
0201

1

CC7A5

12PF

5%
25V

2

CERM
0201

1

CC7E2

3PF

+/-0.1PF
25V

2

C0G
0201

1

CC7E3

12PF

5%
25V

2

CERM
0201

1

CC7A7

12PF

5%
25V

2

CERM
0201

1

CC7E4

3PF

+/-0.1PF
25V

2

C0G
0201

1

CC7E5

12PF

5%
25V

2

CERM
0201

1

CC733

12PF

5%
25V

2

CERM
0201

1

CC7E6

3PF

+/-0.1PF
25V

2

C0G
0201

1

CC7E7

12PF

5%
25V

2

CERM
0201

1

CC7J1

12PF

5%
25V

2

CERM
0201

1

CC7E8

3PF

+/-0.1PF
25V

2

C0G
0201

1

CC7E9

12PF

5%
25V

2

CERM
0201

1

CC7J3

12PF

5%
25V

2

CERM
0201

1

CC7F0

3PF

+/-0.1PF
25V

2

C0G
0201

1

CC7F1

12PF

5%
25V

2

CERM
0201

1

CC7J5

12PF

5%
25V

2

CERM
0201

1

CC7F2

3PF

+/-0.1PF
25V

2

C0G
0201

1

CC7F3

12PF

5%
25V

2

CERM
0201

1

CC7J7

12PF

5%
25V

2

CERM
0201

1

CC7F4

3PF

+/-0.1PF
25V

2

C0G
0201

1

CC7F5

12PF

5%
25V

2

CERM
0201

1

CC7F6

3PF

+/-0.1PF
25V

2

C0G
0201

1

CC7F7

12PF

5%
25V

2

CERM
0201

1

CC715

12PF

5%
25V

2

CERM
0201

DES:INTER

1

CC7I2

3PF

+/-0.1PF
25V

2

C0G
0201

DES:INTER

1

CC7I3

12PF

5%
25V

2

CERM
0201

1

CC717

12PF

5%
25V

2

CERM
0201

DES:INTER

1

CC7I4

3PF

+/-0.1PF
25V

2

C0G
0201

DES:INTER

1

CC7I5

12PF

5%
25V

2

CERM
0201

1

CC775

12PF

5%
25V

2

CERM
0201

DES:INTER

1

CC7I6

3PF

+/-0.1PF
25V

2

C0G
0201

DES:INTER

1

CC7I7

12PF

5%
25V

2

CERM
0201

79 56

DES:INTER

1

CC7I8

3PF

+/-0.1PF
25V

2

C0G
0201

DES:INTER

1

CC7I9

12PF

5%
25V

2

CERM
0201

PPVBAT_G3H_FUSE

1

CC770

3PF

+/-0.1PF
25V

2

C0G
0201

78 75 56

1

CC7J9

12PF

5%
25V

2

CERM
0201

1

CC771

12PF

5%
25V

2

CERM
0201

PPDCIN_G3H

NOSTUFF

1

CC708

3PF

+/-0.1PF
100V

2

C0G
0201

78 75

PP3V3_G3S

1

CC765

12PF

2

PP3V3_G3H_PMU_VDDMAIN

75

NOSTUFF

1

CC718

3PF

+/-0.1PF
25V

2

C0G
0201

NOSTUFF

1

CC709

12PF

5%
100V

2

C0G
0201

BOM_COST_GROUP=DESENSE

5%
25V
CERM
0201

NOSTUFF

1

CC719

12PF

5%
25V

2

CERM
0201

79 78 75 59 16

PAGE TITLE

PP1V8_PRIM_PCH

1

CC7E0

3PF

2

+/-0.1PF
25V
C0G
0201

Desense Caps 1

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

1

CC7E1

12PF

5%
25V

2

CERM
0201

DRAWING NUMBER

051-05232

REVISION

BRANCH

PAGE

127 OF 152

SHEET

A

SIZE

D

2.0.0

proto4b

79 OF 86

8

67

35 4

2

1

678

www.laptoprepairsecrets.com

3 245

1

D

75 59 11

75

PPVCCIN_AUX_PCH

1

CC800

3PF

+/-0.1PF
25V

2

C0G
0201

1

CC801

12PF

5%
25V

2

CERM
0201

PP0V6_S3

1

CC802

3PF

+/-0.1PF
25V

2

C0G
0201

1

CC803

12PF

5%
25V

2

CERM
0201

1

CC804

3PF

+/-0.1PF
25V

2

C0G
0201

1

CC805

12PF

5%
25V

2

CERM
0201

1

CC806

3PF

+/-0.1PF
25V

2

C0G
0201

1

CC807

12PF

5%
25V

2

CERM
0201

DES:INTER

1

CC808

3PF

+/-0.1PF
25V

2

C0G
0201

DES:INTER

1

CC809

12PF

5%
25V

2

CERM
0201

DES:INTER

1

CC810

3PF

+/-0.1PF
25V

2

C0G
0201

1

CC811

12PF

5%
25V

2

CERM
0201

1

CC812

3PF

+/-0.1PF
25V

2

C0G
0201

1

CC813

12PF

5%
25V

2

CERM
0201

1

CC814

3PF

+/-0.1PF
25V

2

C0G
0201

1

CC815

12PF

5%
25V

2

CERM
0201

NOSTUFF

1

CC817

12PF

5%
25V

2

CERM

DES:INTER

1

CC819

12PF

5%
25V

2

CERM
0201

1

CC823

12PF

5%
25V

2

CERM
02010201

NOSTUFF

1

CC827

12PF

5%
25V

2

CERM
0201

D

C

1

CC830

3PF

+/-0.1PF
25V

2

C0G
0201

1

CC831

12PF

5%
25V

2

CERM
0201

1

CC832

3PF

+/-0.1PF
25V

2

C0G
0201

1

CC833

12PF

5%
25V

2

CERM
0201

1

CC834

3PF

+/-0.1PF
25V

2

C0G
0201

1

CC835

12PF

5%
25V

2

CERM
0201

1

CC836

3PF

+/-0.1PF
25V

2

C0G
0201

1

CC837

12PF

5%
25V

2

CERM
0201

1

CC838

3PF

+/-0.1PF
25V

2

C0G
0201

1

CC839

12PF

5%
25V

2

CERM
0201

1

CC840

3PF

+/-0.1PF
25V

2

C0G
0201

1

CC841

12PF

5%
25V

2

CERM
0201

1

CC842

3PF

+/-0.1PF
25V

2

C0G
0201

1

CC843

12PF

5%
25V

2

CERM
0201

1

CC844

3PF

+/-0.1PF
25V

2

C0G
0201

1

CC845

12PF

5%
25V

2

CERM
0201

1

CC846

3PF

+/-0.1PF
25V

2

C0G
0201

1

CC847

12PF

5%
25V

2

CERM
0201

C

B

B

A

8

67

A

PAGE TITLE

Desense Caps 2

DRAWING NUMBER

051-05232

Apple Inc.

REVISION

2.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=DESENSE

35 4

IV ALL RIGHTS RESERVED

2

BRANCH

proto4b

PAGE

128 OF 152

SHEET

80 OF 86

1

SIZE

D

678

www.laptoprepairsecrets.com

3 245

1

D

A Remote Sense Support

PP0V9_SLPDDR

74

PP0V82_SLPDDR

74

PPVNN_PCH_EXT

9 46

PP1V05_PCH_EXT

9 46

PP0V9_SSD0

74

PPVCCQ_ANI_SSD0

74

XWE095

SHORT-12L-0.1MM-SM

2 1

P0V9SLPDDR_FB_R

XWE096

SHORT-12L-0.1MM-SM

2 1

P0V8SLPDDR_FB_R

XWE097

SHORT-12L-0.1MM-SM

2 1

PVNN_PCH_EXT_FB_R_P

XWE098

SHORT-12L-0.1MM-SM

2 1

PVNN_PCH_EXT_FB_R_N

XWE099

SHORT-12L-0.1MM-SM

2 1

P1V05_PCH_EXT_FB_R

XWE100

SHORT-12L-0.1MM-SM

2 1

P0V9SSD_FB_R_P

XWE101

SHORT-12L-0.1MM-SM

2 1

P0V9SSD_FB_R_N

XWE102

SHORT-12L-0.1MM-SM

2 1

1/20W MF 02015%

1/20W

1/20W 5% 0201MF

1/20W

RE095

5% MF 02011/20W

RE096

RE097

RE098

RE099

5%1/20W MF 0201

NOSTUFF

RE100

NOSTUFF

RE101

5% MF1/20W

NOSTUFF

RE102

5%

0

0

0

0

0

0

0

0

21

P0V9SLPDDR_FB

NO_XNET_CONNECTION=1

21

P0V8SLPDDR_FB

NO_XNET_CONNECTION=1

21

PVNN_PCH_EXT_FB_P

MF 02015%

NO_XNET_CONNECTION=1

21

PVNN_PCH_EXT_FB_N

MF 02011/20W 5%

NO_XNET_CONNECTION=1

21

P1V05_PCH_EXT_FB

NO_XNET_CONNECTION=1

21

P0V9SSD_FB_P

NO_XNET_CONNECTION=1

21

P0V9SSD_FB_N

NO_XNET_CONNECTION=1

21

MF 0201

NO_XNET_CONNECTION=1

0201

P1V8SSD_FBP1V8SSD_FB_R

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

62

62

62

62

62

62

62

62

B

System State LED

PP3V3_G3H

18 75 81

78 64 31 23

81 78 64 63

78 17 14

78 66 65 64

78 66 64

RE059

0

DBG_LED

PMU_ACTIVE_READY

IN

P1V1_SLPDDR_SOCFET_EN

IN

PM_SLP_S0_L

IN

PVDDQ_EN

IN

P1V8G3S_EN

IN

VOLTAGE=3.3V

21

PP3V3_G3H_DEBUGLED_R

0201MF1/20W5%

BYPASS=UE050::5mm

CE050

0.1UF

X5R-CERM

0201

DBG_LED

10%

10V

1

2

SLG4AP41990

2

PMU_ACTIVE_READY

3

P1V1_SLPDDR_SCFET_EN

4

PM_SLP_S0*

5

PVDDQ_EN

6

P1V8G3S_EN

1

VDD

UE050

STQFN

DBG_LED

GND

8

R
G
B

RFU1
RFU2
RFU3
RFU4

RE063

0

21

0201MF1/20W5%

DBG_LED

12

SYS_STATE_RED_R

11

SYS_STATE_GREEN_R

10

SYS_STATE_BLUE_R

7
9
13
14

NC
NC
NC
NC

PP3V3_G3H_DEBUGLED_RR

VOLTAGE=3.3V

DBG_LED

RE060

DBG_LED

RE061

DBG_LED

RE062

1% 1/20W MF 201

2.1K

1/20W1% 201MF

5.1K

4.75K

21

SYS_STATE_RED

21

SYS_STATE_GREEN

21

SYS_STATE_BLUE

201MF1/20W1%

DBG_LED

DE050

LTST-C32JBGEW

SM

D

1

R

4

G

3

B

2

C

B

C

SoC State LEDs

62 74

81 78 64 63

62 74

78 40 31 23

PP1V8_SLPS2R

DBG_LED

P1V1_SLPDDR_SOCFET_EN

DBG_LED

PP1V8_AWAKE

DBG_LED

SOC_DFU_STATUS

DBG_LED

2

G

S D

1

5

G

S D

4

2

G

S D

1

5

G

S D

4

PP3V3_G3H

18 75 81

QE000

DMN5L06VK-7

SOT563

VER-5

SOC_SLPS2R_RED

6

QE000

DMN5L06VK-7

SOT563

VER-5

SOC_SLPDDR_GREEN

3

QE001

DMN5L06VK-7

SOT563

VER-5

6

SOC_AWAKE_BLUE

QE001

DMN5L06VK-7

SOT563

VER-5

3

SOC_DFU_AMBER

DBG_LED

RE009

0

5% 1/20W MF 0201

DBG_LED

RE000

2.1K

1/20W

DBG_LED

1%
MF

201

21

SOC_SLPS2R_RED_R

RE001

4.75K

1/20W

DBG_LED

1%
MF

201

21

SOC_SLPDDR_GREEN_R

RE002

4.75K

1/20W

DBG_LED

1%
MF

201

21

SOC_AWAKE_BLUE_R

RE003

5.1K

1/20W

1%
MF

201

21

SOC_DFU_AMBER_R

VOLTAGE=3.3V

21

PP3V3_G3H_DEBUGLED_SOC

DBG_LED

DE000

LTST-C32JBGEW

SM

4

Inputs

PMU

ACT RDY

0
0
1
0
1
1

A

DBG_LED

1

1

P1V1_SLPDDR

SOCFET_EN

0
0
1 0
0
1
1
1

PM_SLP PVDDQ

S0_L

0
0

EN

0
0

0
0
0
1
0

1 1

1

1

0

P1V8G3S

EN

0
1
1

1
1
0

R

BLINK

ON
ON
ON ON
OFF
OFF

BLINK

Outputs

G

OFF
OFF
ON

OFF
ON
ON

B

OFF
OFF
OFF
ON
ON
OFF
OFF

Color

Blinking

Red
Red
Yellow
White
Blue
Green
Blinking &

Yellow Green

System

Shutdown (G3H)
Standby (G3S)
Standby (G3S)
Sleep
Sleep
Run

State

SoC

OFF
SLPS2R
AWAKE
SLPS2R
AWAKE
AWAKE S0

C

CPU

OFF
OFF
OFF
S0i
S0i

DE001

AMBER-605NM-35-56MCD

R

G

3

B

2

LTST-C281KFKT-SM

K

D

System Power States

System State:

CPU/PCH State:

Rails

SoC State:

PP*_S2R (0.8,1.1,1.8V)
PP*_DDR (0.8,0.9,1.1V)
PP*_AWAKE

Shutdown (G3H)
Off (RTC Only)
S2R
On

Off
Off

Awake
On

On
On

Standby (G3S)
Off (RTC Only)
S2R
On

Off

Awake
On

On
OnOff

(CPU,SRAM,1.2,1.8,3.3V)

PP3V3_G3H (VR1)
PP1S_G3H

PP*_G3S (1.8,3.3,5V)
PP*_S5 (1.8,3.3V)
CPU/PCH VRs

On

Off
Off
Off Off Off

On
OnOn

On
Off

On On

OnOn

On

On
OffOff
Off

* System: Shutdown Awake is a transition state only.
* SoC: SLP_DDR is a transition state only.
* CPU/PCH: S4 is only used by desktops for USB wakes.
* CPU/PCH: S5 is a transition state. May also be used for RTC wakes.

All other states are magenta

Standby (S4)
Standby
S2R
On

Off
Off

On

Awake
On

On
On

On
OnOn

On
On

On
On

Off/On Off/On

Sleep (S0i/S3)
Sleep
S2R
On

Off

Awake
On

On
OnOff

OnOn

On On

OnOn
On
Off/On

On

Off/On

Run (S0)
Run
Awake
On

On
On

On
On

On
On
On

B

E

A

Debug Buttons

SWE010

SOX-152HNT

SM

21

DBG_BTN

8

SWE001

SOX-152HNT

SM

DBG_BTN

21

PMU_RSLOC_RST_LPMU_ONOFF_R_L

78 64 55 53 49

67

SYNC_MASTER=X589_BIGSUR SYNC_DATE=04/12/2017

PAGE TITLE

A

Dev Support

DRAWING NUMBER

051-05232

Apple Inc.

REVISION

2.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=DEBUG

35 4

IV ALL RIGHTS RESERVED

2

BRANCH

proto4b

PAGE

140 OF 152

SHEET

81 OF 86

1

SIZE

D

BOM Variants

www.laptoprepairsecrets.com

EEEE

MVWL

BOM NUMBER BOM NAME BOM OPTIONS

685-00329 COMMON PARTS,MLB-TKSB,X1783
985-01143 DEV PARTS,MLB-TKSB,X1783
939-08188

PCBA,MLB-TKSB,DCDC,X1783

678

MLB_COMMON,MLB_DESENSE,MLB_CPUCFG
DBG_BTN,DBG_LED,USBC_DBG,WIFI_DBG,FANTACH:DEBUG

ALTERNATE,COMMON,DEV_PARTS_BOM,SCHEM,PCBF,CPU_ICLY:INTERPOSER,MLB_POWER,MLB_MISC

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

3 245

1

D

C

B

A

EEEE
N4JL
MTPF
MXCP
N4JY
MXD2
MXDF
N4KJ
MXDR
MXF4
N4KY
MXFH
MXFV
N4LF
MXG6
MXGK
N4LR
MXGX
MXH8
MXHM
MXJ0
MXJC
MXJQ
MXK3
MXKG
MXKT
MXL5
MXLJ
MXLW
MXM7
MXML
MXMY
MXN9
MXNN
MXP1
MXPD
MXPQ
MXQ3
MXQG
MXQT
MXR5
MXRJ
MXRW
MXT7
MXTN
MXV1
MXVD
MXVQ
MXW3
MXWG
MXWT
MXX5
MXXJ
MXXW
MXY8
MXYM
MY11
MY1F
MY1R
MY25
MY2L

BOM NUMBER BOM NAME BOM OPTIONS

639-08928

639-08705 PCBA,MLB-TKSB,BEST,MI-8G,TO-128G,X1783
639-08930
639-08706
639-08707
639-08931
639-08708 PCBA,MLB-TKSB,BEST,HY-16G,SS-128G,X1783
639-08709
639-08932

639-08711

639-08712 PCBA,MLB-TKSB,BEST,SS-16G,SS-128G,X1783

639-08714
639-08715 PCBA,MLB-TKSB,BEST,HY-8G,SD-256G,X1783
639-08716 PCBA,MLB-TKSB,BEST,HY-8G,TO-256G,X1783
639-08717 PCBA,MLB-TKSB,BEST,MI-8G,HY-256G,X1783
639-08718 PCBA,MLB-TKSB,BEST,MI-8G,SD-256G,X1783
639-08719 PCBA,MLB-TKSB,BEST,MI-8G,TO-256G,X1783
639-08720 PCBA,MLB-TKSB,BEST,SS-8G,HY-256G,X1783
639-08721 PCBA,MLB-TKSB,BEST,SS-8G,SD-256G,X1783
639-08722
639-08723
639-08724
639-08725
639-08726
639-08727

639-08729
639-08730
639-08731
639-08732
639-08733
639-08734
639-08735
639-08736

639-08738
639-08739
639-08740
639-08741
639-08742

639-08744

639-08746
639-08747
639-08748
639-08749
639-08750

639-08753
639-08754
639-08755

PCBA,MLB-TKSB,BEST,HY-8G,HY-128G,X1783
PCBA,MLB-TKSB,BEST,HY-8G,SS-128G,X1783639-08638
PCBA,MLB-TKSB,BEST,HY-8G,TO-128G,X1783639-08703
PCBA,MLB-TKSB,BEST,MI-8G,HY-128G,X1783639-08929
PCBA,MLB-TKSB,BEST,MI-8G,SS-128G,X1783639-08704

PCBA,MLB-TKSB,BEST,SS-8G,HY-128G,X1783
PCBA,MLB-TKSB,BEST,SS-8G,SS-128G,X1783
PCBA,MLB-TKSB,BEST,SS-8G,TO-128G,X1783

PCBA,MLB-TKSB,BEST,HY-16G,HY-128G,X1783

PCBA,MLB-TKSB,BEST,HY-16G,TO-128G,X1783
PCBA,MLB-TKSB,BEST,MI-16G,HY-128G,X1783
PCBA,MLB-TKSB,BEST,MI-16G,SS-128G,X1783639-08710
PCBA,MLB-TKSB,BEST,MI-16G,TO-128G,X1783
PCBA,MLB-TKSB,BEST,SS-16G,HY-128G,X1783639-08933

PCBA,MLB-TKSB,BEST,SS-16G,TO-128G,X1783639-08713

PCBA,MLB-TKSB,BEST,HY-8G,HY-256G,X1783

PCBA,MLB-TKSB,BEST,SS-8G,TO-256G,X1783
PCBA,MLB-TKSB,BEST,HY-16G,HY-256G,X1783
PCBA,MLB-TKSB,BEST,HY-16G,SD-256G,X1783
PCBA,MLB-TKSB,BEST,HY-16G,TO-256G,X1783
PCBA,MLB-TKSB,BEST,MI-16G,HY-256G,X1783
PCBA,MLB-TKSB,BEST,MI-16G,SD-256G,X1783
PCBA,MLB-TKSB,BEST,MI-16G,TO-256G,X1783639-08728
PCBA,MLB-TKSB,BEST,SS-16G,HY-256G,X1783
PCBA,MLB-TKSB,BEST,SS-16G,SD-256G,X1783
PCBA,MLB-TKSB,BEST,SS-16G,TO-256G,X1783

PCBA,MLB-TKSB,BEST,HY-8G,SD-512G,X1783

PCBA,MLB-TKSB,BEST,HY-8G,TO-512G,X1783

PCBA,MLB-TKSB,BEST,MI-8G,SD-512G,X1783

PCBA,MLB-TKSB,BEST,MI-8G,TO-512G,X1783

PCBA,MLB-TKSB,BEST,SS-8G,SD-512G,X1783

PCBA,MLB-TKSB,BEST,SS-8G,TO-512G,X1783639-08737
PCBA,MLB-TKSB,BEST,HY-16G,SD-512G,X1783
PCBA,MLB-TKSB,BEST,HY-16G,TO-512G,X1783
PCBA,MLB-TKSB,BEST,MI-16G,SD-512G,X1783
PCBA,MLB-TKSB,BEST,MI-16G,TO-512G,X1783
PCBA,MLB-TKSB,BEST,SS-16G,SD-512G,X1783
PCBA,MLB-TKSB,BEST,SS-16G,TO-512G,X1783639-08743

PCBA,MLB-TKSB,BEST,HY-8G,HY-1.0T,X1783

PCBA,MLB-TKSB,BEST,HY-8G,SD-1.0T,X1783639-08745

PCBA,MLB-TKSB,BEST,MI-8G,HY-1.0T,X1783

PCBA,MLB-TKSB,BEST,MI-8G,SD-1.0T,X1783

PCBA,MLB-TKSB,BEST,SS-8G,HY-1.0T,X1783

PCBA,MLB-TKSB,BEST,SS-8G,SD-1.0T,X1783
PCBA,MLB-TKSB,BEST,HY-16G,HY-1.0T,X1783
PCBA,MLB-TKSB,BEST,HY-16G,SD-1.0T,X1783639-08751
PCBA,MLB-TKSB,BEST,MI-16G,HY-1.0T,X1783639-08752
PCBA,MLB-TKSB,BEST,MI-16G,SD-1.0T,X1783
PCBA,MLB-TKSB,BEST,SS-16G,HY-1.0T,X1783
PCBA,MLB-TKSB,BEST,SS-16G,SD-1.0T,X1783

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:BEST,DRAMCFG:HYNIX_8GB,NANDCFG:ITLC_S4E_128G_HY

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:BEST,DRAMCFG:HYNIX_8GB,NANDCFG:ITLC_S4E_128G_SS

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:BEST,DRAMCFG:HYNIX_8GB,NANDCFG:ITLC_S4E_128G_TO

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:BEST,DRAMCFG:MICRON_8GB,NANDCFG:ITLC_S4E_128G_HY

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:BEST,DRAMCFG:MICRON_8GB,NANDCFG:ITLC_S4E_128G_SS

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:BEST,DRAMCFG:MICRON_8GB,NANDCFG:ITLC_S4E_128G_TO

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:BEST,DRAMCFG:SAMSUNG_8GB,NANDCFG:ITLC_S4E_128G_HY

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:BEST,DRAMCFG:SAMSUNG_8GB,NANDCFG:ITLC_S4E_128G_SS

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:BEST,DRAMCFG:SAMSUNG_8GB,NANDCFG:ITLC_S4E_128G_TO

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:BEST,DRAMCFG:HYNIX_16GB,NANDCFG:ITLC_S4E_128G_HY

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:BEST,DRAMCFG:HYNIX_16GB,NANDCFG:ITLC_S4E_128G_SS

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:BEST,DRAMCFG:HYNIX_16GB,NANDCFG:ITLC_S4E_128G_TO

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:BEST,DRAMCFG:MICRON_16GB,NANDCFG:ITLC_S4E_128G_HY

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:BEST,DRAMCFG:MICRON_16GB,NANDCFG:ITLC_S4E_128G_SS

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:BEST,DRAMCFG:MICRON_16GB,NANDCFG:ITLC_S4E_128G_TO

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:BEST,DRAMCFG:SAMSUNG_16GB,NANDCFG:ITLC_S4E_128G_HY

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:BEST,DRAMCFG:SAMSUNG_16GB,NANDCFG:ITLC_S4E_128G_SS

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:BEST,DRAMCFG:SAMSUNG_16GB,NANDCFG:ITLC_S4E_128G_TO

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:BEST,DRAMCFG:HYNIX_8GB,NANDCFG:ITLC_S4E_256G_HY

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:BEST,DRAMCFG:HYNIX_8GB,NANDCFG:ITLC_S4E_256G_SD

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:BEST,DRAMCFG:HYNIX_8GB,NANDCFG:ITLC_S4E_256G_TO

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:BEST,DRAMCFG:MICRON_8GB,NANDCFG:ITLC_S4E_256G_HY

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:BEST,DRAMCFG:MICRON_8GB,NANDCFG:ITLC_S4E_256G_SD

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:BEST,DRAMCFG:MICRON_8GB,NANDCFG:ITLC_S4E_256G_TO

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:BEST,DRAMCFG:SAMSUNG_8GB,NANDCFG:ITLC_S4E_256G_HY

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:BEST,DRAMCFG:SAMSUNG_8GB,NANDCFG:ITLC_S4E_256G_SD

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:BEST,DRAMCFG:SAMSUNG_8GB,NANDCFG:ITLC_S4E_256G_TO

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:BEST,DRAMCFG:HYNIX_16GB,NANDCFG:ITLC_S4E_256G_HY

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:BEST,DRAMCFG:HYNIX_16GB,NANDCFG:ITLC_S4E_256G_SD

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:BEST,DRAMCFG:HYNIX_16GB,NANDCFG:ITLC_S4E_256G_TO

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:BEST,DRAMCFG:MICRON_16GB,NANDCFG:ITLC_S4E_256G_HY

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:BEST,DRAMCFG:MICRON_16GB,NANDCFG:ITLC_S4E_256G_SD

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:BEST,DRAMCFG:MICRON_16GB,NANDCFG:ITLC_S4E_256G_TO

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:BEST,DRAMCFG:SAMSUNG_16GB,NANDCFG:ITLC_S4E_256G_HY

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:BEST,DRAMCFG:SAMSUNG_16GB,NANDCFG:ITLC_S4E_256G_SD

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:BEST,DRAMCFG:SAMSUNG_16GB,NANDCFG:ITLC_S4E_256G_TO

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:BEST,DRAMCFG:HYNIX_8GB,NANDCFG:ITLC_S4E_512G_SD

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:BEST,DRAMCFG:HYNIX_8GB,NANDCFG:ITLC_S4E_512G_TO

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:BEST,DRAMCFG:MICRON_8GB,NANDCFG:ITLC_S4E_512G_SD

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:BEST,DRAMCFG:MICRON_8GB,NANDCFG:ITLC_S4E_512G_TO

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:BEST,DRAMCFG:SAMSUNG_8GB,NANDCFG:ITLC_S4E_512G_SD

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:BEST,DRAMCFG:SAMSUNG_8GB,NANDCFG:ITLC_S4E_512G_TO

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:BEST,DRAMCFG:HYNIX_16GB,NANDCFG:ITLC_S4E_512G_SD

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:BEST,DRAMCFG:HYNIX_16GB,NANDCFG:ITLC_S4E_512G_TO

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:BEST,DRAMCFG:MICRON_16GB,NANDCFG:ITLC_S4E_512G_SD

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:BEST,DRAMCFG:MICRON_16GB,NANDCFG:ITLC_S4E_512G_TO

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:BEST,DRAMCFG:SAMSUNG_16GB,NANDCFG:ITLC_S4E_512G_SD

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:BEST,DRAMCFG:SAMSUNG_16GB,NANDCFG:ITLC_S4E_512G_TO

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:BEST,DRAMCFG:HYNIX_8GB,NANDCFG:ITLC_S4E_1P0T_HY

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:BEST,DRAMCFG:HYNIX_8GB,NANDCFG:ITLC_S4E_1P0T_SD

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:BEST,DRAMCFG:MICRON_8GB,NANDCFG:ITLC_S4E_1P0T_HY

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:BEST,DRAMCFG:MICRON_8GB,NANDCFG:ITLC_S4E_1P0T_SD

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:BEST,DRAMCFG:SAMSUNG_8GB,NANDCFG:ITLC_S4E_1P0T_HY

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:BEST,DRAMCFG:SAMSUNG_8GB,NANDCFG:ITLC_S4E_1P0T_SD

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:BEST,DRAMCFG:HYNIX_16GB,NANDCFG:ITLC_S4E_1P0T_HY

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:BEST,DRAMCFG:HYNIX_16GB,NANDCFG:ITLC_S4E_1P0T_SD

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:BEST,DRAMCFG:MICRON_16GB,NANDCFG:ITLC_S4E_1P0T_HY

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:BEST,DRAMCFG:MICRON_16GB,NANDCFG:ITLC_S4E_1P0T_SD

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:BEST,DRAMCFG:SAMSUNG_16GB,NANDCFG:ITLC_S4E_1P0T_HY

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:BEST,DRAMCFG:SAMSUNG_16GB,NANDCFG:ITLC_S4E_1P0T_SD

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

EEEE
NRDT
MY2Y
NRF5
MY39
NRFJ
MY3N
NRFW
MY41
NRG7
MY4D
NRGL
MY4Q

BOM NUMBER BOM NAME BOM OPTIONS

639-09922 PCBA,MLB-TKSB,BEST,HY-8G,HY-2.0T,X1783
639-08756 PCBA,MLB-TKSB,BEST,HY-8G,SD-2.0T,X1783
639-09923 PCBA,MLB-TKSB,BEST,MI-8G,HY-2.0T,X1783
639-08757

PCBA,MLB-TKSB,BEST,MI-8G,SD-2.0T,X1783
PCBA,MLB-TKSB,BEST,SS-8G,HY-2.0T,X1783639-09924
PCBA,MLB-TKSB,BEST,SS-8G,SD-2.0T,X1783639-08758

PCBA,MLB-TKSB,BEST,HY-16G,HY-2.0T,X1783639-09925
639-08759 PCBA,MLB-TKSB,BEST,HY-16G,SD-2.0T,X1783
639-09926 PCBA,MLB-TKSB,BEST,MI-16G,HY-2.0T,X1783
639-08760
639-09927

PCBA,MLB-TKSB,BEST,MI-16G,SD-2.0T,X1783

PCBA,MLB-TKSB,BEST,SS-16G,HY-2.0T,X1783

PCBA,MLB-TKSB,BEST,SS-16G,SD-2.0T,X1783639-08761

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:BEST,DRAMCFG:HYNIX_8GB,NANDCFG:ITLC_S4E_2P0T_HY

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:BEST,DRAMCFG:HYNIX_8GB,NANDCFG:ITLC_S4E_2P0T_SD

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:BEST,DRAMCFG:MICRON_8GB,NANDCFG:ITLC_S4E_2P0T_HY

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:BEST,DRAMCFG:MICRON_8GB,NANDCFG:ITLC_S4E_2P0T_SD

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:BEST,DRAMCFG:SAMSUNG_8GB,NANDCFG:ITLC_S4E_2P0T_HY

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:BEST,DRAMCFG:SAMSUNG_8GB,NANDCFG:ITLC_S4E_2P0T_SD

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:BEST,DRAMCFG:HYNIX_16GB,NANDCFG:ITLC_S4E_2P0T_HY

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:BEST,DRAMCFG:HYNIX_16GB,NANDCFG:ITLC_S4E_2P0T_SD

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:BEST,DRAMCFG:MICRON_16GB,NANDCFG:ITLC_S4E_2P0T_HY

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:BEST,DRAMCFG:MICRON_16GB,NANDCFG:ITLC_S4E_2P0T_SD

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:BEST,DRAMCFG:SAMSUNG_16GB,NANDCFG:ITLC_S4E_2P0T_HY

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:BEST,DRAMCFG:SAMSUNG_16GB,NANDCFG:ITLC_S4E_2P0T_SD

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

BOM Variants 1

DRAWING NUMBER

Apple Inc.

REVISION

BRANCH

PAGE

SHEET

051-05232

2.0.0

proto4b

141 OF 152

82 OF 86

D

C

B

A

SIZE

D

8

67

35 4

2

1

BOM Variants

www.laptoprepairsecrets.com

678

3 245

1

D

C

B

A

TABLE_BOMGROUP_HEAD

EEEE EEEE
N4M6
N4MM N5KP
N4P1
N4PD
N4PQ
N4Q3
N4QH
N4QV
N4T7
N4TL
N4TY
N4VC
N4VP
N4W2
N4WG
N4WT
N4X5
N4XJ
N4XW
N4Y8
N4YM
N500
N50G
N510
N51G
N51W
N527
N52L
N52Y
N539
N53Q
N555
N55J
N55W
N567
N56L
N56Y
N579
N57N
N591
N59D
N59Q
N5C4
N5CH
N5CV
N5D6
N5DK
N5DX
N5F8
N5FM
N5G0
N5GC
N5GP
N5H3
N5HG
N5HV
N5J6
N5JL
N5JY
N5KC

BOM NUMBER BOM NAME BOM OPTIONS

639-08934
639-08935 PCBA,MLB-TKSB,BEDRE,HY-8G,SS-128G,X1783
639-08936 PCBA,MLB-TKSB,BEDRE,HY-8G,TO-128G,X1783
639-08937 PCBA,MLB-TKSB,BEDRE,MI-8G,HY-128G,X1783
639-08938 PCBA,MLB-TKSB,BEDRE,MI-8G,SS-128G,X1783
639-08939 PCBA,MLB-TKSB,BEDRE,MI-8G,TO-128G,X1783
639-08940 PCBA,MLB-TKSB,BEDRE,SS-8G,HY-128G,X1783
639-08941 PCBA,MLB-TKSB,BEDRE,SS-8G,SS-128G,X1783
639-08942 PCBA,MLB-TKSB,BEDRE,SS-8G,TO-128G,X1783
639-08943
639-08944
639-08945
639-08946 PCBA,MLB-TKSB,BEDRE,MI-16G,HY-128G,X1783
639-08947
639-08948 PCBA,MLB-TKSB,BEDRE,MI-16G,TO-128G,X1783
639-08949 PCBA,MLB-TKSB,BEDRE,SS-16G,HY-128G,X1783
639-08950 PCBA,MLB-TKSB,BEDRE,SS-16G,SS-128G,X1783
639-08951 PCBA,MLB-TKSB,BEDRE,SS-16G,TO-128G,X1783
639-08952 PCBA,MLB-TKSB,BEDRE,HY-8G,HY-256G,X1783
639-08953 PCBA,MLB-TKSB,BEDRE,HY-8G,SD-256G,X1783
639-08954 PCBA,MLB-TKSB,BEDRE,HY-8G,TO-256G,X1783
639-08955 PCBA,MLB-TKSB,BEDRE,MI-8G,HY-256G,X1783
639-08956 PCBA,MLB-TKSB,BEDRE,MI-8G,SD-256G,X1783
639-08957 PCBA,MLB-TKSB,BEDRE,MI-8G,TO-256G,X1783
639-08958 PCBA,MLB-TKSB,BEDRE,SS-8G,HY-256G,X1783
639-08959 PCBA,MLB-TKSB,BEDRE,SS-8G,SD-256G,X1783
639-08960 PCBA,MLB-TKSB,BEDRE,SS-8G,TO-256G,X1783
639-08961 PCBA,MLB-TKSB,BEDRE,HY-16G,HY-256G,X1783
639-08962 PCBA,MLB-TKSB,BEDRE,HY-16G,SD-256G,X1783
639-08963 PCBA,MLB-TKSB,BEDRE,HY-16G,TO-256G,X1783
639-08964 PCBA,MLB-TKSB,BEDRE,MI-16G,HY-256G,X1783
639-08965 PCBA,MLB-TKSB,BEDRE,MI-16G,SD-256G,X1783
639-08966 PCBA,MLB-TKSB,BEDRE,MI-16G,TO-256G,X1783
639-08967 PCBA,MLB-TKSB,BEDRE,SS-16G,HY-256G,X1783
639-08968 PCBA,MLB-TKSB,BEDRE,SS-16G,SD-256G,X1783
639-08969 PCBA,MLB-TKSB,BEDRE,SS-16G,TO-256G,X1783
639-08970 PCBA,MLB-TKSB,BEDRE,HY-8G,SD-512G,X1783
639-08971 PCBA,MLB-TKSB,BEDRE,HY-8G,TO-512G,X1783
639-08972 PCBA,MLB-TKSB,BEDRE,MI-8G,SD-512G,X1783
639-08973 PCBA,MLB-TKSB,BEDRE,MI-8G,TO-512G,X1783
639-08974 PCBA,MLB-TKSB,BEDRE,SS-8G,SD-512G,X1783
639-08975 PCBA,MLB-TKSB,BEDRE,SS-8G,TO-512G,X1783
639-08976 PCBA,MLB-TKSB,BEDRE,HY-16G,SD-512G,X1783
639-08977 PCBA,MLB-TKSB,BEDRE,HY-16G,TO-512G,X1783
639-08978 PCBA,MLB-TKSB,BEDRE,MI-16G,SD-512G,X1783
639-08979 PCBA,MLB-TKSB,BEDRE,MI-16G,TO-512G,X1783
639-08980 PCBA,MLB-TKSB,BEDRE,SS-16G,SD-512G,X1783
639-08981 PCBA,MLB-TKSB,BEDRE,SS-16G,TO-512G,X1783
639-08982 PCBA,MLB-TKSB,BEDRE,HY-8G,HY-1.0T,X1783
639-08983 PCBA,MLB-TKSB,BEDRE,HY-8G,SD-1.0T,X1783
639-08984 PCBA,MLB-TKSB,BEDRE,MI-8G,HY-1.0T,X1783
639-08985 PCBA,MLB-TKSB,BEDRE,MI-8G,SD-1.0T,X1783
639-08986 PCBA,MLB-TKSB,BEDRE,SS-8G,HY-1.0T,X1783
639-08987 PCBA,MLB-TKSB,BEDRE,SS-8G,SD-1.0T,X1783
639-08988 PCBA,MLB-TKSB,BEDRE,HY-16G,HY-1.0T,X1783
639-08989 PCBA,MLB-TKSB,BEDRE,HY-16G,SD-1.0T,X1783
639-08990 PCBA,MLB-TKSB,BEDRE,MI-16G,HY-1.0T,X1783
639-08991 PCBA,MLB-TKSB,BEDRE,MI-16G,SD-1.0T,X1783
639-08992 PCBA,MLB-TKSB,BEDRE,SS-16G,HY-1.0T,X1783
639-08993 PCBA,MLB-TKSB,BEDRE,SS-16G,SD-1.0T,X1783

PCBA,MLB-TKSB,BEDRE,HY-8G,HY-128G,X1783

PCBA,MLB-TKSB,BEDRE,HY-16G,HY-128G,X1783
PCBA,MLB-TKSB,BEDRE,HY-16G,SS-128G,X1783
PCBA,MLB-TKSB,BEDRE,HY-16G,TO-128G,X1783

PCBA,MLB-TKSB,BEDRE,MI-16G,SS-128G,X1783

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:BEDRE,DRAMCFG:HYNIX_8GB,NANDCFG:ITLC_S4E_128G_HY

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:BEDRE,DRAMCFG:HYNIX_8GB,NANDCFG:ITLC_S4E_128G_SS

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:BEDRE,DRAMCFG:HYNIX_8GB,NANDCFG:ITLC_S4E_128G_TO

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:BEDRE,DRAMCFG:MICRON_8GB,NANDCFG:ITLC_S4E_128G_HY

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:BEDRE,DRAMCFG:MICRON_8GB,NANDCFG:ITLC_S4E_128G_SS

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:BEDRE,DRAMCFG:MICRON_8GB,NANDCFG:ITLC_S4E_128G_TO

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:BEDRE,DRAMCFG:SAMSUNG_8GB,NANDCFG:ITLC_S4E_128G_HY

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:BEDRE,DRAMCFG:SAMSUNG_8GB,NANDCFG:ITLC_S4E_128G_SS

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:BEDRE,DRAMCFG:SAMSUNG_8GB,NANDCFG:ITLC_S4E_128G_TO

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:BEDRE,DRAMCFG:HYNIX_16GB,NANDCFG:ITLC_S4E_128G_HY

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:BEDRE,DRAMCFG:HYNIX_16GB,NANDCFG:ITLC_S4E_128G_SS

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:BEDRE,DRAMCFG:HYNIX_16GB,NANDCFG:ITLC_S4E_128G_TO

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:BEDRE,DRAMCFG:MICRON_16GB,NANDCFG:ITLC_S4E_128G_HY

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:BEDRE,DRAMCFG:MICRON_16GB,NANDCFG:ITLC_S4E_128G_SS

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:BEDRE,DRAMCFG:MICRON_16GB,NANDCFG:ITLC_S4E_128G_TO

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:BEDRE,DRAMCFG:SAMSUNG_16GB,NANDCFG:ITLC_S4E_128G_HY

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:BEDRE,DRAMCFG:SAMSUNG_16GB,NANDCFG:ITLC_S4E_128G_SS

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:BEDRE,DRAMCFG:SAMSUNG_16GB,NANDCFG:ITLC_S4E_128G_TO

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:BEDRE,DRAMCFG:HYNIX_8GB,NANDCFG:ITLC_S4E_256G_HY

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:BEDRE,DRAMCFG:HYNIX_8GB,NANDCFG:ITLC_S4E_256G_SD

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:BEDRE,DRAMCFG:HYNIX_8GB,NANDCFG:ITLC_S4E_256G_TO

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:BEDRE,DRAMCFG:MICRON_8GB,NANDCFG:ITLC_S4E_256G_HY

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:BEDRE,DRAMCFG:MICRON_8GB,NANDCFG:ITLC_S4E_256G_SD

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:BEDRE,DRAMCFG:MICRON_8GB,NANDCFG:ITLC_S4E_256G_TO

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:BEDRE,DRAMCFG:SAMSUNG_8GB,NANDCFG:ITLC_S4E_256G_HY

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:BEDRE,DRAMCFG:SAMSUNG_8GB,NANDCFG:ITLC_S4E_256G_SD

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:BEDRE,DRAMCFG:SAMSUNG_8GB,NANDCFG:ITLC_S4E_256G_TO

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:BEDRE,DRAMCFG:HYNIX_16GB,NANDCFG:ITLC_S4E_256G_HY

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:BEDRE,DRAMCFG:HYNIX_16GB,NANDCFG:ITLC_S4E_256G_SD

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:BEDRE,DRAMCFG:HYNIX_16GB,NANDCFG:ITLC_S4E_256G_TO

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:BEDRE,DRAMCFG:MICRON_16GB,NANDCFG:ITLC_S4E_256G_HY

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:BEDRE,DRAMCFG:MICRON_16GB,NANDCFG:ITLC_S4E_256G_SD

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:BEDRE,DRAMCFG:MICRON_16GB,NANDCFG:ITLC_S4E_256G_TO

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:BEDRE,DRAMCFG:SAMSUNG_16GB,NANDCFG:ITLC_S4E_256G_HY

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:BEDRE,DRAMCFG:SAMSUNG_16GB,NANDCFG:ITLC_S4E_256G_SD

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:BEDRE,DRAMCFG:SAMSUNG_16GB,NANDCFG:ITLC_S4E_256G_TO

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:BEDRE,DRAMCFG:HYNIX_8GB,NANDCFG:ITLC_S4E_512G_SD

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:BEDRE,DRAMCFG:HYNIX_8GB,NANDCFG:ITLC_S4E_512G_TO

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:BEDRE,DRAMCFG:MICRON_8GB,NANDCFG:ITLC_S4E_512G_SD

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:BEDRE,DRAMCFG:MICRON_8GB,NANDCFG:ITLC_S4E_512G_TO

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:BEDRE,DRAMCFG:SAMSUNG_8GB,NANDCFG:ITLC_S4E_512G_SD

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:BEDRE,DRAMCFG:SAMSUNG_8GB,NANDCFG:ITLC_S4E_512G_TO

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:BEDRE,DRAMCFG:HYNIX_16GB,NANDCFG:ITLC_S4E_512G_SD

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:BEDRE,DRAMCFG:HYNIX_16GB,NANDCFG:ITLC_S4E_512G_TO

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:BEDRE,DRAMCFG:MICRON_16GB,NANDCFG:ITLC_S4E_512G_SD

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:BEDRE,DRAMCFG:MICRON_16GB,NANDCFG:ITLC_S4E_512G_TO

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:BEDRE,DRAMCFG:SAMSUNG_16GB,NANDCFG:ITLC_S4E_512G_SD

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:BEDRE,DRAMCFG:SAMSUNG_16GB,NANDCFG:ITLC_S4E_512G_TO

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:BEDRE,DRAMCFG:HYNIX_8GB,NANDCFG:ITLC_S4E_1P0T_HY

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:BEDRE,DRAMCFG:HYNIX_8GB,NANDCFG:ITLC_S4E_1P0T_SD

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:BEDRE,DRAMCFG:MICRON_8GB,NANDCFG:ITLC_S4E_1P0T_HY

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:BEDRE,DRAMCFG:MICRON_8GB,NANDCFG:ITLC_S4E_1P0T_SD

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:BEDRE,DRAMCFG:SAMSUNG_8GB,NANDCFG:ITLC_S4E_1P0T_HY

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:BEDRE,DRAMCFG:SAMSUNG_8GB,NANDCFG:ITLC_S4E_1P0T_SD

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:BEDRE,DRAMCFG:HYNIX_16GB,NANDCFG:ITLC_S4E_1P0T_HY

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:BEDRE,DRAMCFG:HYNIX_16GB,NANDCFG:ITLC_S4E_1P0T_SD

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:BEDRE,DRAMCFG:MICRON_16GB,NANDCFG:ITLC_S4E_1P0T_HY

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:BEDRE,DRAMCFG:MICRON_16GB,NANDCFG:ITLC_S4E_1P0T_SD

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:BEDRE,DRAMCFG:SAMSUNG_16GB,NANDCFG:ITLC_S4E_1P0T_HY

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:BEDRE,DRAMCFG:SAMSUNG_16GB,NANDCFG:ITLC_S4E_1P0T_SD

TABLE_BOMGROUP_ITEM

NRGY

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

NRH9

TABLE_BOMGROUP_ITEM

N5L2

TABLE_BOMGROUP_ITEM

NRHN

TABLE_BOMGROUP_ITEM

N5LF

TABLE_BOMGROUP_ITEM

NRJ1

TABLE_BOMGROUP_ITEM

N5LR

TABLE_BOMGROUP_ITEM

NRJD

TABLE_BOMGROUP_ITEM

N5M4

TABLE_BOMGROUP_ITEM

NRJQ

TABLE_BOMGROUP_ITEM

N5MH

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

BOM NUMBER BOM NAME BOM OPTIONS

639-09928
639-08994
639-09929
639-08995 PCBA,MLB-TKSB,BEDRE,MI-8G,SD-2.0T,X1783

639-08996 PCBA,MLB-TKSB,BEDRE,SS-8G,SD-2.0T,X1783

639-08998
639-09933
639-08999

PCBA,MLB-TKSB,BEDRE,HY-8G,HY-2.0T,X1783
PCBA,MLB-TKSB,BEDRE,HY-8G,SD-2.0T,X1783
PCBA,MLB-TKSB,BEDRE,MI-8G,HY-2.0T,X1783

PCBA,MLB-TKSB,BEDRE,SS-8G,HY-2.0T,X1783639-09930

PCBA,MLB-TKSB,BEDRE,HY-16G,HY-2.0T,X1783639-09931
PCBA,MLB-TKSB,BEDRE,HY-16G,SD-2.0T,X1783639-08997
PCBA,MLB-TKSB,BEDRE,MI-16G,HY-2.0T,X1783639-09932
PCBA,MLB-TKSB,BEDRE,MI-16G,SD-2.0T,X1783
PCBA,MLB-TKSB,BEDRE,SS-16G,HY-2.0T,X1783
PCBA,MLB-TKSB,BEDRE,SS-16G,SD-2.0T,X1783

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:BEDRE,DRAMCFG:HYNIX_8GB,NANDCFG:ITLC_S4E_2P0T_HY

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:BEDRE,DRAMCFG:HYNIX_8GB,NANDCFG:ITLC_S4E_2P0T_SD

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:BEDRE,DRAMCFG:MICRON_8GB,NANDCFG:ITLC_S4E_2P0T_HY

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:BEDRE,DRAMCFG:MICRON_8GB,NANDCFG:ITLC_S4E_2P0T_SD

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:BEDRE,DRAMCFG:SAMSUNG_8GB,NANDCFG:ITLC_S4E_2P0T_HY

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:BEDRE,DRAMCFG:SAMSUNG_8GB,NANDCFG:ITLC_S4E_2P0T_SD

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:BEDRE,DRAMCFG:HYNIX_16GB,NANDCFG:ITLC_S4E_2P0T_HY

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:BEDRE,DRAMCFG:HYNIX_16GB,NANDCFG:ITLC_S4E_2P0T_SD

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:BEDRE,DRAMCFG:MICRON_16GB,NANDCFG:ITLC_S4E_2P0T_HY

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:BEDRE,DRAMCFG:MICRON_16GB,NANDCFG:ITLC_S4E_2P0T_SD

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:BEDRE,DRAMCFG:SAMSUNG_16GB,NANDCFG:ITLC_S4E_2P0T_HY

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:BEDRE,DRAMCFG:SAMSUNG_16GB,NANDCFG:ITLC_S4E_2P0T_SD

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

BOM Variants 2

DRAWING NUMBER

Apple Inc.

REVISION

BRANCH

PAGE

SHEET

051-05232

2.0.0

proto4b

142 OF 152

83 OF 86

D

C

B

A

SIZE

D

8

67

35 4

2

1

BOM Variants

www.laptoprepairsecrets.com

678

3 245

1

D

C

B

A

EEEE
N5MV
MY53
MY5G
N5N6
MY5T
MY65
N5NK
MY6J
MY6W
N5NX
MY77
MY7L
N5P9
MY7Y
MY89
N5PN
MY8N
MY91
MY9D
MY9Q
MYC3
MYCG
MYCT
MYD5
MYDJ
MYDW
MYF7
MYFL
MYFY
MYG9
MYGN
MYH1
MYHD
MYHQ
MYJ3
MYJG
MYK5
MYKJ
MYKW
MYL7
MYLL
MYLY
MYM9
MYMN
MYN1
MYND
MYNQ
MYP3
MYPG
MYPT
MYQ5
MYQJ
MYQW
MYR7
MYRL
MYRY
MYT9
MYTN
MYV1
MYVR

BOM NUMBER BOM NAME BOM OPTIONS

639-09000 PCBA,MLB-TKSB,GOOD,HY-8G,HY-128G,X1783
639-08762
639-08763

PCBA,MLB-TKSB,GOOD,HY-8G,SS-128G,X1783

PCBA,MLB-TKSB,GOOD,HY-8G,TO-128G,X1783
639-09001 PCBA,MLB-TKSB,GOOD,MI-8G,HY-128G,X1783
639-08764
639-08765

PCBA,MLB-TKSB,GOOD,MI-8G,SS-128G,X1783

PCBA,MLB-TKSB,GOOD,MI-8G,TO-128G,X1783
639-09002 PCBA,MLB-TKSB,GOOD,SS-8G,HY-128G,X1783
639-08766

PCBA,MLB-TKSB,GOOD,SS-8G,SS-128G,X1783
639-08767 PCBA,MLB-TKSB,GOOD,SS-8G,TO-128G,X1783
639-09003 PCBA,MLB-TKSB,GOOD,HY-16G,HY-128G,X1783

PCBA,MLB-TKSB,GOOD,HY-16G,SS-128G,X1783639-08768

PCBA,MLB-TKSB,GOOD,HY-16G,TO-128G,X1783639-08769
639-09004 PCBA,MLB-TKSB,GOOD,MI-16G,HY-128G,X1783
639-08770 PCBA,MLB-TKSB,GOOD,MI-16G,SS-128G,X1783
639-08771 PCBA,MLB-TKSB,GOOD,MI-16G,TO-128G,X1783
639-09005 PCBA,MLB-TKSB,GOOD,SS-16G,HY-128G,X1783

PCBA,MLB-TKSB,GOOD,SS-16G,SS-128G,X1783639-08772
639-08773 PCBA,MLB-TKSB,GOOD,SS-16G,TO-128G,X1783
639-08774 PCBA,MLB-TKSB,GOOD,HY-8G,HY-256G,X1783
639-08775 PCBA,MLB-TKSB,GOOD,HY-8G,SD-256G,X1783
639-08776 PCBA,MLB-TKSB,GOOD,HY-8G,TO-256G,X1783
639-08777 PCBA,MLB-TKSB,GOOD,MI-8G,HY-256G,X1783
639-08778 PCBA,MLB-TKSB,GOOD,MI-8G,SD-256G,X1783
639-08779 PCBA,MLB-TKSB,GOOD,MI-8G,TO-256G,X1783
639-08780 PCBA,MLB-TKSB,GOOD,SS-8G,HY-256G,X1783
639-08781 PCBA,MLB-TKSB,GOOD,SS-8G,SD-256G,X1783
639-08782 PCBA,MLB-TKSB,GOOD,SS-8G,TO-256G,X1783

PCBA,MLB-TKSB,GOOD,HY-16G,HY-256G,X1783639-08783

PCBA,MLB-TKSB,GOOD,HY-16G,SD-256G,X1783639-08784
639-08785 PCBA,MLB-TKSB,GOOD,HY-16G,TO-256G,X1783
639-08786 PCBA,MLB-TKSB,GOOD,MI-16G,HY-256G,X1783
639-08787 PCBA,MLB-TKSB,GOOD,MI-16G,SD-256G,X1783

PCBA,MLB-TKSB,GOOD,MI-16G,TO-256G,X1783639-08788

PCBA,MLB-TKSB,GOOD,SS-16G,HY-256G,X1783639-08789
639-08790 PCBA,MLB-TKSB,GOOD,SS-16G,SD-256G,X1783

PCBA,MLB-TKSB,GOOD,SS-16G,TO-256G,X1783639-08791
639-08792 PCBA,MLB-TKSB,GOOD,HY-8G,SD-512G,X1783
639-08793 PCBA,MLB-TKSB,GOOD,HY-8G,TO-512G,X1783
639-08794 PCBA,MLB-TKSB,GOOD,MI-8G,SD-512G,X1783
639-08795 PCBA,MLB-TKSB,GOOD,MI-8G,TO-512G,X1783
639-08796 PCBA,MLB-TKSB,GOOD,SS-8G,SD-512G,X1783
639-08797 PCBA,MLB-TKSB,GOOD,SS-8G,TO-512G,X1783
639-08798 PCBA,MLB-TKSB,GOOD,HY-16G,SD-512G,X1783
639-08799 PCBA,MLB-TKSB,GOOD,HY-16G,TO-512G,X1783
639-08800 PCBA,MLB-TKSB,GOOD,MI-16G,SD-512G,X1783
639-08801 PCBA,MLB-TKSB,GOOD,MI-16G,TO-512G,X1783
639-08802 PCBA,MLB-TKSB,GOOD,SS-16G,SD-512G,X1783
639-08803 PCBA,MLB-TKSB,GOOD,SS-16G,TO-512G,X1783
639-08804 PCBA,MLB-TKSB,GOOD,HY-8G,HY-1.0T,X1783
639-08805 PCBA,MLB-TKSB,GOOD,HY-8G,SD-1.0T,X1783
639-08806 PCBA,MLB-TKSB,GOOD,MI-8G,HY-1.0T,X1783
639-08807 PCBA,MLB-TKSB,GOOD,MI-8G,SD-1.0T,X1783
639-08808 PCBA,MLB-TKSB,GOOD,SS-8G,HY-1.0T,X1783
639-08809 PCBA,MLB-TKSB,GOOD,SS-8G,SD-1.0T,X1783
639-08810 PCBA,MLB-TKSB,GOOD,HY-16G,HY-1.0T,X1783
639-08811 PCBA,MLB-TKSB,GOOD,HY-16G,SD-1.0T,X1783
639-08812 PCBA,MLB-TKSB,GOOD,MI-16G,HY-1.0T,X1783
639-08813 PCBA,MLB-TKSB,GOOD,MI-16G,SD-1.0T,X1783
639-08814 PCBA,MLB-TKSB,GOOD,SS-16G,HY-1.0T,X1783
639-08816 PCBA,MLB-TKSB,GOOD,SS-16G,SD-1.0T,X1783

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:GOOD,DRAMCFG:HYNIX_8GB,NANDCFG:ITLC_S4E_128G_HY

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:GOOD,DRAMCFG:HYNIX_8GB,NANDCFG:ITLC_S4E_128G_SS

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:GOOD,DRAMCFG:HYNIX_8GB,NANDCFG:ITLC_S4E_128G_TO

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:GOOD,DRAMCFG:MICRON_8GB,NANDCFG:ITLC_S4E_128G_HY

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:GOOD,DRAMCFG:MICRON_8GB,NANDCFG:ITLC_S4E_128G_SS

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:GOOD,DRAMCFG:MICRON_8GB,NANDCFG:ITLC_S4E_128G_TO

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:GOOD,DRAMCFG:SAMSUNG_8GB,NANDCFG:ITLC_S4E_128G_HY

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:GOOD,DRAMCFG:SAMSUNG_8GB,NANDCFG:ITLC_S4E_128G_SS

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:GOOD,DRAMCFG:SAMSUNG_8GB,NANDCFG:ITLC_S4E_128G_TO

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:GOOD,DRAMCFG:HYNIX_16GB,NANDCFG:ITLC_S4E_128G_HY

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:GOOD,DRAMCFG:HYNIX_16GB,NANDCFG:ITLC_S4E_128G_SS

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:GOOD,DRAMCFG:HYNIX_16GB,NANDCFG:ITLC_S4E_128G_TO

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:GOOD,DRAMCFG:MICRON_16GB,NANDCFG:ITLC_S4E_128G_HY

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:GOOD,DRAMCFG:MICRON_16GB,NANDCFG:ITLC_S4E_128G_SS

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:GOOD,DRAMCFG:MICRON_16GB,NANDCFG:ITLC_S4E_128G_TO

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:GOOD,DRAMCFG:SAMSUNG_16GB,NANDCFG:ITLC_S4E_128G_HY

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:GOOD,DRAMCFG:SAMSUNG_16GB,NANDCFG:ITLC_S4E_128G_SS

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:GOOD,DRAMCFG:SAMSUNG_16GB,NANDCFG:ITLC_S4E_128G_TO

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:GOOD,DRAMCFG:HYNIX_8GB,NANDCFG:ITLC_S4E_256G_HY

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:GOOD,DRAMCFG:HYNIX_8GB,NANDCFG:ITLC_S4E_256G_SD

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:GOOD,DRAMCFG:HYNIX_8GB,NANDCFG:ITLC_S4E_256G_TO

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:GOOD,DRAMCFG:MICRON_8GB,NANDCFG:ITLC_S4E_256G_HY

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:GOOD,DRAMCFG:MICRON_8GB,NANDCFG:ITLC_S4E_256G_SD

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:GOOD,DRAMCFG:MICRON_8GB,NANDCFG:ITLC_S4E_256G_TO

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:GOOD,DRAMCFG:SAMSUNG_8GB,NANDCFG:ITLC_S4E_256G_HY

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:GOOD,DRAMCFG:SAMSUNG_8GB,NANDCFG:ITLC_S4E_256G_SD

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:GOOD,DRAMCFG:SAMSUNG_8GB,NANDCFG:ITLC_S4E_256G_TO

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:GOOD,DRAMCFG:HYNIX_16GB,NANDCFG:ITLC_S4E_256G_HY

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:GOOD,DRAMCFG:HYNIX_16GB,NANDCFG:ITLC_S4E_256G_SD

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:GOOD,DRAMCFG:HYNIX_16GB,NANDCFG:ITLC_S4E_256G_TO

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:GOOD,DRAMCFG:MICRON_16GB,NANDCFG:ITLC_S4E_256G_HY

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:GOOD,DRAMCFG:MICRON_16GB,NANDCFG:ITLC_S4E_256G_SD

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:GOOD,DRAMCFG:MICRON_16GB,NANDCFG:ITLC_S4E_256G_TO

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:GOOD,DRAMCFG:SAMSUNG_16GB,NANDCFG:ITLC_S4E_256G_HY

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:GOOD,DRAMCFG:SAMSUNG_16GB,NANDCFG:ITLC_S4E_256G_SD

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:GOOD,DRAMCFG:SAMSUNG_16GB,NANDCFG:ITLC_S4E_256G_TO

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:GOOD,DRAMCFG:HYNIX_8GB,NANDCFG:ITLC_S4E_512G_SD

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:GOOD,DRAMCFG:HYNIX_8GB,NANDCFG:ITLC_S4E_512G_TO

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:GOOD,DRAMCFG:MICRON_8GB,NANDCFG:ITLC_S4E_512G_SD

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:GOOD,DRAMCFG:MICRON_8GB,NANDCFG:ITLC_S4E_512G_TO

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:GOOD,DRAMCFG:SAMSUNG_8GB,NANDCFG:ITLC_S4E_512G_SD

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:GOOD,DRAMCFG:SAMSUNG_8GB,NANDCFG:ITLC_S4E_512G_TO

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:GOOD,DRAMCFG:HYNIX_16GB,NANDCFG:ITLC_S4E_512G_SD

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:GOOD,DRAMCFG:HYNIX_16GB,NANDCFG:ITLC_S4E_512G_TO

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:GOOD,DRAMCFG:MICRON_16GB,NANDCFG:ITLC_S4E_512G_SD

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:GOOD,DRAMCFG:MICRON_16GB,NANDCFG:ITLC_S4E_512G_TO

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:GOOD,DRAMCFG:SAMSUNG_16GB,NANDCFG:ITLC_S4E_512G_SD

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:GOOD,DRAMCFG:SAMSUNG_16GB,NANDCFG:ITLC_S4E_512G_TO

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:GOOD,DRAMCFG:HYNIX_8GB,NANDCFG:ITLC_S4E_1P0T_HY

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:GOOD,DRAMCFG:HYNIX_8GB,NANDCFG:ITLC_S4E_1P0T_SD

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:GOOD,DRAMCFG:MICRON_8GB,NANDCFG:ITLC_S4E_1P0T_HY

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:GOOD,DRAMCFG:MICRON_8GB,NANDCFG:ITLC_S4E_1P0T_SD

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:GOOD,DRAMCFG:SAMSUNG_8GB,NANDCFG:ITLC_S4E_1P0T_HY

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:GOOD,DRAMCFG:SAMSUNG_8GB,NANDCFG:ITLC_S4E_1P0T_SD

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:GOOD,DRAMCFG:HYNIX_16GB,NANDCFG:ITLC_S4E_1P0T_HY

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:GOOD,DRAMCFG:HYNIX_16GB,NANDCFG:ITLC_S4E_1P0T_SD

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:GOOD,DRAMCFG:MICRON_16GB,NANDCFG:ITLC_S4E_1P0T_HY

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:GOOD,DRAMCFG:MICRON_16GB,NANDCFG:ITLC_S4E_1P0T_SD

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:GOOD,DRAMCFG:SAMSUNG_16GB,NANDCFG:ITLC_S4E_1P0T_HY

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:GOOD,DRAMCFG:SAMSUNG_16GB,NANDCFG:ITLC_S4E_1P0T_SD

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

EEEE
NRK3
MYW4
NRKG
MYWH
NRKT
MYWV
NRL5
MYX6
NRLJ
MYXK
NRLW
MYXX

BOM NUMBER BOM NAME BOM OPTIONS

639-09934

639-09937

PCBA,MLB-TKSB,GOOD,HY-8G,HY-2.0T,X1783
PCBA,MLB-TKSB,GOOD,HY-8G,SD-2.0T,X1783639-08817
PCBA,MLB-TKSB,GOOD,MI-8G,HY-2.0T,X1783639-09935
PCBA,MLB-TKSB,GOOD,MI-8G,SD-2.0T,X1783639-08818
PCBA,MLB-TKSB,GOOD,SS-8G,HY-2.0T,X1783639-09936

PCBA,MLB-TKSB,GOOD,SS-8G,SD-2.0T,X1783639-08819
PCBA,MLB-TKSB,GOOD,HY-16G,HY-2.0T,X1783
PCBA,MLB-TKSB,GOOD,HY-16G,SD-2.0T,X1783639-08820
PCBA,MLB-TKSB,GOOD,MI-16G,HY-2.0T,X1783639-09938
PCBA,MLB-TKSB,GOOD,MI-16G,SD-2.0T,X1783639-08821
PCBA,MLB-TKSB,GOOD,SS-16G,HY-2.0T,X1783639-09939
PCBA,MLB-TKSB,GOOD,SS-16G,SD-2.0T,X1783639-08822

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:GOOD,DRAMCFG:HYNIX_8GB,NANDCFG:ITLC_S4E_2P0T_HY

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:GOOD,DRAMCFG:HYNIX_8GB,NANDCFG:ITLC_S4E_2P0T_SD

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:GOOD,DRAMCFG:MICRON_8GB,NANDCFG:ITLC_S4E_2P0T_HY

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:GOOD,DRAMCFG:MICRON_8GB,NANDCFG:ITLC_S4E_2P0T_SD

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:GOOD,DRAMCFG:SAMSUNG_8GB,NANDCFG:ITLC_S4E_2P0T_HY

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:GOOD,DRAMCFG:SAMSUNG_8GB,NANDCFG:ITLC_S4E_2P0T_SD

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:GOOD,DRAMCFG:HYNIX_16GB,NANDCFG:ITLC_S4E_2P0T_HY

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:GOOD,DRAMCFG:HYNIX_16GB,NANDCFG:ITLC_S4E_2P0T_SD

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:GOOD,DRAMCFG:MICRON_16GB,NANDCFG:ITLC_S4E_2P0T_HY

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:GOOD,DRAMCFG:MICRON_16GB,NANDCFG:ITLC_S4E_2P0T_SD

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:GOOD,DRAMCFG:SAMSUNG_16GB,NANDCFG:ITLC_S4E_2P0T_HY

CMN_PARTS_BOM,DEV_PARTS_BOM,ALTERNATE,CPU_ICLY:GOOD,DRAMCFG:SAMSUNG_16GB,NANDCFG:ITLC_S4E_2P0T_SD

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

BOM Variants 3

DRAWING NUMBER

Apple Inc.

REVISION

BRANCH

PAGE

SHEET

051-05232

2.0.0

proto4b

143 OF 152

84 OF 86

D

C

B

A

SIZE

D

8

67

35 4

2

1

Alternates

www.laptoprepairsecrets.com

678

3 245

1

D

C

B

PART NUMBER

107S00033

107S00076

107S0248

128S00011128S00026

128S00031 ALL

152S00786 152S00344 ALL

152S00785

152S00182 152S00703

128S0364

128S00039

128S0302 128S00038

128S0631 128S0352 ALL

376S00204 376S00203

376S00007 376S1179 ALL

197S00046

138S1101

371S00180 ALL371S00077

138S00181

128S00011

197S00118197S00120

152S00269152S00368

152S00477 ALL

128S0264 ALL

152S00730152S00734 ALL

107S00087107S00029 ALL

376S00203 ALL376S00227

376S00203376S00226

128S0436128S0445 ALL

128S0436 ALL128S0392

128S0311128S00042 ALL

128S0311128S00043 ALL

128S00098128S00058 ALL

376S1179376S00228 ALL

138S00060138S00084 ALL

197S00036197S00047 ALL

197S00036197S00048 ALL

197S00036 ALL

138S0831138S00049

138S0835138S00291

353S3384

371S00181

ALL107S00034

ALL107S00044

ALL107S0178107S00139

ALL107S0250

ALL128S00011128S00087

ALL

ALL

ALL

ALL

ALL128S00038

ALL

ALL

ALL

ALL152S00268152S00800

ALL128S0311128S0329

ALL311S0273311S00060

ALL138S0738

ALL

ALL138S0914138S00109

ALL

ALL138S0835

ALL353S01320 353S01346

ALL132S00010132S00229

ALL353S4376

ALL371S00220

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

rdar://problem/31026333

rdar://problem/31026474

rdar://problem/31026896

rdar://problem/31026938

rdar://problem/31104542

rdar://problem/31104542

rdar://problem/31104542

rdar://problem/32474316

rdar://problem/32986667

rdar://problem/32988704

rdar://problem/32988930

rdar://problem/32989310

rdar://problem/32981497

rdar://problem/32984088

rdar://problem/32984088

rdar://problem/32984967

rdar://problem/32986265

rdar://problem/33006830

rdar://problem/32990227

rdar://problem/32990227

rdar://problem/32990227

rdar://problem/32986455

rdar://problem/32981936

rdar://problem/32981936

rdar://problem/32982452

rdar://problem/32982452

rdar://problem/32982452

rdar://problem/32983704

rdar://problem/33006121

rdar://problem/33006121

rdar://problem/31227858

rdar://problem/31509365

rdar://problem/31509365

rdar://problem/31509365

rdar://problem/31512477

rdar://problem/31491081

rdar://problem/31927114

rdar://problem/31284882

rdar://problem/46640234

rdar://problem/48092454

rdar://problem/48092454

rdar://problem/48088900

rdar://problem/47305238

rdar://problem/48088312

rdar://problem/48058127

TABLE_ALT_HEAD

Alternate Primary
Vendor

TABLE_ALT_ITEM

TFT

TABLE_ALT_ITEM

Yageo

TABLE_ALT_ITEM

Panasonic

TABLE_ALT_ITEM

TFT

TABLE_ALT_ITEM

Cyntec
Cyntec
Murata
Cyntec
KemetPanasonic

TABLE_ALT_ITEM

NEC

TABLE_ALT_ITEM

Rohm

TABLE_ALT_ITEM

Epson

TABLE_ALT_ITEM

NEC

TABLE_ALT_ITEM

Cyntec

TABLE_ALT_ITEM

Chilisin

TABLE_ALT_ITEM

Kemet
Kemet
TXC
Cyntec
Murata
Murata

Cyntec Chilisin

TABLE_ALT_ITEM

Kemet

TABLE_ALT_ITEM

Panasonic
KemetNEC

TABLE_ALT_ITEM

Kemet

TABLE_ALT_ITEM

NEC

TABLE_ALT_ITEM

Panasonic

Chilisin Cyntec

TABLE_ALT_ITEM

TFT

TABLE_ALT_ITEM

Fairchild

TABLE_ALT_ITEM

Diodes

TABLE_ALT_ITEM

Vishay

TABLE_ALT_ITEM

NEC

TABLE_ALT_ITEM

Panasonic

TABLE_ALT_ITEM

Panasonic

TABLE_ALT_ITEM

Kemet

TABLE_ALT_ITEM

Panasonic

TABLE_ALT_ITEM

Panasonic

TABLE_ALT_ITEM

Rohm

TABLE_ALT_ITEM

AOS

TABLE_ALT_ITEM

Fairchild

TABLE_ALT_ITEM

Taiyo

TABLE_ALT_ITEM

Kyocera

TABLE_ALT_ITEM

Murata

TABLE_ALT_ITEM

Epson

TABLE_ALT_ITEM

Yageo
Vishay
Vishay
Vishay Samsung
Cyntec
Kemet
Panasonic
NEC
NEC
NEC
NEC
Vishay
Vishay
Murata
TXC
TXC
TXC

Diodes Philips

TABLE_ALT_ITEM

Murata

TABLE_ALT_ITEM

Diodes

TABLE_ALT_ITEM

Kyocera

TABLE_ALT_ITEM

Kyocera

TABLE_ALT_ITEM

Samsung
NXP
Murata
Murata
MurataKyocera

TABLE_ALT_ITEM

Samsung

TABLE_ALT_ITEM

NXP

TABLE_ALT_ITEM

Taiyo

TABLE_ALT_ITEM

ON Semi

TABLE_ALT_ITEM

ON Semi

Murata
ON Semi
Murata
TI
Diodes

PART NUMBER

138S00035

138S00035

132S00012

138S0777

138S0847138S0786 ALL

152S00204152S00398

152S00311152S00724

152S00592152S00726

152S00725 152S00590

155S00190

155S0667155S00007

155S0894155S00203

740S00028740S0118

155S00401

155S0741

311S0398311S00121

138S1100

311S00104

138S0846 138S0811 ALL

152S00359

376S1106 ALL

371S00074

335S00270 ALL

335S00213 ALL335S0888

378S00029 ALL

311S00178 ALL

138S00116 138S00071 ALL

152S00765 152S00239 ALL

152S00737 152S00733 ALL

152S00997

311S00247

353S01615 ALL

311S00091 ALL

353S01042353S01041 ALL

138S0860138S0775

376S0604

740S0159 ALL740S00041

376S0678

371S0602 ALL

132S0640 ALL132S00176

311S0436

335S00203

378S00002

311S00177

138S00071138S00117 ALL

152S00476 ALL

311S00139 ALL

353S4160

376S00398376S00401 ALL

376S00398376S00403 ALL

ALL138S00077

ALL138S00093

ALL132S0401

ALL138S00015

ALL

ALL

ALL

ALL

ALL155S0914

ALL

ALL

ALL

ALL155S00067

ALL155S0361

ALL

ALL138S00056

ALL311S00129311S00156

ALL

ALL376S1053

ALL152S00253

ALL311S0426 311S00007

ALL155S0665 155S00232

ALL311S00138

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

rdar://problem/31167038

rdar://problem/31167038

rdar://problem/31180314

rdar://problem/31254330

rdar://problem/31253709

rdar://problem/33011314

rdar://problem/33011211

rdar://problem/33011437

rdar://problem/33011526

rdar://problem/32364855

rdar://problem/32415629

rdar://problem/32435328

rdar://problem/32477706

Per CE

rdar://problem/32406745

rdar://problem/32474809

rdar://problem/31411109

rdar://problem/31509861

rdar://problem/31816775

rdar://problem/31941459

rdar://problem/46642485

rdar://problem/30812097

rdar://problem/30812097

rdar://problem/30812097

rdar://problem/30812097

rdar://problem/30812097

rdar://problem/33675478

rdar://problem/33924830

rdar://problem/32364084

rdar://problem/32474939

rdar://problem/33516617

rdar://problem/33927828

rdar://problem/33932183

rdar://problem/39513462

rdar://problem/46491734

rdar://problem/46491734

rdar://problem/40632537

rdar://problem/46492368

rdar://problem/46492529

rdar://problem/52919470

rdar://problem/52860697

per J214

per J214

TABLE_ALT_HEAD

Alternate Alternate
VendorVendor

TABLE_ALT_ITEM

Taiyo

TABLE_ALT_ITEM

Kyocera

TABLE_ALT_ITEM

Murata/TDK

TABLE_ALT_ITEM

Samsung/Taiyo

TABLE_ALT_ITEM

Samsung

TABLE_ALT_ITEM

Taiyo

TABLE_ALT_ITEM

Chilisin

TABLE_ALT_ITEM

Chilisin

TABLE_ALT_ITEM

Chilisin

TABLE_ALT_ITEM

Taiyo

TABLE_ALT_ITEM

Taiyo

TABLE_ALT_ITEM

Taiyo Murata

TABLE_ALT_ITEM

Polytronics

TABLE_ALT_ITEM

TDK

TABLE_ALT_ITEM

Murata

TABLE_ALT_ITEM

Diodes

TABLE_ALT_ITEM

Taiyo/TDK

TABLE_ALT_ITEM

TI

TABLE_ALT_ITEM

ST

TABLE_ALT_ITEM

Nexperia

TABLE_ALT_ITEM

TABLE_ALT_ITEM

Samsung

TABLE_ALT_ITEM

Diodes

TABLE_ALT_ITEM

Chilisin

TABLE_ALT_ITEM

Bourns

TABLE_ALT_ITEM

Fairchild

TABLE_ALT_ITEM

Infineon

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

Murata

TABLE_ALT_ITEM

TABLE_ALT_ITEM

Adesto

TABLE_ALT_ITEM

ON Semi

TABLE_ALT_ITEM

Lite-On

TABLE_ALT_ITEM

On Semi

TABLE_ALT_ITEM

Taiyo

TABLE_ALT_ITEM

Keyocera

TABLE_ALT_ITEM

Chilisin

TABLE_ALT_ITEM

Chilisin

TABLE_ALT_ITEM

Chilisin

TABLE_ALT_ITEM

Nexperia

TABLE_ALT_ITEM

TI

TABLE_ALT_ITEM

Toshiba

TABLE_ALT_ITEM

NXP

Primary
Vendor

Murata
Murata
Taiyo
Murata

Murata/Taiyo

Cyntec
Cyntec
Cyntec
Cyntec
Panasonic
Panasonic

Bussman
Murata
TDKPanasonic

NXP/Nexperia

Murata
ON Semi
TI
TI
Murata
Murata
Fairchild
Cyntec
Littlefuse
Vishay
NXP
MurataYageo
DiodesNXP
TDK
TINexperia
Macronix
STMicro
Everlight
TI
Murata
Murata
Cyntec
Cyntec
Murata
TI
TI
Diodes
Diodes

PART NUMBER

138S00047 ALL

152S00403 ALL152S00322

376S1080 376S0820 ALL

377S00123 ALL

377S0077

377S0184 377S0155

131S00134 131S00041 ALL

353S02004 ALL353S01989

353S02005 353S2216

132S00202 ALL132S00175

376S00282 376S1128 ALL

131S00142

107S00053 ALL107S00071

371S00085 ALL371S00190

353S00832 ALL

376S00373

138S00229 ALL138S00107

138S00022 138S0801

372S0183 ALL

114S00002 ALL

353S02064 353S4471 ALL

377S00106 377S00166 ALL

371S00217 371S00079 ALL

197S00244 197S00227 ALL

138S00097 ALL138S0750

138S00164 ALL138S00138

138S00139 ALL138S00138

311S00096 311S00040 ALL

353S02017 ALL353S4471

138S00073

ALL376S0855376S00399

107S0255

377S00031

377S0183 ALL

376S00019376S1137 ALL

155S0302155S0706 ALL

311S0372

132S0312 ALL

353S4471353S00525 ALL

353S4471

152S01085152S01090

372S00033

114S0618

353S02068 ALL353S01824

371S00064371S00193 ALL

152S1701152S00812 ALL

ALL107S0240

ALL

ALL

ALL311S0562

ALL376S1147376S00281

ALL

ALL376S1038

ALL

ALL353S4471353S02065

ALL138S1086138S00087

ALL138S0818138S0852

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

rdar://problem/34812612

rdar://problem/34319209

rdar://problem/34320959

per J214

rdar://problem/33930580

rdar://problem/35399063

rdar://problem/35403837

rdar://problem/35404095

rdar://problem/33955940

rdar://problem/32364222

rdar://problem/36353852

rdar://problem/48583206

rdar://problem/36563854

rdar://problem/36674713

rdar://problem/47654696

rdar://problem/33904000

rdar://problem/36993892

rdar://problem/40145084

rdar://problem/40314867

rdar://problem/46491385

rdar://problem/46491385

rdar://problem/46491572

rdar://problem/46487936

rdar://problem/46490666

rdar://problem/46631987

rdar://problem/40667960

rdar://problem/50349170

rdar://problem/47304661

rdar://problem/48583357

rdar://problem/46491385

rdar://problem/46491385

rdar://problem/47062814

rdar://problem/50601049

rdar://problem/50678168

rdar://problem/50831008

rdar://problem/51419709

rdar://problem/51371740

rdar://problem/51371269

rdar://problem/51370814

rdar://problem/51370814

rdar://problem/51371859

rdar://problem/51371555

rdar://problem/52837421

TABLE_ALT_HEAD

Vendor

TABLE_ALT_ITEM

Taiyo

TABLE_ALT_ITEM

Chilisin

TABLE_ALT_ITEM

Diodes

TABLE_ALT_ITEM

ON Semi

TABLE_ALT_ITEM

TFT

TABLE_ALT_ITEM

Semtech

TABLE_ALT_ITEM

ST

TABLE_ALT_ITEM

Infineon

TABLE_ALT_ITEM

Vishay

TABLE_ALT_ITEM

Taiyo

TABLE_ALT_ITEM

Murata Taiyo

TABLE_ALT_ITEM

ON Semi

TABLE_ALT_ITEM

ON Semi

TABLE_ALT_ITEM

Murata/Taiyo

TABLE_ALT_ITEM

TI

TABLE_ALT_ITEM

Nexperia

TABLE_ALT_ITEM

Samsung

TABLE_ALT_ITEM

Cyntec

TABLE_ALT_ITEM

ON Semi

TABLE_ALT_ITEM

Vishay

TABLE_ALT_ITEM

Fairchild Vishay

TABLE_ALT_ITEM

Alpha Omega

TABLE_ALT_ITEM

Chilisin

TABLE_ALT_ITEM

Diodes

TABLE_ALT_ITEM

Kyocera

TABLE_ALT_ITEM

Taiyo Yuden

TABLE_ALT_ITEM

Diodes

TABLE_ALT_ITEM

Panasonic

TABLE_ALT_ITEM

ON Semi

TABLE_ALT_ITEM

Vishay

TABLE_ALT_ITEM

Vishay

TABLE_ALT_ITEM

ON Semi

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TXC

TABLE_ALT_ITEM

ROHM NXP

TABLE_ALT_ITEM

Chilisin

TABLE_ALT_ITEM

TABLE_ALT_ITEM

Taiyo Murata

TABLE_ALT_ITEM

Taiyo

TABLE_ALT_ITEM

Murata

TABLE_ALT_ITEM

Diodes NXP

TABLE_ALT_ITEM

Samsung Murata

TABLE_ALT_ITEM

AOS Vishay

Primary
Vendor

Murata
Murata
ON Semi
Diodes
Cyntec
ON Semi
Infineon
ON Semi
Diodes
Murata

TI
TI

Kyocera/Samsung

NXP/Nexperia

Diodes
Murata
Yageo
Diodes
Vishay

ON Semi
Murata
TI
Murata
Murata
ON Semi
Cyntec
TI
Vishay
Vishay
Semtech
NexperiaROHM
NDK

Cyntec
MurataTaiyo

Kyocera
Kyocera

D

C

B

A

8

67

A

PAGE TITLE

BOM Alternates

DRAWING NUMBER

051-05232

Apple Inc.

REVISION

2.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

35 4

2

BRANCH

proto4b

PAGE

145 OF 152

SHEET

85 OF 86

1

SIZE

D

678

www.laptoprepairsecrets.com

Power Supply Sub-System

3 245

1

D

D

C

C

B

B

A

8

67

A

PAGE TITLE

Power Block Diagram

DRAWING NUMBER

051-05232

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

35 4

2

REVISION

2.0.0

BRANCH

proto4b

PAGE

152 OF 152

SHEET

86 OF 86

1

SIZE

D