Apple K18 User Manual

TABLE_TABLEOFCONTENTS_ITEM

3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

8

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT

3

B

7

ECNREV

BRANCH

DRAWING NUMBER

REVISION

SIZE

D

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

DRAWING TITLE

THE POSESSOR AGREES TO THE FOLLOWING:

Apple Inc.

SHEET

R

DATE

D

A

C

THE INFORMATION CONTAINED HEREIN IS THE

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

C

3456

D

B

8 7 6 5 4 2 1

12

APPD

CK

DESCRIPTION OF REVISION

TABLE_TABLEOFCONTENTS_HEAD

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

TABLE_TABLEOFCONTENTS_HEAD

TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

DRAWING

TABLE_TABLEOFCONTENTS_HEAD

02/01/10

SCHEM,WHITE_ARROW,MLB,K18

Schematic / PCB #’s

ALIASES RESOLVED

1 OF 101

<SCH_NUM>

1 OF 132

<ECO_DESCRIPTION>

06/15/2009

49

45

SMC

K17_REF

05/29/2009

48

44

Front Flex Support

K19_MLB

06/15/2009

46

43

External USB Connectors

K17_REF

10/01/2009

45

42

SATA Connectors

T27_REF

05/29/2009

43

41

FireWire Ports

K19_MLB

05/29/2009

42

40

FireWire Port Power

K19_MLB

05/29/2009

41

39

FireWire LLC/PHY (FW643)

K19_MLB

06/15/2009

40

38

Ethernet Connector

K17_REF

08/20/2009

39

37

Ethernet PHY (Caesar II/IV)

T27_REF

10/06/2009

37

36

USB HUB 2

K23F

10/07/2009

36

35

USB HUB 1

K18_MLB

08/26/2009

35

34

SecureDigital Card Reader

T27_REF

06/15/2009

34

33

X16/ALS/CAMERA CONNECTOR

K18_COMMS

06/15/2009

33

32

FSB/DDR3/FRAMEBUF Vref Margining

K17_REF

06/15/2009

32

31

CPU Memory S3 Support

K17_REF

MASTER

31

30

DDR3 SO-DIMM Connector B

MASTER

30

29

DDR3 Byte/Bit Swaps

MASTER

29

28

DDR3 SO-DIMM Connector A

MASTER

06/15/2009

28

27

Chipset Support

K17_REF

06/23/2009

27

26

Clock (CK505)

K17_MLB

06/15/2009

26

25

eXtended Debug Port (XDP)

K17_REF

06/15/2009

25

24

CPU/PCH GFX Decoupling

K17_REF

06/15/2009

24

23

PCH Non-GFX Decoupling

K17_REF

06/15/2009

23

22

PCH Grounds

K17_REF

06/15/2009

22

21

PCH Power

K17_REF

06/15/2009

21

20

PCH MISC

K17_REF

10/07/2009

20

19

PCH PCI/FlashCache/USB

K18_MLB

06/15/2009

19

18

PCH DMI/FDI/Graphics

K17_REF

08/24/2009

18

17

PCH SATA/PCIE/CLK/LPC/SPI

K17_REF

06/15/2009

17

16

CPU Non-GFX Decoupling (2 of 2)

K17_REF

06/15/2009

16

15

CPU Non-GFX Decoupling (1 of 2)

K17_REF

06/15/2009

15

14

CPU Grounds

K17_REF

06/15/2009

14

13

CPU Power (2 of 2)

K17_REF

06/15/2009

13

12

CPU Power (1 of 2)

K17_REF

06/15/2009

12

11

CPU DDR3 Interfaces

K17_REF

06/15/2009

11

10

CPU Clock/Misc/JTAG

K17_REF

06/15/2009

10

9

CPU DMI/PEG/FDI/RSVD

K17_REF

06/11/2009

9

8

Signal Aliases

K17_REF

MASTER

8

7

Power Aliases

MASTER

7

6

Functional / ICT Test

MASTER

05/28/2009

5

BOM Configuration

K17_REF

MASTER

4

Revision History

MASTER

06/30/2009

3

Power Block Diagram

K17_REF

06/30/2009

2

System Block Diagram

K17_REF

Misc Power Supplies

K18_POWER

06/10/2009

99

90

LCD Backlight Support

K19_MLB

05/29/2009

98

89

LCD BACKLIGHT DRIVER

K18_BKLT

07/29/2009

97

88

Graphics MUX (GMUX)

K17_REF

06/15/2009

96

87

1V8 / 1V55 FB Power Supply

K18_POWER

06/26/2009

95

86

DisplayPort Connector

K17_REF

06/15/2009

94

85

Muxed Graphics Support

K17_REF

06/15/2009

93

84

LVDS Display Connector

K19_MLB

05/29/2009

90

83

GPU (GT216) CORE SUPPLY

K18_POWER

07/14/2009

89

82

NV GT216 VIDEO INTERFACES

K17_REF

06/15/2009

88

81

GT216 GPIOS & STRAPS

K17_REF

06/15/2009

87

80

NV GT216 GPIO/MIO/MISC

K17_REF

06/15/2009

86

79

GDDR3 Frame Buffer B (Top)

K17_REF

06/15/2009

85

78

GDDR3 Frame Buffer A (Top)

K17_REF

06/15/2009

84

77

NV GT216 FRAME BUFFER I/F

K17_REF

06/15/2009

82

76

NV GT216 CORE/FB POWER

K17_REF

06/15/2009

81

75

NV GT216 PCI-E

K17_REF

06/15/2009

80

74

Power Control

K17_REF

06/15/2009

79

73

Power FETs

K18_POWER

06/10/2009

78

72

Misc Power Supplies

K18_POWER

06/29/2009

77

71

CPUVTT (1.05V) Power Supply

K18_POWER

07/14/2009

76

70

GFX IMVP VCore Regulator

K18_POWER

07/08/2009

75

69

CPU IMVP VCore Regulator

K18_POWER

06/29/2009

74

68

1.5V DDR3 Supply

K18_POWER

07/14/2009

73

67

5V / 3.3V Power Supply

K18_POWER

07/13/2009

72

66

PBus Supply & Battery Charger

K18_POWER

06/30/2009

70

65

DC-In & Battery Connectors

K18_POWER

06/30/2009

69

64

AUDIO: JACK TRANSLATORS

K18_AUDIO

07/29/2009

68

63

AUDIO: JACKS

K18_AUDIO

07/29/2009

67

62

AUDIO: SPEAKER AMP

K18_AUDIO

07/29/2009

66

61

AUDIO: HEADPHONE FILTER

K18_AUDIO

07/29/2009

65

60

AUDIO: LINE INPUT FILTER

K18_AUDIO

07/29/2009

63

59

AUDIO: CODEC/REGULATOR

K18_AUDIO

09/21/2009

62

58

SPI ROM

K17_REF

06/15/2009

61

57

DEBUG SENSORS AND ADC

K18_SENSORS

07/07/2009

60

56

Sudden Motion Sensor (SMS)

K19_MLB

05/29/2009

59

55

WELLSPRING 2

K19_MLB

05/29/2009

58

54

WELLSPRING 1

K19_MLB

05/29/2009

57

53

Fan Connectors

K19_MLB

05/29/2009

56

52

Thermal Sensors

K18_SENSORS

06/18/2009

55

51

Current Sensing

K18_SENSORS

07/02/2009

54

50

Current & Voltage Sensing

K18_SENSORS

06/29/2009

53

49

K18 SMBus Connections

K18_SENSORS

06/18/2009

52

48

LPC+SPI Debug Connector

K17_MLB

06/23/2009

51

47

101

132

BluRay Decrypter Card Connector

K17_REF

06/15/2009

100

109

PCB Rule Definitions

K17_REF

06/15/2009

99

108

Project Specific Constraints

K17_REF

06/15/2009

98

107

GPU (GT216) CONSTRAINTS

K17_REF

06/15/2009

97

106

SMC Constraints

K17_REF

06/15/2009

96

105

FireWire Constraints

K17_REF

06/15/2009

95

104

Ethernet Constraints

K17_REF

06/15/2009

94

103

PCH Constraints 2

K17_REF

06/15/2009

93

102

PCH Constraints 1

K17_REF

06/15/2009

92

101

Memory Constraints

K17_REF

06/15/2009

MASTER

1

Table of Contents

MASTER

SCHEM,WHITE_ARROW,MLB,K18

SyncPage Contents

Date

(.csa)

820-2850 CRITICAL

PCB

1

PCBF,WHITE_ARROW,MLB,K18

Date

(.csa)

SyncPage Contents

SMC Support

K18_SENSORS

06/29/2009

50

46 91

100

CPU Constraints

K17_REF

06/15/2009

LAST_MODIFIED=Mon Feb 1 10:13:48 2010

ABBREV=DRAWING

TITLE=MLB

Page Sync

Date

Contents

(.csa)

051-8504

1

SCH

CRITICAL

SCHEM,WHITE_ARROW,MLB,K18

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

U9600

GMUX

PG 85

J9400

PG 71

CONN

LVDS

PG 84

DISPLAY PORT

J9000

CONN

LVDS OUT

DP OUT

DVI OUT

HDMI OUT

J4501

SATA Conn

ODD

P8 40

SATA

P8 40

HD

Conn

J4500

1.05V/3GHZ.

P8 26

CK505

CLOCK

U2700

PG 33

CAMERA

SPI

PG 33

PG 17

IBEX PEAK-MPCH

U1800

INTEL

IR

Bluetooth

E-NET

XDP CONN

Misc

Conn

J4310

Mini PCI-E

FW643

AirPort

PG 39

U4100

PG 37

PG 36

Conn

E-NET

PG 35

BCM5764M

J4000

U3900

PG 34

CONN

EXPRESSCARD

J3500

E-NET

PEG

PG 17 PG 17

PCI-E

PG 17

(UP TO 16 LINES)

JTAG

76543

PG 19

PCI-E

PCI

PG 61

J6780,6781,6782,6700,6750

Amp

HEADPHONE

U6500

U6610,6620,6630,6640,6650

Line Out

Amp

PG 59 PG 60

Line In Speaker

PG 57

Codec

PG 17

PG 18

TMDS OUT

HDA

2

DIMM’s

PG 47

PG 17

SMB

PG 41

SMB

Connectors

EXTERNAL

J4600,J4610,4720

PG 19

(UP TO 14 DEVICES)

KEYBOARD

TRACKPAD/

J5713

PG 52PG 33

USB

J3401J3401J3401

1110 1213

98

PG 46

Port80,serial

LPC Conn

PG 63

PG 44

POWER SENSE

J5650,5660

FAN CONN AND CONTROL

PG 51

U4900

J5100

Ser

PG 44

Prt

SMC

PG 17

PG 56

PG 17

PG 20

RGB OUT

PG 17

SATA

BUFFER

CTRL

10

PG 18 PG 18 PG 20

GPIO

PG 17

FDI DMI

CLK

PWR

LPC

RTC

PG 73

PG 9

PRAPHICS

NV GT216

2.X GHZ

ARRANDALE

INTEL CPU

U8000

PG 28,30

DIMM

J2900

2 UDIMMs

DDR3-1067/1333MHZ

PG 25

U2600

U4900

Amp

Boot ROM

CONN

BSBB,0

ADC Fan

TEMP SENSOR

SPI

DC/BATT

USB

U6100

J6950

U6200

Amps

GB

J3400

PG 28

POWER SUPPLY

Audio

Conns

XP2-5

System Block Diagram

SYNC_MASTER=K17_REF

SYNC_DATE=06/30/2009

2 OF 132

<SCH_NUM>

2 OF 101

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

SMC_DCIN_ISENSE

SMC_CPU_ISENSE

PPVBAT_G3H_CHGR_REG

PP3V3_S0

J6950

2S4P

U7000

VIN

A

PGOOD

VR_ON

DELAY

RC

ADJ2

VCC

RST*

DELAY

U4900

P60

PB17A

GMUX

P3V3GPU_EN

P1V8_S0GPU_EN

EN2

PB17B

PB18A

R7020

LT3470A

SMC

EG_RAIL2_EN

EG_RAIL1_EN

EG_RAIL4_EN

SMC_RESET_L

Q5315

EG_RAIL3_EN GPUVCORE_EN

P1V1GPU_EN

PB16B

U9600

U8900

AC

J6900

VLDOIN

PPDCIN_G3H_OR_PBUS_R

DCIN(16.5V)

6A FUSE

F6905

F7040

K17 POWER SYSTEM ARCHITECTURE

R6905

(PAGE 63)

U6990

U5000

SMC PWRGD

NCP303LSN

VIN

(PAGE 45)

ENABLE

3.425V G3HOT

PP3V3_S5_AVREF_SMC

U5001

U4900

(PAGE 44)

SMC_ONOFF_L

SMC_TPAD_RST_L

VOUT

VR5020

U2850

SMC_RESET_L

SYSRST(PA2)

RESET*

P17(BTN_OUT)

RES*

PM_PWRBTN_L

U1000

PM_PWRBTN_L

PM_SYSRST_L

IMVP_VR_ON

PWRBTN#

PWR_BUTTON(P90)

PLT_RERST_L

SMC_ADAPTER_EN

PM_RSMRST_L

DRAMPWROK

SYS_RERST#

PLTRST#

PROCPWRGD

PS_PWRGD

PM_PCH_PWRGD

RC

Q7055

SMC

ALL_SYS_PWRGD

P5VS3_PGOOD

P1V8S0_PGOOD

PP3V3_S0_PWRCTL

PP1V05_S0

PP1V5_S0

S0PGOOD_PWROK

SLP_S3_L(P93)

SLP_S4_L(P94)

SMC_ONOFF_L

RSMRST_PWRGD

(PAGE 9~14)

VCCCPUPWRGD

SM_DRAMPWROK

(PAGE 17~22)

U1800

SMC AVREF SUPPLY

IBEX PEAK M

RSMRST#

ACPRESENT

CPU_PWRGD PM_MEM_PWRGD

(P64)

RSMRST_OUT(P15)

99ms DLY

IMVP_VR_ON(P16)

SLP_S5_L(P95)

PM_SLP_S3_L

ADJ1

U7971

ISL88042IRTEZ

(PAGE 72)

TRST = 200mS

PM_ALL_GPU_PGOOD

VOUT

IN

ADAPTER

ISL6259HRTZ

SMC_BATT_ISENSE

A

PPBUS_G3H

V

BATTERY CHARGER

(PAGE 64)

SMC_PBUS_VSENSE

PPVBATT_G3H_CONN

(6 TO 8.4V)

CHGR_BGATE

PL32A

(PAGE 86)

(PAGE 44)

SMC_PM_G2_EN

P3V3S5_EN

RC

DELAY

RC

SLP_S5#(E4)

IBEX_PEAK_M

U1800

PM_SLP_S4_L

PM_SLP_S5_L

RSMRST_IN(P13)

PWRGD(P12)

CPU

(PAGE 17~22)

R7978

PM_SLP_S3_L_R

P1V8S0_EN

RC

P1V5DDR_EN

P1V2GMUX_EN

DELAY

RC

P5VS0_EN

CPUVTTS0_EN

DELAY

P3V3S0_EN

PBUSVSENS_EN

PP3V42_G3H

A

(PAGE 81)

PGOOD

U5410

V

PPVCORE_GPU

SMC_GPU_VSENSE

F7041

VDD

PP5V_S3_GPUVCORE

GPU VCORE

ISL6263C

SMC_GPU_ISENSE

PGOOD

EN

VOUT

VIN

(PAGE 45)

PP5V_S0_CPUVTTS0

1.05V

A

(PAGE 69)

CPUVTTS0_PGOOD

CPUVTTS0_EN

TPS51513

U7600

R7640

PPCPUVTT_S0

SMC_CPU_FSB_ISENSE

GPUVCORE_PGOOD

SMC_CPU_HI_ISENSE

GPUVCORE_EN

VIN

CPU VCORE

CPUIMVP_GOOD

PPVCORE_S0_CPU

SMC_CPU_VSENSE

R7050

VIN

VOUT

1.05V AUX

VIN

U7790

R5413

VIN

PPVBAT_G3H_CHGR_R

P1V1GPU_EN

P1V8FB_EN

EN1

VOUT1

VOUT

ISL9522

VR_ON

1.5V

VOUT2

VIN

PP1V1_S0GPU

VOUT1

1.103V(L/H)

DDRVTT_EN

0.75V

SMC_GPU_1V8_ISENSE1.8V(R/H)

PPDDR_S3_REG

U7400

PP1V5_S3

V

U5440

SMC_CPU_DDR_VSENSE

(PAGE 67)

CPUIMVP_VR_ON

A

R5388

R7350

SMC_DDR_ISENSE

A

PPVTT_S0_DDR_LDO

PP1V8_S0GPU

(R/H)

(PAGE 85)

U9500

ISL6236

POK1

P1V1GPU_PGOOD

LTC1872

U7201

P5VS3_EN

ENA

U9700

PM_SLP_S3_L

(PAGE 87)

SLP_S4#(H7)

P5VS3_EN

PM_SLP_S4_L

SLP_S3#(P12)

P3V3S3_EN

DDRREG_EN

Q9806

PM_SLP_S5_L

VOUT

SMC_ADAPTER_EN&&PM_SLP_S3_L

(PAGE 70)

GFX_VR_EN

PGOOD

GFXIMVP_PGOOD

A

Q4260

U7500

(PAGE 68)

DPRSLPVR

R7540

V

SMC_GFX_VSENSE

TPS51981

GFXIMVP_ISENSE

VOUT

PFWBOOST

VR_ON

GFX_DPRSLPVR

VIN

&&

PGOOD2PGOOD1

APP001

BKLT_EN

LCD_BKLT_EN

P5VS3_PGOOD

P3V3S5_EN

BKLT_PLT_RST_L

TPS51980

POK2

VIN

5V

(L/H)

VOUT1

EN1

PP3V3_S5

VOUT2

PP1V5_S0

PGOOD

U7801

TPS51116

U7300

PPVOUT_S0_LCDBKLT

Q7870

PP3V3_S3

VIN

EN

OUT

PP3V3_S0_GPU

P3V3GPU_EN

P3V3S5_PGOOD

Q3810

VOUT

PGOOD

Q7810

Q7922

PP1V5_EXP_S0

PP3V3_ENET

P1V5_EXP_S0_EN

P3V3S3_EN

PP1V8_S0

EN

P3V3S0_EN

V

PPVCORE_S0_GFX

A

PP3V3_S0_FET

P1V8_S0_EN

FW_PWR_EN

P1V8S0_PGOOD

Q7830

Q4291

PP3V3_FW_FET

(PAGE 70)

U7720

ISL8014

VIN

PM_SLP_S3_L&&WOL_EN||SMC_ADAPTER_EN

(PAGE 70)

U7710

ISL8009B

VOUT

P1V2ENET_EN

VIN

EN

U7980

PM_ALL_GPU_PGOOD

Q7850

PP1V2_ENET

P1V2GMUX_EN

PP1V2_GMUX_FET

(PAGE 70)

U7760

ISL8009B

SLG5AP020

VOUT

ON

DDRREG_PGOOD

PP5V_S3_DDRREG

S3

S5

P1V8FB_PGOOD

PP5V_S3

(PAGE 65)

EN2

3.3V

VOUT2

PP3V3_S5

P5VS0_EN

Q7860

P1V5DDR_EN

PP5V_S0_FET

(PAGE 66)

DDRREG_EN

8A FUSE

PBUS SUPPLY/

VOUT

VIN

XP2-5

SYNC_DATE=06/30/2009

SYNC_MASTER=K17_REF

Power Block Diagram

3 OF 132

<SCH_NUM>

3 OF 101

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

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REVISION

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SIZE

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PAGE TITLE

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A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROTO:

Revision History

SYNC_MASTER=MASTER

SYNC_DATE=MASTER

4 OF 132

<SCH_NUM>

4 OF 101

TABLE_BOMGROUP_ITEM

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

BOM OPTIONS

BOM NAME

BOM NUMBER

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM GROUP

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM GROUP

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_ALT_ITEM

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

TABLE_ALT_ITEM

TABLE_BOMGROUP_ITEM

PART NUMBER

ALTERNATE FOR

PART NUMBER

BOM OPTION

REF DES

COMMENTS:

TABLE_ALT_HEAD

TABLE_ALT_ITEM

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

TABLE_BOMGROUP_ITEM

BOM Variants

K18 BOM GROUPS

Development BOM

Module Parts

Alternate Parts

Bar Code Labels / EEE #’s

K18_COMMON1

BATT_3S,BCM5764M,GL137,CPUPOC_IMAX_40_50,CPUMEM_S0,SMC_EXCARD_NOT,SMC_DEBUG_YES,HUB1_2NONREM,HUB2_3NONREM

639-0953

K18_COMMON,CPU_2_4GHZ,FB_256_HYNIX,K18_PVT,EEEE_DCJ8

PCBA,2.0G,512HYN_VRAM,K18

639-0954

K18_COMMON,CPU_2_53GHZ,FB_512_SAMSUNG,K18_PVT,EEEE_DCJ9

PCBA,2.13G,512SAM_VRAM,K18

VRAM4,VRAM_512_HYNIX,FB1V35

FB_512_HYNIX

LBL,P/N LABEL,PCB,28MM X 6 MM

EEEE_DCJ8

[EEEE:DCJ8]

CRITICAL

1

826-4393

LBL,P/N LABEL,PCB,28MM X 6 MM

EEEE_DCJ9

[EEEE:DCJ9]

CRITICAL

1

826-4393

CPU_2_66GHZ

ARD,SLBPE,PRQ,2.66G,35W,C2,3M,BGA

337S3848 CRITICAL

U1000

1

ARD,SLBPF,PRQ,2.53G,35W,C2,3M,BGA

337S3847

CPU_2_53GHZ

CRITICAL

1

U1000

6.3V alt to 11V Sanyo

128S0294128S0305

ALL

A02 alt to A03 GPU

337S3839337S3808

ALL

Molex alt to Foxconn

516S0806516S0805

152S1102

ALL

Mag layer alt to Vishay

152S1088

353S2805 353S2603

Fairchild wafer option

ALL

Sanyo alt to Kemet

ALL

128S0264 128S0257

ALL

Panasonic alt to Sanyo

128S0303 128S0282

FB_512_SAMSUNG

VRAM4,VRAM_512_SAMSUNG,FB1V35

ALL

155S0329

MAG LAYERS ALT TO MURATA

155S0457

Samsung I die alt to H

333S0507333S0542

ALL

157S0055

Delta alt to TDK Magnetics

157S0058

ALL

152S0518152S0896

MAG LAYERS ALT TO CYNTEC

138S0602

Murata alt to Samsung

138S0603

ALL

U3900

CRITICAL BCM5764M343S0493

1

IC,ASIC,BCM5764M,ENET CONTROLLER,8x8,64 QFN

IC,SMC,HS8/2117,9MMX9MM,TLP

U4900

338S0563 CRITICAL

SMC_BLANK

1

IR,ENCORE II, CY7C63833-LFXC

U4800

1

CRITICAL341S2384

IC,1MBIT,SPI FLASH,K17/K18

341S2731

U3990

1

CRITICAL

085-1404

K18 MLB DEVELOPMENT

DEVEL_BOM

DEVEL

1

CRITICAL

333S0533

IC,SGRAM,GDDR3,32MX32,1000MHZ,136 FBGA

4

CRITICAL

U8400,U8450,U8500,U8550

VRAM_512_SAMSUNG

IC,PCH,IBEX PEAK-M,SLGZS,PRQ,B3,BGA

337S3849

U1800

CRITICAL

1

IC,EFI ROM,DEVELOPMENT,K18

BOOTROM_PROG

341S2562 CRITICAL

U6100

1

U9600

1

CRITICAL336S0025

GMUX_5K_BLANK

IC,XP2-5,HF,CPLD,BLANK

IC,FLASH,SPI,32MBIT,3.3V,86MHZ,8-SOP

1

CRITICAL

U6100

BOOTROM_BLANK

335S0610

IC,SDRAM,GDDR3,16MX32,900MHZ,136 FBGA

333S0483

VRAM_256_HYNIX

CRITICAL

U8400,U8450,U8500,U8550

4

U5701

1

TPAD_PROG

CRITICAL

IC,PSOC +W/USB,56PIN,MLF,K18

341S2616

IC,SMC,K18

341T0233

1

CRITICAL

U4900

SMC_PROG

341S2566

1

CRITICAL

GMUX_PROG

IC,CPLD,LATTICE,132CSBGA,K18

U9600

IC,GPU,NV GT216 LP++,969BGA,40NM,A03

337S3839

U8000

1

CRITICAL

ARD,SLBNA,PRQ,2.4G,35W,C2,4M,BGA

337S3846

CPU_2_4GHZU1000

CRITICAL

1

[EEEE:DCJD]

EEEE_DCJD

826-4393

1

LBL,P/N LABEL,PCB,28MM X 6 MM

CRITICAL

IC,FW643-E2,1394B PHY/OHCI LINK/PCI-E,12

1

338S0753 CRITICAL

U4100

[EEEE:DCJF]

EEEE_DCJF

826-4393

LBL,P/N LABEL,PCB,28MM X 6 MM

CRITICAL

1

EEEE_DCJC

[EEEE:DCJC]

826-4393

1

CRITICAL

LBL,P/N LABEL,PCB,28MM X 6 MM

333S0535

ALL

Hynix 900M alt to 1000M

333S0506

IC,SDRAM,GDDR3,32MX32,1000MHZ,136 FBGA

333S0535

4

VRAM_512_HYNIX

CRITICAL

U8400,U8450,U8500,U8550

FB_256_HYNIX

VRAM4,VRAM_256_HYNIX,FB1V55

FB_256_SAMSUNG

VRAM4,VRAM_256_SAMSUNG,FB1V55

K18_COMMON2

GMUXPLL_3V3,GPU_SS_INT,MIKEY,GPUVID_0P90V,DPMUX_EN_PLD,DP_CA_DET_EG_PLD,DP_ESD,VFRQ_SLPS3,SMC_OSC_YES,RAIL_MON

K18_COMMON

ALTERNATE,COMMON,K18_COMMON1,K18_COMMON2,K18_PROGPARTS,USBHUB_2061,RDRV:8515A2,DCI

K18_COMMON,CPU_2_66GHZ,FB_512_HYNIX,K18_PVT,EEEE_DCJF

PCBA,2.4G,512HYN_VRAM,K18

639-0957

K18_COMMON,CPU_2_66GHZ,FB_512_SAMSUNG,K18_PVT,EEEE_DCJD

639-0956

PCBA,2.4G,512SAM_VRAM,K18

639-0955

K18_COMMON,CPU_2_53GHZ,FB_512_HYNIX,K18_PVT,EEEE_DCJC

PCBA,2.13G,512HYN_VRAM,K18

VRAM_256_SAMSUNG

333S0507

4

U8400,U8450,U8500,U8550

CRITICAL

IC,SGRAM,GDDR3,16MX32,1000MHZ,136 FBGA

LBL,P/N LABEL,PCB,28MM X 6 MM

EEEE_DCJ7

[EEEE:DCJ7]

CRITICAL826-4393

1

085-1404

K18 DEVELOPMENT BOM

639-0952

K18_COMMON,CPU_2_4GHZ,FB_256_SAMSUNG,K18_PVT,EEEE_DCJ7

PCBA,2.0G,512SAM_VRAM,K18

BOM Configuration

SYNC_DATE=05/28/2009

SYNC_MASTER=K17_REF

K18_PROGPARTS

GMUX_PROG,BOOTROM_PROG,SMC_PROG,TPAD_PROG

K18_PVT

BMON_PROD,VREFMRGN_NOT,XDP,XDP_NORMAL,XDP_CPU_BPM

5 OF 132

<SCH_NUM>

5 OF 101

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

J6780 (MIC CONN)

J6950 (BIL CABLE CONN)

J5800 (IPD FLEX CONN)

J5650 (LEFT FAN CONN)

NC NO_TESTs

FUNC_TEST

POWER RAILS

2 TP needed

FUNC_TEST

ICT Test Points

NC NO_TESTs

NO_TEST

6 TPs

J4500 (SATA ODD CONN)

3 TPs

4 TPs

3 TPs

J6900 (DC POWER CONN)

J6950 (MAIN BATT CONN)

J6995 (BAT LED CONN)

NO_TEST

CPU NO_TESTs

5 TPs

NO_TEST

NC NO_TESTs

J9000 (LVDS CONN)

NO_TEST

J5815 (KBD BACKLIGHT CONN)

J3500 (SD CARD CONN)

per Fan

5 TPs

2 TPs

J4501 (SATA HDD CONN)

J3401 & J3402 (AIRPORT/BT/CAMERA CONN)

FUNC_TEST

USB PORTS

J5713 (KEY BOARD CONN)

FUNC_TEST

J6781 & J6782 (SPEAKERS CONN)

J5660 (RIGHT FAN CONN)

Functional Test Points

per Fan

I1000 I1001 I1002

I1003

I1004

I1005

I1006

I1007

I1008

I1009

I1010 I1011 I1012

I1013

I1014

I1015 I1016 I1017 I1018 I1019 I1020

I1021

I1022

I1024

I1025

I1026

I1027

I1028

I1029

I1031

I1032

I1033

I1034

I1035

I1038 I1039 I1040

I1042 I1043 I1044

I1050

I1051

I1052

I1053

I1054

I1055

I1056

I1057

I1058

I1059

I1060

I1061

I1062

I1063

I1064

I1065

I1066

I1086

I1088

I1089

I1090

I1092 I1093 I1094

I1095 I1096

I1097

I1098

I1099 I1100 I1101

I1102

I1103

I1104 I1105

I1106

I1107

I1108 I1109 I1110 I1111 I1112 I1113 I1114 I1115

I1116

I1117

I1118 I1119 I1120

I1121

I1122

I1123 I1124 I1125

I1126

I1127

I1128 I1129 I1130

I1131 I1132

I1134

I1135

I1136

I1137

I1140

I1141

I1142

I1143

I1145 I1146

I1149

I1150

I1151 I1152

I1156 I1160 I1161

I1273

I1288

I1292

I1297

I1436 I1437

I1438 I1439

I1440

I1441 I1442

I1443

I1444 I1445

I1446

I1447 I1448

I1449

I1450

I1451

I1452

I1453 I1454

I1455

I1464

I557

I558

I559

I600

I602 I603

I604

I605

I606

I607

I610

I611

I612

I613

I614

I615

I616

I617

I618

I620 I621

I623

I624

I625

I626

I627

I636

I637

I638

I639

I640

I709

I714

I720 I722

I723

I724

I725 I726 I727

I728

I729

I730

I731

I732

I733

I734

I735

I737

I738

I739

I740 I741 I742 I743 I744 I751 I752

I756

I760

I761 I762 I763 I764 I765

I766

I767

I768

I769

I770

I771

I772

I774

I989 I990

I991

I992

I993

I994

I995 I996 I997 I998

Functional / ICT Test

SYNC_DATE=MASTER

SYNC_MASTER=MASTER

TRUE

PP5V_S3

TRUE

WS_KBD_ONOFF_L

SYS_LED_ANODE_R

TRUE

TP_GPU_MIOA_DE

TRUE

MAKE_BASE=TRUE

NC_TP_CPU_RSVD_NCTF<8..5>

TRUE MAKE_BASE=TRUE

NC_PCH_LVDS_VBG

MAKE_BASE=TRUE

TRUE

NC_CRT_IG_HSYNC

TRUE

NC_CRT_IG_RED

MAKE_BASE=TRUE

NC_CRT_IG_DDC_DATA

TRUE MAKE_BASE=TRUE

NC_HDA_SDIN1

TRUE MAKE_BASE=TRUE

NC_HDA_SDIN2

TP_PCI_AD<31..0>

TRUE

NC_PCI_C_BE_L<3..0>

MAKE_BASE=TRUE

NC_PCIE_CLK100M_PEBP

NC_PCIE_CLK100M_PEBN

TRUE MAKE_BASE=TRUE

NC_PCIE_CLK100M_PEBP

MAKE_BASE=TRUE

TRUE

NC_PCIE_CLK100M_PEBN

TRUE MAKE_BASE=TRUE

NC_PCIE_CLK100M_PE4N NC_PCIE_CLK100M_PE4P

MAKE_BASE=TRUE

TRUE

NC_PCIE_CLK100M_PE4N NC_PCIE_CLK100M_PE4P

NC_NV_RB_L

MAKE_BASE=TRUE

TRUE

NC_NV_RB_L TP_NV_WR_RE_L<1..0>

NC_PCIE_PE5_R2D_CP

TRUE

MAKE_BASE=TRUE

NC_CLINK_DATA NC_CLINK_RESET_L

NC_CLINK_CLK

NC_CLINK_RESET_L

MAKE_BASE=TRUE

TRUE

NC_CLINK_DATA

TRUE

MAKE_BASE=TRUE

NC_CLINK_CLK

TRUE

MAKE_BASE=TRUE

NC_SATA_D_D2RN

TRUE

NC_SATA_D_D2RP NC_SATA_D_R2D_CN

NC_SATA_SSD2_R2D_CN NC_SATA_SSD2_R2D_CP

NC_PCI_CLK33M_OUT3

MAKE_BASE=TRUE

TRUE

NC_PCH_NV_RCOMP

MAKE_BASE=TRUE

TRUE

NC_NV_DQ<15..0>

TRUE MAKE_BASE=TRUE

SMC_TRST_L

TRUE

NC_PCI_RESET_L

NC_PCI_CLK33M_OUT3

TP_NV_DQ<15..0>

NC_PCH_NV_RCOMP

TP_CPU_RSVD<2..1>

SPI_ALT_CLK

TRUE

NC_PCI_GNT1_L

WS_KBD12

TRUE

WS_KBD11

TRUE

WS_KBD10

NC_TP_CPU_RSVD<2..1>

MAKE_BASE=TRUE

TRUE

SMC_TMS

TRUE

SMC_TDO

TRUE

SMC_TDI

TRUE

SMC_TCK

SMC_RX_L

TRUE

WS_KBD7

TRUE

WS_KBD8

TRUE

LPC_PWRDWN_L

LPC_FRAME_L

TRUE

WS_KBD9

TRUE

PP1V5_S3

PP3V3_S3

TRUE

PP3V3_S3

TRUE

AP_RESET_CONN_L

FAN_LT_PWM

TRUE

SD_CD_L

TRUE

PP5V_S3_IR_R

TRUE

PCIE_WAKE_L

TRUE

AP_CLKREQ_Q_L

TRUE

PCIE_CLK100M_AP_CONN_P

TRUE

WS_KBD16_NUM

WS_KBD21

TRUE TRUE

WS_KBD22

TRUE

WS_KBD23

TRUE

WS_KBD2

TRUE

WS_KBD4

SMC_RESET_L

TRUE

SPI_ALT_CS_L

TRUE

WS_KBD15_CAP

TRUE

WS_KBD6

TRUE

WS_KBD13

TRUE

USB2_LT1_N USB2_LT1_P

TRUE

SPI_ALT_MOSI

TRUE

BKLT_EN

TRUE

WS_KBD1

TRUE

PP3V42_G3H

TRUE

USB_LT2_P

WS_KBD18

TRUE

BI_MIC_N

TRUE

BI_MIC_SHIELD

TRUE

PCIE_CLK100M_AP_CONN_N

TRUE

SD_D<7..0>

PCIE_AP_D2R_P

TRUE

PCIE_AP_D2R_N

TRUE

PCIE_AP_R2D_P

TRUE

Z2_DEBUG3

TRUE

PP1V2_ENET

TRUE

PPVTTDDR_S3

TRUE

PPVP_FW

TRUE

PPVCORE_GPU

TRUE

PPDCIN_G3H

TRUE

PP3V42_G3H

TRUE

PP3V3_S5_AVREF_SMC

TRUE

PP3V3_S5

TRUE

PP3V3_S0GPU

TRUE

PP1V8_S0

TRUE

PP1V8_GPUIFPX

TRUE

PP1V8R1V55_S0GPU_ISNS_R

TRUE

PP1V8R1V55_S0GPU_ISNS

TRUE

PP1V5_S3RS0

TRUE

PP1V0_FW_FWPHY

PP1V05_S0GPU

TRUE

PP1V05_S0

TRUE

PP18V5_S3

TP_PCI_C_BE_L<3..0>

TRUE

SMC_LID_R

SATA_HDD_D2R_C_P

TRUE

SATA_HDD_R2D_P

TRUE

NC_PCIE_PE5_D2RP

TRUE

MAKE_BASE=TRUE

NC_PCIE_PE5_R2D_CN

TRUE

MAKE_BASE=TRUE

TRUE

NC_PCIE_PE6_R2D_CP

MAKE_BASE=TRUE

TRUE

NC_PCIE_PE6_R2D_CN

MAKE_BASE=TRUE

TRUE

NC_PCIE_PE7_D2RN

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

NC_PCIE_PE7_D2RP

TRUE

NC_PCIE_PE6_D2RN

MAKE_BASE=TRUE

TRUE

NC_PCIE_PE7_R2D_CP

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

NC_PCIE_PE8_R2D_CN

TRUE

MAKE_BASE=TRUE

NC_PCIE_PE8_D2RP

TRUE

NC_PCIE_PE8_D2RN

MAKE_BASE=TRUE

NC_PCIE_PE5_R2D_CP

NC_PCIE_PE5_D2RN

NC_PCIE_PE5_R2D_CN

NC_PCIE_PE6_R2D_CP

NC_PCIE_PE6_R2D_CN

NC_PCIE_PE6_D2RP

NC_PCIE_PE7_D2RN NC_PCIE_PE7_D2RP

NC_PCIE_PE6_D2RN

NC_PCIE_PE7_R2D_CP

NC_PCIE_PE7_R2D_CN

NC_PCIE_PE8_R2D_CP

NC_PCIE_PE8_R2D_CN

NC_PCIE_PE8_D2RP

NC_PCIE_PE8_D2RN

PP5V_S3_RTUSB_B_F

TRUE

PP5V_S0_HDD_FLT

TRUE

NC_CRT_IG_DDC_CLK

NC_PCH_LVDS_VBG

TRUE MAKE_BASE=TRUE

NC_CRT_IG_BLUE

Z2_BOOST_EN

TRUE

SATA_ODD_R2D_P

TRUE

LVDS_CONN_A_DATA_P<0>

TRUE

PP3V3_S0

TP_CPU_RSVD_NCTF<8..5>

NC_CRT_IG_BLUE

NC_CRT_IG_RED

NC_CRT_IG_DDC_DATA

NC_CRT_IG_GREEN

NC_CRT_IG_HSYNC NC_CRT_IG_VSYNC

NC_LVDS_IG_CTRL_DATA

TRUE

NC_CRT_IG_VSYNC

MAKE_BASE=TRUE

TRUE

WS_KBD5

SATA_ODD_R2D_N

TRUE

SATA_HDD_R2D_N

TRUE

LED_RETURN_3

TRUE

LVDS_DDC_CLK

TRUE

TRUE MAKE_BASE=TRUE

NC_TP_CPU_RSVD<27..26>

TRUE MAKE_BASE=TRUE

NC_TP_CPU_RSVD<58..45>

TRUE

WS_KBD14

TRUE

USB_LT2_N

TRUE

PP18V5_S3

LPC_AD<0..3>

TRUE

TP_ISSP_SDATA_P1_0

TRUE

SATA_HDD_D2R_C_N

TRUE

SMBUS_SMC_BSA_SDA

TRUE

PP18V5_DCIN_FUSE

TRUE

ADAPTER_SENSE

TRUE

PPVBAT_G3H_CONN

TRUE

SMBUS_SMC_A_S3_SDA

TRUE

PP5V_SW_ODD

TRUE

SMBUS_SMC_A_S3_SCL

TRUE

PSOC_F_CS_L

TRUE

Z2_MISO

TRUE

WS_KBD20

TRUE

TP_ISSP_SCLK_P1_1

TRUE

LPCPLUS_GPIO

TRUE

LED_RETURN_5

TRUE

WS_KBD3

TRUE

LVDS_DDC_DATA

TRUE

LVDS_CONN_A_DATA_N<1>

TRUE

LVDS_CONN_A_DATA_P<2>

TRUE

LVDS_CONN_B_DATA_P<0>

TRUE

LVDS_CONN_B_DATA_P<2>

TRUE

LVDS_CONN_B_CLK_F_P

TRUE

LVDS_CONN_B_CLK_F_N LED_RETURN_1

TRUE

LED_RETURN_2

TRUE

LED_RETURN_4

TRUE

LED_RETURN_6

TRUE

SMC_ODD_DETECT SATA_ODD_D2R_C_P

TRUE

SATA_ODD_D2R_C_N

TRUE

WS_KBD19

TRUE

IR_RX_OUT

WS_LEFT_SHIFT_KBD

TRUE

WS_CONTROL_KBD

LCD_BKLT_PWM

TRUE

TP_CPU_RSVD<24..15>

TP_CPU_RSVD<27..26>

TP_CPU_RSVD<43..32>

TP_CPU_RSVD<58..45>

TP_CPU_RSVD<65..62>

WS_LEFT_OPTION_KBD

TRUE

LVDS_CONN_B_DATA_N<2>

TRUE

PP3V3_SW_LCD

TRUE

SMBUS_SMC_BSA_SDA

TRUE

SPI_ALT_MISO

TRUE

PM_SYSRST_L

TRUE

PM_CLKRUN_L

TRUE

LPC_SERIRQ

LPC_CLK33M_LPCPLUS

TRUE

LPCPLUS_RESET_L

TRUE

NC_SMC_BS_ALRT_L

TRUE

WS_KBD17

SMC_TX_L

TRUE

SPIROM_USE_MLB

TRUE

NC_LVDS_IG_CTRL_CLK

TRUE

PPVOUT_S0_LCDBKLT

KBDLED_ANODE

TRUE TRUE

SMC_KDBLED_PRESENT_L

SMC_BIL_BUTTON_L

TRUE

FAN_LT_TACH

TRUE

NC_SMC_FAN_2_TACH

TRUE

NC_SMC_FAN_2_CTL

TRUE

NC_FW2_TPBN

NC_FW2_TPBP

TRUE

NC_FW2_TPBIAS

TRUE

NC_FW2_TPAP

TRUE TRUE

NC_FW2_TPAN

TRUE

NC_FW0_TPBN

NC_FW0_TPBP

TRUE

NC_FW0_TPAP NC_ESTARLDO_EN

TRUE

NC_ALS_GAIN

TRUE

NC_FW643_AVREG

MAKE_BASE=TRUE

NC_FW643_TDI

TRUE

MAKE_BASE=TRUE

NC_DP_IG_C_HPD

TRUE MAKE_BASE=TRUE

NC_DP_IG_C_CTRL_DATA

TRUE MAKE_BASE=TRUE

NC_DP_IG_C_CTRL_CLK

MAKE_BASE=TRUE

TRUE

NC_DP_IG_C_CTRL_CLK

NC_DP_IG_C_MLP<3..0>

MAKE_BASE=TRUE

TRUE

NC_DP_IG_C_MLN<3..0>

TRUE MAKE_BASE=TRUE

NC_DP_IG_C_AUXP

TRUE MAKE_BASE=TRUE

NC_DP_IG_C_AUXN

TRUE MAKE_BASE=TRUE

NC_DP_IG_C_AUXN

NC_DP_IG_D_HPD

TRUE MAKE_BASE=TRUE

NC_DP_IG_D_HPD

NC_DP_IG_D_CTRL_DATA

TRUE MAKE_BASE=TRUE

NC_DP_IG_D_CTRL_DATA

NC_DP_IG_D_CTRL_CLK

TRUE MAKE_BASE=TRUE

NC_DP_IG_D_CTRL_CLK

TRUE MAKE_BASE=TRUE

NC_DP_IG_D_MLP<3..0>TP_DP_IG_D_MLP<3..0>

TRUE MAKE_BASE=TRUE

NC_DP_IG_D_MLN<3..0>TP_DP_IG_D_MLN<3..0>

MAKE_BASE=TRUE

TRUE

NC_DP_IG_D_AUXPNC_DP_IG_D_AUXP

TRUE MAKE_BASE=TRUE

NC_SDVO_TVCLKINNNC_SDVO_TVCLKINN

MAKE_BASE=TRUE

TRUE

NC_DP_IG_D_AUXN

TRUE MAKE_BASE=TRUE

NC_SDVO_STALLN

MAKE_BASE=TRUE

TRUE

NC_SDVO_TVCLKINPNC_SDVO_TVCLKINP

TRUE MAKE_BASE=TRUE

NC_SDVO_INTNNC_SDVO_INTN

MAKE_BASE=TRUE

TRUE

NC_SDVO_STALLPNC_SDVO_STALLP

MAKE_BASE=TRUE

TRUE

NC_SDVO_INTPNC_SDVO_INTP

MAKE_BASE=TRUE

TRUE

NC_GPU_BUFRST_L

MAKE_BASE=TRUE

TRUE

NC_GPU_GSTATE<1>

MAKE_BASE=TRUE

TRUE

NC_GPU_GSTATE<0>

MAKE_BASE=TRUE

TRUE

NC_GPU_MIOA_D<9..0>TP_GPU_MIOA_D<9..0>

TRUE

NC_GPU_MIOA_DE

MAKE_BASE=TRUE

NC_LVDS_EG_BKL_PWM

TRUE MAKE_BASE=TRUE

NC_LVDS_IG_B_CLKP

TRUE

MAKE_BASE=TRUE

TP_LVDS_IG_B_CLKP

NC_LVDS_IG_B_CLKN

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

NC_PCH_SSTNC_PCH_SST

TRUE

MAKE_BASE=TRUE

NC_SMC_BS_ALRT_LNC_SMC_BS_ALRT_L

NC_LVDS_IG_BKL_PWM

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

NC_PCH_NC1

TRUE

MAKE_BASE=TRUE

NC_PCH_NC5

MAKE_BASE=TRUE

TRUE

NC_PCH_TP19

TRUE

MAKE_BASE=TRUE

NC_PCH_NC3

TRUE

MAKE_BASE=TRUE

NC_PCH_NC2

TRUE

MAKE_BASE=TRUE

NC_PCH_NC4

MAKE_BASE=TRUE

TRUE

NC_PCH_TP14

MAKE_BASE=TRUE

TRUE

NC_PCH_TP15

MAKE_BASE=TRUE

TRUE

NC_PCH_TP16

MAKE_BASE=TRUE

TRUE

NC_PCH_TP17

MAKE_BASE=TRUE

TRUE

NC_PCH_TP18

MAKE_BASE=TRUE

TRUE

NC_PCH_TP10

MAKE_BASE=TRUE

TRUE

NC_PCH_TP9

MAKE_BASE=TRUE

TRUE

NC_PCH_TP12

MAKE_BASE=TRUE

TRUE

NC_PCH_TP11

MAKE_BASE=TRUE

TRUE

NC_PCH_TP13

MAKE_BASE=TRUE

TRUE

NC_PCH_TP8

TP_SMC_P41

NC_HDA_SDIN1 NC_HDA_SDIN2 NC_HDA_SDIN3

MAKE_BASE=TRUE

TRUE

NC_PCI_GNT3_LNC_PCI_GNT3_L

NC_PCI_GNT2_L

MAKE_BASE=TRUE

TRUE

NC_PCI_GNT0_LNC_PCI_GNT0_L

TRUE MAKE_BASE=TRUE

NC_PCI_GNT1_L

NC_PCI_PAR

MAKE_BASE=TRUE

TRUE

NC_PCI_PAR

NC_PCI_PME_L

MAKE_BASE=TRUE

TRUE

NC_PCI_PME_L

TRUE MAKE_BASE=TRUE

NC_PCI_RESET_L

TP_NV_DQS<1..0> TP_NV_CE_L<3..0>

TRUE

NC_NV_ALE

MAKE_BASE=TRUE

NC_NV_ALE

NC_NV_CLE

TRUE MAKE_BASE=TRUE

NC_NV_CLE

TRUE

NC_NV_WE_CK_L<1..0>

MAKE_BASE=TRUE

TP_NV_WE_CK_L<1..0>

TRUE

NC_NV_WR_RE_L<1..0>

MAKE_BASE=TRUE

NC_PCIE_CLK100M_PE5N

TRUE

NC_PCIE_CLK100M_PE6P

MAKE_BASE=TRUE

NC_PCIE_CLK100M_PE6P

NC_PCIE_CLK100M_PE6N

NC_PCIE_CLK100M_PE5P

TRUE

NC_PCIE_CLK100M_PE7N

MAKE_BASE=TRUE

NC_PCIE_CLK100M_PE7N NC_PCIE_CLK100M_PE7P

NC_SATA_C_D2RP

NC_PSOC_P1_3

NC_SATA_C_R2D_CP

NC_SATA_C_R2D_CN

NC_SATA_D_D2RN

TRUE

NC_SATA_SSD2_R2D_CP

MAKE_BASE=TRUE

NC_SATA_SSD2_R2D_CN

TRUE

MAKE_BASE=TRUE

TRUE

NC_SATA_SSD2_D2RPNC_SATA_SSD2_D2RP

NC_PCH_TP1

TRUE

MAKE_BASE=TRUE

NC_PCH_TP2

MAKE_BASE=TRUE

TRUE

NC_PCH_TP3

TRUE

MAKE_BASE=TRUE

NC_PCH_TP6

TRUE

MAKE_BASE=TRUE

NC_PCH_TP7

TRUE

MAKE_BASE=TRUE

NC_PCH_TP5

TRUE

MAKE_BASE=TRUE

NC_PCH_TP4

TRUE

MAKE_BASE=TRUE

NC_PCH_TP10

TRUE

MAKE_BASE=TRUE

NC_SMC_P41

MAKE_BASE=TRUE

TRUE

NC_PCI_GNT2_L

TRUE

NC_PCI_AD<31..0>

MAKE_BASE=TRUE

TRUE MAKE_BASE=TRUE

NC_HDA_SDIN3

TRUE MAKE_BASE=TRUE

NC_LVDS_IG_CTRL_DATA

TRUE

NC_LVDS_IG_CTRL_CLK

MAKE_BASE=TRUE

NC_CRT_IG_DDC_CLK

TRUE

NC_CRT_IG_GREEN

TRUE MAKE_BASE=TRUE

MAKE_BASE=TRUE

TRUE

NC_TP_CPU_RSVD<24..15>

NC_TP_CPU_RSVD<43..32>

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

NC_TP_CPU_RSVD<65..62>

TRUE MAKE_BASE=TRUE

NC_PCIE_CLK100M_PE7P

NC_DP_IG_D_AUXN

NC_SDVO_STALLN

NC_PCH_NC1 NC_PCH_NC2

NC_PCH_TP17

NC_PCH_TP14

NC_PCH_TP12

NC_PCH_TP7

NC_PCH_TP2

NC_PCH_TP9

NC_PCH_TP15

NC_FW643_AVREG

TP_GPU_GSTATE<0>

TP_LVDS_IG_B_CLKN

TRUE MAKE_BASE=TRUE

NC_NV_CE_L<3..0>

MAKE_BASE=TRUE

TRUE

NC_NV_DQS<1..0>

NC_PCH_NC3 NC_PCH_NC4 NC_PCH_NC5 NC_PCH_TP19 NC_PCH_TP18

NC_PCH_TP16

NC_PCH_TP13

NC_PCH_TP11

NC_PCH_TP8

NC_PCH_TP3

TP_LVDS_IG_BKL_PWM

NC_LVDS_EG_BKL_PWM

TP_GPU_GSTATE<1>

NC_GPU_BUFRST_L

NC_FW643_TDI

NC_DP_IG_C_CTRL_DATA

NC_DP_IG_C_AUXP

TP_DP_IG_C_MLN<3..0>

TP_DP_IG_C_MLP<3..0>

NC_DP_IG_C_HPD

NC_SMC_FAN_3_CTL

TRUE

NC_SMC_FAN_3_TACH

TRUE

MAKE_BASE=TRUE

NC_SATA_D_R2D_CP

TRUE

NC_SATA_D_D2RP

MAKE_BASE=TRUE

TRUE

PCH_VSS_NCTF<1>

TRUE

PCH_VSS_NCTF<2>

TRUE

PCH_VSS_NCTF<5>

TRUE

PCH_VSS_NCTF<7> PCH_VSS_NCTF<9>

TRUE

PCH_VSS_NCTF<11>

TRUE

PCH_VSS_NCTF<12>

TRUE

PCH_VSS_NCTF<15>

TRUE

PCH_VSS_NCTF<17>

TRUE

PCH_VSS_NCTF<19>

TRUE

PCH_VSS_NCTF<19>

TRUE

PCH_VSS_NCTF<21>

TRUE

PCH_VSS_NCTF<25>

TRUE

PCH_VSS_NCTF<27>

TRUE

PCH_VSS_NCTF<29>

NC_PCH_TP1

NC_PCH_TP4

NC_PCH_TP5

NC_PCH_TP6

TRUE

NC_PCIE_CLK100M_PE5N

MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE

NC_PCIE_CLK100M_PE5P NC_PCIE_CLK100M_PE6N

MAKE_BASE=TRUE

TRUE

NC_PSOC_P1_3

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

NC_SATA_C_D2RN

MAKE_BASE=TRUE

TRUE

NC_SATA_C_D2RP

TRUE

NC_SATA_C_R2D_CN

MAKE_BASE=TRUE

TRUE

NC_SATA_C_R2D_CP

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

NC_SATA_D_R2D_CN

NC_SATA_SSD2_D2RN

MAKE_BASE=TRUE

TRUE

NC_SATA_SSD2_D2RN

NC_SATA_D_R2D_CP

TRUE

Z2_RESET

TRUE

LVDS_CONN_A_DATA_P<1>

TRUE

LVDS_CONN_A_DATA_N<0>

TRUE

SMBUS_SMC_A_S3_SDA

TRUE

SMBUS_SMC_A_S3_SCL

TRUE

USB_CAMERA_CONN_P

TRUE

USB_CAMERA_CONN_N

TRUE

CONN_USB2_BT_P CONN_USB2_BT_N

TRUE

PP5V_S3_RTUSB_A_F

TRUE

PP3V3_WLAN

TRUE

SYS_LED_ANODE

TRUE

PPBUS_G3H

TRUE

Z2_CS_L

TRUE

PP3V3_FW_FWPHY

TRUE

PPVCORE_S0_GFX

TRUE

PPVCORE_S0_CPU

TRUE

PP3V3_S0

TRUE

PP3V3_ENET

TRUE

PP1V2_S0

PM_SLP_S3_L

TRUE

PP1V05_S5

MAKE_BASE=TRUE

NC_PCIE_PE5_D2RN

TRUE

SMBUS_SMC_BSA_SCL

TRUE

SMBUS_SMC_BSA_SCL

TRUE

PP3V42_G3H

TRUE

PSOC_SCLK

LVDS_CONN_B_DATA_N<1>

TRUE

LVDS_CONN_B_DATA_P<1>

TRUE

LVDS_CONN_B_DATA_N<0>

TRUE

LVDS_CONN_A_CLK_F_N

TRUE

LVDS_CONN_A_CLK_F_P

TRUE

LVDS_CONN_A_DATA_N<2>

TRUE

NC_PCIE_PE5_D2RP

TRUE

NC_PCIE_PE7_R2D_CN

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

NC_PCIE_PE8_R2D_CP

TRUE

NC_PCIE_PE6_D2RP

MAKE_BASE=TRUE

TRUE

PP5V_S5

TRUE

BI_MIC_P

TRUE

FAN_RT_TACH

TRUE

FAN_RT_PWM

TRUE

SPKRCONN_S_OUT_N

SPKRCONN_L_OUT_N

TRUE

SPKRCONN_S_OUT_P

TRUE

SPKRCONN_R_OUT_P

TRUE

SPKRCONN_L_OUT_P

SPKRCONN_R_OUT_N

TRUE

SMC_MD1

TRUE TRUE

SMC_NMI

SMC_ONOFF_L

TRUE

PP0V75_S0_DDRVTT

TRUE

PCIE_AP_R2D_N

TRUE

PP5V_S0

TRUE

NC_SATA_C_D2RN

PP5V_S3_ALSCAMERA_F

TRUE

SD_CMD

TRUE

SD_CLK

TRUE

SD_WP

Z2_CLKIN

TRUE

Z2_SCLK

TRUE

Z2_KEY_ACT_L

TRUE

PICKB_L

TRUE

PSOC_MISO PSOC_MOSI

TRUE

GND

TRUE

GND

TRUE

GND

TRUE

GND

TRUE

GND

TRUE

GND

TRUE

GND

TRUE

GND

TRUE

GND

TRUE

GND

TRUE

7 OF 132

<SCH_NUM>

6 OF 101

7

31 33 42 43 44 46 54 56 58 61 66 67 72

82

101

53

42

79 80

9

6

18

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19

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6

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19

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6

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17

6

17

6

17

6

17

6

17

6

17

6

17

6

17

6

17

6

17

6

19

6

19

45 47

6

19

6

19

6

19

9

47

6

19

53

45 46 47

43 45 46 47

53

53 18 45 47

17 45 47 87 94

53

7

28 30 31 67 72

6 7 8

17 20 31 32 33 34 35 36 48 50 53 54

55 72 73 87

101

6 7 8

17 20

31 32 33 34

35 36 48 50

53 54 55 72

73 87

101

33

52

34 37

42

18 27 33

33

33 99

53

45 46 47 65

47

53

43 99

47

88

53

6 7

17 21 23 43 45 46 47 48 49 53 64 65 66 73

43 99

53

62 63

33 99

34

17 33 94

33 94

53 54

7

37 71 72

7

32 67

7

40 41

7

49 75 82

7

64 65

6 7

17 21 23 43 45 46 47 48 49

53 64 65 66 73

45 46

7

17 18 19 20 21 23 27 31 35 57

66 71 72 73 83 85 99

7

72 74 79 80 81 82 84

7

12 16 21 23 24 58 71 72 87

7

72 81

7

50 86

7 8

50 56 75 76 77 78

7

13 16 31 42 72 73 99

7

39 40

7

74 76 79 81 86

7

10 12 13 15 17 18 20 21 23 24

25 26 40 70 73 86

6

54

64

42 93

6

17

6

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6

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6

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43

42

6

18

6

18

6

18

54

42 93

83 84 98

6 7

17 18 19 20 21 23 24 25 26

27 28 30 34 37 40 42 46 47 48

50 51 52 54 58 62 63 68 69 72

73 80 83

84 85 87 88 99

6

18

6

18

6

18

6

18

6

18

6

18

6

18

6

18

53

42 93

83 88

83 84

53

43 99

6

54

17 45 47 87 94

8

53

42 93

6

45 48 64 65 97

64

64 65

6

33 45 48 54 97

42 56

6

33 45 48 54 97

53 54

53

8

53

20 47

83 88

53

83 84

83 84 98

83 98

83 88

42 45

42 93

53

42 44

53

87 88

9

53

83 84 98

83

6

45 48 64 65 97

47

18 27 45

18 45 47

17 45 47

27 47 94

27 47 87 94

6

53

43 45 46 47

20 47 57

6

18

54

45 46 64

52

45 46

39 41

39 41 96

45 46

6

39

6

39

6

18

6

18

6

18

6

18

6

18

6

18

6

18

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18

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79 80

6

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18 93

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53

6

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6

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39

79 80

8

18 93

19

6

20

6

20

6

20

6

20

6

20

6

20

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20

6

20

6

20

6

20

8

18

6

80

6

74

6

39

6

18

6

18

6

18

45 46

6

17

6

17

20 94

6

20 94

6

20 94

6

20

6

20

6

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6

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6

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20

6

53

6

17

6

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17

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6

17

6

17

6

17

53 54

83 84 98

6

33 45 48 54 97

6

33 45 48 54 97

33 93

33 99

43

33

42 46

7

40 49 65 66 67 69 70 82 86 89

53 54

7

39 40 41

7

13 24 49 69

7

12 15 49 68

6 7

17 18 19 20 21 23 24 25 26

27 28 30 34 37 40 42 46 47 48

50 51 52 54 58 62 63 68 69 72

73 80

83 84 85 87 88 99

7

27 37 73

7

72 87

18 31 45 73 85

7

17 71

6

17

6

45 48 64 65 97

6

45 48 64

65 97

6 7

17 21 23 43

45 46 47

48 49 53

64 65 66

73

53 54

83 84 98

83 98

83 84 98

6

17

6

17

6

17

6

17

7

23 66 72

62 63

52

61 62 99

45 47

45 46 53

7

28 30 31 67

33 94

6 7

23 42 47 52 54 68 69 70 72

86 88

6 7

23 42 47

52 54 68 69

70 72 86 88

6

17

33

34

34 37

53 54

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

"G3Hot" (Always-Present) Rails

1.8V/1.5V/1.2V/1.05V Rails

3.3V Rails

Chipset "VCore" Rails

2A max supply

? mA

"GPU" Rails

"FW" (FireWire) Rails

ENET Rails

5V Rails

Power Aliases

SYNC_DATE=MASTER

SYNC_MASTER=MASTER

PP3V3_S5

MAKE_BASE=TRUE

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.6 MM

PP3V3_S5

MIN_NECK_WIDTH=0.2 MM

PP3V3_S5

PP3V3_S3

MIN_LINE_WIDTH=0.50MM MIN_NECK_WIDTH=0.20MM

MAKE_BASE=TRUE

VOLTAGE=3.3V

PP3V3_S3

PP3V3_S3 PP3V3_S3

PP3V3_S3

PP3V3_S5

PP3V3_S5 PP3V3_S5

PP3V3_S5

MIN_NECK_WIDTH=0.2 MM MAKE_BASE=TRUE

PP1V5_S3RS0

MIN_LINE_WIDTH=0.6 MM VOLTAGE=1.5V

MAKE_BASE=TRUE

VOLTAGE=18.5V

PPDCIN_G3H

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.25 MM

PP1V2_ENET

MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.2V MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 MM

PP1V05_S0

MAKE_BASE=TRUE

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM

PP1V05_S0

PP5V_S5

PP3V42_G3H

PP5V_S5

PP5V_S3

MIN_LINE_WIDTH=0.5 mm VOLTAGE=5V

MAKE_BASE=TRUE

PP5V_S3

MIN_NECK_WIDTH=0.2 mm

PPBUS_G3H

PP3V3_S3

PP1V8_S0

VOLTAGE=1.8V MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM

PP3V3_ENET

MIN_LINE_WIDTH=0.6 MM

MAKE_BASE=TRUE

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2 MM

MAKE_BASE=TRUE

VOLTAGE=1.0V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM

PP1V0_FW_FWPHY

PPVP_FW

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=12.8V

PP3V3_S0GPU

VOLTAGE=3.3V MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.3 MM MIN_NECK_WIDTH=0.10MM

VOLTAGE=1.8V MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.15 MM

PP1V8_GPUIFPX

VOLTAGE=1.8V MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM

PP1V8R1V55_S0GPU_ISNS

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.8V

PP1V8R1V55_S0GPU_ISNS_R

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM

MAKE_BASE=TRUE

PP1V05_S0GPU

VOLTAGE=1.05V

PPVCORE_S0_GFX

VOLTAGE=1.05V MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM

VOLTAGE=1.25V MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.25 MM

MIN_LINE_WIDTH=0.6 MM

PPVCORE_S0_CPU_VCAP0

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.25 MM

MAKE_BASE=TRUE

VOLTAGE=1.25V

PPVCORE_S0_CPU_VCAP1

PPVCORE_S0_CPU_VCAP2

VOLTAGE=1.25V MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.25 MM

PPVTTDDR_S3

VOLTAGE=0.75V MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.3 MM MIN_NECK_WIDTH=0.2 MM

VOLTAGE=1.25V MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.25 MM

MIN_LINE_WIDTH=0.6 MM

PPVCORE_S0_CPU

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM

MAKE_BASE=TRUE

PPVCORE_GPU

VOLTAGE=1.0V

MIN_LINE_WIDTH=0.6 MM VOLTAGE=1.2V

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.09 MM

PP1V2_S0

PP3V3_FW_FWPHY

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.3V MAKE_BASE=TRUE

PP0V75_S0_DDRVTT

VOLTAGE=0.75V

MIN_NECK_WIDTH=0.17 mm MAKE_BASE=TRUE

MIN_LINE_WIDTH=2 mm

PP5V_S5

PP3V42_G3H

PPBUS_G3H

PPDCIN_G3H

PP3V42_G3H

PP3V3_ENET

PPBUS_G3H

PP3V3_S0

PP3V3_S5

PP1V8_S0 PP1V8_S0 PP1V8_S0

PP1V8_S0

PP1V5_S3RS0

PP3V42_G3H

PPBUS_G3H

PP1V2_ENET

PPVP_FW

PPVP_FW PPVP_FW

PP3V3_FW_FWPHY PP3V3_FW_FWPHY

PP1V0_FW_FWPHY

PP3V3_S0GPU PP3V3_S0GPU PP3V3_S0GPU PP3V3_S0GPU PP3V3_S0GPU

PP3V3_S0GPU

PP1V8_GPUIFPX

PP1V8R1V55_S0GPU_ISNS PP1V8R1V55_S0GPU_ISNS PP1V8R1V55_S0GPU_ISNS

PP1V8R1V55_S0GPU_ISNS

PP1V8R1V55_S0GPU_ISNS_R

PP1V05_S0GPU PP1V05_S0GPU PP1V05_S0GPU PP1V05_S0GPU

PP1V05_S0GPU

PPVCORE_GPU

PPVCORE_S0_CPU

PPVCORE_S0_GFX

PPVCORE_S0_CPU

PPVCORE_S0_CPU_VCAP0

PPVCORE_S0_CPU_VCAP1

PPVCORE_S0_CPU_VCAP2

PP1V5_S3RS0

PP1V2_S0

PP1V05_S0

PP1V2_ENET

PP1V05_S0GPU

PP1V05_S0GPU PP1V05_S0GPU

PP1V05_S0GPU

PP1V2_S0

PP3V3_FW_FWPHY

PP3V3_ENET

PP1V5_S3

PP0V75_S0_DDRVTT

PP5V_S0

PPVTTDDR_S3

PP0V75_S0_DDRVTT

PP1V05_S0

PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0

PPBUS_CPU_IMVP_ISNS

PP5V_S3

PP3V3_S5

PP1V8_S0

PP5V_S0

PP5V_S3

PP3V3_S0

PP5V_S5

PP5V_S3

PP5V_S3 PP5V_S3 PP5V_S3

VOLTAGE=5V

PP5V_S0

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

PP5V_S0

PP3V42_G3H

PP3V3_S0

PP3V42_G3H

PP5V_S3

MAKE_BASE=TRUE

VOLTAGE=5V

PP5V_S5

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.5 MM

PPBUS_G3H

PP3V42_G3H

PP1V05_S0

PP3V3_S3

PP3V3_S5

PP3V3_S3

PP1V05_S5

PP0V75_S0_DDRVTT

PP1V05_S0

PP3V42_G3H

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM

PP1V05_S5

MAKE_BASE=TRUE

PP1V05_S5

PP3V3_S0

PP3V42_G3H

MIN_LINE_WIDTH=0.3 MM VOLTAGE=3.42V

MAKE_BASE=TRUE

PP3V42_G3H

MIN_NECK_WIDTH=0.2 MM

PPDCIN_G3H

PPBUS_CPU_IMVP_ISNS

VOLTAGE=12.8V

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.4 mm

PPBUS_CPU_IMVP_ISNS

PP3V3_S3

PP3V3_S5

PPBUS_G3H

PP3V3_S0

PP3V3_S3

PP1V5_S3RS0

PP3V3_S5

PPBUS_G3H

MAKE_BASE=TRUE

VOLTAGE=1.5V

PP1V5_S3

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.17 mm

PP3V3_S0

PPBUS_G3H

MIN_NECK_WIDTH=0.25 mm

MAKE_BASE=TRUE

VOLTAGE=12.8V

MIN_LINE_WIDTH=0.6 mm

PP3V3_S0 PP3V3_S0

PP3V3_S0

PP3V3_S0 PP3V3_S0 PP3V3_S0

PP3V3_S0

PP3V3_S0 PP3V3_S0

PP3V3_S0

PP3V3_S0 PP3V3_S0

PP3V3_S0

PP3V3_S0 PP3V3_S0

PP3V3_S0 PP3V3_S0 PP3V3_S0

PP3V3_S0

MAKE_BASE=TRUE

PP3V3_S0

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.20MM VOLTAGE=3.3V

PP3V3_S0

8 OF 132

<SCH_NUM>

7 OF 101

6 7

17 18 19 20 21 23 27 31 35

57 66 71 72 73 83 85 99

6 7

17 18 19 20 21 23 27 31 35

57 66 71 72 73 83 85 99

6 7

17 18 19 20 21 23 27 31 35

57 66 71 72 73 83 85 99

6 7

17 18 19 20 21 23 27 31 35

57 66 71 72 73 83 85 99

6 7 8

17 20 31 32 33 34 35 36 48 50 53 54

55 72 73 87

101

6 7 8

17 20 31 32 33 34 35 36 48 50 53 54

55 72 73 87

101

6 7 8

17 20 31 32 33 34 35 36 48 50 53 54

55 72 73 87

101

6 7 8

17 20 31 32 33 34 35 36 48 50 53 54

55 72 73 87

101

6 7 8

17 20 31 32 33 34 35 36 48 50 53 54

55 72 73 87

101

6 7

17 18 19 20

21 23 27 31 35 57 66 71 72 73

83 85 99

6 7

17 18 19 20 21 23

27 31 35 57 66 71 72

73 83 85 99

6 7

17 18 19 20 21 23 27 31 35

57 66 71 72 73 83 85 99

6 7

17 18 19 20 21 23 27 31 35

57 66 71 72 73 83 85 99

6 7

17 18 19 20 21 23 27 31 35

57 66 71 72 73 83 85 99

6 7

13 16 31 42 72 73 99

6 7

64 65

6 7

37 71 72

6 7

37 71 72

6 7

10 12 13 15 17 18 20 21 23

24 25 26 40 70 73 86

6 7

10 12 13 15 17 18 20 21 23

24 25 26 40 70 73 86

6 7

10 12 13 15 17 18 20 21 23

24 25 26 40 70 73 86

6 7

10 12 13 15 17

18 20 21 23 24 25

26 40 70 73 86

6 7

23 66 72

6 7

17 21 23 43 45 46 47 48 49

53 64 65 66 73

6 7

23 66 72

6 7

31 33 42 43 44 46 54 56 58 61 66 67

72 82

101

6 7

31 33 42 43 44 46 54 56 58 61 66 67

72 82

101

6 7

31 33 42 43 44 46 54 56 58 61 66 67

72 82

101

6 7

40 49 65 66 67 69 70 82 86

89

6 7

40 49 65 66 67 69 70 82 86

89

6 7 8

17 20 31 32 33 34 35 36 48 50 53

54 55 72 73 87

101

6 7 8

17 20 31 32 33 34 35 36 48 50 53 54

55 72 73 87

101

6 7

12 16 21 23 24 58 71 72 87

6 7

27 37 73

6 7

39 40

6 7

40 41

6 7

72 74 79 80 81 82 84

6 7

72 81

6 7 8

50 56 75 76

77 78

6 7

50 86

6 7

74 76 79 81 86

6 7

13 24 49

69

7

12 16

7

12 16

7

13 24

6 7

32 67

6 7

12 15 49

68

6 7

49 75 82

6 7

72 87

6 7

39 40 41

6 7

28 30 31 67

6 7

23 66 72

6 7

17 21 23 43 45 46 47 48 49

53 64 65 66 73

6 7

17 21 23 43 45 46 47 48 49

53 64 65 66 73

6 7

40 49 65 66 67 69 70 82 86

89

6 7

64 65

6 7

17 21 23 43

45 46 47

48 49 53

64 65 66

73

6 7

17 21 23 43 45 46 47 48 49

53 64 65 66 73

6 7

27 37 73

6 7

40 49 65 66 67 69 70 82 86

89

6 7

17 18 19 20 21 23 24 25 26

27 28 30 34 37 40 42 46 47 48

50 51 52 54 58 62 63 68 69 72

73 80 83 84 85 87 88 99

6 7

17 18 19 20 21 23 24 25 26

27 28 30 34 37 40 42 46 47 48

50 51 52 54 58 62 63 68 69 72

73 80 83 84 85 87 88 99

6 7

17 18 19 20 21 23 27 31 35

57 66 71 72 73 83 85 99

6 7

17 18 19 20 21 23

27 31 35 57 66 71 72 73

83 85 99

6 7

17 18 19 20 21 23 27 31 35

57 66 71 72 73 83 85

99

6 7

17 18 19 20 21 23 27 31 35

57 66 71 72 73 83 85 99

6 7

12 16 21 23 24 58 71 72 87

6 7

12 16 21 23 24 58

71 72 87 6 7

12 16 21 23 24 58 71 72 87

6 7

12 16 21 23 24 58 71 72 87

6 7

12 16 21 23 24 58 71 72 87

6 7

12 16 21 23 24 58 71 72 87

6 7

12 16 21 23 24 58 71 72 87

6 7

13 16 31 42 72 73 99

6 7

13 16 31 42 72 73 99

6 7

13 16 31 42 72 73 99

6 7

17 21 23 43 45 46 47 48 49

53 64 65 66 73

6 7

40 49 65 66 67 69 70 82 86

89

6 7

37 71 72

6 7

40 41

6 7

40 41

6 7

40 41

6 7

39 40 41

6 7

39 40 41

6 7

39 40

6 7

39 40

6 7

72 74 79 80 81 82 84

6 7

72 74 79 80 81 82 84

6 7

72 74 79 80 81

82 84 6 7

72 74 79 80 81 82 84

6 7

72 74 79 80 81 82 84

6 7

72 74 79 80 81 82 84

6 7

72 81

6 7

72 81

6 7 8

50 56 75 76

77 78 6 7 8

50 56 75 76

77 78 6 7 8

50 56 75 76

77 78

6 7 8

50 56 75 76 77 78

6 7 8

50 56 75 76

77 78

6 7

50 86

6 7

50 86

6 7

74 76 79 81 86

6 7

74 76 79 81 86

6 7

74 76 79 81 86

6 7

74 76 79 81 86

6 7

74 76 79 81 86

6 7

74 76 79 81 86

6 7

49 75 82

6 7

49 75 82

6 7

12 15 49

68

6 7

13 24 49

69

6 7

13 24 49 69

7

12 16

7

12 16

7

13 24

6 7

13 16 31 42 72 73 99

6 7

72 87

6 7

10 12 13 15 17 18 20 21 23

24 25 26 40 70 73 86

6 7

37 71 72

6 7

74 76 79 81 86

6 7

74 76 79 81 86

6 7

74 76 79 81 86

6 7

74 76 79 81 86

6 7

72 87

6 7

39 40 41

6 7

27 37 73

6 7

28 30 31 67 72

6 7

28 30 31 67 72

6 7

28 30 31 67 72

6 7

28 30 31 67 72

6 7

28 30 31 67 72

6 7

28 30 31 67

6 7

23 42 47 52 54 68 69 70 72

86 88

6 7

23 42 47 52 54 68 69 70 72

86 88

6 7

23 42 47 52 54 68 69 70 72

86 88

6 7

23 42 47 52 54 68 69 70 72

86 88

6 7

23 42 47

52 54 68 69 70

72 86 88

6 7

23 42 47 52 54 68 69 70 72

86 88

6 7

23 42 47 52 54 68 69 70 72

86 88

6 7

23 42 47 52 54 68 69 70 72

86 88

6 7

23 42 47 52 54 68 69 70 72

86 88

6 7

23 42 47 52 54 68 69 70 72

86 88

6 7

32 67

6 7

28 30 31 67

6 7

10 12 13 15 17 18 20 21 23

24 25 26 40 70 73 86

6 7

10 12 13 15 17 18 20 21 23

24 25 26 40 70 73 86

6 7

10 12 13 15 17 18 20 21 23

24 25 26 40 70 73 86

6 7

10 12 13 15 17 18 20 21 23

24 25 26 40 70 73 86 6 7

10 12 13 15 17 18 20 21 23 24 25 26 40 70 73 86

6 7 10 12 13 15 17 18 20 21 23 24 25 26 40 70 73 86

6 7

10

12 13 15 17 18 20 21 23 24 25

26 40

70 73 86

6 7 10 12 13 15 17 18 20 21 23 24 25 26 40 70 73 86

6 7

10

12 13 15 17 18 20 21 23 24 25 26

40 70 73 86

6 7

10 12 13 15 17 18 20 21 23 24 25 26 40 70 73 86

7

49 68

6 7

31 33 42

43 44 46 54 56

58 61 66 67 72

82

101

6 7

31 33 42 43 44 46 54 56 58 61 66 67

72 82

101

6 7

31 33 42 43 44 46 54 56 58 61 66 67

72 82

101

6 7

31 33 42 43 44 46 54 56 58 61 66 67

72 82

101

6 7

31 33 42 43 44 46 54 56 58 61 66 67

72 82

101

6 7

31 33 42 43 44 46 54 56 58 61 66 67

72 82

101

6 7

31 33 42 43 44 46 54 56 58 61 66 67

72 82

101

6 7

17 18 19 20 21 23 27 31 35

57 66 71 72 73 83 85 99

6 7

17 18 19 20 21 23 27 31 35

57 66 71 72 73 83 85 99

6 7

12 16

21 23 24 58 71 72 87

6 7

23 42 47 52 54 68 69 70 72

86 88

6 7

23 42 47 52 54 68 69 70 72

86 88

6 7

31 33 42 43 44 46 54 56 58 61 66 67

72 82

101

6 7

31 33 42 43 44 46 54 56 58 61 66 67

72 82

101

6 7

17 18 19 20 21 23 24 25

26 27 28 30 34 37 40 42 46 47

48 50 51 52 54 58 62 63 68 69

72 73 80 83 84 85 87 88 99

6 7

23 66 72

6 7

31 33 42 43 44 46 54 56 58 61 66 67

72 82

101

6 7

31 33 42 43 44 46 54 56 58 61 66 67

72 82

101

6 7

31 33 42 43 44 46 54 56 58 61 66 67

72 82

101

6 7

31 33 42 43 44 46 54 56 58 61 66 67

72 82

101

6 7

23 42 47 52 54 68 69 70 72

86 88

6 7

23 42 47 52 54 68 69 70 72

86 88 6 7

23 42 47 52 54 68 69 70 72

86 88

6 7

17 21 23 43 45 46 47 48 49

53 64 65 66 73

6 7

17 21 23 43 45 46 47 48 49

53 64 65 66 73

6 7

31 33 42 43 44 46 54 56 58 61 66 67

72 82

101

6 7

23 66 72

6 7

40 49 65 66

67 69 70

82 86 89

6 7

40 49 65 66 67 69 70 82 86

89

6 7

40 49 65 66 67 69 70 82 86

89

6 7

17 21 23 43 45 46 47 48 49

53 64 65 66 73

6 7

17 21 23 43 45 46 47 48 49

53 64 65 66 73

6 7

10 12 13 15 17 18 20 21

23 24 25 26 40 70 73 86

6 7 8

17 20 31 32 33 34 35 36 48 50 53 54

55 72 73 87

101

6 7 8

17 20 31 32 33 34 35 36 48 50 53 54

55 72 73 87

101

6 7 8

17 20 31 32 33 34 35 36 48 50 53 54

55 72 73 87

101

6 7 8

17 20 31 32 33 34 35 36 48 50 53 54

55 72 73 87

101

6 7

17 18 19 20 21 23 27 31 35

57 66 71 72 73 83 85 99

6 7 8

17 20 31 32 33 34 35 36 48 50 53 54

55 72 73 87

101

6 7 8

17 20 31 32 33 34 35 36 48 50 53 54

55 72 73 87

101

6 7

17 71

6 7

28 30 31 67

6 7 28 30 31 67

6 7

10 12 13 15 17 18 20 21 23 24 25 26 40 70 73 86

6 7

10 12 13 15 17 18 20 21 23 24 25 26 40 70 73 86

6 7

17 21 23 43 45 46 47 48 49

53 64 65 66 73

6 7

17 21 23 43 45 46 47 48 49

53 64 65 66 73

6 7

17 71

6 7

17 71

6 7

17 21 23 43 45 46 47 48 49

53 64 65 66 73

6 7

17 21 23 43 45 46 47 48 49

53 64 65 66 73

6 7

17 21 23 43 45 46 47 48 49

53 64 65 66 73

6 7

17 21 23 43 45 46 47 48 49

53 64 65 66 73

6 7

64 65

7

49 68

7

49 68

6 7

17 18 19 20 21 23 27 31 35

57 66 71 72 73 83 85 99

6 7

40 49 65 66 67 69 70 82 86

89

6 7

17 18 19 20 21 23 24 25 26

27 28 30 34 37 40 42 46 47 48

50 51 52 54 58 62 63 68 69 72

73 80 83 84 85 87 88 99

6 7 8

17 20 31 32 33 34 35 36 48 50 53 54

55 72 73 87

101

6 7 8

17 20 31 32 33 34 35 36 48 50 53 54

55 72 73 87

101

6 7 8

17 20 31 32 33 34

35 36 48 50

53 54 55 72 73 87

101

6 7 8

17 20 31 32 33 34 35 36 48 50 53 54

55 72 73 87

101

6 7

13 16 31 42 72 73 99

6 7

17 18 19 20 21 23 27 31 35

57 66 71 72 73 83 85 99

6 7

17 18 19 20 21 23 27 31 35

57 66 71 72 73 83 85 99

6 7

40 49 65 66 67 69 70 82 86

89

6 7

28 30 31 67 72

6 7

17 18 19 20 21 23 24 25 26

27 28

30 34 37 40 42 46 47 48 50 51 52 54 58 62 63 68 69 72 73 80 83 84 85 87 88 99

6 7

17 18 19 20 21 23 24 25 26

27 28 30 34 37 40 42 46 47 48

50 51 52 54 58 62 63 68 69 72

73 80 83 84 85 87 88 99

6 7

17 18 19 20 21 23 24 25 26

27 28

30 34 37 40 42 46 47 48 50 51 52 54 58 62 63 68 69 72 73 80 83 84 85 87 88 99

6 7

17 18 19 20 21 23

24 25 26 27

28

30 34 37 40

42

46 47 48 50 51 52 54 58 62

63

68 69 72 73 80 83 84 85 87

88

99

6 7

17 18 19 20 21 23 24 25

26 27 28 30 34 37 40 42 46

47

48 50 51 52 54 58 62 63 68

69

72 73 80 83 84 85 87 88 99

6 7

17

18 19 20 21 23 24 25 26 27 28

30

34 37 40 42 46 47 48 50 51 52 54 58 62 63 68 69 72 73 80 83 84 85 87 88 99

6 7

17 18 19 20 21 23 24 25 26

27 28 30 34 37 40 42 46 47 48

50 51 52 54 58 62 63 68 69 72

73 80 83 84 85 87 88 99

6 7

17 18 19 20 21 23 24 25 26

27 28 30 34 37 40 42 46 47 48

50 51 52 54 58 62 63 68 69 72

73 80 83 84 85 87 88 99

6 7

17 18 19 20 21 23 24 25 26

27 28

30 34 37 40 42 46 47 48 50 51 52 54 58 62 63 68 69 72 73 80 83 84 85 87 88 99

6 7

17 18 19 20 21 23 24 25 26

27 28 30 34 37 40 42 46 47 48

50

51 52 54 58 62 63 68 69 72 73

80

83 84 85 87 88 99

6 7

17 18 19 20 21 23 24 25 26

27 28 30 34 37 40 42 46 47 48

50 51 52 54 58 62 63 68 69 72

73 80 83 84 85 87 88 99

6 7

17 18 19 20 21 23 24 25 26

27 28

30 34 37 40 42 46 47 48 50 51 52 54 58 62 63 68 69 72 73 80 83 84 85 87 88 99

6 7

17

18

19

20 21 23 24 25 26 27 28 30 34 37 40 42 46 47 48 50 51 52 54 58 62 63 68 69 72 73 80 83 84 85 87 88 99

6 7

17 18 19 20 21 23 24 25 26

27 28 30 34 37 40 42 46 47 48

50 51 52 54 58 62 63 68 69 72

73 80 83 84 85 87 88 99

6 7

17 18 19 20 21 23 24 25 26

27 28

30 34 37 40 42 46 47 48 50 51 52 54 58 62 63 68 69 72 73 80 83 84 85 87 88 99

6 7

17

18

19

20 21 23 24 25 26 27 28 30 34 37 40 42 46 47 48 50 51 52 54 58 62 63 68 69 72 73 80 83 84 85 87 88 99

6 7

17 18 19 20 21 23 24 25 26

27 28 30 34 37 40 42 46 47 48

50 51 52 54 58 62 63 68 69 72

73 80 83 84 85 87 88 99

6 7

17 18 19 20 21 23 24 25 26

27 28

30 34 37 40 42 46 47 48 50 51 52 54 58 62 63 68 69 72 73 80 83 84 85 87 88 99

6 7

17

18

19

20 21 23 24 25 26 27 28 30 34 37 40 42 46 47 48 50 51 52 54 58 62 63 68 69 72 73 80 83 84 85 87 88 99

6 7

17 18 19 20 21 23 24 25 26

27 28 30 34 37 40 42 46 47 48

50 51 52

54 58 62 63 68 69 72 73 80 83 84 85 87 88 99

6 7

17 18 19 20 21 23 24 25 26

27 28 30 34 37 40 42 46 47 48

50 51 52 54 58 62 63 68 69 72

73 80 83 84 85 87 88 99

6 7

17 18 19 20 21 23 24

25 26 27

28 30 34 37 40 42 46 47 48 50

51 52 54

58 62 63 68 69 72 73 80 83 84

85 87 88 99

6 7

17 18 19 20 21 23 24 25 26

27 28 30 34 37 40 42 46 47 48

50 51 52 54 58 62 63 68 69 72

73 80 83 84 85 87 88 99

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

Digital Ground

** PEG LANES REVERSED. ARD STRAP REQ’D. **

CPU signals

GPU signals

Thermal Module Holes

Fan Holes

Frame Holes

Tall EMI pogo pins

Short (IO Row) EMI pogo pins

Left Speaker Holes

Keyboard / IPD Conn Protect

GMUX ALIASES

1/16W

1%

402

MF-LF

10

R0900

1 2

10

MF-LF

402

1%

1/16W

R0901

1 2

STDOFF-4.5OD.98H-1.1-3.48-TH

ZT0984

1

3R2P5

ZT0990

1

3R2P5

ZT0960

1

SL-3.1X2.7-6CIR-NSP

TH

ZT0950

1

3R2P5

ZT0940

1

3R2P5

ZT0915

1

STDOFF-4.5OD.98H-1.1-3.48-TH

ZT0986

1

STDOFF-4.5OD.98H-1.1-3.48-TH

ZT0981

1

STDOFF-4.5OD.98H-1.1-3.48-TH

ZT0985

1

1.4DIA-SHORT-EMI-MLB-M97-M98

SM

SH0917

1

SM

1.4DIA-SHORT-EMI-MLB-M97-M98

SH0901

1

SM

1.4DIA-SHORT-EMI-MLB-M97-M98

SH0912

1

SM

1.4DIA-SHORT-EMI-MLB-M97-M98

SH0910

1

1.4DIA-SHORT-EMI-MLB-M97-M98

SM

SH0911

1

1.4DIA-SHORT-EMI-MLB-M97-M98

SM

SH0913

1

2.0DIA-TALL-EMI-MLB-M97-M98

SM

SH0903

1

SM

2.0DIA-TALL-EMI-MLB-M97-M98

SH0916

1

2.0DIA-TALL-EMI-MLB-M97-M98

SM

SH0902

1

2.0DIA-TALL-EMI-MLB-M97-M98

SM

SH0900

1

2.0DIA-TALL-EMI-MLB-M97-M98

SM

SH0904

1

1.4DIA-SHORT-EMI-MLB-M97-M98

SM

SH0914

1

STDOFF-4.5OD.98H-1.1-3.48-TH

ZT0991

1

STDOFF-4.5OD.98H-1.1-3.48-TH

ZT0988

1

STDOFF-4.5OD.98H-1.1-3.48-TH

ZT0989

1

STDOFF-4.5OD.98H-1.1-3.48-TH

ZT0987

1

STDOFF-4.5OD.98H-1.1-3.48-TH

ZT0980

1

5%

3.0K

1/16W MF-LF

402

R0902

1 2

4.0OD1.85H-M1.6X0.35

ZT0952

1

4.0OD1.85H-M1.6X0.35

ZT0953

1

STDOFF-4.0OD3.0H-TH

ZT0934

1

STDOFF-4.0OD3.0H-TH

ZT0935

1

STDOFF-4.5OD.98H-1.1-3.48-TH

ZT0930

1

402

5% 1/16W MF-LF

10K

R0903

1

2

402

10K

MF-LF

1/16W

5%

R0904

1

2

Signal Aliases

SYNC_MASTER=K17_REF

SYNC_DATE=06/11/2009

TP_LVDS_MUX_SEL_EG

DP_IG_HPD

MAKE_BASE=TRUE

GND_CHASSIS_AUDIO_JACK

GND

FW_PLUG_DET_L

MAKE_BASE=TRUE

FW643_WAKE_L

MAKE_BASE=TRUE

PEG_CLKREQ_L

MAKE_BASE=TRUE

LVDS_IG_BKL_ON

MAKE_BASE=TRUE

PEG_R2D_C_N<15..0>

PEG_R2D_C_P<15..0>

MAKE_BASE=TRUE

PEG_D2R_P<15..0>

MAKE_BASE=TRUE

PEG_D2R_N<15..0>

GFX_VID<0..6>

MAKE_BASE=TRUE

MEMVTT_EN

MAKE_BASE=TRUE

TP_ISSP_SDATA_P1_0

TP_ISSP_SCLK_P1_1

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_PCIE_CLK100M_EXCARD_P

NC_PCIE_CLK100M_EXCARD_N

NO_TEST=TRUE

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_PCIE_EXCARD_R2D_C_N

MAKE_BASE=TRUE

DP_IG_ML_P<3..0>

MAKE_BASE=TRUE

DP_IG_ML_N<3..0>

PM_ENET_EN

MAKE_BASE=TRUE

PM_ALL_GPU_PGOOD

TP_LVDS_IG_B_CLKP

MAKE_BASE=TRUE

TP_LVDS_IG_B_CLKN

MAKE_BASE=TRUE

NC_LVDS_IG_A_DATAN<3>

NO_TEST=TRUE

NC_LVDS_IG_B_DATAP<3>

NO_TEST=TRUE

MAKE_BASE=TRUE

TP_LVDS_IG_BKL_PWM

MAKE_BASE=TRUE

NC_LVDS_IG_B_DATAN<3>

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_LVDS_IG_A_DATAP<3>

NO_TEST=TRUE

MAKE_BASE=TRUE

GPU_FB_A_VREF_DIV

MAKE_BASE=TRUE

GPU_FB_B_VREF_DIV

MAKE_BASE=TRUE

TP_CPU_VTT_SELECT

MAKE_BASE=TRUE

LCD_BKLT_EN

MAKE_BASE=TRUE

TP_LVDS_MUX_SEL_EG

MAKE_BASE=TRUE

EG_RESET_L

NC_PCIE_EXCARD_R2D_C_P

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_PCIE_EXCARD_D2R_N

NO_TEST=TRUE

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_SATA_EXTA_R2D_C_P

MAKE_BASE=TRUE

TP_SMC_EXCARD_PWR_EN

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_SATA_EXTA_D2R_N

NO_TEST=TRUE

NC_PCIE_EXCARD_D2R_P

MAKE_BASE=TRUE

DP_IG_AUX_CH_N

DP_IG_DDC_CLK

MAKE_BASE=TRUE

DP_IG_DDC_DATA

NC_SATA_EXTA_R2D_C_N

FW643_WAKE_L

NC_LVDS_IG_B_DATAP<3> NC_LVDS_IG_B_DATAN<3>

DP_IG_AUX_CH_P

DP_IG_B_ML_N<3..0>

DP_IG_B_ML_P<3..0>

LVDS_IG_BKL_ON

TP_SMC_EXCARD_PWR_EN

NC_PCIE_EXCARD_D2R_P NC_PCIE_EXCARD_R2D_C_N NC_PCIE_EXCARD_R2D_C_P NC_PCIE_CLK100M_EXCARD_N

TP_ISSP_SCLK_P1_1

=PEG_R2D_C_N<0..15>

=PEG_R2D_C_P<0..15>

=PEG_D2R_P<0..15> =PEG_D2R_N<0..15>

NC_PCIE_CLK100M_EXCARD_P

CPUIMVP_VID<0..6> GFXIMVP_VID<0..6> MEMVTT_EN

PM_ENET_EN

PEG_CLKREQ_L

TP_LVDS_IG_B_CLKN

PEX_CLKREQ_L

NC_GPU_XTALOUT

NC_LVDS_IG_A_DATAN<3>

GPU_FB_A_VREF_DIV

GPU_FB_B_VREF_DIV

TP_CPU_VTT_SELECT

PM_ALL_GPU_PGOOD

PP1V8R1V55_S0GPU_ISNS

DP_IG_HPD

LCD_BKLT_EN

FW_PLUG_DET_L

NC_PCIE_EXCARD_D2R_N

DP_IG_DDC_CLK

GND

NC_SATA_EXTA_D2R_P

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_SATA_EXTA_R2D_C_N

TP_ISSP_SDATA_P1_0

DP_IG_AUX_CH_N

DP_IG_AUX_CH_P

MAKE_BASE=TRUE

EG_RESET_L

GND

PEX_CLKREQ_L

MAKE_BASE=TRUE

LVDS_IG_PANEL_PWR LVDS_IG_PANEL_PWR

MAKE_BASE=TRUE

CPU_VID<0..6>

TP_LVDS_IG_BKL_PWM

TP_LVDS_IG_B_CLKP

NC_LVDS_IG_A_DATAP<3>

MAKE_BASE=TRUE

NC_GPU_XTALOUT

NO_TEST=TRUE

NC_USB_HUB2_OCS3

MAKE_BASE=TRUE

NC_USB_HUB1_OCS4 NC_USB_HUB2_OCS3

USB_SDCARD_N

USB_SDCARD_P

USB_SDCARD_N

MAKE_BASE=TRUE

USB_SDCARD_P

CPU_CFG<3>

DP_IG_DDC_DATA

NC_USB_HUB1_OCS4

MAKE_BASE=TRUE

PP3V3_S3

USB_EXTC_N USB_EXTC_P

NC_SATA_EXTA_R2D_C_P

NC_SATA_EXTA_D2R_P

NC_SATA_EXTA_D2R_N

VOLTAGE=0V

MIN_LINE_WIDTH=0.6 mm

GND

MIN_NECK_WIDTH=0.095 mm

9 OF 132

<SCH_NUM>

8 OF 101

8

87

8

18 84

62

8

20 40

8

39 40

8

17 87

8

18 87

74 91

9

74 91

9

74 91

13 91

8

31 67

6 8

53

6 8

53

8

17 94

8

17 94

8

17

84 93

8

71 73

8

73 82 86 87

6 8

18 93

6 8

18 93

8

18 93

8

18 93

6 8

18

8

18 93

8

18 93

8

32 77

8

32 78

8

12 91

8

87 89

8

87

8

74 87

8

17

8

17

8

17

8

45

8

17

8

17

8

18 84 93

8

18 80 84

8

18 80 84

8

17

8

39 40

8

18 93

8

18 93

8

18 84

93

18

8

18 87

8

45

8

17

8

17

8

17

8

17 94

6 8

53

9

8

17 94

68

69

8

31 67

8

71 73

8

17 87

6 8

18 93

8

74 87

8

79

8

18 93

8

32 77

8

32 78

8

12 91

8

73 82 86 87

6 7

50 56 75 76 77 78

8

18 84

8

87 89

8

20 40

8

17

8

18 80 84

8

17

8

17

6 8

53

8

18 84 93

8

18 84 93

8

74 87

8

74 87

8

18 87

8

18 87

12 15 91

6 8

18

6 8

18 93

8

18 93

8

79

8

36

8

35

8

36

8

34 36 93

8

34 36 93

8

34 36 93

8

34 36 93

9

25 91

8

18 80 84

8

35

6 7

17 20 31 32 33 34 35 36 48 50 53 54

55 72 73 87

101

35 93

8

17

8

17

8

17

IN IN IN IN

IN

OUT

IN IN

IN

IN IN

IN

IN IN IN IN IN

OUT

OUT OUT OUT

OUT

OUT OUT OUT OUT OUT

OUT OUT OUT OUT

OUT

IN

FDI_TX1

DMI_RX0*

DMI_TX2*

DMI_RX1*

PEG_RX0* PEG_RX1* PEG_RX2* PEG_RX3* PEG_RX4* PEG_RX5*

PEG_RX7*

PEG_RX6*

PEG_RX9*

PEG_RX8*

PEG_RX10*

PEG_RX12*

PEG_RX11*

PEG_RX13* PEG_RX14* PEG_RX15*

PEG_RX0 PEG_RX1

PEG_RX3

PEG_RX2

PEG_RX4 PEG_RX5 PEG_RX6 PEG_RX7 PEG_RX8 PEG_RX9

PEG_RX11

PEG_RX10

PEG_RX13

PEG_RX12

PEG_RX15

PEG_RX14

PEG_TX0* PEG_TX1* PEG_TX2*

PEG_TX4*

PEG_TX3*

PEG_TX5* PEG_TX6* PEG_TX7* PEG_TX8*

PEG_TX9* PEG_TX10* PEG_TX11* PEG_TX12* PEG_TX13* PEG_TX14* PEG_TX15*

PEG_TX0 PEG_TX1

PEG_TX3

PEG_TX2

PEG_TX5

PEG_TX4

PEG_TX6

PEG_TX8

PEG_TX7

PEG_TX9 PEG_TX10 PEG_TX11 PEG_TX12 PEG_TX13 PEG_TX14 PEG_TX15

DMI_RX2

DMI_RX0 DMI_RX1

DMI_RX3

DMI_TX0* DMI_TX1*

DMI_TX3*

DMI_TX0 DMI_TX1 DMI_TX2 DMI_TX3

FDI_TX1*

FDI_TX0*

FDI_TX2* FDI_TX3*

FDI_TX5*

FDI_TX4*

FDI_TX6* FDI_TX7*

FDI_TX0

FDI_TX3

FDI_TX2

FDI_TX4 FDI_TX5 FDI_TX6 FDI_TX7

FDI_FSYNC0 FDI_FSYNC1

FDI_LSYNC0

FDI_INT

FDI_LSYNC1

PEG_ICOMPI PEG_ICOMPO

PEG_RBIAS

PEG_RCOMPO

DMI_RX3*

DMI_RX2*

(SYM 1 OF 11)

FLEXIBLE DISPLAY INTERFACE

DMI

PCI EXPRESS -- GRAPHICS

RSVD37

RSVD36

RSVD33

RSVD32

RSVD_NCTF5

RSVD_NCTF6

RSVD_NCTF8

RSVD_NCTF7

RSVD27

RSVD24

RSVD26

RSVD23

RSVD22

RSVD21

RSVD20

RSVD19

RSVD18

RSVD17

RSVD16

RSVD15

RSVD_TP0

CFG17

CFG16

CFG15

CFG14

CFG13

CFG11 CFG12

CFG10

CFG9

CFG8

CFG7

CFG6

CFG5

CFG3 CFG4

CFG2

CFG1

CFG0

DC_TEST_A5

DC_TEST_A69 DC_TEST_A68

DC_TEST_A71

DC_TEST_C3

DC_TEST_C69

DC_TEST_C71

DC_TEST_E1

DC_TEST_E71

DC_TEST_BR1

DC_TEST_BR71

DC_TEST_BT3 DC_TEST_BT1

DC_TEST_BT69

DC_TEST_BV1

DC_TEST_BT71

DC_TEST_BV3

DC_TEST_BV68

DC_TEST_BV5

DC_TEST_BV71 DC_TEST_BV69

RSVD64 RSVD65

RSVD62 RSVD63

RSVD_TP1

RSVD_TP2

RSVD57 RSVD58

RSVD56

RSVD54 RSVD55

RSVD52 RSVD53

RSVD51

RSVD50

RSVD49

RSVD48

RSVD46 RSVD47

RSVD45

RSVD_NCTF1

RSVD_NCTF2

RSVD39

RSVD_NCTF3

RSVD38

RSVD34

RSVD_NCTF4

RSVD35

(SYM 5 OF 11)

RESERVED

BI BI

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

WF: RSVD nets with red wires have 0-ohm resistors to GND in CRB schematic.

WF: RSVD nets with arrows have offpage marks on CRB schematic.

CFG3: PCIe Lane Reversal 1 = Normal Operation 0 = Lanes Reversed

and level-shifted for

NOTE: HPD must be inverted

eDP_TX<3> eDP_TX<2> eDP_TX<1> eDP_TX<0>

eDP_TX#<0>

eDP_TX#<1>

eDP_TX#<2>

eDP_TX#<3>

eDP_HPD# eDP_AUX

eDP_AUX#

Auburndale (1.05V).

(eDP) pins

Embedded DisplayPort

(Auburndale only):

CFG4: Display Port Presence 1 = eDP Disabled 0 = Embedded Display Port Enabled

CFG0: PCIe Configuration Select 1 = Single PEG 0 = Bifurcation Enabled

(IPU)

(IPU) (IPU) (IPU) (IPU) (IPU) (IPU) (IPU) (IPU) (IPU)

(IPU)

18 91

8

74 91

8

74 91

8

74 91

8

74 91

8

74 91

8

74 91

8

74 91

8

74 91

8

74 91

8

74 91

8

74 91

8

74 91

8

74 91

8

74 91

8

74 91

8

74 91

8

74 91

8

74 91

8

74 91

8

74 91

8

74 91

8

74 91

8

74 91

8

74 91

8

74 91

8

74 91

8

74 91

8

74 91

8

74 91

8

74 91

8

74 91

8

74 91

750

MF-LF

1/16W

402

1%

R1012

1

2

1/16W

1%

49.9

402

MF-LF

R1010

1

2

25 91

8

25 91

BGA

OMIT

ARRANDALE

U1000

F9

F7

J6

J8

K9

K8

J2

J4

G17

H17

M15

K15

G13

J13

J11

F10

AC7 AC9

AB5

AA1 AB2

K1

L2

N5

N7

N2

M4

R2

P1

N9

N10

R8

R7

U6

U7

W10

W8

B12 A13

B11

D12

F40

G40

J38

G38

A24

B23

B21

D22

B19

A20

B18

D19

B16

A17

D15

B14

G34

H34

M34

P34

J28

G28

G25

H25

K24

H24

B28

D29

A27

B26

B25

D26

L40

N40

N38

L38

D33

B32

N28

L28

M25

N26

N24

M24

F21

G21

L20

J20

N32

M32

B39

D40

B37

A38

H32

G32

A34

B33

D36

B35

J30

L30

B30

A31

BGA

ARRANDALE

OMIT

U1000

AL4 AM2

AH1 AC2 AC4 AE2 AD1 AF8 AF6 AB7

AK1 AK2 AK4 AJ2 AT2 AG7 AF4 AG2

A5

A68

A69

A71

BR1

BR71

BT1

BT3

BT69

BT71

BV1

BV3

BV5

BV68

BV69

BV71

C3

C69

C71

E1

E71

T4 T2

U1 V2

AV71 AW70

AY69 BB69

D8 B7

A10

B9

W66 W64

AC69 AC71

AA71 AA69

R66 R64

AV69 AK71 AN69 AP66 AH66 AK66 AR71 AM66 AK69 AU71 AT70 AR69 AU69 AT67

AV4 AU2

BE69 BE71

BV8

BV6

BT5 BR5

F1

E3

C5 A6

AU1

AN7

AP2

51 99

SYNC_DATE=06/15/2009

SYNC_MASTER=K17_REF

CPU DMI/PEG/FDI/RSVD

CPU_CFG<0>

CPU_CFG<2>

=PEG_R2D_C_N<8>

=PEG_R2D_C_N<10> =PEG_R2D_C_N<11>

CPU_CFG<1>

CPU_CFG<4>

CPU_CFG<3>

CPU_CFG<5> CPU_CFG<6> CPU_CFG<7> CPU_CFG<8> CPU_CFG<9>

CPU_CFG<12> CPU_CFG<13> CPU_CFG<14> CPU_CFG<15> CPU_CFG<16>

TP_CPU_RSVD<15>

TP_CPU_RSVD<19>

TP_CPU_RSVD<26>

TP_CPU_RSVD<24>

TP_CPU_RSVD<27> NC_TP_CPU_RSVD_NCTF<7>

NC_TP_CPU_RSVD_NCTF<8> NC_TP_CPU_RSVD_NCTF<6>

NC_TP_CPU_RSVD_NCTF<5>

TP_CPU_RSVD<2> TP_CPU_RSVD<1>

TP_CPU_RSVD<64>

TP_CPU_RSVD<55>

TP_CPU_RSVD<54>

TP_CPU_RSVD<56> TP_CPU_RSVD<57>

TP_CPU_RSVD<45> TP_CPU_RSVD<46> TP_CPU_RSVD<47> TP_CPU_RSVD<48> TP_CPU_RSVD<49> TP_CPU_RSVD<50>

TP_CPU_RSVD<58>

TP_CPU_RSVD<52> TP_CPU_RSVD<53>

TP_CPU_RSVD<51>

NC_TP_CPU_RSVD<42>

NC_TP_CPU_RSVD<40>

NC_TP_CPU_RSVD<32> NC_TP_CPU_RSVD<33>

NC_TP_CPU_RSVD<36> NC_TP_CPU_RSVD<37>

NC_TP_CPU_RSVD<41>

NC_TP_CPU_RSVD<43>

NC_TP_CPU_RSVD<34>

NC_TP_CPU_RSVD<38> NC_TP_CPU_RSVD<39>

NC_TP_CPU_RSVD<35>

TP_CPU_TEST_BR1

TP_CPU_TEST_E1

TP_CPU_TEST_E71

TP_CPU_TEST_C3

TP_CPU_TEST_A5

TP_CPU_TEST_A68

CPU_TEST_C71_A71 CPU_TEST_C69_A69

FDI_LSYNC<1>

FDI_LSYNC<0>

FDI_INT

FDI_FSYNC<1>

FDI_FSYNC<0>

FDI_DATA_P<7>

FDI_DATA_P<6>

FDI_DATA_P<5>

FDI_DATA_P<4>

FDI_DATA_P<3>

FDI_DATA_P<2>

FDI_DATA_P<1>

FDI_DATA_P<0>

FDI_DATA_N<6> FDI_DATA_N<7>

FDI_DATA_N<5>

FDI_DATA_N<4>

FDI_DATA_N<3>

FDI_DATA_N<1> FDI_DATA_N<2>

FDI_DATA_N<0>

DMI_N2S_P<3>

DMI_N2S_P<2>

DMI_N2S_P<1>

DMI_N2S_P<0>

DMI_N2S_N<2> DMI_N2S_N<3>

DMI_N2S_N<1>

DMI_N2S_N<0>

DMI_S2N_P<3>

DMI_S2N_P<2>

DMI_S2N_P<0> DMI_S2N_P<1>

DMI_S2N_N<3>

DMI_S2N_N<2>

DMI_S2N_N<1>

DMI_S2N_N<0> CPU_PEG_COMP

CPU_PEG_RBIAS

=PEG_D2R_N<0>

=PEG_D2R_N<4> =PEG_D2R_N<5>

=PEG_D2R_N<2>

=PEG_D2R_N<1>

=PEG_D2R_N<3>

=PEG_D2R_N<9>

=PEG_D2R_N<7>

=PEG_D2R_N<6>

=PEG_D2R_N<8>

=PEG_D2R_N<14> =PEG_D2R_N<15>

=PEG_D2R_N<13>

=PEG_D2R_N<11>

PEG_D2R_P<12> PEG_D2R_P<11>

PEG_D2R_P<13>

PEG_D2R_P<14>

PEG_D2R_P<15>

PEG_D2R_P<7> PEG_D2R_P<6>

PEG_D2R_P<9>

PEG_D2R_P<10>

PEG_D2R_P<8>

PEG_D2R_P<1>

PEG_D2R_P<2>

PEG_D2R_P<3>

PEG_D2R_P<5> PEG_D2R_P<4>

=PEG_R2D_C_N<1> =PEG_R2D_C_N<2>

PEG_D2R_P<0>

=PEG_R2D_C_N<0>

=PEG_R2D_C_N<5> =PEG_R2D_C_N<6> =PEG_R2D_C_N<7>

=PEG_R2D_C_N<3> =PEG_R2D_C_N<4>

=PEG_R2D_C_N<13>

=PEG_R2D_C_N<12>

=PEG_R2D_C_N<9>

=PEG_R2D_C_N<15>

=PEG_R2D_C_N<14>

PEG_R2D_C_P<15> PEG_R2D_C_P<14>

PEG_R2D_C_P<11>

PEG_R2D_C_P<9>

PEG_R2D_C_P<10>

PEG_R2D_C_P<13> PEG_R2D_C_P<12>

PEG_R2D_C_P<6> PEG_R2D_C_P<5> PEG_R2D_C_P<4>

PEG_R2D_C_P<8> PEG_R2D_C_P<7>

PEG_R2D_C_P<0>

PEG_R2D_C_P<3> PEG_R2D_C_P<2> PEG_R2D_C_P<1>

=PEG_D2R_N<10>

=PEG_D2R_N<12>

TP_CPU_RSVD<21>

TP_CPU_RSVD<23>

TP_CPU_RSVD<22>

TP_CPU_RSVD<20>

TP_CPU_RSVD<65>

TP_CPU_TEST_BR71

TP_CPU_RSVD<18>

TP_CPU_RSVD_TP0

CPU_CFG<17>

CPU_CFG<11>

CPU_CFG<10>

CPU_TEST_BV1_BT1 CPU_TEST_BT71_BT69

CPU_TEST_BV3_BT3

TP_CPU_TEST_BV5

TP_CPU_RSVD<17>

TP_CPU_RSVD<16>

TP_CPU_TEST_BV68

CPU_TEST_BV71_BV69

CPU_THERMD_P CPU_THERMD_N

10 OF 132

<SCH_NUM>

9 OF 101

6

91

6

OUT

IN IN

IN

OUT

BI

OUT

IN

OUT

IN IN

IN

OUT

IN

OUT

IN

OUT OUT OUT

IN

OUT OUT OUT OUT

IN

BCLK_ITP

BCLK_ITP*

PEG_CLK

SM_RCOMP2

PM_EXT_TS1*

PRDY* PREQ*

THERMTRIP*

COMP1

COMP2

COMP3

COMP0

PROC_DETECT

PROCHOT*

PECI

CATERR*

RSTIN*

TAPPWRGOOD

VTTPWRGOOD

VCCPWRGOOD_0

SM_DRAMPWROK

VCCPWRGOOD_1

PM_SYNC

RESET_OBS*

BPM7*

BPM6*

BPM5*

BPM4*

BPM3*

BPM2*

BPM1*

BPM0*

TDO_M

DBR*

TDI_M

TDO

TDI

BCLK*

BCLK

TRST*

TMS

TCK

PM_EXT_TS0*

SM_RCOMP1

SM_RCOMP0

PEG_CLK*

DPLL_REF_SSCLK

DPLL_REF_SSCLK*

SM_DRAMRST*

PWR MANAGEMENTTHERMAL

JTAG & MBP

(SYM 2 OF 11)

MISC

DDR3

MISC

CLOCKS

IN

OUT OUT

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

(IPU)

(IPU) (IPU)

(IPU)

(IPD)

(IPU) (IPU)

(IPU)

(GND)

(IPU)

(IPD)

(IPU)

31

46 91

750

1/16W

1%

402

MF-LF

R1126

1

2

1.5K

1%

402

1/16W MF-LF

R1125

1 2

27

18 31 91

70 91

17 93

25 91

20 91

46 68 91

18 91

20 46 91

NO STUFF

402

1/16W MF-LF

5%

68

R1102

1

2

5%

68

MF-LF

1/16W

402

R1101

1

2

MF-LF

1/16W 402

1%

49.9

R1100

1

2

17 93

49.9

MF-LF

402

1%

1/16W

R1112

1

2

1% MF-LF

1/16W 402

49.9

R1113

1

2

20

MF-LF

1/16W

402

1%

R1110

1

2

20

1%

402

1/16W MF-LF

R1111

1

2

25 91

25

17 91

25

25 91

25 27 91

25 91

17 91

25 91

1%

100

MF-LF

1/16W

402

R1162

1

2

1%

MF-LF

1/16W

402

130

R1160

1

2

1%

24.9

402

1/16W MF-LF

R1161

1

2

MF-LF

5%

402

10K

1/16W

R1150

1

2

1/16W MF-LF

5%

402

10K

R1151

1

2

20 91

5%

51

MF-LF

1/16W

402

R1170

1

2

20 25 91

1K

5% MF-LF

402

1/16W

R1103

1

2

OMIT

BGA

ARRANDALE

U1000

AK7 AK8

K71 J70

J69 J67 J62 K65 K62 J64 K69 M69

N61

AE66

AD69

AC70

AD71

W71

Y2 W4

N19

L21 J21

AV66 AV64

M17

U71 U69

M71

N67

N70

G3

AM5

BJ12

BV33 BP39 BV40

Y70

T67

T69

P71

T71

T70

N17

N65 P69

Y67

AM7

H15

20 91

402

1K

5% MF-LF

1/16W

R1120

1

2

25 91

CPU Clock/Misc/JTAG

SYNC_MASTER=K17_REF

SYNC_DATE=06/15/2009

PM_MEM_PWRGD

PP1V05_S0

CPU_COMP3 CPU_COMP2

XDP_DBRESET_L

JTAG_CPU_TDO

XDP_CPUPWRGD

PM_SYNC

FSB_CPURST_L

CPU_COMP0

CPU_PROCHOT_L

CPU_PECI

PM_THRMTRIP_L

CPU_CATERR_L

XDP_BPM_L<6>

XDP_BPM_L<4>

PP1V05_S0

PM_EXT_TS_L<0>

GFX_CLK120M_DPLLSS_N

CPU_MEM_RESET_L CPU_SM_RCOMP0

CPU_PWRGD

CPUVTTS0_PGOOD

CPU_SM_RCOMP2

CPU_SM_RCOMP1

PM_EXT_TS_L<1>

GFX_CLK120M_DPLLSS_P

FSB_CLK133M_ITP_N

FSB_CLK133M_CPU_N FSB_CLK133M_ITP_P

PCIE_CLK100M_CPU_P

XDP_PRDY_L XDP_PREQ_L

CPU_COMP1

PLT_RESET_LS1V1_L

XDP_BPM_L<7>

XDP_BPM_L<5>

XDP_BPM_L<0>

JTAG_GMCH_TDI

FSB_CLK133M_CPU_P

XDP_TMS

XDP_TCK

PCIE_CLK100M_CPU_N

PLT_RST_BUF_L

XDP_BPM_L<3>

XDP_BPM_L<2>

XDP_BPM_L<1>

JTAG_GMCH_TDO

JTAG_CPU_TDI

XDP_TRST_L

TP_CPU_SKTOCC_L

11 OF 132

<SCH_NUM>

10 OF 101

6 7

10 12 13 15 17 18 20 21

23 24 25 26 40 70 73 86

91

6 7

10 12 13 15 17 18 20 21

23 24 25 26 40 70 73 86

91

BI BI BI BI BI BI BI BI BI BI BI BI BI BI

BI

BI BI BI BI BI BI

BI

BI BI BI BI BI BI

BI

BI BI BI BI BI BI

BI

BI BI BI BI BI BI

BI

BI BI BI BI BI BI

BI

BI BI BI BI BI BI

BI

OUT

BI

BI BI

OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT

OUT OUT OUT OUT OUT OUT OUT OUT

OUT OUT

OUT

OUT OUT

OUT

OUT OUT

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

OUT OUT OUT

OUT

OUT OUT

OUT

OUT OUT

OUT

OUT OUT

OUT OUT OUT OUT OUT OUT OUT OUT

BI BI BI BI BI

BI

OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT

SA_RAS* SA_WE*

SA_CAS*

SA_BS2

SA_BS1

SA_BS0

SA_DQ62 SA_DQ63

SA_DQ60 SA_DQ61

SA_DQ59

SA_DQ58

SA_DQ57

SA_DQ54

SA_DQ56

SA_DQ55

SA_DQ53

SA_DQ52

SA_DQ51

SA_DQ50

SA_DQ49

SA_DQ48

SA_DQ47

SA_DQ46

SA_DQ44 SA_DQ45

SA_DQ41 SA_DQ42 SA_DQ43

SA_DQ40

SA_DQ39

SA_DQ37

SA_DQ36

SA_DQ38

SA_DQ35

SA_DQ34

SA_DQ32

SA_DQ31

SA_DQ33

SA_DQ30

SA_DQ29

SA_DQ28

SA_DQ27

SA_DQ26

SA_DQ24 SA_DQ25

SA_DQ23

SA_DQ22

SA_DQ21

SA_DQ19 SA_DQ20

SA_DQ18

SA_DQ17

SA_DQ16

SA_DQ13

SA_DQ15

SA_DQ14

SA_DQ12

SA_DQ11

SA_DQ10

SA_DQ9

SA_DQ8

SA_DQ7

SA_DQ5 SA_DQ6

SA_DQ3 SA_DQ4

SA_DQ1 SA_DQ2

SA_DQ0

SA_MA15

SA_MA14

SA_MA13

SA_MA12

SA_MA11

SA_MA10

SA_MA9

SA_MA7 SA_MA8

SA_MA6

SA_MA5

SA_MA4

SA_MA3

SA_MA2

SA_MA1

SA_MA0

SA_DQS7

SA_DQS6

SA_DQS4 SA_DQS5

SA_DQS3

SA_DQS1 SA_DQS2

SA_DQS0

SA_DQS7*

SA_DQS6*

SA_DQS5*

SA_DQS4*

SA_DQS3*

SA_DQS2*

SA_DQS1*

SA_DQS0*

SA_DM7

SA_DM6

SA_DM5

SA_DM4

SA_DM3

SA_DM2

SA_DM1

SA_DM0

SA_ODT1

SA_ODT0

SA_CS1*

SA_CS0*

SA_CK1*

SA_CKE1

SA_CKE0

SA_CK1

SA_CK0

SA_CK0*

(SYM 3 OF 11)

DDR SYSTEM MEMORY A

SB_DQ0 SB_CK0 SB_DQ1

SB_CK0*

SB_DQ2

SB_CKE0

SB_DQ3 SB_DQ4

SB_CK1

SB_DQ5

SB_CK1*

SB_DQ6 SB_DQ7

SB_CKE1 SB_DQ8 SB_DQ9

SB_CS0* SB_DQ10 SB_CS1* SB_DQ11 SB_DQ12 SB_ODT0 SB_DQ13 SB_ODT1 SB_DQ14 SB_DQ15

SB_DM0

SB_DQ16

SB_DM1

SB_DQ17

SB_DM2

SB_DQ18

SB_DM3

SB_DQ19

SB_DM4

SB_DQ20

SB_DM5

SB_DQ21

SB_DM6

SB_DQ22

SB_DM7 SB_DQ23 SB_DQ24

SB_DQS0*

SB_DQ25

SB_DQS1*

SB_DQ26

SB_DQS2*

SB_DQ27

SB_DQS3*

SB_DQ28

SB_DQS4*

SB_DQ29

SB_DQS5*

SB_DQ30

SB_DQS6*

SB_DQ31

SB_DQS7* SB_DQ32 SB_DQ33 SB_DQS0 SB_DQ34 SB_DQS1 SB_DQ35 SB_DQS2 SB_DQ36 SB_DQS3 SB_DQ37 SB_DQS4 SB_DQ38 SB_DQS5 SB_DQ39 SB_DQS6 SB_DQ40 SB_DQS7 SB_DQ41 SB_DQ42

SB_MA0

SB_DQ43

SB_MA1

SB_DQ44

SB_MA2

SB_DQ45

SB_MA3

SB_DQ46

SB_MA4

SB_DQ47

SB_MA5

SB_DQ48

SB_MA6

SB_DQ49

SB_MA7

SB_DQ50

SB_MA8

SB_DQ51

SB_MA9 SB_DQ52 SB_MA10 SB_DQ53 SB_MA11 SB_DQ54 SB_MA12 SB_DQ55 SB_MA13 SB_DQ56 SB_MA14 SB_DQ57 SB_MA15 SB_DQ58 SB_DQ59 SB_DQ60 SB_DQ61 SB_DQ62 SB_DQ63

SB_BS0 SB_BS1 SB_BS2

SB_CAS* SB_RAS* SB_WE*

DDR SYSTEM MEMORY B

(SYM 4 OF 11)

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

29 92

28 29 92

29 92

28 92

29 92

28 29 92

29 92

28 29 92

29 92

28 92

28 29 92

29 92

28 92

29 92

29 30 92

29 92

30 92

29 30 92

29 92

29 30 92

29 92

29 30 92

29 92

30 92

OMIT

BGA

ARRANDALE

U1000

BT38 BH38 BF21

BK43

BM34 BP35

BK36 BH36

BF20

BK24

BH40 BJ47

BB10 BJ10 BM15 BN24 BG44 BG53 BN62 BH59

AT8 AT6

BK5

BH13

BF9 BF6 BK7 BN8

BN11

BN9 BG17 BK15

BB5

BK9 BG15 BH17 BK17 BN20 BN17 BK25 BH25 BJ20 BH21

BB9

BG24 BG25 BJ40 BM43 BF47 BF48 BN40 BH43 BN44 BN47

AV7

BN48 BN51 BH53 BJ55 BH48 BJ48 BM53 BN55 BF55 BN57

AV6

BN65 BJ61 BF57 BJ57 BK64 BK61 BJ63 BF64 BB64 BB66

BE6

BJ66 BF65 AY64 BC70

BE8 BF11 BE11

AY7

AY5

BJ5

BJ7

BL13

BN13

BN21

BL21

BK44

BH44

BH51

BK51

BM60

BP58

BE64

BE62

BT36 BP33

BH34 BH30 BJ28 BF40 BN28 BN25

BV36 BG34 BG32 BN32 BK32 BJ30 BN30 BF28

BF43 BL47

BL38 BF38

BGA

ARRANDALE

OMIT

U1000

BV43 BV41 BV24

BU46

BU33 BV34

BV38 BU39

BT26

BT24

BP46 BT43

BB4 BL4 BT13 BP22 BV47 BV57 BU65 BF67

BA2 AW2

BR6 BR8 BJ4 BK2

BU9 BV10 BR10 BT12 BT15 BV15

BD1

BV12 BP12 BV17 BU16 BP15 BU19 BV22 BT22 BP19 BV19

BE4

BV20 BT20 BT48 BV48 BV50 BP49 BT47 BV52 BV54 BT54

AY1

BP53 BU53 BT59 BT57 BP56 BT55 BU60 BV59 BV61 BP60

BC2

BR66 BR64 BR62 BT61 BN68 BL69 BJ71 BF70 BG71 BC67

BF2

BK70 BK67 BD71 BD69

BH2

BG4

BG1

BD4

BE2

BN4

BM3

BV13

BU12

BT17

BT19

BT50

BT52

BU56

BV55

BV62

BU63

BJ69

BG69

BT34 BP30

BU42 BU26 BT29 BT45 BV26 BU23

BV29 BU30 BV31 BT33 BT31 BP26 BV27 BT27

BV45 BU49

BT40 BT41

CPU DDR3 Interfaces

SYNC_MASTER=K17_REF

SYNC_DATE=06/15/2009

MEM_B_DQ<27>

MEM_B_DQ<0>

MEM_B_CLK_P<0>

MEM_B_DQ<1>

MEM_B_CLK_N<0>

MEM_B_DQ<2>

MEM_B_CKE<0>

MEM_B_DQ<3> MEM_B_DQ<4>

MEM_B_CLK_P<1>

MEM_B_DQ<5>

MEM_B_CLK_N<1>

MEM_B_DQ<6> MEM_B_DQ<7>

MEM_B_CKE<1> MEM_B_DQ<8> MEM_B_DQ<9>

MEM_B_CS_L<0> MEM_B_DQ<10>

MEM_B_CS_L<1> MEM_B_DQ<11> MEM_B_DQ<12> MEM_B_ODT<0> MEM_B_DQ<13> MEM_B_ODT<1> MEM_B_DQ<14> MEM_B_DQ<15>

MEM_B_DM<0> MEM_B_DQ<16>

MEM_B_DM<1> MEM_B_DQ<17>

MEM_B_DM<2> MEM_B_DQ<18>

MEM_B_DM<3> MEM_B_DQ<19>

MEM_B_DM<4> MEM_B_DQ<20>

MEM_B_DM<5> MEM_B_DQ<21>

MEM_B_DM<6> MEM_B_DQ<22>

MEM_B_DM<7> MEM_B_DQ<23> MEM_B_DQ<24>

MEM_B_DQS_N<0> MEM_B_DQ<25>

MEM_B_DQS_N<1> MEM_B_DQ<26>

MEM_B_DQS_N<2>

MEM_B_DQS_N<3> MEM_B_DQ<28>

MEM_B_DQS_N<4> MEM_B_DQ<29>

MEM_B_DQS_N<5> MEM_B_DQ<30>

MEM_B_DQS_N<6> MEM_B_DQ<31>

MEM_B_DQS_N<7> MEM_B_DQ<32> MEM_B_DQ<33>

MEM_B_DQS_P<0> MEM_B_DQ<34>

MEM_B_DQS_P<1> MEM_B_DQ<35>

MEM_B_DQS_P<2> MEM_B_DQ<36>

MEM_B_DQS_P<3> MEM_B_DQ<37>

MEM_B_DQS_P<4> MEM_B_DQ<38>

MEM_B_DQS_P<5> MEM_B_DQ<39>

MEM_B_DQS_P<6> MEM_B_DQ<40>

MEM_B_DQS_P<7> MEM_B_DQ<41> MEM_B_DQ<42>

MEM_B_A<0> MEM_B_DQ<43>

MEM_B_A<1> MEM_B_DQ<44>

MEM_B_A<2> MEM_B_DQ<45>

MEM_B_A<3> MEM_B_DQ<46>

MEM_B_A<4> MEM_B_DQ<47>

MEM_B_A<5> MEM_B_DQ<48>

MEM_B_A<6> MEM_B_DQ<49>

MEM_B_A<7> MEM_B_DQ<50>

MEM_B_A<8> MEM_B_DQ<51>

MEM_B_A<9> MEM_B_DQ<52>

MEM_B_A<10> MEM_B_DQ<53>

MEM_B_A<11> MEM_B_DQ<54>

MEM_B_A<12> MEM_B_DQ<55>

MEM_B_A<13> MEM_B_DQ<56>

MEM_B_A<14> MEM_B_DQ<57>

MEM_B_A<15> MEM_B_DQ<58> MEM_B_DQ<59> MEM_B_DQ<60> MEM_B_DQ<61> MEM_B_DQ<62> MEM_B_DQ<63>

MEM_B_BA<0> MEM_B_BA<1> MEM_B_BA<2>

MEM_B_CAS_L MEM_B_RAS_L MEM_B_WE_L

MEM_A_CLK_P<0>

MEM_A_DQ<4>

MEM_A_CS_L<1>

MEM_A_A<2>

MEM_A_CLK_N<0>

MEM_A_RAS_L MEM_A_WE_L

MEM_A_CAS_L

MEM_A_BA<2>

MEM_A_BA<1>

MEM_A_BA<0>

MEM_A_DQ<62> MEM_A_DQ<63>

MEM_A_DQ<60> MEM_A_DQ<61>

MEM_A_DQ<59>

MEM_A_DQ<58>

MEM_A_DQ<57>

MEM_A_DQ<54>

MEM_A_DQ<56>

MEM_A_DQ<55>

MEM_A_DQ<53>

MEM_A_DQ<52>

MEM_A_DQ<51>

MEM_A_DQ<50>

MEM_A_DQ<49>

MEM_A_DQ<48>

MEM_A_DQ<47>

MEM_A_DQ<46>

MEM_A_DQ<44> MEM_A_DQ<45>

MEM_A_DQ<41> MEM_A_DQ<42> MEM_A_DQ<43>

MEM_A_DQ<40>

MEM_A_DQ<39>

MEM_A_DQ<37>

MEM_A_DQ<36>

MEM_A_DQ<38>

MEM_A_DQ<35>

MEM_A_DQ<34>

MEM_A_DQ<32>

MEM_A_DQ<31>

MEM_A_DQ<33>

MEM_A_DQ<30>

MEM_A_DQ<29>

MEM_A_DQ<28>

MEM_A_DQ<27>

MEM_A_DQ<26>

MEM_A_DQ<24> MEM_A_DQ<25>

MEM_A_DQ<23>

MEM_A_DQ<22>

MEM_A_DQ<21>

MEM_A_DQ<19> MEM_A_DQ<20>

MEM_A_DQ<18>

MEM_A_DQ<17>

MEM_A_DQ<16>

MEM_A_DQ<13>

MEM_A_DQ<15>

MEM_A_DQ<14>

MEM_A_DQ<12>

MEM_A_DQ<11>

MEM_A_DQ<10>

MEM_A_DQ<9>

MEM_A_DQ<8>

MEM_A_DQ<7>

MEM_A_DQ<5> MEM_A_DQ<6>

MEM_A_DQ<3>

MEM_A_DQ<1> MEM_A_DQ<2>

MEM_A_DQ<0>

MEM_A_A<15>

MEM_A_A<14>

MEM_A_A<13>

MEM_A_A<12>

MEM_A_A<11>

MEM_A_A<10>

MEM_A_A<9>

MEM_A_A<7> MEM_A_A<8>

MEM_A_A<6>

MEM_A_A<5>

MEM_A_A<4>

MEM_A_A<3>

MEM_A_A<1>

MEM_A_A<0>

MEM_A_DQS_P<7>

MEM_A_DQS_P<6>

MEM_A_DQS_P<4> MEM_A_DQS_P<5>

MEM_A_DQS_P<3>

MEM_A_DQS_P<1> MEM_A_DQS_P<2>

MEM_A_DQS_P<0>

MEM_A_DQS_N<7>

MEM_A_DQS_N<6>

MEM_A_DQS_N<5>

MEM_A_DQS_N<4>

MEM_A_DQS_N<3>

MEM_A_DQS_N<2>

MEM_A_DQS_N<1>

MEM_A_DQS_N<0>

MEM_A_DM<7>

MEM_A_DM<6>

MEM_A_DM<5>

MEM_A_DM<4>

MEM_A_DM<3>

MEM_A_DM<2>

MEM_A_DM<1>

MEM_A_DM<0>

MEM_A_ODT<1>

MEM_A_ODT<0>

MEM_A_CS_L<0>

MEM_A_CLK_N<1> MEM_A_CKE<1>

MEM_A_CKE<0>

MEM_A_CLK_P<1>

12 OF 132

<SCH_NUM>

11 OF 101

OUT OUT OUT OUT OUT OUT OUT

OUT

OUT OUT

IN

OUT

VCAP0_15

VCAP0_17

VCC_1 VCC_2 VCC_3 VCC_4 VCC_5

VCC_7

VCC_6

VCC_9

VCC_10

VCC_12

VCC_11

VCC_14

VCC_13

VCC_15

VCC_17

VCC_16

VCC_18 VCC_19 VCC_20 VCC_21 VCC_22

VCC_25

VCC_24

VCC_23

VCC_26 VCC_27

VCC_29 VCC_30

VCC_28

VCC_32

VCC_31

VCC_34

VCC_33

VCC_35

VCC_37

VCC_36

VCC_38

VCC_40

VCC_39

VCC_42

VCC_41

VCC_43 VCC_44 VCC_45 VCC_46 VCC_47

VCC_50

VCC_49

VCC_51 VCC_52 VCC_53

VCC_55

VCC_54

VCC_56

VCC_58

VCC_57

VCC_60

VCC_59

VCC_62

VCC_61

VCC_63 VCC_64 VCC_65 VCC_66 VCC_67 VCC_68 VCC_69 VCC_70 VCC_71 VCC_72 VCC_73 VCC_74 VCC_75 VCC_76 VCC_77 VCC_78

VCC_81

VCC_79 VCC_80

VCC_83

VCC_82

VCC_84 VCC_85 VCC_86 VCC_87

VCC_89

VCC_88

VCAP0_1 VCAP0_2

VCAP0_4

VCAP0_3

VCAP0_5 VCAP0_6 VCAP0_7 VCAP0_8 VCAP0_9

VCAP0_12

VCAP0_10 VCAP0_11

VCAP0_14

VCAP0_16

VCAP0_19

VCAP0_18

VCAP0_20 VCAP0_21 VCAP0_22 VCAP0_23 VCAP0_24 VCAP0_25 VCAP0_26 VCAP0_27

VCAP1_2

VCAP1_1

VCAP1_5

VCAP1_3 VCAP1_4

VCAP1_7

VCAP1_6

VCAP1_8

VCAP1_10

VCAP1_9

VCAP1_13

VCAP1_11 VCAP1_12

VCAP1_15

VCAP1_14

VCAP1_18

VCAP1_17

VCAP1_16

VCAP1_20

VCAP1_19

VCAP1_23

VCAP1_21 VCAP1_22

VCAP1_24 VCAP1_25

VCAP1_27

VCAP1_26

VCAP0_13

VCC_8

VCC_48

(SYM 8 OF 11)

CPU CORE SUPPLY

POWER

VSS_SENSE_VTT

VTT_SENSE

VSS_SENSE

VCC_SENSE

ISENSE

VID2 VID3 VID4

PSI*

VTT0_9

VTT0_22

VTT0_24

VTT0_23

VTT0_26

VTT0_25

VTT0_27 VTT0_28 VTT0_29 VTT0_30 VTT0_31 VTT0_32 VTT0_33 VTT0_34

VTT0_36

VTT0_35

VTT0_37 VTT0_38 VTT0_39 VTT0_40 VTT0_41 VTT0_42 VTT0_43 VTT0_44 VTT0_45 VTT0_46 VTT0_47 VTT0_48 VTT0_49 VTT0_50 VTT0_51 VTT0_52 VTT0_53 VTT0_54 VTT0_55 VTT0_56 VTT0_57 VTT0_58 VTT0_59

VTT0_62

VTT0_60 VTT0_61

VTT0_63 VTT0_64 VTT0_65

VTT0_67

VTT0_66

VTT0_68

VTT0_70

VTT0_69

VTT0_72

VTT0_71

VTT0_73

VTT0_4

VTT0_6

VTT0_5

VTT0_7 VTT0_8

VTT0_10 VTT0_11

VTT0_13

VTT0_12

VTT0_16

VTT0_15

VTT0_14

VTT0_17 VTT0_18 VTT0_19 VTT0_20 VTT0_21

VID5 VID6

VTT_SELECT1

PROC_DPRSLPVR

VTT0_1 VTT0_2 VTT0_3

VID1

VID0

VCCPLL1 VCCPLL2

VCCPLL4

VCCPLL3

VCCPLL5

VDDQ_CK1 VDDQ_CK2

1.8V

(SYM 6 OF 11)

1.1V RAIL POWER

CPU VIDS

SENSE LINES

POWER

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

NOTE: VCAP1 is sourced by CPU

but provide bypass caps on PCB.

Clarksfield: 1.1V

(Controlled by VTT_SELECT pin)

Arrandale: 1.05V

but provide bypass caps on PCB.

Do not connect to power supply,

NOTE: VCAP0 is sourced by CPU

VTT_SELECT: 1 = 1.05V, 0 = 1.1V

8

15 91

8

15 91

8

15 91

8

15 91

8

15 91

8

15 91

8

15 91

8

91

15 68 91

70 91

50 68 91

PLACE_NEAR=U1000.F63:25.4MM

MF-LF

402

100

1%

1/16W

R1301

1

2

68 91

PLACE_NEAR=U1000.F64:25.4MM

MF-LF

402

100

1%

1/16W

R1300

1

2

PLACE_NEAR=U1000.N13:25.4MM

1/16W

10

MF-LF 402

1%

R1305

1

2

PLACE_NEAR=U1000.R12:25.4MM

MF-LF 402

1% 1/16W

10

R1306

1

2

ARRANDALE

BGA

OMIT

U1000

BD55

AW57 AW53 AW50 AU55 AU51 AU48 AR55 AR51 AR48 AN57

BD51

AN53 AN50 AL57 AL53 AL50 AK57 AK53 AK50

BD48 BB55 BB51 BB48 AY57 AY53 AY50

BD44

AW46 AW42 AW39 AU44 AU41 AU37 AR44 AR41 AR37 AN46

BD41

AN42 AN39 AL46 AL42 AL39 AK46 AK42 AK39

BD37 BB44 BB41 BB37 AY46 AY42 AY39

AF57

AF41 AD55 AD51 AD48 AD44 AD41 AB55 AB51 AB48 AB44

AF55

AB41 AA55 AA51 AA48 AA44 AA41 W55 W51 W48 W44

AF53

W41 U55 U51 U48 U44 U41 R55 R51 R48 R44

AF51

R41 P60 N55 N51 N48 N44 N42 M60 M51 M44

AF50

L55 K60 K51 K44 J55 H60 H51 H44 G60 G55

AF48

G51 G44 F55 E60 E57 E53 E50 E46 E42 D59

AF46

D57 D55 D54 D52 D50 D48 D47 D45 D43 B60

AF44

B56 B53 B49 B46 B42 A57 A54 A50 A47 A43

AF42

OMIT

BGA

ARRANDALE

U1000

A41

F66

F68

F64

W39 W37 U37 R39 R37

BB14 BB12

A61 D61 D62 A62 B63 D64 D66

F63

R12

BF60

AW33 AW14 AW12 AU60 AU59 AU12 AR60 AR59 AR12 AN60

BF59

AN59 AN35 AN33 AN17 AN15 AN14 AN12 AM10 AL60 AL59

BD60

AL17 AL15 AL14 AL12 AK35 AK33 AF39 AF37 AF35 AF33

BD59

AF32 AF30 AD39 AD37 AD35 AD33 AD32 AD30 W35 W33

BB60

W32 W30 W28 W26 W24 W23 U35 U33 U32 U30

BB59

U28 U26 U24 U23 R35 R33 R32 R30 R28 R26

AY60

R24 R23 AY10 AN9

AW60 AW35

AN1

N13

SYNC_DATE=06/15/2009

SYNC_MASTER=K17_REF

CPU Power (1 of 2)

CPU_VID<1> CPU_VID<2> CPU_VID<3>

CPUIMVP_IMON

PM_DPRSLPVR

PP1V05_S0

CPU_VTTSENSE_P CPU_VTTSENSE_N

PPVCORE_S0_CPU_VCAP0

PP1V8_S0

CPU_VCCSENSE_N

CPU_VID<4>

CPU_PSI_L

CPU_VID<5> CPU_VID<6>

TP_CPU_VTT_SELECT

CPU_VID<0>

PPVCORE_S0_CPU

PPVCORE_S0_CPU_VCAP1

CPU_VCCSENSE_P

PP1V5_S3_CPU_VCCDDR_CLK

MIN_NECK_WIDTH=0.2mm VOLTAGE=1.5V

MIN_LINE_WIDTH=0.4mm

13 OF 132

<SCH_NUM>

12 OF 101

6 7

10 12 13 15 17 18 20 21 23

24 25 26 40 70 73 86

6 7

10 12 13 15 17 18 20 21

23 24 25 26 40 70 73 86

7

16

6 7

16 21 23 24 58 71 72 87

6 7

12 15 49 68

6 7

12 15 49 68

7

16

VAXG35

VTT1_7

VTT1_9 VTT1_10

VTT1_8

VTT1_5

VAXG3

VAXG2

VAXG1

VSSAXG_SENSE

VAXG_SENSE

VCAP2_19

VCAP2_17 VCAP2_18

VCAP2_16

VCAP2_14 VCAP2_15

VCAP2_12 VCAP2_13

VCAP2_11

VCAP2_10

VCAP2_9

VCAP2_8

VCAP2_6 VCAP2_7

VCAP2_5

VCAP2_4

VCAP2_3

VCAP2_1 VCAP2_2

VTT1_11

VTT1_6

VTT1_4

VTT1_3

VTT1_2

VTT1_1

VAXG37

VAXG36

VAXG33 VAXG34

VAXG32

VAXG31

VAXG30

VAXG27

VAXG29

VAXG28

VAXG25 VAXG26

VAXG23 VAXG24

VAXG22

VAXG20 VAXG21

VAXG19

VAXG17 VAXG18

VAXG14

VAXG16

VAXG15

VAXG13

VAXG12

VAXG11

VAXG10

VAXG9

VAXG8

VAXG7

VAXG6

VAXG5

VAXG4

VTT1_21

VTT1_20

VTT1_18 VTT1_19

VTT1_17

VTT1_16

VTT1_15

VTT1_14

VTT1_13

VTT1_12

VTT0_DDR9

VTT0_DDR8

VTT0_DDR7

VTT0_DDR6

VTT0_DDR5

VTT0_DDR4

VTT0_DDR3

VTT0_DDR2

VTT0_DDR1

VTT0_DDR

VDDQ36

VDDQ35

VDDQ34

VDDQ33

VDDQ31 VDDQ32

VDDQ30

VDDQ29

VDDQ28

VDDQ27

VDDQ26

VDDQ24 VDDQ25

VDDQ23

VDDQ21 VDDQ22

VDDQ20

VDDQ19

VDDQ18

VDDQ17

VDDQ16

VDDQ15

VDDQ13 VDDQ14

VDDQ12

VDDQ11

VDDQ10

VDDQ9

VDDQ8

VDDQ7

VDDQ6

VDDQ5

VDDQ4

VDDQ3

VDDQ2

GFX_IMON

VDDQ1

GFX_DPRSLPVR

GFX_VR_EN

GFX_VID6

GFX_VID5

GFX_VID4

GFX_VID3

GFX_VID2

GFX_VID1

GFX_VID0

(SYM 7 OF 11)

POWER

PEG & DMI

LINES

SENSE

GRAPHICS VIDS

GRAPHICS

DDR3 -1.5 V RAILS

OUT

OUT OUT

IN

OUT

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

Do not connect to power supply, but provide bypass caps on PCB.

NOTE: VCAP2 is sourced by CPU

OMIT

ARRANDALE

BGA

U1000

AL71

AL69

AF71 AG67 AG70 AH71 AN71 AM67 AM70

AH69

AN32

AL30 AL28 AL26 AL24 AL23 AL21 AL19 AK14 AK12 AJ10

AN30

AH14 AH12 AF28 AF26 AF24 AF23 AF21 AF19 AF17 AF15

AN28

AF14 AD28 AD26 AD24 AD23 AD21 AD19 AD17

AN26 AN24 AN23 AN21 AN19 AL32

AF12

AK62

AB60 AB59 AA60 AA59

W60 W59 U60 U59 R60 R59

AK60 AK59 AH60 AH59 AF60 AF59 AD60 AD59

BU40

BG43 BF16 BF15 BD35 BD33 BD32 BD30 BD28 BD26 BD24

BU35

BD23 BD21 BD19 BD17 BD15 BB35 BB33 BB32 BB30 BB28

BU28

BB26 BB24 BB23 BB21 BB19 BB17 BB15

BN38 BM25 BL30 BJ38 BH32 BH28

AF10

AW32 AW30 AW28 AW26 AW24 AW23 AW21 AW19 AW17 AW15

W21

R19 R17

AD15 AD14 AD12 AB12 AA12 W17 W15 W14

W19

W12 R15

U21 U19 U17 U15 U14 U12 R21

8

91

PLACE_NEAR=U1000.AF10:25.4MM

402

1%

100

1/16W MF-LF

R1401

1

2

MF-LF

402

1/16W

4.7K

5%

R1405

1

2

69 91

PLACE_NEAR=U1000.AF12:25.4MM

100

1/16W

1%

402

MF-LF

R1400

1

2

69 91

8

91

8

91

8

91

8

91

8

91

8

91

SYNC_DATE=06/15/2009

SYNC_MASTER=K17_REF

CPU Power (2 of 2)

PPVCORE_S0_GFX

PP1V05_S0

PPVCORE_S0_CPU_VCAP2

GFX_VID<3>

GFX_VID<5> GFX_VID<6>

GFX_VID<0> GFX_VID<1>

GFX_VSENSE_N

PPVCORE_S0_GFX

GFX_VSENSE_P

GFXIMVP_IMON

GFX_VID<2>

GFX_DPRSLPVR

GFX_VR_EN

GFX_VID<4>

PP1V05_S0

PP1V1R1V05_S0_CPU_VTT0_DDR

PP1V5_S3RS0

14 OF 132

<SCH_NUM>

13 OF 101

6 7

13 24 49 69

6 7

10 12 13 15 17 18 20 21

23 24 25 26 40 70 73 86

7

24

6 7

13 24 49 69

6 7

10 12 13 15 17 18 20 21 23

24 25 26 40 70 73 86

15

6 7

16 31 42 72 73 99

VSS77

VSS11

VSS16

VSS110 VSS111

VSS113

VSS112

VSS114

VSS116

VSS115

VSS118

VSS117

VSS119

VSS121

VSS120

VSS122

VSS124

VSS123

VSS125 VSS126 VSS127 VSS128 VSS129

VSS131

VSS130

VSS133

VSS132

VSS134

VSS136

VSS135

VSS137 VSS138 VSS139

VSS141

VSS140

VSS142 VSS143 VSS144

VSS147

VSS145 VSS146

VSS149

VSS148

VSS150

VSS1 VSS2 VSS3

VSS5

VSS4

VSS6 VSS7 VSS8

VSS10

VSS9

VSS13

VSS12

VSS14 VSS15

VSS17 VSS18 VSS19 VSS20 VSS21

VSS23

VSS22

VSS25

VSS24

VSS26

VSS28

VSS27

VSS29 VSS30 VSS31

VSS33

VSS32

VSS34 VSS35 VSS36

VSS39

VSS37 VSS38

VSS41

VSS40

VSS43

VSS42

VSS44

VSS46

VSS45

VSS47

VSS49

VSS48

VSS51

VSS50

VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62

VSS64

VSS63

VSS66

VSS65

VSS67

VSS69

VSS68

VSS71

VSS70

VSS72 VSS73 VSS74 VSS75

VSS76

VSS80

VSS78 VSS79

VSS82

VSS81

VSS85

VSS83 VSS84

VSS87

VSS86

VSS90

VSS88 VSS89

VSS92

VSS91

VSS93

VSS95

VSS94

VSS96 VSS97 VSS98

VSS99 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106

VSS108

VSS107

VSS109

(SYM 9 OF 11)

VSS215 VSS216

VSS214

VSS213

VSS212

VSS210 VSS211

VSS207 VSS208 VSS209

VSS205 VSS206

VSS204

VSS203

VSS202

VSS200 VSS201

VSS199

VSS197 VSS198

VSS195 VSS196

VSS194

VSS192 VSS193

VSS190 VSS191

VSS189

VSS187 VSS188

VSS185

VSS184

VSS186

VSS182 VSS183

VSS181

VSS180

VSS179

VSS177 VSS178

VSS176

VSS175

VSS174

VSS172 VSS173

VSS171

VSS169 VSS170

VSS166 VSS167 VSS168

VSS164 VSS165

VSS163

VSS162

VSS161

VSS159 VSS160

VSS158

VSS156 VSS157

VSS154 VSS155

VSS153

VSS152

VSS151

VSS227

VSS226

VSS228

VSS230

VSS229

VSS231

VSS239 VSS240

VSS232 VSS233 VSS234 VSS235 VSS236

VSS238

VSS237

VSS241

VSS250 VSS251

VSS249

VSS247

VSS242 VSS243

VSS246

VSS245

VSS244

VSS248

VSS261

VSS260

VSS259

VSS253

VSS252

VSS254

VSS256

VSS255

VSS257 VSS258

VSS270 VSS271

VSS268

VSS264

VSS263

VSS262

VSS265 VSS266 VSS267

VSS269

VSS272

VSS280 VSS281

VSS273 VSS274

VSS276

VSS275

VSS277 VSS278 VSS279

VSS282

VSS292

VSS290 VSS291

VSS288

VSS284

VSS283

VSS286

VSS285

VSS287

VSS289

VSS294

VSS293

VSS296

VSS295

VSS297 VSS298 VSS299 VSS300

VSS217 VSS218

VSS220

VSS219

VSS222

VSS221

VSS223

VSS225

VSS224

(SYM 10 OF 11)

VSS358

VSS363

VSS301

VSS429

VSS428

VSS427

VSS426

VSS423

VSS425

VSS424

VSS421 VSS422

VSS420

VSS418 VSS419

VSS416 VSS417

VSS414

VSS413

VSS415

VSS411 VSS412

VSS408 VSS409 VSS410

VSS406 VSS407

VSS405

VSS403 VSS404

VSS400

VSS402

VSS401

VSS398 VSS399

VSS397

VSS396

VSS395

VSS393 VSS394

VSS392

VSS391

VSS390

VSS388 VSS389

VSS387

VSS385 VSS386

VSS383 VSS384

VSS382

VSS380 VSS381

VSS377

VSS379

VSS378

VSS375 VSS376

VSS372 VSS373 VSS374

VSS371

VSS370

VSS367

VSS369

VSS368

VSS366

VSS365

VSS364

VSS362

VSS360 VSS361

VSS357

VSS359

VSS355 VSS356

VSS352 VSS353 VSS354

VSS351

VSS350

VSS347

VSS349

VSS348

VSS345 VSS346

VSS342

VSS344

VSS343

VSS340 VSS341

VSS339

VSS337 VSS338

VSS334 VSS335 VSS336

VSS332 VSS333

VSS330 VSS331

VSS329

VSS327 VSS328

VSS326

VSS325

VSS324

VSS322 VSS323

VSS321

VSS319 VSS320

VSS318

VSS317

VSS316

VSS314 VSS315

VSS313

VSS312

VSS311

VSS309 VSS310

VSS308

VSS307

VSS306

VSS305

VSS304

VSS303

VSS302

VSS432 VSS433

VSS431

VSS430

(SYM 11 OF 11)

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

OMIT

ARRANDALE

BGA

U1000

BU62

BU21

AW67 AW62 AW59 AW55 AW51 AW48 AW44 AW41 AW37 AV9

BU18

AV1 AU70 AU62 AU57 AU53 AU50 AU46 AU42 AU39 AU35

BU14

AU33 AU32 AU30 AU28 AU26 AU24 AU23 AU21 AU19 AU17

BU11

AU15 AU14 AU4 AT64 AT10 AR62 AR57 AR53 AR50 AR46

BU7

AR42 AR39 AR35 AR33 AR32 AR30 AR28 AR26 AR24 AR23

BP42

AR21

BN64

BN6 BM70 BM51

BU58

BM44 BM32 BM24 BM17 BL57 BL55 BL48 BL40 BL28 BL20

BU55

BK63 BK60 BK53 BK34 BK10 BJ64 BJ21

BJ9

BJ1 BH70

BU51

BH57 BH55 BH47 BH24 BH20 BH15 BG51 BG36 BF62 BF30

BU48

BF13

BF8 BE70 BE65

BE9

BE1 BD57 BD53 BD50 BD46

BU44

BD42 BD39 BD14 BB71 BB62 BB57 BB53 BB50 BB46 BB42

BU37

BB39

BB7

BB1 BA70 AY71 AY66

AY62 AY59 AY55 AY51

BU32

AY48 AY44 AY41 AY37 AY35 AY33 AY32 AY30 AY28 AY26

BU25

AY24 AY23 AY21 AY19 AY17 AY15 AY14 AY12 AY8 AY4

ARRANDALE

BGA

OMIT

U1000

AR19 AR17 AR15 AR14

AR4

AR1 AP70 AP64 AN62 AN55 AN51 AN48 AN44 AN41 AN37

AN5

AN4 AM64

AM8 AL62 AL55 AL51 AL48 AL44 AL41 AL37 AL35 AL33

AL1 AK70 AK64 AK55 AK51 AK48 AK44 AK41 AK37 AK32 AK30 AK28 AK26 AK24 AK23 AK21 AK19 AK17 AK15 AJ70 AH62 AH57 AH55 AH53 BV66 AH51 BV64 AH50 BT68 AH48 BR69 BL71 AH46

BL1 AH37 BR68

R14 AH35 AH44

H71 AH33

BR3

F71 AH32 AH42

E69 AH30

BN71 E68 AH28 AH41 A66 AH26 BN1 A64 AH24 AH39 E5 AH23 C68 AH21 AH19 AH17 AH15 AH4 AG64 AG9 AG6 AF69 AF62 AF1 AE70 AE64 AD62 AD57 AD53 AD50 AD46 AD42 AD4 AC67 AC64 AC10 AC5 AC1 AB70 AB62 AB57 AB53 AB50 AB46 AB42 AB39 AB37 AB35 AB33 AB32 AB30 AB28 AB26 AB24 AB23 AB21 AB19 AB17 AB15 AB14 AB9 AA66 AA64 AA62 AA57 AA53 AA50 AA46 AA42 AA39 AA37 AA35 AA33 AA32 AA30

ARRANDALE

BGA

OMIT

U1000

AA28 AA26 AA24 AA23 AA21 AA19 AA17 AA15 AA14

AA4 W69 W62 W57 W53 W50 W46 W42

W6

W1 V70 U64 U62 U57 U53 U50 U46 U42 U39

U9

U4

T1 R70 R62 R57 R53 R50 R46 R42

R5

P4 N63 N57 N53 N50 N46 N30 N21 N15 M53 M42 M36

M1 L70 L57 L48 L47 L13 K64 K53 K43 K36 K34 K32 K25 K17 K11

K6 K4 J65 J57 J48 J47 J40 J9 H53 H43 H36 H1 G70 G57 G53 G48 G47 G43 G30 G24 G20 G15 F61 F48 F47 F28 F20 F4 E37 E33 E30 E16 E12 D41 D38 D34 D31 D27 D24 D20 D17 D13 D10 D6 B65 B62 B58 B55 B51 B48 B44 A59 A55 A52 A48 A45 A40 A36 A33 A29 A26 A22 A19 A15 A12 A8 B40

SYNC_DATE=06/15/2009

SYNC_MASTER=K17_REF

CPU Grounds

15 OF 132

<SCH_NUM>

14 OF 101

OUT OUT OUT OUT OUT OUT OUT OUT OUT

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM GROUP

TABLE_BOMGROUP_HEAD

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PLACEMENT_NOTE (C1625-C1634):

VTT (CPU Uncore) DECOUPLING

PLACEMENT_NOTE (C1600-C1624):

VTT0_DDR DECOUPLING

Instead call out appropriate BOM GROUP defined in tables above.

IMAX @ 900mV

22.5

40A

VID[2:0] = Reserved (111) VID[5:3] = GPU Gain Setting (See below)

NOTE: BOM Configurations should not call out CPUPOCnU/D BOMOPTIONs directly.

18

90A

70A

20A 30A

001

Intel recommends all option straps should be provided in layout

CPU Power On Configuration (POC) Straps

Equivalent Gain

45 30

15

12.857 10

PSI# = Reserved (0)

DPRSLPVR = 1 - IMVP-6.5 compliant controller

VID[6] = Reserved (0)

000

111

110

101

100

011

010

50A 60A

PLACEMENT_NOTE (C1695-C1697):

3x 1uF 0402

PLACEMENT_NOTE (C1657-C1663):

PLACEMENT_NOTE (C1664-C1687):

PLACEMENT_NOTE (C1653-C1656):

3x 330uF 6 mOhm, 4x 22uF 0805, 7x 10uF 0603, 24x 1uF 0402

Design recommendations from Calpella Small Form Factor Design Guide Rev 1.5 (doc #407364) table 2-34 and Calpella Small Form Factor Schematic Check List Rev 1.1 (doc #395914) table 3.26.

CPU Gain Setting

4x 470uF 4.5mOhm, 3x 62uF B2, 10x 22uF 0603, 25x 1uF 0402

CPU VCore HF and Bulk Decoupling

PLACEMENT_NOTE (C1635-C1648):

2

1

R1600

MF-LF

1/16W

5%

402

1K

2

1

R1602

MF-LF

1/16W

5%

402

1K

2

1

R1601

MF-LF

1/16W

5%

402

1K

2

1

R1603

MF-LF

1/16W

5%

402

1K

CPUPOC3U

2

1

R1606

MF-LF

1/16W

5%

402

1K

NO STUFF

2

1

R1607

MF-LF

1/16W

5%

402

1K

2

1

R1604

5%

402

1K

CPUPOC4U

MF-LF

1/16W

2

1

R1605

MF-LF

1/16W

5%

402

1K

CPUPOC5U

2

1

R1616

MF-LF

402

1K

5%

1/16W

2

1

R1617

1K

402

5% 1/16W MF-LF

NO STUFF

2

1

R1615

MF-LF

1/16W

5%

1K

CPUPOC5D

402

2

1

R1614

MF-LF

1/16W

CPUPOC4D

402

5%

1K

2

1

R1612

NO STUFF

5%

1K

1/16W MF-LF

402

2

1

R1613

MF-LF

1/16W

5%

402

1K

CPUPOC3D

NO STUFF

2

1

R1610

MF-LF

402

1K

1/16W

5%

2

1

R1611

MF-LF

1/16W

5%

402

1K

NO STUFF

2

1

R1608

1K

402

5% 1/16W MF-LF

NO STUFF

2

1

R1618

1K

5% 1/16W MF-LF

402

8

12 91

8

12 91

8

12 91

8

12 91

8

12 91

8

12 91

8

12 91

12 68 91

2

1

Place near inductors on bottom side.

20%

603

X5R-CERM

6.3V

22UF

C1635

NO STUFF

2

1

C1625

20% X5R-CERM

6.3V 603

22UF

Place near U1000 on bottom side.

NO STUFF

10%

1UF

X5R

16V 402

1

2

C1600

Place on bottom side of U1000..

2

6.3V X5R-CERM 603

22UF

20%

Place near inductors on bottom side.

1

C1636

NO STUFF

10%

1UF

X5R 402

1

2

C1607

16V

1UF

16V 402

1

2

C1606

10% X5R

10%

1UF

X5R

16V 402

1

2

C1605

X5R

16V 402

1

2

C1604

10%

1UF 1UF

X5R

16V 402

1

2

C1611

10%

X5R

16V 402

1

2

C1610

10%

1UF

1

C1609

2

16V X5R

10%

1UF

402

10%

1UF

X5R 402

1

2

C1608

16V

1UF

16V 402

1

2

C1624

10% X5R

10%

1UF

16V 402

1

C1623

2

X5R

10%

1UF

16V 402

1

2

X5R

C1622

10%

1UF

16V 402

1

2

C1621

X5R

Place on bottom side of U1000..

10%

1UF

402

1

2

X5R

16V

C1601

10%

1UF

X5R

16V

1

2

C1620

402

10% 16V

402

1

2

1UF

C1619

X5R

10%

1UF

16V 402

1

2

C1618

X5R

10%

1UF

16V 402

1

2

X5R

C1617

10%

1UF

X5R

16V

1

2

C1616

402

10%

1UF

X5R 402

1

2

C1615

16V

10%

1UF

X5R

16V 402

1

2

C1614

10%

1UF

X5R

16V 402

1

2

C1613

10%

1UF

X5R 402

1

2

C1612

16V

2

1

C1675

1UF

Place on bottom side of U1000.

10V 402

X5R

10%

2

1

C1674

Place on bottom side of U1000.

10V 402

X5R

10%

1UF

2

1

C1687

Place on bottom side of U1000.

10% X5R

1UF

402

10V

2

1

C1686

Place on bottom side of U1000.

10% X5R

1UF

402

10V

2

1

C1673

Place on bottom side of U1000.

10V 402

1UF

X5R

10%

2

1

C1685

Place on bottom side of U1000.

10% X5R

1UF

402

10V

2

1

C1672

Place on bottom side of U1000.

10V 402

1UF

X5R

10%

2

1

C1671

Place on bottom side of U1000.

10V 402

1UF

X5R

10%

2

1

C1684

Place on bottom side of U1000.

10% X5R

1UF

402

10V

2

1

C1683

Place on bottom side of U1000.

10% X5R

1UF

402

10V

2

1

C1670

Place on bottom side of U1000.

10V 402

1UF

X5R

10%

2

1

C1682

Place on bottom side of U1000.

10% X5R

1UF

402

10V

2

1

C1669

Place on bottom side of U1000.

10V 402

1UF

X5R

10%

2

1

C1681

Place on bottom side of U1000.

10% X5R

1UF

402

10V

2

1

C1668

Place on bottom side of U1000.

10V 402

1UF

X5R

10%

2

1

C1680

Place on bottom side of U1000.

10% X5R

1UF

402

10V

2

1

C1667

Place on bottom side of U1000.

10V 402

1UF

X5R

10%

2

1

C1666

Place on bottom side of U1000.

10V 402

1UF

X5R

10%

2

1

C1643

6.3V X5R-CERM 603

20%

Place near inductors on bottom side.

22UF

NO STUFF

2

1

C1679

Place on bottom side of U1000.

10% X5R

1UF

402

10V

2

1

C1678

Place on bottom side of U1000.

10% X5R

1UF

402

10V

2

1

C1665

Place on bottom side of U1000.

10V 402

1UF

X5R

10%

2

1

C1677

Place on bottom side of U1000.

10% X5R

1UF

402

10V

2

1

C1664

Place on bottom side of U1000.

10V 402

1UF

X5R

10%

2

1

C1676

Place on bottom side of U1000.

10% X5R

1UF

402

10V

2

1

C1697

Place on bottom side of U1000.

10V 402

1UF

X5R

10%

2

1

C1696

Place on bottom side of U1000.

10V 402

X5R

10%

1UF

2

1

6.3V X5R-CERM 603

20%

Place near inductors on bottom side.

22UF

C1644

2

1

C1695

Place on bottom side of U1000.

10V 402

1UF

X5R

10%

21

L1695

0603

30-OHM-5A

2

1

6.3V

22UF

603

20% X5R-CERM

C1626

NO STUFF

Place near U1000 on bottom side.

2

1

Place near U1000 on bottom side.

603

20%

22UF

X5R-CERM

6.3V

C1629

NO STUFF

2

1

C1634

Place near U1000 on bottom side.

603

20% X5R-CERM

22UF

6.3V

NO STUFF

2

1

C1641

603

Place near inductors on bottom side.

20% X5R-CERM

6.3V

22UF

NO STUFF

2

1

C1642

603

Place near inductors on bottom side.

22UF

6.3V X5R-CERM

20%

2

1

C1698

Place near U1000 on bottom side.

603

20%

22UF

X5R-CERM

6.3V

2

1

C1694

Place near U1000 on bottom side.

20%

6.3V 603

X5R-CERM

22UF

C1693

2

1

Place near U1000 on bottom side.

603

22UF

X5R-CERM

6.3V

20%

NO STUFF

2

1

Place near U1000 on bottom side.

6.3V 603

20%

C1692

22UF

X5R-CERM

NO STUFF

20%

2

1

C1691

Place near U1000 on bottom side.

X5R-CERM

6.3V

22UF

603

NO STUFF

C16A0

1

2

CASE-B2

11V ELEC

62UF

20%

11V ELEC CASE-B2

2

1

C16A1

62UF

NO STUFF

20%

C16A3

11V ELEC

62UF

20%

CASE-B2

2

1

20%

62UF

11V CASE-B2

2

1

C16A2

ELEC

2

1

11V ELEC

20%

CASE-B2

62UF

C16A4

603

20%

C1645

2

1

6.3V

22UF

Place near inductors on bottom side.

NO STUFF

X5R-CERM

2

1

C1637

6.3V X5R-CERM 603

22UF

Place near inductors on bottom side.

NO STUFF

20%

X5R-CERM

2

1

C1638

603

22UF

20%

Place near inductors on bottom side.

6.3V

1

C1627

Place near U1000 on bottom side.

20%

22UF

X5R-CERM

6.3V 603

2

Place on bottom side of U1000..

1UF

16V 402

1

2

C1602

10% X5R

2

1

Place near U1000 on bottom side.

6.3V X5R-CERM 603

22UF

20%

NO STUFF

C1628

Place on bottom side of U1000..

X5R

16V 402

1

2

C1603

10%

1UF

Place near inductors on bottom side.

2

1

6.3V X5R-CERM 603

20%

22UF

C1646

NO STUFF

2

1

C1640

6.3V 603

20%

Place near inductors on bottom side.

X5R-CERM

22UF

NO STUFF

2

1

C1630

Place near U1000 on bottom side.

603

20%

6.3V

22UF

X5R-CERM

2

1

C1631

Place near U1000 on bottom side.

20% 603

22UF

6.3V X5R-CERM

NO STUFF

2

1

C1648

6.3V X5R-CERM 603

20%

22UF

2

1

C1632

Place near U1000 on bottom side.

603

20%

6.3V

22UF

X5R-CERM

3 2

1

C1649

2.0V

20%

470UF-4MOHM

D2T-SM

POLY-TANT

3 2

1

C1650

D2T-SM

POLY-TANT

20%

2.0V

470UF-4MOHM

3 2

1

C1651

2.0V

20%

D2T-SM

POLY-TANT

470UF-4MOHM

POLY-TANT

470UF-4MOHM

3 2

1

C1652

D2T-SM

2.0V

20%

2

1

C1653

6.3V

Place on bottom side of U1000.

X5R-CERM 603

22UF

20%

2

1

C1654

Place on bottom side of U1000.

X5R-CERM 603

22UF

20%

6.3V

2

1

C1655

Place on bottom side of U1000.

X5R-CERM 603

22UF

20%

6.3V

2

1

C1656

Place on bottom side of U1000.

X5R-CERM 603

20%

6.3V

22UF

2

1

C1663

603

X5R

10UF

20%

6.3V

Place on bottom side of U1000..

2

1

C1662

603

X5R

10UF

20%

6.3V

Place on bottom side of U1000..

2

1

C1661

603

X5R

10UF

20%

6.3V

Place on bottom side of U1000..

2

1

C1660

603

X5R

10UF

20%

6.3V

Place on bottom side of U1000..

2

1

C1659

603

X5R

10UF

6.3V

20%

Place on bottom side of U1000..

2

1

C1658

X5R 603

10UF

6.3V

20%

Place on bottom side of U1000..

2

1

C1657

603

10UF

6.3V

20%

Place on bottom side of U1000..

X5R

3 2

1

C1688

POLY-TANT

2.0V

20%

D2T-SM2

330UF

3 2

1

C1689

D2T-SM2

POLY-TANT

2.0V

20%

330UF

3 2

1

330UF

D2T-SM2

POLY-TANT

2.0V

20%

C1690

SYNC_MASTER=K17_REF

CPU Non-GFX Decoupling (1 of 2)

SYNC_DATE=06/15/2009

CPUPOC_IMAX_DIS

CPUPOC3D,CPUPOC4D,CPUPOC5D

CPUPOC3U,CPUPOC4U,CPUPOC5U

CPUPOC_IMAX_70_90

CPUPOC3U,CPUPOC4D,CPUPOC5U

CPUPOC_IMAX_50_60

CPUPOC3U,CPUPOC4U,CPUPOC5D

CPUPOC_IMAX_60_70

CPUPOC_IMAX_40_50

CPUPOC3U,CPUPOC4D,CPUPOC5D

CPUPOC_IMAX_0_20

CPUPOC3D,CPUPOC4D,CPUPOC5U

CPUPOC_IMAX_30_40

CPUPOC3D,CPUPOC4U,CPUPOC5U

CPUPOC_IMAX_20_30

CPUPOC3D,CPUPOC4U,CPUPOC5D

PPVCORE_S0_CPU

PP1V05_S0

CPU_PSI_L

PM_DPRSLPVR

CPU_VID<4>

CPU_VID<3>

CPU_VID<2>

CPU_VID<1>

CPU_VID<0>

PP1V05_S0

CPU_VID<5> CPU_VID<6>

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.1V

PP1V1R1V05_S0_CPU_VTT0_DDR

16 OF 132

<SCH_NUM>

15 OF 101

6 7

12 49 68

6 7

10 12 13 15

17 18 20 21 23 24

25 26 40 70 73 86

6 7

10 12 13 15 17 18 20 21

23 24 25 26 40 70 73 86

13

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

VCAP1 (CPU BSC Package) DECOUPLING

VCAP0 (CPU BSC Package) DECOUPLING

5x 1uF 0402

1x 22uF 0805, 1x 4.7uF 0603

1x 1uF 0402

PLACEMENT_NOTE (C1700-C1711):

12x 1uF 0402

PLACEMENT_NOTE (C1712-C1723):

NOTE: 19x 1uF 0402 caps per Apple SI for CMD and CNTRL lines.

Memory (CPU VCCDDR) DECOUPLING

PLL (CPU VCCSFR) DECOUPLING

DDR Clock (CPU VDDQ_CK) DECOUPLING

NOTE: 3x 330uF 6 mOhm caps to be shared between CPU and SO-DIMMs. DG recommends 2x 22uF at SO_DIMM not provided. Decoupling caps at SO-DIMMs on CSA 29 and CSA 31.

Design recommendations from Calpella Small Form Factor Design Guide Rev 1.5 (doc #407364) table 2-34 and Calpella Small Form F actor Schematic Check List Rev 1.1 (doc #395914) table 3.26.

10V 402

1UF

10% X5R

C1745

1

2

1UF

X5R

10%

402

10V

C1744

1

2

10V 402

1UF

10% X5R

C1743

1

2

1UF

X5R

10%

402

10V

C1742

1

2

10V 402

1UF

10% X5R

C1741

1

2

1UF

10% X5R

402

10V

C1740

1

2

X5R 402

1UF

10% 10V

C1739

1

2

1UF

X5R

10%

402

10V

C1738

1

2

10V 402

1UF

10% X5R

C1737

1

2

1UF

X5R

10%

402

10V

C1736

1

2

10V 402

1UF

10% X5R

C1735

1

2

1UF

X5R

10%

402

10V

C1753

1

2

10V 402

1UF

10% X5R

C1752

1

2

1UF

10% X5R

402

10V

C1751

1

2

X5R 402

1UF

10% 10V

C1750

1

2

1UF

X5R

10%

402

10V

C1749

1

2

402

X5R

10V

1UF

10%

C1748

1

2

1UF

X5R

10%

402

10V

C1747

1

2

402

10V

1UF

10% X5R

C1746

1

2

30-OHM-5A

0603

L1734

1 2

Place on bottom side of U1000.

10%

1UF

X5R

16V 402

1

2

C1723

Place on bottom side of U1000.

10%

1UF

X5R

16V 402

1

2

C1722

Place on bottom side of U1000.

10%

1UF

X5R

16V 402

1

2

C1721

Place on bottom side of U1000.

10% X5R

16V 402

1

2

1UF

C1720

Place on bottom side of U1000.

10%

1UF

X5R

16V 402

1

2

C1719

Place on bottom side of U1000.

10% X5R

16V 402

1

2

1UF

C1718

Place on bottom side of U1000.

10%

1UF

X5R

16V 402

1

2

C1717

Place on bottom side of U1000.

10%

1UF

X5R

16V 402

1

2

C1716

Place on bottom side of U1000.

10%

1UF

X5R

16V 402

1

2

C1715

Place on bottom side of U1000.

10%

1UF

X5R

16V 402

1

2

C1714

Place on bottom side of U1000.

10%

1UF

X5R

16V 402

1

2

C1713

Place on bottom side of U1000.

10%

1UF

X5R

16V 402

1

2

C1712

Place on bottom side of U1000.

10%

1UF

X5R

16V 402

1

2

C1711

Place on bottom side of U1000.

10%

1UF

X5R

16V 402

1

2

C1710

Place on bottom side of U1000.

10%

1UF

X5R

16V 402

1

2

C1709

Place on bottom side of U1000.

10% X5R

16V 402

1

2

1UF

C1708

Place on bottom side of U1000.

10%

1UF

X5R

16V 402

1

2

C1707

Place on bottom side of U1000.

10% X5R

16V 402

1

2

1UF

C1706

Place on bottom side of U1000.

10%

1UF

X5R

16V 402

1

2

C1705

Place on bottom side of U1000.

10%

1UF

X5R

16V 402

1

2

C1704

Place on bottom side of U1000.

10%

1UF

X5R

16V 402

1

2

C1703

Place on bottom side of U1000.

10%

1UF

X5R

16V 402

1

2

C1702

Place on bottom side of U1000.

10%

1UF

X5R

16V 402

1

2

C1701

Place on bottom side of U1000.

10%

1UF

X5R

16V 402

1

2

C1700

1UF

10V

10% X5R

402

C1728

1

2

1UF

X5R

10%

402

10V

C1727

1

2

10V 402

1UF

10% X5R

C1726

1

2

1UF

10% 10V

402

X5R

C1725

1

2

X5R

1UF

10%

402

10V

C1724

1

2

X5R-CERM 603

10%

6.3V

4.7UF

C1733

1

2

805

CERM-X5R

22uF

6.3V

20%

C1732

1

2

10V 402

10% X5R

1UF

C1734

1

2

POLY-TANT

2.0V

20%

D2T-SM2

330UF

C1729

1

23

SYNC_MASTER=K17_REF

CPU Non-GFX Decoupling (2 of 2)

SYNC_DATE=06/15/2009

PP1V5_S3RS0

PP1V8_S0

PP1V5_S3RS0

PP1V5_S3_CPU_VCCDDR_CLK

PPVCORE_S0_CPU_VCAP0

PPVCORE_S0_CPU_VCAP1

17 OF 132

<SCH_NUM>

16 OF 101

6 7

13 16 31 42

72 73 99

6 7

12 21 23 24

58 71 72 87

6 7

13 16 31 42

72 73 99

12

7

12

7

12

IN

OUT

IN

BI BI BI BI

OUT

BI

IN

IN OUT OUT

IN

IN OUT OUT

IN IN

OUT

OUT OUT

OUT

IN

OUT

OUT OUT

IN

OUT OUT

IN

OUT OUT

OUT

IN

OUT

IN

IN IN

IN

OUT

BI

OUT

BI

IN IN OUT OUT

FWH4/LFRAME*

SATA1GP/GPIO19

INTVRMEN

SATAICOMPI

SATAICOMPO

SATA0TXN

SATA0RXN

SATA0TXP

SATA0RXP

SATA1TXP

SATA1RXP

SATA1RXN

SATA1TXN

SATA2TXN

SATA2RXN

SATA2TXP

SATA2RXP

SATA5TXN

SATA5RXN

SATA4TXN

SATA4RXN

SATA3TXN

SATA3RXN

SATA5TXP

SATA5RXP

SATA4TXP

SATA4RXP

SATA3TXP

SATA3RXP

FWH1/LAD1

LDRQ0*

LDRQ1*/GPIO23

SERIRQ

FWH3/LAD3

FWH2/LAD2

FWH0/LAD0

SATALED*

SATA0GP/GPIO21

HDA_SYNC

SPKR

SPI_MISO

SPI_MOSI

SPI_CS1*

SPI_CS0*

SPI_CLK

JTAG_TDO

JTAG_RST*

JTAG_TDI

JTAG_TMS

JTAG_TCK

HDA_DOCK_RST*/GPIO13

HDA_DOCK_EN*/GPIO33

HDA_SDO

HDA_SDIN2 HDA_SDIN3

HDA_SDIN1

HDA_SDIN0

HDA_RST*

HDA_BCLK

INTRUDER*

SRTCRST*

RTCRST*

RTCX2

RTCX1

(1 OF 10)

RTC

LPC

IHDAJTAG

SPI

SATA

CLKOUT_DMI_N CLKOUT_DMI_P

CLKOUT_DP_N/CLKOUT_BCLK1_N CLKOUT_DP_P/CLKOUT_BCLK1_P

CLKIN_DMI_N CLKIN_DMI_P

CLKIN_BCLK_N CLKIN_BCLK_P

CLKIN_DOT_96N CLKIN_DOT_96P

CLKIN_PCILOOPBACK

XTAL25_IN

XTAL25_OUT

CLKOUT_PEG_A_P

CLKOUT_PEG_A_N

PEG_A_CLKRQ*/GPIO47

CL_RST1*

CL_DATA1

CL_CLK1

SML1DATA/GPIO75

SML1CLK/GPIO58

SML1ALERT*/GPIO74

SML0DATA

SML0CLK

SML0ALERT*/GPIO60

SMBDATA

CLKOUTFLEX1/GPIO65

CLKOUTFLEX0/GPIO64

XCLK_RCOMP

CLKOUTFLEX2/GPIO66

CLKOUTFLEX3/GPIO67

CLKOUT_PCIE0N CLKOUT_PCIE0P

CLKOUT_PCIE1N

CLKOUT_PCIE2N

PCIECLKRQ1*/GPIO18

PCIECLKRQ2*/GPIO20

CLKOUT_PCIE2P

CLKOUT_PCIE3P

CLKOUT_PCIE3N

PCIECLKRQ3*/GPIO25

CLKOUT_PCIE4N

PCIECLKRQ4*/GPIO26

CLKOUT_PCIE4P

CLKOUT_PCIE5P

CLKOUT_PCIE5N

PCIECLKRQ5*/GPIO44

CLKOUT_PEG_B_P

CLKOUT_PEG_B_N

PEG_B_CLKRQ*/GPIO56

PETP8

PETN8

PERP8

PERN8

PETP7

PETN7

PERP7

PERN7

PETP6

PERP6 PETN6

PETP5

PERN6

PERP5

PERN5

PETN5

PETP4

PETN4

PERP4

PERN4

PETP3

PETN3

PERP3

PERN3

PETP2

PERP2 PETN2

PETP1

PERN2

PERP1

PERN1

PETN1

SMBCLK

SMBALERT*/GPIO11

CLKIN_SATA_N/CKSSCD_N CLKIN_SATA_P/CKSSCD_P

REFCLK14IN

CLKOUT_PCIE1P

PCIECLKRQ0*/GPIO73

FROM CLK BUFFER

(2 OF 10)

SMBUS

C-LINKPEG

CLOCK

FLEX

PCI-E*

OUT OUT

IN

OUT

BI

OUT

IN

IN IN

OUT OUT

OUT

IN

OUT

IN

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

CLKOUTFLEX3 also supports 48 MHz.

Default: 24.576 MHz (unsupported)

Default: 48 MHz

Default: 0V

All 4 CLKOUTFLEX outputs support

(IPD)

port multipliers

(IPU)

Unused

(IPD)

Not available on

eSATA

SSD

ODD

HDD

(IPD)

(IPU)

(IPD)

(IPU)

(IPD)

Default: 14.31818 MHz

33.333 MHz and 14.31818 MHz,

Unused

(IPU/NO)

Only ports 4 & 5

(IPD)

(IPU)

some IbexPeak SKUs

(IPU)

support FIS-based

(IPU)

(IPD)

27

58 94

17 25

47 94

17 25

47 94

6

45 47 87 94

6

45 47 87 94

6

45 47 87 94

6

45 47 87 94

6

45 47 87 94

6

45 47

42 93

37 94

6

33 94

6

33 94

39 94

37 94

33 94

39 94

37 94

17 37

37 94

33 94

17 25 33

39 94

17 25 40

10 91

74 94

8

17 87

10 93

26 93

27 93

27

48 94

25 26 28 30 32 42 47 48 63 88

94

25 26 28 30 32 42 47 48 63 88 94

8

330K

402

MF-LF

1/16W

5%

R1800

1

2

1/16W MF-LF

1M

402

5%

R1801

1

2

5%

20K

402

1/16W MF-LF

R1802

1

2

20K

402

5% 1/16W MF-LF

R1803

1

2

X5R

10V

10%

1UF

402

C1803

1

2

10V X5R 402

1UF

10%

C1802

1

2

1%

402

MF-LF

37.4

1/16W

R1830

1

2

10K

1/16W

5% MF-LF

402

R1820

1

2

IBEX_PEAK_M

FCBGA

OMIT

U1800

D33 B33 C32 A32

C34

A30

H32 J30

C30

G30 F30 E32 F32

B29

D29

A16

A14

J4

M3

K1

J2

K3

A34 F34

C14

B13 D13

Y9

AK7 AK6 AK11 AK9

V1

AH6 AH5 AH9 AH8

AF11 AF9 AF7 AF6

AH3 AH1 AF3 AF1

AD9 AD8 AD6 AD5

AD3 AD1 AB3 AB1

AF15

AF16

T3

AB9

BA2

AV3

AY3

AV1

AY1

P1

D17

FCBGA

OMIT

IBEX_PEAK_M

U1800

T13

T11

T9

AP3 AP1

AW24 BA24

F18 E18

J42

AH13 AH12

AN4 AN2

AT1 AT3

AK48 AK47

AM43 AM45

AM47 AM48

AH42 AH41

AM51 AM53

AJ50 AJ52

AD43 AD45

AK53 AK51

T45

P43

T42

N50

P9

U4

N4

A8

M9

H6

H1

P13

BG30

AW30

AU30

BA32

BF33

BA34

AT34

BG34

BJ30

BA30

AT30

BB32

BH33

AW34

AU34

BJ34

BF29

BC30

AU32

BD32

BG32

BC34

AU36

BG36

BH29

BD30

AV32

BE32

BJ32

BD34

AV36

BJ36

P41

B9

H14 C8

J14

C6 G8

M14

E10 G12

AF38

AH51 AH53

8

94

8

94

17

MF-LF

1/16W

402

1%

90.9

R1890

1

2

MF-LF

1/16W

5%

402

33

R1810

1 2

33

402

5% 1/16W MF-LF

R1811

1 2

33

402

5% 1/16W MF-LF

R1812

1 2

402

MF-LF

1/16W

5%

33

R1813

1 2

58 94

48 94

8

17 45

17 37

17 25 42

17 25

17

101

6

17 45

1/16W

10K

MF-LF

4025%

R1853

1 2

10K

5%

1/16W

402

MF-LF

R1854

1 2

10K

MF-LF

402

1/16W

5%

R1855

1 2

402

10K

MF-LF1/16W

5%

R1852

1 2

1/16W

402

MF-LF

10K

5%

R1851

1 2

1/16W

402

MF-LF

10K

5%

R1850

1 2

10K

402

MF-LF1/16W

5%

R1880

1 2

100K

5%

1/16W

402

MF-LF

R1860

1 2

1/16W

10K

MF-LF

4025%

R1870

1 2

10K

MF-LF

402

1/16W

5%

R1871

1 2

10K

402

MF-LF1/16W

5%

R1872

1 2

MF-LF

402

10K

5%

1/16W

R1898

1 2

1/16W

5% 402

MF-LF

10K

R1897

1 2

MF-LF

5%

1/16W

402

10K

R1896

1 2

10K

MF-LF

402

1/16W

5%

R1895

1 2

5%

1/16W

402

MF-LF

10K

R1840

1 2

10K

MF-LF

402

1/16W

5%

R1841

1 2

10K

5%

1/16W

402

MF-LF

R1816

1 2

5%

1/16W

402

MF-LF

10K

R1815

1 2

1/16W

402

51

MF-LF

5%

R1828

1

2

XDP_PCH

402

1/16W MF-LF

5%

51

R1826

1

2

XDP_PCH

5% MF-LF

1/16W 402

51

R1827

1

2

402

XDP_PCH

51

MF-LF

1/16W

5%

R1825

1

2

402

MF-LF1/16W

5%

2.2K

R1899

1 2

PCH SATA/PCIE/CLK/LPC/SPI

SYNC_DATE=08/24/2009

SYNC_MASTER=K17_REF

PP3V3_S0

PCH_SPKR

TP_PCH_SATALED_L

HDA_RST_R_L

NC_SATA_SSD2_R2D_CP

NC_SATA_EXTA_R2D_C_N

PEG_CLKREQ_L

ARB_DETECT

SPI_CS0_R_L

NC_PCIE_PE5_D2RN NC_PCIE_PE5_D2RP NC_PCIE_PE5_R2D_CN

NC_PCIE_PE6_D2RN

PP1V05_S0

PCH_INTRUDER_L

SATA_ODD_D2R_N SATA_ODD_D2R_P

TP_SPI_CS1_L

SPI_MISO

HDA_SDOUT_R

HDA_RST_L

HDA_RST_R_L

HDA_SDOUT

HDA_SDOUT_R

HDA_SYNC

HDA_SYNC_R

HDA_BIT_CLK

HDA_BIT_CLK_R

NC_SATA_C_D2RN

TP_LPC_DREQ0_L

PCH_SML0ALERT_L SML_PCH_0_CLK

SML_PCH_0_DATA

PCH_SML1ALERT_L

PCIE_CLK100M_FW_P

PCIE_CLK100M_FW_N

PCIE_CLK100M_ENET_N

NC_PCIE_PE8_D2RP

NC_PCIE_PE7_R2D_CP

SMBUS_PCH_CLK SMBUS_PCH_DATA

PCH_CLK33M_PCIIN

PCH_CLK25M_XTALIN PCH_CLK25M_XTALOUT

HDA_BIT_CLK_R

NC_SATA_SSD2_D2RP

PCIE_CLK100M_AP_N

PCIE_CLK100M_ENET_P

SMC_WAKE_SCI_L

NC_PCIE_PE6_R2D_CP

NC_PCIE_PE6_D2RP

FW_CLKREQ_L

NC_PCIE_CLK100M_PE4N

NC_PCIE_EXCARD_D2R_P

NC_PCIE_CLK100M_PE5N

NC_SATA_SSD2_R2D_CN

NC_SATA_SSD2_D2RN

NC_PCIE_CLK100M_PEBP

PCH_INTVRMEN_L

NC_PCIE_CLK100M_EXCARD_P

NC_PCIE_PE8_D2RN

BRCRYPT_RESET

MLB_RAM_VENDOR

PCH_CLK100M_SATA_P

PCH_CLK14P3M_REFCLK

MLB_RAM_SIZE

PP1V05_S0

PCH_CLK96M_DOT_P

NC_CLINK_RESET_L

NC_CLINK_DATA

NC_CLINK_CLK

PCH_CLK100M_SATA_N

NC_PCIE_EXCARD_R2D_C_P

NC_PCIE_PE6_R2D_CN

NC_PCIE_PE7_D2RN NC_PCIE_PE7_D2RP NC_PCIE_PE7_R2D_CN

NC_PCIE_PE8_R2D_CP

NC_PCIE_CLK100M_PE4P

NC_PCIE_CLK100M_EXCARD_N

LPC_SERIRQ

SATA_HDD_R2D_C_P

SML_PCH_1_CLK SML_PCH_1_DATA

NC_SATA_EXTA_D2R_N

NC_SATA_D_R2D_CN

PCH_PEB_CLKREQ_L

ENET_CLKREQ_L

PCIE_CLK100M_AP_P

PCH_PE4_CLKREQ_L

NC_PCIE_CLK100M_PEBN

PCH_INTVRMEN_L

NC_HDA_SDIN1 NC_HDA_SDIN2

PCH_CLK32K_RTCX2

PCH_CLK32K_RTCX1

SPI_DESCRIPTOR_OVERRIDE_L ENET_ENERGY_DET

JTAG_PCH_TCK JTAG_PCH_TMS

SATARDRVR_A_EN

PCH_SPKR

HDA_SYNC_R

SATA_ODD_R2D_C_N

NC_SATA_D_R2D_CP

NC_SATA_EXTA_D2R_P

PCH_INTRUDER_L

NC_HDA_SDIN3

LPC_AD<2> LPC_AD<3>

LPC_FRAME_L

SATA_HDD_R2D_C_N

SATA_ODD_R2D_C_P

NC_SATA_C_R2D_CN

NC_SATA_D_D2RN

NC_SATA_EXTA_R2D_C_P

GFX_CLK120M_DPLLSS_P

PCH_CLK96M_DOT_N

GFX_CLK120M_DPLLSS_N

PCIE_CLK100M_CPU_P

FSB_CLK133M_PCH_P

FSB_CLK133M_PCH_N

PCIE_CLK100M_PCH_P

PCIE_CLK100M_PCH_N

PCIE_CLK100M_CPU_N

PEG_CLK100M_P

PEG_CLK100M_N

PEG_CLKREQ_L

NC_SATA_C_D2RP

SATARDRVR_B_EN

SATARDRVR_A_EN

AP_CLKREQ_L

PCH_SML1ALERT_L

MLB_RAM_VENDOR

JTAG_PCH_TDO JTAG_PCH_TCK

JTAG_PCH_TMS

PCH_SRTCRST_L

SATARDRVR_B_EN

AP_CLKREQ_L

BRCRYPT_PWR_EN

NC_PCIE_CLK100M_PE5P

EXCARD_CLKREQ_L

BRCRYPT_RESET

SMC_WAKE_SCI_L

EXCARD_CLKREQ_L

FW_CLKREQ_L

ENET_CLKREQ_L

NC_PCIE_PE5_R2D_CP

PCH_SATAICOMP

NC_SATA_C_R2D_CP

NC_SATA_D_D2RP

TP_LPC_DREQ1_L

PP3V3_S0

LPC_AD<0> LPC_AD<1>

PCIE_FW_R2D_C_P

PCIE_FW_R2D_C_N

NC_PCIE_EXCARD_R2D_C_N

NC_PCIE_EXCARD_D2R_N

PCIE_FW_D2R_P

JTAG_PCH_TDI

NC_PCIE_PE8_R2D_CN

PCH_XCLK_RCOMP

ARB_DETECT

PCH_SML0ALERT_L

BRCRYPT_PWR_EN

PCH_PEB_CLKREQ_L

PCH_PE4_CLKREQ_L

RTC_RESET_L

ENET_ENERGY_DET

SATA_HDD_D2R_P

SATA_HDD_D2R_N

PCIE_FW_D2R_N

PCIE_AP_R2D_C_P

PCIE_AP_R2D_C_N

PCIE_AP_D2R_P

PCIE_AP_D2R_N

PCIE_ENET_R2D_C_P

PCIE_ENET_R2D_C_N

PCIE_ENET_D2R_P

PCIE_ENET_D2R_N

RTC_RESET_L

HDA_SDIN0

PCH_SRTCRST_L

MLB_RAM_SIZE

PP3V42_G3H

SPI_DESCRIPTOR_OVERRIDE_L

PP3V3_S5

JTAG_PCH_TDI JTAG_PCH_TDO TP_JTAG_PCH_TRST_L

PP3V3_S3

SPI_MOSI_R

SPI_CLK_R

PP1V05_S5

18 OF 132

<SCH_NUM>

17 OF 101

6 7

17 18 19 20 21 23 24 25 26

27 28 30 34 37 40 42 46 47 48

50 51 52 54 58 62 63 68 69 72

73 80 83 84 85 87 88 99

17

17 94

8

17 87

17

6

6 7

10 12 13 15 17 18 20 21

23 24 25 26 40 70 73 86

17

17 94

6

17

6

17 94

6

17

6

17

101

17

6 7

10 12 13 15 17 18 20 21

23 24 25 26 40 70 73 86

6

17

6

17

6

17

17 94

6

17

6 6

6

17 25

17 25 42

17 25 33

17

17 25

17

6

17

101

17 45

17

17 25 40

17 37

6

93

6

6 7

17 18 19 20 21 23 24 25

26 27 28 30 34 37 40 42 46 47

48 50

51 52 54 58 62 63 68 69 72 73 80 83 84 85 87 88 99

17 25

6

17

101

17

17 37

17

6 7

21 23 43 45

46 47 48 49 53 64

65 66 73

17 45

6 7

18 19 20 21 23 27 31 35 57

66 71 72 73 83 85 99 6 7 8

20 31 32 33 34 35 36 48 50 53 54 55

72 73 87

101

6 7

71

IN IN

IN

OUT

OUT OUT

IN IN

OUT OUT

OUT OUT OUT OUT

OUT

OUT OUT

OUT

OUT BI

BI BI

IN

OUT OUT

OUT

BI

OUT OUT

OUT

IN

BI

OUT

BI

OUT

IN

FDI_RXN0

DMI3RXN

RI*

BATLOW*/GPIO72

ACPRESENT/GPIO31

PWRBTN*

SUS_PWR_ACK/GPIO30

RSMRST*

LAN_RST*

DRAMPWROK

MEPWROK

PWROK

SYS_PWROK

SYS_RESET*

SLP_M*

SLP_S4*

SLP_S3*

SUSCLK/GPIO62

SLP_S5*/GPIO63

CLKRUN*/GPIO32

SUS_STAT*/GPIO61

WAKE*

DMI_ZCOMP DMI_IRCOMP

FDI_FSYNC1

FDI_FSYNC0

FDI_LSYNC0 FDI_LSYNC1

DMI3TXP

DMI2TXP

DMI0TXP DMI1TXP

DMI3TXN

DMI2TXN

DMI1TXN

DMI0TXN

DMI3RXP

DMI2RXP

DMI0RXP DMI1RXP

FDI_INT

FDI_RXP7

FDI_RXP6

FDI_RXP5

FDI_RXP4

FDI_RXP1 FDI_RXP2 FDI_RXP3

FDI_RXP0

FDI_RXN7

FDI_RXN6

FDI_RXN5

FDI_RXN4

FDI_RXN3

FDI_RXN2

FDI_RXN1

DMI2RXN

DMI1RXN

DMI0RXN

SLP_LAN*

PMSYNCH

TP23

(3 OF 10)

DMI

FDI

SYSTEM POWER

MANAGEMENT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

CRT_IRTN

DAC_IREF

CRT_VSYNC

CRT_HSYNC

CRT_DDC_CLK CRT_DDC_DATA

CRT_RED

CRT_GREEN

CRT_BLUE

DDPD_3N DDPD_3P

DDPD_2P

DDPD_2N

DDPD_1P

DDPD_1N

DDPD_0N DDPD_0P

DDPD_HPD

DDPD_CTRLDATA

DDPD_CTRLCLK

DDPC_3P

DDPC_2P DDPC_3N

DDPC_2N

DDPC_1P

DDPC_1N

DDPC_0N DDPC_0P

DDPC_HPD

DDPC_CTRLDATA

DDPC_CTRLCLK

DDPB_3N

DDPB_2P

DDPB_3P

DDPB_2N

DDPB_1P

DDPB_0P DDPB_1N

DDPB_0N

DDPB_HPD

SDVO_CTRLDATA

SDVO_CTRLCLK

LVDSB_DATA3

LVDSB_DATA2

LVDSB_DATA1

LVDSB_DATA0

LVDSB_DATA3*

LVDSB_DATA2*

LVDSB_CLK

LVDSB_CLK*

LVDSA_DATA3

LVDSA_DATA1 LVDSA_DATA2

LVDSA_DATA3*

LVDSA_DATA1*

LVDSA_DATA0*

LVDSA_CLK

LVDSA_CLK*

LVD_VREFH

LVD_IBG LVD_VBG

L_CTRL_DATA

L_CTRL_CLK

L_DDC_DATA

L_DDC_CLK

L_BKLTCTL

L_BKLTEN L_VDD_EN

LVD_VREFL

SDVO_TVCLKINN SDVO_TVCLKINP

SDVO_STALLN SDVO_STALLP

SDVO_INTN SDVO_INTP

DDPB_AUXP

DDPB_AUXN

DDPC_AUXN DDPC_AUXP

DDPD_AUXN DDPD_AUXP

LVDSB_DATA1*

LVDSB_DATA0*

LVDSA_DATA0

LVDSA_DATA2*

DIGITAL DISPLAY INTERFACE

CRT

LVDS

(4 OF 10)

OUT

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

(IPU)

(IPD)

(IPU)

(IPD)

(IPU)

(IPD)

0.5% recommended, Intel okay with 5% when CRTDAC not used.

9

91

9

91

9

91

9

91

9

91

9

91

9

91

9

91

9

91

9

91

9

91

9

91

9

91

9

91

9

91

9

91

9

91

9

91

9

91

9

91

9

91

9

91

87 93

6 8

93

6 8

93

87 93

8

93

87 93

8

93

87 93

8

93

87 93

8

93

8

87

8

87

6 8

84

2.37K

1%

402

MF-LF

1/16W

R1950

1

2

8

84 93

8

84 93

8

84

8

80 84

8

80 84

8

5% 1/16W MF-LF 402

1K

R1951

1

2

49.9

MF-LF

1/16W

1%

402

R1900

1

2

6

18 27 33

6

18 45 47

46 94

45 46

31 43 45 46 72 73

6

31 45 73 85

10 91

18

10 31 91

18 45

25 45

45 46 73

18 45

27

6

27 45

OMIT

FCBGA

IBEX_PEAK_M

U1800

P7

A6

Y1

BC24

BD24

BE22

BD22

BJ22

BG22

BF21

BH21

AW20

BA20

BD20

BC20

BJ20

BG20

BE18

BD18

BF25

BH25

D9

BF13 BH13

BJ14

BJ12 BG14

BA18 BH17 BD16 BJ16 BA16 BE14 BA14 BC12

BB18 BF17 BC16 BG16 AW16 BD14 BB14 BD12

A10

K5

BJ10

P5

B17

F14

C16

F6

K8

P12

H7

E4

M1

P8

F3

M6

T6

N2

J12

9

91

9

91

9

91

9

91

9

91

9

91

9

91

9

91

9

91

9

91

9

91

9

91

9

91

9

91

9

91

OMIT

IBEX_PEAK_M

FCBGA

U1800

AA52

V51 V53

AB53

Y53

AB51

AD53

Y51

AD48

BD42 BC42 BJ42 BG42 BB40 BA40 AW38 BA38

BG44 BJ44 AU38

BE40 BD40 BF41 BH41 BD38 BC38 BB36 BA36

BE44 BD44

Y49 AB49

AV40

BJ40 BG40 BJ38 BG38 BF37 BH37 BE36 BD36

BC46 BD46

U50 U52

AT38

Y48

T48

AB46

V48

AB48

Y45

T47

AP39 AP41

AT43 AT42

AV51

AV53

BB48

BB47

BA50

BA52

AY49

AY48

AV48

AV47

AP47

AP48

AY51

AY53

AT48

AT49

AU50

AU52

AT51

AT53

T51 T53

BF45 BH45

BJ48 BG48

BJ46 BG46

6

18 45 47

MF-LF

402

10K

1%

1/16W

R1905

1

2

5%

MF-LF

1/16W

402

10K

R1920

1

2

10K

402

1/16W MF-LF

5%

R1921

1

2

5%

MF-LF

1/16W

402

10K

R1930

1

2

10K

402

1/16W MF-LF

5%

R1931

1

2

5%

MF-LF

1/16W

402

10K

R1925

1

2

5% MF-LF

1/16W 402

10K

R1906

1

2

SYNC_DATE=06/15/2009

SYNC_MASTER=K17_REF

PCH DMI/FDI/Graphics

PCH_DAC_IREF

NC_LVDS_IG_B_DATAP<3>

LVDS_IG_B_DATA_P<2>

FDI_DATA_P<3>

FDI_DATA_N<7>

FDI_FSYNC<0> FDI_FSYNC<1>

NC_SDVO_TVCLKINN

LVDS_IG_A_DATA_P<1>

FDI_LSYNC<1>

PM_SYNC

NC_DP_IG_C_AUXN

NC_DP_IG_C_CTRL_DATA

NC_DP_IG_C_CTRL_CLK

DP_IG_B_ML_P<3>

DP_IG_B_ML_N<3>

NC_LVDS_IG_B_DATAN<3>

PM_SLP_S3_L

PP3V3_S5 PP1V05_S0

DP_IG_B_ML_N<1>

NC_DP_IG_C_MLP<2>

NC_SDVO_STALLN NC_SDVO_STALLP

NC_CRT_IG_HSYNC

NC_CRT_IG_DDC_DATA

NC_CRT_IG_DDC_CLK

NC_CRT_IG_GREEN

NC_CRT_IG_BLUE

LVDS_IG_B_DATA_P<1>

LVDS_IG_B_DATA_P<0>

LVDS_IG_B_DATA_N<1> LVDS_IG_B_DATA_N<2>

LVDS_IG_B_DATA_N<0>

NC_LVDS_IG_A_DATAP<3>

TP_LVDS_IG_B_CLKN

LVDS_IG_A_DATA_N<2>

LVDS_IG_A_DATA_N<0>

LVDS_IG_A_CLK_P

LVDS_IG_A_CLK_N

NC_DP_IG_D_AUXP

NC_DP_IG_D_AUXN

NC_DP_IG_C_AUXP

DP_IG_AUX_CH_N DP_IG_AUX_CH_P

NC_SDVO_INTP

NC_SDVO_INTN

LVDS_IG_PANEL_PWR

LVDS_IG_DDC_DATA NC_LVDS_IG_CTRL_CLK

NC_LVDS_IG_CTRL_DATA

NC_PCH_LVDS_VBG

DP_IG_DDC_CLK DP_IG_DDC_DATA

DP_IG_HPD DP_IG_B_ML_N<0>

DP_IG_B_ML_P<0>

DP_IG_B_ML_P<2>

NC_DP_IG_C_MLP<0>

NC_DP_IG_C_MLN<0>

NC_DP_IG_C_MLN<1> NC_DP_IG_C_MLP<1> NC_DP_IG_C_MLN<2>

NC_DP_IG_D_CTRL_CLK NC_DP_IG_D_CTRL_DATA

NC_DP_IG_D_HPD

NC_DP_IG_D_MLN<1>

NC_DP_IG_D_MLN<2> NC_DP_IG_D_MLP<2>

NC_DP_IG_D_MLP<3>

NC_DP_IG_D_MLN<3>

TP_PM_SLP_DSW_L

FDI_DATA_N<1>

FDI_DATA_N<4>

FDI_DATA_N<6>

FDI_DATA_P<5>

FDI_DATA_P<7>

FDI_INT

TP_PM_SLP_M_L

FDI_DATA_N<0>

NC_CRT_IG_VSYNC

LPC_PWRDWN_L

MAKE_BASE=TRUE

LPC_PWRDWN_L

PCH_LVDS_IBG

PM_BATLOW_L

SMC_ADAPTER_EN

PM_SUS_PWR_ACK PM_PWRBTN_L

PM_RSMRST_L

PM_MEM_PWRGD

PM_SYSRST_L

DMI_S2N_P<3>

DMI_S2N_P<2>

DMI_S2N_N<3>

DMI_S2N_N<2>

DMI_S2N_N<0>

DMI_N2S_P<2>

DMI_N2S_P<1>

DMI_N2S_N<3>

DMI_N2S_N<2>

DMI_N2S_N<0> DMI_N2S_N<1>

TP_SLP_LAN_L

FDI_LSYNC<0>

PM_CLKRUN_L

PCIE_WAKE_L

FDI_DATA_P<2>

FDI_DATA_P<0>

DMI_N2S_P<0>

DMI_N2S_P<3>

FDI_DATA_N<5>

FDI_DATA_P<4>

FDI_DATA_P<6>

PM_CLK32K_SUSCLK

PM_SLP_S4_L

PM_SLP_S5_L

NC_CRT_IG_RED

PM_CLKRUN_L

PM_SUS_PWR_ACK

PP3V3_S0

PM_BATLOW_L PCIE_WAKE_L

PP3V3_S5

PM_RSMRST_L

PM_PCH_PWRGD

PCH_LAN_RST_L

NC_DP_IG_D_MLP<1>

DMI_S2N_P<1>

DMI_S2N_N<1>

LVDS_IG_DDC_CLK

PCH_RI_L

TP_LVDS_IG_BKL_PWM

NC_SDVO_TVCLKINP

NC_DP_IG_D_MLN<0> NC_DP_IG_D_MLP<0>

DP_IG_B_ML_P<1>

LVDS_IG_A_DATA_P<0>

NC_LVDS_IG_A_DATAN<3>

FDI_DATA_P<1>

FDI_DATA_N<3>

FDI_DATA_N<2>

NC_DP_IG_C_MLP<3>

NC_DP_IG_C_MLN<3>

TP_LVDS_IG_B_CLKP

NC_DP_IG_C_HPD

LVDS_IG_A_DATA_N<1>

LVDS_IG_BKL_ON

DP_IG_B_ML_N<2>

LVDS_IG_A_DATA_P<2>

DMI_S2N_P<0>

PCH_DMI_COMP

19 OF 132

<SCH_NUM>

18 OF 101

6

6 7

17 18 19 20 21 23 27 31 35

57 66 71 72 73 83 85 99 6 7

10 12 13 15 17 20 21 23 24

25 26 40 70 73 86

6

18 45 47

6

18 45 47

18

6 7

17 19 20 21 23 24 25 26

27 28 30 34 37 40 42 46 47 48

50 51 52 54 58 62 63 68 69 72

73 80 83 84 85 87 88 99

18 45

6

18 27 33

6 7

17 18 19 20 21 23 27 31

35 57 66 71 72 73 83 85 99

18 45

6

BI

OUT OUT

OUT

IN

OC7*/GPIO14

OC6*/GPIO10

OC5*/GPIO9

OC4*/GPIO43

OC3*/GPIO42

OC1*/GPIO40

OC0*/GPIO59

USBRBIAS

USBRBIAS*

USBP13N

USBP12N

USBP11N

USBP10N

USBP9N

USBP8N

USBP7N

USBP6N

USBP5N

USBP4N

USBP3N

USBP2N

USBP1N

USBP0N

USBP13P

USBP12P

USBP11P

USBP10P

USBP8P

USBP9P

USBP7P

USBP6P

USBP5P

USBP4P

USBP3P

USBP2P

USBP1P

USBP0P

AD2

NV_WE_CK1*

NV_WE_CK0*

NV_WR1_RE*

NV_RB*

NV_WR0_RE*

NV_RCOMP

NV_CLE

NV_ALE

NV_DQ15/NV_IO15

NV_DQ13/NV_IO13 NV_DQ14/NV_IO14

NV_DQ10/NV_IO10 NV_DQ11/NV_IO11 NV_DQ12/NV_IO12

NV_DQ8/NV_IO8 NV_DQ9/NV_IO9

NV_DQ7/NV_IO7

NV_DQ6/NV_IO6

NV_DQ5/NV_IO5

NV_DQ3/NV_IO3 NV_DQ4/NV_IO4

NV_DQ1/NV_IO1 NV_DQ2/NV_IO2

NV_DQ0/NV_IO0

NV_DQS0 NV_DQS1

NV_CE2* NV_CE3*

NV_CE1*

NV_CE0*

AD9

AD3

AD20

AD28 AD29

SERR* PERR*

GNT1*/GPIO51

REQ1*/GPIO50

PIRQC* PIRQD*

REQ0*

AD30

AD21 AD22

PIRQG*/GPIO4 PIRQH*/GPIO5

PCIRST*

AD0 AD1

AD4 AD5 AD6 AD7 AD8

AD10 AD11 AD12 AD13 AD14

AD24 AD25 AD26

CLKOUT_PCI2

C/BE0*

C/BE2* C/BE3*

DEVSEL* FRAME*

GNT0*

GNT2*/GPIO53 GNT3*/GPIO55

IRDY* PAR

PIRQA* PIRQB*

PIRQE*/GPIO2 PIRQF*/GPIO3

PLOCK*

PME*

REQ2*/GPIO52 REQ3*/GPIO54

STOP* TRDY*

AD15 AD16 AD17 AD18 AD19

AD27

AD31

C/BE1*

AD23

OC2*/GPIO41

PLTRST*

CLKOUT_PCI1

CLKOUT_PCI3

CLKOUT_PCI0

CLKOUT_PCI4

(5 OF 10)

USB

PCI

NVRAM

OUT

OUT OUT

IN IN IN

IN

BI BI

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

External Hub 2

External Hub 1

T57

(IPU)

NOTE: Internal pull-downs on all USB pins

EHCI1

(DPD)

(IPU)

(DPD)

EHCI2

(IPD)

36 93

35 93

10K

5%

MF-LF

1/16W

402

R2060

1

2

10K

5%

MF-LF

1/16W

402

R2062

1

2

5% 1/16W

402

10K

MF-LF

R2061

1

2

10K

402

1/16W MF-LF

5%

R2064

1

2

1%

22.6

402

1/16W MF-LF

R2070

1

2

27 94

27

27 31 40

19 25

4025%

1/16W MF-LF

10K

R2024

1 2

402

MF-LF1/16W

5%

10K

R2023

1 2

5%

402

1/16W MF-LF

10K

R2022

1 2

1/16W

402

MF-LF

5%

10K

R2020

1 2

1/16W

402

MF-LF

5%

10K

R2021

1 2

MF-LF1/16W

5% 402

10K

R2027

1 2

5%

10K

MF-LF1/16W

402

R2026

1 2

5%

1/16W MF-LF

402

10K

R2010

1 2

5%

1/16W MF-LF

402

10K

R2011

1 2

5%

MF-LF1/16W

10K

402

R2012

1 2

402

1/16W5%MF-LF

10K

R2013

1 2

5%

1/16W MF-LF

402

10K

R2014

1 2

FCBGA

OMIT

IBEX_PEAK_M

U1800

H40 N34

E40 C40 M48 M45 F53 M40 M43 J36 K48 F40

C44

C42 K46 M51 J52 K51 L34 F42 J40 G46 F44

A38

M47 H36

C36 J34 A40 D45 E36 H48

J50 G42 H47 G34

N52 P53 P46 P51 P48

F46 C46

F48 K45 F36 H53

A42

BD3

AY9 BD1 AP15 BD8

AY6

AP7

BD6 BB7 BC8 BJ8 BJ6 BG6

AP6 AT6 AT9 BB1 AV6 BB3 BA4 BE4 BB6

AV9 BG8

AV7

AU2

AV11 BF5

AY8 AY5

N16 J16 F16 L16 E14 G16 F12 T15

H44

K6

E50

G38 H51 B37 A44

B41 K53 A36 A48

D49

D5

M7

F51 A46 B45 M53

E44

D41 C48

H18 J18

A22 C22 G24 H24 L24 M24 A24 C24

A18 C18 N20 P20 J20 L20 F20 G20 A20 C20 M22 N22 B21 D21 H22 J22 E22 F22

D25

B25

27

10K

402

1/16W MF-LF

5%

R2066

1

2

10K

5%

MF-LF

1/16W

402

R2065

1

2

402

1/16W MF-LF

10K

5%

R2025

1 2

19 87

5%

1/16W

402

MF-LF

10K

R2030

1 2

5%

1/16W

402

MF-LF

10K

R2031

1 2

5%

1/16W

402

MF-LF

10K

R2032

1 2

5%

1/16W MF-LF

10K

402

R2036

1 2

5%

1/16W

402

MF-LF

10K

R2035

1 2

10K

MF-LF

402

1/16W

5%

R2037

1 2

19 63

19

19 63

5%

1/16W

402

MF-LF

10K

R2038

1 2

10K

MF-LF

402

1/16W

5%

R2081

1 2

5%

1/16W

402

MF-LF

10K

R2080

1 2

19 25

93

101

93

101

SYNC_MASTER=K18_MLB

PCH PCI/FlashCache/USB

SYNC_DATE=10/07/2009

JTAG_GMUX_TDI

NC_PCI_AD<3>

NC_PCH_NV_RCOMP

PCH_GPIO10

PCH_GPIO9

PCH_GPIO43

PCH_GPIO42

USB_HUB_SOFT_RESET_L PCH_GPIO41

PCH_GPIO59

NC_USB_12N

NC_USB_9N

NC_NV_DQ<10> NC_NV_DQ<11> NC_NV_DQ<12> NC_NV_DQ<13> NC_NV_DQ<14>

NC_NV_DQ<7> NC_NV_DQ<8>

NC_NV_DQ<15>

NC_USB_7P

NC_NV_DQ<5>

NC_NV_DQ<9>

USB_HUB2_UP_P

USB_HUB2_UP_N

NC_PCI_PME_L

PCI_REQ3_L

JTAG_GMUX_TDI

NC_PCI_GNT3_L

PCI_DEVSEL_L PCI_FRAME_L

MIKEY_MIC_LOAD_DET

PCI_PERR_L

PCI_STOP_L

LPC_CLK33M_LPCPLUS_R

PCI_TRDY_L

NC_PCI_AD<2>

NC_NV_WE_CK_L<0>

NC_NV_CLE

NC_NV_ALE

NC_NV_DQ<6>

NC_NV_DQ<3> NC_NV_DQ<4>

NC_NV_DQ<1> NC_NV_DQ<2>

NC_NV_DQ<0>

NC_NV_DQS<0> NC_NV_DQS<1>

NC_NV_CE_L<2> NC_NV_CE_L<3>

NC_NV_CE_L<1>

NC_NV_CE_L<0>

NC_PCI_AD<9>

NC_PCI_AD<28>

NC_PCI_AD<21> NC_PCI_AD<22>

NC_PCI_RESET_L

NC_PCI_AD<0> NC_PCI_AD<1>

NC_PCI_AD<4> NC_PCI_AD<5> NC_PCI_AD<6> NC_PCI_AD<7> NC_PCI_AD<8>

NC_PCI_AD<10> NC_PCI_AD<11>

NC_PCI_AD<13> NC_PCI_AD<14>

NC_PCI_AD<24> NC_PCI_AD<25> NC_PCI_AD<26>

LPC_CLK33M_GMUX_R

NC_PCI_C_BE_L<2> NC_PCI_C_BE_L<3>

NC_PCI_GNT0_L

NC_PCI_GNT2_L

NC_PCI_PAR

PCH_GPIO2

NC_PCI_AD<15> NC_PCI_AD<16>

NC_PCI_AD<18> NC_PCI_AD<19>

NC_PCI_AD<31>

NC_PCI_C_BE_L<1>

NC_PCI_AD<23>

NC_PCI_CLK33M_OUT3

PM_LATRIGGER_L

JTAG_GMUX_TMS

AUD_I2C_INT_L

AUD_IP_PERIPHERAL_DET MIKEY_MIC_LOAD_DET

PCI_INTB_L

PCI_INTA_L

PCI_REQ0_L

PCI_INTD_L

PCI_SERR_L

PCI_IRDY_L

PLT_RESET_L LPC_CLK33M_SMC_R

PCH_CLK33M_PCIOUT

PCI_PLOCK_L

PM_LATRIGGER_L

PCH_GPIO59

PP3V3_S5

NC_PCI_AD<12>

AUD_I2C_INT_L

JTAG_GMUX_TMS

PCH_GPIO2

PCI_REQ3_L

AUD_IP_PERIPHERAL_DET

NC_PCI_GNT1_L

NC_PCI_C_BE_L<0>

NC_PCI_AD<29> NC_PCI_AD<30>

NC_PCI_AD<20>

NC_PCI_AD<17>

PP3V3_S5

USB_BRCRYPT_N USB_BRCRYPT_P

NC_USB_6P

NC_USB_10P

NC_USB_12P

NC_USB_10N

NC_USB_6N

NC_USB_4N

NC_USB_3N

NC_USB_7N

PCH_USB_RBIAS

NC_USB_13N

NC_USB_5P

NC_USB_5N

NC_USB_4P

NC_USB_3P

NC_USB_1P

NC_USB_13P

NC_USB_11N

NC_PCI_AD<27>

NC_USB_9P

NC_USB_11P

PP3V3_S0

PCI_INTC_L

NC_NV_WE_CK_L<1>

NC_NV_RB_L

NC_USB_1N

USB_HUB1_UP_P

USB_HUB1_UP_N

NC_NV_WR_RE_L<1>

NC_NV_WR_RE_L<0>

20 OF 132

<SCH_NUM>

19 OF 101

19 87

6

25 46

25

25 35

25

6

19

6

19

6

27

6

19

6

19 25

6 7

17 18 19 20 21 23 27 31

35 57 66 71 72 73 83 85 99

6

19 63

19 87

19

19 63

6

6 7

17 18 19 20 21 23 27

31 35 57 66 71 72 73 83

85 99

93

6

6 7

17 18 20 21 23 24 25 26

27 28 30 34 37 40 42 46 47 48

50 51 52 54 58 62 63 68 69 72

73 80 83 84 85 87 88 99

6

IN

OUT OUT

BI

OUT

IN

OUT

NC_5

NC_3 NC_4

NC_1 NC_2

TP8

TP19

TP18

TP17

TP15

TP16

TP14

TP13

TP12

TP11

TP9

TP10

TP6

TP7

TP4

TP5

TP2

TP1

INIT3_3V*

TP24

VSS_NCTF31

VSS_NCTF30

VSS_NCTF28 VSS_NCTF29

VSS_NCTF25 VSS_NCTF26 VSS_NCTF27

VSS_NCTF24

VSS_NCTF23

VSS_NCTF22

VSS_NCTF21

VSS_NCTF20

VSS_NCTF19

VSS_NCTF18

VSS_NCTF17

VSS_NCTF16

VSS_NCTF15

VSS_NCTF14

VSS_NCTF13

VSS_NCTF12

VSS_NCTF10 VSS_NCTF11

VSS_NCTF8 VSS_NCTF9

VSS_NCTF7

VSS_NCTF6

VSS_NCTF5

VSS_NCTF2 VSS_NCTF3 VSS_NCTF4

VSS_NCTF1

GPIO57

SATA5GP/GPIO49

SDATAOUT1/GPIO48

PCIECLKRQ7*/GPIO46

SDATAOUT0/GPIO39

PCIECLKRQ6*/GPIO45

SLOAD/GPIO38

SATA3GP/GPIO37

SATA2GP/GPIO36

SATACLKREQ*/GPIO35

STP_PCI*/GPIO34

GPIO27

GPIO28

MEM_LED/GPIO24

TACH0/GPIO17

SCLOCK/GPIO22

SATA4GP/GPIO16

GPIO15

LAN_PHY_PWR_CTRL/GPIO12

GPIO8

TACH3/GPIO7

TACH1/GPIO1

TACH2/GPIO6

BMBUSY*/GPIO0

THRMTRIP*

PROCPWRGD

RCIN*

PECI

CLKOUT_BCLK0_P/CLKOUT_PCIE8P

CLKOUT_BCLK0_N/CLKOUT_PCIE8N

A20GATE

CLKOUT_PCIE7N

CLKOUT_PCIE6P

CLKOUT_PCIE6N

TP3

CLKOUT_PCIE7P

(6 OF 10)

CPU

NCTF

RSVD

GPIO

MISC

IN

BI

OUT

BI

OUT

IN

OUT

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

(IPD)

(IPU*)

IPU* = Only on TACH function.

(IPU)

(XCKPLL_MON1_N)

(XCKPLL_MON1_P)

(DPL_B_MON1_N)

(DPL_B_MON1_P)

(DPL_B_MON2_N)

(SATA_OB_ANA)

(DPL_B_MON2_P)

(IPU*)

(IPD)

(IPU*)

(IPU)

20 45

10 91

10 25 91

402

1/16W MF-LF

5%

56

R2161

1 2

10 46 91

MF-LF

1/16W 402

5%

56

R2160

1

2

MF-LF

1/16W

5%

402

10K

R2155

1

2

20

IBEX_PEAK_M

FCBGA

OMIT

U1800

U2

Y3

AM3 AM1

AH45 AH46

AF48 AF47

T7

AB12

V13

F8

F10

P6

K9

H10

AB45 AB38 AB42 AB41 T39

H3

F1

BG10

BE10

T1

AB7

AB13

AA2

AA4

V6

Y7

P3

AB6

V3

M11

F38

C38

D37

J32

BD10

BA22

N18

AJ24

AK41

AK42

M32

N32

M30

N30

H12

AA23

AW22

C10

BB22

AY45

AY46

AV43

AV45

AF13

M18

A4

A49

BE1

BE53

BF1

BF53

BH1

BH2 BH52 BH53

BJ1

BJ2

A5

BJ4 BJ49

BJ5 BJ50 BJ52 BJ53

D1 D2

D53

E1

A50

E53

A52

A53

B2

B4 B52 B53

402

5% 1/16W MF-LF

10K

R2150

1

2

MF-LF

402

1/16W

5%

R2116

1 2

10K

2.2K

MF-LF1/16W

5%

402

21

R2115

10K

MF-LF

402

1/16W

R2113

1 2

5%

20K

4025%

R2112

1 2

MF-LF1/16W

10K

MF-LF

402

1/16W

R2114

1 2

5%

1/16W

402

10K

R2110

1 2

MF-LF

5%

1/16W

402

10K

R2111

1 2

MF-LF

20 25 45 46

8

20 40

20 87

6

20 47

20 25 63

20 42

6

20 47 57

20 25

20 40

20 33 73

20 73

20 25 87

20 87

25 31

10K

MF-LF

402

1/16W

5%

R2121

1 2

10K

MF-LF

402

1/16W

5%

R2120

1 2

4025%

1/16W MF-LF

10K

R2122

1 2

402

1/16W5%MF-LF

10K

R2123

1 2

MF-LF

5%

1/16W

402

10K

R2124

1 2

20 25 34

MF-LF

402

1/16W

5%

10K

R2130

1 2

10K

MF-LF

402

1/16W

5%

R2131

1 2

10K

MF-LF

402

1/16W

5%

R2133

1 2

MF-LF

10K

402

1/16W

5%

R2132

1 2

10K

MF-LF

402

1/16W

5%

R2134

1 2

1/16W

10K

MF-LF

4025%

R2135

1 2

5%

1/16W

402

MF-LF

10K

R2136

1 2

1/16W

10K

MF-LF

4025%

R2137

1 2

1/16W MF-LF

4025%

10K

R2138

1 2

1/16W

100K

MF-LF

4025%

R2139

1 2

20 37

SYNC_DATE=06/15/2009

SYNC_MASTER=K17_REF

PCH MISC

SMC_IG_THROTTLE_L

PP3V3_S0

PCH_FCIM_EN_L

SMC_RUNTIME_SCI_L

GMUX_INT

ENET_LOW_PWR

PCH_VSS_NCTF<5>

PP3V3_S3

PM_THRMTRIP_L

ENET_LOW_PWR

SMC_IG_THROTTLE_L FW_PLUG_DET_L

MXM_GOOD

WOL_EN AP_PWR_EN FW_PWR_EN

ME_TEMP_ALERT_L

JTAG_GMUX_TCK

ODD_PWR_EN_L

FW_PWR_EN

SDCARD_RESET

LPCPLUS_GPIO

ISOLATE_CPU_MEM_L

JTAG_GMUX_TDO

JTAG_GMUX_TCK

WOL_EN AP_PWR_EN

ME_TEMP_ALERT_L

PCH_GPIO24

ODD_PWR_EN_L

AUD_IPHS_SWITCH_EN

PCH_FCIM_EN_L

NC_PCIE_CLK100M_PE7P

NC_PCIE_CLK100M_PE6N NC_PCIE_CLK100M_PE6P

NC_PCIE_CLK100M_PE7N

FSB_CLK133M_CPU_N FSB_CLK133M_CPU_P

CPU_PECI

PCH_GPIO15

PCH_VRM_EN

TP_PCH_STP_PCI_L

PCH_GPIO39

TP_PCH_INIT3V3_L

NC_PCH_TP9

NC_PCH_TP11

NC_PCH_TP14

NC_PCH_TP8

PCH_A20GATE

PP3V3_S0

PP1V05_S0

PCH_RCIN_L

FW_PLUG_DET_L

SDCARD_RESET

JTAG_GMUX_TDO PCH_GPIO39

SPIROM_USE_MLB

PCH_GPIO24 PCH_VRM_EN

PCH_VSS_NCTF<22>

PCH_VSS_NCTF<19>

SPIROM_USE_MLB

PCH_VSS_NCTF<21>

PCH_VSS_NCTF<25>

PCH_VSS_NCTF<29>

PCH_VSS_NCTF<17>

PCH_VSS_NCTF<12>

PCH_VSS_NCTF<11>

PCH_VSS_NCTF<9>

TP_PCH_VSS_NCTF<7>

PCH_VSS_NCTF<2>

PCH_VSS_NCTF<1>

NC_PCH_SST

NC_PCH_NC4

NC_PCH_TP18

NC_PCH_NC5

NC_PCH_NC3

NC_PCH_TP17

NC_PCH_TP12

NC_PCH_TP13

NC_PCH_TP15

NC_PCH_TP16

NC_PCH_TP10

NC_PCH_TP7

NC_PCH_TP6

NC_PCH_TP5

NC_PCH_TP1

NC_PCH_TP4

NC_PCH_TP3

NC_PCH_TP2

PCH_THRMTRIP_L

NC_PCH_NC2

NC_PCH_NC1

NC_PCH_TP19

PCH_GPIO15

CPU_PWRGD

SMC_RUNTIME_SCI_L

GMUX_INT

PCH_VSS_NCTF<15>

PCH_VSS_NCTF<27>

LPCPLUS_GPIO

AUD_IPHS_SWITCH_EN

PP3V3_S5

21 OF 132

<SCH_NUM>

20 OF 101

20 25 45 46

6 7

17 18 19 20 21 23 24 25 26

27 28 30 34 37 40 42 46 47 48

50 51 52 54 58 62 63 68 69 72

73 80 83 84 85 87 88 99

20

20 45

20 87

20 37

6

94

6 7 8

17 31 32 33 34 35 36 48 50 53 54 55

72 73 87

101

20

20 73

20 33 73

20 40

20 25

20 25 87

20 42

20

6

20

6

6 7

17 18 19 20 21 23 24 25 26

27 28 30 34 37 40 42 46 47 48

50 51 52 54 58 62 63 68 69 72

73 80 83 84 85 87 88 99

6 7

10 12 13 15 17 18 21 23 24

25 26 40 70 73 86

8

20 40

20 25 34

20 87

20

6

20 47 57

20

94

6

94

6

94

6

94

6

94

6

94

6

94

6

94

6

94

6

94

6

94

6

20

6

94

6

94

6

20 47

20 25 63

6 7

17 18 19 21 23 27 31 35 57 66 71 72 73 83 85 99

VCCIO24

VCCIO55

VCCIO54

VCCIO53

VCCIO52

VCCIO51

VCCIO50

VCCIO49

VCCIO48

VCCIO47

VCCIO46

VCCIO45

VCCIO44

VCCIO43

VCCIO42

VCCIO41

VCCIO40

VCCIO39

VCCIO38

VCCIO37

VCCIO36

VCCIO35

VCCIO34

VCCIO33

VCCIO32

VCCIO31

VCCIO29

VCCIO28

VCCIO27

VCCIO26

VCCIO25

VCCVRM2

VCCFDIPLL

VCCAPLLEXP

VCCALVDS

VCCADAC1 VCCADAC2

VSSA_DAC1 VSSA_DAC2

VCCTX_LVDS1 VCCTX_LVDS2 VCCTX_LVDS3 VCCTX_LVDS4

VCC3_3_2

VCC3_3_4

VCC3_3_3

VCCPNAND1 VCCPNAND2 VCCPNAND3 VCCPNAND4 VCCPNAND5 VCCPNAND6 VCCPNAND7 VCCPNAND8 VCCPNAND9

VCCME3_3_1 VCCME3_3_2 VCCME3_3_3 VCCME3_3_4

VCC3_3_1

VCCVRM1

VSSA_LVDS

VCCCORE1 VCCCORE2 VCCCORE3 VCCCORE4 VCCCORE5 VCCCORE6 VCCCORE7 VCCCORE8 VCCCORE9 VCCCORE10 VCCCORE11 VCCCORE12 VCCCORE13 VCCCORE14 VCCCORE15

VCCDMI1 VCCDMI2

VCCIO30

VCCIO1

CRT

PCI-E*

NAND / SPI

HVCMOS

(7 OF 10)

VCC CORE

LVDS

FDI

DMI

VCCSUS3_3_23

VCCSUS3_3_28

VCCSUS3_3_27

VCCSUS3_3_26

VCCSUS3_3_25

VCCSUS3_3_24

VCCSUS3_3_22

VCCSUS3_3_21

VCCSUS3_3_20

VCCSUS3_3_19

VCCSUS3_3_18

VCCSUS3_3_17

VCCSUS3_3_16

VCCSUS3_3_15

VCCSUS3_3_14

VCCSUS3_3_13

VCCSUS3_3_12

VCCSUS3_3_11

VCCSUS3_3_10

VCCSUS3_3_9

VCCSUS3_3_8

VCCSUS3_3_7

VCCSUS3_3_6

VCCSUS3_3_5

VCCSUS3_3_4

VCCSUS3_3_3

VCCSUS3_3_2

VCCSUS3_3_1

VCCSUS3_3_29

VCCME3

V5REF

V5REF_SUS

VCC3_3_8 VCC3_3_9

VCC3_3_11

VCC3_3_10

VCC3_3_12 VCC3_3_13

VCC3_3_14

VCCSATAPLL1 VCCSATAPLL2

VCCVRM4

VCCME13 VCCME14 VCCME15 VCCME16

VCCSUSHDA

VCCRTC

V_CPU_IO1 V_CPU_IO2

DCPSST

DCPSUS

VCCSUS3_3_30

VCCSUS3_3_32

VCC3_3_6 VCC3_3_7

VCCACLK1 VCCACLK2

VCCLAN1 VCCLAN2

VCCME1

DCPSUSBYP

VCCME2

VCCME6

VCCME5

VCCME4

VCCME7 VCCME8 VCCME9

VCCME11

VCCME10

DCPRTC

VCCME12

VCCVRM3

VCCADPLLA1 VCCADPLLA2

VCCADPLLB2

VCCADPLLB1

VCC3_3_5

VCCSUS3_3_31

VCCIO10 VCCIO11 VCCIO12 VCCIO13 VCCIO14 VCCIO15 VCCIO16 VCCIO17 VCCIO18 VCCIO19 VCCIO20

VCCIO9

VCCIO56VCCIO21 VCCIO22 VCCIO23

VCCIO2 VCCIO3 VCCIO4

VCCIO5 VCCIO6 VCCIO7 VCCIO8

PCI/GPIO/LPC

USB

CPU

RTC

HDA

(10 OF 10)

CLOCK AND MISCELLANEOUS

PCI/GPIO/LPC

SATA

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

Current numbers from Ibex Peak EDS Spec Update rev 0.71, doc #386904 (Table 8-3). Pre-Silicon Mobile Estimates.

163 mA S0, 65 mA S3-S5

1 (IPU) 0 (IPD) 1.8V Float

0 X 1.05V 1.05V

PLLs = VccAClk, VccSATAPLL, VccAPLLEXP & VccFDIPLL

(VCCME[1-16] total)

(VCC3_3[1-14] total)

3062 mA (VCCIO[1-56] total)

1432 mA

357 mA (VCC3_3[1-14] total)

1 (IPU) 1 1.5V Float

Note: 1.5V option consumes more current than 1.8V

(VCC3_3[1-14] total)

3062 mA (VCCIO[1-56] total)

357 mA (VCC3_3[1-14] total)

NOTE: Connect to 3.3V if NAND not used.

156 mA (1.8V)

< 1 mA

85 mA S0, 22 mA M-on

69 mA

3062 mA (VCCIO[1-56] total)

5 mA (if GPIO27 is low)

40 mA (if GPIO27 is low)

3062 mA (VCCIO[1-56] total)

1849 mA S0, 700 mA M-on

6 mA S0, < 1 mA S3-S5

2 mA S0-S5, ~6 uA G3

357 mA

163 mA S0, 65 mA S3-S5

1849 mA S0, 700 mA M-on

320 mA S0, 67 mA M-on

58 mA (1.05V)

61 mA (1.1V)

(VCCSUS3_3[1-32] total)

357 mA

< 1 mA S0-S5

< 1 mA

(VCCME[1-16] total)

Verify S0 okay

52 mA

59 mA

(VCCIO[1-56] total)

3062 mA

PCH output, for decoupling only

69 mA

PCH output, for decoupling only

357 mA (VCC3_3[1-14] total)

164 mA (VCCVRM[1-4] total)

3062 mA (VCCIO[1-56] total)

68 mA

164 mA (VCCVRM[1-4] total)

(VCCSUS3_3[1-32] total)

PCH output, for decoupling only

< 1 mA

31 mA (if GPIO27 is low)

GPIO27 HDA_SYNC VccVRM PLLs

115 mA

3062 mA

(VCCIO[1-56] total)

IBEX_PEAK_M

FCBGA

OMIT

U1800

AN35

AB34 AB35 AD35

AE50 AE52

AH38

BJ24

AB24

AH26 AH28 AH30 AH31 AJ30 AJ31

AB26 AB28 AD26 AD28 AF26 AF28 AF30 AF31

AT16 AU16

BJ18

AM23

AK24

AN20 AN22 AN23 AN24 AN26 AN28 BJ26 BJ28 AT26 AT28 AU26 AU28 AV26 AV28 AW26 AW28 BA26 BA28 BB26 BB28 BC26 BC28 BD26 BD28 BE26 BE28 BG26 BG28 BH27

AN30 AN31

AM8 AM9 AP11 AP9

AM16 AK16 AK20 AK19 AK15 AK13 AM12 AM13 AM15

AP43 AP45 AT46 AT45

AT22

AT24

AF53 AF51

AH39

IBEX_PEAK_M

FCBGA

OMIT

U1800

V9

V12

Y22

Y20

K49

F24

AT18 AU18

M36 N36 P36 U35

AD13

V15 V16 Y16

J38 L38

AP51 AP53

BB51 BB53

BD51 BD53

AH19 AD20 AF22 AD19 AF20 AF19 AH20 AB19 AB20 AB22

AF34

AD22

AH23 AJ35 AH35

AH34 AF32

V24

V23

V26 Y24 Y26

AH22

AF23 AF24

AD38

Y39 Y41 Y42

AA34 Y34 Y35 AA35

AD39 AD41 AF43 AF41 AF42

V39 V41 V42

A12

AK3 AK1

V28

M26 L28 L26 J28 J26 H28 H26 G28 G26 F28

U28

F26 E28 E26 C28 C26 B27 A28 A26 U23

P18

U26

U19 U20 U22

U24 P28 P26 N28 N26 M28

L30

AU24

AT20

20% CERM

10V

0.1UF

402

PLACE_NEAR=U1800.Y20:2.54MM

C2200

1

2

402

0.1UF

20% 10V CERM

PLACE_NEAR=U1800.V9:2.54MM

C2210

1

2

402

0.1UF

20% 10V CERM

PLACE_NEAR=U1800.V12:2.54MM

C2220

1

2

402

0.1UF

20% 10V CERM

PLACE_NEAR=U1800.Y22:2.54MM

C2230

1

2

20%

4.7UF

X5R

4V

402

C2225

1

2

402-HF

1%

0.2

1/6W

MF

R2225

1 2

SYNC_MASTER=K17_REF

PCH Power

SYNC_DATE=06/15/2009

MIN_LINE_WIDTH=0.2 mm VOLTAGE=1.05V

MIN_NECK_WIDTH=0.1 mm

PP1V05_S0_PCH_VCCIO_SSC_FLT

PP1V05_S0

PP3V3_S0

MIN_NECK_WIDTH=0.2 mm

PPVOUT_G3_PCH_DCPRTC

VOLTAGE=X.XV

MIN_LINE_WIDTH=0.2 mm

PP3V3_S0

PP1V8_S0

PP1V05_S0_PCH_VCCADPLLB

PP3V3_S0

PP1V8_S0

PP3V3_S0_PCH_VCCA_DAC

PP3V3_S0

PP1V8_S0_PCH_VCCTX_LVDS

PP1V05_S0

PP1V8_S0

PP3V3_S0

PP3V3_S5

PP1V05_S0_PCH_VCCADPLLA

PP1V05_S0

PP3V3_S0

PPVOUT_S5_PCH_DCPSUS

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=X.XV

PPVOUT_S5_PCH_DCPSUSBYP

MIN_NECK_WIDTH=0.2 mm

VOLTAGE=1.05V

MIN_LINE_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm

VOLTAGE=X.XV

PPVOUT_S0_PCH_DCPSST

PP1V05_S0_PCH_VCCAPLL_EXP

PP1V05_S0

PP1V05_S0_PCH_VCCAPLL_FDI

PP1V05_S0

PP3V3_S5

PP1V05_S0_PCH_VCCAPLL_SATA

PP1V8_S0

PP1V05_S0

PP3V3_S0

PP3V42_G3H

PP1V05_S0

PP1V8_S0

PP1V05_S0_PCH_VCCA_CLK

PP5V_S0_PCH_V5REF

GND

PP5V_S5_PCH_V5REFSUS

PP3V3_S0

PP1V05_S0

22 OF 132

<SCH_NUM>

21 OF 101

6 7

10 12 13

15 17 18 20 21

23 24 25 26

40 70 73 86

6 7

17 18 19 20 21 23 24 25

26 27 28 30 34 37 40 42 46

47 48 50 51 52 54 58 62 63 68

69 72 73 80 83 84 85 87 88

99

6 7

17 18 19 20 21 23 24 25 26

27 28 30 34 37 40 42 46 47 48

50 51 52 54 58 62 63 68 69 72

73 80 83 84 85 87 88 99

6 7

12 16 21 23

24 58 71 72 87

24

6 7

17 18 19 20 21 23 24 25 26

27 28 30 34 37 40 42 46 47 48

50 51 52 54 58 62 63 68 69 72

73 80 83 84 85 87 88 99

6 7

12 16 21 23 24 58 71 72 87

24

6 7

17 18 19 20 21 23 24 25 26

27 28 30 34 37 40 42 46 47 48

50 51 52 54 58 62 63 68 69 72

73 80 83 84 85 87 88 99

24

6 7

10 12 13 15 17 18 20 21 23

24 25 26 40 70 73 86

6 7

12 16 21 23 24 58 71 72 87

6 7

17 18 19 20 21 23 24 25 26

27 28 30 34 37 40 42 46 47 48

50 51 52 54 58 62 63 68 69 72

73 80 83 84 85 87 88 99

6 7

17 18 19 20 21 23 27 31 35

57 66 71 72 73 83 85 99

24

6 7

10 12 13 15

17 18 20 21 23

24 25 26 40 70 73

86

6 7

17 18 19 20 21 23 24 25

26 27 28 30 34 37 40 42 46

47 48 50 51 52 54 58 62 63 68

69 72 73 80 83 84 85 87 88

99

23

6 7

10 12 13 15 17 18 20 21

23 24 25 26 40 70 73 86

6 7

10 12 13 15 17 18 20 21

23 24 25 26 40 70 73 86

23

6 7

10 12 13 15 17 18 20 21

23 24 25 26 40 70 73 86

6 7

17 18 19 20 21 23 27 31

35 57 66 71 72 73 83 85 99

23

6 7

12 16 21 23 24 58 71 72 87

6 7

10 12 13 15 17 18 20 21 23

24 25 26 40 70 73 86

6 7

17

18 19 20 21 23 24 25 26 27 28

30 34

37 40 42 46 47 48 50 51 52 54

58 62 63 68 69 72 73 80 83 84

85 87 88 99

6 7

17 23 43 45 46 47 48 49

53 64 65 66 73

6 7

10 12 13 15 17 18 20 21 23

24 25 26 40 70 73 86

6 7

12 16 21 23 24 58 71 72

87

23

6 7

17 18 19 20 21 23 24 25 26

27 28 30 34 37 40 42 46 47

48 50 51 52 54 58 62 63 68 69

72 73 80 83 84 85 87 88 99

6 7

10 12 13 15 17 18 20 21

23 24 25 26 40 70 73 86

6 7

10 12 13 15 17 18 20 21 23

24 25 26 40 70 73 86

6 7

10 12 13 15 17 18 20 21 23

24 25 26 40 70 73 86

6 7

10 12 13 15 17 18 20 21

23 24 25 26 40 70 73 86

VSSVSS

(8 OF 10)

VSSVSS

(9 OF 10)

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

IBEX_PEAK_M

OMIT

FCBGA

U1800

AB16 AA19

AA32

AM28 BA42 AM30 AM31 AM32 AM34 AM35 AM38 AM39 AM42

AB11

AU20 AM46 AV22 AM49 AM7 AA50 BB10 AN32 AN50 AN52

AB15

AP12 AP42 AP46 AP49 AP5 AP8 AR2 AR52 AT11 BA12

AB23

AH48 AT32 AT36 AT41 AT47 AT7 AV12 AV16 AV20 AV24

AB30

AV30 AV34 AV38 AV42 AV46 AV49 AV5 AV8 AW14 AW18

AB31

AW2 BF9 AW32 AW36 AW40 AW52 AY11 AY43 AY47

AB32 AB39 AB43 AB47

AA20

AB5 AB8

AC2 AC52 AD11 AD12 AD16 AD23 AD30 AD31

AA22

AD32 AD34 AU22 AD42 AD46 AD49

AD7

AE2

AE4 AF12

AM19

Y13 AH49

AU4 AF35 AP13 AN34 AF45 AF46 AF49

AF5

AA24

AF8

AG2 AG52 AH11 AH15 AH16 AH24 AH32 AV18 AH43

AA26

AH47

AH7 AJ19

AJ2 AJ20 AJ22 AJ23 AJ26 AJ28 AJ32

AA28

AJ34

AT5

AJ4 AK12 AM41 AN19 AK26 AK22 AK23 AK28

AA30

AK30 AK31 AK32 AK34 AK35 AK38 AK43 AK46 AK49 AK5

AA31

AK8 AL2 AL52 AM11 BB44 AD24 AM20 AM22 AM24 AM26

FCBGA

IBEX_PEAK_M

OMIT

U1800

AY7 B11 B15 B19 B23 B31 B35 B39 B43 B47

B7 BG12 BB12 BB16 BB20 BB24 BB30 BB34 BB38 BB42 BB49

BB5 BC10 BC14 BC18

BC2 BC22 BC32 BC36 BC40 BC44 BC52

BH9 BD48 BD49

BD5 BE12 BE16 BE20 BE24 BE30 BE34 BE38 BE42 BE46 BE48 BE50

BE6

BE8

BF3 BF49 BF51 BG18 BG24

BG4 BG50 BH11 BH15 BH19 BH23 BH31 BH35 BH39 BH43 BH47

BH7

C12

C50

D51

E12

E16

E20

E24

E30

E34

E38

E42

E46

E48

E6 E8

F49

F5 G10 G14 G18

G2 G22 G32 G36 G40 G44 G52

AF39

H16 H20 H30 H34 H38 H42

H49 H5 J24 K11 K43 K47 K7 L14 L18 L2 L22 L32 L36 L40 L52 M12 M16 M20 N38 M34 M38 M42 M46 M49 M5 M8 N24 P11 AD15 P22 P30 P32 P34 P42 P45 P47 R2 R52 T12 T41 T46 T49 T5 T8 U30 U31 U32 U34 P38 V11 P16 V19 V20 V22 V30 V31 V32 V34 V35 V38 V43 V45 V46 V47 V49 V5 V7 V8 W2 W52 Y11 Y12 Y15 Y19 Y23 Y28 Y30 Y31 Y32 Y38 Y43 Y46 P49 Y5 Y6 Y8 P24 T43 AD51 AT8 AD47 Y47 AT12 AM6 AT13 AM5 AK45 AK39 AV14

PCH Grounds

SYNC_MASTER=K17_REF

SYNC_DATE=06/15/2009

23 OF 132

<SCH_NUM>

22 OF 101

NCNC

NC

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

1 mA S0-S5

PCH V5REF Filter & Follower (PCH Reference for 5V Tolerance on PCI)

(VCCSUS3_3 Total)

PCH VCCME3_3 BYPASS

PCH CORE/VCC3_3 BYPASS (PCH MISC 3.3V PWR)

BB: C2419 removed from DG

BB: C2417 removed from DG

WF: C2413 not in DG or CRB

(PCH PCI 3.3V PWR)

PCH VCCFDIPLL Filter

(PCH PCIe PLL PWR)

PCH VCCAPLLEXP Filter

WF: C2311 not in DG or CRB

(PCH FDI PLL PWR)

(PCH SATA PLL PWR)

PCH VCCSATAPLL Filter

PCH VCCACLK Filter (PCH Misc PLL PWR)

(PCH PCIe/DMI 3.3V PWR)

PCH VCC3_3 BYPASS

(PCH 1.05V ME Core PWR)

PCH VCCME BYPASS

65 mA S3-S5

163 mA S0 /

PCH VCC3_3 BYPASS

(PCH SATA 3.3V PWR)

PCH VCC3_3 BYPASS

(PCH ME 3.3V PWR)

(PCH SUSPEND PCI 3.3V PWR)

PCH VCCSUS3_3 BYPASS

(PCH 1.05V CORE PWR)

(PCH NAND 1.8V/3.3V PWR)

PCH VCCPNAND BYPASS

PCH VCCSUSHDA BYPASS (PCH HD Audio 3.3V/1.5V PWR)

(PCH CLK 1.05V PWR)

1 mA

(PCH RTC 3.3V PWR)

6 uA G3

PCH VCCCORE BYPASS

PCH VCCIO BYPASS

(PCH USB 1.05V PWR)

PCH VCCIO BYPASS

(PCH SATA 1.05V PWR)

PCH VCCIO BYPASS (PCH PCIE 1.05V PWR)

PCH VCCRTC BYPASS

2 mA S0-S5 /

(PCH CLK/HVCMOS 3.3V PWR)

Current numbers from Ibex Peak EDS Spec Update rev 0.71, doc #386904 (Table 8-3). Pre-Silicon Mobile Estimates.

1 mA

PCH V5REF_SUS Filter & Follower (PCH Reference for 5V Tolerance on USB)

1 mA S0-S5

(PCH SUSPEND USB 3.3V PWR)

PCH USB/VCCSUS3_3 BYPASS

(PCH 1.1V/1.05V CPU I/O PWR)

PCH V_CPU_IO BYPASS

(PCH 1.05V LAN Core PWR)

PCH VCCLAN BYPASS

(PCH DMI 1.05V PWR)

PCH VCCIO BYPASS

1UF

X5R

10% 10V

402

PLACE_NEAR=U1800.K49:2.54MM

C2401

1

2

NO STUFF

6.3V

10%

402

CERM

1UF

PLACE_NEAR=U1800.AP51:2.54MM

C2419

1

2

5%

1/16W

402

MF-LF

100

R2401

2

1

BAT54DW-X-G

SOT-363

D2400

1

6

5

1/16W

402

5%

MF-LF

10

R2400

2

1

SOT-363

BAT54DW-X-G

D2400

4

3

2

16V

10% 402

X5R

0.1UF

PLACE_NEAR=U1800.A12:2.54MM

C2421

1

2

0.1UF

X5R 402

10% 16V

PLACE_NEAR=U1800.P18:2.54MM

C2425

1

2

16V

10% 402

X5R

0.1UF

PLACE_NEAR=U1800.A12:2.54MM

C2422

1

2

402

6.3V

10% CERM

1UF

OMIT

PLACE_NEAR=U1800.BJ24:2.54MM

C2413

1

2

6.3V

10% 402

1UF

OMIT

CERM

PLACE_NEAR=U1800.BJ18:2.54MM

C2415

1

2

NO STUFF

6.3V

10% 402

CERM

1UF

PLACE_NEAR=U1800.AK1:2.54MM

C2417

1

2

X5R 402

16V

0.1UF

10%

PLACE_NEAR=U1800.U23:2.54MM

C2427

1

2

PLACE_NEAR=U1800.A26:2.54MM

0.1UF

X5R 402

10% 16V

C2426

1

2

0.1UF

X5R 402

10% 16V

PLACE_NEAR=U1800.AM8:2.54MM

C2430

1

2

0.1UF

X5R 402

10% 16V

PLACE_NEAR=U1800.V15:2.54MM

C2435

1

2

PLACE_NEAR=U1800.J38:2.54MM

0.1UF

X5R 402

10% 16V

C2436

1

2

0.1UF

X5R 402

10% 16V

PLACE_NEAR=U1800.AD13:2.54MM

C2437

1

2

0.1UF

X5R 402

10% 16V

PLACE_NEAR=U1800.AN35:2.54MM

C2438

1

2

0.1UF

X5R 402

10% 16V

PLACE_NEAR=U1800.AB34:2.54MM

C2439

1

2

16V

10%

402

X5R

0.1UF

PLACE_NEAR=U1800.AK13:2.54MM

C2440

1

2

1UF

CERM 402

10%

6.3V

PLACE_NEAR=U1800.L30:2.54MM

C2445

1

2

16V

10%

402

X5R

0.1UF

PLACE_NEAR=U1800.AT18:2.54MM

C2452

1

2

16V

10%

402

X5R

0.1UF

PLACE_NEAR=U1800.AT18:2.54MM

C2451

1

2

6.3V

20%

603

X5R

4.7UF

PLACE_NEAR=U1800.AT18:2.54MM

C2450

1

2

6.3V

10% 402

CERM

1UF

PLACE_NEAR=U1800.V39:2.54MM

C2469

1

2

6.3V

X5R-CERM

603

22UF

20%

PLACE_NEAR=U1800.V39:2.54MM

C2467

1

2

6.3V

X5R-CERM

603

22UF

20%

PLACE_NEAR=U1800.AD38:2.54MM

C2466

1

2

NO STUFF

1UF

10%

6.3V 402

CERM

PLACE_NEAR=U1800.AF23:2.54MM

C2460

1

2

6.3V

10% 402

CERM

1UF

PLACE_NEAR=U1800.AH35:2.54MM

C2477

1

2

6.3V

10% 402

CERM

1UF

PLACE_NEAR=U1800.AH23:2.54MM

C2476

1

2

6.3V

10% 402

CERM

1UF

PLACE_NEAR=U1800.AF32:2.54MM

C2475

1

2

6.3V

10% 402

CERM

1UF

PLACE_NEAR=U1800.V24:2.54MM

C2480

1

2

6.3V

10%

402

CERM

1UF

PLACE_NEAR=U1800.AB19:2.54MM

C2485

1

2

PLACE_NEAR=U1800.AN20:2.54MM

6.3V

10% 402

CERM

1UF

C2494

1

2

6.3V

10% 402

CERM

1UF

PLACE_NEAR=U1800.AN20:2.54MM

C2493

1

2

6.3V

10% 402

CERM

1UF

PLACE_NEAR=U1800.AN20:2.54MM

C2492

1

2

402

6.3V

10% CERM

1UF

PLACE_NEAR=U1800.AN20:2.54MM

C2491

1

2

10UF

6.3V

20% 603

X5R

PLACE_NEAR=U1800.AN20:2.54MM

C2490

1

2

402

6.3V

10% CERM

1UF

PLACE_NEAR=U1800.AT16:2.54MM

C2455

1

2

6.3V

10% 402

CERM

1UF

PLACE_NEAR=U1800.AD38:2.54MM

C2468

1

2

6.3V

X5R-CERM

603

22UF

20%

PLACE_NEAR=U1800.AD38:2.54MM

C2465

1

2

10% 402

1UF

6.3V CERM

PLACE_NEAR=U1800.AB24:2.54MM

C2471

1

2

6.3V

20% 603

X5R

10UF

PLACE_NEAR=U1800.AB24:2.54MM

C2470

1

2

6.3V

10% 402

CERM

1UF

PLACE_NEAR=U1800.A12:2.54MM

C2420

1

2

PLACE_NEAR=U1800.F24:2.54MM

402

1UF

X5R

10% 10V

C2400

1

2

SYNC_DATE=06/15/2009

SYNC_MASTER=K17_REF

PCH Non-GFX Decoupling

PP5V_S5

PP5V_S0

PP5V_S0_PCH_V5REF

MIN_LINE_WIDTH=0.3MM VOLTAGE=5V

MIN_NECK_WIDTH=0.25MM

PP1V05_S0

GND

PP1V8_S0

PP3V3_S0

PP3V42_G3H

PP3V3_S0

PP3V3_S5

PP1V05_S0

PP3V3_S0

PP1V05_S0_PCH_VCCA_CLK

VOLTAGE=1.05V

MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.25MM

PP1V05_S0_PCH_VCCAPLL_SATA

VOLTAGE=1.05V

MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.25MM

PP1V05_S0_PCH_VCCAPLL_FDI

VOLTAGE=1.05V

MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.25MM

VOLTAGE=1.05V

MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.25MM

PP1V05_S0_PCH_VCCAPLL_EXP

PP5V_S5_PCH_V5REFSUS

MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.25MM VOLTAGE=5V

PP3V3_S5

PP3V3_S0

24 OF 132

<SCH_NUM>

23 OF 101

6 7

66 72

6 7

42 47 52 54

68 69 70 72 86

88

21

6 7

10 12 13 15 17 18 20 21

23 24 25 26 40 70 73 86

6 7

10 12 13 15 17 18 20 21

23 24 25 26 40 70 73 86

6 7

10 12 13 15 17 18 20 21

23 24 25 26 40 70 73 86

6 7

10 12 13 15 17 18 20 21

23 24 25 26 40 70 73 86

6 7

10 12 13 15 17 18 20 21

23 24 25 26 40 70 73 86

6 7

10 12 13 15 17 18 20 21

23 24 25 26 40 70 73 86

6 7

10 12 13 15 17 18 20 21

23 24 25 26 40 70 73 86

6 7

12 16 21 24 58 71 72 87

6 7

17 18 19 20 21 23 24 25

26 27 28 30 34 37 40 42 46 47

48 50 51 52 54 58 62 63 68 69

72 73 80 83 84 85 87 88 99

6 7

17 21 43 45 46 47 48 49

53 64 65 66 73

6 7

17 18

19 20 21 23 24 25 26 27 28 30

34 37 40 42

46 47 48 50 51 52 54 58 62

63 68 69 72 73 80 83 84 85

87 88 99

6 7

17 18

19 20 21 23 24 25 26 27 28 30

34 37 40 42

46 47 48 50 51 52 54 58 62

63 68 69 72 73 80 83 84 85

87 88 99

6 7

17 18 19 20 21 23 24 25

26 27 28 30 34 37 40 42 46 47

48 50 51 52 54 58 62 63 68

69 72 73 80 83 84 85 87 88

99

6 7

17 18 19 20 21 23 24 25

26 27 28 30 34 37 40 42 46 47

48 50 51 52 54 58 62 63 68

69 72 73 80 83 84 85 87 88

99

6 7

17 18 19 20 21 23 24 25

26 27 28 30 34 37 40 42 46 47

48 50 51 52 54 58 62 63 68 69

72 73 80 83 84 85 87 88 99

6 7

17

18 19 20

21 23 27

31 35 57

66 71 72

73 83 85

99

6 7

17 18 19 20 21 23 27 31

35 57 66 71 72 73 83 85 99

6 7

10 12 13 15 17 18 20 21

23 24 25 26 40 70 73 86

6 7

17 18 19 20

21 23 24 25 26

27 28 30

34 37 40

42 46 47

48 50 51

52 54 58

62 63 68

69 72 73

80 83 84

85 87 88

99

21

6 7

17 18 19 20

21 23 27

31 35 57

66 71 72

73 83 85

99

6 7

17 18 19 20 21 23 24 25

26 27 28 30 34 37 40 42 46 47

48 50 51 52 54 58 62 63 68 69

72 73 80 83 84 85 87 88 99

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

(PCH DPLLA PWR)

PCH VCCADPLLA Filter

PCH VCCADPLLB Filter

PCH VCCTX_LVDS Filter

69 mA

68 mA

(PCH DPLLB PWR)

Design recommendations from Calpella Design Guide Rev 1.5 (doc #398905) Section 3.25.3 tables 161 and 162.

Current numbers from Ibex Peak EDS Spec Update rev 0.71, doc #386904 (Table 8-3). Pre-Silicon Mobile Estimates.

69 mA

59 mA

(PCH LVDS TX PWR)

PCH VCCADAC Filter

69 mA

68 mA

59 mA

69 mA

137 mA

Design recommendations from Calpella Small Form Factor Design Guide Rev 1.5 (doc #407364) table 2-34 and Calpella Small Form F

actor Schematic Check List Rev 1.1 (doc #395914) table 3.26.

VCAP2 (CPU BSC Package) DECOUPLING

PLACEMENT_NOTE (C2524-C2539):

PLACEMENT_NOTE (C2500-C2506):

3x 330uF 6 mOhm (2 stuffed), 3x 22uF 0603, 16x 1uF 0402

GFX (CPU VCCAXG) DECOUPLING

(PCH DAC PLL PWR)

PLACEMENT_NOTE (C2510-C2514):

5x 1uF 0402

0805

0.1UH

PLACE_NEAR=U1800.AP43:2.54MM

L2570

1 2

PLACE_NEAR=U1800.AP43:2.54MM

16V 402

0.01UF

20% CERM

C2572

1

2

NO STUFF

402

CERM

PLACE_NEAR=U1800.BB51:2.54MM

1UF

6.3V

10%

C2561

1

2

0

402

5%

MF-LF

1/16W

R2560

1 2

CASE-B2-SM1

220UF

POLY-TANT

2.5V

20%

PLACE_NEAR=U1800.BB51:2.54MM

C2560

1

2

NO STUFF

PLACE_NEAR=U1800.BD51:2.54MM

402

6.3V CERM

1UF

10%

C2566

1

2

PLACE_NEAR=U1800.BD51:2.54MM

220UF

POLY-TANT

CASE-B2-SM1

20%

2.5V

C2565

1

2

MF-LF

402

1/16W

0

5%

R2565

1 2

PLACE_NEAR=U1800.AE50:2.54MM

CERM

20% 16V

402

0.01UF

C2552

1

2

PLACE_NEAR=U1800.AE50:2.54MM

20%

6.3V X5R 603

10UF

C2550

1

2

Place on bottom side of U1000.

22UF

20%

603

X5R-CERM

6.3V

C2500

1

2

PLACE_NEAR=U1800.AE50:2.54MM

0603

180-OHM-1.5A

L2550

1 2

MF-LF

1/16W

5%

402

0

R2550

1 2

16V 402

20% CERM

PLACE_NEAR=U1800.AP43:2.54MM

0.01UF

C2571

1

2

10% 402

0.1UF

16V X5R

PLACE_NEAR=U1800.AE50:2.54MM

C2551

1

2

Place on bottom side of U1000.

10V 402

1UF

10% X5R

C2514

1

2

Place on bottom side of U1000.

1UF

X5R

10% 402

10V

C2513

1

2

Place on bottom side of U1000.

X5R

10%

1UF

402

10V

C2512

1

2

Place on bottom side of U1000.

1UF

X5R

10% 402

10V

C2511

1

2

Place on bottom side of U1000.

10V 402

1UF

10% X5R

C2510

1

2

D2T-SM2

20% POLY-TANT

2.0V

330UF

C2505

1

23

330UF

D2T-SM2

2.0V

20% POLY-TANT

C2506

1

23

603

X5R-CERM

PLACE_NEAR=U1800.AP43:2.54MM

22UF

20%

6.3V

C2570

1

2

10UH-0.12A-0.36OHM

0603

L2560

1 2

22UF

20%

6.3V X5R-CERM

Place on bottom side of U1000.

603

C2501

1

2

10UH-0.12A-0.36OHM

0603

L2565

1 2

402

10% X5R

1UF

10V

C2535

1

2

402

10% X5R

10V

1UF

C2534

1

2

402

10% X5R

1UF

10V

C2533

1

2

402

10% X5R

1UF

10V

C2532

1

2

402

10% X5R

1UF

10V

C2531

1

2

402

10% X5R

10V

1UF

C2530

1

2

402

10% X5R

1UF

10V

C2529

1

2

402

10% X5R

1UF

10V

C2528

1

2

Place on bottom side of U1000.

1UF

402

10% X5R

10V

C2527

1

2

Place on bottom side of U1000.

402

10% X5R

10V

1UF

C2526

1

2

Place on bottom side of U1000.

402

10V

10% X5R

1UF

C2525

1

2

Place on bottom side of U1000.

402

10% X5R

1UF

10V

C2524

1

2

402

10V

10% X5R

1UF

C2539

1

2

402

10V X5R

10%

1UF

C2538

1

2

402

10% X5R

1UF

10V

C2537

1

2

402

10% X5R

1UF

10V

C2536

1

2

20%

22UF

603

X5R-CERM

6.3V

Place on bottom side of U1000.

C2502

1

2

SYNC_DATE=06/15/2009

SYNC_MASTER=K17_REF

CPU/PCH GFX Decoupling

PPVCORE_S0_CPU_VCAP2

PPVCORE_S0_GFX

PP3V3_S0

PP1V8_S0

PP3V3_S0_PCH_VCCA_DAC_F

MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.25MM VOLTAGE=3.3V

PP1V8_S0_PCH_VCCTX_LVDS

VOLTAGE=1.8V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM

PP1V05_S0

PP3V3_S0_PCH_VCCA_DAC

MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.3V

MIN_LINE_WIDTH=0.4 MM

MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V

MIN_LINE_WIDTH=0.4 MM

PP1V05_S0_PCH_VCCADPLLA

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.25MM

MIN_LINE_WIDTH=0.5MM

PP1V05_S0_PCH_VCCADPLLA_F

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.25MM

MIN_LINE_WIDTH=0.5MM

PP1V05_S0_PCH_VCCADPLLB_F

PP1V05_S0_PCH_VCCADPLLB

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V

25 OF 132

<SCH_NUM>

24 OF 101

7

13

6 7

13 49 69

6 7

17 18 19 20 21 23 25 26

27 28 30 34 37 40 42 46 47

48 50 51 52 54 58 62 63 68 69

72 73 80 83 84 85 87 88 99

6 7

12 16 21 23 58 71 72 87 21

6 7

10 12 13 15 17 18 20 21

23 25 26 40 70 73 86

21

BI

OUT

BI

OUT

IN

IN IN

IN

OUT

NC

BI

OUT

IN

OUT

IN

IN IN

OUT

IN

OUT

IN

IN IN

IN

IN IN IN IN

IN

IN IN

IN

TABLE_5_ITEM

CRITICAL BOM OPTION

TABLE_5_HEAD

PART#

DESCRIPTION

QTY

REFERENCE DESIGNATOR(S)

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

NOTE: XDP_DBRESET_L must be pulled-up to 3.3V.

OBSFN_D0 OBSFN_D1

OBSDATA_D0

Calpella PCH mini XDP

516S0852

Calpella Processor mini XDP

OBSFN_A1

OBSDATA_A1

RESET#/HOOK6

NOTE: XDP_DBRESET_L must be pulled-up to 3.3V.

OBSDATA_A3

VCC_OBS_CD

OBSDATA_D1

OBSDATA_D2

HOOK2

ITPCLK#/HOOK5 VCC_OBS_CD

DBR#/HOOK7

OBSDATA_C3

1K series R on PCH Support Page

PCH OC2#

PCH OC7#

PCH OC6#

PCH OC5#

PCH OC4#

PCH OC3#

PCH OC1#

PCH OC0#

PCH GPIO28

PCH GPIO18

PCH GPIO20

PCH GPIO21 PCH GPIO19

PCH GPIO36 PCH GPIO37

PCH GPIO16 PCH GPIO49

PCH GPIO0

OBSFN_D1

OBSDATA_D0

RESET#/HOOK6 DBR#/HOOK7

TRSTn

TCK0

TMS XDP_PRESENT#

TDI

TCK1

OBSDATA_B3

PWRGD/HOOK0

HOOK1

HOOK3

SDA SCL

OBSDATA_A0

OBSFN_A0

TDO

OBSDATA_C2

OBSFN_D0

OBSDATA_D3

TRSTn

OBSDATA_C0

OBSFN_C1

OBSFN_C0

OBSFN_B1

OBSDATA_A0 OBSDATA_A1

OBSFN_B0

OBSDATA_A2

OBSFN_A0 OBSFN_A1

OBSDATA_B3

PWRGD/HOOK0

HOOK1

VCC_OBS_AB

OBSDATA_B2

HOOK3

TCK1 TCK0

OBSDATA_B0 OBSDATA_B1

OBSDATA_D2

OBSDATA_D1

SDA SCL

OBSDATA_C1

OBSDATA_C3

OBSDATA_C2

OBSFN_C1

OBSFN_C0

ITPCLK/HOOK4 ITPCLK#/HOOK5

OBSDATA_D3

XDP_PRESENT#

TDO

TDI TMS

OBSDATA_C1

ITPCLK/HOOK4

OBSDATA_C0

HOOK2

VCC_OBS_AB

OBSDATA_A2 OBSDATA_A3

OBSFN_B0 OBSFN_B1

OBSDATA_B0 OBSDATA_B1

OBSDATA_B2

518S0774

17 25 26 28 30 32 42 47 48 63 88 94

17

10 91

17

27 45 73 87

19

19 35

19

19 46

17

2

1

R2615

402

MF-LF

1/16W

5%

XDP

51

9

8 7

60

6

59

58 57

56 55

54 53

52 51

50

5

49

48 47

46 45

44 43

42 41

40

4

39

38 37

36 35

34 33

32 31

30

3

29

28 27

26 25

24 23

22 21

20

2

19

18 17

16 15

14 13

12 11

10

1

J2600

F-ST-SM

LTH-030-01-G-D-NOPEGS

CRITICAL

OMIT

XDP_CONN_PCH

9

87

60

6

59

5857

5655

5453

5251

50

5

49

4847

4645

4443

4241

40

4

39

3837

3635

3433

3231

30

3

29

2827

2625

2423

2221

20

2

19

1817

1615

1413

1211

10

1

J2650

F-ST-SM-HF

CRITICAL

DF40C-60DS-0.4V

2

1

C2600

XDP

402

16V

0.1uF

10% X5R

2

1

C2601

XDP

X5R

0.1uF

10%

402

16V

17 25 26 28 30 32 42 47 48 63 88 94

10 91

10 25 27 91

10 91

21

R2611

PLACE_NEAR=U1000.N70:1.00MM

5%

MF-LF

1/16W

402

XDP

1K

10 20 91

10 91

18 25 45

10 91

21

R2690

MF-LF

1/16W

402

0

5%

XDP_NORMAL&XDP_CPU

21

R2610

1/16W

5%

XDP

MF-LF

402

1K

21

R2695

5%

0

402

1/16W MF-LF

XDP_CPU

21

R2696

MF-LF

1/16W

402

5%

XDP_GMCH

0

21

R2692

MF-LF

1/16W

402

0

5%

XDP_NORMAL&XDP_GMCH

2

1

R2691

XDP_NORMAL

MF-LF

1/16W

402

0

5%

10

9

91

9

91

10 91

9

91

9

91

9

91

9

91

9

91

9

91

9

91

8 9

91

9

91

9

91

9

91

9

91

5

6

7

8

4

3

2

1

RP2600

1/16W SM-LF

5%

0

XDP_CPU_BPM

8

7

6

5

1

2

3

4

RP2601

SM-LF

PLACEMENT_NOTE=Place R2501 close to R2500 to minimize stubs.

1/16W

5%

0

XDP_CPU_CFG

10 91

9

91

9

91

9

91

9

91

20 45 46

20 31

17 40

17 33

17 42

17

27

20 87

20 34

20

20 63

SYNC_DATE=06/15/2009

SYNC_MASTER=K17_REF

eXtended Debug Port (XDP)

516S0852

1

CONN,PLUG,B2B,60P,0.5MM,NOPEG

J2600

CRITICAL

XDP_CONN_CPU

TP_XDP_HOOK3

SMBUS_PCH_DATA SMBUS_PCH_CLK

TP_XDPPCH_OBSFN_A<0> TP_XDPPCH_OBSFN_A<1>

USB_HUB_SOFT_RESET_L

PCH_GPIO59

PCH_GPIO42

PCH_GPIO41

TP_XDPPCH_OBSFN_B<1>

TP_XDPPCH_OBSFN_B<0>

PCH_GPIO43 PCH_GPIO9

PCH_GPIO10 PM_LATRIGGER_L

ALL_SYS_PWRGD

PM_PWRBTN_L

TP_XDPPCH_HOOK2 TP_XDPPCH_HOOK3

SMBUS_PCH_DATA SMBUS_PCH_CLK

JTAG_PCH_TCK

TP_XDPPCH_HOOK4

ME_TEMP_ALERT_L

AUD_IPHS_SWITCH_EN

JTAG_GMUX_TCK

SDCARD_RESET

TP_XDPPCH_OBSFN_D<1>

TP_XDPPCH_OBSFN_D<0>

SATARDRVR_A_EN SATARDRVR_B_EN

FW_CLKREQ_L AP_CLKREQ_L

SMC_IG_THROTTLE_L

ISOLATE_CPU_MEM_L

JTAG_PCH_TDI JTAG_PCH_TMS

TP_XDPPCH_TRST_L

JTAG_PCH_TDO

XDP_DBRESET_L

XDPPCH_PLTRST_L

TP_XDPPCH_HOOK5

XDP_TCK

XDP_OBSDATA_A<2>

XDP_PWRGD

XDP_TDO

XDP_OBSDATA_A<1>

XDP_TDO

XDP_TDI

XDP_CPUPWRGD

PP1V05_S0

PM_PWRBTN_L

XDP_BPM_L<7>

XDP_BPM_L<6>

XDP_BPM_L<4> XDP_BPM_L<5>

CPU_CFG<16>

CPU_CFG<17>

XDP_OBSDATA_A<3>

XDP_OBSDATA_A<0>

XDP_PRDY_L

XDP_PREQ_L CPU_CFG<8>

CPU_CFG<9>

CPU_CFG<0> CPU_CFG<1>

CPU_CFG<2> CPU_CFG<3>

CPU_CFG<11>

CPU_CFG<5>

CPU_CFG<4>

CPU_CFG<6>

FSB_CLK133M_ITP_P

CPU_CFG<7>

FSB_CLK133M_ITP_N

XDP_DBRESET_L

XDP_TDI XDP_TMS

XDP_BPM_L<0>

XDP_BPM_L<2>

XDP_BPM_L<1>

XDP_BPM_L<3>

CPU_CFG<12> CPU_CFG<13>

CPU_CFG<15>

CPU_CFG<14>

CPU_PWRGD

JTAG_GMCH_TDI

JTAG_CPU_TDO

JTAG_GMCH_TDO

JTAG_CPU_TDI

FSB_CPURST_L

XDP_TRST_L

PP3V3_S0

CPU_CFG<10>

XDP_CPURST_L

26 OF 132

<SCH_NUM>

25 OF 101

18 25 45

17 25 26 28 30 32 42 47 48 63 88 94

10 25 27 91

25 91

6 7

10 12 13 15 17 18 20 21

23 24 26 40 70 73 86

25 91

6 7

17 18 19 20 21 23 24 26

27 28 30 34 37 40 42 46 47 48

50 51 52 54 58 62 63 68 69 72

73 80 83 84 85 87 88 99

91

IN

BI

IN

OUT

CPU0*

CPU0

REF_FS

USB

CPU1

CPU1*

SRC1*

SRC1

SRC0*/SATA*

SRC0/SATA

27M_NSS

27M_SS

DOT96*

XOUT

XIN

SCLK

SDATA

CK_PWRGD/PWRDWN*

VDD_SRC

VDD_CPU

VDD_REF

VDD_DOT

VDD_27

VDD_SRC_IO

VDD_CPU_IOVSS_CPU

VSS_27

VSS_DOT

THRM

VSS_SRC

VSS_REF

DOT96

27MHZ_OE*

PAD

OUT OUT

IN

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

No internal pull.

Muxed Graphics implementations.

or connected to logic for

Must be strapped appropriately

(IPD)

PCH USB Clock 96MHz

Unused 48MHz

PCH REFCLK 14.31818MHz

Unused BCLK 133MHz

PCH BCLK 133MHz

PCH SATA 100MHz

GPU 27MHz Clocks (Single-Ended)

PCH DMI/PCIe 100MHz

All other output frequencies are fixed.

FS=0 => 133MHz BCLKs, FS=1 => 100MHz BCLKs

NOTE: REF/FS pin is input until first CK_PWRGD rising edge.

BYPASS=U2790::5 mm

10V

20%

402

CERM

0.1UF

C2790

1

2

68

SC70-5

74HC1G00GWDG

U2790

3

2

1

4

5

PLACE_NEAR=Y2730.1:2 mm:NO_VIA

5%

50V

CERM

402

18pF

C2730

1

2

CRITICAL

5X3.2-SM

14.31818

Y2730

1 2

18pF

402

CERM

50V

5%

PLACE_NEAR=Y2730.2:2 mm:NO_VIA

C2731

1

2

FERR-120-OHM-1.5A

0402

L2710

1 2

0402

FERR-120-OHM-1.5A

L2700

1 2

PLACE_NEAR=L2700.2:2 mm:NO_VIA

10UF

603

X5R

6.3V

20%

C2700

1

2

PLACE_NEAR=L2710.2:2 mm:NO_VIA

20%

6.3V X5R 603

10UF

C2710

1

2

17 25 28 30 32 42 47 48 63 88 94

17 93

PLACE_NEAR=U2700.15:2 mm

10% 16V X5R 402

0.1UF

C2715

1

2

PLACE_NEAR=U2700.18:2 mm

10% 16V X5R 402

0.1UF

C2716

1

2

PLACE_NEAR=U2700.1:2 mm

0.1UF

402

X5R

16V

10%

C2705

1

2

PLACE_NEAR=U2700.5:2 mm

0.1UF

402

X5R

16V

10%

C2706

1

2

CRITICAL

QFN

SL28776

U2700

6

7

16

25

23

22

20

19

3

4

30

32

31

11 10

13

14

33

8

5

24

18

1

29

17

15

9212

26

12

28 27

PLACE_NEAR=U2700.17:2 mm

0.1UF

402

X5R

16V

10%

C2707

1

2

PLACE_NEAR=U2700.24:2 mm

0.1UF

402

X5R

16V

10%

C2708

1

2

PLACE_NEAR=U2700.29:2 mm

0.1UF

402

X5R

16V

10%

C2709

1

2

17 93

73

MF-LF

1/16W

5%

10K

402

R2790

1

2

SYNC_DATE=06/23/2009

SYNC_MASTER=K17_MLB

Clock (CK505)

PCH_CLK14P3M_REFCLK

PCH_CLK96M_DOT_P

PCH_CLK96M_DOT_N

PCH_CLK100M_SATA_N

PCIE_CLK100M_PCH_P

PCIE_CLK100M_PCH_N

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm

PP3V3_S0_CK505_F

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.3 mm

PP1V05_S0_CK505_F

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.2 mm

PP1V05_S0

FSB_CLK133M_PCH_N FSB_CLK133M_PCH_P

TP_CK505_CPU1N

TP_CK505_USB

CK505_CKPWRGD

CK505_CLK14P3M_XIN CK505_CLK14P3M_XOUT

SMBUS_PCH_CLK SMBUS_PCH_DATA

CK505_27MHZ_EN_L

TP_CK505_CLK27M_SS

CK505_CLK27M

PCH_CLK100M_SATA_P

TP_CK505_CPU1P

CPUIMVP_CLK_EN_L

PP3V3_S0

27 OF 132

<SCH_NUM>

26 OF 101

6 7

10 12 13 15 17 18 20 21

23 24 25 40 70 73 86

27

6 7

17 18 19 20 21 23 24 25

27 28 30 34 37 40 42 46 47 48

50 51 52 54 58 62 63 68 69 72

73 80 83 84 85 87 88 99

IN

OUT

IN

OUT

IN

OUT

NC NC

OUT

IN

OUT

IN

NC NC

OUT

IN

OUT

IN

OUT

IN

OUT

BI

OUT

D

GS

OUT

IN

OUT

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PCH S0 PWRGD

Caesar II (ENET) 25MHz Crystal

Ethernet WAKE# Isolation

PCH 25MHz Crystal

PCH RTC Crystal

Platform Reset Connections

Unbuffered

VTT voltage divider on CPU page

Series R is R4283

PCH Reset Button

Buffered

10 25 91

12pF

CERM

50V 402

5%

C2810

1 2

12pF

50V 402

5%

CERM

C2811

1 2

SM-2

CRITICAL

32.768K

Y2810

2 4

1 3

5%

1/16W

0

MF-LF

402

R2810

1 2

5%

10M

MF-LF

402

1/16W

R2811

1

2

1/16W

402

0

5%

MF-LF

XDP

R2896

1 2

5%

33

1/16W

402

MF-LF

R2883

1 2

5%

402

MF-LF

33

1/16W

R2881

1 2

6

27 47 87 94

45

33

17

19 27 31 40

402

1/16W MF-LF

5%

PLACE_NEAR=U1800.P53

22

R2826

1 2

5%

MF-LF

1/16W

402

PLACE_NEAR=U1800.N52

22

R2825

1 2

19 94

CERM

5%

402

50V

12pF

C2815

1 2

402

CERM

12pF

50V

5%

C2816

1 2

CRITICAL

25.0000M

SM-3.2X2.5MM

Y2815

2 4

1 3

402

0

5% 1/16W MF-LF

R2815

1 2

5%

10M

MF-LF

1/16W

402

R2816

1

2

DCI

17

32

1/16W

402

5%

MF-LF

0

R2871

1 2

402

20% CERM

0.1UF

10V

C2850

1

2

25 45 73 87

68

6

47 94

45 94

18

MC74VHC1G08

SC70-HF

U2850

3

2

1

4

5

19

27pF

402

5%

50V

CERM

C2820

1 2

27pF

402

CERM

5%

50V

C2821

1 2

SM-3.2X2.5MM

25.0000M

CRITICAL

Y2820

2 4

1 3

200

MF-LF

5% 1/16W

402

R2820

1 2

10M

MF-LF

5%

1/16W

NO STUFF

402

R2821

1

2

37 95

87

402

MF-LF

1/16W

5%

PLACE_NEAR=U1800.P46

22

R2827

1 2

25

1K

XDP

1/16W

402

MF-LF

5%

R2889

1 2

402

MF-LF

1/16W

0

5%

R2888

1 2

34

0

5%

MF-LF

1/16W

402

R2884

1 2

0.1UF

402

10V

20%

CERM

C2880

1

2

MC74VHC1G08

SC70-HF

U2880

3

2

1

4

5

1/16W MF-LF

5%

100K

402

R2880

1

2

MF-LF

1/16W

402

5%

10K

R2850

1

2

37 95

1/16W

402

MF-LF

5%

0

R2882

1 2

17 93

5% 1/16W MF-LF

402

PLACE_NEAR=U1800.P48

22

R2829

1 2

19

19 27

27 87

0

402

5% 1/16W MF-LF

R2887

1 2

OMIT

0

5%

402

1/16W MF-LF

SILK_PART=SYS RESET

R2897

1

2

6

27 47 87 94

402

MF-LF

5% 1/16W

0

PLACE_NEAR=U2700.6

R2824

1 2

26 27

89

0

5%

MF-LF

1/16W

402

R2893

1 2

5%

402

1/16W MF-LF

10K

R2895

1

2

79 80 98

6

18 45

19 27 31 40

SOD-VESM-HF

SSM3K15FV

Q2830

3

1

2

6

18 33 27 37

MF-LF

1/16W 402

5%

10K

R2830

1

2

10 27

402

0

5%

MF-LF

1/16W

R2851

1 2

Chipset Support

SYNC_MASTER=K17_REF

SYNC_DATE=06/15/2009

PP3V3_S0

PP3V3_S5

PP3V3_S0

PM_SYSRST_L

PP3V3_S0

MAKE_BASE=TRUE

GMUX_RESET_L

BKLT_PLT_RST_L

PLT_RESET_L

MAKE_BASE=TRUE

GMUX_RESET_L

PCH_CLK32K_RTCX1

ENET_RESET_L

AP_RESET_L

LPCPLUS_RESET_L

MAKE_BASE=TRUE

LPCPLUS_RESET_L

PLT_RST_BUF_L

SDCARD_PLT_RST_L

PLT_RESET_L

PCA9557D_RESET_L

XDPPCH_PLTRST_L

MAKE_BASE=TRUE

PLT_RST_BUF_L

XDP_DBRESET_L

SMC_LRESET_L

LPC_CLK33M_SMC

LPC_CLK33M_LPCPLUS

PCH_CLK33M_PCIIN

MAKE_BASE=TRUE

GPU_CLK27M

CK505_CLK27M

MAKE_BASE=TRUE

LPC_CLK33M_GMUX_R

MAKE_BASE=TRUE

LPC_CLK33M_GMUX_R

PCH_CLK33M_PCIOUT

CK505_CLK27M

PCH_CLK25M_XTALIN

PCH_CLK32K_RTCX2_R

PCH_CLK25M_XTALOUT_R

BCM5764_CLK25M_XTALO_R

PCH_CLK32K_RTCX2

PCH_CLK25M_XTALOUT

BCM5764_CLK25M_XTALO

ENET_WAKE_LENET_WAKE_L

MAKE_BASE=TRUE

BCM5764_CLK25M_XTALI

PP3V3_ENET

LPC_CLK33M_GMUX

LPC_CLK33M_LPCPLUS_R

LPC_CLK33M_SMC_R

CPUIMVP_PGOOD

PCIE_WAKE_L

CPUIMVP_PGOOD_R

ALL_SYS_PWRGD

PM_PCH_PWRGD

28 OF 132

<SCH_NUM>

27 OF 101

6 7

17 18 19 20 21 23 24 25

26 27 28 30 34 37 40 42 46 47

48 50 51 52 54 58 62 63 68 69

72 73 80 83 84 85 87 88 99

6 7

17 18 19 20 21 23 31 35

57 66 71 72 73 83 85 99

6 7

17 18 19 20 21 23 24 25

26 27 28 30 34 37 40 42 46 47

48 50 51 52 54 58 62 63 68 69

72 73 80 83 84 85 87 88 99

6 7

17 18 19 20 21 23 24 25

26 27 28 30 34 37 40 42 46 47

48 50 51 52 54 58 62 63 68 69

72 73 80 83 84 85 87 88 99

27 87

10 27

26 27

19 27

27 37

6 7

37 73

A6

A7

A11

A5

DQ33

VDD

A10/AP

VDD

VSS

SA1

VTT

VSS

DQS4* DQS4

VSS

DQ35

VSS

CK0*

SA0

VSS DQ58 DQ59

DM7

VSS

DQ57

DQ56

DQ50 DQ51

VSS

DQS6* DQS6

VSS

DQ49

DQ48

DQ43

VSS

DM5

VSS DQ42

SDA SCL

VTT

VSS

EVENT*

DQ62

VSS

DQ63

DQS7*

DQS7

DQ60 DQ61

VSS

DQ55

DQ54

DM6

VSS

DQ53

VSS

DQ52

DQ47

VSS

DQS5

VSS

DQ46

DQ41

VSS DQ40

DQ34

VSS

DQ32

TEST

VDD

S1*

A13

CAS*

WE*

BA0

VDD

VDD CK0

A1

A3

VDD

VDD A8

A9

A12/BC*

VDD

BA2

NC

VDD

CKE0

VSS

DQS5*

VSS DQ44 DQ45

DQ39

DQ38

VSS

DM4

VSS

DQ37

DQ36

VREFCA

VDD ODT1

NC

S0*

ODT0

BA1

RAS*

VDD

CK1*

VDD

A0

CK1

A2

VDD

A4

VDD

A14

A15

CKE1

VDD

VSS

VDDSPD

KEY

(SYMBOL 2 OF 2)

BI BIBI

BI

IN

BI BI

IN

BI

IN

BI

BI BI

IN

BI BI

DQ16

DM3

DQ26 DQ27

DQ4

DQ31

DQ30

DQS3

DQS3*

DQ29

DQ28

DQ23

DQ22

DM2

DQ21

DQ20

DQ15

DQ14

RESET*

DM1

DQ13

DQ12

DQ7

DQ6

DQS0

DQS0*

DQ5

DQ24 DQ25

DQ19

DQ18

DQS2

DQS2*

DQ17

DQ11

DQ10

DQS1

DQS1*

DQ8 DQ9

DM0

DQ0 DQ1

VREFDQ

DQ3

DQ2

VSS

KEY

VSS

(SYMBOL 1 OF 2)

IN

BI BI

BI

BI BI

BI

IN IN

IN

IN IN

IN

BI BI

IN

BI BI

IN

BI

IN

BI BI

BI

IN

BI BI

BI

OUT

BI

IN

IN IN

BI BI

BI

IN

BI

BI BI

IN

BI BI

NC

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

516-0229

"Factory" (top) slot

(NONE)

SPD ADDR=0xA0(WR)/0xA1(RD)

DDR3 DECOUPLING AND GND RETURN CAPS (SPACE EVENLY AT CONNECTOR)

BOM options provided by this page:

- =I2C_SODIMMA_SDA

- =I2C_SODIMMA_SCL

Signal aliases required by this page:

- =PPSPD_S0_MEM_A (2.5 - 3.3V)

- =PP0V75_S0_MEM_VTT_A

- =PP1V5_S3_MEM_A

- =PP1V5_S0_MEM_A

Power aliases required by this page:

Page Notes

F-RT-THB

DDR3-SODIMM-DUAL-K6

J2900

9897

107

8483

119

80

78

9695

9291

90

86

89

85

109

108

79

115

101 103

102 104

73 74

136

153

170

187

129 131

141 143

130 132

140 142

147 149

157 159

146 148

158 160

163 165

175 177

164 166

174 176

181 183

191 193

180 182

192 194

137

135

154

152

171

169

188

186

198

77

122

116

120

110

114

121

197

201 202

200

125

75 76

105 106

111 112

117 118

123 124

81 82

87 88

93 94

99

100

199

126

127 128

133 134

138

139

144

145

150

151

155 156

161 162

167 168

172

173

178

179

184

185

189 190

195 196

203 204

113

29

10V

20%

402

CERM

0.1UF

C2931

1

2

2.2UF

20%

402-LF

CERM

6.3V

C2930

1

2

29

11 92

11 29 92

29

30 31

29

F-RT-THB

DDR3-SODIMM-DUAL-K6

CRITICAL

J2900

11

28

46

63

5 7

33 35

22 24

34 36

39 41

51 53

15

40 42

50 52

57 59

67 69

56 58

17

68 70

4 6

16 18

21 23

12

10

29

27

47

45

64

62

30

1 2 3

31 32

37 38

43 44

48

49

54

55

8

60

61

65 66

71 72

9

13 14

19 20

25 26

11 29 92

29

11 92

29

11 92

11 29 92

29

0.1UF

CERM 402

20% 10V

C2936

1

2

CERM

2.2UF

6.3V

20%

402-LF

C2935

1

2

29

30 45 46

17 25 26 30 32 42 47 48 63 88 94

11 92

29

MF-LF

1/16W

402

5%

10K

R2941

1

2

402

5% 1/16W MF-LF

10K

R2940

1

2

6.3V

402-LF

CERM

20%

2.2UF

C2940

1

2

603

6.3V X5R

20%

10UF

C2900

1

2

20%

603

X5R

10UF

6.3V

C2901

1

2

0.1UF

20% 10V

402

CERM

C2910

1

2

10V

20% CERM

402

0.1UF

C2911

1

2

402

10V

20%

0.1UF

CERM

C2912

1

2

0.1UF

20% 10V CERM 402

C2913

1

2

0.1UF

20% CERM

402

10V

C2914

1

2

10V CERM 402

20%

0.1UF

C2915

1

2

CERM 402

20%

0.1UF

10V

C2916

1

2

CERM 402

20%

0.1UF

10V

C2917

1

2

CERM 402

20%

0.1UF

10V

C2918

1

2

CERM 402

20%

0.1UF

10V

C2919

1

2

0.1UF

CERM 402

20% 10V

C2920

1

2

CERM 402

20%

0.1UF

10V

C2921

1

2

CERM 402

20%

0.1UF

10V

C2922

1

2

CERM 402

20%

0.1UF

10V

C2923

1

2

SYNC_MASTER=MASTER

SYNC_DATE=MASTER

DDR3 SO-DIMM Connector A

PP1V5_S3

PP0V75_S3_MEM_VREFCA_A

=MEM_A_DQ<2> =MEM_A_DQ<3>

PP0V75_S3_MEM_VREFDQ_A

=MEM_A_DQ<1>

=MEM_A_DQ<0>

MEM_A_DM<0>

=MEM_A_DQ<9>

=MEM_A_DQ<8>

=MEM_A_DQS_N<1> =MEM_A_DQS_P<1>

=MEM_A_DQ<10> =MEM_A_DQ<11>

=MEM_A_DQ<17>

=MEM_A_DQS_N<2> =MEM_A_DQS_P<2>

=MEM_A_DQ<18> =MEM_A_DQ<19>

=MEM_A_DQ<25>

=MEM_A_DQ<24>

=MEM_A_DQ<5>

MEM_A_DQS_N<0> MEM_A_DQS_P<0>

=MEM_A_DQ<6> =MEM_A_DQ<7>

=MEM_A_DQ<12> =MEM_A_DQ<13>

=MEM_A_DM<1> MEM_RESET_L

=MEM_A_DQ<14> =MEM_A_DQ<15>

=MEM_A_DQ<20> =MEM_A_DQ<21>

=MEM_A_DM<2>

=MEM_A_DQ<22> =MEM_A_DQ<23>

=MEM_A_DQ<28> =MEM_A_DQ<29>

=MEM_A_DQS_N<3> =MEM_A_DQS_P<3>

=MEM_A_DQ<30> =MEM_A_DQ<31>

=MEM_A_DQ<4>

=MEM_A_DQ<26>

=MEM_A_DM<3>

=MEM_A_DQ<16>

PP3V3_S0

MEM_A_CKE<1>

MEM_A_A<15> MEM_A_A<14>

MEM_A_A<2>

MEM_A_CLK_P<1>

MEM_A_A<0>

MEM_A_CLK_N<1>

MEM_A_RAS_L

MEM_A_BA<1>

MEM_A_ODT<0>

MEM_A_CS_L<0>

MEM_A_ODT<1>

=MEM_A_DQ<36> MEM_A_DQ<37>

=MEM_A_DM<4>

=MEM_A_DQ<38> =MEM_A_DQ<39>

=MEM_A_DQ<45>

=MEM_A_DQ<44>

=MEM_A_DQS_N<5>

MEM_A_CKE<0>

MEM_A_BA<2>

MEM_A_A<12> MEM_A_A<9>

MEM_A_A<8>

MEM_A_A<3> MEM_A_A<1>

MEM_A_CLK_P<0>

MEM_A_BA<0>

MEM_A_WE_L MEM_A_CAS_L

MEM_A_A<13> MEM_A_CS_L<1>

=MEM_A_DQ<32>

=MEM_A_DQ<34>

=MEM_A_DQ<40> =MEM_A_DQ<41>

=MEM_A_DQ<46>

=MEM_A_DQS_P<5>

=MEM_A_DQ<47>

=MEM_A_DQ<52> =MEM_A_DQ<53>

=MEM_A_DM<6>

=MEM_A_DQ<54> =MEM_A_DQ<55>

=MEM_A_DQ<61>

=MEM_A_DQ<60>

=MEM_A_DQS_P<7>

=MEM_A_DQS_N<7>

=MEM_A_DQ<63>

=MEM_A_DQ<62>

MEM_EVENT_A_L

SMBUS_PCH_CLK

SMBUS_PCH_DATA

=MEM_A_DQ<42>

=MEM_A_DM<5>

=MEM_A_DQ<43>

=MEM_A_DQ<48> =MEM_A_DQ<49>

=MEM_A_DQS_P<6>

=MEM_A_DQS_N<6>

=MEM_A_DQ<51>

=MEM_A_DQ<50>

=MEM_A_DQ<56> =MEM_A_DQ<57>

=MEM_A_DM<7>

=MEM_A_DQ<59>

=MEM_A_DQ<58>

MEM_A_SA<0>

MEM_A_CLK_N<0>

=MEM_A_DQ<35>

=MEM_A_DQS_P<4>

=MEM_A_DQS_N<4>

PP0V75_S0_DDRVTT

MEM_A_SA<1>

MEM_A_A<10>

=MEM_A_DQ<33>

MEM_A_A<5>

MEM_A_A<11> MEM_A_A<7>

MEM_A_A<6>

=MEM_A_DQ<27>

MEM_A_A<4>

29 OF 132

<SCH_NUM>

28 OF 101

6 7

30 31 67 72

32

6 7

17 18 19 20

21 23 24 25 26 27 30 34

37 40 42 46 47

48 50 51 52 54 58 62 63

68 69 72 73 80

83 84 85 87 88 99

6 7

30 31 67

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

CPU CHANNEL B DQS 6 -> DIMM B DQS 6

CPU CHANNEL A DQS 5 -> DIMM A DQS 5

CPU CHANNEL A DQS 2 -> DIMM A DQS 2

CPU CHANNEL A DQS 3 -> DIMM A DQS 3

CPU CHANNEL A DQS 6 -> DIMM A DQS 6

CPU CHANNEL A DQS 7 -> DIMM A DQS 7

CPU CHANNEL A DQS 4 -> DIMM A DQS 4

CPU CHANNEL A DQS 1 -> DIMM A DQS 1

CPU CHANNEL B DQS 7 -> DIMM B DQS 7

CPU CHANNEL B DQS 0 -> DIMM B DQS 0

CPU CHANNEL B DQS 1 -> DIMM B DQS 1

CPU CHANNEL B DQS 2 -> DIMM B DQS 2

CPU CHANNEL A DQS 0 -> DIMM A DQS 0

CPU CHANNEL B DQS 5 -> DIMM B DQS 5

CPU CHANNEL B DQS 4 -> DIMM B DQS 4

CPU CHANNEL B DQS 3 -> DIMM B DQS 3

SYNC_DATE=MASTER

SYNC_MASTER=MASTER

DDR3 Byte/Bit Swaps

=MEM_A_DQ<20> =MEM_A_DQ<22>

MAKE_BASE=TRUE

MEM_B_DQ<16>

MAKE_BASE=TRUE

MEM_B_DQ<29>

=MEM_B_DQ<31>

=MEM_B_DQ<37>

=MEM_B_DQ<39>

=MEM_B_DQ<33>

MAKE_BASE=TRUE

MEM_B_DQS_N<5>

MAKE_BASE=TRUE

MEM_B_DM<4>

MAKE_BASE=TRUE

MEM_B_DQ<24>

MAKE_BASE=TRUE

MEM_B_DQS_N<3>

MEM_B_DQS_N<0>

MAKE_BASE=TRUE

MEM_B_DQS_P<0>

MAKE_BASE=TRUE

MEM_B_DM<0>

MAKE_BASE=TRUE

MEM_B_DQ<23>

MAKE_BASE=TRUE

MEM_B_DQ<22>

=MEM_B_DM<3>

=MEM_B_DQ<19> =MEM_B_DQ<22>

=MEM_B_DQ<27>

=MEM_B_DQS_P<3>

=MEM_B_DQ<17>

=MEM_B_DQ<16>

=MEM_B_DQ<8>

=MEM_B_DQ<15>

MAKE_BASE=TRUE

MEM_B_DM<3>

MEM_B_DQS_P<3>

MAKE_BASE=TRUE

MEM_B_DQ<19>

MEM_B_DQ<8>

MAKE_BASE=TRUE

MEM_B_DQ<12>

MEM_B_DQ<9>

MAKE_BASE=TRUE

MEM_B_DQS_N<2>

MAKE_BASE=TRUE

MEM_B_DQ<15>

MEM_B_DM<1>

MAKE_BASE=TRUE

MEM_B_DQS_P<2> MEM_B_DM<2>

MAKE_BASE=TRUE

=MEM_B_DQ<18>

MAKE_BASE=TRUE

MEM_B_DQ<21>

MAKE_BASE=TRUE

MEM_B_DQ<20>

=MEM_B_DQS_P<2>

MAKE_BASE=TRUE

MEM_B_DQ<14>

MAKE_BASE=TRUE

MEM_B_DQ<1>

MAKE_BASE=TRUE

MEM_B_DQS_N<1>

=MEM_B_DM<1>

=MEM_B_DM<2>

MEM_B_DQ<4>

MAKE_BASE=TRUE

MEM_B_DQ<3>

MAKE_BASE=TRUE

MEM_B_DQ<2>

MAKE_BASE=TRUE

MEM_B_DQS_P<1>

MAKE_BASE=TRUE

MEM_B_DQS_N<0>

MAKE_BASE=TRUE

MEM_B_DQ<0>

MEM_B_DM<0> =MEM_B_DQ<7> =MEM_B_DQ<6>

=MEM_B_DQ<4>

MAKE_BASE=TRUE

MEM_B_DQ<7>

MAKE_BASE=TRUE

MEM_B_DQ<6>

=MEM_B_DQ<24>

=MEM_B_DQ<28>

MEM_A_DQ<4>

MAKE_BASE=TRUE

=MEM_B_DQ<12>

MAKE_BASE=TRUE

MEM_B_DQ<56>

=MEM_B_DQ<61>

MAKE_BASE=TRUE

MEM_B_DQ<58>

MAKE_BASE=TRUE

MEM_B_DQ<57>

=MEM_B_DQ<60>

MAKE_BASE=TRUE

MEM_B_DQ<59>

=MEM_B_DQ<59>

MAKE_BASE=TRUE

MEM_B_DQ<61>

=MEM_B_DQ<57>

MAKE_BASE=TRUE

MEM_B_DQ<60>

=MEM_B_DQ<56>

MAKE_BASE=TRUE

MEM_B_DQ<63>

=MEM_B_DQ<63>

MAKE_BASE=TRUE

MEM_B_DM<7>

=MEM_B_DM<7>

MAKE_BASE=TRUE

MEM_B_DQ<62>

=MEM_B_DQ<62>

MAKE_BASE=TRUE

MEM_B_DQS_N<7>

=MEM_B_DQS_N<7>

MAKE_BASE=TRUE

MEM_B_DQS_P<7>

=MEM_B_DQS_P<7>

MAKE_BASE=TRUE

MEM_B_DQ<48>

MAKE_BASE=TRUE

MEM_B_DQ<49>

=MEM_B_DQ<48>

MAKE_BASE=TRUE

MEM_B_DQ<50>

=MEM_B_DQ<51>

MAKE_BASE=TRUE

MEM_B_DQ<51>

=MEM_B_DQ<49>

MAKE_BASE=TRUE

MEM_B_DQ<52>

=MEM_B_DQ<53>

MAKE_BASE=TRUE

MEM_B_DQ<53>

MAKE_BASE=TRUE

MEM_B_DQ<54>

=MEM_B_DQ<55>

=MEM_B_DM<6>

MAKE_BASE=TRUE

MEM_B_DQ<55>

=MEM_B_DQ<50>

MAKE_BASE=TRUE

MEM_B_DQS_P<6>

=MEM_B_DQS_P<6>

MEM_B_DQS_N<6>

MAKE_BASE=TRUE

=MEM_B_DQS_N<6>

MEM_B_DQ<41>

MAKE_BASE=TRUE

=MEM_B_DQ<44>

MAKE_BASE=TRUE

MEM_B_DQ<40>

MAKE_BASE=TRUE

MEM_B_DQ<43>

MEM_B_DQ<44>

MAKE_BASE=TRUE

MEM_B_DQ<46>

MAKE_BASE=TRUE

MEM_B_DM<5>

=MEM_B_DM<5> =MEM_B_DQ<47>

MAKE_BASE=TRUE

MEM_B_DQS_P<5>

=MEM_B_DQS_P<5>

=MEM_B_DQS_N<5>

MAKE_BASE=TRUE

MEM_B_DQ<32>

=MEM_B_DQ<36>

MAKE_BASE=TRUE

MEM_B_DQ<33>

MAKE_BASE=TRUE

MEM_B_DQ<36>

=MEM_B_DQ<32>

MAKE_BASE=TRUE

MEM_B_DQ<35>

MAKE_BASE=TRUE

MEM_B_DQ<34>

MAKE_BASE=TRUE

MEM_B_DQ<37> MEM_B_DQ<37>

MEM_B_DQ<38>

MAKE_BASE=TRUE

=MEM_B_DQ<38>

MEM_B_DQS_P<4>

MAKE_BASE=TRUE

=MEM_B_DQS_P<4>

MAKE_BASE=TRUE

MEM_B_DQ<39>

=MEM_B_DQ<35>

MAKE_BASE=TRUE

MEM_B_DQS_N<4>

=MEM_B_DQS_N<4>

MAKE_BASE=TRUE

MEM_B_DQ<25>

=MEM_B_DQ<25>

MAKE_BASE=TRUE

MEM_B_DQ<27>

=MEM_B_DQ<30>

MAKE_BASE=TRUE

MEM_B_DQ<26>

=MEM_B_DQ<26>

MEM_B_DQ<31>

MAKE_BASE=TRUE

=MEM_B_DQS_N<3>

MEM_B_DQ<17>

MAKE_BASE=TRUE

=MEM_B_DQ<21>

MEM_B_DQ<18>

MAKE_BASE=TRUE

=MEM_B_DQ<20>

=MEM_B_DQ<23>

=MEM_B_DQS_N<2>

=MEM_B_DQ<9>

MEM_B_DQ<10>

MAKE_BASE=TRUE

=MEM_B_DQ<10>

MEM_B_DQ<11>

MAKE_BASE=TRUE

=MEM_B_DQ<11>

=MEM_B_DQ<13>

=MEM_B_DQ<14>

=MEM_B_DQS_P<1>

=MEM_B_DQS_N<1>

=MEM_B_DQ<0>

=MEM_B_DQ<5>

=MEM_B_DQ<1>

=MEM_B_DQ<3>

=MEM_B_DQ<2>

MEM_B_DQS_P<0>

=MEM_A_DQ<7> =MEM_A_DQ<6>

=MEM_A_DQ<4>

=MEM_A_DQ<11>

=MEM_A_DM<1>

=MEM_A_DQS_P<1>

=MEM_A_DQ<5>

=MEM_A_DQ<2>

=MEM_A_DQ<0>

=MEM_A_DQ<10>

=MEM_A_DQ<12>

=MEM_A_DQ<14>

=MEM_A_DQ<8> =MEM_A_DQ<9> =MEM_A_DQ<15>

=MEM_A_DQS_N<1>

=MEM_A_DQ<3>

=MEM_A_DQ<1>

MEM_A_DM<0>

MEM_A_DQS_P<0>

MAKE_BASE=TRUE

MEM_A_DM<0>

MAKE_BASE=TRUE

MEM_A_DQS_N<0> MEM_A_DQS_P<0>

MAKE_BASE=TRUE

MEM_A_DQ<1>

MAKE_BASE=TRUE

MEM_A_DQ<11>

MEM_A_DQ<5>

MAKE_BASE=TRUE

MEM_A_DQ<6>

MAKE_BASE=TRUE

MEM_A_DQ<7>

MEM_A_DQ<2>

MAKE_BASE=TRUE

MEM_A_DQ<14>

MAKE_BASE=TRUE

MEM_A_DQ<13>

MAKE_BASE=TRUE

MEM_A_DQ<8>

MEM_A_DQS_N<1>

MAKE_BASE=TRUE

MEM_A_DQ<9>

MAKE_BASE=TRUE

MEM_A_DQ<10>

MAKE_BASE=TRUE

MEM_A_DQ<12>

MAKE_BASE=TRUE

MEM_A_DQ<15>

MAKE_BASE=TRUE

MEM_A_DQS_P<1>

MAKE_BASE=TRUE

MEM_A_DM<1>

MAKE_BASE=TRUE

MEM_A_DQ<0>

MAKE_BASE=TRUE

MEM_A_DQ<3>

MAKE_BASE=TRUE

=MEM_A_DQ<19>

=MEM_A_DQS_P<6>

=MEM_A_DQS_N<6>

=MEM_A_DQ<41>

=MEM_A_DQ<40>

=MEM_A_DQ<46>

=MEM_A_DQ<45>

=MEM_A_DQ<43>

=MEM_A_DQ<36>

=MEM_A_DQ<34>

=MEM_A_DQ<21>

=MEM_A_DQ<23>

=MEM_A_DQS_N<2> =MEM_A_DQS_P<2> =MEM_A_DM<2>

=MEM_A_DQ<60>

=MEM_A_DQ<59> =MEM_A_DQ<58> =MEM_A_DQ<57>

=MEM_A_DQ<61>

=MEM_A_DQ<56>

=MEM_A_DM<7> =MEM_A_DQ<62> =MEM_A_DQ<63>

=MEM_A_DQ<52>

=MEM_A_DQS_N<7> =MEM_A_DQS_P<7>

=MEM_A_DQ<48>

=MEM_A_DQ<55> =MEM_A_DQ<51>

=MEM_A_DQ<50> =MEM_A_DQ<54> =MEM_A_DQ<53>

=MEM_A_DQ<49>

=MEM_A_DM<6>

=MEM_A_DQ<47>

=MEM_A_DQ<44>

=MEM_A_DQ<42>

=MEM_A_DM<5>

=MEM_A_DQS_P<5>

=MEM_A_DQS_N<5>

=MEM_A_DQ<32>

=MEM_A_DQ<35>

=MEM_A_DQ<38>

=MEM_A_DQ<39> MEM_A_DQ<37>

=MEM_A_DQS_P<4>

=MEM_A_DQ<33>

=MEM_A_DM<4>

=MEM_A_DQS_N<4>

=MEM_A_DQ<29>

=MEM_A_DQ<28>

=MEM_A_DQ<24> =MEM_A_DQ<31> =MEM_A_DQ<30>

=MEM_A_DQ<26> =MEM_A_DQ<25>

=MEM_A_DQS_P<3>

=MEM_A_DQS_N<3>

MEM_A_DQ<17>

MAKE_BASE=TRUE

MEM_A_DQ<29>

MAKE_BASE=TRUE

MEM_A_DQS_P<3>

MAKE_BASE=TRUE

MEM_A_DQS_N<3>

MEM_A_DQ<16>

MAKE_BASE=TRUE

MEM_A_DQ<19>

MAKE_BASE=TRUE

MEM_A_DQ<20>

MAKE_BASE=TRUE

MEM_A_DQ<23>

MAKE_BASE=TRUE

MEM_A_DQS_N<2>

MEM_A_DQS_P<5>

MAKE_BASE=TRUE

MEM_A_DQS_N<5>

MEM_A_DQ<33>

MAKE_BASE=TRUE

MEM_A_DQ<32>

MAKE_BASE=TRUE

MEM_A_DQ<36>

MAKE_BASE=TRUE

MEM_A_DQ<38>

MAKE_BASE=TRUE

MEM_A_DQ<37>

MAKE_BASE=TRUE

MEM_A_DQS_P<4>

MAKE_BASE=TRUE

MEM_A_DM<4>

MAKE_BASE=TRUE

MEM_A_DQS_N<4>

MAKE_BASE=TRUE

MEM_A_DQ<27>

MAKE_BASE=TRUE

MEM_A_DQ<26>

MAKE_BASE=TRUE

MEM_A_DQ<49>

MAKE_BASE=TRUE

MEM_A_DQ<51> MEM_A_DQ<50>

MAKE_BASE=TRUE

MEM_A_DQ<54>

MAKE_BASE=TRUE

MEM_A_DQ<52>

MEM_A_DQ<55>

MAKE_BASE=TRUE

MEM_A_DM<6>

MEM_A_DQS_P<6>

MAKE_BASE=TRUE

MEM_A_DQ<40>

MEM_A_DQ<41>

MAKE_BASE=TRUE

MEM_A_DQ<42>

MAKE_BASE=TRUE

MEM_A_DQ<44>

MAKE_BASE=TRUE

MEM_A_DM<5>

MAKE_BASE=TRUE

MEM_A_DQ<48>

MAKE_BASE=TRUE

MEM_A_DQ<63>

MEM_A_DQ<59>

MAKE_BASE=TRUE

MEM_A_DQ<58>

MAKE_BASE=TRUE

MEM_A_DQ<56>

MAKE_BASE=TRUE

MEM_A_DQ<57>

MAKE_BASE=TRUE

MEM_A_DQ<60>

MAKE_BASE=TRUE

MEM_A_DQ<61>

MAKE_BASE=TRUE

MEM_A_DM<7>

MEM_A_DQ<62>

MAKE_BASE=TRUE

MEM_A_DQS_P<7>

MEM_A_DQ<53>

MAKE_BASE=TRUE

MEM_A_DQS_N<0>

MAKE_BASE=TRUE

MEM_B_DQ<28>

MEM_A_DQS_P<2>

MAKE_BASE=TRUE

MEM_A_DM<2>

MAKE_BASE=TRUE

MEM_A_DQ<22> MEM_A_DQ<21>

MAKE_BASE=TRUE

=MEM_A_DQ<17> =MEM_A_DQ<16>

=MEM_A_DM<3> =MEM_A_DQ<27>

MEM_A_DQ<30>

MAKE_BASE=TRUE

MEM_B_DM<6>

=MEM_B_DM<4>

=MEM_B_DQ<29>

MAKE_BASE=TRUE

MEM_B_DQ<30>

=MEM_B_DQ<52>

=MEM_B_DQ<54>

MEM_A_DQ<18>

MAKE_BASE=TRUE

MEM_A_DQS_N<7>

MAKE_BASE=TRUE

MEM_A_DQS_N<6>

MAKE_BASE=TRUE

MEM_A_DQ<46>

MAKE_BASE=TRUE

MEM_A_DQ<45>

MAKE_BASE=TRUE

MEM_A_DQ<43>

MAKE_BASE=TRUE

MEM_A_DQ<34>

MAKE_BASE=TRUE

MEM_A_DQ<28>

MAKE_BASE=TRUE

MEM_A_DQ<31>

MAKE_BASE=TRUE

MEM_A_DM<3>

MEM_A_DQ<25>

MAKE_BASE=TRUE

MEM_B_DQ<45>

MAKE_BASE=TRUE

MEM_B_DQ<13>

MAKE_BASE=TRUE

MEM_B_DQ<5>

MEM_A_DQ<39>

MAKE_BASE=TRUE

MEM_A_DQ<24>

=MEM_A_DQ<18>

=MEM_A_DQ<13>

MEM_A_DQ<35>

MAKE_BASE=TRUE

=MEM_B_DQ<58>

MEM_A_DQ<47>

MAKE_BASE=TRUE MAKE_BASE=TRUE

MEM_B_DQ<47>

MEM_B_DQ<42>

MAKE_BASE=TRUE

=MEM_B_DQ<42>

=MEM_B_DQ<46>

=MEM_B_DQ<41>

=MEM_B_DQ<45>

=MEM_B_DQ<40>

=MEM_B_DQ<43>

30 OF 132

<SCH_NUM>

29 OF 101

28

11 92

30

11 92

11 29 30 92

11 92

30

11 92

30

11 92

30

11 92

30

11 92

11 29 30 92

11 92

11 29 30 92

30

11 92

30

11 92

30

11 92 30

11 92

11 92 30

11 92

11 92 30

11 92

11 92 30

30

11 92 30

11 92

11 92 30

30

11 92 30

30

11 92 30

11 92

11 92 30

11 92

11 29 30 92 11 29 30 92

11 92 30

11 92

30

11 92

30

11 92

30

11 92

30

11 92 30

11 92

30

11 92 30

30

11 29 30 92

28

11 28 29 92

11 92

28

11 28 29 92

28

11 92

11 28 29 92

11 92

11 28 29 92

11 92

28

11 92

30

11 92

30

11 92

28

11 92

30

11 92 11 92

11 92 30

30

IN

BI

BI BI

OUT

BI IN

IN

IN IN

IN

IN IN

BI BI

BI

IN

BI BI

IN

BI BI

NC

IN

VDD

A1

A3

VDD

A5

A8

VDD

A9

VDD

A12/BC*

VSS

DQ42 DQ43

DQ48 DQ49

VSS

DQ41

DQS4*

DM5

VDD

CKE1

A15 A14

VDD

A11

A7

A6

VDD

A4

A2

CK1

A0

VDD

CK1*

VDD

RAS*

BA1

ODT0

S0*

NC

ODT1

VDD

VREFCA

VDD

DQ36 DQ37

VSS

DM4

VSS

VSS DQ38 DQ39

DQ45

DQ44

VSS

DQS5*

VSS

CKE0

VDD NC

BA2

CK0

VDD

BA0

WE*

A13 S1*

VDD

TEST

DQ33

DQ32

VSS

DQ34

DQ40

VSS

DQ46

VSS

DQS5

VSS

DQ47

DQ52

VSS

DQ53

VSS

DM6

DQ54 DQ55

VSS

DQ61

DQ60

DQS7

DQS7*

DQ63

VSS DQ62

EVENT*

VSS

VTT

SCL

SDA

VSS

DQS6

DQS6*

VSS

DQ51

DQ50

A10/AP

VDD

CK0*

DQ35

VSS

DQS4

VSS

CAS*

VDD

DM7

VSS

DQ56

MTG PIN

MTG PIN MTG PIN MTG PIN MTG PIN

MTG PIN

VSS

DQ57

VTT

SA1

SA0

DQ58

VSS

DQ59

VSS

VDDSPD

MTG PIN

MTG PINS

KEY

(2 OF 2)

BI BI

IN

BI

IN

BI

BI BI

IN

BI BI

BI

DQ2 DQ3

VREFDQ

DQ1

DQ0

DM0

DQ9

DQ8

DQS1* DQS1

DQ10 DQ11

DQ17

DQS2* DQS2

DQ18 DQ19

DQ25

DQ24

DQ5

DQS0*

DQS0

DQ6 DQ7

DQ12 DQ13

DM1

RESET*

DQ14 DQ15

DQ20 DQ21

DM2

DQ22 DQ23

DQ28 DQ29

DQS3*

DQS3

DQ30 DQ31

DQ4

DQ27

DQ26

DM3

DQ16

(1 OF 2)

VSS

KEY

VSS

IN

BI BI

BI

BI BI

IN IN

IN

BI

IN

IN IN

BI BI

IN

BI BI

IN

BI BI

IN

BI

BI BI

BI

IN

BI

BI BI

BI

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

Page Notes

- =PP1V5_S0_MEM_B

SPD ADDR=0xA4(WR)/0xA5(RD)

516S0806

- =PP0V75_S0_MEM_VTT_B

- =PPSPD_S0_MEM_B (2.5 - 3.3V)

- =PP1V5_S3_MEM_B

"Expansion" (bottom) slot

Signal aliases required by this page:

- =I2C_SODIMMB_SDA

BOM options provided by this page:

(NONE)

DDR3 DECOUPLING AND GND RETURN CAPS (SPACE EVENLY AT CONNECTOR)

- =I2C_SODIMMB_SCL

Power aliases required by this page:

11 92

29

28 45 46

17 25 26 28 32 42 47 48 63 88 94

10V

20%

402

CERM

0.1UF

C3131

1

2

11 92

29

11 29 92

29

CERM 402-LF

6.3V

20%

2.2UF

C3130

1

2

5%

MF-LF 402

10K

1/16W

R3141

1

2

MF-LF

1/16W

402

5%

10K

R3140

1

2

2.2UF

6.3V

402-LF

CERM

20%

C3140

1

2

603

6.3V X5R

20%

10UF

C3100

1

2

20%

603

X5R

10UF

6.3V

C3101

1

2

0.1UF

20% 10V

402

CERM

C3110

1

2

20% 10V CERM 402

0.1UF

C3111

1

2

402

10V

20%

0.1UF

CERM

C3112

1

2

20% 10V

0.1UF

402

CERM

C3113

1

2

29

20% CERM

402

10V

0.1UF

C3114

1

2

402

20%

0.1UF

CERM

10V

C3115

1

2

CERM 402

20%

0.1UF

10V

C3116

1

2

CERM 402

20%

0.1UF

10V

C3117

1

2

CERM 402

20%

0.1UF

10V

C3118

1

2

CERM 402

20%

0.1UF

10V

C3119

1

2

0.1UF

CERM 402

20% 10V

C3120

1

2

CERM 402

20%

0.1UF

10V

C3121

1

2

CERM 402

20%

0.1UF

10V

C3122

1

2

CERM 402

20%

0.1UF

10V

C3123

1

2

29

11 92

F-RT-BGA6

DDR3-SODIMM

J3100

9897

107

8483

119

80

78

9695

9291

90

86

89

85

109

108

79

115

101 103

102 104

73 74

136

153

170

187

129 131

141 143

130 132

140 142

147 149

157 159

146 148

158 160

163 165

175 177

164 166

174 176

181 183

191 193

180 182

192 194

137

135

154

152

171

169

188

186

198

77

122

116

120

110

114

121

197

201 202

200

125

75 76

105 106

111 112

117 118

123 124

81 82

87 88

93 94

99

100

199

126

127 128

133 134

138

139

144

145

150

151

155 156

161 162

167 168

172

173

178

179

184

185

189 190

195 196

205 206 207 208 209 210 211 212

203 204

113

11 29 92

29

28 31

29

F-RT-BGA6

DDR3-SODIMM

CRITICAL

J3100

11

28

46

63

5 7

33 35

22 24

34 36

39 41

51 53

15

40 42

50 52

57 59

67 69

56 58

17

68 70

4 6

16 18

21 23

12

10

29

27

47

45

64

62

30

1 2 3

31 32

37 38

43 44

48

49

54

55

8

60

61

65 66

71 72

9

13 14

19 20

25 26

11 29 92

29

11 92

29

11 92

29

11 92

29

CERM 402

10V

0.1UF

20%

C3136

1

2

2.2UF

6.3V CERM

20%

402-LF

C3135

1

2

29

DDR3 SO-DIMM Connector B

SYNC_DATE=MASTER

SYNC_MASTER=MASTER

PP3V3_S0

MEM_B_SA<0>

PP0V75_S0_DDRVTT

=MEM_B_DM<5>

=MEM_B_DQS_P<4>

MEM_B_DQ<37>

=MEM_B_DQ<62>

=MEM_B_DQ<50>

=MEM_B_DQ<16>

=MEM_B_DM<3>

=MEM_B_DQ<26> =MEM_B_DQ<27>

=MEM_B_DQ<4>

=MEM_B_DQ<31>

=MEM_B_DQ<30>

=MEM_B_DQS_P<3>

=MEM_B_DQS_N<3>

=MEM_B_DQ<29>

=MEM_B_DQ<28>

=MEM_B_DQ<23>

=MEM_B_DQ<22>

=MEM_B_DM<2>

=MEM_B_DQ<21>

=MEM_B_DQ<20>

=MEM_B_DQ<15>

=MEM_B_DQ<14>

MEM_RESET_L

=MEM_B_DM<1>

=MEM_B_DQ<12>

=MEM_B_DQ<7>

=MEM_B_DQ<6>

MEM_B_DQS_P<0>

MEM_B_DQS_N<0>

=MEM_B_DQ<5>

=MEM_B_DQ<24> =MEM_B_DQ<25>

=MEM_B_DQ<19>

=MEM_B_DQ<18>

=MEM_B_DQS_P<2>

=MEM_B_DQS_N<2>

=MEM_B_DQ<17>

=MEM_B_DQ<11>

=MEM_B_DQ<10>

=MEM_B_DQS_P<1>

=MEM_B_DQS_N<1>

=MEM_B_DQ<8> =MEM_B_DQ<9>

MEM_B_DM<0>

=MEM_B_DQ<0> =MEM_B_DQ<1>

PP0V75_S3_MEM_VREFDQ_B

=MEM_B_DQ<3>

=MEM_B_DQ<2>

=MEM_B_DQ<58>

MEM_B_SA<1>

=MEM_B_DQ<57>

=MEM_B_DQ<56>

=MEM_B_DM<7>

MEM_B_CAS_L

=MEM_B_DQ<35>

MEM_B_CLK_N<0>

MEM_B_A<10>

=MEM_B_DQ<51>

=MEM_B_DQS_N<6> =MEM_B_DQS_P<6>

SMBUS_PCH_DATA SMBUS_PCH_CLK

MEM_EVENT_A_L

=MEM_B_DQ<63>

=MEM_B_DQS_N<7> =MEM_B_DQS_P<7>

=MEM_B_DQ<60> =MEM_B_DQ<61>

=MEM_B_DQ<55>

=MEM_B_DQ<54>

=MEM_B_DM<6>

=MEM_B_DQ<53>

=MEM_B_DQ<52>

=MEM_B_DQ<47>

=MEM_B_DQS_P<5>

=MEM_B_DQ<46>

=MEM_B_DQ<40>

=MEM_B_DQ<32> =MEM_B_DQ<33>

MEM_B_CS_L<1>

MEM_B_A<13>

MEM_B_WE_L

MEM_B_BA<0>

MEM_B_CLK_P<0>

MEM_B_BA<2>

MEM_B_CKE<0>

=MEM_B_DQS_N<5>

=MEM_B_DQ<44> =MEM_B_DQ<45>

=MEM_B_DQ<39>

=MEM_B_DQ<38>

=MEM_B_DM<4>

=MEM_B_DQ<37>

=MEM_B_DQ<36>

PP0V75_S3_MEM_VREFCA_B

MEM_B_CS_L<0>

MEM_B_BA<1>

MEM_B_CLK_N<1>

MEM_B_A<0>

MEM_B_A<2>

MEM_B_A<4>

MEM_B_A<6>

MEM_B_A<7>

MEM_B_A<11>

MEM_B_A<14>

MEM_B_A<15>

MEM_B_CKE<1>

=MEM_B_DQS_N<4>

=MEM_B_DQ<41>

=MEM_B_DQ<49>

=MEM_B_DQ<48>

=MEM_B_DQ<43>

=MEM_B_DQ<42>

MEM_B_A<12> MEM_B_A<9>

MEM_B_A<8> MEM_B_A<5>

MEM_B_A<1>

PP1V5_S3

=MEM_B_DQ<13>

=MEM_B_DQ<59>

MEM_B_ODT<0>

MEM_B_RAS_L

MEM_B_CLK_P<1>

MEM_B_ODT<1>

MEM_B_A<3>

31 OF 132

<SCH_NUM>

30 OF 101

6 7

17 18 19 20 21

23 24 25 26 27 28 34 37 40

42 46 47 48 50 51

52 54 58 62 63 68 69 72 73

80 83 84 85 87 88

99

6 7

28 31 67

32

6 7

28 31 67 72