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K18
User Manual
101 pgs2.15 Mb0

Apple K18 User Manual

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3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.
8
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT
3
B
7
ECNREV
BRANCH
DRAWING NUMBER
REVISION
SIZE
D
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
DRAWING TITLE
THE POSESSOR AGREES TO THE FOLLOWING:
Apple Inc.
SHEET
R
DATE
D
A
C
THE INFORMATION CONTAINED HEREIN IS THE
2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
C
3456
D
B
8 7 6 5 4 2 1
12
APPD
CK
DESCRIPTION OF REVISION
TABLE_TABLEOFCONTENTS_HEAD
DESCRIPTION
REFERENCE DES
BOM OPTION
QTY
PART NUMBER
CRITICAL
TABLE_TABLEOFCONTENTS_HEAD
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM
DRAWING
TABLE_TABLEOFCONTENTS_HEAD
02/01/10
SCHEM,WHITE_ARROW,MLB,K18
Schematic / PCB #’s
ALIASES RESOLVED
1 OF 101
<BRANCH>
<ECN><REV>
<SCH_NUM>
<E4LABEL>
1 OF 132
<ECO_DESCRIPTION>
<ECODATE>
06/15/2009
49
45
SMC
K17_REF
05/29/2009
48
44
Front Flex Support
K19_MLB
06/15/2009
46
43
External USB Connectors
K17_REF
10/01/2009
45
42
SATA Connectors
T27_REF
05/29/2009
43
41
FireWire Ports
K19_MLB
05/29/2009
42
40
FireWire Port Power
K19_MLB
05/29/2009
41
39
FireWire LLC/PHY (FW643)
K19_MLB
06/15/2009
40
38
Ethernet Connector
K17_REF
08/20/2009
39
37
Ethernet PHY (Caesar II/IV)
T27_REF
10/06/2009
37
36
USB HUB 2
K23F
10/07/2009
36
35
USB HUB 1
K18_MLB
08/26/2009
35
34
SecureDigital Card Reader
T27_REF
06/15/2009
34
33
X16/ALS/CAMERA CONNECTOR
K18_COMMS
06/15/2009
33
32
FSB/DDR3/FRAMEBUF Vref Margining
K17_REF
06/15/2009
32
31
CPU Memory S3 Support
K17_REF
MASTER
31
30
DDR3 SO-DIMM Connector B
MASTER
MASTER
30
29
DDR3 Byte/Bit Swaps
MASTER
MASTER
29
28
DDR3 SO-DIMM Connector A
MASTER
06/15/2009
28
27
Chipset Support
K17_REF
06/23/2009
27
26
Clock (CK505)
K17_MLB
06/15/2009
26
25
eXtended Debug Port (XDP)
K17_REF
06/15/2009
25
24
CPU/PCH GFX Decoupling
K17_REF
06/15/2009
24
23
PCH Non-GFX Decoupling
K17_REF
06/15/2009
23
22
PCH Grounds
K17_REF
06/15/2009
22
21
PCH Power
K17_REF
06/15/2009
21
20
PCH MISC
K17_REF
10/07/2009
20
19
PCH PCI/FlashCache/USB
K18_MLB
06/15/2009
19
18
PCH DMI/FDI/Graphics
K17_REF
08/24/2009
18
17
PCH SATA/PCIE/CLK/LPC/SPI
K17_REF
06/15/2009
17
16
CPU Non-GFX Decoupling (2 of 2)
K17_REF
06/15/2009
16
15
CPU Non-GFX Decoupling (1 of 2)
K17_REF
06/15/2009
15
14
CPU Grounds
K17_REF
06/15/2009
14
13
CPU Power (2 of 2)
K17_REF
06/15/2009
13
12
CPU Power (1 of 2)
K17_REF
06/15/2009
12
11
CPU DDR3 Interfaces
K17_REF
06/15/2009
11
10
CPU Clock/Misc/JTAG
K17_REF
06/15/2009
10
9
CPU DMI/PEG/FDI/RSVD
K17_REF
06/11/2009
9
8
Signal Aliases
K17_REF
MASTER
8
7
Power Aliases
MASTER
MASTER
7
6
Functional / ICT Test
MASTER
05/28/2009
5
5
BOM Configuration
K17_REF
MASTER
4
4
Revision History
MASTER
06/30/2009
3
3
Power Block Diagram
K17_REF
06/30/2009
2
2
System Block Diagram
K17_REF
Misc Power Supplies
K18_POWER
06/10/2009
99
90
LCD Backlight Support
K19_MLB
05/29/2009
98
89
LCD BACKLIGHT DRIVER
K18_BKLT
07/29/2009
97
88
Graphics MUX (GMUX)
K17_REF
06/15/2009
96
87
1V8 / 1V55 FB Power Supply
K18_POWER
06/26/2009
95
86
DisplayPort Connector
K17_REF
06/15/2009
94
85
Muxed Graphics Support
K17_REF
06/15/2009
93
84
LVDS Display Connector
K19_MLB
05/29/2009
90
83
GPU (GT216) CORE SUPPLY
K18_POWER
07/14/2009
89
82
NV GT216 VIDEO INTERFACES
K17_REF
06/15/2009
88
81
GT216 GPIOS & STRAPS
K17_REF
06/15/2009
87
80
NV GT216 GPIO/MIO/MISC
K17_REF
06/15/2009
86
79
GDDR3 Frame Buffer B (Top)
K17_REF
06/15/2009
85
78
GDDR3 Frame Buffer A (Top)
K17_REF
06/15/2009
84
77
NV GT216 FRAME BUFFER I/F
K17_REF
06/15/2009
82
76
NV GT216 CORE/FB POWER
K17_REF
06/15/2009
81
75
NV GT216 PCI-E
K17_REF
06/15/2009
80
74
Power Control
K17_REF
06/15/2009
79
73
Power FETs
K18_POWER
06/10/2009
78
72
Misc Power Supplies
K18_POWER
06/29/2009
77
71
CPUVTT (1.05V) Power Supply
K18_POWER
07/14/2009
76
70
GFX IMVP VCore Regulator
K18_POWER
07/08/2009
75
69
CPU IMVP VCore Regulator
K18_POWER
06/29/2009
74
68
1.5V DDR3 Supply
K18_POWER
07/14/2009
73
67
5V / 3.3V Power Supply
K18_POWER
07/13/2009
72
66
PBus Supply & Battery Charger
K18_POWER
06/30/2009
70
65
DC-In & Battery Connectors
K18_POWER
06/30/2009
69
64
AUDIO: JACK TRANSLATORS
K18_AUDIO
07/29/2009
68
63
AUDIO: JACKS
K18_AUDIO
07/29/2009
67
62
AUDIO: SPEAKER AMP
K18_AUDIO
07/29/2009
66
61
AUDIO: HEADPHONE FILTER
K18_AUDIO
07/29/2009
65
60
AUDIO: LINE INPUT FILTER
K18_AUDIO
07/29/2009
63
59
AUDIO: CODEC/REGULATOR
K18_AUDIO
09/21/2009
62
58
SPI ROM
K17_REF
06/15/2009
61
57
DEBUG SENSORS AND ADC
K18_SENSORS
07/07/2009
60
56
Sudden Motion Sensor (SMS)
K19_MLB
05/29/2009
59
55
WELLSPRING 2
K19_MLB
05/29/2009
58
54
WELLSPRING 1
K19_MLB
05/29/2009
57
53
Fan Connectors
K19_MLB
05/29/2009
56
52
Thermal Sensors
K18_SENSORS
06/18/2009
55
51
Current Sensing
K18_SENSORS
07/02/2009
54
50
Current & Voltage Sensing
K18_SENSORS
06/29/2009
53
49
K18 SMBus Connections
K18_SENSORS
06/18/2009
52
48
LPC+SPI Debug Connector
K17_MLB
06/23/2009
51
47
101
132
BluRay Decrypter Card Connector
K17_REF
06/15/2009
100
109
PCB Rule Definitions
K17_REF
06/15/2009
99
108
Project Specific Constraints
K17_REF
06/15/2009
98
107
GPU (GT216) CONSTRAINTS
K17_REF
06/15/2009
97
106
SMC Constraints
K17_REF
06/15/2009
96
105
FireWire Constraints
K17_REF
06/15/2009
95
104
Ethernet Constraints
K17_REF
06/15/2009
94
103
PCH Constraints 2
K17_REF
06/15/2009
93
102
PCH Constraints 1
K17_REF
06/15/2009
92
101
Memory Constraints
K17_REF
06/15/2009
MASTER
1
1
Table of Contents
MASTER
SCHEM,WHITE_ARROW,MLB,K18
SyncPage Contents
Date
(.csa)
820-2850 CRITICAL
PCB
1
PCBF,WHITE_ARROW,MLB,K18
Date
(.csa)
SyncPage Contents
SMC Support
K18_SENSORS
06/29/2009
50
46 91
100
CPU Constraints
K17_REF
06/15/2009
LAST_MODIFIED=Mon Feb 1 10:13:48 2010
ABBREV=DRAWING
TITLE=MLB
Page Sync
Date
Contents
(.csa)
051-8504
1
SCH
CRITICAL
SCHEM,WHITE_ARROW,MLB,K18
Page 2
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER
SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
U9600
GMUX
PG 85
J9400
PG 71
CONN
LVDS
PG 84
DISPLAY PORT
J9000
CONN
LVDS OUT
DP OUT
DVI OUT
HDMI OUT
J4501
SATA Conn
ODD
P8 40
SATA
P8 40
HD
Conn
J4500
1.05V/3GHZ.
1.05V/3GHZ.
P8 26
CK505
CLOCK
U2700
PG 33
CAMERA
SPI
PG 33
PG 17
IBEX PEAK-MPCH
U1800
INTEL
IR
Bluetooth
E-NET
XDP CONN
Misc
Conn
J4310
Mini PCI-E
FW643
AirPort
PG 39
U4100
PG 37
PG 36
Conn
E-NET
PG 35
BCM5764M
J4000
U3900
PG 34
CONN
EXPRESSCARD
J3500
E-NET
PEG
PG 17 PG 17
PCI-E
PG 17
(UP TO 16 LINES)
JTAG
76543
PG 19
PG 19
PCI-E
PCI
PG 61
J6780,6781,6782,6700,6750
Amp
HEADPHONE
U6500
U6610,6620,6630,6640,6650
Line Out
Amp
PG 59 PG 60
Line In Speaker
PG 57
Codec
PG 17
PG 18
TMDS OUT
HDA
2
DIMM’s
PG 47
PG 17
SMB
PG 41
SMB
Connectors
EXTERNAL
J4600,J4610,4720
PG 19
(UP TO 14 DEVICES)
KEYBOARD
TRACKPAD/
J5713
PG 52PG 33
USB
J3401J3401J3401
1110 1213
98
PG 46
Port80,serial
LPC Conn
PG 63
PG 44
PG 44
POWER SENSE
J5650,5660
FAN CONN AND CONTROL
PG 51
U4900
J5100
Ser
PG 44
Prt
SMC
PG 17
PG 56
PG 17
PG 20
RGB OUT
PG 17
SATA
BUFFER
CTRL
10
PG 18 PG 18 PG 20
GPIO
PG 17
FDI DMI
CLK
PWR
LPC
RTC
PG 73
PG 9
PRAPHICS
NV GT216
2.X GHZ
ARRANDALE
INTEL CPU
U8000
PG 28,30
DIMM
J2900
2 UDIMMs
DDR3-1067/1333MHZ
PG 25
U2600
U4900
Amp
Boot ROM
CONN
BSBB,0
ADC Fan
TEMP SENSOR
SPI
DC/BATT
USB
U6100
J6950
U6200
Amps
GB
J3400
PG 28
POWER SUPPLY
Audio
Audio
Conns
XP2-5
System Block Diagram
SYNC_MASTER=K17_REF
SYNC_DATE=06/30/2009
2 OF 132
<E4LABEL>
<SCH_NUM>
<BRANCH>
2 OF 101
Page 3
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER
SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
SMC_DCIN_ISENSE
SMC_CPU_ISENSE
PPVBAT_G3H_CHGR_REG
PP3V3_S0
J6950
2S4P
U7000
VIN
A
A
PGOOD
VR_ON
DELAY
DELAY
RC
RC
ADJ2
VCC
RST*
DELAY
U4900
P60
PB17A
GMUX
P3V3GPU_EN
P1V8_S0GPU_EN
EN2
PB17B
PB18A
R7020
LT3470A
SMC
EG_RAIL2_EN
EG_RAIL1_EN
EG_RAIL4_EN
SMC_RESET_L
Q5315
EG_RAIL3_EN GPUVCORE_EN
P1V1GPU_EN
PB16B
U9600
U8900
AC
J6900
VLDOIN
PPDCIN_G3H_OR_PBUS_R
DCIN(16.5V)
6A FUSE
F6905
F7040
K17 POWER SYSTEM ARCHITECTURE
R6905
(PAGE 63)
U6990
U5000
SMC PWRGD
NCP303LSN
VIN
(PAGE 45)
ENABLE
3.425V G3HOT
PP3V3_S5_AVREF_SMC
U5001
U4900
(PAGE 44)
SMC_ONOFF_L
SMC_TPAD_RST_L
VOUT
VR5020
U2850
SMC_RESET_L
SYSRST(PA2)
RESET*
P17(BTN_OUT)
RES*
PM_PWRBTN_L
U1000
PM_PWRBTN_L
PM_SYSRST_L
IMVP_VR_ON
PWRBTN#
PWR_BUTTON(P90)
PLT_RERST_L
SMC_ADAPTER_EN
PM_RSMRST_L
DRAMPWROK
SYS_RERST#
PLTRST#
PROCPWRGD
PS_PWRGD
PM_PCH_PWRGD
RC
Q7055
SMC
ALL_SYS_PWRGD
P5VS3_PGOOD
P1V8S0_PGOOD
PP3V3_S0_PWRCTL
PP1V05_S0
PP1V5_S0
S0PGOOD_PWROK
SLP_S3_L(P93)
SLP_S4_L(P94)
SMC_ONOFF_L
RSMRST_PWRGD
(PAGE 9~14)
VCCCPUPWRGD
SM_DRAMPWROK
(PAGE 17~22)
U1800
SMC AVREF SUPPLY
IBEX PEAK M
RSMRST#
ACPRESENT
CPU_PWRGD PM_MEM_PWRGD
(P64)
RSMRST_OUT(P15)
99ms DLY
IMVP_VR_ON(P16)
SLP_S5_L(P95)
PM_SLP_S3_L
ADJ1
U7971
ISL88042IRTEZ
(PAGE 72)
TRST = 200mS
PM_ALL_GPU_PGOOD
VOUT
IN
ADAPTER
ISL6259HRTZ
SMC_BATT_ISENSE
A
PPBUS_G3H
V
BATTERY CHARGER
(PAGE 64)
SMC_PBUS_VSENSE
PPVBATT_G3H_CONN
(6 TO 8.4V)
CHGR_BGATE
PL32A
(PAGE 86)
(PAGE 44)
SMC_PM_G2_EN
P3V3S5_EN
RC
DELAY
DELAY
RC
SLP_S5#(E4)
IBEX_PEAK_M
U1800
PM_SLP_S4_L
PM_SLP_S5_L
RSMRST_IN(P13)
PWRGD(P12)
CPU
(PAGE 17~22)
R7978
PM_SLP_S3_L_R
P1V8S0_EN
RC
P1V5DDR_EN
P1V2GMUX_EN
DELAY
RC
P5VS0_EN
CPUVTTS0_EN
DELAY
P3V3S0_EN
PBUSVSENS_EN
PP3V42_G3H
A
(PAGE 81)
PGOOD
U5410
V
PPVCORE_GPU
SMC_GPU_VSENSE
F7041
VDD
PP5V_S3_GPUVCORE
GPU VCORE
ISL6263C
SMC_GPU_ISENSE
PGOOD
EN
VOUT
VIN
(PAGE 45)
PP5V_S0_CPUVTTS0
1.05V
A
(PAGE 69)
CPUVTTS0_PGOOD
CPUVTTS0_EN
TPS51513
U7600
R7640
PPCPUVTT_S0
SMC_CPU_FSB_ISENSE
GPUVCORE_PGOOD
SMC_CPU_HI_ISENSE
GPUVCORE_EN
VIN
CPU VCORE
CPUIMVP_GOOD
PPVCORE_S0_CPU
SMC_CPU_VSENSE
R7050
VIN
VOUT
1.05V AUX
VIN
U7790
R5413
VIN
PPVBAT_G3H_CHGR_R
P1V1GPU_EN
P1V8FB_EN
EN1
VOUT1
VOUT
ISL9522
VR_ON
1.5V
VOUT2
VIN
PP1V1_S0GPU
VOUT1
1.103V(L/H)
DDRVTT_EN
0.75V
SMC_GPU_1V8_ISENSE1.8V(R/H)
PPDDR_S3_REG
U7400
PP1V5_S3
V
U5440
SMC_CPU_DDR_VSENSE
(PAGE 67)
CPUIMVP_VR_ON
A
R5388
R7350
SMC_DDR_ISENSE
A
PPVTT_S0_DDR_LDO
PP1V8_S0GPU
(R/H)
(PAGE 85)
U9500
ISL6236
POK1
P1V1GPU_PGOOD
LTC1872
U7201
P5VS3_EN
ENA
U9700
PM_SLP_S3_L
(PAGE 87)
SLP_S4#(H7)
P5VS3_EN
PM_SLP_S4_L
SLP_S3#(P12)
P3V3S3_EN
DDRREG_EN
Q9806
PM_SLP_S5_L
VOUT
SMC_ADAPTER_EN&&PM_SLP_S3_L
(PAGE 70)
GFX_VR_EN
PGOOD
GFXIMVP_PGOOD
A
Q4260
U7500
(PAGE 68)
DPRSLPVR
R7540
V
SMC_GFX_VSENSE
TPS51981
GFXIMVP_ISENSE
VOUT
PFWBOOST
VR_ON
GFX_DPRSLPVR
VIN
&&
PGOOD2PGOOD1
APP001
BKLT_EN
LCD_BKLT_EN
P5VS3_PGOOD
P3V3S5_EN
BKLT_PLT_RST_L
TPS51980
POK2
VIN
5V
(L/H)
VOUT1
EN1
PP3V3_S5
VOUT2
PP1V5_S0
PGOOD
U7801
TPS51116
U7300
PPVOUT_S0_LCDBKLT
Q7870
PP3V3_S3
VIN
EN
OUT
PP3V3_S0_GPU
P3V3GPU_EN
P3V3S5_PGOOD
Q3810
VOUT
PGOOD
Q7810
Q7922
PP1V5_EXP_S0
PP3V3_ENET
P1V5_EXP_S0_EN
P3V3S3_EN
PP1V8_S0
EN
P3V3S0_EN
V
PPVCORE_S0_GFX
A
PP3V3_S0_FET
P1V8_S0_EN
FW_PWR_EN
P1V8S0_PGOOD
Q7830
Q4291
PP3V3_FW_FET
(PAGE 70)
U7720
ISL8014
VIN
PM_SLP_S3_L&&WOL_EN||SMC_ADAPTER_EN
(PAGE 70)
U7710
ISL8009B
VOUT
P1V2ENET_EN
VIN
EN
U7980
PM_ALL_GPU_PGOOD
Q7850
PP1V2_ENET
P1V2GMUX_EN
PP1V2_GMUX_FET
(PAGE 70)
U7760
ISL8009B
SLG5AP020
VOUT
ON
DDRREG_PGOOD
PP5V_S3_DDRREG
S3
S5
P1V8FB_PGOOD
PP5V_S3
(PAGE 65)
EN2
3.3V
VOUT2
PP3V3_S5
P5VS0_EN
Q7860
P1V5DDR_EN
PP5V_S0_FET
(PAGE 66)
DDRREG_EN
8A FUSE
PBUS SUPPLY/
VOUT
VIN
XP2-5
SYNC_DATE=06/30/2009
SYNC_MASTER=K17_REF
Power Block Diagram
3 OF 132
<E4LABEL>
<SCH_NUM>
<BRANCH>
3 OF 101
Page 4
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Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
PROTO:
Revision History
SYNC_MASTER=MASTER
SYNC_DATE=MASTER
4 OF 132
<E4LABEL>
<SCH_NUM>
<BRANCH>
4 OF 101
Page 5
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
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PAGE
NOTICE OF PROPRIETARY PROPERTY:
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B
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345678
D
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8 7 5 4 2 1
BOM OPTIONS
BOM NAME
BOM NUMBER
TABLE_BOMGROUP_HEAD
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
BOM OPTIONS
BOM GROUP
TABLE_BOMGROUP_HEAD
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
BOM OPTIONS
BOM GROUP
TABLE_BOMGROUP_HEAD
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_ALT_ITEM
DESCRIPTION
REFERENCE DES
BOM OPTION
QTY
PART NUMBER
CRITICAL
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_BOMGROUP_ITEM
PART NUMBER
ALTERNATE FOR
PART NUMBER
BOM OPTION
REF DES
COMMENTS:
TABLE_ALT_HEAD
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
DESCRIPTION
REFERENCE DES
BOM OPTION
QTY
PART NUMBER
CRITICAL
DESCRIPTION
REFERENCE DES
BOM OPTION
QTY
PART NUMBER
CRITICAL
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
BOM Variants
K18 BOM GROUPS
Development BOM
Module Parts
Alternate Parts
Bar Code Labels / EEE #’s
K18_COMMON1
BATT_3S,BCM5764M,GL137,CPUPOC_IMAX_40_50,CPUMEM_S0,SMC_EXCARD_NOT,SMC_DEBUG_YES,HUB1_2NONREM,HUB2_3NONREM
639-0953
K18_COMMON,CPU_2_4GHZ,FB_256_HYNIX,K18_PVT,EEEE_DCJ8
PCBA,2.0G,512HYN_VRAM,K18
639-0954
K18_COMMON,CPU_2_53GHZ,FB_512_SAMSUNG,K18_PVT,EEEE_DCJ9
PCBA,2.13G,512SAM_VRAM,K18
VRAM4,VRAM_512_HYNIX,FB1V35
FB_512_HYNIX
LBL,P/N LABEL,PCB,28MM X 6 MM
EEEE_DCJ8
[EEEE:DCJ8]
CRITICAL
1
826-4393
LBL,P/N LABEL,PCB,28MM X 6 MM
EEEE_DCJ9
[EEEE:DCJ9]
CRITICAL
1
826-4393
CPU_2_66GHZ
ARD,SLBPE,PRQ,2.66G,35W,C2,3M,BGA
337S3848 CRITICAL
U1000
1
ARD,SLBPF,PRQ,2.53G,35W,C2,3M,BGA
337S3847
CPU_2_53GHZ
CRITICAL
1
U1000
6.3V alt to 11V Sanyo
128S0294128S0305
ALL
A02 alt to A03 GPU
337S3839337S3808
ALL
ALL
Molex alt to Foxconn
516S0806516S0805
152S1102
ALL
Mag layer alt to Vishay
152S1088
353S2805 353S2603
Fairchild wafer option
ALL
Sanyo alt to Kemet
ALL
128S0264 128S0257
ALL
Panasonic alt to Sanyo
128S0303 128S0282
FB_512_SAMSUNG
VRAM4,VRAM_512_SAMSUNG,FB1V35
ALL
155S0329
MAG LAYERS ALT TO MURATA
155S0457
Samsung I die alt to H
333S0507333S0542
ALL
ALL
157S0055
Delta alt to TDK Magnetics
157S0058
ALL
152S0518152S0896
MAG LAYERS ALT TO CYNTEC
138S0602
Murata alt to Samsung
138S0603
ALL
U3900
CRITICAL BCM5764M343S0493
1
IC,ASIC,BCM5764M,ENET CONTROLLER,8x8,64 QFN
IC,SMC,HS8/2117,9MMX9MM,TLP
U4900
338S0563 CRITICAL
SMC_BLANK
1
IR,ENCORE II, CY7C63833-LFXC
U4800
1
CRITICAL341S2384
IC,1MBIT,SPI FLASH,K17/K18
341S2731
U3990
1
CRITICAL
085-1404
K18 MLB DEVELOPMENT
DEVEL_BOM
DEVEL
1
CRITICAL
333S0533
IC,SGRAM,GDDR3,32MX32,1000MHZ,136 FBGA
4
CRITICAL
U8400,U8450,U8500,U8550
VRAM_512_SAMSUNG
IC,PCH,IBEX PEAK-M,SLGZS,PRQ,B3,BGA
337S3849
U1800
CRITICAL
1
IC,EFI ROM,DEVELOPMENT,K18
BOOTROM_PROG
341S2562 CRITICAL
U6100
1
U9600
1
CRITICAL336S0025
GMUX_5K_BLANK
IC,XP2-5,HF,CPLD,BLANK
IC,FLASH,SPI,32MBIT,3.3V,86MHZ,8-SOP
1
CRITICAL
U6100
BOOTROM_BLANK
335S0610
IC,SDRAM,GDDR3,16MX32,900MHZ,136 FBGA
333S0483
VRAM_256_HYNIX
CRITICAL
U8400,U8450,U8500,U8550
4
U5701
1
TPAD_PROG
CRITICAL
IC,PSOC +W/USB,56PIN,MLF,K18
341S2616
IC,SMC,K18
341T0233
1
CRITICAL
U4900
SMC_PROG
341S2566
1
CRITICAL
GMUX_PROG
IC,CPLD,LATTICE,132CSBGA,K18
U9600
IC,GPU,NV GT216 LP++,969BGA,40NM,A03
337S3839
U8000
1
CRITICAL
ARD,SLBNA,PRQ,2.4G,35W,C2,4M,BGA
337S3846
CPU_2_4GHZU1000
CRITICAL
1
[EEEE:DCJD]
EEEE_DCJD
826-4393
1
LBL,P/N LABEL,PCB,28MM X 6 MM
CRITICAL
IC,FW643-E2,1394B PHY/OHCI LINK/PCI-E,12
1
338S0753 CRITICAL
U4100
[EEEE:DCJF]
EEEE_DCJF
826-4393
LBL,P/N LABEL,PCB,28MM X 6 MM
CRITICAL
1
EEEE_DCJC
[EEEE:DCJC]
826-4393
1
CRITICAL
LBL,P/N LABEL,PCB,28MM X 6 MM
333S0535
ALL
Hynix 900M alt to 1000M
333S0506
IC,SDRAM,GDDR3,32MX32,1000MHZ,136 FBGA
333S0535
4
VRAM_512_HYNIX
CRITICAL
U8400,U8450,U8500,U8550
FB_256_HYNIX
VRAM4,VRAM_256_HYNIX,FB1V55
FB_256_SAMSUNG
VRAM4,VRAM_256_SAMSUNG,FB1V55
K18_COMMON2
GMUXPLL_3V3,GPU_SS_INT,MIKEY,GPUVID_0P90V,DPMUX_EN_PLD,DP_CA_DET_EG_PLD,DP_ESD,VFRQ_SLPS3,SMC_OSC_YES,RAIL_MON
K18_COMMON
ALTERNATE,COMMON,K18_COMMON1,K18_COMMON2,K18_PROGPARTS,USBHUB_2061,RDRV:8515A2,DCI
K18_COMMON,CPU_2_66GHZ,FB_512_HYNIX,K18_PVT,EEEE_DCJF
PCBA,2.4G,512HYN_VRAM,K18
639-0957
K18_COMMON,CPU_2_66GHZ,FB_512_SAMSUNG,K18_PVT,EEEE_DCJD
639-0956
PCBA,2.4G,512SAM_VRAM,K18
639-0955
K18_COMMON,CPU_2_53GHZ,FB_512_HYNIX,K18_PVT,EEEE_DCJC
PCBA,2.13G,512HYN_VRAM,K18
VRAM_256_SAMSUNG
333S0507
4
U8400,U8450,U8500,U8550
CRITICAL
IC,SGRAM,GDDR3,16MX32,1000MHZ,136 FBGA
LBL,P/N LABEL,PCB,28MM X 6 MM
EEEE_DCJ7
[EEEE:DCJ7]
CRITICAL826-4393
1
085-1404
K18 DEVELOPMENT BOM
639-0952
K18_COMMON,CPU_2_4GHZ,FB_256_SAMSUNG,K18_PVT,EEEE_DCJ7
PCBA,2.0G,512SAM_VRAM,K18
BOM Configuration
SYNC_DATE=05/28/2009
SYNC_MASTER=K17_REF
K18_PROGPARTS
GMUX_PROG,BOOTROM_PROG,SMC_PROG,TPAD_PROG
K18_PVT
BMON_PROD,VREFMRGN_NOT,XDP,XDP_NORMAL,XDP_CPU_BPM
5 OF 132
<E4LABEL>
<SCH_NUM>
<BRANCH>
5 OF 101
Page 6
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REVISION
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Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
J6780 (MIC CONN)
J6950 (BIL CABLE CONN)
J5800 (IPD FLEX CONN)
J5650 (LEFT FAN CONN)
NC NO_TESTs
FUNC_TEST
POWER RAILS
2 TP needed
FUNC_TEST
ICT Test Points
NC NO_TESTs
NO_TEST
NO_TEST
6 TPs
J4500 (SATA ODD CONN)
3 TPs
4 TPs
3 TPs
J6900 (DC POWER CONN)
J6950 (MAIN BATT CONN)
J6995 (BAT LED CONN)
NO_TEST
CPU NO_TESTs
5 TPs
NO_TEST
NC NO_TESTs
NC NO_TESTs
J9000 (LVDS CONN)
NO_TEST
J5815 (KBD BACKLIGHT CONN)
J3500 (SD CARD CONN)
per Fan
5 TPs
2 TPs
J4501 (SATA HDD CONN)
J3401 & J3402 (AIRPORT/BT/CAMERA CONN)
FUNC_TEST
USB PORTS
J5713 (KEY BOARD CONN)
FUNC_TEST
J6781 & J6782 (SPEAKERS CONN)
J5660 (RIGHT FAN CONN)
Functional Test Points
per Fan
I1000 I1001 I1002
I1003
I1004
I1005
I1006
I1007
I1008
I1009
I1010 I1011 I1012
I1013
I1014
I1015 I1016 I1017 I1018 I1019 I1020
I1021
I1022
I1024
I1025
I1026
I1027
I1028
I1029
I1031
I1032
I1033
I1034
I1035
I1038 I1039 I1040
I1042 I1043 I1044
I1050
I1051
I1052
I1053
I1054
I1055
I1056
I1057
I1058
I1059
I1060
I1061
I1062
I1063
I1064
I1065
I1066
I1086
I1088
I1089
I1090
I1092 I1093 I1094
I1095 I1096
I1097
I1098
I1099 I1100 I1101
I1102
I1103
I1104 I1105
I1106
I1107
I1108 I1109 I1110 I1111 I1112 I1113 I1114 I1115
I1116
I1117
I1118 I1119 I1120
I1121
I1122
I1123 I1124 I1125
I1126
I1127
I1128 I1129 I1130
I1131 I1132
I1134
I1135
I1136
I1137
I1140
I1141
I1142
I1143
I1145 I1146
I1149
I1150
I1151 I1152
I1156 I1160 I1161
I1273
I1288
I1292
I1297
I1436 I1437
I1438 I1439
I1440
I1441 I1442
I1443
I1444 I1445
I1446
I1447 I1448
I1449
I1450
I1451
I1452
I1453 I1454
I1455
I1464
I557
I558
I559
I600
I602 I603
I604
I605
I606
I607
I610
I611
I612
I613
I614
I615
I616
I617
I618
I620 I621
I623
I624
I625
I626
I627
I636
I637
I638
I639
I640
I709
I714
I720 I722
I723
I724
I725 I726 I727
I728
I729
I730
I731
I732
I733
I734
I735
I737
I738
I739
I740 I741 I742 I743 I744 I751 I752
I756
I760
I761 I762 I763 I764 I765
I766
I767
I768
I769
I770
I771
I772
I774
I989 I990
I991
I992
I993
I994
I995 I996 I997 I998
Functional / ICT Test
SYNC_DATE=MASTER
SYNC_MASTER=MASTER
TRUE
PP5V_S3
TRUE
WS_KBD_ONOFF_L
SYS_LED_ANODE_R
TRUE
TP_GPU_MIOA_DE
TRUE
MAKE_BASE=TRUE
NC_TP_CPU_RSVD_NCTF<8..5>
TRUE MAKE_BASE=TRUE
NC_PCH_LVDS_VBG
MAKE_BASE=TRUE
TRUE
NC_CRT_IG_HSYNC
TRUE
NC_CRT_IG_RED
MAKE_BASE=TRUE
NC_CRT_IG_DDC_DATA
TRUE MAKE_BASE=TRUE
TRUE MAKE_BASE=TRUE
NC_HDA_SDIN1
TRUE MAKE_BASE=TRUE
NC_HDA_SDIN2
TP_PCI_AD<31..0>
TRUE
NC_PCI_C_BE_L<3..0>
MAKE_BASE=TRUE
NC_PCIE_CLK100M_PEBP
NC_PCIE_CLK100M_PEBN
TRUE MAKE_BASE=TRUE
NC_PCIE_CLK100M_PEBP
MAKE_BASE=TRUE
TRUE
NC_PCIE_CLK100M_PEBN
TRUE MAKE_BASE=TRUE
NC_PCIE_CLK100M_PE4N NC_PCIE_CLK100M_PE4P
MAKE_BASE=TRUE
TRUE
NC_PCIE_CLK100M_PE4N NC_PCIE_CLK100M_PE4P
NC_NV_RB_L
MAKE_BASE=TRUE
TRUE
NC_NV_RB_L TP_NV_WR_RE_L<1..0>
NC_PCIE_PE5_R2D_CP
TRUE
MAKE_BASE=TRUE
NC_CLINK_DATA NC_CLINK_RESET_L
NC_CLINK_CLK
NC_CLINK_RESET_L
MAKE_BASE=TRUE
TRUE
NC_CLINK_DATA
TRUE
MAKE_BASE=TRUE
NC_CLINK_CLK
TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
NC_SATA_D_D2RN
TRUE
NC_SATA_D_D2RP NC_SATA_D_R2D_CN
NC_SATA_SSD2_R2D_CN NC_SATA_SSD2_R2D_CP
NC_PCI_CLK33M_OUT3
MAKE_BASE=TRUE
TRUE
NC_PCH_NV_RCOMP
MAKE_BASE=TRUE
TRUE
NC_NV_DQ<15..0>
TRUE MAKE_BASE=TRUE
SMC_TRST_L
TRUE
NC_PCI_RESET_L
NC_PCI_CLK33M_OUT3
TP_NV_DQ<15..0>
NC_PCH_NV_RCOMP
TP_CPU_RSVD<2..1>
SPI_ALT_CLK
TRUE
NC_PCI_GNT1_L
WS_KBD12
TRUE
WS_KBD11
TRUE
TRUE
WS_KBD10
NC_TP_CPU_RSVD<2..1>
MAKE_BASE=TRUE
TRUE
SMC_TMS
TRUE
TRUE
SMC_TDO
TRUE
SMC_TDI
TRUE
SMC_TCK
SMC_RX_L
TRUE
TRUE
WS_KBD7
TRUE
WS_KBD8
TRUE
LPC_PWRDWN_L
LPC_FRAME_L
TRUE
TRUE
WS_KBD9
TRUE
PP1V5_S3
PP3V3_S3
TRUE
TRUE
PP3V3_S3
TRUE
AP_RESET_CONN_L
FAN_LT_PWM
TRUE
SD_CD_L
TRUE
PP5V_S3_IR_R
TRUE
TRUE
PCIE_WAKE_L
TRUE
AP_CLKREQ_Q_L
TRUE
PCIE_CLK100M_AP_CONN_P
TRUE
WS_KBD16_NUM
WS_KBD21
TRUE TRUE
WS_KBD22
TRUE
WS_KBD23
TRUE
WS_KBD2
TRUE
WS_KBD4
SMC_RESET_L
TRUE
SPI_ALT_CS_L
TRUE
WS_KBD15_CAP
TRUE
WS_KBD6
TRUE
TRUE
WS_KBD13
TRUE
USB2_LT1_N USB2_LT1_P
TRUE
SPI_ALT_MOSI
TRUE
BKLT_EN
TRUE
WS_KBD1
TRUE
PP3V42_G3H
TRUE
TRUE
USB_LT2_P
WS_KBD18
TRUE
TRUE
BI_MIC_N
TRUE
BI_MIC_SHIELD
TRUE
PCIE_CLK100M_AP_CONN_N
TRUE
SD_D<7..0>
PCIE_AP_D2R_P
TRUE
PCIE_AP_D2R_N
TRUE
PCIE_AP_R2D_P
TRUE
Z2_DEBUG3
TRUE
TRUE
PP1V2_ENET
TRUE
PPVTTDDR_S3
TRUE
PPVP_FW
TRUE
PPVCORE_GPU
TRUE
PPDCIN_G3H
TRUE
PP3V42_G3H
TRUE
PP3V3_S5_AVREF_SMC
TRUE
PP3V3_S5
TRUE
PP3V3_S0GPU
TRUE
PP1V8_S0
TRUE
PP1V8_GPUIFPX
TRUE
PP1V8R1V55_S0GPU_ISNS_R
TRUE
PP1V8R1V55_S0GPU_ISNS
TRUE
PP1V5_S3RS0
TRUE
PP1V0_FW_FWPHY
PP1V05_S0GPU
TRUE
PP1V05_S0
TRUE
TRUE
PP18V5_S3
TP_PCI_C_BE_L<3..0>
TRUE
SMC_LID_R
SATA_HDD_D2R_C_P
TRUE
SATA_HDD_R2D_P
TRUE
NC_PCIE_PE5_D2RP
TRUE
MAKE_BASE=TRUE
NC_PCIE_PE5_R2D_CN
TRUE
MAKE_BASE=TRUE
TRUE
NC_PCIE_PE6_R2D_CP
MAKE_BASE=TRUE
TRUE
NC_PCIE_PE6_R2D_CN
MAKE_BASE=TRUE
TRUE
NC_PCIE_PE7_D2RN
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
NC_PCIE_PE7_D2RP
TRUE
NC_PCIE_PE6_D2RN
MAKE_BASE=TRUE
TRUE
NC_PCIE_PE7_R2D_CP
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
NC_PCIE_PE8_R2D_CN
TRUE
MAKE_BASE=TRUE
NC_PCIE_PE8_D2RP
TRUE
NC_PCIE_PE8_D2RN
MAKE_BASE=TRUE
NC_PCIE_PE5_R2D_CP
NC_PCIE_PE5_D2RN
NC_PCIE_PE5_R2D_CN
NC_PCIE_PE6_R2D_CP
NC_PCIE_PE6_R2D_CN
NC_PCIE_PE6_D2RP
NC_PCIE_PE7_D2RN NC_PCIE_PE7_D2RP
NC_PCIE_PE6_D2RN
NC_PCIE_PE7_R2D_CP
NC_PCIE_PE7_R2D_CN
NC_PCIE_PE8_R2D_CP
NC_PCIE_PE8_R2D_CN
NC_PCIE_PE8_D2RP
NC_PCIE_PE8_D2RN
PP5V_S3_RTUSB_B_F
TRUE
PP5V_S0_HDD_FLT
TRUE
NC_CRT_IG_DDC_CLK
NC_PCH_LVDS_VBG
TRUE MAKE_BASE=TRUE
NC_CRT_IG_BLUE
Z2_BOOST_EN
TRUE
TRUE
SATA_ODD_R2D_P
TRUE
LVDS_CONN_A_DATA_P<0>
TRUE
PP3V3_S0
TP_CPU_RSVD_NCTF<8..5>
NC_CRT_IG_BLUE
NC_CRT_IG_RED
NC_CRT_IG_DDC_DATA
NC_CRT_IG_GREEN
NC_CRT_IG_HSYNC NC_CRT_IG_VSYNC
NC_LVDS_IG_CTRL_DATA
TRUE
NC_CRT_IG_VSYNC
MAKE_BASE=TRUE
TRUE
WS_KBD5
SATA_ODD_R2D_N
TRUE
SATA_HDD_R2D_N
TRUE
LED_RETURN_3
TRUE
LVDS_DDC_CLK
TRUE
TRUE MAKE_BASE=TRUE
NC_TP_CPU_RSVD<27..26>
TRUE MAKE_BASE=TRUE
NC_TP_CPU_RSVD<58..45>
TRUE
WS_KBD14
TRUE
USB_LT2_N
TRUE
PP18V5_S3
LPC_AD<0..3>
TRUE
TP_ISSP_SDATA_P1_0
TRUE
SATA_HDD_D2R_C_N
TRUE
SMBUS_SMC_BSA_SDA
TRUE
PP18V5_DCIN_FUSE
TRUE
ADAPTER_SENSE
TRUE
PPVBAT_G3H_CONN
TRUE
SMBUS_SMC_A_S3_SDA
TRUE
PP5V_SW_ODD
TRUE
SMBUS_SMC_A_S3_SCL
TRUE
PSOC_F_CS_L
TRUE
Z2_MISO
TRUE
WS_KBD20
TRUE
TP_ISSP_SCLK_P1_1
TRUE
LPCPLUS_GPIO
TRUE
LED_RETURN_5
TRUE
WS_KBD3
TRUE
LVDS_DDC_DATA
TRUE
LVDS_CONN_A_DATA_N<1>
TRUE
LVDS_CONN_A_DATA_P<2>
TRUE
LVDS_CONN_B_DATA_P<0>
TRUE
LVDS_CONN_B_DATA_P<2>
TRUE
TRUE
LVDS_CONN_B_CLK_F_P
TRUE
LVDS_CONN_B_CLK_F_N LED_RETURN_1
TRUE
LED_RETURN_2
TRUE
TRUE
LED_RETURN_4
TRUE
LED_RETURN_6
TRUE
SMC_ODD_DETECT SATA_ODD_D2R_C_P
TRUE
SATA_ODD_D2R_C_N
TRUE
WS_KBD19
TRUE
TRUE
IR_RX_OUT
WS_LEFT_SHIFT_KBD
TRUE
TRUE
WS_CONTROL_KBD
LCD_BKLT_PWM
TRUE
TP_CPU_RSVD<24..15>
TP_CPU_RSVD<27..26>
TP_CPU_RSVD<43..32>
TP_CPU_RSVD<58..45>
TP_CPU_RSVD<65..62>
WS_LEFT_OPTION_KBD
TRUE
LVDS_CONN_B_DATA_N<2>
TRUE
PP3V3_SW_LCD
TRUE
SMBUS_SMC_BSA_SDA
TRUE
SPI_ALT_MISO
TRUE
PM_SYSRST_L
TRUE
PM_CLKRUN_L
TRUE
TRUE
LPC_SERIRQ
LPC_CLK33M_LPCPLUS
TRUE
LPCPLUS_RESET_L
TRUE
TRUE
NC_SMC_BS_ALRT_L
TRUE
WS_KBD17
SMC_TX_L
TRUE
SPIROM_USE_MLB
TRUE
NC_LVDS_IG_CTRL_CLK
TRUE
PPVOUT_S0_LCDBKLT
KBDLED_ANODE
TRUE TRUE
SMC_KDBLED_PRESENT_L
SMC_BIL_BUTTON_L
TRUE
TRUE
FAN_LT_TACH
TRUE
NC_SMC_FAN_2_TACH
TRUE
NC_SMC_FAN_2_CTL
TRUE
NC_FW2_TPBN
NC_FW2_TPBP
TRUE
NC_FW2_TPBIAS
TRUE
NC_FW2_TPAP
TRUE TRUE
NC_FW2_TPAN
TRUE
NC_FW0_TPBN
NC_FW0_TPBP
TRUE
TRUE
NC_FW0_TPAP NC_ESTARLDO_EN
TRUE
NC_ALS_GAIN
TRUE
TRUE
NC_FW643_AVREG
MAKE_BASE=TRUE
NC_FW643_TDI
TRUE
MAKE_BASE=TRUE
NC_DP_IG_C_HPD
TRUE MAKE_BASE=TRUE
NC_DP_IG_C_CTRL_DATA
TRUE MAKE_BASE=TRUE
NC_DP_IG_C_CTRL_CLK
MAKE_BASE=TRUE
TRUE
NC_DP_IG_C_CTRL_CLK
NC_DP_IG_C_MLP<3..0>
MAKE_BASE=TRUE
TRUE
NC_DP_IG_C_MLN<3..0>
TRUE MAKE_BASE=TRUE
NC_DP_IG_C_AUXP
TRUE MAKE_BASE=TRUE
NC_DP_IG_C_AUXN
TRUE MAKE_BASE=TRUE
NC_DP_IG_C_AUXN
NC_DP_IG_D_HPD
TRUE MAKE_BASE=TRUE
NC_DP_IG_D_HPD
NC_DP_IG_D_CTRL_DATA
TRUE MAKE_BASE=TRUE
NC_DP_IG_D_CTRL_DATA
NC_DP_IG_D_CTRL_CLK
TRUE MAKE_BASE=TRUE
NC_DP_IG_D_CTRL_CLK
TRUE MAKE_BASE=TRUE
NC_DP_IG_D_MLP<3..0>TP_DP_IG_D_MLP<3..0>
TRUE MAKE_BASE=TRUE
NC_DP_IG_D_MLN<3..0>TP_DP_IG_D_MLN<3..0>
MAKE_BASE=TRUE
TRUE
NC_DP_IG_D_AUXPNC_DP_IG_D_AUXP
TRUE MAKE_BASE=TRUE
NC_SDVO_TVCLKINNNC_SDVO_TVCLKINN
MAKE_BASE=TRUE
TRUE
NC_DP_IG_D_AUXN
TRUE MAKE_BASE=TRUE
NC_SDVO_STALLN
MAKE_BASE=TRUE
TRUE
NC_SDVO_TVCLKINPNC_SDVO_TVCLKINP
TRUE MAKE_BASE=TRUE
NC_SDVO_INTNNC_SDVO_INTN
MAKE_BASE=TRUE
TRUE
NC_SDVO_STALLPNC_SDVO_STALLP
MAKE_BASE=TRUE
TRUE
NC_SDVO_INTPNC_SDVO_INTP
MAKE_BASE=TRUE
TRUE
NC_GPU_BUFRST_L
MAKE_BASE=TRUE
TRUE
NC_GPU_GSTATE<1>
MAKE_BASE=TRUE
TRUE
NC_GPU_GSTATE<0>
MAKE_BASE=TRUE
TRUE
NC_GPU_MIOA_D<9..0>TP_GPU_MIOA_D<9..0>
TRUE
NC_GPU_MIOA_DE
MAKE_BASE=TRUE
NC_LVDS_EG_BKL_PWM
TRUE MAKE_BASE=TRUE
NC_LVDS_IG_B_CLKP
TRUE
MAKE_BASE=TRUE
TP_LVDS_IG_B_CLKP
NC_LVDS_IG_B_CLKN
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
NC_PCH_SSTNC_PCH_SST
TRUE
MAKE_BASE=TRUE
NC_SMC_BS_ALRT_LNC_SMC_BS_ALRT_L
NC_LVDS_IG_BKL_PWM
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
NC_PCH_NC1
TRUE
MAKE_BASE=TRUE
NC_PCH_NC5
MAKE_BASE=TRUE
TRUE
NC_PCH_TP19
TRUE
MAKE_BASE=TRUE
NC_PCH_NC3
TRUE
MAKE_BASE=TRUE
NC_PCH_NC2
TRUE
MAKE_BASE=TRUE
NC_PCH_NC4
MAKE_BASE=TRUE
TRUE
NC_PCH_TP14
MAKE_BASE=TRUE
TRUE
NC_PCH_TP15
MAKE_BASE=TRUE
TRUE
NC_PCH_TP16
MAKE_BASE=TRUE
TRUE
NC_PCH_TP17
MAKE_BASE=TRUE
TRUE
NC_PCH_TP18
MAKE_BASE=TRUE
TRUE
NC_PCH_TP10
MAKE_BASE=TRUE
TRUE
NC_PCH_TP9
MAKE_BASE=TRUE
TRUE
NC_PCH_TP12
MAKE_BASE=TRUE
TRUE
NC_PCH_TP11
MAKE_BASE=TRUE
TRUE
NC_PCH_TP13
MAKE_BASE=TRUE
TRUE
NC_PCH_TP8
TP_SMC_P41
NC_HDA_SDIN1 NC_HDA_SDIN2 NC_HDA_SDIN3
MAKE_BASE=TRUE
TRUE
NC_PCI_GNT3_LNC_PCI_GNT3_L
NC_PCI_GNT2_L
MAKE_BASE=TRUE
TRUE
NC_PCI_GNT0_LNC_PCI_GNT0_L
TRUE MAKE_BASE=TRUE
NC_PCI_GNT1_L
NC_PCI_PAR
MAKE_BASE=TRUE
TRUE
NC_PCI_PAR
NC_PCI_PME_L
MAKE_BASE=TRUE
TRUE
NC_PCI_PME_L
TRUE MAKE_BASE=TRUE
NC_PCI_RESET_L
TP_NV_DQS<1..0> TP_NV_CE_L<3..0>
TRUE
NC_NV_ALE
MAKE_BASE=TRUE
NC_NV_ALE
NC_NV_CLE
TRUE MAKE_BASE=TRUE
NC_NV_CLE
TRUE
NC_NV_WE_CK_L<1..0>
MAKE_BASE=TRUE
TP_NV_WE_CK_L<1..0>
TRUE
NC_NV_WR_RE_L<1..0>
MAKE_BASE=TRUE
NC_PCIE_CLK100M_PE5N
TRUE
NC_PCIE_CLK100M_PE6P
MAKE_BASE=TRUE
NC_PCIE_CLK100M_PE6P
NC_PCIE_CLK100M_PE6N
NC_PCIE_CLK100M_PE5P
TRUE
NC_PCIE_CLK100M_PE7N
MAKE_BASE=TRUE
NC_PCIE_CLK100M_PE7N NC_PCIE_CLK100M_PE7P
NC_SATA_C_D2RP
NC_PSOC_P1_3
NC_SATA_C_R2D_CP
NC_SATA_C_R2D_CN
NC_SATA_D_D2RN
TRUE
NC_SATA_SSD2_R2D_CP
MAKE_BASE=TRUE
MAKE_BASE=TRUE
NC_SATA_SSD2_R2D_CN
TRUE
MAKE_BASE=TRUE
TRUE
NC_SATA_SSD2_D2RPNC_SATA_SSD2_D2RP
NC_PCH_TP1
TRUE
MAKE_BASE=TRUE
NC_PCH_TP2
MAKE_BASE=TRUE
TRUE
NC_PCH_TP3
TRUE
MAKE_BASE=TRUE
NC_PCH_TP6
TRUE
MAKE_BASE=TRUE
NC_PCH_TP7
TRUE
MAKE_BASE=TRUE
NC_PCH_TP5
TRUE
MAKE_BASE=TRUE
NC_PCH_TP4
TRUE
MAKE_BASE=TRUE
NC_PCH_TP10
TRUE
MAKE_BASE=TRUE
NC_SMC_P41
MAKE_BASE=TRUE
TRUE
NC_PCI_GNT2_L
TRUE
NC_PCI_AD<31..0>
MAKE_BASE=TRUE
TRUE MAKE_BASE=TRUE
NC_HDA_SDIN3
TRUE MAKE_BASE=TRUE
NC_LVDS_IG_CTRL_DATA
TRUE
NC_LVDS_IG_CTRL_CLK
MAKE_BASE=TRUE
MAKE_BASE=TRUE
NC_CRT_IG_DDC_CLK
TRUE
NC_CRT_IG_GREEN
TRUE MAKE_BASE=TRUE
MAKE_BASE=TRUE
TRUE
NC_TP_CPU_RSVD<24..15>
NC_TP_CPU_RSVD<43..32>
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
NC_TP_CPU_RSVD<65..62>
TRUE MAKE_BASE=TRUE
NC_PCIE_CLK100M_PE7P
NC_DP_IG_D_AUXN
NC_SDVO_STALLN
NC_PCH_NC1 NC_PCH_NC2
NC_PCH_TP17
NC_PCH_TP14
NC_PCH_TP12
NC_PCH_TP7
NC_PCH_TP2
NC_PCH_TP9
NC_PCH_TP15
NC_FW643_AVREG
TP_GPU_GSTATE<0>
TP_LVDS_IG_B_CLKN
TRUE MAKE_BASE=TRUE
NC_NV_CE_L<3..0>
MAKE_BASE=TRUE
TRUE
NC_NV_DQS<1..0>
NC_PCH_NC3 NC_PCH_NC4 NC_PCH_NC5 NC_PCH_TP19 NC_PCH_TP18
NC_PCH_TP16
NC_PCH_TP13
NC_PCH_TP11
NC_PCH_TP8
NC_PCH_TP3
TP_LVDS_IG_BKL_PWM
NC_LVDS_EG_BKL_PWM
TP_GPU_GSTATE<1>
NC_GPU_BUFRST_L
NC_FW643_TDI
NC_DP_IG_C_CTRL_DATA
NC_DP_IG_C_AUXP
TP_DP_IG_C_MLN<3..0>
TP_DP_IG_C_MLP<3..0>
NC_DP_IG_C_HPD
NC_SMC_FAN_3_CTL
TRUE
TRUE
NC_SMC_FAN_3_TACH
TRUE
MAKE_BASE=TRUE
NC_SATA_D_R2D_CP
TRUE
NC_SATA_D_D2RP
MAKE_BASE=TRUE
TRUE
PCH_VSS_NCTF<1>
TRUE
PCH_VSS_NCTF<2>
TRUE
PCH_VSS_NCTF<5>
TRUE
PCH_VSS_NCTF<7> PCH_VSS_NCTF<9>
TRUE
PCH_VSS_NCTF<11>
TRUE
PCH_VSS_NCTF<12>
TRUE
TRUE
PCH_VSS_NCTF<15>
TRUE
PCH_VSS_NCTF<17>
TRUE
PCH_VSS_NCTF<19>
TRUE
PCH_VSS_NCTF<19>
TRUE
PCH_VSS_NCTF<21>
TRUE
PCH_VSS_NCTF<25>
TRUE
PCH_VSS_NCTF<27>
TRUE
PCH_VSS_NCTF<29>
NC_PCH_TP1
NC_PCH_TP4
NC_PCH_TP5
NC_PCH_TP6
TRUE
NC_PCIE_CLK100M_PE5N
MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE
NC_PCIE_CLK100M_PE5P NC_PCIE_CLK100M_PE6N
MAKE_BASE=TRUE
TRUE
NC_PSOC_P1_3
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
NC_SATA_C_D2RN
MAKE_BASE=TRUE
TRUE
NC_SATA_C_D2RP
TRUE
NC_SATA_C_R2D_CN
MAKE_BASE=TRUE
TRUE
NC_SATA_C_R2D_CP
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
NC_SATA_D_R2D_CN
NC_SATA_SSD2_D2RN
MAKE_BASE=TRUE
TRUE
NC_SATA_SSD2_D2RN
NC_SATA_D_R2D_CP
TRUE
Z2_RESET
TRUE
LVDS_CONN_A_DATA_P<1>
TRUE
LVDS_CONN_A_DATA_N<0>
TRUE
SMBUS_SMC_A_S3_SDA
TRUE
SMBUS_SMC_A_S3_SCL
TRUE
USB_CAMERA_CONN_P
TRUE
USB_CAMERA_CONN_N
TRUE
CONN_USB2_BT_P CONN_USB2_BT_N
TRUE
PP5V_S3_RTUSB_A_F
TRUE
PP3V3_WLAN
TRUE
SYS_LED_ANODE
TRUE
TRUE
PPBUS_G3H
TRUE
Z2_CS_L
TRUE
PP3V3_FW_FWPHY
TRUE
PPVCORE_S0_GFX
TRUE
PPVCORE_S0_CPU
TRUE
PP3V3_S0
TRUE
PP3V3_ENET
TRUE
PP1V2_S0
PM_SLP_S3_L
TRUE
TRUE
PP1V05_S5
MAKE_BASE=TRUE
NC_PCIE_PE5_D2RN
TRUE
SMBUS_SMC_BSA_SCL
TRUE
SMBUS_SMC_BSA_SCL
TRUE
TRUE
PP3V42_G3H
TRUE
PSOC_SCLK
LVDS_CONN_B_DATA_N<1>
TRUE
LVDS_CONN_B_DATA_P<1>
TRUE
LVDS_CONN_B_DATA_N<0>
TRUE
LVDS_CONN_A_CLK_F_N
TRUE
LVDS_CONN_A_CLK_F_P
TRUE
LVDS_CONN_A_DATA_N<2>
TRUE
NC_PCIE_PE5_D2RP
TRUE
NC_PCIE_PE7_R2D_CN
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
NC_PCIE_PE8_R2D_CP
TRUE
NC_PCIE_PE6_D2RP
MAKE_BASE=TRUE
TRUE
PP5V_S5
TRUE
BI_MIC_P
TRUE
FAN_RT_TACH
TRUE
FAN_RT_PWM
TRUE
SPKRCONN_S_OUT_N
SPKRCONN_L_OUT_N
TRUE
TRUE
SPKRCONN_S_OUT_P
TRUE
SPKRCONN_R_OUT_P
TRUE
SPKRCONN_L_OUT_P
SPKRCONN_R_OUT_N
TRUE
SMC_MD1
TRUE TRUE
SMC_NMI
SMC_ONOFF_L
TRUE
TRUE
PP0V75_S0_DDRVTT
TRUE
PCIE_AP_R2D_N
TRUE
PP5V_S0
PP5V_S0
TRUE
NC_SATA_C_D2RN
PP5V_S3_ALSCAMERA_F
TRUE
TRUE
SD_CMD
TRUE
SD_CLK
TRUE
SD_WP
Z2_CLKIN
TRUE
Z2_SCLK
TRUE
TRUE
Z2_KEY_ACT_L
TRUE
PICKB_L
TRUE
PSOC_MISO PSOC_MOSI
TRUE
TRUE
GND
GND
TRUE
TRUE
GND
TRUE
GND
GND
TRUE
TRUE
GND
TRUE
GND
GND
TRUE
TRUE
GND
TRUE
GND
TRUE
GND
GND
TRUE
GND
TRUE
GND
TRUE
7 OF 132
<E4LABEL>
<SCH_NUM>
<BRANCH>
6 OF 101
7
31 33 42 43 44 46 54 56 58 61 66 67 72
82
101
53
42
79 80
9
6
18
6
18
6
18
6
18
6
17
6
17
19
6
17
6
17
6
17
6
17
6
17
6
17
6
17
6
17
6
19
6
19
6
17
6
17
6
17
6
17
6
17
6
17
6
17
6
17
6
17
6
17
6
17
6
17
6
19
6
19
19
45 47
6
19
6
19
6
19
9
47
6
19
53
53
53
45 46 47
45 46 47
45 46 47
45 46 47
43 45 46 47
53
53 18 45 47
17 45 47 87 94
53
7
28 30 31 67 72
6 7 8
17 20 31 32 33 34 35 36 48 50 53 54
55 72 73 87
101
6 7 8
17 20
31 32 33 34
35 36 48 50
53 54 55 72
73 87
101
33
52
34 37
42
18 27 33
33
33 99
53
53
53
53
53
53
45 46 47 65
47
53
53
53
43 99
43 99
47
88
53
6 7
17 21 23 43 45 46 47 48 49 53 64 65 66 73
43 99
53
62 63
62 63
33 99
34
17 33 94
17 33 94
33 94
53 54
7
37 71 72
7
32 67
7
40 41
7
49 75 82
7
64 65
6 7
17 21 23 43 45 46 47 48 49
53 64 65 66 73
45 46
7
17 18 19 20 21 23 27 31 35 57
66 71 72 73 83 85 99
7
72 74 79 80 81 82 84
7
12 16 21 23 24 58 71 72 87
7
72 81
7
50 86
7 8
50 56 75 76 77 78
7
13 16 31 42 72 73 99
7
39 40
7
74 76 79 81 86
7
10 12 13 15 17 18 20 21 23 24
25 26 40 70 73 86
6
54
64
42 93
42 93
6
17
6
17
6
17
6
17
6
17
6
17
6
17
6
17
6
17
6
17
6
17
6
17
6
17
6
17
6
17
6
17
6
17
6
17
6
17
6
17
6
17
6
17
6
17
6
17
6
17
6
17
43
42
6
18
6
18
6
18
54
42 93
83 84 98
6 7
17 18 19 20 21 23 24 25 26
27 28 30 34 37 40 42 46 47 48
50 51 52 54 58 62 63 68 69 72
73 80 83
84 85 87 88 99
6
18
6
18
6
18
6
18
6
18
6
18
6
18
6
18
53
42 93
42 93
83 88
83 84
53
43 99
6
54
17 45 47 87 94
8
53
42 93
6
45 48 64 65 97
64
64
64 65
6
33 45 48 54 97
42 56
6
33 45 48 54 97
53 54
53 54
53
8
53
20 47
83 88
53
83 84
83 84 98
83 84 98
83 84 98
83 84 98
83 98
83 98
83 88
83 88
83 88
83 88
42 45
42 93
42 93
53
42 44
53
53
87 88
9
9
9
9
53
83 84 98
83
6
45 48 64 65 97
47
18 27 45
18 45 47
17 45 47
27 47 94
27 47 87 94
6
53
43 45 46 47
20 47 57
6
18
54
54
45 46 64
52
45 46
45 46
39 41
39 41
39 41
39 41
39 41
39 41 96
39 41 96
39 41 96
45 46
45 46
6
39
6
39
6
18
6
18
6
18
6
18
18
18
6
18
6
18
6
18
6
18
6
18
6
18
6
18
6
18
6
18
18
18
6
18
6
18
6
18
6
18
6
18
6
18
6
18
6
18
6
18
6
18
6
18
6
18
6
18
6
18
6
74
79 80
6
8
18 93
6
20
6
20
6
6
6
20
6
20
6
20
6
20
6
20
6
20
6
20
6
20
6
20
6
20
6
20
6
20
6
20
6
20
6
20
6
20
6
20
45 46
6
17
6
17
6
17
6
19
6
19
6
19
6
19
6
19
6
19
6
19
6
19
6
19
6
19
6
19
6
19
6
19
6
19
6
19
19
19
6
17
6
20
6
20
6
20
6
17
6
20
6
20
6
20
6
17
6
53
6
17
6
17
6
17
6
17
6
17
6
17
6
17
6
20
6
20
6
20
6
20
6
20
6
20
6
20
6
20
6
19
19
6
17
6
18
6
18
6
18
6
18
9
6
20
6
18
6
18
6
20
6
20
6
20
6
20
6
20
6
20
6
20
6
20
6
20
6
39
79 80
8
18 93
19
19
6
20
6
20
6
20
6
20
6
20
6
20
6
20
6
20
6
20
6
20
8
18
6
80
6
74
6
39
6
18
6
18
6
18
45 46
45 46
6
17
6
17
20 94
20 94
20 94
20 94
20 94
20 94
20 94
20 94
6
20 94
6
20 94
20 94
20 94
20 94
20 94
6
20
6
20
6
20
6
20
6
17
6
17
6
20
6
53
6
17
6
17
6
17
6
17
6
17
6
17
6
17
6
17
53 54
83 84 98
83 84 98
6
33 45 48 54 97
6
33 45 48 54 97
33 93
33 93
33 99
33 99
43
33
42 46
7
40 49 65 66 67 69 70 82 86 89
53 54
7
39 40 41
7
13 24 49 69
7
12 15 49 68
6 7
17 18 19 20 21 23 24 25 26
27 28 30 34 37 40 42 46 47 48
50 51 52 54 58 62 63 68 69 72
73 80
83 84 85 87 88 99
7
27 37 73
7
72 87
18 31 45 73 85
7
17 71
6
17
6
45 48 64 65 97
6
45 48 64
65 97
6 7
17 21 23 43
45 46 47
48 49 53
64 65 66
73
53 54
83 84 98
83 84 98
83 84 98
83 98
83 98
83 84 98
6
17
6
17
6
17
6
17
7
23 66 72
62 63
52
52
61 62 99
61 62 99
61 62 99
61 62 99
61 62 99
61 62 99
45 47
45 47
45 46 53
7
28 30 31 67
33 94
6 7
23 42 47 52 54 68 69 70 72
86 88
6 7
23 42 47
52 54 68 69
70 72 86 88
6
17
33
34
34
34 37
53 54
53 54
53 54
53 54
53 54
53 54
Page 7
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER
SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
"G3Hot" (Always-Present) Rails
1.8V/1.5V/1.2V/1.05V Rails
3.3V Rails
Chipset "VCore" Rails
2A max supply
? mA
"GPU" Rails
"FW" (FireWire) Rails
ENET Rails
5V Rails
Power Aliases
SYNC_DATE=MASTER
SYNC_MASTER=MASTER
PP3V3_S5
MAKE_BASE=TRUE
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.6 MM
PP3V3_S5
MIN_NECK_WIDTH=0.2 MM
PP3V3_S5
PP3V3_S5
PP3V3_S3
MIN_LINE_WIDTH=0.50MM MIN_NECK_WIDTH=0.20MM
MAKE_BASE=TRUE
VOLTAGE=3.3V
PP3V3_S3
PP3V3_S3 PP3V3_S3
PP3V3_S3
PP3V3_S5
PP3V3_S5 PP3V3_S5
PP3V3_S5
PP3V3_S5
MIN_NECK_WIDTH=0.2 MM MAKE_BASE=TRUE
PP1V5_S3RS0
MIN_LINE_WIDTH=0.6 MM VOLTAGE=1.5V
MAKE_BASE=TRUE
VOLTAGE=18.5V
PPDCIN_G3H
MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.25 MM
PP1V2_ENET
PP1V2_ENET
MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.2V MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.6 MM
PP1V05_S0
PP1V05_S0
MAKE_BASE=TRUE
VOLTAGE=1.05V
MIN_NECK_WIDTH=0.2 MM
MIN_LINE_WIDTH=0.6 MM
PP1V05_S0
PP1V05_S0
PP5V_S5
PP3V42_G3H
PP5V_S5
PP5V_S3
PP5V_S3
MIN_LINE_WIDTH=0.5 mm VOLTAGE=5V
MAKE_BASE=TRUE
PP5V_S3
MIN_NECK_WIDTH=0.2 mm
PPBUS_G3H
PPBUS_G3H
PP3V3_S3
PP3V3_S3
PP1V8_S0
VOLTAGE=1.8V MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM
PP3V3_ENET
MIN_LINE_WIDTH=0.6 MM
MAKE_BASE=TRUE
VOLTAGE=3.3V
MIN_NECK_WIDTH=0.2 MM
MAKE_BASE=TRUE
VOLTAGE=1.0V
MIN_NECK_WIDTH=0.2 MM
MIN_LINE_WIDTH=0.4 MM
PP1V0_FW_FWPHY
PPVP_FW
MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=12.8V
PP3V3_S0GPU
VOLTAGE=3.3V MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.3 MM MIN_NECK_WIDTH=0.10MM
VOLTAGE=1.8V MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.15 MM
PP1V8_GPUIFPX
VOLTAGE=1.8V MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM
PP1V8R1V55_S0GPU_ISNS
MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.8V
PP1V8R1V55_S0GPU_ISNS_R
MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM
MAKE_BASE=TRUE
PP1V05_S0GPU
VOLTAGE=1.05V
PPVCORE_S0_GFX
VOLTAGE=1.05V MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.25V MAKE_BASE=TRUE
MIN_NECK_WIDTH=0.25 MM
MIN_LINE_WIDTH=0.6 MM
PPVCORE_S0_CPU_VCAP0
MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.25 MM
MAKE_BASE=TRUE
VOLTAGE=1.25V
PPVCORE_S0_CPU_VCAP1
PPVCORE_S0_CPU_VCAP2
VOLTAGE=1.25V MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.25 MM
PPVTTDDR_S3
VOLTAGE=0.75V MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.3 MM MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.25V MAKE_BASE=TRUE
MIN_NECK_WIDTH=0.25 MM
MIN_LINE_WIDTH=0.6 MM
PPVCORE_S0_CPU
MIN_NECK_WIDTH=0.2 MM
MIN_LINE_WIDTH=0.6 MM
MAKE_BASE=TRUE
PPVCORE_GPU
VOLTAGE=1.0V
MIN_LINE_WIDTH=0.6 MM VOLTAGE=1.2V
MAKE_BASE=TRUE
MIN_NECK_WIDTH=0.09 MM
PP1V2_S0
PP3V3_FW_FWPHY
MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.3V MAKE_BASE=TRUE
PP0V75_S0_DDRVTT
VOLTAGE=0.75V
MIN_NECK_WIDTH=0.17 mm MAKE_BASE=TRUE
MIN_LINE_WIDTH=2 mm
PP5V_S5
PP3V42_G3H
PP3V42_G3H
PPBUS_G3H
PPDCIN_G3H
PP3V42_G3H
PP3V42_G3H
PP3V3_ENET
PPBUS_G3H
PP3V3_S0
PP3V3_S0
PP3V3_S5
PP3V3_S5
PP3V3_S5
PP3V3_S5
PP1V8_S0 PP1V8_S0 PP1V8_S0
PP1V8_S0
PP1V8_S0
PP1V8_S0
PP1V8_S0
PP1V5_S3RS0
PP1V5_S3RS0
PP1V5_S3RS0
PP3V42_G3H
PPBUS_G3H
PP1V2_ENET
PPVP_FW
PPVP_FW PPVP_FW
PP3V3_FW_FWPHY PP3V3_FW_FWPHY
PP1V0_FW_FWPHY
PP1V0_FW_FWPHY
PP3V3_S0GPU PP3V3_S0GPU PP3V3_S0GPU PP3V3_S0GPU PP3V3_S0GPU
PP3V3_S0GPU
PP1V8_GPUIFPX
PP1V8_GPUIFPX
PP1V8R1V55_S0GPU_ISNS PP1V8R1V55_S0GPU_ISNS PP1V8R1V55_S0GPU_ISNS
PP1V8R1V55_S0GPU_ISNS
PP1V8R1V55_S0GPU_ISNS
PP1V8R1V55_S0GPU_ISNS_R
PP1V8R1V55_S0GPU_ISNS_R
PP1V05_S0GPU PP1V05_S0GPU PP1V05_S0GPU PP1V05_S0GPU
PP1V05_S0GPU
PP1V05_S0GPU
PPVCORE_GPU
PPVCORE_GPU
PPVCORE_S0_CPU
PPVCORE_S0_GFX
PPVCORE_S0_GFX
PPVCORE_S0_CPU
PPVCORE_S0_CPU_VCAP0
PPVCORE_S0_CPU_VCAP1
PPVCORE_S0_CPU_VCAP2
PP1V5_S3RS0
PP1V2_S0
PP1V05_S0
PP1V2_ENET
PP1V05_S0GPU
PP1V05_S0GPU PP1V05_S0GPU
PP1V05_S0GPU
PP1V2_S0
PP3V3_FW_FWPHY
PP3V3_ENET
PP1V5_S3
PP1V5_S3
PP1V5_S3
PP1V5_S3
PP1V5_S3
PP1V5_S3
PP0V75_S0_DDRVTT
PP5V_S0
PP5V_S0
PP5V_S0
PP5V_S0
PP5V_S0
PP5V_S0
PP5V_S0
PP5V_S0
PP5V_S0
PP5V_S0
PPVTTDDR_S3
PP0V75_S0_DDRVTT
PP1V05_S0
PP1V05_S0
PP1V05_S0
PP1V05_S0
PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0
PPBUS_CPU_IMVP_ISNS
PP5V_S3
PP5V_S3
PP5V_S3
PP5V_S3
PP5V_S3
PP5V_S3
PP5V_S3
PP3V3_S5
PP3V3_S5
PP1V8_S0
PP5V_S0
PP5V_S0
PP5V_S3
PP5V_S3
PP3V3_S0
PP5V_S5
PP5V_S3
PP5V_S3 PP5V_S3 PP5V_S3
VOLTAGE=5V
PP5V_S0
MAKE_BASE=TRUE
MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.6 mm
PP5V_S0
PP5V_S0
PP3V42_G3H
PP3V3_S0
PP3V42_G3H
PP5V_S3
MAKE_BASE=TRUE
VOLTAGE=5V
PP5V_S5
MIN_NECK_WIDTH=0.2 MM
MIN_LINE_WIDTH=0.5 MM
PPBUS_G3H
PPBUS_G3H
PPBUS_G3H
PP3V42_G3H
PP3V42_G3H
PP1V05_S0
PP3V3_S3
PP3V3_S3
PP3V3_S3
PP3V3_S3
PP3V3_S5
PP3V3_S3
PP3V3_S3
PP1V05_S5
PP0V75_S0_DDRVTT
PP0V75_S0_DDRVTT
PP1V05_S0
PP1V05_S0
PP3V42_G3H
PP3V42_G3H
VOLTAGE=1.05V
MIN_NECK_WIDTH=0.2 MM
MIN_LINE_WIDTH=0.4 MM
PP1V05_S5
MAKE_BASE=TRUE
PP1V05_S5
PP3V3_S0
PP3V42_G3H
PP3V42_G3H
PP3V42_G3H
MIN_LINE_WIDTH=0.3 MM VOLTAGE=3.42V
MAKE_BASE=TRUE
PP3V42_G3H
MIN_NECK_WIDTH=0.2 MM
PPDCIN_G3H
PPBUS_CPU_IMVP_ISNS
VOLTAGE=12.8V
MAKE_BASE=TRUE
MIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.4 mm
PPBUS_CPU_IMVP_ISNS
PP3V3_S3
PP3V3_S5
PPBUS_G3H
PP3V3_S0
PP3V3_S3
PP3V3_S3
PP3V3_S3
PP3V3_S3
PP1V5_S3RS0
PP3V3_S5
PP3V3_S5
PPBUS_G3H
MAKE_BASE=TRUE
VOLTAGE=1.5V
PP1V5_S3
MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.17 mm
PP3V3_S0
PPBUS_G3H
MIN_NECK_WIDTH=0.25 mm
MAKE_BASE=TRUE
VOLTAGE=12.8V
MIN_LINE_WIDTH=0.6 mm
PP3V3_S0 PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0 PP3V3_S0 PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0 PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0 PP3V3_S0
PP3V3_S0
PP3V3_S0 PP3V3_S0
PP3V3_S0 PP3V3_S0 PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
MAKE_BASE=TRUE
PP3V3_S0
MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.20MM VOLTAGE=3.3V
PP3V3_S0
PP3V3_S0
8 OF 132
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6 7 8
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55 72 73 87
101
6 7
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7
49 68
6 7
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89
6 7
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101
6 7 8
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101
6 7 8
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101
6 7
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6 7
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6 7
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6 7
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6 7
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27 28
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6 7
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28
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42
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63
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88
99
6 7
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47
48 50 51 52 54 58 62 63 68
69
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6 7
17
18 19 20 21 23 24 25 26 27 28
30
34 37 40 42 46 47 48 50 51 52 54 58 62 63 68 69 72 73 80 83 84 85 87 88 99
6 7
17 18 19 20 21 23 24 25 26
27 28 30 34 37 40 42 46 47 48
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73 80 83 84 85 87 88 99
6 7
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27 28 30 34 37 40 42 46 47 48
50 51 52 54 58 62 63 68 69 72
73 80 83 84 85 87 88 99
6 7
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27 28
30 34 37 40 42 46 47 48 50 51 52 54 58 62 63 68 69 72 73 80 83 84 85 87 88 99
6 7
17 18 19 20 21 23 24 25 26
27 28 30 34 37 40 42 46 47 48
50
51 52 54 58 62 63 68 69 72 73
80
83 84 85 87 88 99
6 7
17 18 19 20 21 23 24 25 26
27 28 30 34 37 40 42 46 47 48
50 51 52 54 58 62 63 68 69 72
73 80 83 84 85 87 88 99
6 7
17 18 19 20 21 23 24 25 26
27 28
30 34 37 40 42 46 47 48 50 51 52 54 58 62 63 68 69 72 73 80 83 84 85 87 88 99
6 7
17
18
19
20 21 23 24 25 26 27 28 30 34 37 40 42 46 47 48 50 51 52 54 58 62 63 68 69 72 73 80 83 84 85 87 88 99
6 7
17 18 19 20 21 23 24 25 26
27 28 30 34 37 40 42 46 47 48
50 51 52 54 58 62 63 68 69 72
73 80 83 84 85 87 88 99
6 7
17 18 19 20 21 23 24 25 26
27 28
30 34 37 40 42 46 47 48 50 51 52 54 58 62 63 68 69 72 73 80 83 84 85 87 88 99
6 7
17
18
19
20 21 23 24 25 26 27 28 30 34 37 40 42 46 47 48 50 51 52 54 58 62 63 68 69 72 73 80 83 84 85 87 88 99
6 7
17 18 19 20 21 23 24 25 26
27 28 30 34 37 40 42 46 47 48
50 51 52 54 58 62 63 68 69 72
73 80 83 84 85 87 88 99
6 7
17 18 19 20 21 23 24 25 26
27 28
30 34 37 40 42 46 47 48 50 51 52 54 58 62 63 68 69 72 73 80 83 84 85 87 88 99
6 7
17
18
19
20 21 23 24 25 26 27 28 30 34 37 40 42 46 47 48 50 51 52 54 58 62 63 68 69 72 73 80 83 84 85 87 88 99
6 7
17 18 19 20 21 23 24 25 26
27 28 30 34 37 40 42 46 47 48
50 51 52
54 58 62 63 68 69 72 73 80 83 84 85 87 88 99
6 7
17 18 19 20 21 23 24 25 26
27 28 30 34 37 40 42 46 47 48
50 51 52 54 58 62 63 68 69 72
73 80 83 84 85 87 88 99
6 7
17 18 19 20 21 23 24
25 26 27
28 30 34 37 40 42 46 47 48 50
51 52 54
58 62 63 68 69 72 73 80 83 84
85 87 88 99
6 7
17 18 19 20 21 23 24 25 26
27 28 30 34 37 40 42 46 47 48
50 51 52 54 58 62 63 68 69 72
73 80 83 84 85 87 88 99
Page 8
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER
SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
Digital Ground
** PEG LANES REVERSED. ARD STRAP REQ’D. **
CPU signals
GPU signals
Thermal Module Holes
Fan Holes
Frame Holes
Tall EMI pogo pins
Short (IO Row) EMI pogo pins
Left Speaker Holes
Keyboard / IPD Conn Protect
GMUX ALIASES
1/16W
1%
402
MF-LF
10
R0900
1 2
10
MF-LF
402
1%
1/16W
R0901
1 2
STDOFF-4.5OD.98H-1.1-3.48-TH
ZT0984
1
3R2P5
ZT0990
1
3R2P5
ZT0960
1
SL-3.1X2.7-6CIR-NSP
TH
ZT0950
1
3R2P5
ZT0940
1
3R2P5
ZT0915
1
STDOFF-4.5OD.98H-1.1-3.48-TH
ZT0986
1
STDOFF-4.5OD.98H-1.1-3.48-TH
ZT0981
1
STDOFF-4.5OD.98H-1.1-3.48-TH
ZT0985
1
1.4DIA-SHORT-EMI-MLB-M97-M98
SM
SH0917
1
SM
1.4DIA-SHORT-EMI-MLB-M97-M98
SH0901
1
SM
1.4DIA-SHORT-EMI-MLB-M97-M98
SH0912
1
SM
1.4DIA-SHORT-EMI-MLB-M97-M98
SH0910
1
1.4DIA-SHORT-EMI-MLB-M97-M98
SM
SH0911
1
1.4DIA-SHORT-EMI-MLB-M97-M98
SM
SH0913
1
2.0DIA-TALL-EMI-MLB-M97-M98
SM
SH0903
1
SM
2.0DIA-TALL-EMI-MLB-M97-M98
SH0916
1
2.0DIA-TALL-EMI-MLB-M97-M98
SM
SH0902
1
2.0DIA-TALL-EMI-MLB-M97-M98
SM
SH0900
1
2.0DIA-TALL-EMI-MLB-M97-M98
SM
SH0904
1
1.4DIA-SHORT-EMI-MLB-M97-M98
SM
SH0914
1
STDOFF-4.5OD.98H-1.1-3.48-TH
ZT0991
1
STDOFF-4.5OD.98H-1.1-3.48-TH
ZT0988
1
STDOFF-4.5OD.98H-1.1-3.48-TH
ZT0989
1
STDOFF-4.5OD.98H-1.1-3.48-TH
ZT0987
1
STDOFF-4.5OD.98H-1.1-3.48-TH
ZT0980
1
5%
3.0K
1/16W MF-LF
402
R0902
1 2
4.0OD1.85H-M1.6X0.35
ZT0952
1
4.0OD1.85H-M1.6X0.35
ZT0953
1
STDOFF-4.0OD3.0H-TH
ZT0934
1
STDOFF-4.0OD3.0H-TH
ZT0935
1
STDOFF-4.5OD.98H-1.1-3.48-TH
ZT0930
1
402
5% 1/16W MF-LF
10K
R0903
1
2
402
10K
MF-LF
1/16W
5%
R0904
1
2
Signal Aliases
SYNC_MASTER=K17_REF
SYNC_DATE=06/11/2009
TP_LVDS_MUX_SEL_EG
DP_IG_HPD
MAKE_BASE=TRUE
GND_CHASSIS_AUDIO_JACK
GND
GND
GND
GND
GND
FW_PLUG_DET_L
MAKE_BASE=TRUE
MAKE_BASE=TRUE
FW643_WAKE_L
MAKE_BASE=TRUE
PEG_CLKREQ_L
MAKE_BASE=TRUE
LVDS_IG_BKL_ON
MAKE_BASE=TRUE
PEG_R2D_C_N<15..0>
PEG_R2D_C_P<15..0>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
PEG_D2R_P<15..0>
MAKE_BASE=TRUE
PEG_D2R_N<15..0>
GFX_VID<0..6>
MAKE_BASE=TRUE
MEMVTT_EN
MAKE_BASE=TRUE
MAKE_BASE=TRUE
TP_ISSP_SDATA_P1_0
TP_ISSP_SCLK_P1_1
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_PCIE_CLK100M_EXCARD_P
NC_PCIE_CLK100M_EXCARD_N
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_PCIE_EXCARD_R2D_C_N
MAKE_BASE=TRUE
DP_IG_ML_P<3..0>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
DP_IG_ML_N<3..0>
PM_ENET_EN
MAKE_BASE=TRUE
MAKE_BASE=TRUE
PM_ALL_GPU_PGOOD
TP_LVDS_IG_B_CLKP
MAKE_BASE=TRUE
TP_LVDS_IG_B_CLKN
MAKE_BASE=TRUE
MAKE_BASE=TRUE
NC_LVDS_IG_A_DATAN<3>
NO_TEST=TRUE
NC_LVDS_IG_B_DATAP<3>
NO_TEST=TRUE
MAKE_BASE=TRUE
TP_LVDS_IG_BKL_PWM
MAKE_BASE=TRUE
NC_LVDS_IG_B_DATAN<3>
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_LVDS_IG_A_DATAP<3>
NO_TEST=TRUE
MAKE_BASE=TRUE
GPU_FB_A_VREF_DIV
MAKE_BASE=TRUE
GPU_FB_B_VREF_DIV
MAKE_BASE=TRUE
MAKE_BASE=TRUE
TP_CPU_VTT_SELECT
MAKE_BASE=TRUE
LCD_BKLT_EN
MAKE_BASE=TRUE
TP_LVDS_MUX_SEL_EG
MAKE_BASE=TRUE
EG_RESET_L
NC_PCIE_EXCARD_R2D_C_P
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_PCIE_EXCARD_D2R_N
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_SATA_EXTA_R2D_C_P
MAKE_BASE=TRUE
TP_SMC_EXCARD_PWR_EN
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_SATA_EXTA_D2R_N
NO_TEST=TRUE
NC_PCIE_EXCARD_D2R_P
MAKE_BASE=TRUE
MAKE_BASE=TRUE
DP_IG_AUX_CH_N
DP_IG_DDC_CLK
MAKE_BASE=TRUE
MAKE_BASE=TRUE
DP_IG_DDC_DATA
NC_SATA_EXTA_R2D_C_N
FW643_WAKE_L
NC_LVDS_IG_B_DATAP<3> NC_LVDS_IG_B_DATAN<3>
DP_IG_AUX_CH_P
DP_IG_B_ML_N<3..0>
DP_IG_B_ML_P<3..0>
LVDS_IG_BKL_ON
TP_SMC_EXCARD_PWR_EN
NC_PCIE_EXCARD_D2R_P NC_PCIE_EXCARD_R2D_C_N NC_PCIE_EXCARD_R2D_C_P NC_PCIE_CLK100M_EXCARD_N
TP_ISSP_SCLK_P1_1
=PEG_R2D_C_N<0..15>
=PEG_R2D_C_P<0..15>
=PEG_D2R_P<0..15> =PEG_D2R_N<0..15>
NC_PCIE_CLK100M_EXCARD_P
CPUIMVP_VID<0..6> GFXIMVP_VID<0..6> MEMVTT_EN
PM_ENET_EN
PEG_CLKREQ_L
TP_LVDS_IG_B_CLKN
PEX_CLKREQ_L
NC_GPU_XTALOUT
NC_LVDS_IG_A_DATAN<3>
GPU_FB_A_VREF_DIV
GPU_FB_B_VREF_DIV
TP_CPU_VTT_SELECT
PM_ALL_GPU_PGOOD
PP1V8R1V55_S0GPU_ISNS
DP_IG_HPD
LCD_BKLT_EN
FW_PLUG_DET_L
NC_PCIE_EXCARD_D2R_N
DP_IG_DDC_CLK
GND
GND
GND
GND
NC_SATA_EXTA_D2R_P
MAKE_BASE=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_SATA_EXTA_R2D_C_N
TP_ISSP_SDATA_P1_0
DP_IG_AUX_CH_N
DP_IG_AUX_CH_P
MAKE_BASE=TRUE
EG_RESET_L
GND
PEX_CLKREQ_L
MAKE_BASE=TRUE
MAKE_BASE=TRUE
LVDS_IG_PANEL_PWR LVDS_IG_PANEL_PWR
MAKE_BASE=TRUE
CPU_VID<0..6>
TP_LVDS_IG_BKL_PWM
TP_LVDS_IG_B_CLKP
NC_LVDS_IG_A_DATAP<3>
MAKE_BASE=TRUE
NC_GPU_XTALOUT
NO_TEST=TRUE
NC_USB_HUB2_OCS3
MAKE_BASE=TRUE
NC_USB_HUB1_OCS4 NC_USB_HUB2_OCS3
USB_SDCARD_N
USB_SDCARD_P
USB_SDCARD_N
MAKE_BASE=TRUE
MAKE_BASE=TRUE
USB_SDCARD_P
CPU_CFG<3>
DP_IG_DDC_DATA
NC_USB_HUB1_OCS4
MAKE_BASE=TRUE
PP3V3_S3
USB_EXTC_N USB_EXTC_P
NC_SATA_EXTA_R2D_C_P
NC_SATA_EXTA_D2R_P
NC_SATA_EXTA_D2R_N
VOLTAGE=0V
MIN_LINE_WIDTH=0.6 mm
GND
MIN_NECK_WIDTH=0.095 mm
9 OF 132
<E4LABEL>
<SCH_NUM>
<BRANCH>
8 OF 101
8
87
8
18 84
62
8
20 40
8
39 40
8
17 87
8
18 87
74 91
9
74 91
9
74 91
74 91
13 91
8
31 67
6 8
53
6 8
53
8
17 94
8
17 94
8
17
84 93
84 93
8
71 73
8
73 82 86 87
6 8
18 93
6 8
18 93
8
18 93
8
18 93
6 8
18
8
18 93
8
18 93
8
32 77
8
32 78
8
12 91
8
87 89
8
87
8
74 87
8
17
8
17
8
17
8
45
8
17
8
17
8
18 84 93
8
18 80 84
8
18 80 84
8
17
8
39 40
8
18 93
8
18 93
8
18 84
93
18
18
8
18 87
8
45
8
17
8
17
8
17
8
17 94
6 8
53
9
9
8
17 94
68
69
8
31 67
8
71 73
8
17 87
6 8
18 93
8
74 87
8
79
8
18 93
8
32 77
8
32 78
8
12 91
8
73 82 86 87
6 7
50 56 75 76 77 78
8
18 84
8
87 89
8
20 40
8
17
8
18 80 84
8
17
8
17
6 8
53
8
18 84 93
8
18 84 93
8
74 87
8
74 87
8
18 87
8
18 87
12 15 91
6 8
18
6 8
18 93
8
18 93
8
79
8
36
8
35
8
36
8
34 36 93
8
34 36 93
8
34 36 93
8
34 36 93
9
25 91
8
18 80 84
8
35
6 7
17 20 31 32 33 34 35 36 48 50 53 54
55 72 73 87
101
35 93
35 93
8
17
8
17
8
17
Page 9
IN IN IN IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN IN
IN
IN IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN IN IN IN IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT OUT OUT
OUT
OUT OUT OUT OUT OUT
OUT OUT OUT OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
FDI_TX1
DMI_RX0*
DMI_TX2*
DMI_RX1*
PEG_RX0* PEG_RX1* PEG_RX2* PEG_RX3* PEG_RX4* PEG_RX5*
PEG_RX7*
PEG_RX6*
PEG_RX9*
PEG_RX8*
PEG_RX10*
PEG_RX12*
PEG_RX11*
PEG_RX13* PEG_RX14* PEG_RX15*
PEG_RX0 PEG_RX1
PEG_RX3
PEG_RX2
PEG_RX4 PEG_RX5 PEG_RX6 PEG_RX7 PEG_RX8 PEG_RX9
PEG_RX11
PEG_RX10
PEG_RX13
PEG_RX12
PEG_RX15
PEG_RX14
PEG_TX0* PEG_TX1* PEG_TX2*
PEG_TX4*
PEG_TX3*
PEG_TX5* PEG_TX6* PEG_TX7* PEG_TX8*
PEG_TX9* PEG_TX10* PEG_TX11* PEG_TX12* PEG_TX13* PEG_TX14* PEG_TX15*
PEG_TX0 PEG_TX1
PEG_TX3
PEG_TX2
PEG_TX5
PEG_TX4
PEG_TX6
PEG_TX8
PEG_TX7
PEG_TX9 PEG_TX10 PEG_TX11 PEG_TX12 PEG_TX13 PEG_TX14 PEG_TX15
DMI_RX2
DMI_RX0 DMI_RX1
DMI_RX3
DMI_TX0* DMI_TX1*
DMI_TX3*
DMI_TX0 DMI_TX1 DMI_TX2 DMI_TX3
FDI_TX1*
FDI_TX0*
FDI_TX2* FDI_TX3*
FDI_TX5*
FDI_TX4*
FDI_TX6* FDI_TX7*
FDI_TX0
FDI_TX3
FDI_TX2
FDI_TX4 FDI_TX5 FDI_TX6 FDI_TX7
FDI_FSYNC0 FDI_FSYNC1
FDI_LSYNC0
FDI_INT
FDI_LSYNC1
PEG_ICOMPI PEG_ICOMPO
PEG_RBIAS
PEG_RCOMPO
DMI_RX3*
DMI_RX2*
(SYM 1 OF 11)
FLEXIBLE DISPLAY INTERFACE
DMI
PCI EXPRESS -- GRAPHICS
RSVD37
RSVD36
RSVD33
RSVD32
RSVD_NCTF5
RSVD_NCTF6
RSVD_NCTF8
RSVD_NCTF7
RSVD27
RSVD24
RSVD26
RSVD23
RSVD22
RSVD21
RSVD20
RSVD19
RSVD18
RSVD17
RSVD16
RSVD15
RSVD_TP0
CFG17
CFG16
CFG15
CFG14
CFG13
CFG11 CFG12
CFG10
CFG9
CFG8
CFG7
CFG6
CFG5
CFG3 CFG4
CFG2
CFG1
CFG0
DC_TEST_A5
DC_TEST_A69 DC_TEST_A68
DC_TEST_A71
DC_TEST_C3
DC_TEST_C69
DC_TEST_C71
DC_TEST_E1
DC_TEST_E71
DC_TEST_BR1
DC_TEST_BR71
DC_TEST_BT3 DC_TEST_BT1
DC_TEST_BT69
DC_TEST_BV1
DC_TEST_BT71
DC_TEST_BV3
DC_TEST_BV68
DC_TEST_BV5
DC_TEST_BV71 DC_TEST_BV69
RSVD64 RSVD65
RSVD62 RSVD63
RSVD_TP1
RSVD_TP2
RSVD57 RSVD58
RSVD56
RSVD54 RSVD55
RSVD52 RSVD53
RSVD51
RSVD50
RSVD49
RSVD48
RSVD46 RSVD47
RSVD45
RSVD_NCTF1
RSVD_NCTF2
RSVD39
RSVD_NCTF3
RSVD38
RSVD34
RSVD_NCTF4
RSVD35
(SYM 5 OF 11)
RESERVED
BI BI
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER
SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
WF: RSVD nets with red wires have 0-ohm resistors to GND in CRB schematic.
WF: RSVD nets with arrows have offpage marks on CRB schematic.
CFG3: PCIe Lane Reversal 1 = Normal Operation 0 = Lanes Reversed
and level-shifted for
NOTE: HPD must be inverted
eDP_TX<3> eDP_TX<2> eDP_TX<1> eDP_TX<0>
eDP_TX#<0>
eDP_TX#<1>
eDP_TX#<2>
eDP_TX#<3>
eDP_HPD# eDP_AUX
eDP_AUX#
Auburndale (1.05V).
(eDP) pins
Embedded DisplayPort
(Auburndale only):
CFG4: Display Port Presence 1 = eDP Disabled 0 = Embedded Display Port Enabled
CFG0: PCIe Configuration Select 1 = Single PEG 0 = Bifurcation Enabled
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU) (IPU) (IPU) (IPU) (IPU) (IPU) (IPU) (IPU) (IPU)
(IPU)
(IPU)
18 91
18 91
18 91
18 91
18 91
18 91
18 91
18 91
18 91
18 91
18 91
18 91
18 91
18 91
18 91
18 91
18 91
18 91
18 91
18 91
18 91
18 91
18 91
18 91
18 91
18 91
18 91
18 91
18 91
18 91
18 91
18 91
18 91
18 91
18 91
18 91
18 91
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
74 91
8
74 91
8
74 91
8
74 91
8
74 91
8
74 91
8
74 91
8
74 91
8
74 91
8
74 91
8
74 91
8
74 91
8
74 91
8
74 91
8
74 91
8
74 91
8
8
8
8
8
8
8
8
8
8
8
8
74 91
8
74 91
8
74 91
8
74 91
8
8
8
8
8
8
74 91
8
74 91
8
74 91
8
74 91
8
74 91
8
74 91
8
74 91
8
74 91
8
74 91
8
74 91
8
74 91
8
74 91
750
MF-LF
1/16W
402
1%
R1012
1
2
1/16W
1%
49.9
402
MF-LF
R1010
1
2
25 91
25 91
25 91
25 91
25 91
25 91
25 91
25 91
25 91
25 91
25 91
25 91
25 91
25 91
8
25 91
25 91
25 91
25 91
BGA
OMIT
ARRANDALE
U1000
F9
F7
J6
J8
K9
K8
J2
J4
G17
H17
M15
K15
G13
J13
J11
F10
AC7 AC9
AB5
AA1 AB2
K1
L2
N5
N7
N2
M4
R2
P1
N9
N10
R8
R7
U6
U7
W10
W8
B12 A13
B11
D12
F40
G40
J38
G38
A24
B23
B21
D22
B19
A20
B18
D19
B16
A17
D15
B14
G34
H34
M34
P34
J28
G28
G25
H25
K24
H24
B28
D29
A27
B26
B25
D26
L40
N40
N38
L38
D33
B32
N28
L28
M25
N26
N24
M24
F21
G21
L20
J20
N32
M32
B39
D40
B37
A38
H32
G32
A34
B33
D36
B35
J30
L30
B30
A31
BGA
ARRANDALE
OMIT
U1000
AL4 AM2
AH1 AC2 AC4 AE2 AD1 AF8 AF6 AB7
AK1 AK2 AK4 AJ2 AT2 AG7 AF4 AG2
A5
A68
A69
A71
BR1
BR71
BT1
BT3
BT69
BT71
BV1
BV3
BV5
BV68
BV69
BV71
C3
C69
C71
E1
E71
T4 T2
U1 V2
AV71 AW70
AY69 BB69
D8 B7
A10
B9
W66 W64
AC69 AC71
AA71 AA69
R66 R64
AV69 AK71 AN69 AP66 AH66 AK66 AR71 AM66 AK69 AU71 AT70 AR69 AU69 AT67
AV4 AU2
BE69 BE71
BV8
BV6
BT5 BR5
F1
E3
C5 A6
AU1
AN7
AP2
51 99
51 99
SYNC_DATE=06/15/2009
SYNC_MASTER=K17_REF
CPU DMI/PEG/FDI/RSVD
CPU_CFG<0>
CPU_CFG<2>
=PEG_R2D_C_N<8>
=PEG_R2D_C_N<10> =PEG_R2D_C_N<11>
CPU_CFG<1>
CPU_CFG<4>
CPU_CFG<3>
CPU_CFG<5> CPU_CFG<6> CPU_CFG<7> CPU_CFG<8> CPU_CFG<9>
CPU_CFG<12> CPU_CFG<13> CPU_CFG<14> CPU_CFG<15> CPU_CFG<16>
TP_CPU_RSVD<15>
TP_CPU_RSVD<19>
TP_CPU_RSVD<26>
TP_CPU_RSVD<24>
TP_CPU_RSVD<27> NC_TP_CPU_RSVD_NCTF<7>
NC_TP_CPU_RSVD_NCTF<8> NC_TP_CPU_RSVD_NCTF<6>
NC_TP_CPU_RSVD_NCTF<5>
TP_CPU_RSVD<2> TP_CPU_RSVD<1>
TP_CPU_RSVD<64>
TP_CPU_RSVD<55>
TP_CPU_RSVD<54>
TP_CPU_RSVD<56> TP_CPU_RSVD<57>
TP_CPU_RSVD<45> TP_CPU_RSVD<46> TP_CPU_RSVD<47> TP_CPU_RSVD<48> TP_CPU_RSVD<49> TP_CPU_RSVD<50>
TP_CPU_RSVD<58>
TP_CPU_RSVD<52> TP_CPU_RSVD<53>
TP_CPU_RSVD<51>
NC_TP_CPU_RSVD<42>
NC_TP_CPU_RSVD<40>
NC_TP_CPU_RSVD<32> NC_TP_CPU_RSVD<33>
NC_TP_CPU_RSVD<36> NC_TP_CPU_RSVD<37>
NC_TP_CPU_RSVD<41>
NC_TP_CPU_RSVD<43>
NC_TP_CPU_RSVD<34>
NC_TP_CPU_RSVD<38> NC_TP_CPU_RSVD<39>
NC_TP_CPU_RSVD<35>
TP_CPU_TEST_BR1
TP_CPU_TEST_E1
TP_CPU_TEST_E71
TP_CPU_TEST_C3
TP_CPU_TEST_A5
TP_CPU_TEST_A68
CPU_TEST_C71_A71 CPU_TEST_C69_A69
FDI_LSYNC<1>
FDI_LSYNC<0>
FDI_INT
FDI_FSYNC<1>
FDI_FSYNC<0>
FDI_DATA_P<7>
FDI_DATA_P<6>
FDI_DATA_P<5>
FDI_DATA_P<4>
FDI_DATA_P<3>
FDI_DATA_P<2>
FDI_DATA_P<1>
FDI_DATA_P<0>
FDI_DATA_N<6> FDI_DATA_N<7>
FDI_DATA_N<5>
FDI_DATA_N<4>
FDI_DATA_N<3>
FDI_DATA_N<1> FDI_DATA_N<2>
FDI_DATA_N<0>
DMI_N2S_P<3>
DMI_N2S_P<2>
DMI_N2S_P<1>
DMI_N2S_P<0>
DMI_N2S_N<2> DMI_N2S_N<3>
DMI_N2S_N<1>
DMI_N2S_N<0>
DMI_S2N_P<3>
DMI_S2N_P<2>
DMI_S2N_P<0> DMI_S2N_P<1>
DMI_S2N_N<3>
DMI_S2N_N<2>
DMI_S2N_N<1>
DMI_S2N_N<0> CPU_PEG_COMP
CPU_PEG_RBIAS
=PEG_D2R_N<0>
=PEG_D2R_N<4> =PEG_D2R_N<5>
=PEG_D2R_N<2>
=PEG_D2R_N<1>
=PEG_D2R_N<3>
=PEG_D2R_N<9>
=PEG_D2R_N<7>
=PEG_D2R_N<6>
=PEG_D2R_N<8>
=PEG_D2R_N<14> =PEG_D2R_N<15>
=PEG_D2R_N<13>
=PEG_D2R_N<11>
PEG_D2R_P<12> PEG_D2R_P<11>
PEG_D2R_P<13>
PEG_D2R_P<14>
PEG_D2R_P<15>
PEG_D2R_P<7> PEG_D2R_P<6>
PEG_D2R_P<9>
PEG_D2R_P<10>
PEG_D2R_P<8>
PEG_D2R_P<1>
PEG_D2R_P<2>
PEG_D2R_P<3>
PEG_D2R_P<5> PEG_D2R_P<4>
=PEG_R2D_C_N<1> =PEG_R2D_C_N<2>
PEG_D2R_P<0>
=PEG_R2D_C_N<0>
=PEG_R2D_C_N<5> =PEG_R2D_C_N<6> =PEG_R2D_C_N<7>
=PEG_R2D_C_N<3> =PEG_R2D_C_N<4>
=PEG_R2D_C_N<13>
=PEG_R2D_C_N<12>
=PEG_R2D_C_N<9>
=PEG_R2D_C_N<15>
=PEG_R2D_C_N<14>
PEG_R2D_C_P<15> PEG_R2D_C_P<14>
PEG_R2D_C_P<11>
PEG_R2D_C_P<9>
PEG_R2D_C_P<10>
PEG_R2D_C_P<13> PEG_R2D_C_P<12>
PEG_R2D_C_P<6> PEG_R2D_C_P<5> PEG_R2D_C_P<4>
PEG_R2D_C_P<8> PEG_R2D_C_P<7>
PEG_R2D_C_P<0>
PEG_R2D_C_P<3> PEG_R2D_C_P<2> PEG_R2D_C_P<1>
=PEG_D2R_N<10>
=PEG_D2R_N<12>
TP_CPU_RSVD<21>
TP_CPU_RSVD<23>
TP_CPU_RSVD<22>
TP_CPU_RSVD<20>
TP_CPU_RSVD<65>
TP_CPU_TEST_BR71
TP_CPU_RSVD<18>
TP_CPU_RSVD_TP0
CPU_CFG<17>
CPU_CFG<11>
CPU_CFG<10>
CPU_TEST_BV1_BT1 CPU_TEST_BT71_BT69
CPU_TEST_BV3_BT3
TP_CPU_TEST_BV5
TP_CPU_RSVD<17>
TP_CPU_RSVD<16>
TP_CPU_TEST_BV68
CPU_TEST_BV71_BV69
CPU_THERMD_P CPU_THERMD_N
10 OF 132
<E4LABEL>
<SCH_NUM>
<BRANCH>
9 OF 101
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
91
91
6
6
6
6
6
6
6
6
Page 10
OUT
IN IN
IN
IN
IN
IN
OUT
OUT
BI
BI
BI
OUT
IN
IN
OUT
IN IN
IN
IN
OUT
IN
OUT
OUT
OUT
IN
OUT OUT OUT
IN
OUT OUT OUT OUT
IN
IN
BCLK_ITP
BCLK_ITP*
PEG_CLK
SM_RCOMP2
PM_EXT_TS1*
PRDY* PREQ*
THERMTRIP*
COMP1
COMP2
COMP3
COMP0
PROC_DETECT
PROCHOT*
PECI
CATERR*
RSTIN*
TAPPWRGOOD
VTTPWRGOOD
VCCPWRGOOD_0
SM_DRAMPWROK
VCCPWRGOOD_1
PM_SYNC
RESET_OBS*
BPM7*
BPM6*
BPM5*
BPM4*
BPM3*
BPM2*
BPM1*
BPM0*
TDO_M
DBR*
TDI_M
TDO
TDI
BCLK*
BCLK
TRST*
TMS
TCK
PM_EXT_TS0*
SM_RCOMP1
SM_RCOMP0
PEG_CLK*
DPLL_REF_SSCLK
DPLL_REF_SSCLK*
SM_DRAMRST*
PWR MANAGEMENTTHERMAL
JTAG & MBP
(SYM 2 OF 11)
MISC
DDR3
MISC
CLOCKS
IN
OUT OUT
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER
SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
(IPU)
(IPU)
(IPU) (IPU)
(IPU) (IPU)
(IPU)
(IPU)
(IPD)
(IPD)
(IPD)
(IPU) (IPU)
(IPU)
(IPU)
(GND)
(IPU)
(IPD)
(IPU)
31
46 91
46 91
750
1/16W
1%
402
MF-LF
R1126
1
2
1.5K
1%
402
1/16W MF-LF
R1125
1 2
27
18 31 91
70 91
17 93
25 91
25 91
20 91
46 68 91
18 91
20 46 91
NO STUFF
402
1/16W MF-LF
5%
68
R1102
1
2
5%
68
MF-LF
1/16W
402
R1101
1
2
MF-LF
1/16W 402
1%
49.9
R1100
1
2
17 93
49.9
MF-LF
402
1%
1/16W
R1112
1
2
1% MF-LF
1/16W 402
49.9
R1113
1
2
20
MF-LF
1/16W
402
1%
R1110
1
2
20
1%
402
1/16W MF-LF
R1111
1
2
25 91
25 91
25 91
25 91
25
17 91
25
25
25
25 91
25 27 91
25 91
25 91
25 91
25 91
17 91
25 91
25 91
25 91
25 91
1%
100
MF-LF
1/16W
402
R1162
1
2
1%
MF-LF
1/16W
402
130
R1160
1
2
1%
24.9
402
1/16W MF-LF
R1161
1
2
MF-LF
5%
402
10K
1/16W
R1150
1
2
1/16W MF-LF
5%
402
10K
R1151
1
2
20 91
5%
51
MF-LF
1/16W
402
R1170
1
2
20 25 91
1K
5% MF-LF
402
1/16W
R1103
1
2
OMIT
BGA
ARRANDALE
U1000
AK7 AK8
K71 J70
J69 J67 J62 K65 K62 J64 K69 M69
N61
AE66
AD69
AC70
AD71
W71
Y2 W4
N19
L21 J21
AV66 AV64
M17
U71 U69
M71
N67
N70
G3
AM5
BJ12
BV33 BP39 BV40
Y70
T67
T69
P71
T71
T70
N17
N65 P69
Y67
AM7
H15
20 91
402
1K
5% MF-LF
1/16W
R1120
1
2
25 91
25 91
CPU Clock/Misc/JTAG
SYNC_MASTER=K17_REF
SYNC_DATE=06/15/2009
PM_MEM_PWRGD
PP1V05_S0
CPU_COMP3 CPU_COMP2
XDP_DBRESET_L
JTAG_CPU_TDO
XDP_CPUPWRGD
PM_SYNC
FSB_CPURST_L
CPU_COMP0
CPU_PROCHOT_L
CPU_PECI
PM_THRMTRIP_L
CPU_CATERR_L
XDP_BPM_L<6>
XDP_BPM_L<4>
PP1V05_S0
PM_EXT_TS_L<0>
GFX_CLK120M_DPLLSS_N
CPU_MEM_RESET_L CPU_SM_RCOMP0
CPU_PWRGD
CPUVTTS0_PGOOD
CPU_SM_RCOMP2
CPU_SM_RCOMP1
PM_EXT_TS_L<1>
GFX_CLK120M_DPLLSS_P
FSB_CLK133M_ITP_N
FSB_CLK133M_CPU_N FSB_CLK133M_ITP_P
PCIE_CLK100M_CPU_P
XDP_PRDY_L XDP_PREQ_L
CPU_COMP1
PLT_RESET_LS1V1_L
XDP_BPM_L<7>
XDP_BPM_L<5>
XDP_BPM_L<0>
JTAG_GMCH_TDI
FSB_CLK133M_CPU_P
XDP_TMS
XDP_TCK
PCIE_CLK100M_CPU_N
PLT_RST_BUF_L
XDP_BPM_L<3>
XDP_BPM_L<2>
XDP_BPM_L<1>
JTAG_GMCH_TDO
JTAG_CPU_TDI
XDP_TRST_L
TP_CPU_SKTOCC_L
11 OF 132
<E4LABEL>
<SCH_NUM>
<BRANCH>
10 OF 101
6 7
10 12 13 15 17 18 20 21
23 24 25 26 40 70 73 86
91
91
91
91
6 7
10 12 13 15 17 18 20 21
23 24 25 26 40 70 73 86
91
91
91
91
Page 11
BI BI BI BI BI BI BI BI BI BI BI BI BI BI
BI
BI
BI BI BI BI BI BI
BI
BI
BI BI BI BI BI BI
BI
BI
BI BI BI BI BI BI
BI
BI
BI BI BI BI BI BI
BI
BI
BI BI BI BI BI BI
BI
BI
BI BI BI BI BI BI
BI
BI
OUT
OUT
OUT
OUT
OUT
OUT
BI
BI
BI
BI
BI BI
BI BI
BI BI
BI BI
BI BI
BI BI
OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT
OUT OUT OUT OUT OUT OUT OUT OUT
OUT OUT
OUT
OUT OUT
OUT
OUT OUT
OUT OUT
BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI
OUT OUT OUT
OUT
OUT
OUT
OUT OUT
OUT
OUT OUT
OUT
OUT OUT
OUT OUT
OUT OUT OUT OUT OUT OUT OUT OUT
BI BI BI BI BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT
SA_RAS* SA_WE*
SA_CAS*
SA_BS2
SA_BS1
SA_BS0
SA_DQ62 SA_DQ63
SA_DQ60 SA_DQ61
SA_DQ59
SA_DQ58
SA_DQ57
SA_DQ54
SA_DQ56
SA_DQ55
SA_DQ53
SA_DQ52
SA_DQ51
SA_DQ50
SA_DQ49
SA_DQ48
SA_DQ47
SA_DQ46
SA_DQ44 SA_DQ45
SA_DQ41 SA_DQ42 SA_DQ43
SA_DQ40
SA_DQ39
SA_DQ37
SA_DQ36
SA_DQ38
SA_DQ35
SA_DQ34
SA_DQ32
SA_DQ31
SA_DQ33
SA_DQ30
SA_DQ29
SA_DQ28
SA_DQ27
SA_DQ26
SA_DQ24 SA_DQ25
SA_DQ23
SA_DQ22
SA_DQ21
SA_DQ19 SA_DQ20
SA_DQ18
SA_DQ17
SA_DQ16
SA_DQ13
SA_DQ15
SA_DQ14
SA_DQ12
SA_DQ11
SA_DQ10
SA_DQ9
SA_DQ8
SA_DQ7
SA_DQ5 SA_DQ6
SA_DQ3 SA_DQ4
SA_DQ1 SA_DQ2
SA_DQ0
SA_MA15
SA_MA14
SA_MA13
SA_MA12
SA_MA11
SA_MA10
SA_MA9
SA_MA7 SA_MA8
SA_MA6
SA_MA5
SA_MA4
SA_MA3
SA_MA2
SA_MA1
SA_MA0
SA_DQS7
SA_DQS6
SA_DQS4 SA_DQS5
SA_DQS3
SA_DQS1 SA_DQS2
SA_DQS0
SA_DQS7*
SA_DQS6*
SA_DQS5*
SA_DQS4*
SA_DQS3*
SA_DQS2*
SA_DQS1*
SA_DQS0*
SA_DM7
SA_DM6
SA_DM5
SA_DM4
SA_DM3
SA_DM2
SA_DM1
SA_DM0
SA_ODT1
SA_ODT0
SA_CS1*
SA_CS0*
SA_CK1*
SA_CKE1
SA_CKE0
SA_CK1
SA_CK0
SA_CK0*
(SYM 3 OF 11)
DDR SYSTEM MEMORY A
SB_DQ0 SB_CK0 SB_DQ1
SB_CK0*
SB_DQ2
SB_CKE0
SB_DQ3 SB_DQ4
SB_CK1
SB_DQ5
SB_CK1*
SB_DQ6 SB_DQ7
SB_CKE1 SB_DQ8 SB_DQ9
SB_CS0* SB_DQ10 SB_CS1* SB_DQ11 SB_DQ12 SB_ODT0 SB_DQ13 SB_ODT1 SB_DQ14 SB_DQ15
SB_DM0
SB_DQ16
SB_DM1
SB_DQ17
SB_DM2
SB_DQ18
SB_DM3
SB_DQ19
SB_DM4
SB_DQ20
SB_DM5
SB_DQ21
SB_DM6
SB_DQ22
SB_DM7 SB_DQ23 SB_DQ24
SB_DQS0*
SB_DQ25
SB_DQS1*
SB_DQ26
SB_DQS2*
SB_DQ27
SB_DQS3*
SB_DQ28
SB_DQS4*
SB_DQ29
SB_DQS5*
SB_DQ30
SB_DQS6*
SB_DQ31
SB_DQS7* SB_DQ32 SB_DQ33 SB_DQS0 SB_DQ34 SB_DQS1 SB_DQ35 SB_DQS2 SB_DQ36 SB_DQS3 SB_DQ37 SB_DQS4 SB_DQ38 SB_DQS5 SB_DQ39 SB_DQS6 SB_DQ40 SB_DQS7 SB_DQ41 SB_DQ42
SB_MA0
SB_DQ43
SB_MA1
SB_DQ44
SB_MA2
SB_DQ45
SB_MA3
SB_DQ46
SB_MA4
SB_DQ47
SB_MA5
SB_DQ48
SB_MA6
SB_DQ49
SB_MA7
SB_DQ50
SB_MA8
SB_DQ51
SB_MA9 SB_DQ52 SB_MA10 SB_DQ53 SB_MA11 SB_DQ54 SB_MA12 SB_DQ55 SB_MA13 SB_DQ56 SB_MA14 SB_DQ57 SB_MA15 SB_DQ58 SB_DQ59 SB_DQ60 SB_DQ61 SB_DQ62 SB_DQ63
SB_BS0 SB_BS1 SB_BS2
SB_CAS* SB_RAS* SB_WE*
DDR SYSTEM MEMORY B
(SYM 4 OF 11)
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER
SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
29 92
29 92
29 92
29 92
29 92
29 92
29 92
29 92
29 92
29 92
29 92
29 92
29 92
29 92
29 92
29 92
29 92
29 92
29 92
29 92
29 92
29 92
29 92
29 92
29 92
29 92
29 92
29 92
29 92
29 92
29 92
29 92
29 92
29 92
29 92
29 92
29 92
28 29 92
29 92
29 92
29 92
29 92
29 92
29 92
29 92
29 92
29 92
29 92
29 92
29 92
29 92
29 92
29 92
29 92
29 92
29 92
29 92
29 92
29 92
29 92
29 92
29 92
29 92
29 92
28 92
28 92
28 92
28 92
28 92
28 92
29 92
29 92
29 92
29 92
29 92
29 92
29 92
29 92
29 92
29 92
29 92
29 92
28 29 92
29 92
28 29 92
29 92
28 92
28 92
28 92
28 92
28 92
28 92
28 92
28 92
28 92
28 92
28 92
28 92
28 92
28 92
28 92
28 92
28 29 92
29 92
29 92
29 92
29 92
29 92
29 92
29 92
28 92
28 92
28 92
28 92
28 92
28 92
28 92
28 92
28 92
28 92
29 92
29 92
29 92
29 92
29 92
29 92
29 92
29 92
29 92
29 92
29 92
29 92
29 92
29 92
29 92
29 92
29 92
29 92
29 92
29 92
29 92
29 92
29 92
29 92
29 92
29 92
29 92
29 92
29 92
29 92
29 92
29 92
29 92
29 92
29 92
29 92
29 92
29 30 92
29 92
29 92
29 92
29 92
29 92
29 92
29 92
29 92
29 92
29 92
29 92
29 92
29 92
29 92
29 92
29 92
29 92
29 92
29 92
29 92
29 92
29 92
29 92
29 92
29 92
29 92
30 92
30 92
30 92
30 92
30 92
30 92
30 92
30 92
30 92
30 92
30 92
30 92
30 92
30 92
30 92
30 92
29 30 92
29 92
29 92
29 92
29 92
29 92
29 92
29 92
29 30 92
29 92
29 92
29 92
29 92
29 92
29 92
29 92
29 30 92
29 92
29 92
29 92
29 92
29 92
29 92
29 92
30 92
30 92
30 92
30 92
30 92
30 92
30 92
30 92
30 92
30 92
30 92
30 92
30 92
30 92
30 92
30 92
OMIT
BGA
ARRANDALE
U1000
BT38 BH38 BF21
BK43
BM34 BP35
BK36 BH36
BF20
BK24
BH40 BJ47
BB10 BJ10 BM15 BN24 BG44 BG53 BN62 BH59
AT8 AT6
BK5
BH13
BF9 BF6 BK7 BN8
BN11
BN9 BG17 BK15
BB5
BK9 BG15 BH17 BK17 BN20 BN17 BK25 BH25 BJ20 BH21
BB9
BG24 BG25 BJ40 BM43 BF47 BF48 BN40 BH43 BN44 BN47
AV7
BN48 BN51 BH53 BJ55 BH48 BJ48 BM53 BN55 BF55 BN57
AV6
BN65 BJ61 BF57 BJ57 BK64 BK61 BJ63 BF64 BB64 BB66
BE6
BJ66 BF65 AY64 BC70
BE8 BF11 BE11
AY7
AY5
BJ5
BJ7
BL13
BN13
BN21
BL21
BK44
BH44
BH51
BK51
BM60
BP58
BE64
BE62
BT36 BP33
BH34 BH30 BJ28 BF40 BN28 BN25
BV36 BG34 BG32 BN32 BK32 BJ30 BN30 BF28
BF43 BL47
BL38 BF38
BGA
ARRANDALE
OMIT
U1000
BV43 BV41 BV24
BU46
BU33 BV34
BV38 BU39
BT26
BT24
BP46 BT43
BB4 BL4 BT13 BP22 BV47 BV57 BU65 BF67
BA2 AW2
BR6 BR8 BJ4 BK2
BU9 BV10 BR10 BT12 BT15 BV15
BD1
BV12 BP12 BV17 BU16 BP15 BU19 BV22 BT22 BP19 BV19
BE4
BV20 BT20 BT48 BV48 BV50 BP49 BT47 BV52 BV54 BT54
AY1
BP53 BU53 BT59 BT57 BP56 BT55 BU60 BV59 BV61 BP60
BC2
BR66 BR64 BR62 BT61 BN68 BL69 BJ71 BF70 BG71 BC67
BF2
BK70 BK67 BD71 BD69
BH2
BG4
BG1
BD4
BE2
BN4
BM3
BV13
BU12
BT17
BT19
BT50
BT52
BU56
BV55
BV62
BU63
BJ69
BG69
BT34 BP30
BU42 BU26 BT29 BT45 BV26 BU23
BV29 BU30 BV31 BT33 BT31 BP26 BV27 BT27
BV45 BU49
BT40 BT41
CPU DDR3 Interfaces
SYNC_MASTER=K17_REF
SYNC_DATE=06/15/2009
MEM_B_DQ<27>
MEM_B_DQ<0>
MEM_B_CLK_P<0>
MEM_B_DQ<1>
MEM_B_CLK_N<0>
MEM_B_DQ<2>
MEM_B_CKE<0>
MEM_B_DQ<3> MEM_B_DQ<4>
MEM_B_CLK_P<1>
MEM_B_DQ<5>
MEM_B_CLK_N<1>
MEM_B_DQ<6> MEM_B_DQ<7>
MEM_B_CKE<1> MEM_B_DQ<8> MEM_B_DQ<9>
MEM_B_CS_L<0> MEM_B_DQ<10>
MEM_B_CS_L<1> MEM_B_DQ<11> MEM_B_DQ<12> MEM_B_ODT<0> MEM_B_DQ<13> MEM_B_ODT<1> MEM_B_DQ<14> MEM_B_DQ<15>
MEM_B_DM<0> MEM_B_DQ<16>
MEM_B_DM<1> MEM_B_DQ<17>
MEM_B_DM<2> MEM_B_DQ<18>
MEM_B_DM<3> MEM_B_DQ<19>
MEM_B_DM<4> MEM_B_DQ<20>
MEM_B_DM<5> MEM_B_DQ<21>
MEM_B_DM<6> MEM_B_DQ<22>
MEM_B_DM<7> MEM_B_DQ<23> MEM_B_DQ<24>
MEM_B_DQS_N<0> MEM_B_DQ<25>
MEM_B_DQS_N<1> MEM_B_DQ<26>
MEM_B_DQS_N<2>
MEM_B_DQS_N<3> MEM_B_DQ<28>
MEM_B_DQS_N<4> MEM_B_DQ<29>
MEM_B_DQS_N<5> MEM_B_DQ<30>
MEM_B_DQS_N<6> MEM_B_DQ<31>
MEM_B_DQS_N<7> MEM_B_DQ<32> MEM_B_DQ<33>
MEM_B_DQS_P<0> MEM_B_DQ<34>
MEM_B_DQS_P<1> MEM_B_DQ<35>
MEM_B_DQS_P<2> MEM_B_DQ<36>
MEM_B_DQS_P<3> MEM_B_DQ<37>
MEM_B_DQS_P<4> MEM_B_DQ<38>
MEM_B_DQS_P<5> MEM_B_DQ<39>
MEM_B_DQS_P<6> MEM_B_DQ<40>
MEM_B_DQS_P<7> MEM_B_DQ<41> MEM_B_DQ<42>
MEM_B_A<0> MEM_B_DQ<43>
MEM_B_A<1> MEM_B_DQ<44>
MEM_B_A<2> MEM_B_DQ<45>
MEM_B_A<3> MEM_B_DQ<46>
MEM_B_A<4> MEM_B_DQ<47>
MEM_B_A<5> MEM_B_DQ<48>
MEM_B_A<6> MEM_B_DQ<49>
MEM_B_A<7> MEM_B_DQ<50>
MEM_B_A<8> MEM_B_DQ<51>
MEM_B_A<9> MEM_B_DQ<52>
MEM_B_A<10> MEM_B_DQ<53>
MEM_B_A<11> MEM_B_DQ<54>
MEM_B_A<12> MEM_B_DQ<55>
MEM_B_A<13> MEM_B_DQ<56>
MEM_B_A<14> MEM_B_DQ<57>
MEM_B_A<15> MEM_B_DQ<58> MEM_B_DQ<59> MEM_B_DQ<60> MEM_B_DQ<61> MEM_B_DQ<62> MEM_B_DQ<63>
MEM_B_BA<0> MEM_B_BA<1> MEM_B_BA<2>
MEM_B_CAS_L MEM_B_RAS_L MEM_B_WE_L
MEM_A_CLK_P<0>
MEM_A_DQ<4>
MEM_A_CS_L<1>
MEM_A_A<2>
MEM_A_CLK_N<0>
MEM_A_RAS_L MEM_A_WE_L
MEM_A_CAS_L
MEM_A_BA<2>
MEM_A_BA<1>
MEM_A_BA<0>
MEM_A_DQ<62> MEM_A_DQ<63>
MEM_A_DQ<60> MEM_A_DQ<61>
MEM_A_DQ<59>
MEM_A_DQ<58>
MEM_A_DQ<57>
MEM_A_DQ<54>
MEM_A_DQ<56>
MEM_A_DQ<55>
MEM_A_DQ<53>
MEM_A_DQ<52>
MEM_A_DQ<51>
MEM_A_DQ<50>
MEM_A_DQ<49>
MEM_A_DQ<48>
MEM_A_DQ<47>
MEM_A_DQ<46>
MEM_A_DQ<44> MEM_A_DQ<45>
MEM_A_DQ<41> MEM_A_DQ<42> MEM_A_DQ<43>
MEM_A_DQ<40>
MEM_A_DQ<39>
MEM_A_DQ<37>
MEM_A_DQ<36>
MEM_A_DQ<38>
MEM_A_DQ<35>
MEM_A_DQ<34>
MEM_A_DQ<32>
MEM_A_DQ<31>
MEM_A_DQ<33>
MEM_A_DQ<30>
MEM_A_DQ<29>
MEM_A_DQ<28>
MEM_A_DQ<27>
MEM_A_DQ<26>
MEM_A_DQ<24> MEM_A_DQ<25>
MEM_A_DQ<23>
MEM_A_DQ<22>
MEM_A_DQ<21>
MEM_A_DQ<19> MEM_A_DQ<20>
MEM_A_DQ<18>
MEM_A_DQ<17>
MEM_A_DQ<16>
MEM_A_DQ<13>
MEM_A_DQ<15>
MEM_A_DQ<14>
MEM_A_DQ<12>
MEM_A_DQ<11>
MEM_A_DQ<10>
MEM_A_DQ<9>
MEM_A_DQ<8>
MEM_A_DQ<7>
MEM_A_DQ<5> MEM_A_DQ<6>
MEM_A_DQ<3>
MEM_A_DQ<1> MEM_A_DQ<2>
MEM_A_DQ<0>
MEM_A_A<15>
MEM_A_A<14>
MEM_A_A<13>
MEM_A_A<12>
MEM_A_A<11>
MEM_A_A<10>
MEM_A_A<9>
MEM_A_A<7> MEM_A_A<8>
MEM_A_A<6>
MEM_A_A<5>
MEM_A_A<4>
MEM_A_A<3>
MEM_A_A<1>
MEM_A_A<0>
MEM_A_DQS_P<7>
MEM_A_DQS_P<6>
MEM_A_DQS_P<4> MEM_A_DQS_P<5>
MEM_A_DQS_P<3>
MEM_A_DQS_P<1> MEM_A_DQS_P<2>
MEM_A_DQS_P<0>
MEM_A_DQS_N<7>
MEM_A_DQS_N<6>
MEM_A_DQS_N<5>
MEM_A_DQS_N<4>
MEM_A_DQS_N<3>
MEM_A_DQS_N<2>
MEM_A_DQS_N<1>
MEM_A_DQS_N<0>
MEM_A_DM<7>
MEM_A_DM<6>
MEM_A_DM<5>
MEM_A_DM<4>
MEM_A_DM<3>
MEM_A_DM<2>
MEM_A_DM<1>
MEM_A_DM<0>
MEM_A_ODT<1>
MEM_A_ODT<0>
MEM_A_CS_L<0>
MEM_A_CLK_N<1> MEM_A_CKE<1>
MEM_A_CKE<0>
MEM_A_CLK_P<1>
12 OF 132
<E4LABEL>
<SCH_NUM>
<BRANCH>
11 OF 101
Page 12
OUT OUT OUT OUT OUT OUT OUT
OUT
OUT
OUT
OUT OUT
IN
OUT
OUT
VCAP0_15
VCAP0_17
VCC_1 VCC_2 VCC_3 VCC_4 VCC_5
VCC_7
VCC_6
VCC_9
VCC_10
VCC_12
VCC_11
VCC_14
VCC_13
VCC_15
VCC_17
VCC_16
VCC_18 VCC_19 VCC_20 VCC_21 VCC_22
VCC_25
VCC_24
VCC_23
VCC_26 VCC_27
VCC_29 VCC_30
VCC_28
VCC_32
VCC_31
VCC_34
VCC_33
VCC_35
VCC_37
VCC_36
VCC_38
VCC_40
VCC_39
VCC_42
VCC_41
VCC_43 VCC_44 VCC_45 VCC_46 VCC_47
VCC_50
VCC_49
VCC_51 VCC_52 VCC_53
VCC_55
VCC_54
VCC_56
VCC_58
VCC_57
VCC_60
VCC_59
VCC_62
VCC_61
VCC_63 VCC_64 VCC_65 VCC_66 VCC_67 VCC_68 VCC_69 VCC_70 VCC_71 VCC_72 VCC_73 VCC_74 VCC_75 VCC_76 VCC_77 VCC_78
VCC_81
VCC_79 VCC_80
VCC_83
VCC_82
VCC_84 VCC_85 VCC_86 VCC_87
VCC_89
VCC_88
VCAP0_1 VCAP0_2
VCAP0_4
VCAP0_3
VCAP0_5 VCAP0_6 VCAP0_7 VCAP0_8 VCAP0_9
VCAP0_12
VCAP0_10 VCAP0_11
VCAP0_14
VCAP0_16
VCAP0_19
VCAP0_18
VCAP0_20 VCAP0_21 VCAP0_22 VCAP0_23 VCAP0_24 VCAP0_25 VCAP0_26 VCAP0_27
VCAP1_2
VCAP1_1
VCAP1_5
VCAP1_3 VCAP1_4
VCAP1_7
VCAP1_6
VCAP1_8
VCAP1_10
VCAP1_9
VCAP1_13
VCAP1_11 VCAP1_12
VCAP1_15
VCAP1_14
VCAP1_18
VCAP1_17
VCAP1_16
VCAP1_20
VCAP1_19
VCAP1_23
VCAP1_21 VCAP1_22
VCAP1_24 VCAP1_25
VCAP1_27
VCAP1_26
VCAP0_13
VCC_8
VCC_48
(SYM 8 OF 11)
CPU CORE SUPPLY
POWER
VSS_SENSE_VTT
VTT_SENSE
VSS_SENSE
VCC_SENSE
ISENSE
VID2 VID3 VID4
PSI*
VTT0_9
VTT0_22
VTT0_24
VTT0_23
VTT0_26
VTT0_25
VTT0_27 VTT0_28 VTT0_29 VTT0_30 VTT0_31 VTT0_32 VTT0_33 VTT0_34
VTT0_36
VTT0_35
VTT0_37 VTT0_38 VTT0_39 VTT0_40 VTT0_41 VTT0_42 VTT0_43 VTT0_44 VTT0_45 VTT0_46 VTT0_47 VTT0_48 VTT0_49 VTT0_50 VTT0_51 VTT0_52 VTT0_53 VTT0_54 VTT0_55 VTT0_56 VTT0_57 VTT0_58 VTT0_59
VTT0_62
VTT0_60 VTT0_61
VTT0_63 VTT0_64 VTT0_65
VTT0_67
VTT0_66
VTT0_68
VTT0_70
VTT0_69
VTT0_72
VTT0_71
VTT0_73
VTT0_4
VTT0_6
VTT0_5
VTT0_7 VTT0_8
VTT0_10 VTT0_11
VTT0_13
VTT0_12
VTT0_16
VTT0_15
VTT0_14
VTT0_17 VTT0_18 VTT0_19 VTT0_20 VTT0_21
VID5 VID6
VTT_SELECT1
PROC_DPRSLPVR
VTT0_1 VTT0_2 VTT0_3
VID1
VID0
VCCPLL1 VCCPLL2
VCCPLL4
VCCPLL3
VCCPLL5
VDDQ_CK1 VDDQ_CK2
1.8V
(SYM 6 OF 11)
1.1V RAIL POWER
CPU VIDS
SENSE LINES
POWER
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER
SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
NOTE: VCAP1 is sourced by CPU
but provide bypass caps on PCB.
Clarksfield: 1.1V
(Controlled by VTT_SELECT pin)
Arrandale: 1.05V
but provide bypass caps on PCB.
Do not connect to power supply,
Do not connect to power supply,
NOTE: VCAP0 is sourced by CPU
VTT_SELECT: 1 = 1.05V, 0 = 1.1V
8
15 91
8
15 91
8
15 91
8
15 91
8
15 91
8
15 91
8
15 91
8
91
15 68 91
15 68 91
70 91
70 91
50 68 91
PLACE_NEAR=U1000.F63:25.4MM
MF-LF
402
100
1%
1/16W
R1301
1
2
68 91
68 91
PLACE_NEAR=U1000.F64:25.4MM
MF-LF
402
100
1%
1/16W
R1300
1
2
PLACE_NEAR=U1000.N13:25.4MM
1/16W
10
MF-LF 402
1%
R1305
1
2
PLACE_NEAR=U1000.R12:25.4MM
MF-LF 402
1% 1/16W
10
R1306
1
2
ARRANDALE
BGA
OMIT
U1000
BD55
AW57 AW53 AW50 AU55 AU51 AU48 AR55 AR51 AR48 AN57
BD51
AN53 AN50 AL57 AL53 AL50 AK57 AK53 AK50
BD48 BB55 BB51 BB48 AY57 AY53 AY50
BD44
AW46 AW42 AW39 AU44 AU41 AU37 AR44 AR41 AR37 AN46
BD41
AN42 AN39 AL46 AL42 AL39 AK46 AK42 AK39
BD37 BB44 BB41 BB37 AY46 AY42 AY39
AF57
AF41 AD55 AD51 AD48 AD44 AD41 AB55 AB51 AB48 AB44
AF55
AB41 AA55 AA51 AA48 AA44 AA41 W55 W51 W48 W44
AF53
W41 U55 U51 U48 U44 U41 R55 R51 R48 R44
AF51
R41 P60 N55 N51 N48 N44 N42 M60 M51 M44
AF50
L55 K60 K51 K44 J55 H60 H51 H44 G60 G55
AF48
G51 G44 F55 E60 E57 E53 E50 E46 E42 D59
AF46
D57 D55 D54 D52 D50 D48 D47 D45 D43 B60
AF44
B56 B53 B49 B46 B42 A57 A54 A50 A47 A43
AF42
OMIT
BGA
ARRANDALE
U1000
A41
F66
F68
F64
W39 W37 U37 R39 R37
BB14 BB12
A61 D61 D62 A62 B63 D64 D66
F63
R12
BF60
AW33 AW14 AW12 AU60 AU59 AU12 AR60 AR59 AR12 AN60
BF59
AN59 AN35 AN33 AN17 AN15 AN14 AN12 AM10 AL60 AL59
BD60
AL17 AL15 AL14 AL12 AK35 AK33 AF39 AF37 AF35 AF33
BD59
AF32 AF30 AD39 AD37 AD35 AD33 AD32 AD30 W35 W33
BB60
W32 W30 W28 W26 W24 W23 U35 U33 U32 U30
BB59
U28 U26 U24 U23 R35 R33 R32 R30 R28 R26
AY60
R24 R23 AY10 AN9
AW60 AW35
AN1
N13
SYNC_DATE=06/15/2009
SYNC_MASTER=K17_REF
CPU Power (1 of 2)
CPU_VID<1> CPU_VID<2> CPU_VID<3>
CPUIMVP_IMON
PM_DPRSLPVR
PP1V05_S0
PP1V05_S0
CPU_VTTSENSE_P CPU_VTTSENSE_N
PPVCORE_S0_CPU_VCAP0
PP1V8_S0
CPU_VCCSENSE_N
CPU_VID<4>
CPU_PSI_L
CPU_VID<5> CPU_VID<6>
TP_CPU_VTT_SELECT
CPU_VID<0>
PPVCORE_S0_CPU
PPVCORE_S0_CPU
PPVCORE_S0_CPU_VCAP1
CPU_VCCSENSE_P
PP1V5_S3_CPU_VCCDDR_CLK
MIN_NECK_WIDTH=0.2mm VOLTAGE=1.5V
MIN_LINE_WIDTH=0.4mm
13 OF 132
<E4LABEL>
<SCH_NUM>
<BRANCH>
12 OF 101
6 7
10 12 13 15 17 18 20 21 23
24 25 26 40 70 73 86
6 7
10 12 13 15 17 18 20 21
23 24 25 26 40 70 73 86
7
16
6 7
16 21 23 24 58 71 72 87
6 7
12 15 49 68
6 7
12 15 49 68
7
16
16
Page 13
VAXG35
VTT1_7
VTT1_9 VTT1_10
VTT1_8
VTT1_5
VAXG3
VAXG2
VAXG1
VSSAXG_SENSE
VAXG_SENSE
VCAP2_19
VCAP2_17 VCAP2_18
VCAP2_16
VCAP2_14 VCAP2_15
VCAP2_12 VCAP2_13
VCAP2_11
VCAP2_10
VCAP2_9
VCAP2_8
VCAP2_6 VCAP2_7
VCAP2_5
VCAP2_4
VCAP2_3
VCAP2_1 VCAP2_2
VTT1_11
VTT1_6
VTT1_4
VTT1_3
VTT1_2
VTT1_1
VAXG37
VAXG36
VAXG33 VAXG34
VAXG32
VAXG31
VAXG30
VAXG27
VAXG29
VAXG28
VAXG25 VAXG26
VAXG23 VAXG24
VAXG22
VAXG20 VAXG21
VAXG19
VAXG17 VAXG18
VAXG14
VAXG16
VAXG15
VAXG13
VAXG12
VAXG11
VAXG10
VAXG9
VAXG8
VAXG7
VAXG6
VAXG5
VAXG4
VTT1_21
VTT1_20
VTT1_18 VTT1_19
VTT1_17
VTT1_16
VTT1_15
VTT1_14
VTT1_13
VTT1_12
VTT0_DDR9
VTT0_DDR8
VTT0_DDR7
VTT0_DDR6
VTT0_DDR5
VTT0_DDR4
VTT0_DDR3
VTT0_DDR2
VTT0_DDR1
VTT0_DDR
VDDQ36
VDDQ35
VDDQ34
VDDQ33
VDDQ31 VDDQ32
VDDQ30
VDDQ29
VDDQ28
VDDQ27
VDDQ26
VDDQ24 VDDQ25
VDDQ23
VDDQ21 VDDQ22
VDDQ20
VDDQ19
VDDQ18
VDDQ17
VDDQ16
VDDQ15
VDDQ13 VDDQ14
VDDQ12
VDDQ11
VDDQ10
VDDQ9
VDDQ8
VDDQ7
VDDQ6
VDDQ5
VDDQ4
VDDQ3
VDDQ2
GFX_IMON
VDDQ1
GFX_DPRSLPVR
GFX_VR_EN
GFX_VID6
GFX_VID5
GFX_VID4
GFX_VID3
GFX_VID2
GFX_VID1
GFX_VID0
(SYM 7 OF 11)
POWER
PEG & DMI
LINES
SENSE
GRAPHICS VIDS
GRAPHICS
DDR3 -1.5 V RAILS
OUT
OUT
OUT OUT
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER
SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
Do not connect to power supply, but provide bypass caps on PCB.
NOTE: VCAP2 is sourced by CPU
OMIT
ARRANDALE
BGA
U1000
AL71
AL69
AF71 AG67 AG70 AH71 AN71 AM67 AM70
AH69
AN32
AL30 AL28 AL26 AL24 AL23 AL21 AL19 AK14 AK12 AJ10
AN30
AH14 AH12 AF28 AF26 AF24 AF23 AF21 AF19 AF17 AF15
AN28
AF14 AD28 AD26 AD24 AD23 AD21 AD19 AD17
AN26 AN24 AN23 AN21 AN19 AL32
AF12
AK62
AB60 AB59 AA60 AA59
W60 W59 U60 U59 R60 R59
AK60 AK59 AH60 AH59 AF60 AF59 AD60 AD59
BU40
BG43 BF16 BF15 BD35 BD33 BD32 BD30 BD28 BD26 BD24
BU35
BD23 BD21 BD19 BD17 BD15 BB35 BB33 BB32 BB30 BB28
BU28
BB26 BB24 BB23 BB21 BB19 BB17 BB15
BN38 BM25 BL30 BJ38 BH32 BH28
AF10
AW32 AW30 AW28 AW26 AW24 AW23 AW21 AW19 AW17 AW15
W21
R19 R17
AD15 AD14 AD12 AB12 AA12 W17 W15 W14
W19
W12 R15
U21 U19 U17 U15 U14 U12 R21
8
91
PLACE_NEAR=U1000.AF10:25.4MM
402
1%
100
1/16W MF-LF
R1401
1
2
MF-LF
402
1/16W
4.7K
5%
R1405
1
2
69 91
69 91
69 91
PLACE_NEAR=U1000.AF12:25.4MM
100
1/16W
1%
402
MF-LF
R1400
1
2
69 91
69 91
8
91
8
91
8
91
8
91
8
91
8
91
SYNC_DATE=06/15/2009
SYNC_MASTER=K17_REF
CPU Power (2 of 2)
PPVCORE_S0_GFX
PP1V05_S0
PPVCORE_S0_CPU_VCAP2
GFX_VID<3>
GFX_VID<5> GFX_VID<6>
GFX_VID<0> GFX_VID<1>
GFX_VSENSE_N
PPVCORE_S0_GFX
GFX_VSENSE_P
GFXIMVP_IMON
GFX_VID<2>
GFX_DPRSLPVR
GFX_VR_EN
GFX_VID<4>
PP1V05_S0
PP1V1R1V05_S0_CPU_VTT0_DDR
PP1V5_S3RS0
14 OF 132
<E4LABEL>
<SCH_NUM>
<BRANCH>
13 OF 101
6 7
13 24 49 69
6 7
10 12 13 15 17 18 20 21
23 24 25 26 40 70 73 86
7
24
6 7
13 24 49 69
6 7
10 12 13 15 17 18 20 21 23
24 25 26 40 70 73 86
15
6 7
16 31 42 72 73 99
Page 14
VSS77
VSS11
VSS16
VSS110 VSS111
VSS113
VSS112
VSS114
VSS116
VSS115
VSS118
VSS117
VSS119
VSS121
VSS120
VSS122
VSS124
VSS123
VSS125 VSS126 VSS127 VSS128 VSS129
VSS131
VSS130
VSS133
VSS132
VSS134
VSS136
VSS135
VSS137 VSS138 VSS139
VSS141
VSS140
VSS142 VSS143 VSS144
VSS147
VSS145 VSS146
VSS149
VSS148
VSS150
VSS1 VSS2 VSS3
VSS5
VSS4
VSS6 VSS7 VSS8
VSS10
VSS9
VSS13
VSS12
VSS14 VSS15
VSS17 VSS18 VSS19 VSS20 VSS21
VSS23
VSS22
VSS25
VSS24
VSS26
VSS28
VSS27
VSS29 VSS30 VSS31
VSS33
VSS32
VSS34 VSS35 VSS36
VSS39
VSS37 VSS38
VSS41
VSS40
VSS43
VSS42
VSS44
VSS46
VSS45
VSS47
VSS49
VSS48
VSS51
VSS50
VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62
VSS64
VSS63
VSS66
VSS65
VSS67
VSS69
VSS68
VSS71
VSS70
VSS72 VSS73 VSS74 VSS75
VSS76
VSS80
VSS78 VSS79
VSS82
VSS81
VSS85
VSS83 VSS84
VSS87
VSS86
VSS90
VSS88 VSS89
VSS92
VSS91
VSS93
VSS95
VSS94
VSS96 VSS97 VSS98
VSS99 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106
VSS108
VSS107
VSS109
(SYM 9 OF 11)
VSS215 VSS216
VSS214
VSS213
VSS212
VSS210 VSS211
VSS207 VSS208 VSS209
VSS205 VSS206
VSS204
VSS203
VSS202
VSS200 VSS201
VSS199
VSS197 VSS198
VSS195 VSS196
VSS194
VSS192 VSS193
VSS190 VSS191
VSS189
VSS187 VSS188
VSS185
VSS184
VSS186
VSS182 VSS183
VSS181
VSS180
VSS179
VSS177 VSS178
VSS176
VSS175
VSS174
VSS172 VSS173
VSS171
VSS169 VSS170
VSS166 VSS167 VSS168
VSS164 VSS165
VSS163
VSS162
VSS161
VSS159 VSS160
VSS158
VSS156 VSS157
VSS154 VSS155
VSS153
VSS152
VSS151
VSS227
VSS226
VSS228
VSS230
VSS229
VSS231
VSS239 VSS240
VSS232 VSS233 VSS234 VSS235 VSS236
VSS238
VSS237
VSS241
VSS250 VSS251
VSS249
VSS247
VSS242 VSS243
VSS246
VSS245
VSS244
VSS248
VSS261
VSS260
VSS259
VSS253
VSS252
VSS254
VSS256
VSS255
VSS257 VSS258
VSS270 VSS271
VSS268
VSS264
VSS263
VSS262
VSS265 VSS266 VSS267
VSS269
VSS272
VSS280 VSS281
VSS273 VSS274
VSS276
VSS275
VSS277 VSS278 VSS279
VSS282
VSS292
VSS290 VSS291
VSS288
VSS284
VSS283
VSS286
VSS285
VSS287
VSS289
VSS294
VSS293
VSS296
VSS295
VSS297 VSS298 VSS299 VSS300
VSS217 VSS218
VSS220
VSS219
VSS222
VSS221
VSS223
VSS225
VSS224
(SYM 10 OF 11)
VSS358
VSS363
VSS301
VSS429
VSS428
VSS427
VSS426
VSS423
VSS425
VSS424
VSS421 VSS422
VSS420
VSS418 VSS419
VSS416 VSS417
VSS414
VSS413
VSS415
VSS411 VSS412
VSS408 VSS409 VSS410
VSS406 VSS407
VSS405
VSS403 VSS404
VSS400
VSS402
VSS401
VSS398 VSS399
VSS397
VSS396
VSS395
VSS393 VSS394
VSS392
VSS391
VSS390
VSS388 VSS389
VSS387
VSS385 VSS386
VSS383 VSS384
VSS382
VSS380 VSS381
VSS377
VSS379
VSS378
VSS375 VSS376
VSS372 VSS373 VSS374
VSS371
VSS370
VSS367
VSS369
VSS368
VSS366
VSS365
VSS364
VSS362
VSS360 VSS361
VSS357
VSS359
VSS355 VSS356
VSS352 VSS353 VSS354
VSS351
VSS350
VSS347
VSS349
VSS348
VSS345 VSS346
VSS342
VSS344
VSS343
VSS340 VSS341
VSS339
VSS337 VSS338
VSS334 VSS335 VSS336
VSS332 VSS333
VSS330 VSS331
VSS329
VSS327 VSS328
VSS326
VSS325
VSS324
VSS322 VSS323
VSS321
VSS319 VSS320
VSS318
VSS317
VSS316
VSS314 VSS315
VSS313
VSS312
VSS311
VSS309 VSS310
VSS308
VSS307
VSS306
VSS305
VSS304
VSS303
VSS302
VSS432 VSS433
VSS431
VSS430
(SYM 11 OF 11)
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8 7 5 4 2 1
OMIT
ARRANDALE
BGA
U1000
BU62
BU21
AW67 AW62 AW59 AW55 AW51 AW48 AW44 AW41 AW37 AV9
BU18
AV1 AU70 AU62 AU57 AU53 AU50 AU46 AU42 AU39 AU35
BU14
AU33 AU32 AU30 AU28 AU26 AU24 AU23 AU21 AU19 AU17
BU11
AU15 AU14 AU4 AT64 AT10 AR62 AR57 AR53 AR50 AR46
BU7
AR42 AR39 AR35 AR33 AR32 AR30 AR28 AR26 AR24 AR23
BP42
AR21
BN64
BN6 BM70 BM51
BU58
BM44 BM32 BM24 BM17 BL57 BL55 BL48 BL40 BL28 BL20
BU55
BK63 BK60 BK53 BK34 BK10 BJ64 BJ21
BJ9
BJ1 BH70
BU51
BH57 BH55 BH47 BH24 BH20 BH15 BG51 BG36 BF62 BF30
BU48
BF13
BF8 BE70 BE65
BE9
BE1 BD57 BD53 BD50 BD46
BU44
BD42 BD39 BD14 BB71 BB62 BB57 BB53 BB50 BB46 BB42
BU37
BB39
BB7
BB1 BA70 AY71 AY66
AY62 AY59 AY55 AY51
BU32
AY48 AY44 AY41 AY37 AY35 AY33 AY32 AY30 AY28 AY26
BU25
AY24 AY23 AY21 AY19 AY17 AY15 AY14 AY12 AY8 AY4
ARRANDALE
BGA
OMIT
U1000
AR19 AR17 AR15 AR14
AR4
AR1 AP70 AP64 AN62 AN55 AN51 AN48 AN44 AN41 AN37
AN5
AN4 AM64
AM8 AL62 AL55 AL51 AL48 AL44 AL41 AL37 AL35 AL33
AL1 AK70 AK64 AK55 AK51 AK48 AK44 AK41 AK37 AK32 AK30 AK28 AK26 AK24 AK23 AK21 AK19 AK17 AK15 AJ70 AH62 AH57 AH55 AH53 BV66 AH51 BV64 AH50 BT68 AH48 BR69 BL71 AH46
BL1 AH37 BR68
R14 AH35 AH44
H71 AH33
BR3
F71 AH32 AH42
E69 AH30
BN71 E68 AH28 AH41 A66 AH26 BN1 A64 AH24 AH39 E5 AH23 C68 AH21 AH19 AH17 AH15 AH4 AG64 AG9 AG6 AF69 AF62 AF1 AE70 AE64 AD62 AD57 AD53 AD50 AD46 AD42 AD4 AC67 AC64 AC10 AC5 AC1 AB70 AB62 AB57 AB53 AB50 AB46 AB42 AB39 AB37 AB35 AB33 AB32 AB30 AB28 AB26 AB24 AB23 AB21 AB19 AB17 AB15 AB14 AB9 AA66 AA64 AA62 AA57 AA53 AA50 AA46 AA42 AA39 AA37 AA35 AA33 AA32 AA30
ARRANDALE
BGA
OMIT
U1000
AA28 AA26 AA24 AA23 AA21 AA19 AA17 AA15 AA14
AA4 W69 W62 W57 W53 W50 W46 W42
W6
W1 V70 U64 U62 U57 U53 U50 U46 U42 U39
U9
U4
T1 R70 R62 R57 R53 R50 R46 R42
R5
P4 N63 N57 N53 N50 N46 N30 N21 N15 M53 M42 M36
M1 L70 L57 L48 L47 L13 K64 K53 K43 K36 K34 K32 K25 K17 K11
K6 K4 J65 J57 J48 J47 J40 J9 H53 H43 H36 H1 G70 G57 G53 G48 G47 G43 G30 G24 G20 G15 F61 F48 F47 F28 F20 F4 E37 E33 E30 E16 E12 D41 D38 D34 D31 D27 D24 D20 D17 D13 D10 D6 B65 B62 B58 B55 B51 B48 B44 A59 A55 A52 A48 A45 A40 A36 A33 A29 A26 A22 A19 A15 A12 A8 B40
SYNC_DATE=06/15/2009
SYNC_MASTER=K17_REF
CPU Grounds
15 OF 132
<E4LABEL>
<SCH_NUM>
<BRANCH>
14 OF 101
Page 15
OUT OUT OUT OUT OUT OUT OUT OUT OUT
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
BOM OPTIONS
BOM GROUP
TABLE_BOMGROUP_HEAD
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8 7 5 4 2 1
PLACEMENT_NOTE (C1625-C1634):
VTT (CPU Uncore) DECOUPLING
PLACEMENT_NOTE (C1600-C1624):
VTT0_DDR DECOUPLING
Instead call out appropriate BOM GROUP defined in tables above.
IMAX @ 900mV
22.5
40A
VID[2:0] = Reserved (111) VID[5:3] = GPU Gain Setting (See below)
NOTE: BOM Configurations should not call out CPUPOCnU/D BOMOPTIONs directly.
18
90A
70A
20A 30A
001
Intel recommends all option straps should be provided in layout
CPU Power On Configuration (POC) Straps
Equivalent Gain
45 30
15
12.857 10
PSI# = Reserved (0)
DPRSLPVR = 1 - IMVP-6.5 compliant controller
VID[6] = Reserved (0)
000
111
110
101
100
011
010
50A 60A
PLACEMENT_NOTE (C1695-C1697):
3x 1uF 0402
PLACEMENT_NOTE (C1657-C1663):
PLACEMENT_NOTE (C1664-C1687):
PLACEMENT_NOTE (C1653-C1656):
3x 330uF 6 mOhm, 4x 22uF 0805, 7x 10uF 0603, 24x 1uF 0402
Design recommendations from Calpella Small Form Factor Design Guide Rev 1.5 (doc #407364) table 2-34 and Calpella Small Form Factor Schematic Check List Rev 1.1 (doc #395914) table 3.26.
CPU Gain Setting
4x 470uF 4.5mOhm, 3x 62uF B2, 10x 22uF 0603, 25x 1uF 0402
CPU VCore HF and Bulk Decoupling
PLACEMENT_NOTE (C1635-C1648):
2
1
R1600
MF-LF
1/16W
5%
402
1K
2
1
R1602
MF-LF
1/16W
5%
402
1K
2
1
R1601
MF-LF
1/16W
5%
402
1K
2
1
R1603
MF-LF
1/16W
5%
402
1K
CPUPOC3U
2
1
R1606
MF-LF
1/16W
5%
402
1K
NO STUFF
2
1
R1607
MF-LF
1/16W
5%
402
1K
2
1
R1604
5%
402
1K
CPUPOC4U
MF-LF
1/16W
2
1
R1605
MF-LF
1/16W
5%
402
1K
CPUPOC5U
2
1
R1616
MF-LF
402
1K
5%
1/16W
2
1
R1617
1K
402
5% 1/16W MF-LF
NO STUFF
2
1
R1615
MF-LF
1/16W
5%
1K
CPUPOC5D
402
2
1
R1614
MF-LF
1/16W
CPUPOC4D
402
5%
1K
2
1
R1612
NO STUFF
5%
1K
1/16W MF-LF
402
2
1
R1613
MF-LF
1/16W
5%
402
1K
CPUPOC3D
NO STUFF
2
1
R1610
MF-LF
402
1K
1/16W
5%
2
1
R1611
MF-LF
1/16W
5%
402
1K
NO STUFF
2
1
R1608
1K
402
5% 1/16W MF-LF
NO STUFF
2
1
R1618
1K
5% 1/16W MF-LF
402
8
12 91
8
12 91
8
12 91
8
12 91
8
12 91
8
12 91
8
12 91
12 68 91
12 68 91
2
1
Place near inductors on bottom side.
20%
603
X5R-CERM
6.3V
22UF
C1635
NO STUFF
2
1
C1625
20% X5R-CERM
6.3V 603
22UF
Place near U1000 on bottom side.
NO STUFF
10%
1UF
X5R
16V 402
1
2
C1600
Place on bottom side of U1000..
2
6.3V X5R-CERM 603
22UF
20%
Place near inductors on bottom side.
1
C1636
NO STUFF
10%
1UF
X5R 402
1
2
C1607
16V
1UF
16V 402
1
2
C1606
10% X5R
10%
1UF
X5R
16V 402
1
2
C1605
X5R
16V 402
1
2
C1604
10%
1UF 1UF
X5R
16V 402
1
2
C1611
10%
X5R
16V 402
1
2
C1610
10%
1UF
1
C1609
2
16V X5R
10%
1UF
402
10%
1UF
X5R 402
1
2
C1608
16V
1UF
16V 402
1
2
C1624
10% X5R
10%
1UF
16V 402
1
C1623
2
X5R
10%
1UF
16V 402
1
2
X5R
C1622
10%
1UF
16V 402
1
2
C1621
X5R
Place on bottom side of U1000..
10%
1UF
402
1
2
X5R
16V
C1601
10%
1UF
X5R
16V
1
2
C1620
402
10% 16V
402
1
2
1UF
C1619
X5R
10%
1UF
16V 402
1
2
C1618
X5R
10%
1UF
16V 402
1
2
X5R
C1617
10%
1UF
X5R
16V
1
2
C1616
402
10%
1UF
X5R 402
1
2
C1615
16V
10%
1UF
X5R
16V 402
1
2
C1614
10%
1UF
X5R
16V 402
1
2
C1613
10%
1UF
X5R 402
1
2
C1612
16V
2
1
C1675
1UF
Place on bottom side of U1000.
10V 402
X5R
10%
2
1
C1674
Place on bottom side of U1000.
10V 402
X5R
10%
1UF
2
1
C1687
Place on bottom side of U1000.
10% X5R
1UF
402
10V
2
1
C1686
Place on bottom side of U1000.
10% X5R
1UF
402
10V
2
1
C1673
Place on bottom side of U1000.
10V 402
1UF
X5R
10%
2
1
C1685
Place on bottom side of U1000.
10% X5R
1UF
402
10V
2
1
C1672
Place on bottom side of U1000.
10V 402
1UF
X5R
10%
2
1
C1671
Place on bottom side of U1000.
10V 402
1UF
X5R
10%
2
1
C1684
Place on bottom side of U1000.
10% X5R
1UF
402
10V
2
1
C1683
Place on bottom side of U1000.
10% X5R
1UF
402
10V
2
1
C1670
Place on bottom side of U1000.
10V 402
1UF
X5R
10%
2
1
C1682
Place on bottom side of U1000.
10% X5R
1UF
402
10V
2
1
C1669
Place on bottom side of U1000.
10V 402
1UF
X5R
10%
2
1
C1681
Place on bottom side of U1000.
10% X5R
1UF
402
10V
2
1
C1668
Place on bottom side of U1000.
10V 402
1UF
X5R
10%
2
1
C1680
Place on bottom side of U1000.
10% X5R
1UF
402
10V
2
1
C1667
Place on bottom side of U1000.
10V 402
1UF
X5R
10%
2
1
C1666
Place on bottom side of U1000.
10V 402
1UF
X5R
10%
2
1
C1643
6.3V X5R-CERM 603
20%
Place near inductors on bottom side.
22UF
NO STUFF
2
1
C1679
Place on bottom side of U1000.
10% X5R
1UF
402
10V
2
1
C1678
Place on bottom side of U1000.
10% X5R
1UF
402
10V
2
1
C1665
Place on bottom side of U1000.
10V 402
1UF
X5R
10%
2
1
C1677
Place on bottom side of U1000.
10% X5R
1UF
402
10V
2
1
C1664
Place on bottom side of U1000.
10V 402
1UF
X5R
10%
2
1
C1676
Place on bottom side of U1000.
10% X5R
1UF
402
10V
2
1
C1697
Place on bottom side of U1000.
10V 402
1UF
X5R
10%
2
1
C1696
Place on bottom side of U1000.
10V 402
X5R
10%
1UF
2
1
6.3V X5R-CERM 603
20%
Place near inductors on bottom side.
22UF
C1644
2
1
C1695
Place on bottom side of U1000.
10V 402
1UF
X5R
10%
21
L1695
0603
30-OHM-5A
2
1
6.3V
22UF
603
20% X5R-CERM
C1626
NO STUFF
Place near U1000 on bottom side.
2
1
Place near U1000 on bottom side.
603
20%
22UF
X5R-CERM
6.3V
C1629
NO STUFF
2
1
C1634
Place near U1000 on bottom side.
603
20% X5R-CERM
22UF
6.3V
NO STUFF
2
1
C1641
603
Place near inductors on bottom side.
20% X5R-CERM
6.3V
22UF
NO STUFF
2
1
C1642
603
Place near inductors on bottom side.
22UF
6.3V X5R-CERM
20%
2
1
C1698
Place near U1000 on bottom side.
603
20%
22UF
X5R-CERM
6.3V
2
1
C1694
Place near U1000 on bottom side.
20%
6.3V 603
X5R-CERM
22UF
C1693
2
1
Place near U1000 on bottom side.
603
22UF
X5R-CERM
6.3V
20%
NO STUFF
2
1
Place near U1000 on bottom side.
6.3V 603
20%
C1692
22UF
X5R-CERM
NO STUFF
20%
2
1
C1691
Place near U1000 on bottom side.
X5R-CERM
6.3V
22UF
603
NO STUFF
C16A0
1
2
CASE-B2
11V ELEC
62UF
20%
11V ELEC CASE-B2
2
1
C16A1
62UF
NO STUFF
20%
C16A3
11V ELEC
62UF
20%
CASE-B2
2
1
20%
62UF
11V CASE-B2
2
1
C16A2
ELEC
2
1
11V ELEC
20%
CASE-B2
62UF
C16A4
603
20%
C1645
2
1
6.3V
22UF
Place near inductors on bottom side.
NO STUFF
X5R-CERM
2
1
C1637
6.3V X5R-CERM 603
22UF
Place near inductors on bottom side.
NO STUFF
20%
X5R-CERM
2
1
C1638
603
22UF
20%
Place near inductors on bottom side.
6.3V
1
C1627
Place near U1000 on bottom side.
20%
22UF
X5R-CERM
6.3V 603
2
Place on bottom side of U1000..
1UF
16V 402
1
2
C1602
10% X5R
2
1
Place near U1000 on bottom side.
6.3V X5R-CERM 603
22UF
20%
NO STUFF
C1628
Place on bottom side of U1000..
X5R
16V 402
1
2
C1603
10%
1UF
Place near inductors on bottom side.
2
1
6.3V X5R-CERM 603
20%
22UF
C1646
NO STUFF
2
1
C1640
6.3V 603
20%
Place near inductors on bottom side.
X5R-CERM
22UF
NO STUFF
2
1
C1630
Place near U1000 on bottom side.
603
20%
6.3V
22UF
X5R-CERM
2
1
C1631
Place near U1000 on bottom side.
20% 603
22UF
6.3V X5R-CERM
NO STUFF
2
1
C1648
6.3V X5R-CERM 603
20%
22UF
2
1
C1632
Place near U1000 on bottom side.
603
20%
6.3V
22UF
X5R-CERM
3 2
1
C1649
2.0V
20%
470UF-4MOHM
D2T-SM
POLY-TANT
3 2
1
C1650
D2T-SM
POLY-TANT
20%
2.0V
470UF-4MOHM
3 2
1
C1651
2.0V
20%
D2T-SM
POLY-TANT
470UF-4MOHM
POLY-TANT
470UF-4MOHM
3 2
1
C1652
D2T-SM
2.0V
20%
2
1
C1653
6.3V
Place on bottom side of U1000.
X5R-CERM 603
22UF
20%
2
1
C1654
Place on bottom side of U1000.
X5R-CERM 603
22UF
20%
6.3V
2
1
C1655
Place on bottom side of U1000.
X5R-CERM 603
22UF
20%
6.3V
2
1
C1656
Place on bottom side of U1000.
X5R-CERM 603
20%
6.3V
22UF
2
1
C1663
603
X5R
10UF
20%
6.3V
Place on bottom side of U1000..
2
1
C1662
603
X5R
10UF
20%
6.3V
Place on bottom side of U1000..
2
1
C1661
603
X5R
10UF
20%
6.3V
Place on bottom side of U1000..
2
1
C1660
603
X5R
10UF
20%
6.3V
Place on bottom side of U1000..
2
1
C1659
603
X5R
10UF
6.3V
20%
Place on bottom side of U1000..
2
1
C1658
X5R 603
10UF
6.3V
20%
Place on bottom side of U1000..
2
1
C1657
603
10UF
6.3V
20%
Place on bottom side of U1000..
X5R
3 2
1
C1688
POLY-TANT
2.0V
20%
D2T-SM2
330UF
3 2
1
C1689
D2T-SM2
POLY-TANT
2.0V
20%
330UF
3 2
1
330UF
D2T-SM2
POLY-TANT
2.0V
20%
C1690
SYNC_MASTER=K17_REF
CPU Non-GFX Decoupling (1 of 2)
SYNC_DATE=06/15/2009
CPUPOC_IMAX_DIS
CPUPOC3D,CPUPOC4D,CPUPOC5D
CPUPOC3U,CPUPOC4U,CPUPOC5U
CPUPOC_IMAX_70_90
CPUPOC3U,CPUPOC4D,CPUPOC5U
CPUPOC_IMAX_50_60
CPUPOC3U,CPUPOC4U,CPUPOC5D
CPUPOC_IMAX_60_70
CPUPOC_IMAX_40_50
CPUPOC3U,CPUPOC4D,CPUPOC5D
CPUPOC_IMAX_0_20
CPUPOC3D,CPUPOC4D,CPUPOC5U
CPUPOC_IMAX_30_40
CPUPOC3D,CPUPOC4U,CPUPOC5U
CPUPOC_IMAX_20_30
CPUPOC3D,CPUPOC4U,CPUPOC5D
PPVCORE_S0_CPU
PP1V05_S0
CPU_PSI_L
PM_DPRSLPVR
CPU_VID<4>
CPU_VID<3>
CPU_VID<2>
CPU_VID<1>
CPU_VID<0>
PP1V05_S0
CPU_VID<5> CPU_VID<6>
MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.1V
PP1V1R1V05_S0_CPU_VTT0_DDR
16 OF 132
<E4LABEL>
<SCH_NUM>
<BRANCH>
15 OF 101
6 7
12 49 68
6 7
10 12 13 15
17 18 20 21 23 24
25 26 40 70 73 86
6 7
10 12 13 15 17 18 20 21
23 24 25 26 40 70 73 86
13
Page 16
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER
SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
VCAP1 (CPU BSC Package) DECOUPLING
VCAP0 (CPU BSC Package) DECOUPLING
5x 1uF 0402
1x 22uF 0805, 1x 4.7uF 0603
1x 1uF 0402
PLACEMENT_NOTE (C1700-C1711):
12x 1uF 0402
12x 1uF 0402
PLACEMENT_NOTE (C1712-C1723):
NOTE: 19x 1uF 0402 caps per Apple SI for CMD and CNTRL lines.
Memory (CPU VCCDDR) DECOUPLING
PLL (CPU VCCSFR) DECOUPLING
DDR Clock (CPU VDDQ_CK) DECOUPLING
NOTE: 3x 330uF 6 mOhm caps to be shared between CPU and SO-DIMMs. DG recommends 2x 22uF at SO_DIMM not provided. Decoupling caps at SO-DIMMs on CSA 29 and CSA 31.
Design recommendations from Calpella Small Form Factor Design Guide Rev 1.5 (doc #407364) table 2-34 and Calpella Small Form F actor Schematic Check List Rev 1.1 (doc #395914) table 3.26.
10V 402
1UF
10% X5R
C1745
1
2
1UF
X5R
10%
402
10V
C1744
1
2
10V 402
1UF
10% X5R
C1743
1
2
1UF
X5R
10%
402
10V
C1742
1
2
10V 402
1UF
10% X5R
C1741
1
2
1UF
10% X5R
402
10V
C1740
1
2
X5R 402
1UF
10% 10V
C1739
1
2
1UF
X5R
10%
402
10V
C1738
1
2
10V 402
1UF
10% X5R
C1737
1
2
1UF
X5R
10%
402
10V
C1736
1
2
10V 402
1UF
10% X5R
C1735
1
2
1UF
X5R
10%
402
10V
C1753
1
2
10V 402
1UF
10% X5R
C1752
1
2
1UF
10% X5R
402
10V
C1751
1
2
X5R 402
1UF
10% 10V
C1750
1
2
1UF
X5R
10%
402
10V
C1749
1
2
402
X5R
10V
1UF
10%
C1748
1
2
1UF
X5R
10%
402
10V
C1747
1
2
402
10V
1UF
10% X5R
C1746
1
2
30-OHM-5A
0603
L1734
1 2
Place on bottom side of U1000.
10%
1UF
X5R
16V 402
1
2
C1723
Place on bottom side of U1000.
10%
1UF
X5R
16V 402
1
2
C1722
Place on bottom side of U1000.
10%
1UF
X5R
16V 402
1
2
C1721
Place on bottom side of U1000.
10% X5R
16V 402
1
2
1UF
C1720
Place on bottom side of U1000.
10%
1UF
X5R
16V 402
1
2
C1719
Place on bottom side of U1000.
10% X5R
16V 402
1
2
1UF
C1718
Place on bottom side of U1000.
10%
1UF
X5R
16V 402
1
2
C1717
Place on bottom side of U1000.
10%
1UF
X5R
16V 402
1
2
C1716
Place on bottom side of U1000.
10%
1UF
X5R
16V 402
1
2
C1715
Place on bottom side of U1000.
10%
1UF
X5R
16V 402
1
2
C1714
Place on bottom side of U1000.
10%
1UF
X5R
16V 402
1
2
C1713
Place on bottom side of U1000.
10%
1UF
X5R
16V 402
1
2
C1712
Place on bottom side of U1000.
10%
1UF
X5R
16V 402
1
2
C1711
Place on bottom side of U1000.
10%
1UF
X5R
16V 402
1
2
C1710
Place on bottom side of U1000.
10%
1UF
X5R
16V 402
1
2
C1709
Place on bottom side of U1000.
10% X5R
16V 402
1
2
1UF
C1708
Place on bottom side of U1000.
10%
1UF
X5R
16V 402
1
2
C1707
Place on bottom side of U1000.
10% X5R
16V 402
1
2
1UF
C1706
Place on bottom side of U1000.
10%
1UF
X5R
16V 402
1
2
C1705
Place on bottom side of U1000.
10%
1UF
X5R
16V 402
1
2
C1704
Place on bottom side of U1000.
10%
1UF
X5R
16V 402
1
2
C1703
Place on bottom side of U1000.
10%
1UF
X5R
16V 402
1
2
C1702
Place on bottom side of U1000.
10%
1UF
X5R
16V 402
1
2
C1701
Place on bottom side of U1000.
10%
1UF
X5R
16V 402
1
2
C1700
1UF
10V
10% X5R
402
C1728
1
2
1UF
X5R
10%
402
10V
C1727
1
2
10V 402
1UF
10% X5R
C1726
1
2
1UF
10% 10V
402
X5R
C1725
1
2
X5R
1UF
10%
402
10V
C1724
1
2
X5R-CERM 603
10%
6.3V
4.7UF
C1733
1
2
805
CERM-X5R
22uF
6.3V
20%
C1732
1
2
10V 402
10% X5R
1UF
C1734
1
2
POLY-TANT
2.0V
20%
D2T-SM2
330UF
C1729
1
23
SYNC_MASTER=K17_REF
CPU Non-GFX Decoupling (2 of 2)
SYNC_DATE=06/15/2009
PP1V5_S3RS0
PP1V8_S0
PP1V5_S3RS0
PP1V5_S3_CPU_VCCDDR_CLK
PPVCORE_S0_CPU_VCAP0
PPVCORE_S0_CPU_VCAP1
17 OF 132
<E4LABEL>
<SCH_NUM>
<BRANCH>
16 OF 101
6 7
13 16 31 42
72 73 99
6 7
12 21 23 24
58 71 72 87
6 7
13 16 31 42
72 73 99
12
7
12
7
12
Page 17
IN
IN
OUT
OUT
OUT
OUT
IN
IN
IN
IN
BI BI BI BI
OUT
BI
IN
IN OUT OUT
IN
IN OUT OUT
IN IN
IN IN
IN IN
OUT
OUT
OUT OUT
OUT OUT
OUT
IN
OUT
OUT OUT
IN
OUT OUT
IN
OUT OUT
OUT
OUT
IN
OUT
OUT
IN
IN
IN IN
IN IN
IN IN
IN
IN
IN
OUT
OUT
OUT
BI
OUT
BI
IN IN OUT OUT
FWH4/LFRAME*
SATA1GP/GPIO19
INTVRMEN
SATAICOMPI
SATAICOMPO
SATA0TXN
SATA0RXN
SATA0TXP
SATA0RXP
SATA1TXP
SATA1RXP
SATA1RXN
SATA1TXN
SATA2TXN
SATA2RXN
SATA2TXP
SATA2RXP
SATA5TXN
SATA5RXN
SATA4TXN
SATA4RXN
SATA3TXN
SATA3RXN
SATA5TXP
SATA5RXP
SATA4TXP
SATA4RXP
SATA3TXP
SATA3RXP
FWH1/LAD1
LDRQ0*
LDRQ1*/GPIO23
SERIRQ
FWH3/LAD3
FWH2/LAD2
FWH0/LAD0
SATALED*
SATA0GP/GPIO21
HDA_SYNC
SPKR
SPI_MISO
SPI_MOSI
SPI_CS1*
SPI_CS0*
SPI_CLK
JTAG_TDO
JTAG_RST*
JTAG_TDI
JTAG_TMS
JTAG_TCK
HDA_DOCK_RST*/GPIO13
HDA_DOCK_EN*/GPIO33
HDA_SDO
HDA_SDIN2 HDA_SDIN3
HDA_SDIN1
HDA_SDIN0
HDA_RST*
HDA_BCLK
INTRUDER*
SRTCRST*
RTCRST*
RTCX2
RTCX1
(1 OF 10)
RTC
LPC
IHDAJTAG
SPI
SATA
CLKOUT_DMI_N CLKOUT_DMI_P
CLKOUT_DP_N/CLKOUT_BCLK1_N CLKOUT_DP_P/CLKOUT_BCLK1_P
CLKIN_DMI_N CLKIN_DMI_P
CLKIN_BCLK_N CLKIN_BCLK_P
CLKIN_DOT_96N CLKIN_DOT_96P
CLKIN_PCILOOPBACK
XTAL25_IN
XTAL25_OUT
CLKOUT_PEG_A_P
CLKOUT_PEG_A_N
PEG_A_CLKRQ*/GPIO47
CL_RST1*
CL_DATA1
CL_CLK1
SML1DATA/GPIO75
SML1CLK/GPIO58
SML1ALERT*/GPIO74
SML0DATA
SML0CLK
SML0ALERT*/GPIO60
SMBDATA
CLKOUTFLEX1/GPIO65
CLKOUTFLEX0/GPIO64
XCLK_RCOMP
CLKOUTFLEX2/GPIO66
CLKOUTFLEX3/GPIO67
CLKOUT_PCIE0N CLKOUT_PCIE0P
CLKOUT_PCIE1N
CLKOUT_PCIE2N
PCIECLKRQ1*/GPIO18
PCIECLKRQ2*/GPIO20
CLKOUT_PCIE2P
CLKOUT_PCIE3P
CLKOUT_PCIE3N
PCIECLKRQ3*/GPIO25
CLKOUT_PCIE4N
PCIECLKRQ4*/GPIO26
CLKOUT_PCIE4P
CLKOUT_PCIE5P
CLKOUT_PCIE5N
PCIECLKRQ5*/GPIO44
CLKOUT_PEG_B_P
CLKOUT_PEG_B_N
PEG_B_CLKRQ*/GPIO56
PETP8
PETN8
PERP8
PERN8
PETP7
PETN7
PERP7
PERN7
PETP6
PERP6 PETN6
PETP5
PERN6
PERP5
PERN5
PETN5
PETP4
PETN4
PERP4
PERN4
PETP3
PETN3
PERP3
PERN3
PETP2
PERP2 PETN2
PETP1
PERN2
PERP1
PERN1
PETN1
SMBCLK
SMBALERT*/GPIO11
CLKIN_SATA_N/CKSSCD_N CLKIN_SATA_P/CKSSCD_P
REFCLK14IN
CLKOUT_PCIE1P
PCIECLKRQ0*/GPIO73
FROM CLK BUFFER
(2 OF 10)
SMBUS
C-LINKPEG
CLOCK
FLEX
PCI-E*
OUT OUT
IN
OUT
OUT
OUT
OUT
BI
OUT
OUT
OUT
IN
IN
IN IN
OUT OUT
OUT
IN
IN
OUT
OUT
IN
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER
SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
CLKOUTFLEX3 also supports 48 MHz.
Default: 24.576 MHz (unsupported)
Default: 48 MHz
Default: 0V
All 4 CLKOUTFLEX outputs support
(IPD)
port multipliers
(IPU)
Unused
(IPD)
(IPD)
(IPD)
Not available on
eSATA
SSD
ODD
HDD
(IPD)
(IPD)
(IPD)
(IPD)
(IPU)
(IPU)
(IPU)
(IPD)
(IPD)
(IPD)
(IPU)
(IPD)
Default: 14.31818 MHz
33.333 MHz and 14.31818 MHz,
Unused
(IPU/NO)
Only ports 4 & 5
(IPD)
(IPU)
(IPU)
(IPU)
some IbexPeak SKUs
(IPU)
support FIS-based
(IPU)
(IPD)
27
58 94
17 25
47 94
47 94
47 94
17 25
17 25
17 25
47 94
6
45 47 87 94
6
45 47 87 94
6
45 47 87 94
6
45 47 87 94
6
45 47 87 94
6
45 47
42 93
42 93
42 93
42 93
42 93
42 93
42 93
42 93
37 94
37 94
6
33 94
6
33 94
39 94
39 94
37 94
37 94
33 94
33 94
39 94
39 94
37 94
17 37
37 94
33 94
33 94
17 25 33
39 94
39 94
17 25 40
10 91
10 91
74 94
74 94
8
17 87
10 93
10 93
26 93
26 93
26 93
26 93
26 93
26 93
26 93
26 93
26 93
27 93
27
27
27
48 94
48 94
25 26 28 30 32 42 47 48 63 88
94
25 26 28 30 32 42 47 48 63 88 94
8
8
8
8
330K
402
MF-LF
1/16W
5%
R1800
1
2
1/16W MF-LF
1M
402
5%
R1801
1
2
5%
20K
402
1/16W MF-LF
R1802
1
2
20K
402
5% 1/16W MF-LF
R1803
1
2
X5R
10V
10%
1UF
402
C1803
1
2
10V X5R 402
1UF
10%
C1802
1
2
1%
402
MF-LF
37.4
1/16W
R1830
1
2
10K
1/16W
5% MF-LF
402
R1820
1
2
IBEX_PEAK_M
FCBGA
OMIT
U1800
D33 B33 C32 A32
C34
A30
H32 J30
C30
G30 F30 E32 F32
B29
D29
A16
A14
J4
M3
K1
J2
K3
A34 F34
C14
B13 D13
Y9
AK7 AK6 AK11 AK9
V1
AH6 AH5 AH9 AH8
AF11 AF9 AF7 AF6
AH3 AH1 AF3 AF1
AD9 AD8 AD6 AD5
AD3 AD1 AB3 AB1
AF15
AF16
T3
AB9
BA2
AV3
AY3
AV1
AY1
P1
D17
FCBGA
OMIT
IBEX_PEAK_M
U1800
T13
T11
T9
AP3 AP1
AW24 BA24
F18 E18
J42
AH13 AH12
AN4 AN2
AT1 AT3
AK48 AK47
AM43 AM45
AM47 AM48
AH42 AH41
AM51 AM53
AJ50 AJ52
AD43 AD45
AK53 AK51
T45
P43
T42
N50
P9
U4
N4
A8
M9
H6
H1
P13
BG30
AW30
AU30
BA32
BF33
BA34
AT34
BG34
BJ30
BA30
AT30
BB32
BH33
AW34
AU34
BJ34
BF29
BC30
AU32
BD32
BG32
BC34
AU36
BG36
BH29
BD30
AV32
BE32
BJ32
BD34
AV36
BJ36
P41
B9
H14 C8
J14
C6 G8
M14
E10 G12
AF38
AH51 AH53
8
94
8
94
17
MF-LF
1/16W
402
1%
90.9
R1890
1
2
MF-LF
1/16W
5%
402
33
R1810
1 2
33
402
5% 1/16W MF-LF
R1811
1 2
33
402
5% 1/16W MF-LF
R1812
1 2
402
MF-LF
1/16W
5%
33
R1813
1 2
58 94
58 94
58 94
58 94
48 94
48 94
8
8
8
8
17 45
17 37
17 25 42
17 25
17
101
6
6
6
6
17 45
1/16W
10K
MF-LF
4025%
R1853
1 2
10K
5%
1/16W
402
MF-LF
R1854
1 2
10K
MF-LF
402
1/16W
5%
R1855
1 2
402
10K
MF-LF1/16W
5%
R1852
1 2
1/16W
402
MF-LF
10K
5%
R1851
1 2
1/16W
402
MF-LF
10K
5%
R1850
1 2
10K
402
MF-LF1/16W
5%
R1880
1 2
100K
5%
1/16W
402
MF-LF
R1860
1 2
1/16W
10K
MF-LF
4025%
R1870
1 2
10K
MF-LF
402
1/16W
5%
R1871
1 2
10K
402
MF-LF1/16W
5%
R1872
1 2
MF-LF
402
10K
5%
1/16W
R1898
1 2
1/16W
5% 402
MF-LF
10K
R1897
1 2
MF-LF
5%
1/16W
402
10K
R1896
1 2
10K
MF-LF
402
1/16W
5%
R1895
1 2
5%
1/16W
402
MF-LF
10K
R1840
1 2
10K
MF-LF
402
1/16W
5%
R1841
1 2
10K
5%
1/16W
402
MF-LF
R1816
1 2
5%
1/16W
402
MF-LF
10K
R1815
1 2
1/16W
402
51
MF-LF
5%
R1828
1
2
XDP_PCH
402
1/16W MF-LF
5%
51
R1826
1
2
XDP_PCH
5% MF-LF
1/16W 402
51
R1827
1
2
402
XDP_PCH
51
MF-LF
1/16W
5%
R1825
1
2
402
MF-LF1/16W
5%
2.2K
R1899
1 2
PCH SATA/PCIE/CLK/LPC/SPI
SYNC_DATE=08/24/2009
SYNC_MASTER=K17_REF
PP3V3_S0
PCH_SPKR
TP_PCH_SATALED_L
HDA_RST_R_L
NC_SATA_SSD2_R2D_CP
NC_SATA_EXTA_R2D_C_N
PEG_CLKREQ_L
ARB_DETECT
SPI_CS0_R_L
NC_PCIE_PE5_D2RN NC_PCIE_PE5_D2RP NC_PCIE_PE5_R2D_CN
NC_PCIE_PE6_D2RN
PP1V05_S0
PCH_INTRUDER_L
SATA_ODD_D2R_N SATA_ODD_D2R_P
TP_SPI_CS1_L
SPI_MISO
HDA_SDOUT_R
HDA_RST_L
HDA_RST_R_L
HDA_SDOUT
HDA_SDOUT_R
HDA_SYNC
HDA_SYNC_R
HDA_BIT_CLK
HDA_BIT_CLK_R
NC_SATA_C_D2RN
TP_LPC_DREQ0_L
PCH_SML0ALERT_L SML_PCH_0_CLK
SML_PCH_0_DATA
PCH_SML1ALERT_L
PCIE_CLK100M_FW_P
PCIE_CLK100M_FW_N
PCIE_CLK100M_ENET_N
NC_PCIE_PE8_D2RP
NC_PCIE_PE7_R2D_CP
SMBUS_PCH_CLK SMBUS_PCH_DATA
PCH_CLK33M_PCIIN
PCH_CLK25M_XTALIN PCH_CLK25M_XTALOUT
HDA_BIT_CLK_R
NC_SATA_SSD2_D2RP
PCIE_CLK100M_AP_N
PCIE_CLK100M_ENET_P
SMC_WAKE_SCI_L
NC_PCIE_PE6_R2D_CP
NC_PCIE_PE6_D2RP
FW_CLKREQ_L
NC_PCIE_CLK100M_PE4N
NC_PCIE_EXCARD_D2R_P
NC_PCIE_CLK100M_PE5N
NC_SATA_SSD2_R2D_CN
NC_SATA_SSD2_D2RN
NC_PCIE_CLK100M_PEBP
PCH_INTVRMEN_L
NC_PCIE_CLK100M_EXCARD_P
NC_PCIE_PE8_D2RN
BRCRYPT_RESET
MLB_RAM_VENDOR
PCH_CLK100M_SATA_P
PCH_CLK14P3M_REFCLK
MLB_RAM_SIZE
PP1V05_S0
PCH_CLK96M_DOT_P
NC_CLINK_RESET_L
NC_CLINK_DATA
NC_CLINK_CLK
PCH_CLK100M_SATA_N
NC_PCIE_EXCARD_R2D_C_P
NC_PCIE_PE6_R2D_CN
NC_PCIE_PE7_D2RN NC_PCIE_PE7_D2RP NC_PCIE_PE7_R2D_CN
NC_PCIE_PE8_R2D_CP
NC_PCIE_CLK100M_PE4P
NC_PCIE_CLK100M_EXCARD_N
LPC_SERIRQ
SATA_HDD_R2D_C_P
SML_PCH_1_CLK SML_PCH_1_DATA
NC_SATA_EXTA_D2R_N
NC_SATA_D_R2D_CN
PCH_PEB_CLKREQ_L
ENET_CLKREQ_L
PCIE_CLK100M_AP_P
PCH_PE4_CLKREQ_L
NC_PCIE_CLK100M_PEBN
PCH_INTVRMEN_L
NC_HDA_SDIN1 NC_HDA_SDIN2
PCH_CLK32K_RTCX2
PCH_CLK32K_RTCX1
SPI_DESCRIPTOR_OVERRIDE_L ENET_ENERGY_DET
JTAG_PCH_TCK JTAG_PCH_TMS
SATARDRVR_A_EN
PCH_SPKR
HDA_SYNC_R
SATA_ODD_R2D_C_N
NC_SATA_D_R2D_CP
NC_SATA_EXTA_D2R_P
PCH_INTRUDER_L
NC_HDA_SDIN3
LPC_AD<2> LPC_AD<3>
LPC_FRAME_L
SATA_HDD_R2D_C_N
SATA_ODD_R2D_C_P
NC_SATA_C_R2D_CN
NC_SATA_D_D2RN
NC_SATA_EXTA_R2D_C_P
GFX_CLK120M_DPLLSS_P
PCH_CLK96M_DOT_N
GFX_CLK120M_DPLLSS_N
PCIE_CLK100M_CPU_P
FSB_CLK133M_PCH_P
FSB_CLK133M_PCH_N
PCIE_CLK100M_PCH_P
PCIE_CLK100M_PCH_N
PCIE_CLK100M_CPU_N
PEG_CLK100M_P
PEG_CLK100M_N
PEG_CLKREQ_L
NC_SATA_C_D2RP
SATARDRVR_B_EN
SATARDRVR_A_EN
AP_CLKREQ_L
PCH_SML1ALERT_L
MLB_RAM_VENDOR
JTAG_PCH_TDO JTAG_PCH_TCK
JTAG_PCH_TMS
PCH_SRTCRST_L
SATARDRVR_B_EN
AP_CLKREQ_L
BRCRYPT_PWR_EN
NC_PCIE_CLK100M_PE5P
EXCARD_CLKREQ_L
BRCRYPT_RESET
SMC_WAKE_SCI_L
EXCARD_CLKREQ_L
FW_CLKREQ_L
ENET_CLKREQ_L
NC_PCIE_PE5_R2D_CP
PCH_SATAICOMP
NC_SATA_C_R2D_CP
NC_SATA_D_D2RP
TP_LPC_DREQ1_L
PP3V3_S0
LPC_AD<0> LPC_AD<1>
PCIE_FW_R2D_C_P
PCIE_FW_R2D_C_N
NC_PCIE_EXCARD_R2D_C_N
NC_PCIE_EXCARD_D2R_N
PCIE_FW_D2R_P
JTAG_PCH_TDI
NC_PCIE_PE8_R2D_CN
PCH_XCLK_RCOMP
ARB_DETECT
PCH_SML0ALERT_L
BRCRYPT_PWR_EN
PCH_PEB_CLKREQ_L
PCH_PE4_CLKREQ_L
RTC_RESET_L
ENET_ENERGY_DET
SATA_HDD_D2R_P
SATA_HDD_D2R_N
PCIE_FW_D2R_N
PCIE_AP_R2D_C_P
PCIE_AP_R2D_C_N
PCIE_AP_D2R_P
PCIE_AP_D2R_N
PCIE_ENET_R2D_C_P
PCIE_ENET_R2D_C_N
PCIE_ENET_D2R_P
PCIE_ENET_D2R_N
RTC_RESET_L
HDA_SDIN0
PCH_SRTCRST_L
MLB_RAM_SIZE
PP3V42_G3H
SPI_DESCRIPTOR_OVERRIDE_L
PP3V3_S5
JTAG_PCH_TDI JTAG_PCH_TDO TP_JTAG_PCH_TRST_L
PP3V3_S3
SPI_MOSI_R
SPI_CLK_R
PP1V05_S5
18 OF 132
<E4LABEL>
<SCH_NUM>
<BRANCH>
17 OF 101
6 7
17 18 19 20 21 23 24 25 26
27 28 30 34 37 40 42 46 47 48
50 51 52 54 58 62 63 68 69 72
73 80 83 84 85 87 88 99
17
17 94
8
17 87
17
6
6
6
6
6 7
10 12 13 15 17 18 20 21
23 24 25 26 40 70 73 86
17
17 94
17 94
17 94
17 94
17 94
6
17
17
6
6
17 94
6
6
6
6
6
17
6
17
101
17
17
6 7
10 12 13 15 17 18 20 21
23 24 25 26 40 70 73 86
6
6
6
6
6
6
6
6
6
6
17
17
6
17
6
6
17
17 94
6
17
6 6
6
6
17 25
17 25 42
17 25 33
17
17
17 25
17 25
17 25
17
6
17
101
17 45
17
17 25 40
17 37
6
93
6
6
6 7
17 18 19 20 21 23 24 25
26 27 28 30 34 37 40 42 46 47
48 50
51 52 54 58 62 63 68 69 72 73 80 83 84 85 87 88 99
17 25
6
17
17
17
101
17
17
17
17 37
17
17
17
6 7
21 23 43 45
46 47 48 49 53 64
65 66 73
17 45
6 7
18 19 20 21 23 27 31 35 57
66 71 72 73 83 85 99 6 7 8
20 31 32 33 34 35 36 48 50 53 54 55
72 73 87
101
6 7
71
Page 18
IN IN
IN
OUT
OUT OUT
OUT OUT
IN IN
IN IN
IN IN
IN IN
IN IN
IN IN
IN IN
OUT OUT
OUT OUT
OUT OUT OUT OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT OUT
OUT
OUT BI
BI BI
IN
OUT OUT
OUT
BI
OUT OUT
OUT OUT
OUT
OUT
IN
BI
OUT
OUT
OUT
OUT
BI
OUT
OUT
IN
IN
IN
IN
IN
IN
FDI_RXN0
DMI3RXN
RI*
BATLOW*/GPIO72
ACPRESENT/GPIO31
PWRBTN*
SUS_PWR_ACK/GPIO30
RSMRST*
LAN_RST*
DRAMPWROK
MEPWROK
PWROK
SYS_PWROK
SYS_RESET*
SLP_M*
SLP_S4*
SLP_S3*
SUSCLK/GPIO62
SLP_S5*/GPIO63
CLKRUN*/GPIO32
SUS_STAT*/GPIO61
WAKE*
DMI_ZCOMP DMI_IRCOMP
FDI_FSYNC1
FDI_FSYNC0
FDI_LSYNC0 FDI_LSYNC1
DMI3TXP
DMI2TXP
DMI0TXP DMI1TXP
DMI3TXN
DMI2TXN
DMI1TXN
DMI0TXN
DMI3RXP
DMI2RXP
DMI0RXP DMI1RXP
FDI_INT
FDI_RXP7
FDI_RXP6
FDI_RXP5
FDI_RXP4
FDI_RXP1 FDI_RXP2 FDI_RXP3
FDI_RXP0
FDI_RXN7
FDI_RXN6
FDI_RXN5
FDI_RXN4
FDI_RXN3
FDI_RXN2
FDI_RXN1
DMI2RXN
DMI1RXN
DMI0RXN
SLP_LAN*
PMSYNCH
TP23
(3 OF 10)
DMI
FDI
SYSTEM POWER
MANAGEMENT
IN
OUT
OUT
IN
IN
OUT
OUT
IN
IN
OUT
OUT
IN
IN
OUT
OUT
CRT_IRTN
DAC_IREF
CRT_VSYNC
CRT_HSYNC
CRT_DDC_CLK CRT_DDC_DATA
CRT_RED
CRT_GREEN
CRT_BLUE
DDPD_3N DDPD_3P
DDPD_2P
DDPD_2N
DDPD_1P
DDPD_1N
DDPD_0N DDPD_0P
DDPD_HPD
DDPD_CTRLDATA
DDPD_CTRLCLK
DDPC_3P
DDPC_2P DDPC_3N
DDPC_2N
DDPC_1P
DDPC_1N
DDPC_0N DDPC_0P
DDPC_HPD
DDPC_CTRLDATA
DDPC_CTRLCLK
DDPB_3N
DDPB_2P
DDPB_3P
DDPB_2N
DDPB_1P
DDPB_0P DDPB_1N
DDPB_0N
DDPB_HPD
SDVO_CTRLDATA
SDVO_CTRLCLK
LVDSB_DATA3
LVDSB_DATA2
LVDSB_DATA1
LVDSB_DATA0
LVDSB_DATA3*
LVDSB_DATA2*
LVDSB_CLK
LVDSB_CLK*
LVDSA_DATA3
LVDSA_DATA1 LVDSA_DATA2
LVDSA_DATA3*
LVDSA_DATA1*
LVDSA_DATA0*
LVDSA_CLK
LVDSA_CLK*
LVD_VREFH
LVD_IBG LVD_VBG
L_CTRL_DATA
L_CTRL_CLK
L_DDC_DATA
L_DDC_CLK
L_BKLTCTL
L_BKLTEN L_VDD_EN
LVD_VREFL
SDVO_TVCLKINN SDVO_TVCLKINP
SDVO_STALLN SDVO_STALLP
SDVO_INTN SDVO_INTP
DDPB_AUXP
DDPB_AUXN
DDPC_AUXN DDPC_AUXP
DDPD_AUXN DDPD_AUXP
LVDSB_DATA1*
LVDSB_DATA0*
LVDSA_DATA0
LVDSA_DATA2*
DIGITAL DISPLAY INTERFACE
CRT
LVDS
(4 OF 10)
OUT
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER
SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
(IPU)
(IPD)
(IPD)
(IPU)
(IPD)
(IPD)
(IPU)
(IPD)
0.5% recommended, Intel okay with 5% when CRTDAC not used.
9
91
9
91
9
91
9
91
9
91
9
91
9
91
9
91
9
91
9
91
9
91
9
91
9
91
9
91
9
91
9
91
9
91
9
91
9
91
9
91
9
91
9
91
87 93
87 93
6 8
93
6 8
93
87 93
87 93
87 93
8
93
87 93
87 93
87 93
8
93
87 93
87 93
87 93
8
93
87 93
87 93
87 93
8
93
8
87
8
87
6 8
84
84
2.37K
1%
402
MF-LF
1/16W
R1950
1
2
8
84 93
8
84 93
8
84
8
8
8
80 84
8
80 84
8
8
8
8
8
8
5% 1/16W MF-LF 402
1K
R1951
1
2
49.9
MF-LF
1/16W
1%
402
R1900
1
2
6
18 27 33
6
18 45 47
46 94
45 46
31 43 45 46 72 73
6
31 45 73 85
10 91
18
10 31 91
18 45
25 45
45 46 73
18 45
27
6
27 45
OMIT
FCBGA
IBEX_PEAK_M
U1800
P7
A6
Y1
BC24
BD24
BE22
BD22
BJ22
BG22
BF21
BH21
AW20
BA20
BD20
BC20
BJ20
BG20
BE18
BD18
BF25
BH25
D9
BF13 BH13
BJ14
BJ12 BG14
BA18 BH17 BD16 BJ16 BA16 BE14 BA14 BC12
BB18 BF17 BC16 BG16 AW16 BD14 BB14 BD12
A10
K5
BJ10
P5
B17
F14
C16
F6
K8
P12
H7
E4
M1
P8
F3
M6
T6
N2
J12
9
91
9
91
9
91
9
91
9
91
9
91
9
91
9
91
9
91
9
91
9
91
9
91
9
91
9
91
9
91
OMIT
IBEX_PEAK_M
FCBGA
U1800
AA52
V51 V53
AB53
Y53
AB51
AD53
Y51
AD48
BD42 BC42 BJ42 BG42 BB40 BA40 AW38 BA38
BG44 BJ44 AU38
BE40 BD40 BF41 BH41 BD38 BC38 BB36 BA36
BE44 BD44
Y49 AB49
AV40
BJ40 BG40 BJ38 BG38 BF37 BH37 BE36 BD36
BC46 BD46
U50 U52
AT38
Y48
T48
AB46
V48
AB48
Y45
T47
AP39 AP41
AT43 AT42
AV51
AV53
BB48
BB47
BA50
BA52
AY49
AY48
AV48
AV47
AP47
AP48
AY51
AY53
AT48
AT49
AU50
AU52
AT51
AT53
T51 T53
BF45 BH45
BJ48 BG48
BJ46 BG46
6
18 45 47
MF-LF
402
10K
1%
1/16W
R1905
1
2
5%
MF-LF
1/16W
402
10K
R1920
1
2
10K
402
1/16W MF-LF
5%
R1921
1
2
5%
MF-LF
1/16W
402
10K
R1930
1
2
10K
402
1/16W MF-LF
5%
R1931
1
2
5%
MF-LF
1/16W
402
10K
R1925
1
2
5% MF-LF
1/16W 402
10K
R1906
1
2
SYNC_DATE=06/15/2009
SYNC_MASTER=K17_REF
PCH DMI/FDI/Graphics
PCH_DAC_IREF
NC_LVDS_IG_B_DATAP<3>
LVDS_IG_B_DATA_P<2>
FDI_DATA_P<3>
FDI_DATA_N<7>
FDI_FSYNC<0> FDI_FSYNC<1>
NC_SDVO_TVCLKINN
LVDS_IG_A_DATA_P<1>
FDI_LSYNC<1>
PM_SYNC
NC_DP_IG_C_AUXN
NC_DP_IG_C_CTRL_DATA
NC_DP_IG_C_CTRL_CLK
DP_IG_B_ML_P<3>
DP_IG_B_ML_N<3>
NC_LVDS_IG_B_DATAN<3>
PM_SLP_S3_L
PP3V3_S5 PP1V05_S0
DP_IG_B_ML_N<1>
NC_DP_IG_C_MLP<2>
NC_SDVO_STALLN NC_SDVO_STALLP
NC_CRT_IG_HSYNC
NC_CRT_IG_DDC_DATA
NC_CRT_IG_DDC_CLK
NC_CRT_IG_GREEN
NC_CRT_IG_BLUE
LVDS_IG_B_DATA_P<1>
LVDS_IG_B_DATA_P<0>
LVDS_IG_B_DATA_N<1> LVDS_IG_B_DATA_N<2>
LVDS_IG_B_DATA_N<0>
NC_LVDS_IG_A_DATAP<3>
TP_LVDS_IG_B_CLKN
LVDS_IG_A_DATA_N<2>
LVDS_IG_A_DATA_N<0>
LVDS_IG_A_CLK_P
LVDS_IG_A_CLK_N
NC_DP_IG_D_AUXP
NC_DP_IG_D_AUXN
NC_DP_IG_C_AUXP
DP_IG_AUX_CH_N DP_IG_AUX_CH_P
NC_SDVO_INTP
NC_SDVO_INTN
LVDS_IG_PANEL_PWR
LVDS_IG_DDC_DATA NC_LVDS_IG_CTRL_CLK
NC_LVDS_IG_CTRL_DATA
NC_PCH_LVDS_VBG
DP_IG_DDC_CLK DP_IG_DDC_DATA
DP_IG_HPD DP_IG_B_ML_N<0>
DP_IG_B_ML_P<0>
DP_IG_B_ML_P<2>
NC_DP_IG_C_MLP<0>
NC_DP_IG_C_MLN<0>
NC_DP_IG_C_MLN<1> NC_DP_IG_C_MLP<1> NC_DP_IG_C_MLN<2>
NC_DP_IG_D_CTRL_CLK NC_DP_IG_D_CTRL_DATA
NC_DP_IG_D_HPD
NC_DP_IG_D_MLN<1>
NC_DP_IG_D_MLN<2> NC_DP_IG_D_MLP<2>
NC_DP_IG_D_MLP<3>
NC_DP_IG_D_MLN<3>
TP_PM_SLP_DSW_L
FDI_DATA_N<1>
FDI_DATA_N<4>
FDI_DATA_N<6>
FDI_DATA_P<5>
FDI_DATA_P<7>
FDI_INT
TP_PM_SLP_M_L
FDI_DATA_N<0>
NC_CRT_IG_VSYNC
LPC_PWRDWN_L
MAKE_BASE=TRUE
LPC_PWRDWN_L
PCH_LVDS_IBG
PM_BATLOW_L
SMC_ADAPTER_EN
PM_SUS_PWR_ACK PM_PWRBTN_L
PM_RSMRST_L
PM_MEM_PWRGD
PM_SYSRST_L
DMI_S2N_P<3>
DMI_S2N_P<2>
DMI_S2N_N<3>
DMI_S2N_N<2>
DMI_S2N_N<0>
DMI_N2S_P<2>
DMI_N2S_P<1>
DMI_N2S_N<3>
DMI_N2S_N<2>
DMI_N2S_N<0> DMI_N2S_N<1>
TP_SLP_LAN_L
FDI_LSYNC<0>
PM_CLKRUN_L
PCIE_WAKE_L
FDI_DATA_P<2>
FDI_DATA_P<0>
DMI_N2S_P<0>
DMI_N2S_P<3>
FDI_DATA_N<5>
FDI_DATA_P<4>
FDI_DATA_P<6>
PM_CLK32K_SUSCLK
PM_SLP_S4_L
PM_SLP_S5_L
NC_CRT_IG_RED
PM_CLKRUN_L
PM_SUS_PWR_ACK
PP3V3_S0
PM_BATLOW_L PCIE_WAKE_L
PP3V3_S5
PM_RSMRST_L
PM_PCH_PWRGD
PCH_LAN_RST_L
NC_DP_IG_D_MLP<1>
DMI_S2N_P<1>
DMI_S2N_N<1>
LVDS_IG_DDC_CLK
PCH_RI_L
TP_LVDS_IG_BKL_PWM
NC_SDVO_TVCLKINP
NC_DP_IG_D_MLN<0> NC_DP_IG_D_MLP<0>
DP_IG_B_ML_P<1>
LVDS_IG_A_DATA_P<0>
NC_LVDS_IG_A_DATAN<3>
FDI_DATA_P<1>
FDI_DATA_N<3>
FDI_DATA_N<2>
NC_DP_IG_C_MLP<3>
NC_DP_IG_C_MLN<3>
TP_LVDS_IG_B_CLKP
NC_DP_IG_C_HPD
LVDS_IG_A_DATA_N<1>
LVDS_IG_BKL_ON
DP_IG_B_ML_N<2>
LVDS_IG_A_DATA_P<2>
DMI_S2N_P<0>
PCH_DMI_COMP
19 OF 132
<E4LABEL>
<SCH_NUM>
<BRANCH>
18 OF 101
6
6
6
6
6 7
17 18 19 20 21 23 27 31 35
57 66 71 72 73 83 85 99 6 7
10 12 13 15 17 20 21 23 24
25 26 40 70 73 86
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
18 45 47
6
6
18 45 47
18
6 7
17 19 20 21 23 24 25 26
27 28 30 34 37 40 42 46 47 48
50 51 52 54 58 62 63 68 69 72
73 80 83 84 85 87 88 99
18 45
6
18 27 33
6 7
17 18 19 20 21 23 27 31
35 57 66 71 72 73 83 85 99
18 45
6
6
6
6
6
6
6
Page 19
BI
BI
BI
BI
OUT OUT
OUT
IN
OC7*/GPIO14
OC6*/GPIO10
OC5*/GPIO9
OC4*/GPIO43
OC3*/GPIO42
OC1*/GPIO40
OC0*/GPIO59
USBRBIAS
USBRBIAS*
USBP13N
USBP12N
USBP11N
USBP10N
USBP9N
USBP8N
USBP7N
USBP6N
USBP5N
USBP4N
USBP3N
USBP2N
USBP1N
USBP0N
USBP13P
USBP12P
USBP11P
USBP10P
USBP8P
USBP9P
USBP7P
USBP6P
USBP5P
USBP4P
USBP3P
USBP2P
USBP1P
USBP0P
AD2
NV_WE_CK1*
NV_WE_CK0*
NV_WR1_RE*
NV_RB*
NV_WR0_RE*
NV_RCOMP
NV_CLE
NV_ALE
NV_DQ15/NV_IO15
NV_DQ13/NV_IO13 NV_DQ14/NV_IO14
NV_DQ10/NV_IO10 NV_DQ11/NV_IO11 NV_DQ12/NV_IO12
NV_DQ8/NV_IO8 NV_DQ9/NV_IO9
NV_DQ7/NV_IO7
NV_DQ6/NV_IO6
NV_DQ5/NV_IO5
NV_DQ3/NV_IO3 NV_DQ4/NV_IO4
NV_DQ1/NV_IO1 NV_DQ2/NV_IO2
NV_DQ0/NV_IO0
NV_DQS0 NV_DQS1
NV_CE2* NV_CE3*
NV_CE1*
NV_CE0*
AD9
AD3
AD20
AD28 AD29
SERR* PERR*
GNT1*/GPIO51
REQ1*/GPIO50
PIRQC* PIRQD*
REQ0*
AD30
AD21 AD22
PIRQG*/GPIO4 PIRQH*/GPIO5
PCIRST*
AD0 AD1
AD4 AD5 AD6 AD7 AD8
AD10 AD11 AD12 AD13 AD14
AD24 AD25 AD26
CLKOUT_PCI2
C/BE0*
C/BE2* C/BE3*
DEVSEL* FRAME*
GNT0*
GNT2*/GPIO53 GNT3*/GPIO55
IRDY* PAR
PIRQA* PIRQB*
PIRQE*/GPIO2 PIRQF*/GPIO3
PLOCK*
PME*
REQ2*/GPIO52 REQ3*/GPIO54
STOP* TRDY*
AD15 AD16 AD17 AD18 AD19
AD27
AD31
C/BE1*
AD23
OC2*/GPIO41
PLTRST*
CLKOUT_PCI1
CLKOUT_PCI3
CLKOUT_PCI0
CLKOUT_PCI4
(5 OF 10)
USB
PCI
NVRAM
OUT
OUT OUT
IN IN IN
IN
BI BI
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER
SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
External Hub 2
External Hub 1
T57
(IPU)
NOTE: Internal pull-downs on all USB pins
EHCI1
(DPD)
(IPU)
(IPU)
(DPD)
EHCI2
(IPD)
(IPD)
36 93
36 93
35 93
35 93
10K
5%
MF-LF
1/16W
402
R2060
1
2
10K
5%
MF-LF
1/16W
402
R2062
1
2
5% 1/16W
402
10K
MF-LF
R2061
1
2
10K
402
1/16W MF-LF
5%
R2064
1
2
1%
22.6
402
1/16W MF-LF
R2070
1
2
27 94
27
27 31 40
19 25
4025%
1/16W MF-LF
10K
R2024
1 2
402
MF-LF1/16W
5%
10K
R2023
1 2
5%
402
1/16W MF-LF
10K
R2022
1 2
1/16W
402
MF-LF
5%
10K
R2020
1 2
1/16W
402
MF-LF
5%
10K
R2021
1 2
MF-LF1/16W
5% 402
10K
R2027
1 2
5%
10K
MF-LF1/16W
402
R2026
1 2
5%
1/16W MF-LF
402
10K
R2010
1 2
5%
1/16W MF-LF
402
10K
R2011
1 2
5%
MF-LF1/16W
10K
402
R2012
1 2
402
1/16W5%MF-LF
10K
R2013
1 2
5%
1/16W MF-LF
402
10K
R2014
1 2
FCBGA
OMIT
IBEX_PEAK_M
U1800
H40 N34
E40 C40 M48 M45 F53 M40 M43 J36 K48 F40
C44
C42 K46 M51 J52 K51 L34 F42 J40 G46 F44
A38
M47 H36
C36 J34 A40 D45 E36 H48
J50 G42 H47 G34
N52 P53 P46 P51 P48
F46 C46
F48 K45 F36 H53
A42
BD3
AY9 BD1 AP15 BD8
AY6
AP7
BD6 BB7 BC8 BJ8 BJ6 BG6
AP6 AT6 AT9 BB1 AV6 BB3 BA4 BE4 BB6
AV9 BG8
AV7
AU2
AV11 BF5
AY8 AY5
N16 J16 F16 L16 E14 G16 F12 T15
H44
K6
E50
G38 H51 B37 A44
B41 K53 A36 A48
D49
D5
M7
F51 A46 B45 M53
E44
D41 C48
H18 J18
A22 C22 G24 H24 L24 M24 A24 C24
A18 C18 N20 P20 J20 L20 F20 G20 A20 C20 M22 N22 B21 D21 H22 J22 E22 F22
D25
B25
27
10K
402
1/16W MF-LF
5%
R2066
1
2
10K
5%
MF-LF
1/16W
402
R2065
1
2
402
1/16W MF-LF
10K
5%
R2025
1 2
19 87
19 87
5%
1/16W
402
MF-LF
10K
R2030
1 2
5%
1/16W
402
MF-LF
10K
R2031
1 2
5%
1/16W
402
MF-LF
10K
R2032
1 2
5%
1/16W MF-LF
10K
402
R2036
1 2
5%
1/16W
402
MF-LF
10K
R2035
1 2
10K
MF-LF
402
1/16W
5%
R2037
1 2
19 63
19
19 63
5%
1/16W
402
MF-LF
10K
R2038
1 2
10K
MF-LF
402
1/16W
5%
R2081
1 2
5%
1/16W
402
MF-LF
10K
R2080
1 2
19 25
93
101
93
101
SYNC_MASTER=K18_MLB
PCH PCI/FlashCache/USB
SYNC_DATE=10/07/2009
JTAG_GMUX_TDI
NC_PCI_AD<3>
NC_PCH_NV_RCOMP
PCH_GPIO10
PCH_GPIO9
PCH_GPIO43
PCH_GPIO42
USB_HUB_SOFT_RESET_L PCH_GPIO41
PCH_GPIO59
NC_USB_12N
NC_USB_9N
NC_NV_DQ<10> NC_NV_DQ<11> NC_NV_DQ<12> NC_NV_DQ<13> NC_NV_DQ<14>
NC_NV_DQ<7> NC_NV_DQ<8>
NC_NV_DQ<15>
NC_USB_7P
NC_NV_DQ<5>
NC_NV_DQ<9>
USB_HUB2_UP_P
USB_HUB2_UP_N
NC_PCI_PME_L
PCI_REQ3_L
JTAG_GMUX_TDI
NC_PCI_GNT3_L
PCI_DEVSEL_L PCI_FRAME_L
MIKEY_MIC_LOAD_DET
PCI_PERR_L
PCI_STOP_L
LPC_CLK33M_LPCPLUS_R
PCI_TRDY_L
NC_PCI_AD<2>
NC_NV_WE_CK_L<0>
NC_NV_CLE
NC_NV_ALE
NC_NV_DQ<6>
NC_NV_DQ<3> NC_NV_DQ<4>
NC_NV_DQ<1> NC_NV_DQ<2>
NC_NV_DQ<0>
NC_NV_DQS<0> NC_NV_DQS<1>
NC_NV_CE_L<2> NC_NV_CE_L<3>
NC_NV_CE_L<1>
NC_NV_CE_L<0>
NC_PCI_AD<9>
NC_PCI_AD<28>
NC_PCI_AD<21> NC_PCI_AD<22>
NC_PCI_RESET_L
NC_PCI_AD<0> NC_PCI_AD<1>
NC_PCI_AD<4> NC_PCI_AD<5> NC_PCI_AD<6> NC_PCI_AD<7> NC_PCI_AD<8>
NC_PCI_AD<10> NC_PCI_AD<11>
NC_PCI_AD<13> NC_PCI_AD<14>
NC_PCI_AD<24> NC_PCI_AD<25> NC_PCI_AD<26>
LPC_CLK33M_GMUX_R
NC_PCI_C_BE_L<2> NC_PCI_C_BE_L<3>
NC_PCI_GNT0_L
NC_PCI_GNT2_L
NC_PCI_PAR
PCH_GPIO2
NC_PCI_AD<15> NC_PCI_AD<16>
NC_PCI_AD<18> NC_PCI_AD<19>
NC_PCI_AD<31>
NC_PCI_C_BE_L<1>
NC_PCI_AD<23>
NC_PCI_CLK33M_OUT3
PM_LATRIGGER_L
JTAG_GMUX_TMS
AUD_I2C_INT_L
AUD_IP_PERIPHERAL_DET MIKEY_MIC_LOAD_DET
PCI_INTB_L
PCI_INTA_L
PCI_REQ0_L
PCI_INTD_L
PCI_SERR_L
PCI_IRDY_L
PLT_RESET_L LPC_CLK33M_SMC_R
PCH_CLK33M_PCIOUT
PCI_PLOCK_L
PM_LATRIGGER_L
PCH_GPIO59
PP3V3_S5
NC_PCI_AD<12>
AUD_I2C_INT_L
JTAG_GMUX_TMS
PCH_GPIO2
PCI_REQ3_L
AUD_IP_PERIPHERAL_DET
NC_PCI_GNT1_L
NC_PCI_C_BE_L<0>
NC_PCI_AD<29> NC_PCI_AD<30>
NC_PCI_AD<20>
NC_PCI_AD<17>
PP3V3_S5
USB_BRCRYPT_N USB_BRCRYPT_P
NC_USB_6P
NC_USB_10P
NC_USB_12P
NC_USB_10N
NC_USB_6N
NC_USB_4N
NC_USB_3N
NC_USB_7N
PCH_USB_RBIAS
NC_USB_13N
NC_USB_5P
NC_USB_5N
NC_USB_4P
NC_USB_3P
NC_USB_1P
NC_USB_13P
NC_USB_11N
NC_PCI_AD<27>
NC_USB_9P
NC_USB_11P
PP3V3_S0
PCI_INTC_L
NC_NV_WE_CK_L<1>
NC_NV_RB_L
NC_USB_1N
USB_HUB1_UP_P
USB_HUB1_UP_N
NC_NV_WR_RE_L<1>
NC_NV_WR_RE_L<0>
20 OF 132
<E4LABEL>
<SCH_NUM>
<BRANCH>
19 OF 101
19 87
6
6
25 46
25
25
25
25 35
25
6
6
6
6
6
6
6
6
6
6
6
19
6
19
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
27
6
6
6
6
6
19
6
6
6
6
6
6
6
6
19 25
19 25
6 7
17 18 19 20 21 23 27 31
35 57 66 71 72 73 83 85 99
6
19 63
19 87
19
19
19 63
6
6
6
6
6
6
6 7
17 18 19 20 21 23 27
31 35 57 66 71 72 73 83
85 99
93
6
6 7
17 18 20 21 23 24 25 26
27 28 30 34 37 40 42 46 47 48
50 51 52 54 58 62 63 68 69 72
73 80 83 84 85 87 88 99
6
6
6
6
Page 20
IN
OUT OUT
BI
OUT
IN
OUT
NC_5
NC_3 NC_4
NC_1 NC_2
TP8
TP19
TP18
TP17
TP15
TP16
TP14
TP13
TP12
TP11
TP9
TP10
TP6
TP7
TP4
TP5
TP2
TP1
INIT3_3V*
TP24
VSS_NCTF31
VSS_NCTF30
VSS_NCTF28 VSS_NCTF29
VSS_NCTF25 VSS_NCTF26 VSS_NCTF27
VSS_NCTF24
VSS_NCTF23
VSS_NCTF22
VSS_NCTF21
VSS_NCTF20
VSS_NCTF19
VSS_NCTF18
VSS_NCTF17
VSS_NCTF16
VSS_NCTF15
VSS_NCTF14
VSS_NCTF13
VSS_NCTF12
VSS_NCTF10 VSS_NCTF11
VSS_NCTF8 VSS_NCTF9
VSS_NCTF7
VSS_NCTF6
VSS_NCTF5
VSS_NCTF2 VSS_NCTF3 VSS_NCTF4
VSS_NCTF1
GPIO57
SATA5GP/GPIO49
SDATAOUT1/GPIO48
PCIECLKRQ7*/GPIO46
SDATAOUT0/GPIO39
PCIECLKRQ6*/GPIO45
SLOAD/GPIO38
SATA3GP/GPIO37
SATA2GP/GPIO36
SATACLKREQ*/GPIO35
STP_PCI*/GPIO34
GPIO27
GPIO28
MEM_LED/GPIO24
TACH0/GPIO17
SCLOCK/GPIO22
SATA4GP/GPIO16
GPIO15
LAN_PHY_PWR_CTRL/GPIO12
GPIO8
TACH3/GPIO7
TACH1/GPIO1
TACH2/GPIO6
BMBUSY*/GPIO0
THRMTRIP*
PROCPWRGD
RCIN*
PECI
CLKOUT_BCLK0_P/CLKOUT_PCIE8P
CLKOUT_BCLK0_N/CLKOUT_PCIE8N
A20GATE
CLKOUT_PCIE7N
CLKOUT_PCIE6P
CLKOUT_PCIE6N
TP3
CLKOUT_PCIE7P
(6 OF 10)
CPU
NCTF
RSVD
GPIO
MISC
IN
IN
IN
BI
OUT
OUT
BI
OUT
OUT
OUT
OUT
OUT
IN
OUT
OUT
OUT
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER
SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
(IPD)
(IPU*)
(IPU*)
IPU* = Only on TACH function.
(IPU)
(XCKPLL_MON1_N)
(XCKPLL_MON1_P)
(DPL_B_MON1_N)
(DPL_B_MON1_P)
(DPL_B_MON2_N)
(SATA_OB_ANA)
(DPL_B_MON2_P)
(IPU*)
(IPD)
(IPU*)
(IPU)
20 45
10 91
10 91
10 91
10 25 91
402
1/16W MF-LF
5%
56
R2161
1 2
10 46 91
MF-LF
1/16W 402
5%
56
R2160
1
2
MF-LF
1/16W
5%
402
10K
R2155
1
2
20
IBEX_PEAK_M
FCBGA
OMIT
U1800
U2
Y3
AM3 AM1
AH45 AH46
AF48 AF47
T7
AB12
V13
F8
F10
P6
K9
H10
AB45 AB38 AB42 AB41 T39
H3
F1
BG10
BE10
T1
AB7
AB13
AA2
AA4
V6
Y7
P3
AB6
V3
M11
F38
C38
D37
J32
BD10
BA22
N18
AJ24
AK41
AK42
M32
N32
M30
N30
H12
AA23
AW22
C10
BB22
AY45
AY46
AV43
AV45
AF13
M18
A4
A49
BE1
BE53
BF1
BF53
BH1
BH2 BH52 BH53
BJ1
BJ2
A5
BJ4 BJ49
BJ5 BJ50 BJ52 BJ53
D1 D2
D53
E1
A50
E53
A52
A53
B2
B4 B52 B53
402
5% 1/16W MF-LF
10K
R2150
1
2
MF-LF
402
1/16W
5%
R2116
1 2
10K
2.2K
MF-LF1/16W
5%
402
21
R2115
10K
MF-LF
402
1/16W
R2113
1 2
5%
20K
4025%
R2112
1 2
MF-LF1/16W
10K
MF-LF
402
1/16W
R2114
1 2
5%
5%
1/16W
402
10K
R2110
1 2
MF-LF
5%
1/16W
402
10K
R2111
1 2
MF-LF
20 25 45 46
8
20 40
20 87
6
20 47
20 25 63
20 42
6
20 47 57
20 25
20 40
20 33 73
20 73
20 25 87
20 87
25 31
10K
MF-LF
402
1/16W
5%
R2121
1 2
10K
MF-LF
402
1/16W
5%
R2120
1 2
4025%
1/16W MF-LF
10K
R2122
1 2
402
1/16W5%MF-LF
10K
R2123
1 2
MF-LF
5%
1/16W
402
10K
R2124
1 2
20 25 34
MF-LF
402
1/16W
5%
10K
R2130
1 2
10K
MF-LF
402
1/16W
5%
R2131
1 2
10K
MF-LF
402
1/16W
5%
R2133
1 2
MF-LF
10K
402
1/16W
5%
R2132
1 2
10K
MF-LF
402
1/16W
5%
R2134
1 2
1/16W
10K
MF-LF
4025%
R2135
1 2
5%
1/16W
402
MF-LF
10K
R2136
1 2
1/16W
10K
MF-LF
4025%
R2137
1 2
1/16W MF-LF
4025%
10K
R2138
1 2
1/16W
100K
MF-LF
4025%
R2139
1 2
20 37
SYNC_DATE=06/15/2009
SYNC_MASTER=K17_REF
PCH MISC
SMC_IG_THROTTLE_L
PP3V3_S0
PCH_FCIM_EN_L
SMC_RUNTIME_SCI_L
GMUX_INT
ENET_LOW_PWR
PCH_VSS_NCTF<5>
PP3V3_S3
PM_THRMTRIP_L
ENET_LOW_PWR
SMC_IG_THROTTLE_L FW_PLUG_DET_L
MXM_GOOD
MXM_GOOD
WOL_EN AP_PWR_EN FW_PWR_EN
ME_TEMP_ALERT_L
JTAG_GMUX_TCK
ODD_PWR_EN_L
FW_PWR_EN
SDCARD_RESET
LPCPLUS_GPIO
ISOLATE_CPU_MEM_L
JTAG_GMUX_TDO
JTAG_GMUX_TCK
WOL_EN AP_PWR_EN
ME_TEMP_ALERT_L
PCH_GPIO24
ODD_PWR_EN_L
AUD_IPHS_SWITCH_EN
PCH_FCIM_EN_L
NC_PCIE_CLK100M_PE7P
NC_PCIE_CLK100M_PE6N NC_PCIE_CLK100M_PE6P
NC_PCIE_CLK100M_PE7N
FSB_CLK133M_CPU_N FSB_CLK133M_CPU_P
CPU_PECI
PCH_GPIO15
PCH_VRM_EN
TP_PCH_STP_PCI_L
PCH_GPIO39
TP_PCH_INIT3V3_L
NC_PCH_TP9
NC_PCH_TP11
NC_PCH_TP14
NC_PCH_TP8
PCH_A20GATE
PP3V3_S0
PP1V05_S0
PCH_RCIN_L
FW_PLUG_DET_L
SDCARD_RESET
JTAG_GMUX_TDO PCH_GPIO39
SPIROM_USE_MLB
PCH_GPIO24 PCH_VRM_EN
PCH_VSS_NCTF<22>
PCH_VSS_NCTF<19>
SPIROM_USE_MLB
PCH_VSS_NCTF<21>
PCH_VSS_NCTF<25>
PCH_VSS_NCTF<29>
PCH_VSS_NCTF<17>
PCH_VSS_NCTF<12>
PCH_VSS_NCTF<11>
PCH_VSS_NCTF<9>
TP_PCH_VSS_NCTF<7>
PCH_VSS_NCTF<2>
PCH_VSS_NCTF<1>
NC_PCH_SST
NC_PCH_NC4
NC_PCH_TP18
NC_PCH_NC5
NC_PCH_NC3
NC_PCH_TP17
NC_PCH_TP12
NC_PCH_TP13
NC_PCH_TP15
NC_PCH_TP16
NC_PCH_TP10
NC_PCH_TP7
NC_PCH_TP6
NC_PCH_TP5
NC_PCH_TP1
NC_PCH_TP4
NC_PCH_TP3
NC_PCH_TP2
PCH_THRMTRIP_L
NC_PCH_NC2
NC_PCH_NC1
NC_PCH_TP19
PCH_GPIO15
CPU_PWRGD
SMC_RUNTIME_SCI_L
GMUX_INT
PCH_VSS_NCTF<15>
PCH_VSS_NCTF<27>
LPCPLUS_GPIO
AUD_IPHS_SWITCH_EN
PP3V3_S5
21 OF 132
<E4LABEL>
<SCH_NUM>
<BRANCH>
20 OF 101
20 25 45 46
6 7
17 18 19 20 21 23 24 25 26
27 28 30 34 37 40 42 46 47 48
50 51 52 54 58 62 63 68 69 72
73 80 83 84 85 87 88 99
20
20 45
20 87
20 37
6
94
6 7 8
17 31 32 33 34 35 36 48 50 53 54 55
72 73 87
101
20
20 73
20 33 73
20 40
20 25
20 25 87
20 42
20
20
6
6
6
6
20
20
20
6
6
6
6
6 7
17 18 19 20 21 23 24 25 26
27 28 30 34 37 40 42 46 47 48
50 51 52 54 58 62 63 68 69 72
73 80 83 84 85 87 88 99
6 7
10 12 13 15 17 18 21 23 24
25 26 40 70 73 86
8
20 40
20 25 34
20 87
20
6
20 47 57
20
20
94
6
94
6
94
6
94
6
94
6
94
6
94
6
94
6
94
94
6
94
6
94
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
20
6
94
6
94
6
20 47
20 25 63
6 7
17 18 19 21 23 27 31 35 57 66 71 72 73 83 85 99
Page 21
VCCIO24
VCCIO55
VCCIO54
VCCIO53
VCCIO52
VCCIO51
VCCIO50
VCCIO49
VCCIO48
VCCIO47
VCCIO46
VCCIO45
VCCIO44
VCCIO43
VCCIO42
VCCIO41
VCCIO40
VCCIO39
VCCIO38
VCCIO37
VCCIO36
VCCIO35
VCCIO34
VCCIO33
VCCIO32
VCCIO31
VCCIO29
VCCIO28
VCCIO27
VCCIO26
VCCIO25
VCCVRM2
VCCFDIPLL
VCCAPLLEXP
VCCALVDS
VCCADAC1 VCCADAC2
VSSA_DAC1 VSSA_DAC2
VCCTX_LVDS1 VCCTX_LVDS2 VCCTX_LVDS3 VCCTX_LVDS4
VCC3_3_2
VCC3_3_4
VCC3_3_3
VCCPNAND1 VCCPNAND2 VCCPNAND3 VCCPNAND4 VCCPNAND5 VCCPNAND6 VCCPNAND7 VCCPNAND8 VCCPNAND9
VCCME3_3_1 VCCME3_3_2 VCCME3_3_3 VCCME3_3_4
VCC3_3_1
VCCVRM1
VSSA_LVDS
VCCCORE1 VCCCORE2 VCCCORE3 VCCCORE4 VCCCORE5 VCCCORE6 VCCCORE7 VCCCORE8 VCCCORE9 VCCCORE10 VCCCORE11 VCCCORE12 VCCCORE13 VCCCORE14 VCCCORE15
VCCDMI1 VCCDMI2
VCCIO30
VCCIO1
CRT
PCI-E*
NAND / SPI
HVCMOS
(7 OF 10)
VCC CORE
LVDS
FDI
DMI
VCCSUS3_3_23
VCCSUS3_3_28
VCCSUS3_3_27
VCCSUS3_3_26
VCCSUS3_3_25
VCCSUS3_3_24
VCCSUS3_3_22
VCCSUS3_3_21
VCCSUS3_3_20
VCCSUS3_3_19
VCCSUS3_3_18
VCCSUS3_3_17
VCCSUS3_3_16
VCCSUS3_3_15
VCCSUS3_3_14
VCCSUS3_3_13
VCCSUS3_3_12
VCCSUS3_3_11
VCCSUS3_3_10
VCCSUS3_3_9
VCCSUS3_3_8
VCCSUS3_3_7
VCCSUS3_3_6
VCCSUS3_3_5
VCCSUS3_3_4
VCCSUS3_3_3
VCCSUS3_3_2
VCCSUS3_3_1
VCCSUS3_3_29
VCCME3
V5REF
V5REF_SUS
VCC3_3_8 VCC3_3_9
VCC3_3_11
VCC3_3_10
VCC3_3_12 VCC3_3_13
VCC3_3_14
VCCSATAPLL1 VCCSATAPLL2
VCCVRM4
VCCME13 VCCME14 VCCME15 VCCME16
VCCSUSHDA
VCCRTC
V_CPU_IO1 V_CPU_IO2
DCPSST
DCPSUS
VCCSUS3_3_30
VCCSUS3_3_32
VCC3_3_6 VCC3_3_7
VCCACLK1 VCCACLK2
VCCLAN1 VCCLAN2
VCCME1
DCPSUSBYP
VCCME2
VCCME6
VCCME5
VCCME4
VCCME7 VCCME8 VCCME9
VCCME11
VCCME10
DCPRTC
VCCME12
VCCVRM3
VCCADPLLA1 VCCADPLLA2
VCCADPLLB2
VCCADPLLB1
VCC3_3_5
VCCSUS3_3_31
VCCIO10 VCCIO11 VCCIO12 VCCIO13 VCCIO14 VCCIO15 VCCIO16 VCCIO17 VCCIO18 VCCIO19 VCCIO20
VCCIO9
VCCIO56VCCIO21 VCCIO22 VCCIO23
VCCIO2 VCCIO3 VCCIO4
VCCIO5 VCCIO6 VCCIO7 VCCIO8
PCI/GPIO/LPC
USB
CPU
RTC
HDA
(10 OF 10)
CLOCK AND MISCELLANEOUS
PCI/GPIO/LPC
SATA
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
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Current numbers from Ibex Peak EDS Spec Update rev 0.71, doc #386904 (Table 8-3). Pre-Silicon Mobile Estimates.
163 mA S0, 65 mA S3-S5
1 (IPU) 0 (IPD) 1.8V Float
0 X 1.05V 1.05V
PLLs = VccAClk, VccSATAPLL, VccAPLLEXP & VccFDIPLL
(VCCME[1-16] total)
(VCC3_3[1-14] total)
3062 mA (VCCIO[1-56] total)
1432 mA
357 mA (VCC3_3[1-14] total)
1 (IPU) 1 1.5V Float
Note: 1.5V option consumes more current than 1.8V
(VCC3_3[1-14] total)
3062 mA (VCCIO[1-56] total)
357 mA (VCC3_3[1-14] total)
NOTE: Connect to 3.3V if NAND not used.
156 mA (1.8V)
< 1 mA
85 mA S0, 22 mA M-on
69 mA
3062 mA (VCCIO[1-56] total)
5 mA (if GPIO27 is low)
40 mA (if GPIO27 is low)
3062 mA (VCCIO[1-56] total)
1849 mA S0, 700 mA M-on
6 mA S0, < 1 mA S3-S5
2 mA S0-S5, ~6 uA G3
357 mA
163 mA S0, 65 mA S3-S5
1849 mA S0, 700 mA M-on
320 mA S0, 67 mA M-on
58 mA (1.05V)
61 mA (1.1V)
(VCCSUS3_3[1-32] total)
357 mA
< 1 mA S0-S5
< 1 mA
(VCCME[1-16] total)
Verify S0 okay
52 mA
59 mA
(VCCIO[1-56] total)
3062 mA
PCH output, for decoupling only
69 mA
PCH output, for decoupling only
357 mA (VCC3_3[1-14] total)
164 mA (VCCVRM[1-4] total)
3062 mA (VCCIO[1-56] total)
68 mA
164 mA (VCCVRM[1-4] total)
164 mA (VCCVRM[1-4] total)
164 mA (VCCVRM[1-4] total)
(VCCSUS3_3[1-32] total)
PCH output, for decoupling only
PCH output, for decoupling only
< 1 mA
31 mA (if GPIO27 is low)
GPIO27 HDA_SYNC VccVRM PLLs
115 mA
3062 mA
(VCCIO[1-56] total)
IBEX_PEAK_M
FCBGA
OMIT
U1800
AN35
AB34 AB35 AD35
AE50 AE52
AH38
BJ24
AB24
AH26 AH28 AH30 AH31 AJ30 AJ31
AB26 AB28 AD26 AD28 AF26 AF28 AF30 AF31
AT16 AU16
BJ18
AM23
AK24
AN20 AN22 AN23 AN24 AN26 AN28 BJ26 BJ28 AT26 AT28 AU26 AU28 AV26 AV28 AW26 AW28 BA26 BA28 BB26 BB28 BC26 BC28 BD26 BD28 BE26 BE28 BG26 BG28 BH27
AN30 AN31
AM8 AM9 AP11 AP9
AM16 AK16 AK20 AK19 AK15 AK13 AM12 AM13 AM15
AP43 AP45 AT46 AT45
AT22
AT24
AF53 AF51
AH39
IBEX_PEAK_M
FCBGA
OMIT
U1800
V9
V12
Y22
Y20
K49
F24
AT18 AU18
M36 N36 P36 U35
AD13
V15 V16 Y16
J38 L38
AP51 AP53
BB51 BB53
BD51 BD53
AH19 AD20 AF22 AD19 AF20 AF19 AH20 AB19 AB20 AB22
AF34
AD22
AH23 AJ35 AH35
AH34 AF32
V24
V23
V26 Y24 Y26
AH22
AF23 AF24
AD38
Y39 Y41 Y42
AA34 Y34 Y35 AA35
AD39 AD41 AF43 AF41 AF42
V39 V41 V42
A12
AK3 AK1
V28
M26 L28 L26 J28 J26 H28 H26 G28 G26 F28
U28
F26 E28 E26 C28 C26 B27 A28 A26 U23
P18
U26
U19 U20 U22
U24 P28 P26 N28 N26 M28
L30
AU24
AT20
20% CERM
10V
0.1UF
402
PLACE_NEAR=U1800.Y20:2.54MM
C2200
1
2
402
0.1UF
20% 10V CERM
PLACE_NEAR=U1800.V9:2.54MM
C2210
1
2
402
0.1UF
20% 10V CERM
PLACE_NEAR=U1800.V12:2.54MM
C2220
1
2
402
0.1UF
20% 10V CERM
PLACE_NEAR=U1800.Y22:2.54MM
C2230
1
2
20%
4.7UF
X5R
4V
402
C2225
1
2
402-HF
1%
0.2
1/6W
MF
R2225
1 2
SYNC_MASTER=K17_REF
PCH Power
SYNC_DATE=06/15/2009
MIN_LINE_WIDTH=0.2 mm VOLTAGE=1.05V
MIN_NECK_WIDTH=0.1 mm
PP1V05_S0_PCH_VCCIO_SSC_FLT
PP1V05_S0
PP3V3_S0
MIN_NECK_WIDTH=0.2 mm
PPVOUT_G3_PCH_DCPRTC
VOLTAGE=X.XV
MIN_LINE_WIDTH=0.2 mm
PP3V3_S0
PP1V8_S0
PP1V05_S0_PCH_VCCADPLLB
PP3V3_S0
PP1V8_S0
PP3V3_S0_PCH_VCCA_DAC
PP3V3_S0
PP1V8_S0_PCH_VCCTX_LVDS
PP1V05_S0
PP1V8_S0
PP3V3_S0
PP3V3_S5
PP1V05_S0_PCH_VCCADPLLA
PP1V05_S0
PP3V3_S0
PPVOUT_S5_PCH_DCPSUS
MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=X.XV
PPVOUT_S5_PCH_DCPSUSBYP
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.05V
MIN_LINE_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm
VOLTAGE=X.XV
PPVOUT_S0_PCH_DCPSST
PP1V05_S0_PCH_VCCAPLL_EXP
PP1V05_S0
PP1V05_S0
PP1V05_S0_PCH_VCCAPLL_FDI
PP1V05_S0
PP3V3_S5
PP1V05_S0_PCH_VCCAPLL_SATA
PP1V8_S0
PP1V05_S0
PP3V3_S0
PP3V42_G3H
PP1V05_S0
PP1V8_S0
PP1V05_S0_PCH_VCCA_CLK
PP5V_S0_PCH_V5REF
GND
PP5V_S5_PCH_V5REFSUS
PP3V3_S0
PP1V05_S0
PP1V05_S0
PP1V05_S0
PP1V05_S0
22 OF 132
<E4LABEL>
<SCH_NUM>
<BRANCH>
21 OF 101
6 7
10 12 13
15 17 18 20 21
23 24 25 26
40 70 73 86
6 7
17 18 19 20 21 23 24 25
26 27 28 30 34 37 40 42 46
47 48 50 51 52 54 58 62 63 68
69 72 73 80 83 84 85 87 88
99
6 7
17 18 19 20 21 23 24 25 26
27 28 30 34 37 40 42 46 47 48
50 51 52 54 58 62 63 68 69 72
73 80 83 84 85 87 88 99
6 7
12 16 21 23
24 58 71 72 87
24
6 7
17 18 19 20 21 23 24 25 26
27 28 30 34 37 40 42 46 47 48
50 51 52 54 58 62 63 68 69 72
73 80 83 84 85 87 88 99
6 7
12 16 21 23 24 58 71 72 87
24
6 7
17 18 19 20 21 23 24 25 26
27 28 30 34 37 40 42 46 47 48
50 51 52 54 58 62 63 68 69 72
73 80 83 84 85 87 88 99
24
6 7
10 12 13 15 17 18 20 21 23
24 25 26 40 70 73 86
6 7
12 16 21 23 24 58 71 72 87
6 7
17 18 19 20 21 23 24 25 26
27 28 30 34 37 40 42 46 47 48
50 51 52 54 58 62 63 68 69 72
73 80 83 84 85 87 88 99
6 7
17 18 19 20 21 23 27 31 35
57 66 71 72 73 83 85 99
24
6 7
10 12 13 15
17 18 20 21 23
24 25 26 40 70 73
86
6 7
17 18 19 20 21 23 24 25
26 27 28 30 34 37 40 42 46
47 48 50 51 52 54 58 62 63 68
69 72 73 80 83 84 85 87 88
99
23
6 7
10 12 13 15 17 18 20 21
23 24 25 26 40 70 73 86
6 7
10 12 13 15 17 18 20 21
23 24 25 26 40 70 73 86
23
6 7
10 12 13 15 17 18 20 21
23 24 25 26 40 70 73 86
6 7
17 18 19 20 21 23 27 31
35 57 66 71 72 73 83 85 99
23
6 7
12 16 21 23 24 58 71 72 87
6 7
10 12 13 15 17 18 20 21 23
24 25 26 40 70 73 86
6 7
17
18 19 20 21 23 24 25 26 27 28
30 34
37 40 42 46 47 48 50 51 52 54
58 62 63 68 69 72 73 80 83 84
85 87 88 99
6 7
17 23 43 45 46 47 48 49
53 64 65 66 73
6 7
10 12 13 15 17 18 20 21 23
24 25 26 40 70 73 86
6 7
12 16 21 23 24 58 71 72
87
23
23
23
6 7
17 18 19 20 21 23 24 25 26
27 28 30 34 37 40 42 46 47
48 50 51 52 54 58 62 63 68 69
72 73 80 83 84 85 87 88 99
6 7
10 12 13 15 17 18 20 21
23 24 25 26 40 70 73 86
6 7
10 12 13 15 17 18 20 21 23
24 25 26 40 70 73 86
6 7
10 12 13 15 17 18 20 21 23
24 25 26 40 70 73 86
6 7
10 12 13 15 17 18 20 21
23 24 25 26 40 70 73 86
Page 22
VSSVSS
(8 OF 10)
VSSVSS
(9 OF 10)
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DRAWING NUMBER
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PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
IBEX_PEAK_M
OMIT
FCBGA
U1800
AB16 AA19
AA32
AM28 BA42 AM30 AM31 AM32 AM34 AM35 AM38 AM39 AM42
AB11
AU20 AM46 AV22 AM49 AM7 AA50 BB10 AN32 AN50 AN52
AB15
AP12 AP42 AP46 AP49 AP5 AP8 AR2 AR52 AT11 BA12
AB23
AH48 AT32 AT36 AT41 AT47 AT7 AV12 AV16 AV20 AV24
AB30
AV30 AV34 AV38 AV42 AV46 AV49 AV5 AV8 AW14 AW18
AB31
AW2 BF9 AW32 AW36 AW40 AW52 AY11 AY43 AY47
AB32 AB39 AB43 AB47
AA20
AB5 AB8
AC2 AC52 AD11 AD12 AD16 AD23 AD30 AD31
AA22
AD32 AD34 AU22 AD42 AD46 AD49
AD7
AE2
AE4 AF12
AM19
Y13 AH49
AU4 AF35 AP13 AN34 AF45 AF46 AF49
AF5
AA24
AF8
AG2 AG52 AH11 AH15 AH16 AH24 AH32 AV18 AH43
AA26
AH47
AH7 AJ19
AJ2 AJ20 AJ22 AJ23 AJ26 AJ28 AJ32
AA28
AJ34
AT5
AJ4 AK12 AM41 AN19 AK26 AK22 AK23 AK28
AA30
AK30 AK31 AK32 AK34 AK35 AK38 AK43 AK46 AK49 AK5
AA31
AK8 AL2 AL52 AM11 BB44 AD24 AM20 AM22 AM24 AM26
FCBGA
IBEX_PEAK_M
OMIT
U1800
AY7 B11 B15 B19 B23 B31 B35 B39 B43 B47
B7 BG12 BB12 BB16 BB20 BB24 BB30 BB34 BB38 BB42 BB49
BB5 BC10 BC14 BC18
BC2 BC22 BC32 BC36 BC40 BC44 BC52
BH9 BD48 BD49
BD5 BE12 BE16 BE20 BE24 BE30 BE34 BE38 BE42 BE46 BE48 BE50
BE6
BE8
BF3 BF49 BF51 BG18 BG24
BG4 BG50 BH11 BH15 BH19 BH23 BH31 BH35 BH39 BH43 BH47
BH7
C12
C50
D51
E12
E16
E20
E24
E30
E34
E38
E42
E46
E48
E6 E8
F49
F5 G10 G14 G18
G2 G22 G32 G36 G40 G44 G52
AF39
H16 H20 H30 H34 H38 H42
H49 H5 J24 K11 K43 K47 K7 L14 L18 L2 L22 L32 L36 L40 L52 M12 M16 M20 N38 M34 M38 M42 M46 M49 M5 M8 N24 P11 AD15 P22 P30 P32 P34 P42 P45 P47 R2 R52 T12 T41 T46 T49 T5 T8 U30 U31 U32 U34 P38 V11 P16 V19 V20 V22 V30 V31 V32 V34 V35 V38 V43 V45 V46 V47 V49 V5 V7 V8 W2 W52 Y11 Y12 Y15 Y19 Y23 Y28 Y30 Y31 Y32 Y38 Y43 Y46 P49 Y5 Y6 Y8 P24 T43 AD51 AT8 AD47 Y47 AT12 AM6 AT13 AM5 AK45 AK39 AV14
PCH Grounds
SYNC_MASTER=K17_REF
SYNC_DATE=06/15/2009
23 OF 132
<E4LABEL>
<SCH_NUM>
<BRANCH>
22 OF 101
Page 23
NCNC
NC
NC
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THE INFORMATION CONTAINED HEREIN IS THE
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REVISION
DRAWING NUMBER
SIZE
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SHEET
PAGE TITLE
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PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
1 mA S0-S5
PCH V5REF Filter & Follower (PCH Reference for 5V Tolerance on PCI)
(VCCSUS3_3 Total)
PCH VCCME3_3 BYPASS
PCH CORE/VCC3_3 BYPASS (PCH MISC 3.3V PWR)
BB: C2419 removed from DG
BB: C2417 removed from DG
WF: C2413 not in DG or CRB
(PCH PCI 3.3V PWR)
PCH VCCFDIPLL Filter
(PCH PCIe PLL PWR)
PCH VCCAPLLEXP Filter
WF: C2311 not in DG or CRB
(PCH FDI PLL PWR)
(PCH SATA PLL PWR)
PCH VCCSATAPLL Filter
PCH VCCACLK Filter (PCH Misc PLL PWR)
(PCH PCIe/DMI 3.3V PWR)
PCH VCC3_3 BYPASS
(PCH 1.05V ME Core PWR)
PCH VCCME BYPASS
65 mA S3-S5
163 mA S0 /
PCH VCC3_3 BYPASS
PCH VCC3_3 BYPASS
(PCH SATA 3.3V PWR)
PCH VCC3_3 BYPASS
(PCH ME 3.3V PWR)
(PCH SUSPEND PCI 3.3V PWR)
PCH VCCSUS3_3 BYPASS
(PCH 1.05V CORE PWR)
(PCH NAND 1.8V/3.3V PWR)
PCH VCCPNAND BYPASS
PCH VCCSUSHDA BYPASS (PCH HD Audio 3.3V/1.5V PWR)
(PCH CLK 1.05V PWR)
1 mA
(PCH RTC 3.3V PWR)
6 uA G3
PCH VCCCORE BYPASS
PCH VCCIO BYPASS
(PCH USB 1.05V PWR)
PCH VCCIO BYPASS
PCH VCCIO BYPASS
(PCH SATA 1.05V PWR)
PCH VCCIO BYPASS (PCH PCIE 1.05V PWR)
PCH VCCRTC BYPASS
2 mA S0-S5 /
(PCH CLK/HVCMOS 3.3V PWR)
Current numbers from Ibex Peak EDS Spec Update rev 0.71, doc #386904 (Table 8-3). Pre-Silicon Mobile Estimates.
1 mA
PCH V5REF_SUS Filter & Follower (PCH Reference for 5V Tolerance on USB)
1 mA S0-S5
(PCH SUSPEND USB 3.3V PWR)
PCH USB/VCCSUS3_3 BYPASS
(PCH 1.1V/1.05V CPU I/O PWR)
PCH V_CPU_IO BYPASS
(PCH 1.05V LAN Core PWR)
PCH VCCLAN BYPASS
(PCH DMI 1.05V PWR)
PCH VCCIO BYPASS
1UF
X5R
10% 10V
402
PLACE_NEAR=U1800.K49:2.54MM
C2401
1
2
NO STUFF
6.3V
10%
402
CERM
1UF
PLACE_NEAR=U1800.AP51:2.54MM
C2419
1
2
5%
1/16W
402
MF-LF
100
R2401
2
1
BAT54DW-X-G
SOT-363
D2400
1
6
5
1/16W
402
5%
MF-LF
10
R2400
2
1
SOT-363
BAT54DW-X-G
D2400
4
3
2
16V
10% 402
X5R
0.1UF
PLACE_NEAR=U1800.A12:2.54MM
C2421
1
2
0.1UF
X5R 402
10% 16V
PLACE_NEAR=U1800.P18:2.54MM
C2425
1
2
16V
10% 402
X5R
0.1UF
PLACE_NEAR=U1800.A12:2.54MM
C2422
1
2
402
6.3V
10% CERM
1UF
OMIT
PLACE_NEAR=U1800.BJ24:2.54MM
C2413
1
2
6.3V
10% 402
1UF
OMIT
CERM
PLACE_NEAR=U1800.BJ18:2.54MM
C2415
1
2
NO STUFF
6.3V
10% 402
CERM
1UF
PLACE_NEAR=U1800.AK1:2.54MM
C2417
1
2
X5R 402
16V
0.1UF
10%
PLACE_NEAR=U1800.U23:2.54MM
C2427
1
2
PLACE_NEAR=U1800.A26:2.54MM
0.1UF
X5R 402
10% 16V
C2426
1
2
0.1UF
X5R 402
10% 16V
PLACE_NEAR=U1800.AM8:2.54MM
C2430
1
2
0.1UF
X5R 402
10% 16V
PLACE_NEAR=U1800.V15:2.54MM
C2435
1
2
PLACE_NEAR=U1800.J38:2.54MM
0.1UF
X5R 402
10% 16V
C2436
1
2
0.1UF
X5R 402
10% 16V
PLACE_NEAR=U1800.AD13:2.54MM
C2437
1
2
0.1UF
X5R 402
10% 16V
PLACE_NEAR=U1800.AN35:2.54MM
C2438
1
2
0.1UF
X5R 402
10% 16V
PLACE_NEAR=U1800.AB34:2.54MM
C2439
1
2
16V
10%
402
X5R
0.1UF
PLACE_NEAR=U1800.AK13:2.54MM
C2440
1
2
1UF
CERM 402
10%
6.3V
PLACE_NEAR=U1800.L30:2.54MM
C2445
1
2
16V
10%
402
X5R
0.1UF
PLACE_NEAR=U1800.AT18:2.54MM
C2452
1
2
16V
10%
402
X5R
0.1UF
PLACE_NEAR=U1800.AT18:2.54MM
C2451
1
2
6.3V
20%
603
X5R
4.7UF
PLACE_NEAR=U1800.AT18:2.54MM
C2450
1
2
6.3V
10% 402
CERM
1UF
PLACE_NEAR=U1800.V39:2.54MM
C2469
1
2
6.3V
X5R-CERM
603
22UF
20%
PLACE_NEAR=U1800.V39:2.54MM
C2467
1
2
6.3V
X5R-CERM
603
22UF
20%
PLACE_NEAR=U1800.AD38:2.54MM
C2466
1
2
NO STUFF
1UF
10%
6.3V 402
CERM
PLACE_NEAR=U1800.AF23:2.54MM
C2460
1
2
6.3V
10% 402
CERM
1UF
PLACE_NEAR=U1800.AH35:2.54MM
C2477
1
2
6.3V
10% 402
CERM
1UF
PLACE_NEAR=U1800.AH23:2.54MM
C2476
1
2
6.3V
10% 402
CERM
1UF
PLACE_NEAR=U1800.AF32:2.54MM
C2475
1
2
6.3V
10% 402
CERM
1UF
PLACE_NEAR=U1800.V24:2.54MM
C2480
1
2
6.3V
10%
402
CERM
1UF
PLACE_NEAR=U1800.AB19:2.54MM
C2485
1
2
PLACE_NEAR=U1800.AN20:2.54MM
6.3V
10% 402
CERM
1UF
C2494
1
2
6.3V
10% 402
CERM
1UF
PLACE_NEAR=U1800.AN20:2.54MM
C2493
1
2
6.3V
10% 402
CERM
1UF
PLACE_NEAR=U1800.AN20:2.54MM
C2492
1
2
402
6.3V
10% CERM
1UF
PLACE_NEAR=U1800.AN20:2.54MM
C2491
1
2
10UF
6.3V
20% 603
X5R
PLACE_NEAR=U1800.AN20:2.54MM
C2490
1
2
402
6.3V
10% CERM
1UF
PLACE_NEAR=U1800.AT16:2.54MM
C2455
1
2
6.3V
10% 402
CERM
1UF
PLACE_NEAR=U1800.AD38:2.54MM
C2468
1
2
6.3V
X5R-CERM
603
22UF
20%
PLACE_NEAR=U1800.AD38:2.54MM
C2465
1
2
10% 402
1UF
6.3V CERM
PLACE_NEAR=U1800.AB24:2.54MM
C2471
1
2
6.3V
20% 603
X5R
10UF
PLACE_NEAR=U1800.AB24:2.54MM
C2470
1
2
6.3V
10% 402
CERM
1UF
PLACE_NEAR=U1800.A12:2.54MM
C2420
1
2
PLACE_NEAR=U1800.F24:2.54MM
402
1UF
X5R
10% 10V
C2400
1
2
SYNC_DATE=06/15/2009
SYNC_MASTER=K17_REF
PCH Non-GFX Decoupling
PP5V_S5
PP5V_S0
PP5V_S0_PCH_V5REF
MIN_LINE_WIDTH=0.3MM VOLTAGE=5V
MIN_NECK_WIDTH=0.25MM
PP1V05_S0
PP1V05_S0
PP1V05_S0
PP1V05_S0
PP1V05_S0
PP1V05_S0
PP1V05_S0
GND
PP1V8_S0
PP3V3_S0
PP3V42_G3H
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S5
PP3V3_S5
PP1V05_S0
PP3V3_S0
PP1V05_S0_PCH_VCCA_CLK
VOLTAGE=1.05V
MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.25MM
PP1V05_S0_PCH_VCCAPLL_SATA
VOLTAGE=1.05V
MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.25MM
PP1V05_S0_PCH_VCCAPLL_FDI
VOLTAGE=1.05V
MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.25MM
VOLTAGE=1.05V
MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.25MM
PP1V05_S0_PCH_VCCAPLL_EXP
PP5V_S5_PCH_V5REFSUS
MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.25MM VOLTAGE=5V
PP3V3_S5
PP3V3_S0
24 OF 132
<E4LABEL>
<SCH_NUM>
<BRANCH>
23 OF 101
6 7
66 72
6 7
42 47 52 54
68 69 70 72 86
88
21
6 7
10 12 13 15 17 18 20 21
23 24 25 26 40 70 73 86
6 7
10 12 13 15 17 18 20 21
23 24 25 26 40 70 73 86
6 7
10 12 13 15 17 18 20 21
23 24 25 26 40 70 73 86
6 7
10 12 13 15 17 18 20 21
23 24 25 26 40 70 73 86
6 7
10 12 13 15 17 18 20 21
23 24 25 26 40 70 73 86
6 7
10 12 13 15 17 18 20 21
23 24 25 26 40 70 73 86
6 7
10 12 13 15 17 18 20 21
23 24 25 26 40 70 73 86
6 7
12 16 21 24 58 71 72 87
6 7
17 18 19 20 21 23 24 25
26 27 28 30 34 37 40 42 46 47
48 50 51 52 54 58 62 63 68 69
72 73 80 83 84 85 87 88 99
6 7
17 21 43 45 46 47 48 49
53 64 65 66 73
6 7
17 18
19 20 21 23 24 25 26 27 28 30
34 37 40 42
46 47 48 50 51 52 54 58 62
63 68 69 72 73 80 83 84 85
87 88 99
6 7
17 18
19 20 21 23 24 25 26 27 28 30
34 37 40 42
46 47 48 50 51 52 54 58 62
63 68 69 72 73 80 83 84 85
87 88 99
6 7
17 18 19 20 21 23 24 25
26 27 28 30 34 37 40 42 46 47
48 50 51 52 54 58 62 63 68
69 72 73 80 83 84 85 87 88
99
6 7
17 18 19 20 21 23 24 25
26 27 28 30 34 37 40 42 46 47
48 50 51 52 54 58 62 63 68
69 72 73 80 83 84 85 87 88
99
6 7
17 18 19 20 21 23 24 25
26 27 28 30 34 37 40 42 46 47
48 50 51 52 54 58 62 63 68 69
72 73 80 83 84 85 87 88 99
6 7
17
18 19 20
21 23 27
31 35 57
66 71 72
73 83 85
99
6 7
17 18 19 20 21 23 27 31
35 57 66 71 72 73 83 85 99
6 7
10 12 13 15 17 18 20 21
23 24 25 26 40 70 73 86
6 7
17 18 19 20
21 23 24 25 26
27 28 30
34 37 40
42 46 47
48 50 51
52 54 58
62 63 68
69 72 73
80 83 84
85 87 88
99
21
21
21
21
21
6 7
17 18 19 20
21 23 27
31 35 57
66 71 72
73 83 85
99
6 7
17 18 19 20 21 23 24 25
26 27 28 30 34 37 40 42 46 47
48 50 51 52 54 58 62 63 68 69
72 73 80 83 84 85 87 88 99
Page 24
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER
SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
(PCH DPLLA PWR)
PCH VCCADPLLA Filter
PCH VCCADPLLB Filter
PCH VCCTX_LVDS Filter
69 mA
68 mA
(PCH DPLLB PWR)
Design recommendations from Calpella Design Guide Rev 1.5 (doc #398905) Section 3.25.3 tables 161 and 162.
Current numbers from Ibex Peak EDS Spec Update rev 0.71, doc #386904 (Table 8-3). Pre-Silicon Mobile Estimates.
69 mA
59 mA
(PCH LVDS TX PWR)
PCH VCCADAC Filter
69 mA
68 mA
59 mA
69 mA
69 mA
137 mA
Design recommendations from Calpella Small Form Factor Design Guide Rev 1.5 (doc #407364) table 2-34 and Calpella Small Form F
actor Schematic Check List Rev 1.1 (doc #395914) table 3.26.
VCAP2 (CPU BSC Package) DECOUPLING
PLACEMENT_NOTE (C2524-C2539):
PLACEMENT_NOTE (C2500-C2506):
3x 330uF 6 mOhm (2 stuffed), 3x 22uF 0603, 16x 1uF 0402
GFX (CPU VCCAXG) DECOUPLING
(PCH DAC PLL PWR)
PLACEMENT_NOTE (C2510-C2514):
5x 1uF 0402
0805
0.1UH
PLACE_NEAR=U1800.AP43:2.54MM
L2570
1 2
PLACE_NEAR=U1800.AP43:2.54MM
16V 402
0.01UF
20% CERM
C2572
1
2
NO STUFF
402
CERM
PLACE_NEAR=U1800.BB51:2.54MM
1UF
6.3V
10%
C2561
1
2
0
402
5%
MF-LF
1/16W
R2560
1 2
CASE-B2-SM1
220UF
POLY-TANT
2.5V
20%
PLACE_NEAR=U1800.BB51:2.54MM
C2560
1
2
NO STUFF
PLACE_NEAR=U1800.BD51:2.54MM
402
6.3V CERM
1UF
10%
C2566
1
2
PLACE_NEAR=U1800.BD51:2.54MM
220UF
POLY-TANT
CASE-B2-SM1
20%
2.5V
C2565
1
2
MF-LF
402
1/16W
0
5%
R2565
1 2
PLACE_NEAR=U1800.AE50:2.54MM
CERM
20% 16V
402
0.01UF
C2552
1
2
PLACE_NEAR=U1800.AE50:2.54MM
20%
6.3V X5R 603
10UF
C2550
1
2
Place on bottom side of U1000.
22UF
20%
603
X5R-CERM
6.3V
C2500
1
2
PLACE_NEAR=U1800.AE50:2.54MM
0603
180-OHM-1.5A
L2550
1 2
MF-LF
1/16W
5%
402
0
R2550
1 2
16V 402
20% CERM
PLACE_NEAR=U1800.AP43:2.54MM
0.01UF
C2571
1
2
10% 402
0.1UF
16V X5R
PLACE_NEAR=U1800.AE50:2.54MM
C2551
1
2
Place on bottom side of U1000.
10V 402
1UF
10% X5R
C2514
1
2
Place on bottom side of U1000.
1UF
X5R
10% 402
10V
C2513
1
2
Place on bottom side of U1000.
X5R
10%
1UF
402
10V
C2512
1
2
Place on bottom side of U1000.
1UF
X5R
10% 402
10V
C2511
1
2
Place on bottom side of U1000.
10V 402
1UF
10% X5R
C2510
1
2
D2T-SM2
20% POLY-TANT
2.0V
330UF
C2505
1
23
330UF
D2T-SM2
2.0V
20% POLY-TANT
C2506
1
23
603
X5R-CERM
PLACE_NEAR=U1800.AP43:2.54MM
22UF
20%
6.3V
C2570
1
2
10UH-0.12A-0.36OHM
0603
L2560
1 2
22UF
20%
6.3V X5R-CERM
Place on bottom side of U1000.
603
C2501
1
2
10UH-0.12A-0.36OHM
0603
L2565
1 2
402
10% X5R
1UF
10V
C2535
1
2
402
10% X5R
10V
1UF
C2534
1
2
402
10% X5R
1UF
10V
C2533
1
2
402
10% X5R
1UF
10V
C2532
1
2
402
10% X5R
1UF
10V
C2531
1
2
402
10% X5R
10V
1UF
C2530
1
2
402
10% X5R
1UF
10V
C2529
1
2
402
10% X5R
1UF
10V
C2528
1
2
Place on bottom side of U1000.
1UF
402
10% X5R
10V
C2527
1
2
Place on bottom side of U1000.
402
10% X5R
10V
1UF
C2526
1
2
Place on bottom side of U1000.
402
10V
10% X5R
1UF
C2525
1
2
Place on bottom side of U1000.
402
10% X5R
1UF
10V
C2524
1
2
402
10V
10% X5R
1UF
C2539
1
2
402
10V X5R
10%
1UF
C2538
1
2
402
10% X5R
1UF
10V
C2537
1
2
402
10% X5R
1UF
10V
C2536
1
2
20%
22UF
603
X5R-CERM
6.3V
Place on bottom side of U1000.
C2502
1
2
SYNC_DATE=06/15/2009
SYNC_MASTER=K17_REF
CPU/PCH GFX Decoupling
PPVCORE_S0_CPU_VCAP2
PPVCORE_S0_GFX
PP3V3_S0
PP1V8_S0
PP3V3_S0_PCH_VCCA_DAC_F
MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.25MM VOLTAGE=3.3V
PP1V8_S0_PCH_VCCTX_LVDS
VOLTAGE=1.8V
MIN_NECK_WIDTH=0.2 MM
MIN_LINE_WIDTH=0.4 MM
PP1V05_S0
PP3V3_S0_PCH_VCCA_DAC
MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.3V
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V
MIN_LINE_WIDTH=0.4 MM
PP1V05_S0_PCH_VCCADPLLA
VOLTAGE=1.05V
MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.5MM
PP1V05_S0_PCH_VCCADPLLA_F
VOLTAGE=1.05V
MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.5MM
PP1V05_S0_PCH_VCCADPLLB_F
PP1V05_S0_PCH_VCCADPLLB
MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V
25 OF 132
<E4LABEL>
<SCH_NUM>
<BRANCH>
24 OF 101
7
13
6 7
13 49 69
6 7
17 18 19 20 21 23 25 26
27 28 30 34 37 40 42 46 47
48 50 51 52 54 58 62 63 68 69
72 73 80 83 84 85 87 88 99
6 7
12 16 21 23 58 71 72 87 21
6 7
10 12 13 15 17 18 20 21
23 25 26 40 70 73 86
21
21
21
Page 25
BI
OUT
BI
OUT
IN
IN IN
IN IN
IN
IN
IN
IN
IN
OUT
NC
NC
BI
OUT
OUT
OUT
IN
OUT
IN
IN
IN
IN IN
IN IN
OUT
IN
IN
IN
OUT
OUT
IN
IN
IN
IN IN
IN IN
IN IN
IN IN
IN IN
IN IN
IN
IN
IN
IN
IN IN IN IN
IN
IN
IN IN
IN IN
IN
IN
IN
IN
IN
TABLE_5_ITEM
CRITICAL BOM OPTION
TABLE_5_HEAD
PART#
DESCRIPTION
QTY
REFERENCE DESIGNATOR(S)
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER
SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
NOTE: XDP_DBRESET_L must be pulled-up to 3.3V.
OBSFN_D0 OBSFN_D1
OBSDATA_D0
Calpella PCH mini XDP
516S0852
Calpella Processor mini XDP
OBSFN_A1
OBSDATA_A1
RESET#/HOOK6
NOTE: XDP_DBRESET_L must be pulled-up to 3.3V.
OBSDATA_A3
VCC_OBS_CD
OBSDATA_D1
OBSDATA_D2
HOOK2
ITPCLK#/HOOK5 VCC_OBS_CD
DBR#/HOOK7
OBSDATA_C3
1K series R on PCH Support Page
PCH OC2#
PCH OC7#
PCH OC6#
PCH OC5#
PCH OC4#
PCH OC3#
PCH OC1#
PCH OC0#
PCH GPIO28
PCH GPIO18
PCH GPIO20
PCH GPIO21 PCH GPIO19
PCH GPIO36 PCH GPIO37
PCH GPIO16 PCH GPIO49
PCH GPIO0
OBSFN_D1
OBSDATA_D0
RESET#/HOOK6 DBR#/HOOK7
TRSTn
TCK0
TMS XDP_PRESENT#
TDI
TCK1
OBSDATA_B3
PWRGD/HOOK0
HOOK1
HOOK3
SDA SCL
OBSDATA_A0
OBSFN_A0
TDO
OBSDATA_C2
OBSFN_D0
OBSDATA_D3
TRSTn
OBSDATA_C0
OBSFN_C1
OBSFN_C0
OBSFN_B1
OBSDATA_A0 OBSDATA_A1
OBSFN_B0
OBSDATA_A2
OBSFN_A0 OBSFN_A1
OBSDATA_B3
PWRGD/HOOK0
HOOK1
VCC_OBS_AB
OBSDATA_B2
HOOK3
TCK1 TCK0
OBSDATA_B0 OBSDATA_B1
OBSDATA_D2
OBSDATA_D1
SDA SCL
OBSDATA_C1
OBSDATA_C3
OBSDATA_C2
OBSFN_C1
OBSFN_C0
ITPCLK/HOOK4 ITPCLK#/HOOK5
OBSDATA_D3
XDP_PRESENT#
TDO
TDI TMS
OBSDATA_C1
ITPCLK/HOOK4
OBSDATA_C0
HOOK2
VCC_OBS_AB
OBSDATA_A2 OBSDATA_A3
OBSFN_B0 OBSFN_B1
OBSDATA_B0 OBSDATA_B1
OBSDATA_B2
518S0774
17 25 26 28 30 32 42 47 48 63 88 94
17
10 91
17
27 45 73 87
19
19 35
19
19
19
19
19
19 46
17
17
2
1
R2615
402
MF-LF
1/16W
5%
XDP
51
9
8 7
60
6
59
58 57
56 55
54 53
52 51
50
5
49
48 47
46 45
44 43
42 41
40
4
39
38 37
36 35
34 33
32 31
30
3
29
28 27
26 25
24 23
22 21
20
2
19
18 17
16 15
14 13
12 11
10
1
J2600
F-ST-SM
LTH-030-01-G-D-NOPEGS
CRITICAL
OMIT
XDP_CONN_PCH
9
87
60
6
59
5857
5655
5453
5251
50
5
49
4847
4645
4443
4241
40
4
39
3837
3635
3433
3231
30
3
29
2827
2625
2423
2221
20
2
19
1817
1615
1413
1211
10
1
J2650
F-ST-SM-HF
CRITICAL
DF40C-60DS-0.4V
2
1
C2600
XDP
402
16V
0.1uF
10% X5R
2
1
C2601
XDP
X5R
0.1uF
10%
402
16V
17 25 26 28 30 32 42 47 48 63 88 94
10 91
10 91
10 25 27 91
10 91
10 91
21
R2611
PLACE_NEAR=U1000.N70:1.00MM
5%
MF-LF
1/16W
402
XDP
1K
10 20 91
10 91
10 91
10 91
10 91
10 91
10 91
18 25 45
10 91
21
R2690
MF-LF
1/16W
402
0
5%
XDP_NORMAL&XDP_CPU
21
R2610
1/16W
5%
XDP
MF-LF
402
1K
21
R2695
5%
0
402
1/16W MF-LF
XDP_CPU
21
R2696
MF-LF
1/16W
402
5%
XDP_GMCH
0
21
R2692
MF-LF
1/16W
402
0
5%
XDP_NORMAL&XDP_GMCH
2
1
R2691
XDP_NORMAL
MF-LF
1/16W
402
0
5%
10
10
10
10
9
91
9
91
10 91
9
91
9
91
9
91
9
91
9
91
9
91
9
91
8 9
91
9
91
9
91
9
91
9
91
5
6
7
8
4
3
2
1
RP2600
1/16W SM-LF
5%
0
XDP_CPU_BPM
8
7
6
5
1
2
3
4
RP2601
SM-LF
PLACEMENT_NOTE=Place R2501 close to R2500 to minimize stubs.
1/16W
5%
0
XDP_CPU_CFG
10 91
10 91
10 91
10 91
9
91
9
91
9
91
9
91
20 45 46
20 31
17 40
17 33
17 42
17
27
20 87
20 34
20
20 63
SYNC_DATE=06/15/2009
SYNC_MASTER=K17_REF
eXtended Debug Port (XDP)
516S0852
1
CONN,PLUG,B2B,60P,0.5MM,NOPEG
J2600
CRITICAL
XDP_CONN_CPU
TP_XDP_HOOK3
SMBUS_PCH_DATA SMBUS_PCH_CLK
TP_XDPPCH_OBSFN_A<0> TP_XDPPCH_OBSFN_A<1>
USB_HUB_SOFT_RESET_L
PCH_GPIO59
PCH_GPIO42
PCH_GPIO41
TP_XDPPCH_OBSFN_B<1>
TP_XDPPCH_OBSFN_B<0>
PCH_GPIO43 PCH_GPIO9
PCH_GPIO10 PM_LATRIGGER_L
ALL_SYS_PWRGD
PM_PWRBTN_L
TP_XDPPCH_HOOK2 TP_XDPPCH_HOOK3
SMBUS_PCH_DATA SMBUS_PCH_CLK
JTAG_PCH_TCK
TP_XDPPCH_HOOK4
ME_TEMP_ALERT_L
AUD_IPHS_SWITCH_EN
JTAG_GMUX_TCK
SDCARD_RESET
TP_XDPPCH_OBSFN_D<1>
TP_XDPPCH_OBSFN_D<0>
SATARDRVR_A_EN SATARDRVR_B_EN
FW_CLKREQ_L AP_CLKREQ_L
SMC_IG_THROTTLE_L
ISOLATE_CPU_MEM_L
JTAG_PCH_TDI JTAG_PCH_TMS
TP_XDPPCH_TRST_L
JTAG_PCH_TDO
XDP_DBRESET_L
XDPPCH_PLTRST_L
TP_XDPPCH_HOOK5
XDP_TCK
XDP_OBSDATA_A<2>
XDP_PWRGD
XDP_TDO
XDP_OBSDATA_A<1>
XDP_TDO
XDP_TDI
XDP_CPUPWRGD
PP1V05_S0
PM_PWRBTN_L
XDP_BPM_L<7>
XDP_BPM_L<6>
XDP_BPM_L<4> XDP_BPM_L<5>
CPU_CFG<16>
CPU_CFG<17>
XDP_OBSDATA_A<3>
XDP_OBSDATA_A<0>
XDP_PRDY_L
XDP_PREQ_L CPU_CFG<8>
CPU_CFG<9>
CPU_CFG<0> CPU_CFG<1>
CPU_CFG<2> CPU_CFG<3>
CPU_CFG<11>
CPU_CFG<5>
CPU_CFG<4>
CPU_CFG<6>
FSB_CLK133M_ITP_P
CPU_CFG<7>
FSB_CLK133M_ITP_N
XDP_DBRESET_L
XDP_TDI XDP_TMS
XDP_BPM_L<0>
XDP_BPM_L<2>
XDP_BPM_L<1>
XDP_BPM_L<3>
CPU_CFG<12> CPU_CFG<13>
CPU_CFG<15>
CPU_CFG<14>
CPU_PWRGD
JTAG_GMCH_TDI
JTAG_CPU_TDO
JTAG_GMCH_TDO
JTAG_CPU_TDI
FSB_CPURST_L
XDP_TRST_L
PP3V3_S0
CPU_CFG<10>
XDP_CPURST_L
26 OF 132
<E4LABEL>
<SCH_NUM>
<BRANCH>
25 OF 101
18 25 45
17 25 26 28 30 32 42 47 48 63 88 94
17 25 26 28 30 32 42 47 48 63 88 94
10 25 27 91
25 91
25 91
25 91
6 7
10 12 13 15 17 18 20 21
23 24 26 40 70 73 86
25 91
6 7
17 18 19 20 21 23 24 26
27 28 30 34 37 40 42 46 47 48
50 51 52 54 58 62 63 68 69 72
73 80 83 84 85 87 88 99
91
Page 26
IN
BI
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
CPU0*
CPU0
REF_FS
USB
CPU1
CPU1*
SRC1*
SRC1
SRC0*/SATA*
SRC0/SATA
27M_NSS
27M_SS
DOT96*
XOUT
XIN
SCLK
SDATA
CK_PWRGD/PWRDWN*
VDD_SRC
VDD_CPU
VDD_REF
VDD_DOT
VDD_27
VDD_SRC_IO
VDD_CPU_IOVSS_CPU
VSS_27
VSS_DOT
THRM
VSS_SRC
VSS_REF
DOT96
27MHZ_OE*
PAD
OUT OUT
IN
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER
SIZE
D
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IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
No internal pull.
Muxed Graphics implementations.
or connected to logic for
Must be strapped appropriately
(IPD)
PCH USB Clock 96MHz
Unused 48MHz
PCH REFCLK 14.31818MHz
Unused BCLK 133MHz
PCH BCLK 133MHz
PCH SATA 100MHz
GPU 27MHz Clocks (Single-Ended)
PCH DMI/PCIe 100MHz
All other output frequencies are fixed.
FS=0 => 133MHz BCLKs, FS=1 => 100MHz BCLKs
NOTE: REF/FS pin is input until first CK_PWRGD rising edge.
BYPASS=U2790::5 mm
10V
20%
402
CERM
0.1UF
C2790
1
2
68
SC70-5
74HC1G00GWDG
U2790
3
2
1
4
5
PLACE_NEAR=Y2730.1:2 mm:NO_VIA
5%
50V
CERM
402
18pF
C2730
1
2
CRITICAL
5X3.2-SM
14.31818
Y2730
1 2
18pF
402
CERM
50V
5%
PLACE_NEAR=Y2730.2:2 mm:NO_VIA
C2731
1
2
FERR-120-OHM-1.5A
0402
L2710
1 2
0402
FERR-120-OHM-1.5A
L2700
1 2
PLACE_NEAR=L2700.2:2 mm:NO_VIA
10UF
603
X5R
6.3V
20%
C2700
1
2
PLACE_NEAR=L2710.2:2 mm:NO_VIA
20%
6.3V X5R 603
10UF
C2710
1
2
17 25 28 30 32 42 47 48 63 88 94
17 25 28 30 32 42 47 48 63 88 94
17 93
17 93
17 93
17 93
17 93
17 93
17 93
PLACE_NEAR=U2700.15:2 mm
10% 16V X5R 402
0.1UF
C2715
1
2
PLACE_NEAR=U2700.18:2 mm
10% 16V X5R 402
0.1UF
C2716
1
2
PLACE_NEAR=U2700.1:2 mm
0.1UF
402
X5R
16V
10%
C2705
1
2
PLACE_NEAR=U2700.5:2 mm
0.1UF
402
X5R
16V
10%
C2706
1
2
CRITICAL
QFN
SL28776
U2700
6
7
16
25
23
22
20
19
3
4
30
32
31
11 10
13
14
33
8
5
24
18
1
29
17
15
9212
26
12
28 27
PLACE_NEAR=U2700.17:2 mm
0.1UF
402
X5R
16V
10%
C2707
1
2
PLACE_NEAR=U2700.24:2 mm
0.1UF
402
X5R
16V
10%
C2708
1
2
PLACE_NEAR=U2700.29:2 mm
0.1UF
402
X5R
16V
10%
C2709
1
2
17 93
17 93
73
MF-LF
1/16W
5%
10K
402
R2790
1
2
SYNC_DATE=06/23/2009
SYNC_MASTER=K17_MLB
Clock (CK505)
PCH_CLK14P3M_REFCLK
PCH_CLK96M_DOT_P
PCH_CLK96M_DOT_N
PCH_CLK100M_SATA_N
PCIE_CLK100M_PCH_P
PCIE_CLK100M_PCH_N
MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm
PP3V3_S0_CK505_F
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.3 mm
PP1V05_S0_CK505_F
VOLTAGE=1.05V
MIN_NECK_WIDTH=0.2 mm
PP1V05_S0
FSB_CLK133M_PCH_N FSB_CLK133M_PCH_P
TP_CK505_CPU1N
TP_CK505_USB
CK505_CKPWRGD
CK505_CLK14P3M_XIN CK505_CLK14P3M_XOUT
SMBUS_PCH_CLK SMBUS_PCH_DATA
CK505_27MHZ_EN_L
TP_CK505_CLK27M_SS
CK505_CLK27M
PCH_CLK100M_SATA_P
TP_CK505_CPU1P
CPUIMVP_CLK_EN_L
PP3V3_S0
27 OF 132
<E4LABEL>
<SCH_NUM>
<BRANCH>
26 OF 101
6 7
10 12 13 15 17 18 20 21
23 24 25 40 70 73 86
27
6 7
17 18 19 20 21 23 24 25
27 28 30 34 37 40 42 46 47 48
50 51 52 54 58 62 63 68 69 72
73 80 83 84 85 87 88 99
Page 27
IN
OUT
OUT
OUT
IN
OUT
IN
IN
IN
OUT
NC NC
NC NC
OUT
IN
IN
OUT
OUT
OUT
IN
NC NC
OUT
IN
OUT
OUT
OUT
OUT
OUT
IN
IN
OUT
OUT
IN
OUT
OUT
BI
OUT
D
GS
OUT
IN
OUT
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER
SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
PCH S0 PWRGD
Caesar II (ENET) 25MHz Crystal
Ethernet WAKE# Isolation
PCH 25MHz Crystal
PCH RTC Crystal
Platform Reset Connections
Unbuffered
VTT voltage divider on CPU page
Series R is R4283
PCH Reset Button
Buffered
10 25 91
12pF
CERM
50V 402
5%
C2810
1 2
12pF
50V 402
5%
CERM
C2811
1 2
SM-2
CRITICAL
32.768K
Y2810
2 4
1 3
5%
1/16W
0
MF-LF
402
R2810
1 2
5%
10M
MF-LF
402
1/16W
R2811
1
2
1/16W
402
0
5%
MF-LF
XDP
R2896
1 2
5%
33
1/16W
402
MF-LF
R2883
1 2
5%
402
MF-LF
33
1/16W
R2881
1 2
6
27 47 87 94
45
33
17
17
19 27 31 40
402
1/16W MF-LF
5%
PLACE_NEAR=U1800.P53
22
R2826
1 2
5%
MF-LF
1/16W
402
PLACE_NEAR=U1800.N52
22
R2825
1 2
19 94
CERM
5%
402
50V
12pF
C2815
1 2
402
CERM
12pF
50V
5%
C2816
1 2
CRITICAL
25.0000M
SM-3.2X2.5MM
Y2815
2 4
1 3
402
0
5% 1/16W MF-LF
R2815
1 2
5%
10M
MF-LF
1/16W
402
R2816
1
2
DCI
17
17
32
1/16W
402
5%
MF-LF
0
R2871
1 2
402
20% CERM
0.1UF
10V
C2850
1
2
25 45 73 87
68
6
47 94
45 94
18
MC74VHC1G08
SC70-HF
U2850
3
2
1
4
5
19
27pF
402
5%
50V
CERM
C2820
1 2
27pF
402
CERM
5%
50V
C2821
1 2
SM-3.2X2.5MM
25.0000M
CRITICAL
Y2820
2 4
1 3
200
MF-LF
5% 1/16W
402
R2820
1 2
10M
MF-LF
5%
1/16W
NO STUFF
402
R2821
1
2
37 95
37 95
87
402
MF-LF
1/16W
5%
PLACE_NEAR=U1800.P46
22
R2827
1 2
25
1K
XDP
1/16W
402
MF-LF
5%
R2889
1 2
402
MF-LF
1/16W
0
5%
R2888
1 2
34
0
5%
MF-LF
1/16W
402
R2884
1 2
0.1UF
402
10V
20%
CERM
C2880
1
2
MC74VHC1G08
SC70-HF
U2880
3
2
1
4
5
1/16W MF-LF
5%
100K
402
R2880
1
2
MF-LF
1/16W
402
5%
10K
R2850
1
2
37 95
1/16W
402
MF-LF
5%
0
R2882
1 2
17 93
5% 1/16W MF-LF
402
PLACE_NEAR=U1800.P48
22
R2829
1 2
19
19 27
27 87
0
402
5% 1/16W MF-LF
R2887
1 2
OMIT
0
5%
402
1/16W MF-LF
SILK_PART=SYS RESET
R2897
1
2
6
27 47 87 94
402
MF-LF
5% 1/16W
0
PLACE_NEAR=U2700.6
R2824
1 2
26 27
89
0
5%
MF-LF
1/16W
402
R2893
1 2
5%
402
1/16W MF-LF
10K
R2895
1
2
79 80 98
6
18 45
19 27 31 40
SOD-VESM-HF
SSM3K15FV
Q2830
3
1
2
6
18 33 27 37
MF-LF
1/16W 402
5%
10K
R2830
1
2
10 27
402
0
5%
MF-LF
1/16W
R2851
1 2
Chipset Support
SYNC_MASTER=K17_REF
SYNC_DATE=06/15/2009
PP3V3_S0
PP3V3_S5
PP3V3_S0
PM_SYSRST_L
PP3V3_S0
MAKE_BASE=TRUE
GMUX_RESET_L
BKLT_PLT_RST_L
PLT_RESET_L
MAKE_BASE=TRUE
GMUX_RESET_L
PCH_CLK32K_RTCX1
ENET_RESET_L
AP_RESET_L
LPCPLUS_RESET_L
MAKE_BASE=TRUE
LPCPLUS_RESET_L
PLT_RST_BUF_L
SDCARD_PLT_RST_L
PLT_RESET_L
PCA9557D_RESET_L
XDPPCH_PLTRST_L
MAKE_BASE=TRUE
PLT_RST_BUF_L
XDP_DBRESET_L
SMC_LRESET_L
LPC_CLK33M_SMC
LPC_CLK33M_LPCPLUS
PCH_CLK33M_PCIIN
MAKE_BASE=TRUE
GPU_CLK27M
CK505_CLK27M
MAKE_BASE=TRUE
LPC_CLK33M_GMUX_R
MAKE_BASE=TRUE
LPC_CLK33M_GMUX_R
PCH_CLK33M_PCIOUT
CK505_CLK27M
PCH_CLK25M_XTALIN
PCH_CLK32K_RTCX2_R
PCH_CLK25M_XTALOUT_R
BCM5764_CLK25M_XTALO_R
PCH_CLK32K_RTCX2
PCH_CLK25M_XTALOUT
BCM5764_CLK25M_XTALO
ENET_WAKE_LENET_WAKE_L
MAKE_BASE=TRUE
BCM5764_CLK25M_XTALI
PP3V3_ENET
LPC_CLK33M_GMUX
LPC_CLK33M_LPCPLUS_R
LPC_CLK33M_SMC_R
CPUIMVP_PGOOD
PCIE_WAKE_L
CPUIMVP_PGOOD_R
ALL_SYS_PWRGD
PM_PCH_PWRGD
28 OF 132
<E4LABEL>
<SCH_NUM>
<BRANCH>
27 OF 101
6 7
17 18 19 20 21 23 24 25
26 27 28 30 34 37 40 42 46 47
48 50 51 52 54 58 62 63 68 69
72 73 80 83 84 85 87 88 99
6 7
17 18 19 20 21 23 31 35
57 66 71 72 73 83 85 99
6 7
17 18 19 20 21 23 24 25
26 27 28 30 34 37 40 42 46 47
48 50 51 52 54 58 62 63 68 69
72 73 80 83 84 85 87 88 99
6 7
17 18 19 20 21 23 24 25
26 27 28 30 34 37 40 42 46 47
48 50 51 52 54 58 62 63 68 69
72 73 80 83 84 85 87 88 99
27 87
10 27
26 27
19 27
27 37
6 7
37 73
Page 28
A6
A7
A11
A5
DQ33
VDD
A10/AP
VDD
VSS
SA1
VTT
VSS
DQS4* DQS4
VSS
DQ35
VSS
CK0*
SA0
VSS DQ58 DQ59
DM7
VSS
DQ57
DQ56
DQ50 DQ51
VSS
DQS6* DQS6
VSS
DQ49
DQ48
DQ43
VSS
DM5
VSS DQ42
SDA SCL
VTT
VSS
EVENT*
DQ62
VSS
DQ63
DQS7*
DQS7
DQ60 DQ61
VSS
VSS
DQ55
DQ54
DM6
VSS
DQ53
VSS
DQ52
DQ47
VSS
DQS5
VSS
DQ46
DQ41
VSS DQ40
DQ34
VSS
DQ32
TEST
VDD
VDD
S1*
A13
CAS*
WE*
BA0
VDD
VDD CK0
A1
A3
VDD
VDD A8
A9
A12/BC*
VDD
BA2
NC
VDD
CKE0
VSS
DQS5*
VSS DQ44 DQ45
DQ39
DQ38
VSS
VSS
DM4
VSS
DQ37
DQ36
VREFCA
VDD ODT1
NC
S0*
ODT0
BA1
RAS*
VDD
CK1*
VDD
VDD
A0
CK1
A2
VDD
A4
VDD
VDD
A14
A15
CKE1
VDD
VSS
VDDSPD
KEY
(SYMBOL 2 OF 2)
BI BIBI
BI
IN
BI BI
BI BI
BI BI
IN
BI
IN
BI
BI BI
IN
BI BI
BI BI
BI BI
BI BI
DQ16
DM3
DQ26 DQ27
DQ4
DQ31
DQ30
DQS3
DQS3*
DQ29
DQ28
DQ23
DQ22
DM2
DQ21
DQ20
DQ15
DQ14
RESET*
DM1
DQ13
DQ12
DQ7
DQ6
DQS0
DQS0*
DQ5
DQ24 DQ25
DQ19
DQ18
DQS2
DQS2*
DQ17
DQ11
DQ10
DQS1
DQS1*
DQ8 DQ9
DM0
DQ0 DQ1
VREFDQ
DQ3
DQ2
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
KEY
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
(SYMBOL 1 OF 2)
IN
BI BI
BI BI
BI
BI
BI
BI
BI BI
BI
BI
IN IN
IN
IN
IN
IN
IN IN
IN IN
IN
IN
IN
IN
BI BI
BI BI
IN
BI BI
IN
BI
BI
IN
BI BI
BI
BI
BI
BI
BI
BI
BI
BI
IN
BI BI
BI BI
BI
BI
BI
BI
OUT
BI
IN
IN
IN
IN IN
IN IN
IN IN
IN IN
IN IN
IN IN
IN IN
BI BI
BI BI
BI BI
BI
IN
BI
BI BI
BI BI
BI BI
BI BI
IN
BI BI
BI BI
NC
NC
NC
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER
SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
516-0229
516-0229
"Factory" (top) slot
(NONE)
SPD ADDR=0xA0(WR)/0xA1(RD)
DDR3 DECOUPLING AND GND RETURN CAPS (SPACE EVENLY AT CONNECTOR)
BOM options provided by this page:
- =I2C_SODIMMA_SDA
- =I2C_SODIMMA_SCL
Signal aliases required by this page:
- =PPSPD_S0_MEM_A (2.5 - 3.3V)
- =PP0V75_S0_MEM_VTT_A
- =PP1V5_S3_MEM_A
- =PP1V5_S0_MEM_A
Power aliases required by this page:
Page Notes
F-RT-THB
DDR3-SODIMM-DUAL-K6
J2900
9897
107
8483
119
80
78
9695
9291
90
86
89
85
109
108
79
115
101 103
102 104
73 74
136
153
170
187
129 131
141 143
130 132
140 142
147 149
157 159
146 148
158 160
163 165
175 177
164 166
174 176
181 183
191 193
180 182
192 194
137
135
154
152
171
169
188
186
198
77
122
116
120
110
114
121
197
201 202
200
125
75 76
105 106
111 112
117 118
123 124
81 82
87 88
93 94
99
100
199
126
127 128
133 134
138
139
144
145
150
151
155 156
161 162
167 168
172
173
178
179
184
185
189 190
195 196
203 204
113
29
29
10V
20%
402
CERM
0.1UF
C2931
1
2
2.2UF
20%
402-LF
CERM
6.3V
C2930
1
2
29
29
11 92
11 29 92
11 29 92
29
29
29
29
29
29
30 31
29
29
29
29
29
29
29
29
29
29
29
29
F-RT-THB
DDR3-SODIMM-DUAL-K6
CRITICAL
J2900
11
28
46
63
5 7
33 35
22 24
34 36
39 41
51 53
15
40 42
50 52
57 59
67 69
56 58
17
68 70
4 6
16 18
21 23
12
10
29
27
47
45
64
62
30
1 2 3
31 32
37 38
43 44
48
49
54
55
8
60
61
65 66
71 72
9
13 14
19 20
25 26
11 29 92
29
29
29
29
29
29
29
29
29
29
29
29
11 92
11 92
11 92
11 92
11 92
11 92
11 92
11 92
11 92
11 92
11 92
11 92
11 92
11 92
29
29
29
29
29
29
29
11 92
11 29 92
29
29
29
29
29
29
29
29
29
0.1UF
CERM 402
20% 10V
C2936
1
2
CERM
2.2UF
6.3V
20%
402-LF
C2935
1
2
29
29
29
29
29
29
29
29
29
29
29
29
30 45 46
17 25 26 30 32 42 47 48 63 88 94
17 25 26 30 32 42 47 48 63 88 94
11 92
11 92
11 92
11 92
11 92
11 92
11 92
11 92
11 92
11 92
11 92
11 92
11 92
11 92
11 92
11 92
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
MF-LF
1/16W
402
5%
10K
R2941
1
2
402
5% 1/16W MF-LF
10K
R2940
1
2
6.3V
402-LF
CERM
20%
2.2UF
C2940
1
2
603
6.3V X5R
20%
10UF
C2900
1
2
20%
603
X5R
10UF
6.3V
C2901
1
2
0.1UF
20% 10V
402
CERM
C2910
1
2
10V
20% CERM
402
0.1UF
C2911
1
2
402
10V
20%
0.1UF
CERM
C2912
1
2
0.1UF
20% 10V CERM 402
C2913
1
2
0.1UF
20% CERM
402
10V
C2914
1
2
10V CERM 402
20%
0.1UF
C2915
1
2
CERM 402
20%
0.1UF
10V
C2916
1
2
CERM 402
20%
0.1UF
10V
C2917
1
2
CERM 402
20%
0.1UF
10V
C2918
1
2
CERM 402
20%
0.1UF
10V
C2919
1
2
0.1UF
CERM 402
20% 10V
C2920
1
2
CERM 402
20%
0.1UF
10V
C2921
1
2
CERM 402
20%
0.1UF
10V
C2922
1
2
CERM 402
20%
0.1UF
10V
C2923
1
2
SYNC_MASTER=MASTER
SYNC_DATE=MASTER
DDR3 SO-DIMM Connector A
PP1V5_S3
PP0V75_S3_MEM_VREFCA_A
=MEM_A_DQ<2> =MEM_A_DQ<3>
PP0V75_S3_MEM_VREFDQ_A
=MEM_A_DQ<1>
=MEM_A_DQ<0>
MEM_A_DM<0>
=MEM_A_DQ<9>
=MEM_A_DQ<8>
=MEM_A_DQS_N<1> =MEM_A_DQS_P<1>
=MEM_A_DQ<10> =MEM_A_DQ<11>
=MEM_A_DQ<17>
=MEM_A_DQS_N<2> =MEM_A_DQS_P<2>
=MEM_A_DQ<18> =MEM_A_DQ<19>
=MEM_A_DQ<25>
=MEM_A_DQ<24>
=MEM_A_DQ<5>
MEM_A_DQS_N<0> MEM_A_DQS_P<0>
=MEM_A_DQ<6> =MEM_A_DQ<7>
=MEM_A_DQ<12> =MEM_A_DQ<13>
=MEM_A_DM<1> MEM_RESET_L
=MEM_A_DQ<14> =MEM_A_DQ<15>
=MEM_A_DQ<20> =MEM_A_DQ<21>
=MEM_A_DM<2>
=MEM_A_DQ<22> =MEM_A_DQ<23>
=MEM_A_DQ<28> =MEM_A_DQ<29>
=MEM_A_DQS_N<3> =MEM_A_DQS_P<3>
=MEM_A_DQ<30> =MEM_A_DQ<31>
=MEM_A_DQ<4>
=MEM_A_DQ<26>
=MEM_A_DM<3>
=MEM_A_DQ<16>
PP3V3_S0
MEM_A_CKE<1>
MEM_A_A<15> MEM_A_A<14>
MEM_A_A<2>
MEM_A_CLK_P<1>
MEM_A_A<0>
MEM_A_CLK_N<1>
MEM_A_RAS_L
MEM_A_BA<1>
MEM_A_ODT<0>
MEM_A_CS_L<0>
MEM_A_ODT<1>
=MEM_A_DQ<36> MEM_A_DQ<37>
=MEM_A_DM<4>
=MEM_A_DQ<38> =MEM_A_DQ<39>
=MEM_A_DQ<45>
=MEM_A_DQ<44>
=MEM_A_DQS_N<5>
MEM_A_CKE<0>
MEM_A_BA<2>
MEM_A_A<12> MEM_A_A<9>
MEM_A_A<8>
MEM_A_A<3> MEM_A_A<1>
MEM_A_CLK_P<0>
MEM_A_BA<0>
MEM_A_WE_L MEM_A_CAS_L
MEM_A_A<13> MEM_A_CS_L<1>
=MEM_A_DQ<32>
=MEM_A_DQ<34>
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=MEM_A_DQ<46>
=MEM_A_DQS_P<5>
=MEM_A_DQ<47>
=MEM_A_DQ<52> =MEM_A_DQ<53>
=MEM_A_DM<6>
=MEM_A_DQ<54> =MEM_A_DQ<55>
=MEM_A_DQ<61>
=MEM_A_DQ<60>
=MEM_A_DQS_P<7>
=MEM_A_DQS_N<7>
=MEM_A_DQ<63>
=MEM_A_DQ<62>
MEM_EVENT_A_L
SMBUS_PCH_CLK
SMBUS_PCH_DATA
=MEM_A_DQ<42>
=MEM_A_DM<5>
=MEM_A_DQ<43>
=MEM_A_DQ<48> =MEM_A_DQ<49>
=MEM_A_DQS_P<6>
=MEM_A_DQS_N<6>
=MEM_A_DQ<51>
=MEM_A_DQ<50>
=MEM_A_DQ<56> =MEM_A_DQ<57>
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=MEM_A_DQ<59>
=MEM_A_DQ<58>
MEM_A_SA<0>
MEM_A_CLK_N<0>
=MEM_A_DQ<35>
=MEM_A_DQS_P<4>
=MEM_A_DQS_N<4>
PP0V75_S0_DDRVTT
MEM_A_SA<1>
MEM_A_A<10>
=MEM_A_DQ<33>
MEM_A_A<5>
MEM_A_A<11> MEM_A_A<7>
MEM_A_A<6>
=MEM_A_DQ<27>
MEM_A_A<4>
29 OF 132
<E4LABEL>
<SCH_NUM>
<BRANCH>
28 OF 101
6 7
30 31 67 72
32
32
6 7
17 18 19 20
21 23 24 25 26 27 30 34
37 40 42 46 47
48 50 51 52 54 58 62 63
68 69 72 73 80
83 84 85 87 88 99
6 7
30 31 67
Page 29
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER
SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
CPU CHANNEL B DQS 6 -> DIMM B DQS 6
CPU CHANNEL A DQS 5 -> DIMM A DQS 5
CPU CHANNEL A DQS 2 -> DIMM A DQS 2
CPU CHANNEL A DQS 3 -> DIMM A DQS 3
CPU CHANNEL A DQS 6 -> DIMM A DQS 6
CPU CHANNEL A DQS 7 -> DIMM A DQS 7
CPU CHANNEL A DQS 4 -> DIMM A DQS 4
CPU CHANNEL A DQS 1 -> DIMM A DQS 1
CPU CHANNEL B DQS 7 -> DIMM B DQS 7
CPU CHANNEL B DQS 0 -> DIMM B DQS 0
CPU CHANNEL B DQS 1 -> DIMM B DQS 1
CPU CHANNEL B DQS 2 -> DIMM B DQS 2
CPU CHANNEL A DQS 0 -> DIMM A DQS 0
CPU CHANNEL B DQS 5 -> DIMM B DQS 5
CPU CHANNEL B DQS 4 -> DIMM B DQS 4
CPU CHANNEL B DQS 3 -> DIMM B DQS 3
SYNC_DATE=MASTER
SYNC_MASTER=MASTER
DDR3 Byte/Bit Swaps
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MAKE_BASE=TRUE
MEM_B_DQ<16>
MAKE_BASE=TRUE
MEM_B_DQ<29>
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=MEM_B_DQ<33>
MAKE_BASE=TRUE
MEM_B_DQS_N<5>
MAKE_BASE=TRUE
MEM_B_DM<4>
MAKE_BASE=TRUE
MEM_B_DQ<24>
MAKE_BASE=TRUE
MEM_B_DQS_N<3>
MEM_B_DQS_N<0>
MAKE_BASE=TRUE
MEM_B_DQS_P<0>
MAKE_BASE=TRUE
MEM_B_DM<0>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MEM_B_DQ<23>
MAKE_BASE=TRUE
MEM_B_DQ<22>
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MAKE_BASE=TRUE
MEM_B_DM<3>
MEM_B_DQS_P<3>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MEM_B_DQ<19>
MEM_B_DQ<8>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MEM_B_DQ<12>
MEM_B_DQ<9>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MEM_B_DQS_N<2>
MAKE_BASE=TRUE
MEM_B_DQ<15>
MEM_B_DM<1>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MEM_B_DQS_P<2> MEM_B_DM<2>
MAKE_BASE=TRUE
=MEM_B_DQ<18>
MAKE_BASE=TRUE
MEM_B_DQ<21>
MAKE_BASE=TRUE
MEM_B_DQ<20>
=MEM_B_DQS_P<2>
MAKE_BASE=TRUE
MEM_B_DQ<14>
MAKE_BASE=TRUE
MEM_B_DQ<1>
MAKE_BASE=TRUE
MEM_B_DQS_N<1>
=MEM_B_DM<1>
=MEM_B_DM<2>
MEM_B_DQ<4>
MAKE_BASE=TRUE
MEM_B_DQ<3>
MAKE_BASE=TRUE
MEM_B_DQ<2>
MAKE_BASE=TRUE
MEM_B_DQS_P<1>
MAKE_BASE=TRUE
MEM_B_DQS_N<0>
MAKE_BASE=TRUE
MEM_B_DQ<0>
MEM_B_DM<0> =MEM_B_DQ<7> =MEM_B_DQ<6>
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MAKE_BASE=TRUE
MEM_B_DQ<7>
MAKE_BASE=TRUE
MEM_B_DQ<6>
=MEM_B_DQ<24>
=MEM_B_DQ<28>
MEM_A_DQ<4>
MAKE_BASE=TRUE
=MEM_B_DQ<12>
MAKE_BASE=TRUE
MEM_B_DQ<56>
=MEM_B_DQ<61>
MAKE_BASE=TRUE
MEM_B_DQ<58>
MAKE_BASE=TRUE
MEM_B_DQ<57>
=MEM_B_DQ<60>
MAKE_BASE=TRUE
MEM_B_DQ<59>
=MEM_B_DQ<59>
MAKE_BASE=TRUE
MEM_B_DQ<61>
=MEM_B_DQ<57>
MAKE_BASE=TRUE
MEM_B_DQ<60>
=MEM_B_DQ<56>
MAKE_BASE=TRUE
MEM_B_DQ<63>
=MEM_B_DQ<63>
MAKE_BASE=TRUE
MEM_B_DM<7>
=MEM_B_DM<7>
MAKE_BASE=TRUE
MEM_B_DQ<62>
=MEM_B_DQ<62>
MAKE_BASE=TRUE
MEM_B_DQS_N<7>
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MAKE_BASE=TRUE
MEM_B_DQS_P<7>
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MAKE_BASE=TRUE
MEM_B_DQ<48>
MAKE_BASE=TRUE
MEM_B_DQ<49>
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MAKE_BASE=TRUE
MEM_B_DQ<50>
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MAKE_BASE=TRUE
MEM_B_DQ<51>
=MEM_B_DQ<49>
MAKE_BASE=TRUE
MEM_B_DQ<52>
=MEM_B_DQ<53>
MAKE_BASE=TRUE
MEM_B_DQ<53>
MAKE_BASE=TRUE
MEM_B_DQ<54>
=MEM_B_DQ<55>
=MEM_B_DM<6>
MAKE_BASE=TRUE
MEM_B_DQ<55>
=MEM_B_DQ<50>
MAKE_BASE=TRUE
MEM_B_DQS_P<6>
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MEM_B_DQS_N<6>
MAKE_BASE=TRUE
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MEM_B_DQ<41>
MAKE_BASE=TRUE
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MAKE_BASE=TRUE
MEM_B_DQ<40>
MAKE_BASE=TRUE
MEM_B_DQ<43>
MEM_B_DQ<44>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MEM_B_DQ<46>
MAKE_BASE=TRUE
MEM_B_DM<5>
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MAKE_BASE=TRUE
MEM_B_DQS_P<5>
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MAKE_BASE=TRUE
MEM_B_DQ<32>
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MAKE_BASE=TRUE
MEM_B_DQ<33>
MAKE_BASE=TRUE
MEM_B_DQ<36>
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MAKE_BASE=TRUE
MEM_B_DQ<35>
MAKE_BASE=TRUE
MEM_B_DQ<34>
MAKE_BASE=TRUE
MEM_B_DQ<37> MEM_B_DQ<37>
MEM_B_DQ<38>
MAKE_BASE=TRUE
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MEM_B_DQS_P<4>
MAKE_BASE=TRUE
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MAKE_BASE=TRUE
MEM_B_DQ<39>
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MAKE_BASE=TRUE
MEM_B_DQS_N<4>
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MAKE_BASE=TRUE
MEM_B_DQ<25>
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MAKE_BASE=TRUE
MEM_B_DQ<27>
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MAKE_BASE=TRUE
MEM_B_DQ<26>
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MEM_B_DQ<31>
MAKE_BASE=TRUE
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MEM_B_DQ<17>
MAKE_BASE=TRUE
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MEM_B_DQ<18>
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MEM_B_DQ<10>
MAKE_BASE=TRUE
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MEM_B_DQ<11>
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MEM_B_DQS_P<0>
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MEM_A_DM<0>
MEM_A_DQS_P<0>
MAKE_BASE=TRUE
MEM_A_DM<0>
MAKE_BASE=TRUE
MEM_A_DQS_N<0> MEM_A_DQS_P<0>
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MEM_A_DQ<1>
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MAKE_BASE=TRUE
MEM_A_DQ<11>
MEM_A_DQ<5>
MAKE_BASE=TRUE
MEM_A_DQ<6>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MEM_A_DQ<7>
MEM_A_DQ<2>
MAKE_BASE=TRUE
MEM_A_DQ<14>
MAKE_BASE=TRUE
MEM_A_DQ<13>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MEM_A_DQ<8>
MEM_A_DQS_N<1>
MAKE_BASE=TRUE
MEM_A_DQ<9>
MAKE_BASE=TRUE
MEM_A_DQ<10>
MAKE_BASE=TRUE
MEM_A_DQ<12>
MAKE_BASE=TRUE
MEM_A_DQ<15>
MAKE_BASE=TRUE
MEM_A_DQS_P<1>
MAKE_BASE=TRUE
MEM_A_DM<1>
MAKE_BASE=TRUE
MEM_A_DQ<0>
MAKE_BASE=TRUE
MEM_A_DQ<3>
MAKE_BASE=TRUE
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MEM_A_DQ<17>
MAKE_BASE=TRUE
MEM_A_DQ<29>
MAKE_BASE=TRUE
MEM_A_DQS_P<3>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MEM_A_DQS_N<3>
MEM_A_DQ<16>
MAKE_BASE=TRUE
MEM_A_DQ<19>
MAKE_BASE=TRUE
MEM_A_DQ<20>
MAKE_BASE=TRUE
MEM_A_DQ<23>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MEM_A_DQS_N<2>
MEM_A_DQS_P<5>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MEM_A_DQS_N<5>
MEM_A_DQ<33>
MAKE_BASE=TRUE
MEM_A_DQ<32>
MAKE_BASE=TRUE
MEM_A_DQ<36>
MAKE_BASE=TRUE
MEM_A_DQ<38>
MAKE_BASE=TRUE
MEM_A_DQ<37>
MAKE_BASE=TRUE
MEM_A_DQS_P<4>
MAKE_BASE=TRUE
MEM_A_DM<4>
MAKE_BASE=TRUE
MEM_A_DQS_N<4>
MAKE_BASE=TRUE
MEM_A_DQ<27>
MAKE_BASE=TRUE
MEM_A_DQ<26>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MEM_A_DQ<49>
MAKE_BASE=TRUE
MEM_A_DQ<51> MEM_A_DQ<50>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MEM_A_DQ<54>
MAKE_BASE=TRUE
MEM_A_DQ<52>
MEM_A_DQ<55>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MEM_A_DM<6>
MEM_A_DQS_P<6>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MEM_A_DQ<40>
MEM_A_DQ<41>
MAKE_BASE=TRUE
MEM_A_DQ<42>
MAKE_BASE=TRUE
MEM_A_DQ<44>
MAKE_BASE=TRUE
MEM_A_DM<5>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MEM_A_DQ<48>
MAKE_BASE=TRUE
MEM_A_DQ<63>
MEM_A_DQ<59>
MAKE_BASE=TRUE
MEM_A_DQ<58>
MAKE_BASE=TRUE
MEM_A_DQ<56>
MAKE_BASE=TRUE
MEM_A_DQ<57>
MAKE_BASE=TRUE
MEM_A_DQ<60>
MAKE_BASE=TRUE
MEM_A_DQ<61>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MEM_A_DM<7>
MEM_A_DQ<62>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MEM_A_DQS_P<7>
MEM_A_DQ<53>
MAKE_BASE=TRUE
MEM_A_DQS_N<0>
MAKE_BASE=TRUE
MEM_B_DQ<28>
MEM_A_DQS_P<2>
MAKE_BASE=TRUE
MEM_A_DM<2>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MEM_A_DQ<22> MEM_A_DQ<21>
MAKE_BASE=TRUE
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MEM_A_DQ<30>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MEM_B_DM<6>
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MAKE_BASE=TRUE
MEM_B_DQ<30>
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MEM_A_DQ<18>
MAKE_BASE=TRUE
MEM_A_DQS_N<7>
MAKE_BASE=TRUE
MEM_A_DQS_N<6>
MAKE_BASE=TRUE
MEM_A_DQ<46>
MAKE_BASE=TRUE
MEM_A_DQ<45>
MAKE_BASE=TRUE
MEM_A_DQ<43>
MAKE_BASE=TRUE
MEM_A_DQ<34>
MAKE_BASE=TRUE
MEM_A_DQ<28>
MAKE_BASE=TRUE
MEM_A_DQ<31>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MEM_A_DM<3>
MEM_A_DQ<25>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MEM_B_DQ<45>
MAKE_BASE=TRUE
MEM_B_DQ<13>
MAKE_BASE=TRUE
MEM_B_DQ<5>
MEM_A_DQ<39>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MEM_A_DQ<24>
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MEM_A_DQ<35>
MAKE_BASE=TRUE
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MEM_A_DQ<47>
MAKE_BASE=TRUE MAKE_BASE=TRUE
MEM_B_DQ<47>
MEM_B_DQ<42>
MAKE_BASE=TRUE
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30 OF 132
<E4LABEL>
<SCH_NUM>
<BRANCH>
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Page 30
IN
BI
BI BI
OUT
BI IN
IN
IN
IN IN
IN IN
IN
IN IN
IN IN
IN IN
IN IN
BI BI
BI BI
BI BI
BI
IN
BI BI
BI BI
BI BI
BI BI
IN
BI BI
BI BI
BI BI
NC
NC
NC
IN
VDD
A1
A3
VDD
A5
A8
VDD
A9
VDD
A12/BC*
VSS
DQ42 DQ43
DQ48 DQ49
VSS
VSS
DQ41
DQS4*
DM5
VDD
CKE1
A15 A14
VDD
A11
A7
A6
VDD
A4
A2
CK1
A0
VDD
VDD
CK1*
VDD
RAS*
BA1
ODT0
S0*
NC
ODT1
VDD
VREFCA
VDD
DQ36 DQ37
VSS
DM4
VSS
VSS DQ38 DQ39
DQ45
DQ44
VSS
DQS5*
VSS
CKE0
VDD NC
BA2
CK0
VDD
BA0
WE*
A13 S1*
VDD
VDD
TEST
DQ33
DQ32
VSS
DQ34
DQ40
VSS
DQ46
VSS
DQS5
VSS
DQ47
DQ52
VSS
DQ53
VSS
DM6
DQ54 DQ55
VSS
VSS
DQ61
DQ60
DQS7
DQS7*
DQ63
VSS DQ62
EVENT*
VSS
VTT
SCL
SDA
VSS
DQS6
DQS6*
VSS
DQ51
DQ50
A10/AP
VDD
CK0*
DQ35
VSS
DQS4
VSS
CAS*
VDD
DM7
VSS
DQ56
MTG PIN
MTG PIN MTG PIN MTG PIN MTG PIN
MTG PIN
MTG PIN
VSS
DQ57
VTT
SA1
SA0
DQ58
VSS
DQ59
VSS
VDDSPD
MTG PIN
MTG PINS
KEY
(2 OF 2)
BI BI
BI BI
BI BI
IN
BI
IN
BI
BI
BI BI
IN
BI BI
BI BI
BI BI
BI
BI
BI
DQ2 DQ3
VREFDQ
DQ1
DQ0
DM0
DQ9
DQ8
DQS1* DQS1
DQ10 DQ11
DQ17
DQS2* DQS2
DQ18 DQ19
DQ25
DQ24
DQ5
DQS0*
DQS0
DQ6 DQ7
DQ12 DQ13
DM1
RESET*
DQ14 DQ15
DQ20 DQ21
DM2
DQ22 DQ23
DQ28 DQ29
DQS3*
DQS3
DQ30 DQ31
DQ4
DQ27
DQ26
DM3
DQ16
(1 OF 2)
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
KEY
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
IN
BI BI
BI BI
BI
BI
BI
BI
BI
BI BI
BI BI
IN IN
IN
BI
IN
IN IN
IN IN
IN IN
IN IN
IN IN
BI BI
BI BI
IN
BI BI
IN
BI BI
IN
BI
BI BI
BI BI
BI BI
BI BI
BI
IN
BI
BI BI
BI
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER
SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
Page Notes
- =PP1V5_S0_MEM_B
SPD ADDR=0xA4(WR)/0xA5(RD)
516S0806
516S0806
- =PP0V75_S0_MEM_VTT_B
- =PPSPD_S0_MEM_B (2.5 - 3.3V)
- =PP1V5_S3_MEM_B
"Expansion" (bottom) slot
Signal aliases required by this page:
- =I2C_SODIMMB_SDA
BOM options provided by this page:
(NONE)
DDR3 DECOUPLING AND GND RETURN CAPS (SPACE EVENLY AT CONNECTOR)
- =I2C_SODIMMB_SCL
Power aliases required by this page:
11 92
29
29
29
28 45 46
17 25 26 28 32 42 47 48 63 88 94
17 25 26 28 32 42 47 48 63 88 94
10V
20%
402
CERM
0.1UF
C3131
1
2
11 92
11 92
11 92
11 92
11 92
11 92
11 92
11 92
11 92
11 92
11 92
11 92
11 92
11 92
11 92
29
29
29
29
11 29 92
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
CERM 402-LF
6.3V
20%
2.2UF
C3130
1
2
5%
MF-LF 402
10K
1/16W
R3141
1
2
MF-LF
1/16W
402
5%
10K
R3140
1
2
2.2UF
6.3V
402-LF
CERM
20%
C3140
1
2
603
6.3V X5R
20%
10UF
C3100
1
2
20%
603
X5R
10UF
6.3V
C3101
1
2
0.1UF
20% 10V
402
CERM
C3110
1
2
20% 10V CERM 402
0.1UF
C3111
1
2
402
10V
20%
0.1UF
CERM
C3112
1
2
20% 10V
0.1UF
402
CERM
C3113
1
2
29
20% CERM
402
10V
0.1UF
C3114
1
2
402
20%
0.1UF
CERM
10V
C3115
1
2
CERM 402
20%
0.1UF
10V
C3116
1
2
CERM 402
20%
0.1UF
10V
C3117
1
2
CERM 402
20%
0.1UF
10V
C3118
1
2
CERM 402
20%
0.1UF
10V
C3119
1
2
0.1UF
CERM 402
20% 10V
C3120
1
2
CERM 402
20%
0.1UF
10V
C3121
1
2
CERM 402
20%
0.1UF
10V
C3122
1
2
CERM 402
20%
0.1UF
10V
C3123
1
2
29
11 92
F-RT-BGA6
DDR3-SODIMM
J3100
9897
107
8483
119
80
78
9695
9291
90
86
89
85
109
108
79
115
101 103
102 104
73 74
136
153
170
187
129 131
141 143
130 132
140 142
147 149
157 159
146 148
158 160
163 165
175 177
164 166
174 176
181 183
191 193
180 182
192 194
137
135
154
152
171
169
188
186
198
77
122
116
120
110
114
121
197
201 202
200
125
75 76
105 106
111 112
117 118
123 124
81 82
87 88
93 94
99
100
199
126
127 128
133 134
138
139
144
145
150
151
155 156
161 162
167 168
172
173
178
179
184
185
189 190
195 196
205 206 207 208 209 210 211 212
203 204
113
11 29 92
11 29 92
29
29
29
29
29
29
28 31
29
29
29
29
29
29
29
29
29
29
29
29
29
29
F-RT-BGA6
DDR3-SODIMM
CRITICAL
J3100
11
28
46
63
5 7
33 35
22 24
34 36
39 41
51 53
15
40 42
50 52
57 59
67 69
56 58
17
68 70
4 6
16 18
21 23
12
10
29
27
47
45
64
62
30
1 2 3
31 32
37 38
43 44
48
49
54
55
8
60
61
65 66
71 72
9
13 14
19 20
25 26
11 29 92
29
29
29
29
29
29
29
29
29
29
29
29
29
11 92
11 92
11 92
29
11 92
11 92
11 92
11 92
11 92
11 92
11 92
11 92
11 92
11 92
11 92
29
29
29
29
29
29
29
11 92
29
29
29
29
29
29
29
29
29
CERM 402
10V
0.1UF
20%
C3136
1
2
2.2UF
6.3V CERM
20%
402-LF
C3135
1
2
29
29
29
29
29
29
29
29
29
DDR3 SO-DIMM Connector B
SYNC_DATE=MASTER
SYNC_MASTER=MASTER
PP3V3_S0
MEM_B_SA<0>
PP0V75_S0_DDRVTT
=MEM_B_DM<5>
=MEM_B_DQS_P<4>
MEM_B_DQ<37>
=MEM_B_DQ<62>
=MEM_B_DQ<50>
=MEM_B_DQ<16>
=MEM_B_DM<3>
=MEM_B_DQ<26> =MEM_B_DQ<27>
=MEM_B_DQ<4>
=MEM_B_DQ<31>
=MEM_B_DQ<30>
=MEM_B_DQS_P<3>
=MEM_B_DQS_N<3>
=MEM_B_DQ<29>
=MEM_B_DQ<28>
=MEM_B_DQ<23>
=MEM_B_DQ<22>
=MEM_B_DM<2>
=MEM_B_DQ<21>
=MEM_B_DQ<20>
=MEM_B_DQ<15>
=MEM_B_DQ<14>
MEM_RESET_L
=MEM_B_DM<1>
=MEM_B_DQ<12>
=MEM_B_DQ<7>
=MEM_B_DQ<6>
MEM_B_DQS_P<0>
MEM_B_DQS_N<0>
=MEM_B_DQ<5>
=MEM_B_DQ<24> =MEM_B_DQ<25>
=MEM_B_DQ<19>
=MEM_B_DQ<18>
=MEM_B_DQS_P<2>
=MEM_B_DQS_N<2>
=MEM_B_DQ<17>
=MEM_B_DQ<11>
=MEM_B_DQ<10>
=MEM_B_DQS_P<1>
=MEM_B_DQS_N<1>
=MEM_B_DQ<8> =MEM_B_DQ<9>
MEM_B_DM<0>
=MEM_B_DQ<0> =MEM_B_DQ<1>
PP0V75_S3_MEM_VREFDQ_B
=MEM_B_DQ<3>
=MEM_B_DQ<2>
=MEM_B_DQ<58>
MEM_B_SA<1>
=MEM_B_DQ<57>
=MEM_B_DQ<56>
=MEM_B_DM<7>
MEM_B_CAS_L
=MEM_B_DQ<35>
MEM_B_CLK_N<0>
MEM_B_A<10>
=MEM_B_DQ<51>
=MEM_B_DQS_N<6> =MEM_B_DQS_P<6>
SMBUS_PCH_DATA SMBUS_PCH_CLK
MEM_EVENT_A_L
=MEM_B_DQ<63>
=MEM_B_DQS_N<7> =MEM_B_DQS_P<7>
=MEM_B_DQ<60> =MEM_B_DQ<61>
=MEM_B_DQ<55>
=MEM_B_DQ<54>
=MEM_B_DM<6>
=MEM_B_DQ<53>
=MEM_B_DQ<52>
=MEM_B_DQ<47>
=MEM_B_DQS_P<5>
=MEM_B_DQ<46>
=MEM_B_DQ<40>
=MEM_B_DQ<32> =MEM_B_DQ<33>
MEM_B_CS_L<1>
MEM_B_A<13>
MEM_B_WE_L
MEM_B_BA<0>
MEM_B_CLK_P<0>
MEM_B_BA<2>
MEM_B_CKE<0>
=MEM_B_DQS_N<5>
=MEM_B_DQ<44> =MEM_B_DQ<45>
=MEM_B_DQ<39>
=MEM_B_DQ<38>
=MEM_B_DM<4>
=MEM_B_DQ<37>
=MEM_B_DQ<36>
PP0V75_S3_MEM_VREFCA_B
MEM_B_CS_L<0>
MEM_B_BA<1>
MEM_B_CLK_N<1>
MEM_B_A<0>
MEM_B_A<2>
MEM_B_A<4>
MEM_B_A<6>
MEM_B_A<7>
MEM_B_A<11>
MEM_B_A<14>
MEM_B_A<15>
MEM_B_CKE<1>
=MEM_B_DQS_N<4>
=MEM_B_DQ<41>
=MEM_B_DQ<49>
=MEM_B_DQ<48>
=MEM_B_DQ<43>
=MEM_B_DQ<42>
MEM_B_A<12> MEM_B_A<9>
MEM_B_A<8> MEM_B_A<5>
MEM_B_A<1>
PP1V5_S3
=MEM_B_DQ<13>
=MEM_B_DQ<59>
MEM_B_ODT<0>
MEM_B_RAS_L
MEM_B_CLK_P<1>
MEM_B_ODT<1>
MEM_B_A<3>
31 OF 132
<E4LABEL>
<SCH_NUM>
<BRANCH>
30 OF 101
6 7
17 18 19 20 21
23 24 25 26 27 28 34 37 40
42 46 47 48 50 51
52 54 58 62 63 68 69 72 73
80 83 84 85 87 88
99
6 7
28 31 67
32
32
6 7
28 31 67 72
Page 31
IN IN
IN
OUT
OUT
D
SG
D
S G
D
SG
D
S G
D
SG
D
S G
D
S G
D
SG
OUT
IN
IN
D
SG
D
SG
IN
G
D
S
OUT
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER
SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
The circuit below handles CPU and VTT power during S0->S3->S0 transitions, as well
WHEN HIGH: CPU 1.5V remains powered in S3, VTT follows S0 rails, MEM_RESET_L not isolated.
1V5 S0 "PGOOD" for CPU
MEMVTT Clamp
as isolating the CPU’s SM_DRAMRST# output from the SO-DIMMs when necessary. ISOLATE_CPU_MEM_L GPIO state during S3<->S0 transitions determines behavior of signals.
PM_MEM_PWRGD pull-up to CPU VTT rail is on CPU page
MEMVTT_EN = (ISOLATE_CPU_MEM_L + PLT_RST_L) * PM_SLP_S3_L
75mA max load @ 0.75V
WHEN LOW: CPU 1.5V follows S0 rails, VTT ensures clean CKE transition, MEM_RESET_L isolated.
MEM_RESET_L = !ISOLATE_CPU_MEM_L + CPU_MEM_RESET_L
7 1 1 1 1 1 CPU_MEM_RESET_L 1 1
6 0 1 1 1 1 1 1 1
5 0 1 1 1 0 (*) 1 1 1
4 0 0 1 1 X 1 0 1
3 0 0 0 1 X 1 0 0
2 0 0 1 1 1 1 0 1
0 1 1 1 1 1 CPU_MEM_RESET_L 1 1
Step ISOLATE_CPU_MEM_L PLT_RESET_L PM_SLP_S3_L PM_SLP_S4_L CPU_MEM_RESET_L MEM_RESET_L MEMVTT_EN P1V5CPU_EN
1 0 1 1 1 1 1 1 1
(*) CPU_MEM_RESET_L asserts due to loss of PM_MEM_PWRGD, must wait for software to clear before deasserting ISOLATE_CPU_MEM_L GPIO.
NOTE: In the event of a S3->S5 transition ISOLATE_CPU_MEM_L will still be asserted on next S5->S0 transition. Rails will power-up as if from S3, but MEM_RESET_L will not properly assert. Software must deassert ISOLATE_CPU_MEM_L and then generate a valid reset cycle on CPU_MEM_RESET_L.
P1V5CPU_EN = (ISOLATE_CPU_MEM_L + PM_SLP_S3_L) * PM_SLP_S4_L
S0
to
S3
to
S0
60mW max power
Ensures CKE signals are held low in S3
20 25
6
18 45 73 85
19 27 40
1/16W
5%
MF-LF
CPUMEM_S0
100K
402
R3202
1
2
8
31 67
10K
1/16W
5%
402
MF-LF
CPUMEM_S0
R3210
1
2
CPUMEM_S0
100K
MF-LF
402
5%
1/16W
R3215
1
2
28 30
CPUMEM_S0
20K
MF-LF 402
5% 1/16W
R3216
1
2
SOT563
SSM6N15FEAPE
CPUMEM_S0
Q3200
3
5
4
SOT563
CPUMEM_S0
SSM6N15FEAPE
Q3205
3
5
4
SOT563
CPUMEM_S0
SSM6N15FEAPE
Q3210
6
2
1
SSM6N15FEAPE
CPUMEM_S0
SOT563
Q3210
3
5
4
SOT563
SSM6N15FEAPE
CPUMEM_S0
Q3200
6
2
1
SOT563
SSM6N15FEAPE
CPUMEM_S0
Q3215
6
2
1
CPUMEM_S0
SSM6N15FEAPE
SOT563
Q3215
3
5
4
SOT563
SSM6N15FEAPE
CPUMEM_S0
Q3205
6
2
1
72
10K
1/16W
5%
402
MF-LF
CPUMEM_S0
R3205
1
2
18 43 45 46 72 73
100K
5%
402
MF-LF
CPUMEM_S0
1/16W
R3201
1
2
8
31 67
SSM6N15FEAPE
SOT563
CPUMEM_S0
Q3250
3
5
4
1/16W MF-LF
5%
100K
402
CPUMEM_S0
R3251
1
2
402
NO STUFF
50V
0.001UF
20%
CERM
C3251
1
2
SSM6N15FEAPE
SOT563
CPUMEM_S0
Q3250
6
2
1
MF-LF
10
5%
603
1/10W
CPUMEM_S0
R3250
1
2
MF-LF
1/16W
5%
402
0
CPUMEM_S3
R3217
1 2
10 31
MF-LF
1%
33.2K
402
1/16W
R3221
1
2
402
27.4K
1% 1/16W MF-LF
R3220
1
2
SOT-563
DMB53D0UV
CRITICAL
Q3220
5
3
4
MF-LF
1/16W
5%
10K
402
R3222
1
2
SOT-563
CRITICAL
DMB53D0UV
Q3220
6
2
1
10 18 91
CERM
NO STUFF
402
50V
20%
0.001UF
C3220
1
2
SYNC_MASTER=K17_REF
SYNC_DATE=06/15/2009
CPU Memory S3 Support
CPU_MEM_RESET_L CPU_MEM_RESET_L
MAKE_BASE=TRUE
MEM_RESET_L
PP1V5_S3
PLT_RESET_L
MEMVTT_EN
PM_SLP_S3_L
P1V5CPU_EN
P1V5CPU_EN_L
PP0V75_S0_DDRVTT
VTTCLAMP_L
VTTCLAMP_EN
PP5V_S3
MEMVTT_EN
MEMVTT_EN_L
MEMRESET_ISOL_LS5V_L
ISOLATE_CPU_MEM_L
PP5V_S3
PM_SLP_S4_L
PP3V3_S3
PP1V5_S3RS0
PP3V3_S5
PM_MEM_PWRGD_L
PM_MEM_PWRGD
P1V5_S0_DIV
32 OF 132
<E4LABEL>
<SCH_NUM>
<BRANCH>
31 OF 101
6 7
28 30 67 72
6 7
28 30 67
6 7
31 33 42 43 44 46 54 56 58 61 66 67
72 82
101
6 7
31 33 42 43 44 46 54 56 58 61 66 67
72 82
101
6 7 8
17 20 32 33 34 35 36 48 50 53 54
55 72 73 87
101
6 7
13 16 42 72 73 99
6 7
17 18 19 20 21 23 27 35
57 66 71 72 73 83 85 99
Page 32
OUT
OUT
OUT
V-
V+
V-
V+
V-
V+
V-
V+
V-
V+
V-
V+
IN
RESET*
A0 A1 A2
SCL SDA
P0 P1 P2
P5 P6 P7
P3 P4
THRM
VCC
GND
PAD
NC
NC
IN
BI
VDD
VOUTD
VOUTC
VOUTB
VOUTA
SCL
SDA
A0
A1
GND
IN
BI
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER
SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
DESCRIPTION
REFERENCE DES
BOM OPTION
QTY
PART NUMBER
CRITICAL
1.056V - 1.442V (+/- 180mV)
1.51mV / step @ output
+33uA - -33uA (- = sourced) +6.0mA - -5.0mA (- = sourced)
0.000V - 3.300V (0x00 - 0xFF)
1.267V (DAC: 0x8B)
6
D
GPU Frame Buffer (1.8V, 70% VRef)
0.75V (DAC: 0x3A) 1.5V (DAC: 0x3A)
MEM B VREF CA
NOTE: Must not enable more than two SO-DIMM margining buffers at once or VRef source may be overloaded.
0.000V - 1.501V (0x00 - 0x74)
1.998V - 1.002V (+/- 498mV)
8.59mV / step @ output
MEM VREG
5
D
DAC Channel: PCA9557D Pin:
DAC range:
Nominal value
DAC step size:
VRef current:
Margined target:
MEM A VREF DQ
B 21
A
MEM B VREF DQ
0.300V - 1.200V (+/- 450mV)
+3.4mA - -3.4mA (- = sourced)
0.000V - 1.501V (0x00 - 0x74)
7.69mV / step @ output
C 3
MEM A VREF CA
4
C
- =PP3V3_S3_VREFMRGN
- =I2C_VREFDACS_SCL
- =I2C_VREFDACS_SDA
- =I2C_PCA9557D_SCL
- =I2C_PCA9557D_SDA
Circuitry.
Circuitry.
- =PPVTT_S3_DDR_BUF
Page Notes
Power aliases required by this page:
BOM options provided by this page: VREFMRGN - Stuffs VREF Margining
VREFMRGN_NOT - Bypasses VREF Margining
Signal aliases required by this page:
10mA max load
Required zero ohm resistors when no VREF margining circuit stuffed
RST* on ’platform reset’ so that system watchdog will disable margining.
NOTE: Margining will be disabled across all soft-resets and sleep/wake cycles.
Addr=0x30(WR)/0x31(RD)
both at the same time!
NOTE: MEMVREG and FRAMEBUF share a DAC output, cannot enable
(OD)
Addr=0x98(WR)/0x99(RD)
8
77
VREFMRGN
1/16W
1%
402
MF-LF
49.9
PLACE_NEAR=R0900.2:1mm
R3316
1 2
67
VREFMRGN
0.1UF
CERM
402
20% 10V
C3302
1
2
22.6K
VREFMRGN
1/16W
1%
402
MF-LF
PLACE_NEAR=R7320.2:1mm
R3314
1 2
402
MF-LF
1/16W
5%
100K
VREFMRGN
R3313
1
2
VREFMRGN
5% 1/16W MF-LF 402
100K
R3315
1
2
8
78
VREFMRGN
1/16W
1%
402
MF-LF
49.9
PLACE_NEAR=R0901.2:1mm
R3317
1 2
VREFMRGN MAX4253
UCSP
U3302
C3
C2
C1
C4
B1
B4
VREFMRGN
UCSP
MAX4253
U3303
A3
A2
A1
A4
B1
B4
MAX4253
UCSP
VREFMRGN
U3302
A3
A2
A1
A4
B1
B4
UCSP
MAX4253
VREFMRGN
U3303
C3
C2
C1
C4
B1
B4
VREFMRGN
UCSP
MAX4253
U3304
A3
A2
A1
A4
B1
B4
VREFMRGN
UCSP
MAX4253
U3304
C3
C2
C1
C4
B1
B4
PLACE_NEAR=J2900.126:2.54mm
1/16W
1%
402
MF-LF
200
VREFMRGN
R3309
1 2
PLACE_NEAR=J3100.126:2.54mm
200
MF-LF
402
1%
1/16W
VREFMRGN
R3311
1 2
SHORT
NONE
402
NONE NONE
OMIT
R3318
1 2
NONE
402
NONE
SHORT
NONE
OMIT
R3319
1 2
27
200
MF-LF
402
1%
1/16W
VREFMRGN
PLACE_NEAR=J2900.1:2.54mm
R3303
1 2
133
PLACE_NEAR=R3303.2:1mm
1/16W
1%
402
MF-LF
VREFMRGN
R3304
1 2
VREFMRGN
200
MF-LF
402
1%
1/16W
PLACE_NEAR=J3100.1:2.54mm
R3305
1 2
133
PLACE_NEAR=R3305.2:1mm
VREFMRGN
1/16W
1%
MF-LF
402
R3306
1 2
5% 1/16W MF-LF 402
VREFMRGN
100K
R3302
1
2
MF-LF
1/16W
5%
100K
402
VREFMRGN
R3301
1
2
133
PLACE_NEAR=R3309.2:1mm
VREFMRGN
MF-LF
402
1%
1/16W
R3310
1 2
402
MF-LF
1/16W
5%
100K
VREFMRGN
R3307
1
2
PCA9557
QFN
VREFMRGN
CRITICAL
U3301
3 4 5
8
6 7 9 10 11 12 13 14
15
1 2
17
16
VREFMRGN
0.1UF
CERM
402
20% 10V
C3304
1
2
133
MF-LF
402
1%
VREFMRGN
1/16W
PLACE_NEAR=R3311.2:1mm
R3312
1 2
MF-LF 402
1/16W
100K
5%
VREFMRGN
R3308
1
2
17 25 26 28 30 32 42 47 48 63 88 94
17 25 26 28 30 32 42 47 48 63 88 94
CRITICAL
MSOP
DAC5574
VREFMRGN
U3300
9
10
3
6
7
8
1
2
4
5
17 25 26 28 30 32 42 47 48 63 88 94
17 25 26 28 30 32 42 47 48 63 88 94
10V
20% 402
CERM
0.1UF
VREFMRGN
C3301
1
2
6.3V
20%
402-LF
CERM
2.2UF
VREFMRGN
C3300
1
2
VREFMRGN
0.1UF
CERM
402
10V
20%
C3305
1
2
VREFMRGN
402
CERM
20% 10V
0.1UF
C3303
1
2
CRITICAL116S0004
RES,MTL FILM,0,5%,0402,SM,LF
R3303,R3305
2
VREFMRGN_NOT
CRITICAL116S0004
RES,MTL FILM,0,5%,0402,SM,LF
R3309,R3311
2
VREFMRGN_NOT
SYNC_DATE=06/15/2009
SYNC_MASTER=K17_REF
FSB/DDR3/FRAMEBUF Vref Margining
VREFMRGN_MEMVREG_EN
VREFMRGN_DQ_SODIMMA_EN
VREFMRGN_CA_SODIMMA_EN
PCA9557D_RESET_L
VOLTAGE=3.3V
MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.3 mm
PP3V3_S3_VREFMRGN_DAC
VOLTAGE=3.3V
MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.3 mm
PP3V3_S3_VREFMRGN_CTRL
SMBUS_PCH_CLK SMBUS_PCH_DATA
SMBUS_PCH_CLK SMBUS_PCH_DATA
VREFMRGN_SODIMMB_DQ
MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.3 mm VOLTAGE=0.75V
PP0V75_S3_MEM_VREFDQ_A
MIN_NECK_WIDTH=0.2 mm VOLTAGE=0.75V
MIN_LINE_WIDTH=0.3 mm
PP0V75_S3_MEM_VREFDQ_B
PP0V75_S3_MEM_VREFCA_A
MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=0.75V
PPVTTDDR_S3
PP0V75_S3_MEM_VREFCA_B
MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=0.75V
DDRREG_FB
GPU_FB_A_VREF_DIV
GPU_FB_B_VREF_DIV
VREFMRGN_FRAMEBUF_BUF
VREFMRGN_DQ_SODIMMA_BUF
VREFMRGN_DQ_SODIMMB_BUF
VREFMRGN_CA_SODIMMA_BUF
VREFMRGN_CA_SODIMMB_BUF
VREFMRGN_FRAMEBUF_EN
VREFMRGN_SODIMMA_DQ
VREFMRGN_MEMVREG_FBVREF
VREFMRGN_DQ_SODIMMB_EN
VREFMRGN_SODIMMS_CA
PP3V3_S3
VREFMRGN_MEMVREG_BUF
VREFMRGN_CA_SODIMMB_EN
33 OF 132
<E4LABEL>
<SCH_NUM>
<BRANCH>
32 OF 101
28
30
28
6 7
67
30
6 7 8
17 20 31 33 34 35 36 48 50
53 54 55 72 73 87
101
Page 33
BI
BI
IN
BI
SYM_VER-1
IN
IN
S
G
D
IN IN
IN
IN
BI
BI
SYM_VER-1
SYM_VER-1
NC
NC
IN
Y
B
A
D
S G
OUT
OUT
OUT
OUT
NC NC
D
S G
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER
SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
3V S3 WLAN FET
TPCP8102
P-TYPE
20-30 MOHM @2.5V
CAMERA
727 MA PEAK
ALS
275 mA peak 206 mA nominal max
155S0367
LOADING 0.727 A (EDP)
516S0582
BLUETOOTH
606 MA NOMINAL MAX
3.3 WLAN POWER GETTING STABLE AND AIRPORT CARD COMING OUT OF RESET
AIRPORT
RC (R3453 AND C3453)VALUE IS CHOSEN TO MEET THE 100 MS DELAY REQUIREMENT BETWEEN
518S0767
MOSFET
CHANNEL
RDS(ON)
0402-LF
FERR-120-OHM-1.5A
PLACEMENT_NOTE=Place close to J3402
L3408
12
402
CERM
20% 10V
0.1uF
C3452
1
2
35
35
6
45 48 54 97
6
45 48 54 97
PLACEMENT_NOTE=Place close to J3402
DLP0NS
90-OHM
CRITICAL
PLACE_NEAR=J3402.6:2.54MM
L3407
1 2
34
33 73
MF-LF
5%
402
10K
1/16W
R3451
1
2
402
MF-LF
1/16W
33K
5%
R3450
1 2
20 73
10% X5R
16V 402
0.033UF
C3451
1
2
TPCP8102
23V1K-SM
CRITICAL
Q3450
5 6 7 8
4
1 2 3
402
10% 16V X5R
0.1UF
C3450
1 2
10V
20%
805
10UF
X5R
C3420
1
2
PLACEMENT_NOTE=Place close to Q3450.
0603
FERR-120-OHM-3A
L3404
1 2
CERM
0.1uF
10V 402
20%
PLACEMENT_NOTE=Place close to Q3450.
C3421
1
2
1
MF-LF
402
1/16W
5%
R3455
1 2
10V
20%
402
0.1uF
CERM
PLACEMENT_NOTE=Place close to J3401.
C3422
1
2
17 94
17 94
17 94
17 94
36 93
36 93
402X5R16V10%
0.1uF
PLACEMENT_NOTE=Place close to J3401.
C3431
1 2
0.1uF
10% X5R16V 402
PLACEMENT_NOTE=Place close to J3401.
C3430
1 2
90-OHM-100MA
DLP11S
PLACEMENT_NOTE=Place close to J3401.
CRITICAL
L3401
1 2
34
PLACEMENT_NOTE=Place close to J3401.
DLP0NS
90-OHM
CRITICAL
PLACE_NEAR=J3401.21:2.54MM
L3403
1 2
34
5%
402
110K
1/16W MF-LF
R3453
1
2
74LVC1G17
SOT353-1
U3402
2
3 1
5
4
5%
62K
1/16W MF-LF 402
NOSTUFF
R3454
1
2
10%
6.3V CERM
1UF
402
C3453
1
2
27
SOT665
TC7SZ08AFEAPE
U3401
2
1
3
5
4
SSM6N15FEAPE
SOT563
Q3401
6
2
1
17 25
6
17 94
6 17
94
0402-LF
FERR-120-OHM-1.5A
PLACEMENT_NOTE=PLACE L3406 NEAR J3401.
L3406
12
6
18 27
F-ST-SM
500913-0302
CRITICAL
J3401
1
10
11
12
13
14
15
16
17
18
19
2
20
21
22
23
24
25
26
27
28
29
3
30
31
32
33
34
4
5
6
7
8
9
SOT563
SSM6N15FEAPE
Q3401
3
5
4
16V 402
10% CERM
PLACEMENT_NOTE=PLACE C3432 NEAR J3401
0.01UF
C3432
1
2
CRITICAL
819Q-3506-K281
F-RT-SM
J3402
7
8
1
2
3
4
5
6
21
SM
XW3452
SYNC_DATE=06/15/2009
SYNC_MASTER=K18_COMMS
X16/ALS/CAMERA CONNECTOR
P3V3WLAN_SS
PM_WLAN_EN_L
MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.5 mm
PP5V_S3_ALSCAMERA_F SMBUS_SMC_A_S3_SCL SMBUS_SMC_A_S3_SDA
USB_CAMERA_CONN_N
USB_CAMERA_CONN_P
PCIE_AP_R2D_P
MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.2 mm
PP3V3_S3_BT_F
AP_PWR_EN
PP3V3_WLAN
MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=1 mm
PP3V3_S3
PCIE_CLK100M_AP_CONN_N
PCIE_CLK100M_AP_CONN_P
CONN_USB2_BT_N
AP_RESET_CONN_L
USB_BT_N
AP_CLKREQ_L
WLAN_SMIT_DISCHRG
PM_WLAN_EN_L
PP5V_S3
WLAN_SMIT_RC
PP3V3_WLAN_F
USB_BT_P
WLAN_SMIT_BUF
AP_RESET_L
USB_CAMERA_P
USB_CAMERA_N
PP3V3_S3
PCIE_AP_R2D_C_N
PCIE_AP_R2D_C_P
PP3V3_S3
CONN_USB2_BT_P
PCIE_WAKE_L
PCIE_AP_R2D_N
PCIE_AP_D2R_N
PCIE_AP_D2R_P
AP_CLKREQ_Q_L
MIN_LINE_WIDTH=1 mm
PP3V3_WLAN_R
MIN_NECK_WIDTH=0.5 mm
PP3V3_WLAN_F
MIN_LINE_WIDTH=1 mm
MIN_NECK_WIDTH=0.4 mm
34 OF 132
<E4LABEL>
<SCH_NUM>
<BRANCH>
33 OF 101
6
6
93
6
93
6
94
6
6 7 8
17 20 31 32 33 34 35 36 48 50 53 54
55 72 73 87
101
6
99
6
99
6
99
6
33 73
6 7
31 42 43 44 46 54 56 58 61 66 67 72
82
101
33 56
6 7 8
17 20 31 32 33 34 35 36 48 50 53 54
55 72 73 87
101
6 7 8
17 20 31 32
33 34 35 36 48 50
53 54 55 72 73 87
101
6
99
6
94
6
33 56
Page 34
BI
BI
BI
BI
BI
NC
IN
OUT
OUT
OUT
VDD
WRITE_PROTECT_SW
CARD_DETECT_SW CARD_DETECT_GND
DAT6 DAT7
DAT1
CD/DAT3
DAT2
DAT4 DAT5
VSS
VSS
CLK CMD DAT0
SHLD_PIN
SHLD_PIN SHLD_PIN
SHLD_PIN
BI BI
X2
DP
CS
PMOSO
D1
VDD5V
D0
SK
DI
DO
D4
D2
D5
DM
GPIO2
D7
X1
GPIO3
GPIO1
VDD18O
AVDD
EXTRSTZ*
D3
DVDD
TESTMOD
CLK
D6
RREF
SD_CDZ
XD_CDZ
XD_CE
XD_WEZ XD_RBZ XD_WPZ
MS_INS
SD_WP
SD_CMD
PDMOD
MS_BS
GND
NC
NC
NC
NC
NC
NC NC NC NC NC
NC NC
D
SG
D
SG
IN
IN
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER
SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
(IPD)
(IPD)
(IPU)
(IPD)
(IPD)
(IPD)
(IPU)
(IPU)
(IPU)
(IPU)
(IPD)
(IPD)
NC = DISABLE (DEFAULT)
Keep this net short!
10K LOW = POWER SAVING MODE ENABLE 10K HIGH = REMOTE WAKE UP ENABLE
PDMOD: POWER DOWN MODES
(IPD)
Max Current = 250 mA
Caesar IV Support
516-0225
21
R3552
0
5% 402
1/16W
BCM57765
MF-LF
21
R3553
1/16W
5%
0
402
BCM57765
MF-LF
37
37
37
37
37
1
2
L3500
0.22UH
0805-1
GL137
37
37
6
34 37
6
34 37
21
R3555
603
1/10W
5%
MF-LF
0
BCM57765
2
1
R3502
402
MF-LF
1/16W
5%
0
GL137
21
R3554
MF-LF
5% 402
BCM57765
0
1/16W
16
6
3
4
20
19
18
17
13
12
11
10
9
8
7
2
5
1
14 15
J3500
SD-CARD-K19-K24
F-RT-TH
CRITICAL
21
R3556
BCM57765
0
5%
1/16W MF-LF
402
2
1
C3500
6.3V
603
X5R
20%
10UF
GL137
2
1
C3501
20% CERM
402
10V
BYPASS=U3500.15:16:5 mm
0.1UF
GL137
21
R3503
NO STUFF
1M
1/16W MF-LF
5%
402
2
1
C3505
0.1UF
20%
10V
402
CERM
2
1
C3506
10V
0.1UF
CERM
20%
BYPASS=U3500.4:5:5 mm
GL137
402
2.2UF
20%
C3507
2
1
603
CERM1
6.3V
2
1
C3508
0.1UF
402
CERM
20%
10V
BYPASS=U3500.11:12:5 mm
GL137
2
1
C3502
10V
0.1UF
402
CERM
20%
BYPASS=U3500.26:27:5 mm
GL137
2
1
C3503
10V
0.1UF
402
CERM
20%
BYPASS=U3500.35:34:5 mm
GL137
2
1
C3504
CERM
10V
402
20%
0.1UF
BYPASS=U3500.6:5:5 mm
GL137
8
36 93
8
36 93
21
C3511
50V
33PF
402
CERM
5%
GL137
21
Y3500
CRITICAL
8X4.5X1.4-SM
12.000M-100PPM
GL137
21
C3512
5%
CERM
402
33PF
50V
GL137
45
42
44
31
1
14
13
25
4
17
19
3 41
23
10
36
2
24 33
46
47
48
342716
12
9
5
18
352615
8
21
7
22
38
32
30
28
29
37
43
40
20
39
11
6
U3500
CRITICAL
LQFP
GL137A
GL137
10UF
6.3V
2
1
C3514
20% X5R
603
GL137
2
1
R3505
MF-LF 402
1/16W
5%
39K
2
1
C3513
NO STUFF
10V
0.1UF
402
CERM
20%
2
1
R3506
1% 1/16W MF-LF
402
715
GL137
2
1
R3507
402
MF-LF
1/16W
5%
10K
GL137
2
1
R3508
10K
5% 1/16W MF-LF 402
NO STUFF
2
1
R3509
402
MF-LF
1/16W
5%
10K
NO STUFF
2
1
R3510
10K
5% 1/16W MF-LF 402
GL137
21
R3511
0
1/16W MF-LF
5%
402
GL137
GL137
10K
5% 1/16W MF-LF
402
R3512
1
2
NO STUFF
10K
2
1
R3513
402
MF-LF
1/16W
5%
21
R3504
0
1/16W MF-LF
5%
402
GL137
2
1
C3515
NO STUFF
50V
10PF
402-1
CERM
5%
4
5
3
Q3500
SOT563
SSM6N15FEAPE
GL137
1
2
6
Q3500
SSM6N15FEAPE
SOT563
GL137
20 25
27
21
R3550
MF-LF1/16W
5%
0
BCM57765
402
21
R3551
0
4025%
1/16W MF-LF
BCM57765
SecureDigital Card Reader
SYNC_DATE=08/26/2009
SYNC_MASTER=T27_REF
MIN_LINE_WIDTH=0.40MM
PP3V3_S3_CARDREADER_DVDD
VOLTAGE=3.3V
MIN_NECK_WIDTH=0.20MM
SD_CD_L
MIN_NECK_WIDTH=0.20MM VOLTAGE=3.3V
PP3V3_S3_CARDREADER_AVDD
MIN_LINE_WIDTH=0.40MM
MIN_LINE_WIDTH=0.30 MM VOLTAGE=3.3V
MAKE_BASE=TRUE
MIN_NECK_WIDTH=0.20 MM
PP3V3_SW_SD_PWR
SD_D<0>
USB_SDCARD_P
GL137_CLK12M_X2 GL137_RREF
GL137_CLK12M_X1
SD_CD_L
MAKE_BASE=TRUE
SD_CMD
MAKE_BASE=TRUE
SD_D<3>
SD_D<2>
SD_D<1>
SD_D<0>
SD_WP
SD_CLK
PP3V3_S0
SDCONN_CMD
SDCONN_DATA<1>
SDCONN_DATA<2>
SD_CMD
SD_D<3> SD_D<4>
SD_D<1> SD_D<2>
SD_D<5>
SD_D<7>
SD_D<6>
SD_WP
PP3V3_S3
USB_SDCARD_N
PP1V8_S3_CARDREADER
MIN_NECK_WIDTH=0.20MM VOLTAGE=1.8V
MIN_LINE_WIDTH=0.30MM
GL137_GPIO1
SDCARD_PLT_RST
SDCARD_PLT_RST_L
SDCARD_RESET
MAKE_BASE=TRUE
SD_D<4..7>
SD_WP
MAKE_BASE=TRUE
SDCONN_DATA<0>
SDCONN_DATA<3>
SDCONN_DATA<4..7>
SD_CD_L
GL137_PDMOD
SD_CLK_R
GL137_TESTMOD GL137_RESET_L
GL137_GPIO2
SD_CLK
SDCONN_CLK
35 OF 132
<E4LABEL>
<SCH_NUM>
<BRANCH>
34 OF 101
6
34 37
6
34
6
34 37
6
34
6
34
6
34
6
34
6
34
6
34
6 7
17 18 19 20 21 23 24 25
26 27 28 30 37 40 42 46 47 48
50 51 52 54 58 62 63 68 69 72
73 80 83 84 85 87 88 99
6
34
6
34
6
34
6
34
6
34
6
34
6
34
6
34
6
34 37
6 7 8
17 20 31 32 33 35 36 48 50
53 54 55 72 73 87
101
6
34
6
34 37
6
34
Page 35
G
D
S
G
D
S
THRML_PAD
VDD18PLL
VDD18
VDD33
VDD33CR
VDD33PLL
OCS1*
PRTPWR4
OCS2*
USBUP_DM USBUP_DP
RESET*
XTAL1/CLKIN XTAL2
SUSP_IND/LOCAL_PWR/NON_REM0
USBDN1_DM/PRT_DIS_M1 USBDN1_DP/PRT_DIS_P1
USBDN2_DM/PRT_DIS_M2
PRTPWR2 PRTPWR3
VBUS_DET
RBIAS
OCS3* OCS4*
SDA/SMBDATA/NON_REM1
USBDN4_DM/PRT_DIS_M4 USBDN4_DP/PRT_DIS_P4
TEST
SCL/SMBCLK/CFG_SEL0
HS_IND/CFG_SEL1
PRTPWR1
USBDN3_DP/PRT_DIS_P3
USBDN3_DM/PRT_DOS_M3
USBDN2_DP/PRT_DIS_P2
VDDA33
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
IN
WP
SDA SCL
GND
VCC
IN
IN
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER
SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
BOM OPTIONS
BOM GROUP
TABLE_BOMGROUP_HEAD
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
CRITICAL BOM OPTION
TABLE_5_HEAD
PART#
DESCRIPTION
QTY
REFERENCE DESIGNATOR(S)
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_BOMGROUP_ITEM
IPU
1 0 Internal Default with Bus powered Operation
K17/K18 configuration: 0 0 Internal Default with Self powered Operation
IPU
External B
0 0 All ports are removable
1 1 Port 1, 2, and 3 are non removable
1 0 Port 1 and 2 are non removable
NON_REM1 NON_REM0 DESCRIPTION
IPU
IPU
0 1 SMBUS Slave Config
1 1 EEPROM Supported
SEL1 SEL0 DESCRIPTION
External C
0 1 Port 1 is non removable
USB HUB-1
Camera
IR Receiver
BOM TABLE
5%
10K
402
1/16W MF-LF
R3641
1
2
2N7002DW-X-G
SOT-363
Q3640
3
5
4
402
5%
MF-LF
1/16W
20K
R3640
1 2
2N7002DW-X-G
SOT-363
Q3640
6
2
1
CERM
50V 402
5%
NOSTUFF
100PF
C3641
1
2
402
0.47UF
10%
6.3V CERM-X5R
C3640
1
2
16V
10%
0.1UF
X5R 402
C3634
1
2
10K
5% 1/16W MF-LF
402
R3604
1
2
CERM
402
50V
5%
18PF
CRITICAL
C3619
1
2
HUB1_NONREM1_0
10K
5% 1/16W
402
MF-LF
R3665
1
2
402
MF-LF
1/16W
5%
10K
R3666
1
2
1/16W MF-LF
402
5%
10K
HUB1_NONREM1_1
R3692
1
2
402
MF-LF
5% 1/16W
10K
NOSTUFF
R3694
1
2
1/16W MF-LF
402
5%
1M
CRITICAL
R3691
1 2
5X3.2X1.4-SM
24.000M-60PPM-16PF
CRITICAL
Y3600
1 2
50V
18PF
CRITICAL
402
5% CERM
C3620
1
2
6.3V 603
X5R
10UF
20%
C3618
1
2
0.01UF
402
CERM
16V
10%
C3642
1
2
100PF
CERM 402
50V
5%
C3643
1
2
0.01UF
10% 402
16V CERM
C3636
1
2
FERR-120-OHM-1.5A
0402
L3629
1 2
10UF
X5R 603
20%
6.3V
C3644
1
2
402
50V
5% CERM
100PF
C3637
1
2
FERR-120-OHM-1.5A
0402
L3658
1 2
5% 1/16W MF-LF 402
10K
HUB1_NONREM0_0
R3667
1
2
402
MF-LF
1/16W
10K
5%
R3698
1
2
QFN
USX2061
OMIT
U3600
25
13 17 19 21
12 16 18 20
35
26
24
22
28
11
37
1 2
3 4
6 7
8 9
30 31
27
143423
15
36510
29
33 32
402
MF-LF
1/16W
5%
10K
NOSTUFF
R3697
1
2
1/16W MF
1%
402
12K
CRITICAL
R3600
1
2
8
93
8
93
43 93
19 93
19 93
43 93
44 93
33
44 93
33
402
10% 16V X7R-CERM
0.1UF
C3624
1
2
1UF
X5R
16V 402
10%
C3627
1
2
1/16W
10K
MF-LF
402
5%
R3682
1
2
0.1UF
X7R-CERM
10% 402
16V
C3628
1
2
1UF
402
X5R
16V
10%
C3630
1
2
0.1UF
16V X7R-CERM 402
10%
C3645
1
2
603
6.3V
10UF
X5R
20%
C3638
1
2
0.1UF
16V 402
X7R-CERM
10%
C3646
1
2
402
X7R-CERM
16V
10%
0.1UF
C3647
1
2
0.1UF
X7R-CERM
16V
10% 402
C3639
1
2
X7R-CERM
16V 402
10%
0.1UF
C3623
1
2
X7R-CERM
16V 402
10%
0.1UF
C3625
1
2
402
CERM
16V
10%
0.01UF
C3626
1
2
402
16V CERM
0.01UF
10%
C3629
1
2
19 25
100K
5% 1/16W MF-LF
402
R3642
1
2
SOT23-5
NOSTUFF
AT24C02B
U3614
2
1
3
4
5
8
HUB1_NONREM0_1
10K
5% 1/16W MF-LF 402
R3699
1
2
43
100
5% 1/16W MF-LF 402
R3668
1
2
BAT54XV2T1
SOD-523
D3600
12
HUB1_ALLREM
HUB1_NONREM1_0,HUB1_NONREM0_0
USBHUB_2061
338S0721
SMSC USX2061
2
U3600,U3700
CRITICAL
338S0824
USBHUB_2514B
SMSC USB2514B
CRITICAL
U3600,U3700
2
U3600,U3700
USBHUB_2514
2
CRITICAL
338S0720
SMSC USB2514
HUB1_1NONREM
HUB1_NONREM1_0,HUB1_NONREM0_1
HUB1_2NONREM
HUB1_NONREM1_1,HUB1_NONREM0_0
HUB1_3NONREM
HUB1_NONREM1_1,HUB1_NONREM0_1
USB HUB 1
SYNC_MASTER=K18_MLB
SYNC_DATE=10/07/2009
USB_HUB_RESET_L
USB_HUB_SOFT_RESET_L
PP3V3_S3
WP_HUB1
PP3V3_S3
PP3V3_S3
PP3V3_S3
USB_IR_P USB_EXTB_N
USB_EXTB_P
TP_USB_HUB1_PRTPWR1
USB_HUB1_CFG_SEL1
USB_HUB1_SMBCLK
USB_HUB1_TEST
USB_EXTC_P
USB_EXTC_N
USB_HUB1_SMBDATA
NC_USB_HUB1_OCS4
USB_EXTB_OC_L
USB_HUB1_RBIAS
USB_HUB1_VBUS_DET
NC_USB_HUB1_PRTPWR3
NC_USB_HUB1_PRTPWR2
USB_IR_N
USB_HUB1_LOCAL_PWR
USB_HUB1_XTAL2
USB_HUB1_XTAL1
USB_HUB_RESET_L
USB_HUB1_UP_P
USB_HUB1_UP_N
NC_USB_HUB1_OCS2
NC_USB_HUB1_PRTPWR4
TP_USB_HUB1_OCS1
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.4MM VOLTAGE=3.3V
PPUSB_HUB1_VDDA3V3
MIN_LINE_WIDTH=0.4MM MIN_NECK_WIDTH=0.2MM
VOLTAGE=3.3V
PPUSB_HUB1_VDDPLL3V3
PP3V3_S3
MIN_LINE_WIDTH=0.4MM MIN_NECK_WIDTH=0.2MM
VOLTAGE=1.8V
PPUSB_HUB1_VDD1V8
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.4MM
VOLTAGE=1.8V
PPUSB_HUB1_VDD1V8PLL
USB_CAMERA_N USB_CAMERA_P
USB_HUB_RESET
P3V3S3_EN_RC
PP3V3_S5
PP3V3_S3
36 OF 132
<E4LABEL>
<SCH_NUM>
<BRANCH>
35 OF 101
6 7 8
17 20 31 32 33
34 35 36 48 50 53 54 55
72 73 87
101
6 7 8
17 20 31 32 33 34 35 36 48 50 53 54
55 72 73 87
101
6 7 8
17 20 31 32
33 34 35 36
48 50 53 54
55 72 73 87
101
6 7 8
17 20 31 32 33 34 35 36 48 50 53
54 55 72 73 87
101
35 36
6 7 8
17 20 31 32 33 34 35 36 48 50 53
54 55 72 73 87
101
6 7
17 18 19 20 21 23 27 31
57 66 71 72 73 83 85 99
6 7 8
17 20 31 32 33 34 35 36 48 50 53
54 55 72 73 87
101
Page 36
BI
IN
BI
BI
BI
BI
BI
BI
BI
BI
BI
IN
WP
SDA SCL
GND
VCC
IN
THRML_PAD
VDD18PLL
VDD18
VDD33
VDD33CR
VDD33PLL
OCS1*
PRTPWR4
OCS2*
USBUP_DM USBUP_DP
RESET*
XTAL1/CLKIN XTAL2
SUSP_IND/LOCAL_PWR/NON_REM0
USBDN1_DM/PRT_DIS_M1 USBDN1_DP/PRT_DIS_P1
USBDN2_DM/PRT_DIS_M2
PRTPWR2 PRTPWR3
VBUS_DET
RBIAS
OCS3* OCS4*
SDA/SMBDATA/NON_REM1
USBDN4_DM/PRT_DIS_M4 USBDN4_DP/PRT_DIS_P4
TEST
SCL/SMBCLK/CFG_SEL0
HS_IND/CFG_SEL1
PRTPWR1
USBDN3_DP/PRT_DIS_P3
USBDN3_DM/PRT_DOS_M3
USBDN2_DP/PRT_DIS_P2
VDDA33
BOM OPTIONS
BOM GROUP
TABLE_BOMGROUP_HEAD
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER
SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
Trackpad/Keyboard
SD Card/Express Card
SEL1 SEL0 DESCRIPTION
1 1 EEPROM Supported
0 1 SMBUS Slave Config
K17/K18 configuration: 0 0 Internal Default with Self powered Operation
1 0 Internal Default with Bus powered Operation
Bluetooth
IPU
IPU
IPU IPU
NON_REM1 NON_REM0 DESCRIPTION
0 1 Port 1 is non removable 1 0 Port 1 and 2 are non removable 1 1 Port 1, 2, and 3 are non removable
0 0 All ports are removable
External A
USB HUB-2
402
CERM
50V
5%
18PF
CRITICAL
C3720
1
2
402
1/16W MF-LF
CRITICAL
5%
1M
R3791
1 2
18PF
50V
5%
CERM
CRITICAL
402
C3719
1
2
16V 402
X5R
10%
0.1UF
C3734
1
2
100PF
402
CERM
50V
5%
C3737
1
2
100PF
50V
5% 402
CERM
C3743
1
2
X7R-CERM
0.1UF
10% 402
16V
C3739
1
2
402
X7R-CERM
16V
0.1UF
10%
C3745
1
2
16V X7R-CERM
0.1UF
402
10%
C3746
1
2
16V 402
10% X7R-CERM
0.1UF
C3747
1
2
0.1UF
10% 402
16V X7R-CERM
C3725
1
2
X7R-CERM
0.1UF
402
10% 16V
C3723
1
2
0.1UF
X7R-CERM
16V
10% 402
C3724
1
2
0.1UF
10% 402
16V X7R-CERM
C3728
1
2
CERM
10% 16V
402
0.01UF
C3736
1
2
0.01UF
CERM
16V
10% 402
C3742
1
2
10%
0.01UF
402
CERM
16V
C3729
1
2
0.01UF
402
CERM
16V
10%
C3726
1
2
19 93
35
10UF
6.3V X5R 603
20%
C3718
1
2
NOSTUFF
1/16W MF-LF
10K
5%
402
R3797
1
2
5% 402
MF-LF
10K
1/16W
R3798
1
2
FERR-120-OHM-1.5A
0402
L3729
1 2
HUB2_NONREM1_1
10K
5% 1/16W MF-LF
402
R3792
1
2
5%
10K
402
MF-LF
1/16W
NOSTUFF
R3794
1
2
10K
402
MF-LF
1/16W
5%
R3704
1
2
402
5% 1/16W MF-LF
10K
R3782
1
2
402
MF-LF
1/16W
5%
10K
R3766
1
2
1/16W
5% 402
10K
MF-LF
HUB2_NONREM1_0
R3765
1
2
10K
5% 1/16W MF-LF
HUB2_NONREM0_0
402
R3767
1
2
19 93
43 93
43 93
8
34 93
8
34 93
53 93
53 93
33 93
33 93
8
NOSTUFF
SOT23-5
AT24C02B
U3714
2
1
3
4
5
43
CRITICAL
24.000M-60PPM-16PF
5X3.2X1.4-SM
Y3700
1 2
5%
10K
402
1/16W MF-LF
HUB2_NONREM0_1
R3799
1
2
100
1/16W MF-LF
5%
402
R3768
1
2
1UF
402
X5R
16V
10%
C3730
1
2
X5R
1UF
16V 402
10%
C3727
1
2
10UF
603
X5R
20%
6.3V
C3738
1
2
10UF
6.3V X5R 603
20%
C3744
1
2
0402
FERR-120-OHM-1.5A
L3758
1 2
CRITICAL
402
MF
12K
1/16W
1%
R3700
1
2
QFN
USX2061
OMIT
U3700
25
13 17 19 21
12 16 18 20
35
26
24
22
28
11
37
1 2
3 4
6 7
8 9
30 31
27
143423
15
36510
29
33 32
SYNC_DATE=10/06/2009SYNC_MASTER=K23F
USB HUB 2
HUB2_1NONREM
HUB2_NONREM1_0,HUB2_NONREM0_1
HUB2_3NONREM
HUB2_NONREM1_1,HUB2_NONREM0_1
HUB2_ALLREM
HUB2_NONREM1_0,HUB2_NONREM0_0
HUB2_2NONREM
HUB2_NONREM1_1,HUB2_NONREM0_0
VOLTAGE=1.8V
MIN_LINE_WIDTH=0.4MM MIN_NECK_WIDTH=0.2MM
PPUSB_HUB2_VDD1V8
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.4MM
VOLTAGE=1.8V
PPUSB_HUB2_VDD1V8PLL
PP3V3_S3
MIN_LINE_WIDTH=0.4MM MIN_NECK_WIDTH=0.2MM
PPUSB_HUB2_VDDPLL3V3
VOLTAGE=3.3V
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.4MM
VOLTAGE=3.3V
PPUSB_HUB2_VDDA3V3
TP_USB_HUB2_OCS1
NC_USB_HUB2_PRTPWR4
NC_USB_HUB2_OCS2
USB_HUB2_UP_N USB_HUB2_UP_P
USB_HUB_RESET_L
USB_HUB2_XTAL1 USB_HUB2_XTAL2
USB_HUB2_LOCAL_PWR
USB_BT_N USB_BT_P
USB_TPAD_N
NC_USB_HUB2_PRTPWR2 NC_USB_HUB2_PRTPWR3
USB_HUB2_VBUS_DET
USB_HUB2_RBIAS
NC_USB_HUB2_OCS3
USB_EXTA_OC_L
USB_HUB2_SMBDATA
USB_EXTA_N USB_EXTA_P
USB_HUB2_TEST
USB_HUB2_SMBCLK
USB_HUB2_CFG_SEL1
TP_USB_HUB2_PRTPWR1
USB_SDCARD_P
USB_SDCARD_N
USB_TPAD_P
PP3V3_S3
WP_HUB2
PP3V3_S3
PP3V3_S3
PP3V3_S3
37 OF 132
<E4LABEL>
<SCH_NUM>
<BRANCH>
36 OF 101
6 7 8
17 20 31 32 33 34 35 36 48 50 53 54
55 72 73 87
101
6 7 8
17 20 31 32 33 34 35 36 48 50 53
54 55 72 73 87
101
6 7 8
17 20 31 32 33 34 35 36 48 50 53
54 55 72 73 87
101
6 7 8
17 20 31 32 33 34 35 36 48 50 53
54 55 72 73 87
101
6 7 8
17 20 31 32 33 34 35 36 48 50 53 54
55 72 73 87
101
Page 37
IN
IN
IN
OUT
OUT
IN
IN OUT
OUT
OUT
IN
IN
BI
BI BI
BI BI BI BI BI
NC
BI
BI BI BI BI BI BI BI
OUT
IN
IN
IN
AVDDH
BIASVDDH
VDDC
VDDIO
XTALVDDH
VDDIO
VDDC
AVDDL
SI SO CS*
RDAC
VDDC UART_MODE
SCLK
LOW_PWR
LINKLED*
CLKREQ*
PERST*
PCIE_REFCLK_N
PCIE_REFCLK_P
PCIE_TXD_P
PCIE_RXD_P
VDDC
VDDC
VDDIO
PCIE_PLLVDDL
GPHY_PLLVDDL
DC2 DC1
NC
VMAIN_PRSNT
VAUX_PRSNT
ENERGY_DET
DC3
DC4
NC
GPIO_2
TRD1_N
TRD1_P
TRD0_N
SMB_DATA
TRD0_P
TRD2_N
TRD2_P
TRD3_P
THRM_PAD
XTALI XTALO
SPD100LED* TRAFFICLED*
TRD3_N
DC5
PCIE_TXD_N
SPD1000LED*
DC0
WAKE*
PCIE_VDDL
REGCTL12
VDDIO
PCIE_RXD_N
GPIO_0/SERIAL_DO GPIO_1/SERIAL_DI
SMB_CLK
VDDC
VERSION 2
OUT
RESET*
CS*
SCK
SO
WP*
SI
GND
VCC
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER
SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
(IPD)
is powered-down in S3/S5. Standard
Must isolate from PCIe WAKE# if PHY
WAKE#
info as well as code for Bonjour proxy.
PHY Non-Volatile Memory
Required for proper PHY operation.
ROM contains MAC address, PCIe config
Atmel AT45DB011D (1Mbit) ROM. If a different ROM is used then the straps must change. NOTE: BCM5764M requires SI pull-down instead of SO.
53-VMAIN_PRSNT
(IPD)
20-XTALVDDH
26-PCIE_VDDL
86mA (1000base-T, Caesar II)
(See note)
(See note)
=ENET_WAKE_L to PCIE_WAKE_L.
396mA (1000base-T, Caesar II)
55-VDDC 17-VDDC
06-VDDC
14-VDDC
13-WAKE*
(IPD)
N-channel FET isolation suggested. If PHY is always powered then alias
(OD) (OD)
(IPD)
BCM57765 SR pins are internal 1.2V switching regulator.
BCM57765 supports both active-levels for WP.
All resistors above BOMOPTIONed BCM57765
just decoupling for BCM57765 CR I/Os.
CR_BUS_PWR is not for SD Card power,
If used: VDD/VDDP connect to =PP3V3_ENET_PHY (add bypassing), LX connects to inductor, VFB to =PP1V2_ENET_PHY
If unused: Okay to float all 4 pins. (Broadcom not so sure now)
(Required ROM size TBD)
All parts below BOMOPTIONed BCM5764M
BCM5764M Support
58-SMB_DATA 54-VAUX_PRSNT 16-VDDIO
(IPD-BCM5764M)
(IPU)
other 3 SPI pins configures BCM57765 for the
NOTE: Pull-down on SO plus internal pull-ups on
59-SMB_CLK
BCM5764M pin-function 60-ENERGY_DET
with no stubs.
Keep net short,
10% 16V
402
X7R-CERM
0.1UF
C3921
1
2
X5R
6.3V
10%
805
10UF
C3935
1
2
6.3V
10%
603
X5R-CERM
4.7UF
C3925
1
2
CRITICAL
SM
FERR-600-OHM-0.5A
L3925
1 2
4.7UF
X5R-CERM
10%
6.3V 603
C3920
1
2
CRITICAL
SM
FERR-600-OHM-0.5A
L3920
1 2
FERR-600-OHM-0.5A
SM
CRITICAL
L3900
1 2
FERR-600-OHM-0.5A
CRITICAL
SM
L3905
1 2
1/16W
1K
5% MF-LF
402
BCM57765
R3942
1
2
17 94
17 94
27 95
17
27 37
20
27 95
27 95
10% 16V X5R 402
0.1uF
C3951
1 2
10% 16V X5R
0.1uF
402
C3950
1 2
402
X5R
0.1uF
10% 16V
C3956
1 2
10% 16V X5R 402
0.1uF
C3955
1 2
MF-LF
1/16W
1%
402
1.24K
R3965
1
2
17 94
17 94
17 94
17 94
38 95
38 95
38 95
38 95
38 95
38 95
38 95
38 95
BCM57765
402
4.7K
5% 1/16W MF-LF
R3941
1
2
BCM57765
4.7K
1/16W
402
5%
MF-LF
R3940
1
2
0
5%
1/16W MF-LF
402
BCM5764M
R3980
1 2
BCM5764M
4.7K
5%
1/16W MF-LF
402
R3984
1 2
BCM5764M
402
MF-LF1/16W
5%
0
R3999
1 2
MF-LF
BCM57765
402
1/16W
5%
0
R3978
1 2
34
BCM5764M
4.7K
5%
1/16W MF-LF
402
R3983
1 2
BCM5764M
402
MF-LF1/16W
5%
1K
R3982
1 2
FERR-600-OHM-0.5A
PLACE_NEAR=U3900.26:2 mm
BCM5764M
SM
CRITICAL
L3999
1 2
PLACE_NEAR=L3999.1:1 mm
BCM5764M
10% 603
X5R-CERM
4.7UF
6.3V
C3998
1
2
X7R-CERM
402
PLACE_NEAR=U3900.26:1 mm
BCM5764M
16V
10%
0.1UF
C3999
1
2
402
MF-LF1/16W
5%
0
BCM57765
R3977
1 2
402
0
5%
1/16W MF-LF
BCM57765
R3976
1 2
0
5%
1/16W MF-LF
402
BCM57765
R3975
1 2
34
34
34
34
34
34
34
34
BCM57765
PLACE_NEAR=L3999.1:1 mm
0
5%
1/16W MF-LF
402
R3974
1 2
BCM57765
402
MF-LF1/16W
5%
0
R3973
1 2
6
34
0
BCM57765
402
1/16W MF-LF
5%
R3943
1 2
BCM5764M
0
5%
1/16W MF-LF
402
R3981
1 2
BCM5764M
0
5%
1/16W MF-LF
402
R3986
1 2
BCM5764M
1K
402
MF-LF1/16W
5%
R3985
1 2
BCM5764M
0
5%
1/16W MF-LF
402
R3989
1 2
BCM5764M
0
1/16W MF-LF
4025%
R3987
1 2
BCM5764M
0
5%
1/16W MF-LF
402
R3988
1 2
5%
MF-LF
1/16W
402
0
BCM57765
R3900
1 2
5%
MF-LF
1/16W
402
0
BCM57765
R3915
1 2
4.7K
MF-LF 402
5% 1/16W
BCM57765
R3990
1
2
BCM5764M
0
5%
1/16W MF-LF
402
R3998
1 2
34
6
34
OMIT
CRITICAL
BCM5764M
QFN-8X8
U3900
42
48
394551
37
12
63
21
22
23
24
25
57
60
36
5 8 9
3
4
1
52
29
32
30
31
34
33
27 28
26
11
38
15
66 64
59
58
65
68
2
69
67
41
40
43
44
47
46
49
50
10
54
6
14
17
355561
71656
62
53
13
18 19
20
BCM57765
10%
6.3V
X5R-CERM
603
4.7UF
C3970
1
2
0.1UF
16V
10%
402
X7R-CERM
BCM57765
C3971
1
2
0.1UF
16V
10%
402
X7R-CERM
BCM57765
C3972
1
2
BCM57765
0
5%
1/16W MF-LF
402
R3972
1 2
17 37
5%
4.7K
402
1/16W MF-LF
R3910
1
2
CRITICAL
FERR-600-OHM-0.5A
SM
L3910
1 2
0.1UF
X7R-CERM 402
10% 16V
C3910
1
2
0.1UF
402
10% 16V X7R-CERM
C3911
1
2
16V
10% 402
0.1UF
X7R-CERM
C3990
1
2
16V
10%
402
0.1UF
X7R-CERM
C3900
1
2
16V
10%
402
0.1UF
X7R-CERM
C3905
1
2
4.7UF
603
X5R-CERM
6.3V
10%
C3930
1
2
X7R-CERM
402
10% 16V
0.1UF
C3931
1
2
CRITICAL
SM
FERR-600-OHM-0.5A
L3930
1 2
4.7UF
10%
6.3V 603
X5R-CERM
C3915
1
2
16V
0.1UF
X7R-CERM
10%
402
C3916
1
2
AT45DB011D
SOIC-8S1
OMIT
U3990
4
7
3
2 1
8
6
5
BCM5764M
1/16W
5%
402
MF-LF
4.7K
R3997
1
2
X7R-CERM
16V
0.1UF
402
10%
C3936
1
2
402
0.1UF
X7R-CERM
10% 16V
C3926
1
2
SYNC_MASTER=T27_REF
SYNC_DATE=08/20/2009
Ethernet PHY (Caesar II/IV)
PP3V3_ENET
PCIE_ENET_D2R_C_N
ENET_RESET_L
BCM5764_CS_L
BCM57765_SMB_DATA BCM5764_SCLK
BCM5764_MISO
TP_BCM5764_TRAFFICLED_L
BCM5764_CLK25M_XTALO BCM5764_RDAC
BCM57765_CR_CMD
SDCONN_CLK
BCM57765_SD_DETECT
BCM57765_MEDIA_SENSE
ENET_MDI_P<1>
BCM5764_CS_L
MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V
PP3V3_ENET_PHY_AVDDH
PP3V3_ENET_PHY_BIASVDDH
VOLTAGE=3.3V
MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.4 mm
PP3V3R1V8_SW_SD_VIO
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm
ENET_MDI_P<0>
SD_WP
SDCONN_DATA<7>
SDCONN_DATA<6>
SDCONN_DATA<5>
SDCONN_DATA<4>
SDCONN_DATA<3>
SDCONN_DATA<2>
SDCONN_DATA<1>
SDCONN_DATA<0>
SDCONN_CMD
SD_CD_L
ENET_ENERGY_DET
ENET_ENERGY_DET
TP_BCM57765_SR_VDDP
PP1V2_ENET_PHY_AVDDL
MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.4 mm VOLTAGE=1.2V
MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.2V
PP1V2_ENET_PHY_PCIEPLL
MIN_LINE_WIDTH=0.4 mm
BCM57765_SR_LX
ENET_MDI_N<0>
BCM57765_CR_DATA<4>
PCIE_ENET_R2D_P
ENET_LOW_PWR
BCM57765_CR_DATA<7>
BCM57765_CR_LED
TP_BCM57765_XD_DET
BCM57765_CE_L_MS_INS_L
ENET_CLKREQ_L
BCM57765_CR_CMD
BCM57765_SR_VFB
ENET_MDI_N<3>
TP_BCM5764_SPD100LED_L
BCM5764_CLK25M_XTALI
ENET_MDI_P<3>
ENET_MDI_P<2> ENET_MDI_N<2>
BCM57765_VMAIN_PRSNT
ENET_MDI_N<1>
BCM57765_CR_DATA<6>
BCM57765_CR_DATA<5>
PP1V2_ENET_PHY_GPHYPLL
VOLTAGE=1.2V
MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.4 mm
PP1V2_ENET
PCIE_ENET_D2R_C_P
PCIE_ENET_R2D_N PCIE_CLK100M_ENET_P
PCIE_CLK100M_ENET_N
BCM57765_WAKE_L
BCM57765_SMB_CLK
BCM5764_MOSI
BCM57765_SR_VDD
VOLTAGE=3.3V
MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.4 mm
BCM57765_VDDO_PIN20
BCM57765_XTALVDDH
MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V
BCM57765_CR_LED
BCM57765_CR_DATA<5> BCM57765_CE_L_MS_INS_L
BCM57765_SR_VDD
PP1V2_ENET
BCM57765_SMB_CLK
MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.4 mm VOLTAGE=3.3V
PP3V3_ENET_PHY_XTALVDDH
PP3V3_S0
BCM57765_VMAIN_PRSNT
BCM57765_VDDO_PIN20
BCM57765_XTALVDDH
BCM57765_CR_DATA<7>
BCM57765_SR_LX
PP3V3_ENET_PHY_XTALVDDH
BCM57765_CR_DATA<6>
PP3V3_S0
ENET_WAKE_L
BCM57765_SR_VFB
PP3V3_ENET
BCM5764_MOSI
BCM5764_MISO
PP3V3_ENET
BCM5764_SCLK
ENET_WAKE_L
PCIE_ENET_R2D_C_P
PCIE_ENET_R2D_C_N
PCIE_ENET_D2R_P
PCIE_ENET_D2R_N
39 OF 132
<E4LABEL>
<SCH_NUM>
<BRANCH>
37 OF 101
6 7
27 37 73
94
37
37
37
37
37
17 37
37
94
37
37
37
37
37
37
37
37
6 7
37 71 72
94
94
37
37
37
37
37
37
37
37
37
6 7
37 71 72
37
37
6 7
17 18 19 20 21 23 24 25
26 27 28 30 34 37 40 42 46 47
48 50 51 52 54 58 62 63 68 69
72 73 80 83 84 85 87 88 99
37
37
37
37
37
37
37
6 7
17 18 19 20 21 23 24 25 26
27 28 30 34 37 40 42 46 47 48
50 51 52 54 58 62 63 68 69 72
73 80 83 84 85 87 88 99
27 37 37
6 7
27 37 73
37
37
6 7
27 37 73
37
Page 38
BI
RX
TX
BI
RX
TX
BI
IONCNC
IONCIO
IO
NC
GND
IONCNC
IONCIO
IO
NC
GND
BI
BI
BI
BI
BI
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER
SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
mirrored on opposite
Transformers should be
Place one of 0.1uf cap close to each centertap pin of transformer
514-0636
BOM options provided by this page:
(NONE)
(NONE)
(NONE) Signal aliases required by this page:
Power aliases required by this page:
Page Notes
sides of the board
37 95
CRITICAL
SM
TLA-6T213HF
T4000
1
10
11
12
2
3
4
5
6 7
8
9
75
MF-LF
402
5%
1/16W
R4000
1
2
75
MF-LF
402
5%
1/16W
R4001
1
2
75
MF-LF 402
5% 1/16W
R4002
1
2
75
MF-LF 402
5% 1/16W
R4003
1
2
2KV
10%
1206
CERM
CRITICAL
1000PF
C4008
1 2
37 95
X5R 402
16V
10%
0.1UF
C4006
1
2
0.1UF
X5R 402
10% 16V
C4004
1
2
402
0.1UF
X5R
10% 16V
C4002
1
2
TLA-6T213HF
SM
CRITICAL
T4001
1
10
11
12
2
3
4
5
6 7
8
9
X5R 402
10% 16V
0.1UF
C4000
1
2
37 95
RJ45-M97-3
CRITICAL
F-RT-TH
J4000
1
10
11 12
2 3 4 5 6 7 8
9
PLACE_NEAR=T4001.1:5mm
RCLAMP0524P
CRITICAL
SLP2510P8
D4001
3
5 4 2 16 7 9
10
PLACE_NEAR=T4000.5:5mm
RCLAMP0524P
CRITICAL
SLP2510P8
D4000
3
5 4 2 16 7 9
10
37 95
37 95
37 95
37 95
37 95
SYNC_DATE=06/15/2009
SYNC_MASTER=K17_REF
Ethernet Connector
ENET_MDI_P<1>
ENET_MDI_N<2>
ENET_MDI_N<1>
ENET_MDI_P<2>
ENET_MDI_P<3>
ENET_MDI_N<3>
ENET_MDI_N<0>
ENET_MDI_P<0>
ENETCONN_P<3>
ENETCONN_P<0>
ENETCONN_N<3>
ENETCONN_N<0>
ENETCONN_N<2>
ENETCONN_N<1>
ENETCONN_P<2>
ENET_CTAP3
ENETCONN_CTAP
ENET_BOB_SMITH_CAP
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm
ENET_CTAP0
ENET_CTAP1
ENETCONN_P<1>
ENET_CTAP2
40 OF 132
<E4LABEL>
<SCH_NUM>
<BRANCH>
38 OF 101
99
99
99
99
99
99
99
99
Page 39
DS2
ATBUSH ATBUSN
VP25
OCR_CTL_V10
VAUX_DETECT
TMS
TCK
REFCLKN
PCIE_TXD0P
TRST*
ATBUSB
TDI
DS1
TPA0N TPA0P
AVREG
CE
CLKREQN
FW_RESET*
FW620* JASI_EN
MODE_A
NAND_TREE
OCR_CTL_V12
PCIE_RXD0N PCIE_RXD0P PCIE_TXD0N
PERST*
R0
REFCLKP
REGCLT
REXT
SCIFCLK SCIFDAIN SCIFDOUT
SCIFMC
SCL SDA
SE SM
TDO
TPA1N
TPA2N TPA2P TPB0N TPB0P TPB1N TPB1P TPB2N TPB2P
TPBIAS0 TPBIAS1 TPBIAS2
TPCPS
VAUX_DISABLE
VBUF
VDDH
VP
VREG_PWR
WAKE*
XI
XO
DS0
TPA1P
VDD33
VDD10
VREG_VSS
VSS
SERIAL EEPROM
MISCELLANEOUS
CONTROLLER
POWER MANAGEMENT
TEST CONTROLLER
PCI EXPRESS PHY
CHIP RESET
SCIF
1394 PHY
NC NC NC
NC
IN IN
IN
IN
OUT
OUT
OUT
OUT
IN IN IN
BI BI BI BI BI BI BI BI BI BI BI BI
BI BI BI
IN
NC NC
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER
SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
CRITICAL BOM OPTION
TABLE_5_HEAD
PART#
DESCRIPTION
QTY
REFERENCE DESIGNATOR(S)
TABLE_5_ITEM
NT-9
(IPD) (IPD)
(IPD)
NT-7
NT-10 (IPD)
NT-12 (IPD)
(IPU)
(IPD) NT-20
(IPD) NT-19
(Reserved)
NT-OUT
NT-14 (IPD)
NT-5
NT-17
NT-16 (IPD)
(OD)
NT-4 (IPU)
25 mA PCIe SerDes 17 mA PCIe SerDes
0 mA VReg PWR
114 mA FireWire PHY
7 mA I/O
138 mA
(IPU) NT-8
(IPD) NT-11
NT-15 (IPD)
(IPU)
110 mA Digital Core
NOTE: NT-xx notes show NAND tree order.
NT-3 (IPU)
FIXME!!! - TYPO IN SYMBOL REGCTL
NT-13
NT-1 (IPU)
NT-2 (IPU)
NT-6
(IPD) NT-18
(IPD) NT-21
135 mA
191
MF-LF 402
1% 1/16W
R4170
1
2
0.33UF
CERM-X5R 402
10%
6.3V
C4162
1
2
470K
402
5% 1/16W MF-LF
R4162
1
2
OMIT
CRITICAL
FW643
BGA
U4100
B13 A13 A11
A10
L13
L2
F12 E12 E13
D12
K13
D1
J2
K1
J12 J13
N8 N7 N5 N6
N4
B11
N9 N10
D13
L8
G2 G1 H1 F2
N12 M11
M13 N13
M4 N2 M1 M3
B8 A8 B5 A5 B3 A3 B9 A9 B6 A6 B4 A4
B7 C3 A2
B10
N1
E1 D2
H13
A1
B1
M12N3N11
B12
C13E2E10H2H12K2L1
C1
C12F1G12J1L3
L11M2A12D5D6D8L5
L10L6L9
K12
L12
B2
D4
F7
F8
F10
G4G6G7
G8
G10
H4
H6D7H7
H8
H10
J4J5J9
J10
K4K5K7D9K8K9L7
K6
K10
D10
E4E5E9F4F6
C2
G13
F13
22PF
CERM
402
5%
50V
C4151
1 2
22PF
CERM
402
5%
50V
C4150
1 2
200K
MF-LF
402
1%
1/16W
PLACE_NEAR=U4100.B10:2mm
R4160
1
2
412
MF-LF
402
1%
1/16W
R4150
1 2
10K
MF-LF 402
5% 1/16W
R4163
1
2
10K
MF-LF 402
5% 1/16W
R4164
1
2
FW643_LDO
10K
MF-LF
402
5%
1/16W
R4165
1
2
PLACEMENT_NOTE=Place C4176 close to U4100
0.1UF
X5R 402
10% 16V
C4176
1 2
PLACEMENT_NOTE=Place C4175 close to U4100
0.1UF
X5R 402
10% 16V
C4175
1 2
10K
MF-LF 402
5% 1/16W
R4166
1
2
PLACEMENT_NOTE=Place C4171 close to U1800
0.1UF
X5R 402
10% 16V
C4171
1 2
PLACEMENT_NOTE=Place C4170 close to U1800
0.1UF
X5R 402
10% 16V
C4170
1 2
1UF
CERM
402
10%
6.3V
C4130
1
2
1UF
CERM
402
10%
6.3V
C4131
1
2
10%
1UF
CERM 402
6.3V
C4100
1
2
1UF
CERM 402
10%
6.3V
C4101
1
2
1UF
CERM
402
10%
6.3V
C4132
1
2
1UF
CERM 402
10%
6.3V
C4102
1
2
1UF
402
10%
6.3V CERM
C4103
1
2
1UF
CERM
402
10%
6.3V
C4135
1
2
1UF
CERM
402
10%
6.3V
C4136
1
2
1UF
CERM 402
10%
6.3V
C4104
1
2
1UF
CERM 402
10%
6.3V
C4110
1
2
1UF
CERM 402
10%
6.3V
C4105
1
2
1UF
CERM 402
10%
6.3V
C4106
1
2
1UF
CERM
402
10%
6.3V
C4120
1
2
1UF
CERM
402
10%
6.3V
C4121
1
2
1UF
CERM
402
10%
6.3V
C4122
1
2
1UF
CERM
402
10%
6.3V
C4123
1
2
1UF
CERM
402
10%
6.3V
C4124
1
2
0.1UF
CERM
402
20% 10V
C4141
1
2
1UF
CERM 402
10%
6.3V
C4111
1
2
1UF
CERM 402
10%
6.3V
C4140
1
2
17 94
17 94
17 94
17 94
17 94
17 94
8
40
40
2.94K
MF-LF
402
1% 1/16W
R4161
1
2
41
41
41
41 96
6
41 96
40 41 96
40 41 96
6
41
6
41
6
41 96
6
41 96
40 41 96
40 41 96
6
41
6
41
41
40 41
6
41
120-OHM-0.3A-EMI
0402-LF
L4130
1 2
120-OHM-0.3A-EMI
0402-LF
L4135
1 2
40
120-OHM-0.3A-EMI
0402-LF
L4110
1 2
CRITICAL
SM-3.2X2.5MM
24.576MHZ
Y4150
2 4
1 3
OMIT
1%
0.2
1/16W MF-LF
402
R4100
1 2
RES,0.475 ohm,1%,1/16W,0402
CRITICAL
R4100
1
114S0557
SYNC_DATE=05/29/2009
SYNC_MASTER=K19_MLB
FireWire LLC/PHY (FW643)
FW643_TPCPS
PP1V0_FW_R
MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.0V
MIN_LINE_WIDTH=0.4 MM
PP1V0_FW_FWPHY
FW643_R0
NC_FW2_TPBN
FW643_PU_RST_L
FW643_WAKE_L
TP_FW643_SDA
FW_RESET_L
FW643_REGCTL
TP_FW643_VAUX_ENABLE
FW643_TRST_L
FW643_VAUX_DETECT
TP_FW643_SCIFDOUT TP_FW643_SCIFMC
PP3V3_FW_FWPHY
FW_CLK24P576M_XO
PPVP_FW_CPS
TP_FW643_OCR10_CTL
TP_FW643_TMS
NC_FW643_TDI
NC_FW643_AVREG
TP_FW643_FW620_L
TP_FW643_SCIFCLK
TP_FW643_SM
TP_FW643_VBUF
FW_PORT1_TPA_P
FW_PORT1_TPA_N
NC_FW2_TPAN NC_FW2_TPAP NC_FW0_TPBN
FW_PORT1_TPB_N FW_PORT1_TPB_P
NC_FW2_TPBP NC_FW0_TPBIAS
NC_FW2_TPBIAS
FW_CLK24P576M_XO_R
FW643_REXT
FWPHY_DS2
FWPHY_DS0
PP3V3_FW_FWPHY
FWPHY_DS1
FW_P1_TPBIAS
NC_FW0_TPBP
PP3V3_FW_FWPHY_VP25
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM
NC_FW0_TPAP
NC_FW0_TPAN
PCIE_FW_R2D_C_N
PCIE_FW_R2D_N
PCIE_FW_R2D_C_P
PCIE_FW_R2D_P
PCIE_FW_D2R_N
PCIE_FW_D2R_P
PP3V3_FW_FWPHY_VDDA
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.0V
MIN_NECK_WIDTH=0.2 MM
MIN_LINE_WIDTH=0.4 MM
PP1V0_FW_FWPHY_AVDD
TP_FW643_SE
TP_FW643_NAND_TREE
TP_FW643_TDO
PCIE_FW_D2R_C_N PCIE_FW_D2R_C_P
PCIE_CLK100M_FW_N PCIE_CLK100M_FW_P
TP_FW643_TCK
TP_FW643_JASI_EN
TP_FW643_CE
TP_FW643_MODE_A
FW643_SCL
TP_FW643_SCIFDAIN
FW_CLKREQ_PHY_L
FW_CLK24P576M_XI
41 OF 132
<E4LABEL>
<SCH_NUM>
<BRANCH>
39 OF 101
6 7
40
6 7
39 40 41
41
6
6
6 7
39 40 41
94
94
94
94
Page 40
D
SG
G
D
S
G
D
S
IN
IN
D
SG
OUT
IN
OUT
IN
G
D
S
OUT
VCC
VCLMP
D1-
GND
D2-
D2+
D1+
FWPWR_EN
BI
BI
BI
BI
OUT
IN
S
G
D
(SYM-VER2)
G
S
(SYM-VER1)
D
GND
VOUT
ON
VIN
GND
VOUT
ON
VIN
IN
II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
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REVISION
DRAWING NUMBER
SIZE
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IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
Signal aliases required by this page:
BOM options provided by this page:
PP1V05_FW PGOOD/FW_RESET_L
3.3V FW FET
I(max) = 1.7A (85C)
FireWire Port Power Switch
- =PP3V3_FW_LATEVG_ACTIVE
(NONE)
- =PPBUS_S5_FWPWRSW (system supply for bus power)
Late-VG Protection
- =PPVP_FW_SUMNODE (power passthru summation node)
Power aliases required by this page:
Page Notes
1.05V FW FET
CRITICAL
NDS9407
SOI-HF
Q4260
5
6
7
8
4
1
2
3
0.1UF
10% X5R
25V 402
C4260
1
2
SSM6N15FEAPE
SOT563
Q4261
6
2
1
MF-LF
1/16W
5%
470K
402
R4260
1
2
330K
1/16W MF-LF 402
5%
R4261
1
2
MINISMDC110H24
1.1A-24V
CRITICAL
F4260
1 2
SM
CRITICAL
CRS08-1.5A-30V
D4260
1 2
SOT563
BC847CDXV6TXG
CRITICAL
Q4270
2
6
1
CRITICAL
BC847CDXV6TXG
SOT563
Q4270
5
3
4
MF-LF
5%
402
1/16W
330K
R4270
1
2
1/16W
5%
402
MF-LF
56K
R4271
1
2
5% 1/16W MF-LF 402
12K
R4273
1
2
PLACE_NEAR=C4360.1:2mm
MF-LF 402
5%
1K
1/16W
R4272
1
2
CRITICAL
SOT-563
DMB53D0UV
Q4275
6
2
1
SOT-563
DMB53D0UV
CRITICAL
Q4275
5
3
4
CRITICAL
SOT-563
DMB53D0UV
Q4299
6
2
1
10K
1/16W MF-LF
5%
402
R4283
1 2
19 27 31
402
CERM
10%
1UF
6.3V
C4281
1
2
CRITICAL
DMB53D0UV
SOT-563
Q4299
5
3
4
402
MF-LF
1%
1/16W
10K
R4280
1 2
1/16W MF-LF
5%
100K
402
R4281
1
2
39 40
SSM6N15FEAPE
SOT563
Q4261
3
5
4
17 25
16V X5R 402
0.1UF
10%
C4270
1
2
39 41
39
1/16W MF-LF
5%
1K
402
R4275
1
2
20 40
SOT-563
CRITICAL
DMB53D0UV
Q4276
5
3
4
SOT-563
DMB53D0UV
CRITICAL
Q4276
6
2
1
5% 1/16W MF-LF 402
100K
R4276
1
2
NOSTUFF
402
X5R
16V
10%
0.1UF
C4276
1
2
10K
402
1/16W
5%
MF-LF
R4277
1
2
8 20 40
PLACE_NEAR=J4310.1:2mm
LLP
TPD4S1394
CRITICAL
U4200
7
8
5
6
4
2 1
3
402
MF-LF
1/16W
5%
100K
R4201
1
2
PLACE_NEAR=U4200.1:2mm
0.1UF
16V X5R
10%
402
C4200
1
2
39 41 96
39 41 96
39 41 96
39 41 96
8 20 40
8 39
SOT-363
BSS8402DW
Q4262
3
5
4
402
1/16W
5%
MF-LF
10K
R4262
1
2
BSS8402DW
SOT-363
Q4262
6
2
1
402
NOSTUFF
25V X5R
0.1UF
10%
C4261
1
2
402
MF-LF
1/16W
5%
10
R4263
1
2
TPS22924
CSP
CRITICAL
U4201
C1
C2
A2 B2
A1 B1
CSP
TPS22924
CRITICAL
U4202
C1
C2
A2 B2
A1 B1
20 40
CERM
10%
1UF
6.3V 402
C4202
1
2
CERM
10%
1UF
6.3V 402
C4201
1
2
SYNC_DATE=05/29/2009
SYNC_MASTER=K19_MLB
FireWire Port Power
PP1V05_S0
FW_PLUG_DET_L
PP3V3_S0
FW_PWR_EN
PP3V3_S0
FWPWR_EN_TRI
FWPWR_EN_TRI_R
FWPWR_EN_L_DIV
FWPWR_EN
FWPWR_EN_L
FW_PWR_EN
TP_FW_LATEVG_VCLMP
FW_PORT1_TPA_P
FW_PORT1_TPB_N
FW_PWR_EN_L
FW_PORT1_TPA_N
FW_PORT1_TPB_P
FW_P1_TPBIAS
MIN_NECK_WIDTH=0.25 mm VOLTAGE=12.6V
PPBUS_FW_FWPWRSW_D
MIN_LINE_WIDTH=0.5 mm
PPBUS_FW_FWPWRSW_F
MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=12.6V
FW_DET_MIRROR
PP1V05_S0
FW_PLUG_DET
FW_P1_TPBIAS_R
FW_DET_EMIT
FW_PLUG_DET_L
PPVP_FW
PPBUS_G3H
PP3V3_FW_FWPHY
FW_CLKREQ_L
FW_CLKREQ_PHY_L
MAKE_BASE=TRUE
FW_CLKREQ_PHY_L
PP3V3_S0
P1V0_RESET_GATE
FW_RESET_L
PLT_RESET_L
PP1V0_FW_FWPHY
FW643_WAKE_L
PP1V0_FW_FWPHY
P1V0_FW_RC
FW_WAKE
PP3V3_FW_FWPHY
42 OF 132
<E4LABEL>
<SCH_NUM>
<BRANCH>
40 OF 101
6 7 10 12 13 15 17 18 20 21 23 24 25
26 40
70 73 86
6 7 17 18 19 20 21 23 24 25 26 27 28 30 34 37 40 42 46 47
48 50 51 52 54 58 62 63 68
69 72 73 80 83 84 85 87 88
99
6 7 17 18 19 20 21 23 24 25 26 27 28 30 34 37 40 42 46 47
48 50 51 52 54 58 62 63 68 69
72 73 80 83 84 85 87 88 99
6 7 10 12 13 15 17 18 20 21 23 24 25 26 40 70 73 86
6 7 41 6 7 49 65 66 67 69 70 82 86 89
6 7 39 40 41
39
40
6 7 17 18 19 20 21 23 24 25 26 27 28 30 34 37 40 42 46 47
48 50 51 52 54 58 62 63 68
69 72 73 80 83 84 85 87 88
99
6 7 39 40
6 7 39 40
6 7 39 40 41
Page 41
SC/NC
TPA+
TPA(R)
VG
VPTPB+
TPB(R)
TPB-
TPA-
CHASSIS
GND
SGD
(SYM-VER2)
G
S
(SYM-VER1)
D
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER
SIZE
D
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IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
FireWire PHY Config Straps
Page Notes
TI PHYs require 1uF even though
constrained on this page. It is
provide the appropriate constraints
Configures PHY for:
NOTE: This page is expected to contain
- 1-port Portable Power Class (0)
- Port "1" Bilingual (1394B)
Power aliases required by this page:
assumed that FireWire PHY page will
to apply to entire TPA/TPB XNets.
Termination
FW spec calls out 0.33uF
Place close to FireWire PHY
- =PPVP_FW_PORT1
- =PP3V3_FW_LATEVG
514S0605
beta-only device, there is no DC path between them (to avoid ground offset issue)
BREF should be hard-connected to logic ground for speed signaling and connection
appropriate connectors and/or to
NOTE: FireWire TPA/TPB pairs are NOT
Cable Power
(GND_FW_PORT1_VG)
(FW_PORT1_BREF)
AREF needs to be isolated from all
INPUT
NC
TPB<R>
TPB-
TPA-
TPA+
(NONE)
OUTPUT
BILINGUAL
- =GND_CHASSIS_FW_EMI_R
(NONE)
FireWire Design Guide (FWDG 0.6, 5/14/03)
1394b implementation based on Apple
the necessary aliases to map the FireWire TPA/TPB pairs to their
- =GND_CHASSIS_FW_PORT1
PORT 1
Signal aliases required by this page:
BOM options provided by this page:
properly terminate unused signals.
NC
VP
TPB+
VG
TPA<R>
When a bilingual device is connected to a
Note: Trace PPVP_FW_PORT1 must handle up to 5A
local grounds per 1394b spec
PLACE_NEAR=U4100.A6:4mm
1%
402
SIGNAL_MODEL=EMPTY
56.2
MF-LF
1/16W
R4363
1
2
1/16W
1%
402
MF-LF
4.99K
R4364
1
2
PLACE_NEAR=U4100.B6:4mm
1%
402
MF-LF
SIGNAL_MODEL=EMPTY
56.2
1/16W
R4362
1
2
25V
5% 402
CERM
220pF
C4364
1
2
1/16W
1%
402
MF-LF
56.2
SIGNAL_MODEL=EMPTY
PLACE_NEAR=U4100.B5:2mm
R4361
1
2
6.3V
10% 402
CERM-X5R
0.33UF
C4360
1
2
1/16W
1% MF-LF
56.2
SIGNAL_MODEL=EMPTY
402
R4360
1
2
50V
10%
603-1
X7R
0.1uF
PLACEMENT_NOTE=Place C4319 close to connector pin 5.
C4319
1
2
1/16W
5%
402
MF-LF
1M
R4319
1
2
50V
10% 402
X7R
0.01UF
C4314
1
2
SM
FERR-250-OHM
CRITICAL
L4310
1 2
F-RT-TH
1394B-M97
CRITICAL
J4310
1
10 11 12 13
2
3
4
5
6
7
8
9
1/16W
1%
402
MF-LF
10K
R4381
1
2
1/16W
1%
402
MF-LF
10K
R4382
1
2
1/16W
1%
402
MF-LF
10K
R4380
1
2
SOT-363
BSS8402DW
Q4300
3
5
4
SOT-363
BSS8402DW
Q4300
6
2
1
1/16W
5%
402
MF-LF
330K
R4312
1
2
1/16W
5%
402
MF-LF
470K
R4311
1
2
FireWire Ports
SYNC_MASTER=K19_MLB
SYNC_DATE=05/29/2009
MIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.5 mm VOLTAGE=33V
PPVP_FW_PORT1_F
MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
MAKE_BASE=TRUE
VOLTAGE=12.6V
PPVP_FW_CPS
FW_P1_TPBIAS
MAKE_BASE=TRUE
FW_PORT1_TPB_P
MAKE_BASE=TRUE
NC_FW0_TPBN
MAKE_BASE=TRUE
NC_FW2_TPAP
MAKE_BASE=TRUE
NC_FW0_TPAN
NC_FW0_TPBIAS NC_FW2_TPBIAS NC_FW0_TPAN
NC_FW2_TPAP
MAKE_BASE=TRUE
NC_FW2_TPAN
MAKE_BASE=TRUE
NC_FW0_TPAP
MAKE_BASE=TRUE
NC_FW0_TPBIAS
MAKE_BASE=TRUE
NC_FW2_TPBIAS
NC_FW0_TPBN
NC_FW2_TPBN
NC_FW0_TPBP
MAKE_BASE=TRUE
FW_PORT1_TPA_N
MAKE_BASE=TRUE
FW_PORT1_TPA_P
MAKE_BASE=TRUE
FW_PORT1_TPB_N
FW_PORT1_TPB_C
PPVP_FW
MAKE_BASE=TRUE
FWPHY_DS1
MAKE_BASE=TRUE
FWPHY_DS2
MAKE_BASE=TRUE
FWPHY_DS0
FWPHY_DS2
FWPHY_DS1
FWPHY_DS0
MAKE_BASE=TRUE
NC_FW0_TPBP
NC_FW2_TPAN
NC_FW0_TPAP
MAKE_BASE=TRUE
NC_FW2_TPBN
NC_FW2_TPBP
MAKE_BASE=TRUE
NC_FW2_TPBP
PPVP_FW_CPS
PP3V3_FW_FWPHY
CPS_EN_L
CPS_EN_L_DIV
PPVP_FW
FW_PORT1_TPB_N
FW_PORT1_TPB_P
FW_PORT1_TPA_N
PLACE_NEAR=U4100.A5:2mm
FW_PORT1_TPA_P
PP3V3_FW_FWPHY
FW_PORT1_AREF
FW_PORT1_TPB_P
FW_PORT1_TPB_N
FW_PORT1_TPA_N
FW_PORT1_TPA_P
43 OF 132
<E4LABEL>
<SCH_NUM>
<BRANCH>
41 OF 101
39 41
39 40
39 40 41 96
6
39 41 96
6
39 41
39 41 96
39 41
6
39 41
39 41 96
6
39 41
6
39 41
6
39 41 96
39 41
6
39 41
6
39 41 96
6
39 41
6
39 41 96
39 40 41 96
39 40 41 96
39 40 41 96
6 7
40 41
39 41
39 41
39 41
39 41
39 41
39 41
6
39 41 96
6
39 41
6
39 41 96
6
39 41
6
39 41
6
39 41
39 41
6 7
39 40 41
6 7
40 41
39 40 41 96
39 40 41 96
39 40 41 96
39 40 41 96
6 7
39 40 41
39 40 41 96
39 40 41 96
39 40 41 96
39 40 41 96
Page 42
S
G
D
SYM_VER-1
SYM_VER-1
OUT
OUT
IN
IN
NC
NC NC
IN
OUT
OUT
B_SD
A_SD
A_INP A_INN
A_OUTN
A_OUTP
VDD
GND
THRM
I2C_ADDR
I2C_EN
B_INN B_INP
B_OUTN B_OUTP
EN AUTOPW_EN
SCL_CTL SDA_CTL
PAD
SYM_VER-1
IN
IN
IN
SYM_VER-1
OUT
OUT
IN
IN
IN
D
SG
D
SG
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER
SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
DESCRIPTION
REFERENCE DES
BOM OPTION
QTY
PART NUMBER
CRITICAL
NOTE: 3.3V must be S0 if 5V is S3 or S5 to
338S0848 (PS8515A2)
(All 4 C’s)
- RDRV:NO stuffs bypass path (neither IC or associated parts stuffed)
- RDRV:8511 stuffs PS8511A & associated parts (STRAPS TBD!!!)
BOMOPTIONs:
- RDRV:8515A1&RDRV:8515A2 stuffs PS8515A & associated parts
PS8515A:
Addr: 0x94(Wr)/0x95(Rd)
ensure the drive is unpowered in S3/S5.
8 B_PRE (IPD) 20 A_BST# (IPU)
PS8511A / PS8515A Straps
18 B_EQ (IPD)
PS8511A:
PIN NAME 9 A_PRE (IPD)
10 B_BST# (IPU)
19 A_EQ (IPD)
516S0616
(C4514,
(IPD)
(IPU)
(IPD)
(IPD)
NOTE: Internal pulls are ~150K
(All 4 C’s)
SATA Redriver
(All 4 C’s)
Redriver Bypass Path
support debug sense resistor.
Indicates disc presence
SATA ODD Connector
Alias together if no sense R.
J4500 connection separated to
516S0687
x_SD pins are outputs
(All 4 R’s, 2 C’s)
ODD Power Control
SATA HDD/IR/SIL Connector
C4519 & R4510)
321
4
8765
Q4590
CRITICAL
TPCP8102
23V1K-SM
1
2
C4501
20% 10V CERM
0.1UF
402
PLACE_NEAR=L4500.1:2mm
1
2
C4502
PLACE_NEAR=L4500.2:2mm
20% 10V CERM
0.1UF
402
21
L4500
0603
CRITICAL
FERR-70-OHM-4A
PLACE_NEAR=J4501.9:3mm
4 3
21
FL4525
CRITICAL
DLP11S
90-OHM-100MA
43
2 1
FL4520
CRITICAL
DLP11S
90-OHM-100MA
21
C4525
402
CERM
16V10%
0.01UF
21
C4526
402
CERM
0.01UF
16V10%
21
C4520
0.01UF
402
CERM
16V10%
21
C4521
0.01UF
10%
CERM
16V 402
17 93
17 93
17 93
17 93
9
87
65
43
2221
20
2
19
1817
1615
1413
1211
10
1
J4501
CRITICAL
54722-0224
F-ST-SM
2
1
C4532
10% 16V X7R-CERM 402
0.1UF
1
2
R4532
MF-LF
1/16W
5%
10
402
2 1
R4531
5%
1/16W
4.7
402
MF-LF
2
1
C4531
0.001UF
402
CERM
50V
10%
6
46
6
44
21
C4516
RDRV:8511&RDRV:8515A1&RDRV:8515A2
16V10% 402
CERM
0.01UF
21
C4515
RDRV:8511&RDRV:8515A1&RDRV:8515A2
402
16V
CERM
10%
0.01UF
6
45
16
6
21
18
19
10
8
13
3
7
9
5
4
11
12
17
20
15 14
1 2
U4510
TQFN
PS8515A-A2
CRITICAL RDRV:8515A2
21
C4511
RDRV:8511&RDRV:8515A1&RDRV:8515A2
16V10% 402
CERM
0.01UF
21
C4510
RDRV:8511&RDRV:8515A1&RDRV:8515A2
402
16V10%
CERM
0.01UF
43
2 1
FL4501
CRITICAL
DLP11S
90-OHM-100MA
17 25
2
1
C4519
CERM
RDRV:8511&RDRV:8515A1&RDRV:8515A2
0.01UF
402
16V
10%
PLACE_NEAR=U4510.16:3mm
2
1
C4514
RDRV:8511&RDRV:8515A1&RDRV:8515A2
1UF
402
CERM-X5R
6.3V
10%
PLACE_NEAR=U4510.16:3mm
2
1
R4590
5%
402
MF-LF
1/16W
33K
1
2
R4510
RDRV:8511&RDRV:8515A1&RDRV:8515A2
10K
5%
402
1/16W MF-LF
17 93
17 93
21
C4518
0.01UF
10%
CERM
RDRV:8511&RDRV:8515A1&RDRV:8515A2
16V 402
21
C4517
0.01UF
CERM
16V 402
RDRV:8511&RDRV:8515A1&RDRV:8515A2
10%
21
C4513
0.01UF
10%
CERM
402
16V
RDRV:8511&RDRV:8515A1&RDRV:8515A2
21
C4512
0.01UF
10%
CERM
402
16V
RDRV:8511&RDRV:8515A1&RDRV:8515A2
43
2 1
FL4502
CRITICAL
90-OHM-100MA
DLP11S
17 93
17 93
17 25 26 28 30 32 47 48 63 88 94
17 25 26 28 30 32 47 48 63 88 94
1
2
R4511
NO STUFF
10K
402
5% 1/16W MF-LF
1
2
R4512
RDRV:8515A1&RDRV:8515A2
10K
402
5% 1/16W MF-LF
21
C4585
RDRV:NO
0.01UF
10%
CERM
16V 402
21
C4586
0.01UF
RDRV:NO
10%
CERM
402
16V
21
C4580
SIGNAL_MODEL=EMPTY
RDRV:NO
0.01UF
10%
CERM
16V 402
21
C4581
RDRV:NO
0.01UF
10%
CERM
402
16V
21
R4580
402
RDRV:NO
SIGNAL_MODEL=EMPTY
51.1
MF-LF
1/16W
1%
21
R4581
402
RDRV:NO
51.1
1%
1/16W
MF-LF
21
R4585
RDRV:NO
0
5%
MF-LF
402
1/16W
9
87
65
43
2
1615
1413
1211
10
1
J4500
CRITICAL
F-ST-SM
54722-0164
21
R4586
RDRV:NO
0
5%
MF-LF
402
1/16W
1
2
R4515
RDRV:8515A1&RDRV:8515A2
10K
MF-LF
1/16W
5%
402
1
2
R4516
NO STUFF
10K
MF-LF
1/16W 402
5%
1
2
R4517
NO STUFF
10K
MF-LF
1/16W
5%
402
1
2
R4518
NO STUFF
10K
402
5% 1/16W MF-LF
2 1
R4513
RDRV:8515A1&RDRV:8515A2
MF-LF
1/16W
402
5%
0
2 1
R4514
RDRV:8515A1&RDRV:8515A2
0
5%
1/16W
402
MF-LF
2
1
R4520
NO STUFF
5% 1/16W MF-LF
10K
402
2
1
R4519
NO STUFF
MF-LF
1/16W
5%
402
10K
20
21
C4582
SIGNAL_MODEL=EMPTY
RDRV:NO
402
50V
CERM
5%
10PF
21
C4583
RDRV:NO
402
50V
CERM
5%
10PF
SIGNAL_MODEL=EMPTY
1 2
SM
XW4599
1 2
SM
XW4598
4
5
3
Q4596
SOT563
SSM6N15FEAPE
2
1
R4597
MF-LF
402
100K
5%
1/16W
1
2
6
Q4596
SSM6N15FEAPE
SOT563
2
1
R4596
MF-LF
1/16W
5%
402
100K
21
R4595
1/16W
5%
402
MF-LF
100K
2
1
C4595
0.068UF
10V
10%
402
CERM
21
C4596
10%
0.01UF
16V
CERM
402
SATA 3GB/S REDRIVER, LOW POWER
1338S0769 U4510 CRITICAL
RDRV:8511
SATA 3GB/S REDRIVER, LOW POWER
1338S0778
RDRV:8515A1
CRITICALU4510
SYNC_DATE=10/01/2009
SYNC_MASTER=T27_REF
SATA Connectors
ODD_PWR_EN
SATARDRVR_A_I2C_ADDR
VOLTAGE=5V
MIN_NECK_WIDTH=0.4mm
MIN_LINE_WIDTH=0.6mm
PP5V_S0_HDD_FLT
PP5V_S3
PP1V5_S3RS0
SATA_HDD_R2D_C_P
SATA_HDD_R2D_NORDRV_P
SATA_HDD_R2D_C_N
SATA_HDD_R2D_NORDRV_N
SATA_HDD_D2R_UF_N
SATA_HDD_D2R_UF_P
SATARDRVR_A_A_SD SATARDRVR_A_B_SD
SATA_HDD_D2R_P
SATA_HDD_D2R_N
PP5V_S3_IR_R
MIN_LINE_WIDTH=0.5mm MIN_NECK_WIDTH=0.2mm VOLTAGE=5V
SATA_HDD_R2D_P
SATA_HDD_R2D_N
PP5V_S3
SATA_ODD_D2R_C_P
SATA_ODD_D2R_C_N
SATA_ODD_D2R_P
SATA_ODD_D2R_N
SATA_ODD_R2D_C_N
SATA_ODD_R2D_C_P
PP5V_SW_ODD
SATA_ODD_D2R_UF_P
SATA_ODD_D2R_UF_N
SATA_ODD_R2D_P SATA_ODD_R2D_N
ODD_PWR_EN_L
ODD_PWR_SS
PP5V_SW_ODD_R
PP3V3_S0
SATA_ODD_R2D_UF_N
SATA_ODD_R2D_UF_P
SYS_LED_ANODE
SATA_HDD_R2D_UF_P
SATA_HDD_R2D_UF_N
SATA_HDD_D2R_C_P
SATA_HDD_D2R_C_N
SATA_HDD_D2R_RDRV_IN_N SATA_HDD_R2D_RDRV_OUT_N
SATA_HDD_D2R_RDRV_IN_P
SATARDRVR_A_I2C_EN
SATA_HDD_R2D_RDRV_OUT_P
SATARDRVR_A_AUTOPWR_EN
SATARDRVR_A_I2C_SCL SATARDRVR_A_I2C_SDA
IR_RX_OUT
SYS_LED_ANODE_R
PP3V3_S0
SMC_ODD_DETECT
SMBUS_PCH_DATA
SMBUS_PCH_CLK
PP1V5_S3RS0
SATARDRVR_A_I2C_SCL
SATARDRVR_A_B_SD
SATARDRVR_A_A_SD SATARDRVR_A_I2C_EN
SATARDRVR_A_I2C_ADDR
SATARDRVR_A_I2C_SDA
SATA_HDD_D2R_NORDRV_N
SATA_HDD_D2R_NORDRV_P
SATA_HDD_D2R_RDRV_OUT_N
SATA_HDD_R2D_RDRV_IN_P
SATA_HDD_D2R_RDRV_OUT_P
SATA_HDD_R2D_RDRV_IN_N
SATARDRVR_A_EN
ODD_PWR_EN_LS5V_L
PP5V_S0
VOLTAGE=5V
MIN_LINE_WIDTH=0.6mm
PP5V_S0_HDD_R
MIN_NECK_WIDTH=0.4mm
VOLTAGE=5V
MIN_LINE_WIDTH=0.6mm MIN_NECK_WIDTH=0.4mm
PP5V_SW_ODD
PP5V_SW_ODD_R
MIN_NECK_WIDTH=0.4mm
MIN_LINE_WIDTH=0.6mm VOLTAGE=5V
45 OF 132
<E4LABEL>
<SCH_NUM>
<BRANCH>
42 OF 101
42
6
6 7
31 33 42 43 44 46 54 56 58 61 66 67
72 82
101
6 7
13 16 31
42 72 73 99
99
99
42
42
6
6
93
6
93
6 7
31 33 42
43 44 46 54
56 58 61 66
67 72 82
101
6
93
6
93
6
42 56
99
99
6
93
6
93
42
6 7
17 18 19 20 21 23 24 25
26 27 28 30 34 37 40 42 46 47
48 50 51 52 54 58 62 63 68
69 72 73 80 83 84 85 87 88
99
99
99
99
99
6
93
6
93
93
93
93
42
93
42
42
6
6 7
17 18 19 20 21 23 24 25
26 27 28 30 34 37 40 42 46 47
48 50 51 52 54 58 62 63 68 69
72 73 80 83 84 85 87 88 99
6 7
13 16 31 42 72 73 99
42
42
42
42
42
42
93
93
93
93
6 7
23 47 52 54 68 69 70 72 86
88
6
42 56 42
Page 43
OUT
BI
BI
SYM_VER-1
IN OUT
IN
SYM_VER-1
BI
BI
OUT
IOIONC
GND
VBUS
NC
IOIONC
GND
VBUS
NC
OUT2
TPAD
GND
OUT1
OC1*
EN2
EN1 OC2*
IN
VCC
GND
SELOE*
D+ D-
Y+ Y-
M+ M-
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER
SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
Port Power Switch
SEL=0 Choose SMC
Left USB Port A
Left USB Port B
USB/SMC Debug Mux
SEL=1 Choose USB
We can add protection to 5V if we want, but leaving NC for now
Place L4600 and L4605 at connector pin
FERR-220-OHM-2.5A
0603
CRITICAL
L4605
1 2
CASE-B2-SM
POLY-TANT
100UF
20%
CRITICAL
6.3V
C4696
1
2
10UF
20% 603
X5R
6.3V
C4695
1
2
0.1UF
402
CERM
10V
20%
C4691
1
2
35
36 93
36 93
CERM
402
10V
0.1UF
SMC_DEBUG_YES
20%
C4650
1
2
MF-LF
5%
10K
402
1/16W
R4650
1
2
CRITICAL
DLP11S
90-OHM-100MA
L4600
1 2
34
6
45 46 47
6
45 46 47
45
402
5%
0
MF-LF
1/16W
SMC_DEBUG_NO
R4651
1 2
SMC_DEBUG_NO
0
402
5% 1/16W MF-LF
R4652
1 2
16V 402
0.01uF
CERM
20%
C4605
1
2
402
CERM
16V
0.01uF
20%
C4615
1
2
CRITICAL
0603
FERR-220-OHM-2.5A
L4615
1 2
90-OHM-100MA
CRITICAL
DLP11S
L4610
1 2
34
6.3V X5R
10UF
603
20%
C4617
1
2
POLY-TANT CASE-B2-SM
6.3V
100UF
CRITICAL
20%
C4616
1
2
35 93
35 93
36
RCLAMP0502N
CRITICAL
SLP1210N6
D4600
1
5 42 3
6
SLP1210N6
RCLAMP0502N
CRITICAL
D4610
1
5 42 3
6
603
10UF
X5R
20%
6.3V
C4690
1
2
F-RT-TH-M97-4
CRITICAL
USB
J4600
1 2 3 4
5 6
7 8
F-RT-TH-M97-4
CRITICAL
USB
J4610
1 2 3 4
5 6
7 8
CRITICAL
MSOP
TPS2064DGN
Q4690
3
4
1
2
8
5
7
6
9
402
1/16W
5.1K
MF-LF
5%
R4690
1
2
10% 10V
402
X5R
0.47UF
C4692
1
2
TQFN
SMC_DEBUG_YES
CRITICAL
PI3USB102ZLE
U4650
6
7
3
4
5
8
10
9
2
1
External USB Connectors
SYNC_DATE=06/15/2009
SYNC_MASTER=K17_REF
USB_EXTB_OC_L
USB2_EXTA_MUXED_N
USB2_EXTA_MUXED_P
PP3V42_G3H
USB_PWR_EN
MIN_NECK_WIDTH=0.375 mm
PP5V_S3_RTUSB_A_F
MIN_LINE_WIDTH=0.5 mm VOLTAGE=5V
USB2_LT1_N
USB_EXTB_N
USB_LT2_P
USB_LT2_N
MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.375 mm VOLTAGE=5V
PP5V_S3_RTUSB_B_ILIM
VOLTAGE=5V
MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.375 mm
PP5V_S3_RTUSB_B_F
USB2_LT1_P
USB_EXTA_N
USB_EXTA_P
SMC_RX_L SMC_TX_L
PM_SLP_S4_L
USB_EXTB_P
PP5V_S3_RTUSB_A_ILIM
MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.375 mm VOLTAGE=5V
USB_DEBUGPRT_EN_L
PP5V_S3
USB_EXTA_OC_L
46 OF 132
<E4LABEL>
<SCH_NUM>
<BRANCH>
43 OF 101
99
99
6 7
17 21 23 45
46 47 48 49 53 64
65 66 73
6
6
99
6
99
6
99
6
6
99
18 31 45 46 72 73
6 7
31 33 42 44 46 54 56 58 61 66 67 72
82
101
Page 44
BI BI
VCC
P1.0/D+ P1.1/D­P1.2/VREG P1.3/SSEL P1.4/SCLK
P1.5/SMOSI
P1.6/SMISO
P0.0
P0.1 INT0/P0.2 INT1/P0.3
TIO1/P0.6
NC
TIO0/P0.5
INT2/P0.4
VSSPAD
THRML
IN
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER
SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
IR SUPPORT
35 93
35 93
1UF
X5R 402-1
10% 10V
C4803
1
2
CY7C63803-LQXC
QFN
OMIT
CRITICAL
U4800
5 4 3
8
9 10 20 21 22 23 24
7 6
12 13 15 16 17 18 19
25
2 1
14
11
X7R-CERM
10%
0.1UF
402
16V
C4801
1
2
0.001UF
CERM 402
10% 50V
C4804
1
2
100
MF-LF
402
5%
1/16W
R4800
1 2
6
42
SYNC_MASTER=K19_MLB
SYNC_DATE=05/29/2009
Front Flex Support
IR_RX_OUT_RC
IR_RX_OUT
IR_VREF_FILTER
PP5V_S3
USB_IR_P
DIFFERENTIAL_PAIR=USB2_IR
USB_IR_N
DIFFERENTIAL_PAIR=USB2_IR
48 OF 132
<E4LABEL>
<SCH_NUM>
<BRANCH>
P/N 338S0633
44 OF 101
6 7
31 33 42 43 46 54 56 58 61 66 67 72
82
101
Page 45
IN
IN
IN
OUT
OUT
OUT
IN
IN
OUT
IN IN IN IN IN IN IN IN
IN
OUT
IN
OUT
BI
IN
IN
OUT
BI OUT
IN
IN
OUT
IN
OUT OUT OUT OUT
IN
IN
IN
IN
IN IN
IN
IN
IN IN
IN
IN
IN
IN
OUT
IN
IN
BI BI BI BI BI BI
OUT OUT
OUT
IN
IN
OUT
IN
IN
BI
BI
OUT
IN
OUT
OUT
NC
OUT
OUT
OUT
NC
NC NC NC
NC
NC
NC
NC NC
NC NC NC
NC
NC
NC
NC
NC NC
NC NC
NC
NC NC
IN
OUT
OUT
OUT
P13 P14 P15 P16 P66
P10 P11 P12
P17
P20 P21 P22 P23 P24 P25 P26 P27
P30 P31 P32 P33 P34
P36 P37
P40 P41 P42 P43 P44 P45 P46 P47
P50 P51 P52
P60 P61 P62 P63 P64 P65
P67
P70 P71 P72 P73 P74 P75 P76 P77
P80 P81
P84 P85 P86
P90 P91 P92 P93 P94 P95 P96 P97
P35
P83
P82
(1 OF 3)
PA5
PA4
PA0 PA1 PA2 PA3
PA6 PA7
PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7
PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7
PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7
PE0 PE1 PE2 PE3 PE4 PF0
PF1 PF2 PF3 PF4 PF5 PF6 PF7
PG0 PG1 PG2 PG3 PG4 PG5 PG6 PG7
PH0 PH1 PH2 PH3 PH4 PH5
(2 OF 3)
RES*
NMI
VSS
VCLVCC
NC
MD2
MD1
ETRST
AVSS
AVREF
AVCC
EXTAL
XTAL
(3 OF 3)
OUT
NC
INBI
BI BI BI BI
IN IN IN
OUT
BI
IN IN IN IN
BI
BI
IN
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER
SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
NOTE: P94 and P95 are shorted, P95 could be spare.
(OC)
(OC)
(OC)
Otherwise, TP/NC okay (was ISENSE_CAL_EN)
(OC)
(DEBUG_SW_1)
(OC)
(OC) (OC)
(OC)
(See below)
(OC)
(OC)
(OC)
(OC)
(OC)
(OC) (OC)
(OC)
(OC)
If SMS interrupt is not used, pull up to SMC rail.
NOTE: SMS Interrupt can be active high or low, rename net accordingly.
SMC_PB3: SMC_IG_THROTTLE_L for MG systems.
those designated as inputs require pull-ups.
pins designed as outputs can be left floating,
NOTE: Unused pins have "SMC_Pxx" names. Unused
22UF
CERM
805
20%
6.3V
C4902
1
2
6
18 47
6
46 47 65
6
46 53
0.47UF
CERM-X5R
402
10%
6.3V
PLACE_NEAR=U4900.E1:3mm
C4907
1
2
402
20% 10V CERM
0.1UF
C4903
1
2
0.1UF
CERM
402
20% 10V
PLACE_NEAR=U4900.M12:3mm
C4920
1
2
4.7
MF-LF
5%
1/16W
402
PLACE_NEAR=U4900.M12:3mm
R4999
1 2
0.1UF
CERM 402
20% 10V
C4904
1
2
PLACE_NEAR=U4900.L3:4mm
SM
XW4900
12
18 25
68
0.1UF
CERM 402
20% 10V
C4905
1
2
18
73
25 27 73 87
46
0.1UF
CERM 402
20% 10V
C4906
1
2
50
49
50
49
49
49
49
46 50
46 64 65
6
43 45 46 47
6
43 45 46 47
66 73
48 56 97
10K
MF-LF
5%
1/16W
402
R4909
1
2
6
47
6
47
10K
MF-LF 402
5% 1/16W
R4901
1
2
10K
MF-LF 402
5% 1/16W
R4902
1
2
NO STUFF
0
MF-LF 402
5% 1/16W
R4903
1
2
10K
MF-LF 402
5% 1/16W
R4998
1
2
43
46 64
18
6
42
46
20
46
52
52
6
46
6
46
6
46
6
46
52
52
55
55
46 50
55
46 49
46 49
46 50
6
46 47
46
6
46 47
6
46 47
6
46 47
46 53 64
6
48 64 65 97
6
48 64 65 97
6
33 48 54 97
6
33 48 54 97
48 51 97
48 51 97
46
46
6
46
46 50
6
43 45 46 47
6
43 45 46 47
46
80
6
17 47
28 30 46
6
18 27
6
47
17
6
18 47
80
55
18 46 73
6
46 64
6
46
46
8
OMIT
H8S2117
LGA-HF
U4900
B12 A13 A12 B13 D11 C13 C12 D10
D13 E11 D12 F11 E13 E12 F13 E10
A9 D9 C8 B7 A8 D8 D7 D6
D4 A5 B4 A1 C2 B2 C1 C3
G2 F3 E4
L13 K12 K11 J12 K13 J10 J11 H12
N10 M11 L10 N11 N12 M13 N13 L12
A7 B6 C7 D5 A6 B5 C6
J4 G3 H2 G1 H4 G4 F4 F1
OMIT
H8S2117
LGA-HF
U4900
N3 N1 M3 M2 N2 L1 K3 L2
B8 C9
B9 A10 C10 B10 C11 A11
G11 G13 F12 H13 G10 G12 H11 J13
M10
N9 K10
L8
M9
N8
K9
L7
K1 J3 K2 J1 K4 K5
N5 M6 L5 M5 N4 L4 M4
M8 N7 K8 K7 K6 N6 M7 L6
E2 F2 J2 A4 B3 C4
H8S2117
LGA-HF
OMIT
U4900
M12
L11
L9
H3
A2
D1 H1
E5
E3
D3
B1M1H10
E1
D2
L3
F10
B11
C5
A3
17
46 46
6
17 47 87 94
6
17 47 87 94
6
17 47 87 94
6
17 47 87 94
6
17 47 87 94
27
27 94
54
48 51 81 97
6
18 31 73 85
18 31 43 46 72 73
18 46
46
48 51 81 97
48 56 97
46
SYNC_DATE=06/15/2009
SYNC_MASTER=K17_REF
SMC
TP_SMC_PF5
SMBUS_SMC_A_S3_SCL
SMC_PROCHOT
MEM_EVENT_B_L
PM_SYSRST_L
SYS_ONEWIRE
SMC_ODD_DETECT
SMC_EXCARD_CP
SMC_EXCARD_OC_L
SPI_DESCRIPTOR_OVERRIDE_L
PM_RSMRST_L
SMC_PROCHOT_3_3_L
TP_SMC_RSTGATE_L ALL_SYS_PWRGD
TP_SMC_P24
SMC_BMON_MUX_SEL
LPC_AD<0>
LPC_AD<2> LPC_AD<3> LPC_FRAME_L
LPC_SERIRQ
TP_SMC_P41
SMBUS_SMC_MGMT_SDA
SMC_GFX_THROTTLE_L SMC_SYS_KBDLED
SMC_TX_L SMC_RX_L SMBUS_SMC_0_S0_SCL
SMC_PM_G2_EN
SMC_ADAPTER_EN
SMC_BIL_BUTTON_L SMC_CPU_ISENSE
SMC_CPU_VSENSE SMC_GPU_ISENSE SMC_GPU_VSENSE SMC_DCIN_ISENSE SMC_PBUS_VSENSE
SMC_WAKE_SCI_L
SMC_TX_L
SMBUS_SMC_MGMT_SCL
SMC_LRESET_L
LPC_PWRDWN_L
PM_CLKRUN_L
SMC_PA0
USB_DEBUGPRT_EN_L
SMC_RUNTIME_SCI_L
SMC_FAN_0_CTL SMC_FAN_1_CTL
SMC_FAN_1_TACH NC_SMC_FAN_2_TACH NC_SMC_FAN_3_TACH
SMC_GPU_1V8_ISENSE
SMC_P1V5S3_ISENSE SMC_GFX_VSENSE SMC_CPU_HI_ISENSE
SMC_CASE_OPEN SMC_TCK
SMC_TDO
SMC_SYS_LED
SMS_INT_L SMBUS_SMC_BSA_SDA SMBUS_SMC_BSA_SCL SMBUS_SMC_A_S3_SDA
SMBUS_SMC_B_S0_SDA SMBUS_SMC_B_S0_SCL
SMC_THRMTRIP
MIN_NECK_WIDTH=0.1 MM
PP3V3_S5_SMC_AVCC
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.25 MM
SMC_NMI
SMC_TRST_L
SMC_KBC_MDE
SMC_EXTAL
SMC_XTAL
SMC_RESET_L
LPC_CLK33M_SMC
SMC_BATT_ISENSE SMC_GFX_ISENSE
PP3V42_G3H
SMC_MD1
SMC_VCL
PP3V3_S5_AVREF_SMC
TP_SMC_EXCARD_PWR_EN
RSMRST_PWRGD
CPUIMVP_VR_ON PM_PWRBTN_L
NC_ESTARLDO_EN
LPC_AD<1>
SMS_PWRDN
SMS_Y_AXIS
SMS_X_AXIS
NC_SMC_FAN_3_CTL
NC_SMC_FAN_2_CTL
SMC_GFX_OVERTEMP_L
SMC_IG_THROTTLE_L
NC_ALS_GAIN
SMC_TMS G3_POWERON_L
MEM_EVENT_A_L
PM_BATLOW_L
GND_SMC_AVSS
SMC_CPUVTT_ISENSE
SMS_Z_AXIS
SMC_FAN_0_TACH
SMC_LID
SMC_TDI
SMC_RX_L
PM_SLP_S3_L
SMC_ONOFF_L SMC_BC_ACOK
SMBUS_SMC_0_S0_SDA
SMC_CLK32K
PM_SLP_S5_L
PM_SLP_S4_L
SMC_P92
49 OF 132
<E4LABEL>
<SCH_NUM>
<BRANCH>
45 OF 101
46
46
46 49
6
46
46
46
46
6 7
17 21 23 43 46 47 48 49
53 64 65 66 73
6
46
20 25 46
46 49 50
46
Page 46
D
S G
CD
GND
NC
OUT
IN
OUT
IN
OUT
BI
IN
D
S G
GND
OUT
IN
OUT
IN
02
D
SG
NC
IN
IN
IN
E
Q2
C
BD
Q1
GS
OUT
G
D
S
OUT
IN
G
D
S
G
D
S
BI
OUT
OUT
NC7
NC6
NC5
NC4
NC2 NC3
OUT
VDD
NC0 NC1
VIO
GND
IN
NC NC NC NC
NC NC NC NC
OUT
D
SG
NC NC
NC
OUT
PART NUMBER
ALTERNATE FOR
PART NUMBER
BOM OPTION
REF DES
COMMENTS:
TABLE_ALT_HEAD
TABLE_ALT_ITEM
TABLE_5_ITEM
CRITICAL BOM OPTION
TABLE_5_HEAD
PART#
DESCRIPTION
QTY
REFERENCE DESIGNATOR(S)
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER
SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
SMC AVREF Supply
TO/FROM SMC
FROM DIMMS
TO CPU
SMC Crystal Circuit
TO CPU
TO SMC
SMC FSB to 3.3V Level Shifting
CPU PM_EXTTS_L / MEM_EVENT_L Level Shifting
System (Sleep) LED Circuit
To support timed wake-up events in G3Hot
Debug Power "Buttons"
SMC G3Hot 32kHz Oscillator
SMC Reset "Button" / Brownout Detect
0.1uF
CERM
402
20% 10V
C5000
1
2
SSM6N15FEAPE
SOT563
Q5059
3
5
4
0.47UF
CERM-X5R 402
10%
6.3V
C5020
1
2
0.01UF
CERM 402
10% 16V
C5026
1
2
10uF
X5R 603
20%
6.3V
C5025
1
2
SMC_EXCARD
5% 1/16W MF-LF
402
0
R5095
1 2
10K
MF-LF
4025%
1/16W
R5070
1 2
100K
MF-LF
4025%
1/16W
R5071
1 2
10K
MF-LF
4025%
1/16W
R5073
1 2
100K
MF-LF
4025%
1/16W
R5074
1 2
2.0K
MF-LF
4025%
1/16W
NO STUFF
R5075
1 2
1/16W
5% 402
MF-LF
100K
R5076
1 2
1/16W
5% 402
MF-LF
10K
R5077
1 2
1/16W
5% 402
MF-LF
10K
R5078
1 2
MF-LF1/16W
5% 402
10K
R5079
1 2
1/16W
5% 402
MF-LF
10K
R5080
1 2
10K
5%
1/16W
402
MF-LF
R5085
1 2
10K
MF-LF
4025%
1/16W
R5086
1 2
10K
MF-LF
4025%
1/16W
R5088
1 2
NCP303LSN
CRITICAL
SOT23-5-HF
U5000
5
3
2
4
1
100K
MF-LF
4025%
1/16W
R5090
1 2
6
45 47 65
45
10 20 91
OMIT
0
MF-LF 603
5% 1/10W
SILK_PART=SMC_RST
R5001
1
2
PLACEMENT_NOTE=Place R5015 on top side
OMIT
0
603
SILK_PART=PWR_BTN
MF-LF
1/10W
5%
R5015
1
2
3.3K
MF-LF
402
5%
1/16W
R5062
1 2
10 68 91
45
SSM6N15FEAPE
SOT563
Q5059
6
2
1
1/16W
5% 402
MF-LF
100K
R5091
1 2
CRITICAL
REF3333
SOT23-3
VR5020
3
1 2
45 46 19 25
1K
MF-LF 402
5% 1/16W
R5000
1
2
10K
MF-LF
4025%
1/16W
R5089
1 2
1/16W
5% 402
MF-LF
10K
R5081
1 2
1/16W
5%
402
MF-LF
0
R5010
1 2
CRITICAL
20.00MHZ
5X3.2-SM
Y5010
1
2
50V
5%
402
CERM
15pF
C5011
1 2
5%
402
15pF
CERM
50V
C5010
1 2
1/16W
5% 402
MF-LF
470K
R5087
1 2
SN74LVC1G02
SOT553-5
U5001
1
2
3
5
4
SOT563
SSM6N15FEAPE
Q5032
3
5
4
1/16W
5% 402
MF-LF
10K
R5093
1 2
100K
MF-LF
4025%
1/16W
R5094
1 2
10K
MF-LF
4025%
1/16W
R5072
1 2
53
6
45 46 53
45
1/16W
1%
402
MF-LF
1.47K
R5032
1
2
1/16W
1%
402
MF-LF
523
R5031
1
2
1/16W
1%
402
MF-LF
20
R5030
1
2
SOT-563
DMB54D0UV
CRITICAL
Q5030
5
3
6 4
21
6
42
DMB53D0UV
SOT-563
Q5060
5
3
4
100K
MF-LF 402
5% 1/16W
R5061
1
2
DMB53D0UV
SOT-563
Q5060
6
2
1
10K
MF-LF 402
5% 1/16W
R5060
1
2
45
PLACEMENT_NOTE=Place R5016 on bottom side
SILK_PART=PWR_BTN
0
MF-LF
603
5%
1/10W
OMIT
R5016
1
2
28 30 45 46
SOT-363
2N7002DW-X-G
Q5040
3
5
4
10K
MF-LF
402
5%
1/16W
R5040
1
2
SOT-363
2N7002DW-X-G
Q5040
6
2
1
1/16W
5%
402
MF-LF
10K
R5042
1
2
0
MF-LF
402
5%
1/16W
R5044
1 2
28 30 45 46
10 91
10 91
SMC_OSC_YES
6.3V
20%
CERM
4.7UF
603
C5002
1
2
SMC_OSC_YES
10V
20% 402
CERM
0.1UF
C5003
1
2
OMIT
CRITICAL
32.768KHZ-9-3.6V SG-3040LC-SM
U5010
6
2 3 4 5
8 9 10 11
7
12
1
SMC_OSC_YES
0603
FERR-120-OHM-0.2A
L5010
1 2
22
1/16W
5%
402
MF-LF
NO STUFF
R5011
1 2
1/16W
5%
402
MF-LF
0
R5012
1 2
18 94
MF-LF
4025%
1/16W
SMC_EXCARD_NOT
100K
R5092
1 2
45
SSM6N15FEAPE
SOT563
Q5032
6
2
1
6
45 46 53
0.01UF
CERM
402
10% 16V
C5001
1
2
SMC Support
SYNC_MASTER=K18_SENSORS
SYNC_DATE=06/29/2009
OSC,XTAL,32.768KHZ,LF,HF
SMC_OSC_YES
U5010
1
197S0350
CRITICAL
353S1912353S1381
ALL
Intersil ISL60002-33
NC_ALS_GAIN
MAKE_BASE=TRUE
PP3V42_G3H
SMC_GFX_VSENSE SMC_CPU_HI_ISENSE SMC_CPUVTT_ISENSE
TP_SMC_P41
SMC_EXCARD_OC_L
SMC_GPU_1V8_ISENSE
SMC_P1V5S3_ISENSE
TP_SMC_PF5
MAKE_BASE=TRUE
MAKE_BASE=TRUE
TP_SMC_P41
MAKE_BASE=TRUE
SMC_CPU_HI_ISENSE SMC_CPUVTT_ISENSE
MAKE_BASE=TRUE
SMC_GFX_ISENSE
TP_SMC_P24
TP_SMC_PF5
MIN_NECK_WIDTH=0.1 mm
PP3V3_S5_AVREF_SMC
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.4 mm
SMC_RESET_L
MAKE_BASE=TRUE
SMC_GFX_VSENSE
SMS_INT_L
SMC_IG_THROTTLE_L
MAKE_BASE=TRUE
SMC_P1V5S3_ISENSE
MAKE_BASE=TRUE
SMC_GFX_ISENSE SMC_GPU_1V8_ISENSE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
TP_SMC_P24
PP3V42_G3H
SYS_LED_ANODE
SMC_TPAD_RST_L
PP3V42_G3H
SYS_LED_ILIM
SMC_EXTAL
SMC_SYS_LED
MIN_NECK_WIDTH=0.1 mm
MIN_LINE_WIDTH=0.4 mm
GND_SMC_AVSS
VOLTAGE=0V
SMC_MANUAL_RST_L
TP_SMC_RSTGATE_L
PM_CLK32K_SUSCLK
MIN_LINE_WIDTH=0.2 MM
PP3V42_G3H_SMC_CLK_F
MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.425V
SMS_INT_L
MAKE_BASE=TRUE
MAKE_BASE=TRUE
SMC_IG_THROTTLE_L
SMC_BMON_MUX_SEL SMC_BMON_MUX_SEL
MAKE_BASE=TRUE
SMC_BC_ACOK
MAKE_BASE=TRUE
SMC_BC_ACOK
TP_SMC_RSTGATE_L
MAKE_BASE=TRUE
PCH_GPIO10
PP3V42_G3H
SMC_BC_ACOK
SMS_INT_L
SMC_BIL_BUTTON_L
SMC_TCK
SMC_TDO
SMC_TMS
SMC_PA0
SMC_CLK32K
SMC_CLK32K_R
SYS_LED_L_VDIV
PP5V_S3
SYS_LED_L
MAKE_BASE=TRUE
NC_SMC_FAN_3_TACHNC_SMC_FAN_3_TACH
SMC_ONOFF_L
SMC_TPAD_RST
NC_ALS_GAIN
SMC_THRMTRIP
PP3V3_S0
SMC_PROCHOT_3_3_L
SMC_PROCHOT
CPU_PROCHOT_BUF
CPU_PROCHOT_L
CPU_PROCHOT_L_R
PM_THRMTRIP_L
NC_SMC_FAN_2_CTL
MAKE_BASE=TRUE
NC_SMC_FAN_2_CTL
NC_SMC_FAN_2_TACH
MAKE_BASE=TRUE
NC_SMC_FAN_2_TACH
NC_SMC_FAN_3_CTL
MAKE_BASE=TRUE
NC_SMC_FAN_3_CTL
MAKE_BASE=TRUE
NC_ESTARLDO_ENNC_ESTARLDO_EN
SMC_XTAL_R
SMC_XTAL
SMC_LID
SMC_RX_L
PP3V3_S0
PP3V3_S0
PM_EXT_TS_L<0>
MEM_EVENT_A_L
PM_EXT_TS_L<1>
MEM_EVENT
MEM_EVENT_A_L
MAKE_BASE=TRUE
SMC_ONOFF_L
PP3V42_G3H
PP3V3_S0
SMC_EXCARD_OC_L
SMC_ADAPTER_EN SMC_CASE_OPEN
SMC_EXCARD_CP PM_SLP_S5_L PM_SLP_S4_L
MEM_EVENT_B_L
SMC_ONOFF_L G3_POWERON_L
SMC_TX_L
SYS_ONEWIRE
SMC_TDI
SMC_P92
50 OF 132
<E4LABEL>
<SCH_NUM>
<BRANCH>
46 OF 101
6
45 46
6 7
17 21 23 43 45 46 47 48
49 53 64 65 66 73
45 46 49
45 46 49
45 46 50
6
45 46
45 46 50
45 46 50
45 46
6
45 46
45 46 49
45 46 50
45 46 50
45 46
45 46
6
45
45 46 49
45 46
20 25 45 46
45 46 50
45 46 50
45 46 50
45 46
6 7
17 21 23 43 45 46 47 48
49 53 64 65 66 73
6 7
17 21 23 43 45 46 47 48
49 53 64 65 66 73
45
45 49 50
45 46
45 46
20 25 45 46
45 46 49 45 46 49
45 46 64 65 45 46 64 65
45 46
6 7
17 21 23 43 45 46 47 48
49 53 64 65 66 73
45 46 64 65
45 46
6
45 64
6
45 47
6
45 47
6
45 47
45
6 7 31 33 42 43
44 54 56 58
61 66 67 72
82
101
6
45 46
6
45 46
6
45 46
6 7
17 18 19 20 21 23 24 25
26 27 28 30 34 37 40 42 46 47
48 50 51 52 54 58 62 63 68 69
72 73 80 83 84 85 87 88 99
6
45 46
6
45 46
6
45 46
6
45 46
6
45 46
6
45 46
6
45 46
45
45 53 64
6
43 45 47
6 7
17 18 19 20 21 23 24 25
26 27 28 30 34 37 40 42 46 47
48 50 51 52 54 58 62 63 68 69
72 73 80 83 84 85 87 88 99
6 7
17 18 19 20 21 23 24 25
26 27 28 30 34 37 40 42 46 47
48 50 51 52 54 58 62 63 68 69
72 73 80 83 84 85 87 88 99
6 7
17 21 23 43 45 46 47
48 49 53 64 65 66 73
6 7
17 18 19 20 21 23 24 25
26 27 28 30 34 37 40 42 46 47
48 50 51 52 54 58 62 63 68 69
72 73 80 83 84 85 87 88 99
45 46
18 45 73
45
45
18 45
18 31 43 45 72 73
45
6
45 46 53
45
6
43 45 47
45 64
6
45 47
45
Page 47
OUT
IN
E0/NC0
SCL
SDA
E2 E1
WC*
VCC
VSS
IN
BI
NC
IN
IN OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT IN
OUT IN OUT
IN
BI BI
OUT
IN
BI
IN
IN
OUT
BI
BI
IN
OUT
IN
OUT
IN
IN
OUT
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER
SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
Read: 0xAD 0xAF
Write: 0xAC 0xAE
LPC+SPI Connector
EFI Debug ROM
SPI Bus Series Termination
516S0573
PLACE_NEAR=J5100.12:5mm
47
402
MF-LF
1/16W
5%
LPCPLUS
R5126
1
2
57
PLACE_NEAR=R5127.2:5mm
47
MF-LF
5%
1/16W
402
R5122
1 2
1/16W
5%
MF-LF
402
15
PLACE_NEAR=U1800.AY1:5mm
R5112
1 2
17 94
PLACE_NEAR=J5100.9:5mm
47
LPCPLUS
5% 1/16W MF-LF 402
R5127
1
2
0
402
MF-LF
1/16W
5%
LPCPLUS
PLACE_NEAR=J5100.11:5mm
R5128
1
2
EFI_DEBUG
M24M01-R
SO8N
CRITICAL
U5101
2
3
1
6
5
8
4
7
MF-LF
5% 1/16W
402
0
EFI_DEBUG
R5101
1
2
MF-LF
5% 1/16W
402
0
NO STUFF
R5104
1
2
MF-LF
5% 1/16W
402
0
NO STUFF
R5102
1
2
1/16W
5% MF-LF
402
0
EFI_DEBUG
R5103
1
2
20% 10V CERM
0.1UF
402
EFI_DEBUG
C5101
1
2
17 25 26 28 30 32 42 48 63 88 94
17 25 26 28 30 32 42 48 63 88 94
6
43 45 46
6
45
6
45
6
45 46
55909-0374
CRITICAL
LPCPLUS
M-ST-SM
J5100
1
10
11
12
13
14
15
16
17
18
19
2
20
21
22
23
24
25
26
27
28
29
3
30
31
32
33
34
4
5
6
7
8
9
6
20
6
43 45 46
6
45
6
45 46 65
6
45 46
6
45 46
6
27 87 94
6
47
6
17 45 87 94
6
18 45
6
47
6
17 45 87 94
6
17 45 87 94
6
45 46
6
18 45
6
17 45
6
47
6
47
6
20 57
6
17 45 87 94
6
17 45 87 94
6
27 94
57
PLACE_NEAR=U1800.AV3:5mm
402
MF-LF
1/16W
5%
15
R5110
1 2
17 94
57
PLACE_NEAR=U1800.BA2:5mm
1/16W
5%
MF-LF
402
15
R5111
1 2
17 94
57
PLACE_NEAR=U6100.2:5mm
15
402
MF-LF
5%
1/16W
R5123
1 2
17 94
PLACE_NEAR=R5125.2:5mm
47
402
1/16W
5%
MF-LF
R5120
1 2
PLACE_NEAR=J5100.14:5mm
47
402
MF-LF
1/16W
5%
LPCPLUS
R5125
1
2
PLACE_NEAR=R5126.2:5mm
1/16W
47
MF-LF
5%
402
R5121
1 2
LPC+SPI Debug Connector
SYNC_DATE=06/23/2009
SYNC_MASTER=K17_MLB
SPI_ALT_CLK
SPIROM_USE_MLB
SMC_TX_L
SMC_TRST_L SMC_MD1
LPCPLUS_RESET_L SMC_TDO
SMC_TMS
LPC_FRAME_L PM_CLKRUN_L
SPI_ALT_MISO
SPI_ALT_MOSI
LPC_AD<1>
LPC_AD<0>
LPCPLUS_GPIO
SMC_RX_L
SMC_NMI
SMC_RESET_L
SMC_TCK
SMC_TDI
LPC_PWRDWN_L
LPC_SERIRQ
SPI_ALT_CS_L
LPC_AD<3>
LPC_AD<2>
LPC_CLK33M_LPCPLUS
PP5V_S0
PP3V42_G3H
PP3V3_S0
SMBUS_PCH_CLK
SPI_MOSI
SPI_MISO
SPI_CLK
DEBUGROM_E2
SMBUS_PCH_DATA
SPI_CLK_R
SPI_CS0_R_L
SPI_CS0_L
SPI_ALT_MISO SPI_ALT_MOSI SPI_ALT_CLK SPI_ALT_CS_L
SPI_MLB_MOSI
SPI_MLB_CLK
SPI_MLB_CS_L
SPI_MLB_MISO
SPI_MOSI_R
DEBUGROM_E1
51 OF 132
<E4LABEL>
<SCH_NUM>
<BRANCH>
47 OF 101
6 7
23 42 52 54 68 69 70 72
86 88
6 7
17 21 23 43 45 46 48 49
53 64 65 66 73
6 7
17 18 19 20 21 23 24 25
26 27 28 30 34 37 40 42 46 48
50 51 52 54 58 62 63 68 69
72 73 80 83 84 85 87 88 99
94
94
94
6
47
6
47
6
47
6
47
Page 48
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER
SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
Mikey
HDD Redriver Control A
(Write: 0xD2 Read: 0xD3)
PCH "SMLink 0" Connections
U1800
(Write: 0x90 Read: 0x91)
Ibex Peak-M
U1800
Ibex Peak-M
(MASTER)
access PCH & CPU via PECI.
SMLink 1 is slave port to
PCH "SMLink 1" Connections
LED BACKLIGHT
U4510
(Write: 0x94 Read: 0x95)
PCH SMBus "0" Connections
J2900
(WRITE: 0x58 READ: 0x59)
(Write: 0xA0 Read: 0xA1)
SO-DIMM "B"
SMC "B" SMBus Connections
SMC "A" SMBus Connections
SO-DIMM "A"
SMC
(Write: 0x98 Read: 0x99)
EMC1414-A: U5570
CPU Temp
(Write: 0x72 Read: 0x73)
(Write: 0x90 Read: 0x91)
NOTE: SMC RMT bus remains powered and may be active in S3 state
EMC1414-A: U5550
GPU Temp (Ext)
(Write: 0x98 Read: 0x99)
Battery Manager - (Write: 0x16 Read: 0x17)
Battery Temp - (Write: 0x90 Read: 0x91)
Battery
Battery LED Driver - (Write: 0x36 Read: 0x37)
J5800
SMC "Battery A" SMBus Connections
(MASTER)
U4900
U4900
Sensor ADC A
(Write: 0x10 Read: 0x11)
CK505 (Clock)
J3401
SMC "Management" SMBus Connections
U5930
ALS
Trackpad
(Write: 0x9E Read: 0x9F)
GT216: U8000
GPU Temp (Int)
SMC "0" SMBus Connections
(MASTER)
U2900
Ibex Peak-M
(MASTER)
SMC
U4900
SMC
SMC
(MASTER)
U4900
J6955
ISL6258 - U7000
(See Table)
Battery
Battery Charger
(Write: 0x12 Read: 0x13)
(MASTER)
U1800
U6800
J3100
U2700
(MASTER)
(Write: 0x72 Read: 0x73)
J2600 & J2650
(MASTER)
XDP Connectors
SMC
The bus formerly known as "Battery B"
U4900
U2901
U5101
VRef DACs
U9701
Margin Control
(Write: 0x98 Read: 0x99)
(Write: 0x30 Read: 0x31)
(Write: 0xAC/AE Read: 0xAD/AF)
EFI Debug Serial
(Write: 0xA4 Read: 0xA5)
4.7K
MF-LF 402
5% 1/16W
R5291
1
2
4.7K
MF-LF
402
5%
1/16W
R5290
1
2
402
4.7K
1/16W
5% MF-LF
R5261
1
2
4.7K
1/16W
5%
402
MF-LF
R5260
1
2
1K
MF-LF
5%
1/16W
402
R5280
1
2
1/16W
1K
5%
402
MF-LF
R5281
1
2
MF-LF
1K
402
5%
1/16W
R5270
1
2
402
MF-LF
1/16W
5%
1K
R5271
1
2
4.7K
5% 1/16W
402
MF-LF
R5251
1
2
4.7K
402
5%
MF-LF
1/16W
R5250
1
2
MF-LF
402
5%
1/16W
8.2K
R5210
1
2
8.2K
1/16W 402
5% MF-LF
R5211
1
2
MF-LF 402
1/16W
8.2K
NO STUFF
5%
R5221
1
2
402
5%
1/16W
8.2K
MF-LF
NO STUFF
R5220
1
2
MF-LF
1/16W
5%
0
402
R5223
1 2
0
5% 1/16W MF-LF
402
R5222
1 2
MF-LF
1/16W 402
5%
1K
R5201
1
2
402
5%
MF-LF
1K
1/16W
R5200
1
2
K18 SMBus Connections
SYNC_DATE=06/18/2009
SYNC_MASTER=K18_SENSORS
SMBUS_PCH_DATA
SMBUS_PCH_DATA
SMBUS_PCH_CLK
SMBUS_PCH_CLK
SMBUS_SMC_MGMT_SDA
SMBUS_SMC_MGMT_SCL
MAKE_BASE=TRUE
SMBUS_SMC_BSA_SCL
SMBUS_SMC_A_S3_SDA
SMBUS_PCH_CLK SMBUS_PCH_DATA
PP3V3_S0
SMBUS_SMC_A_S3_SDA
SMBUS_SMC_A_S3_SCL
SMBUS_PCH_DATA
SMBUS_PCH_CLK
SMBUS_PCH_CLK SMBUS_PCH_DATA
SMBUS_SMC_BSA_SDA
SMBUS_SMC_BSA_SCL
SMBUS_SMC_BSA_SCL
SMBUS_SMC_0_S0_SCL
SMBUS_SMC_B_S0_SCL SMBUS_SMC_B_S0_SDA
SMBUS_SMC_A_S3_SDA
MAKE_BASE=TRUE
SMBUS_PCH_CLK
SMBUS_PCH_DATA
SMBUS_PCH_CLK
SMBUS_PCH_CLK
MAKE_BASE=TRUE
SMBUS_SMC_0_S0_SDA
SMBUS_SMC_0_S0_SCL SMBUS_SMC_0_S0_SDA
SMBUS_SMC_A_S3_SCL
MAKE_BASE=TRUE
SMBUS_SMC_0_S0_SCL
SMBUS_SMC_MGMT_SCL
PP3V3_S3
SMBUS_PCH_CLK
PP3V3_S3
SMBUS_SMC_BSA_SDA
MAKE_BASE=TRUE
SMBUS_SMC_BSA_SDASMBUS_SMC_BSA_SDA
SMBUS_SMC_MGMT_SDA
SMBUS_SMC_B_S0_SDA
SMBUS_PCH_DATA
PP3V42_G3H
SMBUS_SMC_MGMT_SCL
MAKE_BASE=TRUE
SMBUS_SMC_MGMT_SDA
MAKE_BASE=TRUE
PP3V3_S0
SMBUS_SMC_0_S0_SDA
SMBUS_SMC_0_S0_SCL
SMBUS_SMC_BSA_SCL
SMBUS_SMC_0_S0_SDA
MAKE_BASE=TRUE
SMBUS_SMC_A_S3_SCL
SMBUS_SMC_A_S3_SDA
SMBUS_SMC_A_S3_SCL
SMBUS_SMC_B_S0_SCL
PP3V3_S0
SMBUS_PCH_DATA
SMBUS_PCH_DATA
SMBUS_PCH_CLK SMBUS_PCH_DATA
SML_PCH_0_DATA
MAKE_BASE=TRUE
MAKE_BASE=TRUE
SML_PCH_0_CLK
PP3V3_S0
PP3V3_S0
SML_PCH_1_CLK
MAKE_BASE=TRUE
SML_PCH_1_DATA
MAKE_BASE=TRUE
MAKE_BASE=TRUE
SMBUS_SMC_B_S0_SCL SMBUS_SMC_B_S0_SDA
MAKE_BASE=TRUE
SMBUS_PCH_CLK
MAKE_BASE=TRUE
SMBUS_PCH_DATA
MAKE_BASE=TRUE
52 OF 132
<E4LABEL>
<SCH_NUM>
<BRANCH>
48 OF 101
17 25 26 28 30 32
42 47 48
63 88 94
17 25 26 28 30 32
42 47 48
63 88 94
17 25 26 28 30 32
42 47 48
63 88 94
17 25 26 28 30 32
42 47 48
63 88 94
45 48 56 97
45 48 56 97
6
33
45 48 54
97
17 25 26 28 30 32 42 47
48 63 88 94
17 25 26 28 30 32 42 47
48 63 88 94
6 7
17 18 19 20 21 23 24 25
26 27 28 30 34 37 40 42 46 47
48 50 51 52 54 58 62 63 68
69 72 73 80 83 84 85 87 88
99
6
33 45 48
54 97
6 33 45 48 54
97
17 25 26 28 30 32
42 47 48
63 88 94
17 25 26 28 30 32
42 47 48
63 88 94
17 25 26 28 30 32
42 47 48
63 88 94 17 25 26
28 30 32
42 47 48
63 88 94
6
45 48
64 65 97
6
45 48
64 65 97
6
45 48
64 65 97
45 48 51 81 97
45 48 51 97
45 48 51 97
17 25 26 28 30 32
42 47 48
63 88 94
17 25 26 28 30 32
42 47 48
63 88 94
17 25 26 28 30 32
42 47 48
63 88 94
17 25 26 28 30 32
42 47 48
63 88 94
45
48 51
81 97
45 48
51
81
97
45 48
51
81 97
6
33
45 48 54
97
45
48 51
81
97
45 48 56 97
6 7 8
17 20 31 32 33 34 35 36 48 50 53
54 55 72 73 87
101
17 25 26 28 30 32
42 47 48
63 88 94
6 7 8
17 20 31 32 33 34 35 36 48 50 53
54 55 72 73 87
101
6
45 48
64 65 97
6
45 48 64
65 97
45 48 56 97
45 48 51 97
17 25 26 28 30 32
42 47 48
63 88 94
6 7
17 21 23 43 45 46 47 49
53 64 65 66 73
45
48 56
97
45
48 56
97
6 7
17 18 19 20 21 23 24 25
26 27 28 30 34 37 40 42 46 47
48 50 51 52 54 58 62 63 68
69 72 73 80 83 84 85 87 88
99
45 48 51 81 97
45 48 51 81 97
6
45 48 64
65 97
45 48 51 81 97
6
33
45 48 54
97
6
33
45 48 54
97
45 48 51 97
6 7
17 18 19 20 21 23 24 25
26 27 28 30 34 37 40 42 46 47
48 50 51 52 54 58 62 63 68
69 72 73 80 83 84 85 87 88
99
17 25 26 28 30 32
42 47 48
63 88 94
17 25 26 28 30 32
42 47 48
63 88 94
17 25 26 28 30 32
42 47 48
63 88 94 17 25 26
28 30 32
42 47 48
63 88 94
17 94
17 94
6 7
17 18 19 20 21 23 24 25
26 27 28 30 34 37 40 42 46 47
48 50 51 52 54 58 62 63 68
69 72 73 80 83 84 85 87 88
99
6 7
17 18 19 20 21 23 24 25
26 27 28 30 34 37 40 42 46 47
48 50 51 52 54 58 62 63 68
69 72 73 80 83 84 85 87 88
99
17 94
17 94
45
48 51
97
45
48 51
97
17 25 26 28 30 32 42 47
48 63 88 94
17 25 26 28 30 32 42 47
48 63 88 94
Page 49
OUT
N-CHN
S
D
G
P-CHN
G
D
S
OUT
OUT
IN
VER 1
VCC
A
1
0
B1
GND
B0
SEL
IN
OUT
IN
V+
REFIN+
IN-
OUT
GND
OUT
V+
REFIN+
IN-
OUT
GND
OUT
IN
OUT
OUT
IN
OUT
TABLE_5_ITEM
CRITICAL BOM OPTION
TABLE_5_HEAD
PART#
DESCRIPTION
QTY
REFERENCE DESIGNATOR(S)
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER
SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
EDP for PPVIN_S5_CPU_IMVP_ISNS_R = 5.867 amps for K18.
GPU Voltage Sense / Filter
Rthevenin = 4504 ohms
REGULATOR SIDE:
GFX Voltage Sense / Filter
CPU Voltage Sense / Filter
LOAD SIDE:
Monitors battery discharge
GAIN: 50X
U5303 only senses current up to 6.6A
current from battery to PBUS
Enables PBUS VSense divider when high.
DCIN Current Sense Filter
PBUS Voltage Sense & Filter
GAIN: 500X
CPU VCore High Side Current Sensor
BMON Current Sense - Entire circuit must be near SMC (U4900)
402
1/16W
100K
5%
MF-LF
R5315
1
2
45
27.4K
1%
1/16W
402
MF-LF
PLACE_NEAR=U4900.M13:5mm
R5385
1
2
PLACE_NEAR=U4900.M13:5mm
0.22UF
6.3V
20%
X5R 402
C5385
1
2
5.49K
MF-LF
1%
1/16W
402
PLACE_NEAR=U4900.M13:5mm
R5386
1
2
FDG6332CG
SC70-6
Q5315
6
2
1
FDG6332CG
SC70-6
Q5315
3
5
4
MF-LF
100K
402
1/16W
5%
R5316
1
2
PLACE_NEAR=U4900.K9:5mm
X5R
20%
6.3V 402
0.22UF
C5399
1
2
SM
PLACEMENT_NOTE=Place near U1000
XW5399
1 2
PLACE_NEAR=U4900.K9:5mm
MF-LF
1%
402
1/16W
4.53K
R5399
1 2
45 46
CERM
20% 402
10V
0.1uF
BMON_ENG
C5369
1
2
45
402
16V CERM-X5R
0.022UF
10%
PLACE_NEAR=U4900.N13:5mm
C5390
1
2
45 46
402
MF-LF
1/16W
45.3K
1%
PLACE_NEAR=U4900.N13:5mm
R5391
1 2
5%
402
BMON_ENG
100K
1/16W MF-LF
R5371
1
2
NC7SB3157P6XG
SC70
BMON_ENG
U5313
43
1
2
6
5
MF-LF
1/16W
5%
402
0
BMON_PROD
R5330
12
65
20%
0.1uF
10V 402
BMON_ENG
CERM
C5318
1
2
65 99
65 99
SC70
INA213
BMON_ENG
U5323
2
5
4
6
1
3
45 46
402
PLACE_NEAR=U4900.L7:5mm
0.22UF
20%
6.3V X5R
C5335
1
2
MF-LF
402
1/16W
1%
4.53K
PLACE_NEAR=U4900.L7:5mm
R5335
1 2
0.1UF
CERM 402
20% 10V
C5388
1
2
INA213
SC70
U5388
2
5
4
6
1
3
0.001
1206
MF
1W
1%
OMIT
R5388
123
4
7
68
6 7
40 49 65 66 67 69 70 82
86 89
45
0.22UF
20%
PLACE_NEAR=U4900.N11:5mm
402
X5R
6.3V
C5359
1
2
4.53K
PLACE_NEAR=U4900.N11:5mm
1%
1/16W
402
MF-LF
R5359
1 2
45
PLACE_NEAR=U4900.N12:5mm
402
X5R
6.3V
0.22UF
20%
C5380
1
2
4.53K
MF-LF
1%
402
1/16W
PLACE_NEAR=U4900.N12:5mm
R5380
1 2
65
PLACEMENT_NOTE=Place near U8000
SM
XW5359
1 2
45
4.53K
1/16W MF-LF
1%
402
PLACE_NEAR=U4900.M11:5mm
R5309
1 2
PLACE_NEAR=U4900.M11:5mm
6.3V
20%
X5R 402
0.22UF
C5309
1
2
PLACEMENT_NOTE=Place near U1000
SM
XW5309
1 2
SYNC_MASTER=K18_SENSORS
SYNC_DATE=06/29/2009
Current & Voltage Sensing
102S0858
1
R5388
CRITICAL
RES,0.010 OHM,1%,1/2W,1206
GND_SMC_AVSS
SMC_BATT_ISENSE
BMON_AMUX_OUT
PM_SLP_S3_L_R
PPBUS_G3H
SMC_GPU_VSENSE
CHGR_CSO_R_N
BMON_INA_OUT
PPBUS_CPU_IMVP_ISNS
GND_SMC_AVSS
SMC_CPU_HI_ISENSE
PBUSVSENS_EN_L
SMC_DCIN_ISENSE
CPUVSENSE_IN
PPVCORE_S0_CPU
SMC_GFX_VSENSE
GND_SMC_AVSS
SMC_CPU_VSENSE
GND_SMC_AVSS
PPVCORE_GPU
GND_SMC_AVSS
GND_SMC_AVSS
GPUVSENSE_IN
CHGR_BMON
CHGR_CSO_R_P
CHGR_AMON
GND_SMC_AVSS
SMC_BMON_MUX_SEL
GFXVSENSE_IN
PBUSVSENS_EN_DIV
PPBUS_G3H
PPBUS_G3H_VSENSE
MIN_NECK_WIDTH=0.20 mm
MIN_LINE_WIDTH=0.20 mm
VOLTAGE=6V
SMC_PBUS_VSENSE
CPUVCORE_HISIDE_IOUT
ISNS_CPU_N
ISNS_CPU_P
PP3V42_G3H
PP3V42_G3H
PPVCORE_S0_GFX
53 OF 132
<E4LABEL>
<SCH_NUM>
<BRANCH>
49 OF 101
45 46 49 50
72 73
45 46 49 50
6 7
12 15 68
45 46 49 50
45 46 49 50
6 7
75 82
45 46 49 50
45 46 49 50
45 46 49 50
6 7
40 49 65 66 67 69 70 82
86 89
99
99
6 7
17 21 23 43 45 46 47 48
49 53 64 65 66 73
6 7
17 21 23 43 45 46 47 48
49 53 64 65 66 73
6 7
13 24 69
Page 50
OUT
IN
OUT
OUT
IN
IN
OUT
IN
IN
IN
IN
V+ V-
THRM
V+ V-
THRM
V+ V-
THRM
V+ V-
THRM
V+ V-
THRM
V+ V-
THRM
IN
OUT
IN
OUT
OUT
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER
SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
Gain: 1.4x
GFX VCore Current Sense
GPU VCore Current Sense
Gain: 140x
Gain: 243x
Gain: 431x
CPUVTT 1.05V Current Sense
GAIN: 140X
CPU & MEM 1.5V S3 (DDR) Current Sense
1.8V FB Current Sense
CPU VCore Load Side Current Sense / Filter
Gain: 3X
1/16W
4.53K
MF-LF
1%
402
PLACE_NEAR=U4900.L10:5mm
R5411
1 2
MF-LF
1/16W
1%
1M
402
SIGNAL_MODEL=EMPTY
R5417
1 2
45 46
PLACE_NEAR=U4900.N8:5mm
402
6.3V X5R
20%
0.22UF
C5490
1
2
PLACE_NEAR=U4900.N8:5mm
402
MF-LF
1/16W
1%
4.53K
R5440
1 2
NOSTUFF
50V
10%
CERM
402
SIGNAL_MODEL=EMPTY
470PF
C5441
1 2
MF-LF
1%
1/16W
1M
SIGNAL_MODEL=EMPTY
402
R5441
1 2
1/16W
1%
4.12K
MF-LF
402
R5443
1 2
402
MF-LF
1%
1M
1/16W
R5442
1
2
NOSTUFF
50V
470PF
402
CERM
10%
C5442
1
2
67 99
21
R5444
1%
4.12K
MF-LF
402
1/16W
1%
MF-LF
402
1/16W
2.32K
R5415
1 2
45
6.3V X5R 402
20%
C5453
1
2
0.22UF
PLACE_NEAR=U4900.N10:5mm
4.53K
1/16W
1%
402
PLACE_NEAR=U4900.N10:5mm
R5453
1 2
MF-LF
45 46
6.3V
20%
402
X5R
PLACE_NEAR=U4900.L12:5mm
0.22UF
C5479
1
2
MF-LF
4.53K
402
1%
1/16W
PLACE_NEAR=U4900.L12:5mm
R5479
1 2
10V
20%
0.1UF
402
CERM
C5444
1
2
10%
470PF
402
CERM
50V
SIGNAL_MODEL=EMPTY
C5443
1 2
NOSTUFF
1/16W
402
MF-LF
1%
1M
SIGNAL_MODEL=EMPTY
R5483
1 2
69 99
67 99
45 46
402
6.3V X5R
20%
0.22UF
PLACE_NEAR=U4900.M9:5mm
C5480
1
2
402
MF-LF
1/16W
1%
4.53K
R5487
1 2
PLACE_NEAR=U4900.M9:5mm
NOSTUFF
470PF
50V
10%
CERM
402
SIGNAL_MODEL=EMPTY
C5471
1 2
402
MF-LF
1M
1%
1/16W
SIGNAL_MODEL=EMPTY
R5471
1 2
1%
MF-LF
402
1/16W
7.15K
R5474
1 2
402
MF-LF
1%
1M
1/16W
R5472
1
2
NOSTUFF
50V
470PF
402
CERM
10%
C5472
1
2
MF-LF
1/16W
1%
402
7.15K
R5473
1 2
70 99
70 99
0.1UF
CERM
10V
20%
402
C5454
1
2
69 99
7.15K
1/16W
402
MF-LF
1%
R5481
1 2
7.15K
1/16W
402
MF-LF
1%
R5484
1 2
402
MF-LF
1%
1M
1/16W
R5482
1
2
NOSTUFF
50V
470PF
402
CERM
10%
C5482
1
2
CRITICAL
0.001
1%
1W MF-1 0612
R5413
123
4
2.32K
1/16W
402
MF-LF
1%
R5414
1 2
12 68 91
OPA2333
DFN
CRITICAL
U5430
3
2
1
9
4
8
OPA2333
DFN
CRITICAL
U5430
5
6
7
9
4
8
OPA2333
DFN
CRITICAL
U5410
5
6
7
9
4
8
8
4
9
1
2
3
U5410
CRITICAL
DFN
OPA2333
CRITICAL
OPA2333
6
9
4
8
7
5
DFN
U5450
CRITICAL
OPA2333
DFN
3
1
8
4
9
2
U5450
1/16W
1%
MF-LF
402
21
R5459
2.87K
MF-LF
1/16W
1%
10K
1 2
402
R5450
1% 1/16W MF-LF
402
21
R5452
20.0K
470PF
10% 50V
CERM
NOSTUFF
402
21
C5457
21
R5409
402
MF-LF
2.87K
1%
1/16W
21
R5410
MF-LF
1/16W
1%
10K
402
21
R5412
402
4.02K
1/16W MF-LF
1%
PLACE_NEAR=U4900.L8:5mm
0.22UF
20%
X5R 402
6.3V
C5411
1
2
21
C5407
470PF
10% 50V
CERM
402
NOSTUFF
82
45 46
MF-LF
1/16W
402
1%
4.53K
PLACE_NEAR=U4900.L8:5mm
R5418
1 2
NOSTUFF
470PF
CERM
10% 50V
402
SIGNAL_MODEL=EMPTY
C5412
1 2
10V
0.1UF
20%
CERM 402
C5410
1
2
1M
1/16W MF-LF
1%
402
R5416
1
2
NOSTUFF
470PF
10%
402
50V
CERM
C5409
1
2
6 7
86
6 7 8
56 75 76 77 78
45
PLACE_NEAR=U4900.L10:5mm
402
20%
X5R
0.22UF
6.3V
C5408
1
2
SYNC_DATE=07/02/2009
Current Sensing
SYNC_MASTER=K18_SENSORS
CPUVCORE_IOUT
CPUISENS_N
GFXIMVP_ISNS_IOUT
GFXIMVP_CS_R_P
GFXIMVP_CS_R_N
SMC_GFX_ISENSE
ISNS_1V5_S3_N
SMC_CPUVTT_ISENSE
GND_SMC_AVSS
CPUVTTS0_CS_P
CPUVTTS0_CS_N
SMC_GPU_1V8_ISENSE
GND_SMC_AVSS
SMC_P1V5S3_ISENSE
GND_SMC_AVSS
GND_SMC_AVSS
SMC_GPU_ISENSE
GFX_ISNS_R_P
GFX_ISNS_R_N
CPUVTTISNS_R_P
CPUVTT_IOUT
CPUVTTISNS_R_N
GPUISENS_P
GPUVCORE_IOUT
ISNS_P1V8GPU_R_P
P1V8_S0GPU_IOUT
ISNS_P1V8GPU_R_N
PP3V3_S0
PP3V3_S0
ISNS_P1V8GPU_P
PP1V8R1V55_S0GPU_ISNS_R
PP1V8R1V55_S0GPU_ISNS
ISNS_P1V8GPU_N
CPUDDR_IOUT
PP3V3_S3
DDRISNS_R_N
DDRISNS_R_P
ISNS_1V5_S3_P
SMC_CPU_ISENSE
GFXIMVP6_IMON
CPUIMVP_IMON
CPUISENS_P
GPUISENS_N
54 OF 132
<E4LABEL>
<SCH_NUM>
<BRANCH>
50 OF 101
45 46 49 50
45 46 49 50
45 46 49 50
45 46 49 50
99
99
99
99
99
99
6 7
17 18 19 20 21 23 24 25
26 27 28 30 34 37 40 42 46 47
48 50 51 52 54 58 62 63 68 69
72 73 80 83 84 85 87 88 99
6 7
17 18 19 20 21 23 24 25
26 27 28 30 34 37 40 42 46 47
48 50 51 52 54 58 62 63 68
69 72 73 80 83 84 85 87 88
99
99
6 7 8
17 20 31 32 33 34 35 36 48 53 54
55 72 73 87
101
99
99
99
Page 51
BI
BI
BI
BI
ALERT*
THERM*/ADDR
DP1
SMCLK
SMDATA
VDD
DN1
DP2/DN3
DN2/DP3
GND
ALERT*
THERM*/ADDR
DP1
SMCLK
SMDATA
VDD
DN1
DP2/DN3
DN2/DP3
GND
BI
BI
BI
BI
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER
SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
CPU Proximity/CPU Die/PCH Proximity/Battery Charger Proximity
Detect CPU Die Temperature
GPU Proximity/GPU Die/Left Heat Pipe/Right Fin Stack
Detect Right Fin Stack Temperature
Write Address: 0x98
Place U5550 on bottom side under GPU
Placement note:
Read Address: 0x99
Detect GPU Die Temperature
Place U5570 under CPU
Placement note:
Detect Battery Charger Proximity Temperature
Place Q5502 on bottom side
Placement note:
Compensation for External Diode 1 only
Note: EMC1414 can perform Beta
close to battery charger circuit
Placement note:
Write Address: 0x98 Read Address: 0x99
close to the right fin stack
Place Q5503 on top side under left heat pipe near GPU
Placement note:
Detect Left Heat Pipe Temperature
Detect PCH Proximity Temperature
Placement note:
Place Q5504 under PCH
Place Q5501 on bottom side
10K
5% 1/16W MF-LF 402
R5572
1
2
402
5%
MF-LF
10K
1/16W
R5571
1
2
SOT732-3
BC846BMXXH
Q5504
1
3
2
45 48 81 97
45 48 81 97
MF-LF
402
5%
10K
1/16W
R5551
1
2
5%
402
1/16W
10K
MF-LF
R5552
1
2
402
0.1uF
20% 10V CERM
C5550
1
2
5%
47
1/16W MF-LF
402
R5550
1 2
CERM
402
50V
10%
0.0022uF
PLACE_NEAR=U5550.3:5mm
PLACE_NEAR=U5550.2:5mm
SIGNAL_MODEL=EMPTY
C5551
1
2
50V
10%
PLACE_NEAR=U5550.4:5mm
0.0022uF
CERM
402
PLACE_NEAR=U5550.5:5mm
SIGNAL_MODEL=EMPTY
C5552
1
2
79 80 99
79 80 99
BC846BMXXH
SOT732-3
Q5503
1
3
2
CRITICAL
MSOP
EMC1414-A
U5550
83
5
2
4
6
10
9
7
1
BC846BMXXH
SOT732-3
Q5501
1
3
2
EMC1414-A
MSOP
CRITICAL
U5570
83
5
2
4
6
10
9
7
1
BC846BMXXH
SOT732-3
Q5502
1
3
2
CERM
402
50V
10%
0.0022uF
PLACE_NEAR=U5570.3:5mm
PLACE_NEAR=U5570.2:5mm
SIGNAL_MODEL=EMPTY
C5571
1
2
9
99
9
99
45 48 97
45 48 97
0.1uF
20% 10V CERM 402
C5570
1
2
1/16W MF-LF
402
5%
47
R5570
1 2
0.0022uF
402
10% 50V
CERM
PLACE_NEAR=U5570.5:5mm
PLACE_NEAR=U5570.4:5mm
SIGNAL_MODEL=EMPTY
C5590
1
2
SYNC_MASTER=K18_SENSORS
SYNC_DATE=06/18/2009
Thermal Sensors
CPUTHMSNS_D2_P
CPUTHMSNS_D2_N
CPU_THERMD_P
GPUTHMSNS_D_P
GPU_TDIODE_N
SMBUS_SMC_B_S0_SCL
SMBUS_SMC_B_S0_SDA
CPUTHMSNS_THM_L CPUTHMSNS_ALERT_L
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm
PP3V3_S0_CPUTHMSNS_R
SMBUS_SMC_0_S0_SCL
GPUTHMSNS_THM_L GPUTHMSNS_ALERT_L
SMBUS_SMC_0_S0_SDA
GPU_TDIODE_P
PP3V3_S0
GPUTHMSNS_D_N
CPU_THERMD_N
PP3V3_S0
MIN_LINE_WIDTH=0.38 mm
PP3V3_S0_GPUTHMSNS_R
VOLTAGE=3.3V
MIN_NECK_WIDTH=0.25 mm
55 OF 132
<E4LABEL>
<SCH_NUM>
<BRANCH>
51 OF 101
99
99
99
6 7
17 18 19 20 21 23 24 25
26 27 28 30 34 37 40 42 46 47
48 50 51 52 54 58 62 63 68 69
72 73 80 83 84 85 87 88 99
99
6 7
17 18 19 20 21 23 24 25
26 27 28 30 34 37 40 42 46 47
48 50 51 52 54 58 62 63 68 69
72 73 80 83 84 85 87 88 99
Page 52
G
S D
G
S D
IN
OUT OUT
IN
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER
SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
518S0369
Left Fan
Right Fan
518S0369
1/16W
5%
402
MF-LF
47K
R5650
1
2
1/16W
5%
402
MF-LF
47K
R5655
1 2
1/16W
5%
402
MF-LF
47K
R5660
1
2
1/16W
5%
402
MF-LF
47K
R5665
1 2
1/16W
5%
402
MF-LF
100K
R5651
1
2
SOT-363
2N7002DW-X-G
Q5660
3
5
4
1/16W
5%
402
MF-LF
100K
R5661
1
2
SOT-363
2N7002DW-X-G
Q5660
6
2
1
M-RT-SM
78171-0004
CRITICAL
J5650
5
6
1 2 3 4
M-RT-SM
78171-0004
CRITICAL
J5660
5
6
1 2 3 4
45
45 45
45
SYNC_DATE=05/29/2009
SYNC_MASTER=K19_MLB
Fan Connectors
SMC_FAN_0_TACH
PP3V3_S0
PP5V_S0
FAN_LT_TACH
PP3V3_S0
FAN_RT_TACH
PP5V_S0
FAN_RT_PWM
SMC_FAN_0_CTL
SMC_FAN_1_TACH
SMC_FAN_1_CTL
FAN_LT_PWM
56 OF 132
<E4LABEL>
<SCH_NUM>
<BRANCH>
52 OF 101
6 7
17 18 19 20 21 23 24 25
26 27 28 30 34 37 40 42 46 47
48 50 51 52 54 58 62 63 68
69 72 73 80 83 84 85 87 88
99
6
6 7
17 18 19 20 21 23 24 25
26 27 28 30 34 37 40 42 46 47
48 50 51 52 54 58 62 63 68
69 72 73 80 83 84 85 87 88
99
6
6 6
Page 53
D
G S
P2_4
P2_6
VDD
P0_4
P0_2
P2_0
P2_2
P0_0
P2_3 P2_1 P4_7 P4_5 P4_3 P4_1 P3_7 P3_5 P3_3 P3_1 P5_7 P5_5 P5_3 P5_1
P1_1
P1_3
P1_5
P1_7
P7_7
VSSD+D-
VDD
P7_0
P1_0
P1_2
P1_4
P1_6
P5_0
P5_2
P5_4
P5_6
P3_0
P3_2
P3_4
P4_0
P4_2
P4_4
P4_6
P3_6
P2_5
P2_7
P0_3
VSS
P0_5
P0_7
P0_6
PAD
THRML
(SYM-VER2)
P0_1
Y
C
B
A
IN
OUT
IN
Y
B
A
Y
B
A
Y
B
A
NC
NC
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER
SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
PSOC USB CONTROLLER
TRACKPAD PICK BUTTONS
SMC_MANUAL_RESET LOGIC
APN 311S0406
THIS ASSUMES THERE’S A PP3V42_G3H PULL UP ON MLB
LID OPEN => SMC_LID_LC ~ 3.42V
THE TPAD BUTTONS WILL BE DISABLE
ISSP SDATA/I2C SDA
APN 337S2983
SPI HOST TO Z2
PLACE C5704, C5705 & C5706
ISSP SCLK/I2C SCL
18V BOOSTER
PSOC
3V3 LDO
IC
PIN NAME
V+
VDD
VDD
VIN
CURRENT
4MA (MAX)
14MA (MAX)
8MA (TYP)
60MA MAX
60MA MAX
80UA
10UA
R_SNS
2.55 KOHM
10 OHM
0.2 OHM
1.5 OHM
4.7 OHM
V_SNS POWER
0.0188 V
0.021 V
0.012 V
0.012 V
0.6 V
0.204 V
0.0255 V
0.255E-6 W
16.32E-6 W 36E-3 W
0.72E-3 W 96E-6 W
294E-6 W
75.2E-6 W
APN 518S0637
LID CLOSE => SMC_LID_LC < 0.50V
WHEN THE LID IS CLOSED
KEYBOARD CONNECTOR
TMP102
PLACE THESE COMPONENTS CLOSE TO J5800
TPAD BUTTONS DISABLE
USB INTERFACES TO MLB
ISOLATION CIRCUIT
VOUT
CLOSE TO U5701 CLOSE TO U5701
VDD PIN 49
KEYBOARD SCANNER
TO MLB CONNECTOR
VDD PIN 22
PLACE C5701, C5702 & C5703
U5701 CHIP DECOUPLING
SSM3K15FV
SOD-VESM-HF
Q5701
3
1
2
0.1UF
X7R-CERM 402
10% 16V
C5758
1
2
33K
MF-LF 402
5% 1/16W
R5771
1
2
33K
MF-LF 402
5% 1/16W
R5770
1
2
33K
MF-LF 402
5% 1/16W
R5769
1
2
4.7UF
X5R 603
20%
6.3V
C5706
1
2
0.1UF
X7R-CERM 402
10% 16V
C5705
1
2
100PF
CERM 402
5% 50V
C5704
1
2
0.1UF
X7R-CERM 402
10% 16V
C5703
1
2
100PF
CERM 402
5% 50V
C5702
1
2
4.7UF
X5R 603
20%
6.3V
C5701
1
2
1/16W
5%
402
MF-LF
24
R5702
1 2
OMIT
CY8C24794
MLF
CRITICAL
U5701
20
21
45544653475248
51
25182617271628
15
412
421
435644
55
3310
349
358
367
376
385
394
403
2914
3013
3112
3211
24
235722 49
19
50
1/16W
5%
402
MF-LF
24
R5701
1 2
CRITICAL
SN74LVC1G10
SC70
U5703
2
1 3 6
4
5
1.5
MF-LF
402
5%
1/16W
R5704
1 2
45 46 64
PLACEMENT_NOTE=NEAR J5713
0.1UF
CERM 402
20% 10V
C5710
1
2
1K
MF-LF
402
5%
1/16W
R5710
1 2
470
MF-LF
402
1%
1/16W
R5714
1 2
10K
MF-LF
402
1%
1/16W
R5715
1 2
FF14-30A-R11B-B-3H
F-RT-SM
J5713
31
32
1
10
11
12
13
14
15
16
17
18
19
2
20
21
22
23
24
25
26
27
28
29
3
30
4
5
6
7
8
9
CRITICAL
TC7SZ08AFEAPE
SOT665
U5726
2
1
3
5
4
CRITICAL
TC7SZ08AFEAPE
SOT665
U5727
2
1
3
5
4
CRITICAL
TC7SZ08AFEAPE
SOT665
U5725
2
1
3
5
4
0.1UF
CERM
402
20% 10V
C5725
12
WELLSPRING 1
SYNC_DATE=05/29/2009
SYNC_MASTER=K19_MLB
USB_TPAD_N
DIFFERENTIAL_PAIR=USB2_TPAD
USB_TPAD_P
DIFFERENTIAL_PAIR=USB2_TPAD
MIN_NECK_WIDTH=0.20MM
MIN_LINE_WIDTH=0.50MM
VOLTAGE=3.3V
PP3V3_S3_PSOC
NET_SPACING_TYPE=USB
DIFFERENTIAL_PAIR=USB2_TPAD
USB_TPAD_R_N
NET_PHYSICAL_TYPE=USB_85D
NET_SPACING_TYPE=USB
DIFFERENTIAL_PAIR=USB2_TPAD
USB_TPAD_R_P
NET_PHYSICAL_TYPE=USB_85D
WS_CONTROL_KEY
Z2_DEBUG3
PSOC_F_CS_L
Z2_MOSI
Z2_MISO
PSOC_MISO
TP_P4_5
TP_BOOT_CFG1
Z2_RESET
WS_KBD6
Z2_CLKIN
WS_KBD1
WS_KBD15_CAP
WS_CONTROL_KBD
PP3V42_G3H
PP3V42_G3H
WS_LEFT_SHIFT_KEY
WS_LEFT_SHIFT_KBD
PP3V3_S3
WS_LEFT_OPTION_KBD
WS_LEFT_OPTION_KEY
SMC_TPAD_RST_L
WS_LEFT_OPTION_KEY
WS_KBD23
BUTTON_DISABLE
WS_KBD15_C
WS_KBD12
PSOC_MOSI
WS_CONTROL_KEY
WS_CONTROL_KBD
SMC_LID
BUTTON_DISABLE
WS_KBD17 WS_KBD16N
WS_LEFT_SHIFT_KEY
WS_KBD8
WS_KBD1
WS_KBD2 WS_KBD3 WS_KBD4 WS_KBD5 WS_KBD6
WS_KBD18
WS_KBD17
WS_KBD14
WS_KBD11
WS_KBD10
WS_KBD21
WS_KBD20
WS_KBD19
WS_KBD23
WS_LEFT_SHIFT_KBD
PP3V42_G3H
WS_KBD_ONOFF_L
WS_LEFT_OPTION_KBD WS_CONTROL_KBD
WS_KBD7 WS_KBD8
TP_PSOC_SDA
TP_PSOC_SCL
WS_KBD11
PP3V3_S3
WS_KBD15_C WS_KBD14
WS_KBD12
WS_KBD10 WS_KBD9
WS_KBD3
NC_PSOC_P1_3
WS_KBD13
Z2_KEY_ACT_L
WS_KBD7
WS_KBD16N
WS_KBD18
Z2_HOST_INTN
TP_ISSP_SCLK_P1_1
PSOC_SCLK
Z2_SCLK
PICKB_L
Z2_CS_L
WS_KBD2
WS_KBD19
WS_KBD20
WS_KBD21
WS_KBD22
PP3V3_S3_PSOC
PP3V3_S3_PSOC
TP_P7_7
TP_ISSP_SDATA_P1_0
WS_KBD5
WS_KBD4
PP3V3_S3
PP3V42_G3H
PP3V3_S3
SMC_ONOFF_L
WS_LEFT_SHIFT_KBD WS_LEFT_OPTION_KBD
PP3V42_G3H
WS_KBD22
WS_KBD16_NUM
WS_KBD13
WS_KBD9
PP3V3_S3
57 OF 132
<E4LABEL>
<SCH_NUM>
<BRANCH>
53 OF 101
36 93
36 93
53
53
6
54
6
54
54
6
54
6
54
6
54
6
53
6
54
6
53
6
6
53
6 7
17 21 23 43 45 46 47 48
49 53 64 65 66 73
6 7
17 21 23 43 45 46 47 48 49
53 64 65 66 73
53
6
53
6 7 8
17 20 31 32 33 34 35 36
48 50 53 54 55 72 73 87
101
6
53
53
46
53
6
53
53
53
6
53
6
54
53
6
53
53
6
53
53
53
6
53
6
53
6
53
6
53
6
53
6
53
6
53
6
53
6
53
6
53
6
53
6
53
6
53
6
53
6
53
6
53
6
53
6 7
17 21 23 43 45 46 47
48 49 53 64 65 66 73
6
6
53
6
53
6
53
6
53
6
53
6 7 8
17 20 31 32 33 34 35 36 48 50 53
54 55 72 73 87
101
53
6
53
6
53
6
53
6
53
6
53
6
6
53
6
54
6
53
53
6
53
54
6 8
6
54
6
54
6
54
6
54
6
53
6
53 6 53 6 53 6 53
53
53
6
53
6
53
6 7 8
17 20 31 32 33 34 35 36 48
50 53 54 55 72 73 87
101
6 7
17 21 23 43 45 46 47 48 49
53 64 65 66 73
6 7 8
17 20 31 32 33 34
35 36 48 50 53 54 55 72
73 87
101
6
45 46
6
53
6
53
6 7
17 21 23 43 45 46 47 48
49 53 64 65 66 73
6
53
6
6
53
6
53
Page 54
THRML
CAP
SW
LED
VIN
CTRL
PAD
GND
CTRL
PGND
THRML
L
VIN
DO
FB
SW
PAD
GND
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER
SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
tristate SMC_SYS_KBDLED:
KBD BACKLIGHT CONNECTOR
APN 518S0612
APN 152S0504
- RIPPLE TO MEET ERS
- 100-300 KHZ CLEAN SPECTRUM
BOOSTER DESIGN CONSIDERATION:
- DROOP LINE REGULATION
APN 371S0313
R5853 ALWAYS PRESENT
BOM OPTION: KBDLED_YES
on keyboard backlight flex
J5815 pin 1 is grounded
HIGH= keyboard backlight not present
LOW = keyboard backlight present
To detect Keyboard backlight, SMC will
Keyboard LED Driver
APN 516S0689
IPD FLEX CONNECTOR
- POWER CONSUMPTION
BOOSTER +18.5VDC FOR SENSORS
APN 353S1401
- R5812,R5813,C5818 MODIFIED
- STARTUP TIME LESS THAN 2MS
M-ST-SM
55560-0228
CRITICAL
J5800
1
10
1112 1314 1516 1718 19
2
20
2122
34 56 78 9
5%
402
MF-LF
4.7K
1/16W
R5854
1
2
1/16W
5%
402
MF-LF
470K
R5853
1
2
DFN
LT3491
CRITICAL
U5850
4
6
2
5
3
7
1
5%
1/16W
402
MF-LF
10K
NO STUFF
R5852
1
2
10V
10%
402-1
X5R
1UF
C5850
1
2
1/16W
1% MF-LF
10
402
R5855
1
2
1098AS-SM
10UH-0.58A-0.35OHM
CRITICAL
L5850
1 2
35V
10%
603
X5R
1UF
C5855
1
2
F-RT-SM
FF18-4A-R11AD-B-3H
CRITICAL
J5815
1 2 3 4
1/16W
5%
402
MF-LF
0
R5806
1 2
1/16W
1%
402
MF-LF
1M
R5812
1
2
50V
5% 402
CERM
39PF
C5818
1
2
SOD-323
B0520WSXG
D5802
1 2
25V
10%
603-1
X5R
1UF
C5819
1
2
1/16W
1%
402
MF-LF
71.5K
R5813
1
2
1/16W
1%
402
MF-LF
100K
R5811
1
2
3.3UH-870MA
CRITICAL
VLF3010AT-SM-HF
L5801
1 2
5%
402
MF-LF
1/16W
0
R5805
1 2
CRITICAL
TPS61045
QFN
U5805
53
4
6
1
7
8
9
2
2.2UF
603
16V
10% X5R
C5817
1
2
0.1UF
X7R-CERM
16V
10% 402
C5816
1
2
WELLSPRING 2
SYNC_MASTER=K19_MLB
SYNC_DATE=05/29/2009
MIN_NECK_WIDTH=0.25 MM
MIN_LINE_WIDTH=0.3 MM
KBDLED_SW
SWITCH_NODE=TRUE
SMC_KDBLED_PRESENT_L
MIN_LINE_WIDTH=0.50MM
MIN_NECK_WIDTH=0.20MM
PP18V5_S3
VOLTAGE=18.5V
Z2_CLKIN
PP3V3_S3
0.50MM
0.20MM
INPUT_SW
PP5V_S3_BOOSTER
MIN_LINE_WIDTH=0.50MM MIN_NECK_WIDTH=0.20MM
VOLTAGE=5V
Z2_BOOST_EN
MIN_NECK_WIDTH=0.20MM
MIN_LINE_WIDTH=0.50MM
BOOST_SW
SWITCH_NODE=TRUE
Z2_HOST_INTN
Z2_BOOST_EN
Z2_SCLK
Z2_MISO
Z2_MOSI
Z2_DEBUG3
Z2_CS_L
Z2_KEY_ACT_L
PP18V5_S3
SMBUS_SMC_A_S3_SCL
SMBUS_SMC_A_S3_SDA
PSOC_SCLK
PSOC_MOSI
PSOC_MISO
PICKB_L
PSOC_F_CS_L
Z2_RESET
PP18V5_S3_SW
MIN_NECK_WIDTH=0.20MM
MIN_LINE_WIDTH=0.50MM
VOLTAGE=18.5V
PP5V_S0
MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.25 MM
KBDLED_CAP
MIN_LINE_WIDTH=0.2 MM MIN_NECK_WIDTH=0.2 MM
KBDLED_ANODE
SMC_KDBLED_PRESENT_L
PP3V3_S0
PP5V_S3
SMC_SYS_KBDLED
BOOST_FB
58 OF 132
<E4LABEL>
<SCH_NUM>
<BRANCH>
54 OF 101
6
54
6
53
6 7 8
17 20 31 32 33 34 35 36 48 50 53
55 72 73 87
101
6
54
53
6
54
6
53
6
53
53
6
53
6
53
6
53
6
54
6
33 45 48
97
6
33 45 48
97
6
53
6
53
6
53
6
53
6
53
6
53
6 7
23 42 47 52 68 69 70 72
86 88
6
6
54
6 7
17 18 19 20 21 23 24 25
26 27 28 30 34 37 40 42 46 47
48 50 51 52 58 62 63 68 69
72 73 80 83 84 85 87 88 99
6 7
31 33 42 43 44 46 56 58 61 66 67 72
82
101
45
Page 55
FS PD ST
RES RES
GND
NC
NC NC
NC
NC NC
VOUTX
VOUTY
VOUTZ
VDD
OUT
OUT
OUT
FS PD ST
RES RES
GND
NC
NC NC
NC
NC NC
VOUTX
VOUTY
VOUTZ
VDD
IN
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
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PAGE TITLE
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A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
Alternate location Analog SMS
PLACE CAPS ON SMS OUTPUT SIGNALS CLOSE TO SMC
R5921 PULLS UP SMS_PWRDN TO TURN OFF SMS WHEN PIN IS NOT BEING DRIVEN BY SMC
in correct orientation
+Z (up)
+Y
+X
Front of system
Desired orientation when
+Z (up)
placed on board top-side:
in correct orientation
placed on board top-side:
Desired orientation when
+Y
+X
Front of system
Circle indicates pin 1 location when placed
Circle indicates pin 1 location when placed
NC NC
NC
NC
NC
NC
NC
Analog SMS
NC NC NC
NC
NC
NC
NC
LGA
AP344ALH
CRITICAL
U5930
1
7
3 6 9
11 13 16
5
15
4
2
14
12
10
8
1/16W
5%
402
MF-LF
10K
R5932
1
2
45
45
45
10UF
X5R 603
20% 4V
C5926
1
22
1
C5922
16V
10% 402
X5R
0.1UF
CRITICAL
AP344ALH
LGA
U5920
1
7
3 6 9
11 13 16
5
15
4
2
14
12
10
8
NO STUFF
1/16W
5%
402
MF-LF
10K
R5921
1
2
NO STUFF
1/16W
5%
402
MF-LF
10K
R5922
1
2
45 55
0
5% 1/16W MF-LF 402
R5940
1
2
402
0
5% 1/16W MF-LF
R5941
1
2
MF-LF
1/16W
5%
0
402
R5942
1
2
16V
10% X5R
0.1UF
402
1
2
C5923
16V
10% X5R
0.1UF
402
1
2
C5924
0.1UF
X5R
10% 16V
402
1
2
C5925
4V
20%
603
X5R
10UF
C5936
1
2
NO STUFF
16V
10%
402
X5R
0.1UF
C5932
1
2
NO STUFF
SYNC_MASTER=K19_MLB
Sudden Motion Sensor (SMS)
SYNC_DATE=05/29/2009
SMS_ALT_Y_AXIS
SMS_ALT_X_AXIS
SMS_ALT_Z_AXIS
SMS_ALT_SELFTEST
SMS_PWRDN
PP3V3_S3
SMS_PWRDN
MAKE_BASE=TRUE
SMS_SELFTEST
PP3V3_S3
SMS_X_AXIS SMS_Y_AXIS SMS_Z_AXIS
59 OF 132
<E4LABEL>
<SCH_NUM>
<BRANCH>
55 OF 101
6 7 8
17 20 31 32 33 34 35 36 48 50 53
54 55 72 73 87
101
45 55
6 7 8
17
20 31 32
33 34 35
36 48 50
53 54 55
72 73 87
101
Page 56
IN
BI
V+
REFIN+
IN-
OUT
GND
V+ V-
THRM
V+ V-
THRM
V+ V-
THRM
IN
IN
IN
IN
IN
ININ
COM
GND
THRM
DVDDAVDD
AD0 AD1
SDA SCL
CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7
VREF
REFCOMP
PAD
IN
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER
SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
GAIN: 200X
FB Voltage Sense / Filter
DIVIDER: ~ 1/20
GAIN: 845X
GAIN: 1239X
GAIN: 561X
LSB: 0.001V
I2C ADDRESS: 0X10 / 0X11
DIVIDER: ~ 2/3
ADC RANGE: 0V TO 4.096V
DIVIDER: ~ 2/5
243
402
1% 1/16W MF-LF
DEBUG_ADC
R6030
1 2
45 48 97
PLACEMENT_NOTE=Place near R5413
SM
XW6040
1 2
402
MF-LF
1/16W
10
5%
DEBUG_ADC
R6004
1 2
402
DEBUG_ADC
5%
10
1/16W MF-LF
1 2
R6003
INA210
DEBUG_ADC
SC70
U6050
2
5
4
6
1
3
DFN
DEBUG_ADC
OPA2333
U6030
3
2
1
9
4
8
DEBUG_ADC
OPA2333
DFN
U6040
3
2
1
9
4
8
OPA2333
DFN
U6040
5
6
7
9
4
8
DEBUG_ADC
20%
10UF
X5R
10V
C6001
603
1
2
10V
20% CERM
0.1UF
402
1
2
C6000
DEBUG_ADC
1%
MF-LF
402
DEBUG_ADC
1/16W
226K
PLACE_NEAR=U6000.4:5mm
R6074
1 2
CERM
DEBUG_ADC
0.1UF
20% 10V
402
C6050
1
2
NOSTUFF
470PF
402
CERM
10% 50V
C6032
1
2
301K
DEBUG_ADC
1%
402
MF-LF
1/16W
R6032
1
2
NOSTUFF
402
50V
10%
CERM
470PF
C6033
1 2
301K
MF-LF
1/16W
1%
402
DEBUG_ADC
R6033
1 2
226K
MF-LF
PLACE_NEAR=U6000.1:5mm
DEBUG_ADC
1/16W
402
1%
R6044
1 2
0.1UF
DEBUG_ADC
10V 402
CERM
20%
C6030
1
2
226K
1/16W
402
1%
MF-LF
PLACE_NEAR=U6000.24:5mm
1 2
R6034
DEBUG_ADC
MF-LF
1/16W
649K
DEBUG_ADC
402
1%
R6010
1
2
1M
1/16W MF-LF 402
1%
DEBUG_ADC
R6011
1
2
SM
PLACE_NEAR=R3404.1:3mm
XW6010
1 2
PLACE_NEAR=U6000.22:5mm
226K
DEBUG_ADC
MF-LF
1/16W
1%
402
R6012
1 2
6.3V
10%
402
2.2UF
DEBUG_ADC
PLACE_NEAR=U6000.22:5mm
X5R
C6012
1
2
DEBUG_ADC
1/16W
1%
402
MF-LF
681K
R6021
1
2
DEBUG_ADC
1% 1/16W
402
MF-LF
1M
R6020
1
2
SM
PLACE_NEAR=R4598.2:3mm
XW6020
1 2
402
10%
6.3V
DEBUG_ADC
X5R
2.2UF
PLACE_NEAR=U6000.4:5mm
C6074
1
2
MF-LF
1/16W
1%
52.3K
DEBUG_ADC
402
R6081
1
2
SM
PLACE_NEAR=D9701.2:3mm
XW6080
1 2
1%
1M
DEBUG_ADC
1/16W MF-LF 402
R6080
1
2
PLACE_NEAR=U6000.1:5mm
2.2UF
X5R
6.3V
10%
402
DEBUG_ADC
C6044
1
2
6.3V X5R
2.2UF
DEBUG_ADC
402
10%
PLACE_NEAR=U6000.24:5mm
C6034
1
2
412
1%
MF-LF
1/16W
402
DEBUG_ADC
R6061
1 2
412
MF-LF
1/16W
1%
402
DEBUG_ADC
R6060
1 2
DEBUG_ADC
1% 1/16W MF-LF
402
499
R6050
1 2
DEBUG_ADC
1% 1/16W MF-LF
402
499
R6051
1 2
10% 402
6.3V
DEBUG_ADC
X5R
2.2UF
PLACE_NEAR=U6000.5:5mm
C6082
1
2
1%
402
1/16W MF-LF
226K
DEBUG_ADC
PLACE_NEAR=U6000.5:5mm
R6082
1 2
NOSTUFF
402
CERM
470PF
50V
10%
C6062
1
2
348K
1/16W
1%
402
MF-LF
DEBUG_ADC
R6062
1
2
348K
1/16W
1%
402
MF-LF
DEBUG_ADC
R6063
1 2
NOSTUFF
470PF
CERM
10%
402
50V
C6063
1 2
NOSTUFF
402
50V
10%
CERM
470PF
C6052
1
2
1/16W
1%
402
MF-LF
DEBUG_ADC
280K
R6052
1
2
DEBUG_ADC
1%
402
MF-LF
1/16W
280K
R6053
1 2
NOSTUFF
50V
CERM
402
10%
470PF
C6053
1 2
MF-LF
1/16W
1%
402
226K
PLACE_NEAR=U6000.3:5mm
DEBUG_ADC
R6064
1 2
20% 10V
402
CERM
0.1UF
DEBUG_ADC
C6040
1
2
MF-LF
402
1%
1/16W
DEBUG_ADC
226K
PLACE_NEAR=U6000.2:5mm
R6054
1 2
DEBUG_ADC
MF-LF
1%
1/16W
226K
PLACE_NEAR=U6000.23:5mm
402
R6022
1 2
6.3V
DEBUG_ADC
402
10% X5R
2.2UF
C6022
1
2
PLACE_NEAR=U6000.23:5mm
DEBUG_ADC
LTC2309
QFN
U6000
14 15
12
13
22 23 24
1 2 3 4 5
6
21
9
1011181920
8
16
17
25
7
10V
20%
402
CERM
0.1UF
DEBUG_ADC
C6004
1
2
1/16W
5%
MF-LF
0
402
PLACE_NEAR=U4900.F1:3mm
DEBUG_ADC
R6001
1 2
1/16W
402
MF-LF
1%
243
DEBUG_ADC
R6031
1 2
2
1
C6002
DEBUG_ADC
0.1UF
CERM
402
20% 10V
6.3V
20%
603
X5R
10UF
DEBUG_ADC
C6005
1
2
1/16W
5%
MF-LF
DEBUG_ADC
402
0
PLACE_NEAR=U4900.E4:3mm
R6002
1 2
DEBUG_ADC
20%
10UF
X5R
10V 603
1
2
C6003
6.3V
10%
402
DEBUG_ADC
X5R
2.2UF
PLACE_NEAR=U6000.3:5mm
C6064
1
2
402
6.3V
DEBUG_ADC
10% X5R
2.2UF
PLACE_NEAR=U6000.2:5mm
C6054
1
2
402-LF
CERM
6.3V
20%
DEBUG_ADC
2.2UF
C6006
1
2
45 48 97
DEBUG SENSORS AND ADC
SYNC_MASTER=K18_SENSORS
SYNC_DATE=07/07/2009
ISNS_HDD_R_N
ISNS_HDD_IOUT
ISNS_HDD_R_P
ISNS_ODD_R_N
ISNS_ODD_IOUT
ISNS_AIRPORT_R_N
ISNS_AIRPORT_IOUT
ISNS_AIRPORT_R_P
PP3V3_WLAN_F
P3V3_WLAN_F_DIV
PP5V_S3 PP5V_S3
FBVSENSE_IN
P5V_SW_ODD_XW
SMBUS_SMC_MGMT_SCL
SMBUS_SMC_MGMT_SDA
ADC_VREF
ADC_CH4
ADC_CH5
ADC_SCL
ADC_REFCOMP
ADC_SDA
ADC_CH2
ADC_CH7
ADC_CH6
ADC_CH0
ADC_CH4 ADC_CH5
ADC_CH3
ADC_CH1
ADC_CH1
TP_ISNS_HDD_P
TP_ISNS_ODD_N
ADC_CH2
P5V_SW_ODD_DIV
PP5V_SW_ODD
TP_ISNS_AIRPORT_N
ADC_CH0
ADC_CH7ADC_CH6
PPVOUT_S0_LCDBKLT
PVOUT_S0_LCDBKLT_XW
PVOUT_S0_LCDBKLT_DIV
P3V3_WLAN_F_XW
ADC_CH3
TP_ISNS_HDD_N
TP_ISNS_AIRPORT_P
TP_ISNS_LCDBKLT_N
TP_ISNS_LCDBKLT_P
PP5V_S3
ISNS_LCDBKLT_IOUT
PP1V8R1V55_S0GPU_ISNS
ISNS_ODD_R_P
PP5V_S3_DEBUG_ADC_DVDD_R
MIN_NECK_WIDTH=0.25mm
MIN_LINE_WIDTH=0.3mm
VOLTAGE=5V
TP_ISNS_ODD_P
PP5V_S3
MIN_NECK_WIDTH=0.25mm
MIN_LINE_WIDTH=0.3mm
VOLTAGE=5V
PP5V_S3_DEBUG_ADC_AVDD_R
60 OF 132
<E4LABEL>
<SCH_NUM>
<BRANCH>
56 OF 101
99
99
99 99
99
33
6 7
31 33 42 43 44 46 54 56 58 61 66 67
72 82
101
6 7
31 33 42
43 44
46 54
56 58
61 66
67 72
82
101
56
56
56
56
56
56
56
56
56
56
56
56
6
42
56
56 56
6
83 88
56
6 7
31 33 42 43 44 46 54 56 58 61 66 67
72 82
101
6 7 8
50 75 76 77 78
99
6 7
31 33 42 43 44 46 54 56 58 61 66 67
72 82
101
Page 57
OUT
IN
IN IN
IN
GND
VCC
WP*/ACC
CE*
SI/SIO0
HOLD*
SCLK
SO/SIO1
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
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DRAWING NUMBER
SIZE
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A
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PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
ROM will ignore SPI cycles.
NOTE: If HOLD* is asserted
402
20%
CERM
0.1UF
10V
C6100
1
2
402
3.3K
5% MF-LF
1/16W
R6101
1
2
47
47
47 47
6
20 47
32MBIT
SOP
MX25L3205DM2I-12G
OMIT
CRITICAL
U6100
1
4
7
6
5
2
8
3
SPI ROM
SYNC_MASTER=K17_REF
SYNC_DATE=06/15/2009
SPI_MLB_MOSI
SPI_MLB_MISO
SPIROM_USE_MLB
SPI_MLB_CS_L
SPI_MLB_CLK
PP3V3_S5
SPI_WP_L
61 OF 132
<E4LABEL>
<SCH_NUM>
<BRANCH>
57 OF 101
6 7
17 18 19 20 21 23 27 31
35 66 71 72 73 83 85 99
Page 58
IN
IN
IN
IN
OUT
IN
OUT
OUT OUT
OUT OUT
OUT
OUT
IN
IN
IN IN IN IN
VL_HD
SENSE_A
GPIO1/DMIC_SDA2
GPIO0/DMIC_SDA1
VHP_FILT+
GPIO2
RESET*
LINEOUT_L1-
VBIAS_DAC
FLYP
VA_REF
VD
GPIO3
VHP_FILT-
LINEOUT_R1-
LINEOUT_R1+
LINEOUT_R2-
SPDIF_OUT
LINEIN_C-
FLYC FLYN
SPDIF_IN
LINEOUT_L1+
THRM_PAD
VA_HP
HPOUT_R
HPREF
VCOM
AGND
VA
LINEIN_R+
LINEIN_L+
MICIN_L+ MICIN_L-
MICBIAS
SYNC
DGND
DMIC_SCL
HPOUT_L
SDI SDO
VL_IF
BITCLK
MICIN_R-
MICIN_R+
VREF+_ADC
LINEOUT_L2+ LINEOUT_L2­LINEOUT_R2+
/SPDIF_OUT2
IN
IN
IN
OUT
IN
IN
IN
IN
OUT
IN
OUT
OUT OUT
BP
NC
SHDN*
IN OUT
GND
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER
SIZE
D
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SHEET
PAGE TITLE
C
A
D
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PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
AUDIO CODEC
NC
NC
APPLE P/N 353S2234
NC
NC
NC
NC
DIFF FSINPUT= 2.45VRMS
NC
DAC1 FSOUTPUT= 1.34VRMS DAC2/3 FSOUTPUTDIFF= 2.67VRMS
4.5V POWER SUPPLY FOR CODEC
APPLE P/N 353S2592
SE FSINPUT= 1.22VRMS
NOTES ON CODEC I/O
DAC2/3 FSOUTPUTSE= 1.34VRMS
603
X5R
20%
10UF
6.3V
CRITICAL
C6221
1
2
SM
XW6201
1 2
CRITICAL
6.3V
20% CERM
2.2UF
402-LF
C6222
1
2
CRITICAL
2.2UF
20%
CERM
402-LF
6.3V
C6223
1
2
CRITICAL
603
6.3V
10UF
X5R
20%
C6220
1
2
CASE-P3-HF
20V
10%
TANT
1UF
CRITICAL
C6224
1
2
4.7UF
CRITICAL
X5R
4V
20% 402
C6210
1
2
17 94
17 94
17 94
17 94
17 94
63
61
60
60
61
61
61
63
59
59
63
63
63
63
CRITICAL
10UF
6.3V X5R 603
20%
C6213
1
2
QFN
CRITICAL
CS4206ACNZC
U6201
26
6
7
4
43 42
45
2 12 14 15
38 40
39
22
21
23
34
35
30
31
37
36
33
32
16
17
18
20
19
11
8
5
13
47 48
10
49
25
46
24
29
28
9
41
44
3
1
27
59
FERR-220-OHM
0402
CRITICAL
L6200
1 2
1/16W
1%
402
MF-LF
2.21K
R6200
1 2
402
16V
0.1UF
X5R
10%
C6215
1
2
0.1UF
10% 16V X5R 402
C6211
1
2
X5R
16V
10% 402
0.1UF
C6214
1
2
MF-LF 402
2.67K
1/16W
1%
R6210
1
2
1/16W
5%
100K
MF-LF 402
R6213
1
2
402
1/16W
5%
MF-LF
39
R6211
1 2
0.1UF
10% 16V
402
X5R
C6218
1
2
CRITICAL
10UF
TANT-POLY
20% 16V
2012-LLP
C6217
1
2
CRITICAL
10UF
2012-LLP
16V
20%
TANT-POLY
C6219
1
2
6 7
31 33 42 43 44 46 54 56 58 61 66 67
72 82
101
6 7
17 18 19 20 21 23 24 25
26 27 28 30 34 37 40 42 46
47 48 50 51 52 54 58 62 63
68 69 72 73 80 83 84 85 87
88 99
62
58
6 7
12 16 21 23 24 71 72 87
58
62
58
62
402-1
CRITICAL
X5R
10V
10%
1UF
C6216
1
2
402
X7R-CERM
10%
0.1UF
16V
C6202
1 2
61
61
61
SM
XW6200
1 2
NOSTUFF
1/16W
5%
402
MF-LF
0
R6201
1 2
CRITICAL
FERR-220-OHM
0402
L6201
1 2
1/16W
5%
402
MF-LF
39
R6212
1 2
MAX8840-4.5V
CRITICAL
UDFN
U6200
4
2
1
5
6
3
10%
1UF
X5R
10V 402-1
C6200
1
2
10%
1UF
X5R 402-1
CRITICAL
10V
C6201
1
2
10%
402-1
CRITICAL
10V X5R
1UF
C6203
1
2
20% POLY-TANT
16V CASE-B2-SM
CRITICAL 10UF
C6225
1
2
SYNC_MASTER=K18_AUDIO
SYNC_DATE=09/21/2009
AUDIO: CODEC/REGULATOR
VBIAS_DAC
AUD_LI_P_R
AUD_MIC_INN_L
MIN_LINE_WIDTH=0.5MM VOLTAGE=0V
MIN_NECK_WIDTH=0.2MM
GND_AUDIO_CODEC
HDA_RST_L
HDA_SYNC
CS4206_VCOM
AUD_LI_REF
CS4206_FLYN
AUD_SENSE_A
TP_AUD_GPIO_2
TP_AUD_GPIO_0
CS4206_FN
CS4206_VREF_ADC
TP_AUD_DMIC_CLK
PP3V3_S0
TP_AUD_GPIO_1
CS4206_FP
TP_AUD_LO1_N_L
CS4206_FLYP
VOLTAGE=4.5V
PP4V5_AUDIO_ANALOG
MIN_NECK_WIDTH=0.10MM
MIN_LINE_WIDTH=0.15MM
VOLTAGE=1.8V
PP1V8_S0_AUDIO_DIG
MIN_LINE_WIDTH=0.10MM MIN_NECK_WIDTH=0.10MM
AUD_GPIO_3
AUD_LO1_N_R
AUD_LO1_P_R
AUD_LO2_N_R
AUD_SPDIF_OUT_CHIP
CS4206_FLYC
AUD_SPDIF_IN
TP_AUD_LO1_P_L
PP5V_S3
AUD_HP_PORT_R
MIN_NECK_WIDTH=0.20MMMIN_LINE_WIDTH=0.30MM
MIN_LINE_WIDTH=0.30MM
AUD_HP_PORT_REF
MIN_NECK_WIDTH=0.20MM
AUD_LI_P_L
AUD_MIC_INP_L
AUD_CODEC_MICBIAS
MIN_LINE_WIDTH=0.30MM
AUD_HP_PORT_L
MIN_NECK_WIDTH=0.20MM
AUD_SDI_R
HDA_SDOUT
HDA_BIT_CLK
AUD_MIC_INN_R
AUD_MIC_INP_R
AUD_LO2_P_L AUD_LO2_N_L AUD_LO2_P_R
GND_AUDIO_CODEC
VOLTAGE=4.5V
MIN_NECK_WIDTH=0.10MM
MIN_LINE_WIDTH=0.15MM
PP4V5_AUDIO_ANALOG
AUD_SPDIF_OUT
PP3V3_S0
GND_AUDIO_HP_AMP
VOLTAGE=0V
MIN_NECK_WIDTH=0.10MM
MIN_LINE_WIDTH=0.15MM
HDA_SDIN0
GND_AUDIO_HP_AMP
4V5_NR
PP5V_S3
4V5_REG_EN
VOLTAGE=5V
MIN_LINE_WIDTH=0.15MM MIN_NECK_WIDTH=0.10MM
4V5_REG_IN
VOLTAGE=0V
GND_AUDIO_CODEC
PP4V5_AUDIO_ANALOG
PP1V8_S0
GND_AUDIO_HP_AMP
62 OF 132
<E4LABEL>
<SCH_NUM>
<BRANCH>
58 OF 101
58 59 63
6 7
17 18 19 20 21 23 24 25 26
27 28 30 34 37 40 42 46 47 48
50 51 52 54 58 62 63 68 69 72
73 80 83 84 85 87 88 99
6 7
31 33 42 43 44 46 54 56 58 61 66 67
72 82
101
94
58 59 63
58 60 62
58 60 62
58 59 63
58 60 62
Page 59
IN
IN
IN
OUT
OUT
OUT
IN
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER
SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
CODEC RIN = 20K OHMS NET RIN = 18K OHMS
VIN = 2VRMS, CODEC VIN = 1.14 VRMS
LINE INPUT VOLTAGE DIVIDER
FC = 8 HZ
62
62
62
58
58
58
3.3UF
CERM-X5R
CRITICAL
805-1
10% 10V
C6301
1 2
CRITICAL
3.3UF
10%
CERM-X5R
805-1
10V
C6302
1 2
3.3UF
CRITICAL
CERM-X5R
805-1
10% 10V
C6311
1 2
CRITICAL
3.3UF
CERM-X5R
805-1
10% 10V
C6312
1 2
58 63
1%
MF-LF
402
7.87K
1/16W
R6301
1 2
1%
1/16W
402
MF-LF
7.87K
R6311
1 2
1% 1/16W MF-LF 402
21.5K
R6312
1
2
402
1% 1/16W MF-LF
21.5K
R6302
1
2
1/16W MF-LF
1%
10
402
R6300
1
2
AUDIO: LINE INPUT FILTER
SYNC_DATE=07/29/2009
SYNC_MASTER=K18_AUDIO
MIN_NECK_WIDTH=.1MM
MIN_LINE_WIDTH=.1MM
AUD_LI_L
GND_AUDIO_CODEC
MIN_NECK_WIDTH=.1MM
MIN_LINE_WIDTH=.1MM
AUD_LI_R
MIN_LINE_WIDTH=.1MM MIN_NECK_WIDTH=.1MM
AUD_LI_GND
AUD_LI_R_DIV
MIN_LINE_WIDTH=.1MM MIN_NECK_WIDTH=.1MM
MIN_NECK_WIDTH=.1MM
MIN_LINE_WIDTH=.1MM
AUD_LI_P_L
AUD_LI_REF
MIN_LINE_WIDTH=.1MM MIN_NECK_WIDTH=.1MM
AUD_LI_P_R
MIN_LINE_WIDTH=.1MM MIN_NECK_WIDTH=.1MM
AUD_LI_L_DIV
MIN_NECK_WIDTH=.1MM
MIN_LINE_WIDTH=.1MM
63 OF 132
<E4LABEL>
<SCH_NUM>
<BRANCH>
59 OF 101
Page 60
OUT
OUT
IN
IN
IN
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER
SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
ZOBEL NETWORK & 1ST ORDER DAC FILTER PLACEHOLDER
NC
NC
62
1/16W 402
MF-LF
3.32K
1%
R6502
1
2
1%
3.32K
MF-LF
1/16W 402
R6512
1
2
16V
10%
X7R-CERM
0.1UF
CRITICAL
402
C6500
1
2
1/16W
5%
MF-LF
39
402
R6500
1
2
0.1UF
X7R-CERM
402
10% 16V
CRITICAL
C6510
1
2
1/16W
5%
402
MF-LF
39
R6510
1
2
62
0
MF-LF
603
5%
1/10W
R6501
1 2
0
MF-LF
603
5%
1/10W
R6511
1 2
58
58 62
58
SYNC_DATE=07/29/2009
SYNC_MASTER=K18_AUDIO
AUDIO: HEADPHONE FILTER
AUD_HP_ZOBEL_R
GND_AUDIO_HP_AMP
AUD_HP_ZOBEL_L
AUD_HP_PORT_L
AUD_HP_L
AUD_HP_PORT_R
AUD_HP_R
65 OF 132
<E4LABEL>
<SCH_NUM>
<BRANCH>
60 OF 101
Page 61
IN
IN
OUT
OUT
OUT
IN
OUT
IN
OUT
OUT
IN
IN
IN
SD*
OUT+
PVDD
GND
VDD
IN+
IN-
OUT_
SD*
OUT+
PVDD
GND
VDD
IN+
IN-
OUT_
SD*
OUT+
PVDD
GND
VDD
IN+
IN-
OUT_
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER
SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
PLACE C6630 CLOSE TO VDD PIN
PLACE C6610 CLOSE TO VDD PIN
APN: 353S2500
3X MONO SPEAKER AMPLIFIERS (SSM2315)
PLACE C6620 CLOSE TO VDD PIN
1ST ORDER FC (SUB) = 58HZ +/- 30%
GAIN = 6DB
1ST ORDER FC (L&R) = 120 HZ +/- 30%
5%
MF-LF
402
1/16W
100K
R6601
1
2
0.033UF
16V
10%
402
X5R
CRITICAL
C6610
1 2
CRITICAL
FERR-1000-OHM
0402
L6601
1 2
58
58
FERR-1000-OHM
CRITICAL
0402
L6610
1 2
6
62 99
6
62 99
6
62 99
X5R
16V
0.033UF
402
10%
CRITICAL
C6611
1 2
10% 16V
402
0.1UF
X5R
CRITICAL
C6613
1
2
47UF
CRITICAL
TANT-POLY
CASE-A4
6.3V
20%
C6622
1
2
0.1UF
X5R 402
16V
10%
CRITICAL
C6623
1
2
402
0.033UF
X5R
10% 16V
CRITICAL
C6620
1 2
0402
FERR-1000-OHM
CRITICAL
L6620
1 2
58
6
62 99
6.3V
CRITICAL
CASE-A4
20%
TANT-POLY
47UF
C6612
1
2
CRITICAL
100UF
6.3V
20%
CASE-AL1
TANT
C6632
1
2
CRITICAL
0.068UF
CERM
402
10% 10V
C6630
1 2
CRITICAL
0402
FERR-1000-OHM
L6630
1 2
58
6
62 99
6
62 99
FERR-1000-OHM
CRITICAL
0402
L6611
1 2
58
CRITICAL
0.033UF
X5R
10% 16V
402
C6621
1 2
CRITICAL
FERR-1000-OHM
0402
L6621
1 2
58
CRITICAL
0.068UF
CERM
402
10% 10V
C6631
1 2
CRITICAL
0402
FERR-1000-OHM
L6631
1 2
58
16V
10% 402
X5R
0.1UF
CRITICAL
C6633
1
2
WLCSP
CRITICAL
SSM2315
U6610
A2
B3
C1 A1
A3
C3
B2
C2
B1
CRITICAL
WLCSP
SSM2315
U6620
A2
B3
C1 A1
A3
C3
B2
C2
B1
CRITICAL
WLCSP
SSM2315
U6630
A2
B3
C1 A1
A3
C3
B2
C2
B1
SYNC_MASTER=K18_AUDIO
SYNC_DATE=07/29/2009
AUDIO: SPEAKER AMP
AUD_SPKRAMP_SHUTDOWN_L
SPKRCONN_R_OUT_N
MIN_LINE_WIDTH=0.30 mm MIN_NECK_WIDTH=0.20 MM
PP5V_S3
NO_TEST=TRUE
AUD_SPKRAMP_SUBIN_P
AUD_SPKRAMP_SHUTDOWN_L
NO_TEST=TRUE
AUD_SPKRAMP_LIN_N
NO_TEST=TRUE
AUD_SPKRAMP_LIN_P
SSM2315S_N SSM2315S_P
PP5V_S3
AUD_LO2_N_R
AUD_SPKRAMP_RIN_P
NO_TEST=TRUE
SSM2315R_P
AUD_LO1_P_R
AUD_LO1_N_R
AUD_SPKRAMP_SUBIN_N
NO_TEST=TRUE
PP5V_S3
SPKRCONN_R_OUT_P
MIN_NECK_WIDTH=0.20 MM
MIN_LINE_WIDTH=0.30 mm
AUD_SPKRAMP_SHUTDOWN_L
SSM2315R_N
SSM2315L_P
AUD_LO2_P_R
AUD_SPKRAMP_RIN_N
NO_TEST=TRUE
SSM2315L_N
AUD_LO2_P_L
AUD_LO2_N_L
AUD_GPIO_3
MIN_NECK_WIDTH=0.20 MM
MIN_LINE_WIDTH=0.30 mm
SPKRCONN_L_OUT_P
MIN_NECK_WIDTH=0.20 MM
MIN_LINE_WIDTH=0.30 mm
SPKRCONN_L_OUT_N
MIN_LINE_WIDTH=0.30 mm MIN_NECK_WIDTH=0.20 MM
SPKRCONN_S_OUT_N
MIN_LINE_WIDTH=0.30 mm MIN_NECK_WIDTH=0.20 MM
SPKRCONN_S_OUT_P
66 OF 132
<E4LABEL>
<SCH_NUM>
<BRANCH>
61 OF 101
61
6 7
31 33 42 43 44 46 54 56 58 61 66 67
72 82
101
61
6 7
31 33 42 43 44 46 54 56 58 61 66 67
72 82
101
6 7
31 33 42 43 44 46 54 56 58 61 66 67
72 82
101
61
Page 62
IN IN
IN IN
OUT
OUT OUT OUT
IN
IN
PINS
SHELL
SHIELD
POF
A - VDD B - GND
C - VOUT
OPERATING VOLTAGE 3.3
AUDIO
SWITCH
LEFT
RIGHT
GROUND
DETECT FOR PLUG TYPE
OUT
OUT
RIGHT
MIC
AUDIO
GND
LEFT
SWITCH
DETECT
B - VCC
POF
SHIELD
SHELL
PINS
C - GND
A - VIN
OPERATING VOLTAGE 3.3
BI
OUT
BI
BI
OUT
IN
BI
BI
OUT
OUT
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
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REVISION
DRAWING NUMBER
SIZE
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R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
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PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
GND PATCH
AUDIO JACK 1 LO/HP JACK, SPDIF TX
APN: 518S0520
APN: 514-0635
APN: 518S0521
APN: 518S0519
MIC CONNECTOR
SPEAKER CONNECTOR
APN: 514-0671
AUDIO JACK 2 LINE IN JACK, SPDIF RX
6
61 99
6
61 99
6
61 99
6
61 99
402
4.7
MF-LF
5%
1/16W
R6749
1 2
10% X5R
1UF
10V 402-1
C6750
1
2
CRITICAL
6.8V-100PF
402
DZ6701
1
2
SOD882
ESDALC5-1BM2
CRITICAL
DZ6758
1
2
CRITICAL
600-OHM-300MA
0402
L6758
1 2
6.8V-100PF
402
CRITICAL
DZ6700
1
2
402
6.8V-100PF
CRITICAL
DZ6706
1
2
6.8V-100PF
402
CRITICAL
DZ6704
1
2
402
6.8V-100PF
CRITICAL
DZ6754
1
2
58 60
FERR-1000-OHM
CRITICAL
0402
L6702
1 2
CRITICAL
0402
FERR-1000-OHM
L6703
1 2
6.8V-100PF
402
CRITICAL
DZ6703
1
2
6
63
6
63
6
63
FERR-1000-OHM
0402
CRITICAL
L6705
1 2
0402
FERR-1000-OHM
CRITICAL
L6752
1 2
10% 402
X5R
0.1UF
16V
C6700
1
2
M-RT-SM
78171-0004
CRITICAL
J6782
5
6
1 2 3 4
M-RT-SM
78171-0003
CRITICAL
J6780
4
5
1 2 3
M-RT-SM
78171-0002
CRITICAL
J6781
3
4
1 2
6
61 99
6
61 99
20%
6.3V
2.2UF
402-LF
CERM
C6701
1
2
0
MF-LF
402
1/16W
5%
R6701
1 2
FERR-1000-OHM
CRITICAL
0402
L6754
1 2
F-RT-TH5
AUDIO-RCVR-M97
J6750
5
7
4
10 11 12
9
1 3
2
6
8
50V
5%
402
CERM
33PF
CRITICAL
NOSTUFF
C6782
1
2
50V
5%
402
CERM
33PF
CRITICAL
NOSTUFF
C6781
1
2
50V
5% 402
CERM
33PF
CRITICAL
NOSTUFF
C6784
1
2
50V
5%
402
CERM
33PF
CRITICAL
NOSTUFF
C6783
1
2
63
FERR-1000-OHM
0402
CRITICAL
L6756
1 2
63
F-RT-TH
SPDIF-TXRX-K24
J6700
5
4
10 11 12 13
7 8 9
1
6
3
2
58
CRITICAL
6.8V-100PF
402
DZ6756
1
2
SM
XW6702
1 2
SM
XW6701
1 2
FERR-220-OHM
CRITICAL
0402
L6707
1 2
SOD882
ESDALC5-1BM2
CRITICAL
DZ6757
1
2
50V
5%
402
CERM
100PF
C6756
1
2
58
59
59
63
58
60
60
CRITICAL
FERR-220-OHM-2.5A
0603
L6701
1 2
CRITICAL
FERR-220-OHM
0402
L6704
1 2
0402
FERR-220-OHM
CRITICAL
L6706
1 2
63
63
10K
5%
1/16W
402
MF-LF
R6700
1 2
402
CERM
50V
5%
100PF
C6705
1
2
AUDIO: JACKS
SYNC_MASTER=K18_AUDIO
SYNC_DATE=07/29/2009
AUD_J2_TIPDET_R
GND_CHASSIS_AUDIO_JACK
AUD_SPDIF_IN
AUD_CONNJ2_RING
BI_MIC_N
BI_MIC_P
AUD_CONNJ2_TIPDET
AUD_J2_OPT_OUT
PP3V3_S0
AUD_LI_GND
AUD_LI_R
AUD_HP_L
AUD_HP_R
SPKRCONN_L_OUT_P SPKRCONN_L_OUT_N
AUD_LI_L
SPKRCONN_S_OUT_N
SPKRCONN_R_OUT_N
SPKRCONN_R_OUT_P
SPKRCONN_S_OUT_P
AUD_J1_TIPDET_R
BI_MIC_SHIELD
AUD_J1_SLEEVEDET_R
MIN_LINE_WIDTH=0.30 mm MIN_NECK_WIDTH=0.10 MM VOLTAGE=0V
GND_CHASSIS_AUDIO_JACK
AUD_CONNJ1_SLEEVE
AUD_CONNJ1_RING
PP3V3_S0
AUD_CONNJ1_TIP
AUD_CONNJ1_SLEEVEDET
AUD_CONNJ1_SLEEVE2
AUD_CONNJ1_TIPDET
GND_AUDIO_HP_AMP
AUD_HP_PORT_REF
HS_MIC_N
HS_MIC_P
AUD_SPDIF_OUT
GND_CHASSIS_AUDIO_JACK
AUD_CONNJ2_SLEEVE
AUD_CONNJ2_TIP
67 OF 132
<E4LABEL>
<SCH_NUM>
<BRANCH>
62 OF 101
8
62
6 7
17 18 19 20
21 23 24 25 26 27 28 30
34 37 40 42 46
47 48 50 51 52 54 58 62
63 68 69 72 73
80 83 84 85 87 88 99
59
8
62
6 7
17 18 19
20 21 23 24 25
26 27 28 30
34 37 40 42 46
47 48 50 51
52 54 58 62 63
68 69 72 73
80 83 84 85
87 88 99
8
62
Page 63
IN
OUT
IN
IN
D
SG
D
SG
D
SG
D
SG
D
G S
OUT
IN
OUT
OUT
IN
IN
IN
IN
IN
OUT
OUT
IN
BI
IN
OUT
OUT
D
SG
D
SG
IN
GND THM
ENABLE
AVDD
SDA
MICBIAS
DETECT
BYPASS
INT*
SCL
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER
SIZE
D
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IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
CODEC INPUT SIGNAL PATHS
0X0C (12,C)
0X08 (8)
0X0C (12,C)
SUB SPDIF OUT
0X05 (5)
PORT B DETECT(SPDIF DELEGATE)
PORT B RIGHT(BUILT-IN MIC)
SYSTEM INT AND GPIO LINES
INT
MIC_BIAS (80%)
GPIO
FUNCTION
PIN COMPLEX
DET ASSIGNMENT
N/A
VREF
N/A N/A
N/A
0X06 (6)
0X07 (7)
CONVERTER
SPDIF IN
LINE IN
FUNCTION
0X0A (10) 0X10 (16)
0X06 (6)
APN:376S0613
PORT A DETECT (HEADPHONES)
NC NC
EXTRACTION NOTIFICATION
NC
PULLUPS ON MCP PAGE
0X0C (B)
N/A
N/A
0X09 (A)
N/A
PORT B LEFT(HEADSET MIC)
DRC MIKEY
HP=80HZ, LP=8.82KHZ
APN:376S0612
0X02 (2)
HP/LINE OUT
MIKEY MIKEY
DET ASSIGNMENT
CONVERTER
APN:353S2256
HP=80HZ
GPIO_3
N/A
PORT C DETECT (LINE-IN)
0X04 (4)
GPIO_3
0X03 (03)
0X0B (11)
MUTE CONTROL
0X0F (15) 0X0D (13,B,RIGHT) 0X0D (13,V22,B,LEFT)
GPIO 3
GPIO 5PIRQ H
PIRQ F
HEADSET MIC
MIKEY ENABLE
SATA4GP/GPIO 16
PERIPHERAL DETECT
MIKEY INTERRUPT
SATELLITES
0X02 (2) 0X04 (4)
BUILT-IN MIC
N/A
CODEC OUTPUT SIGNAL PATHS
FUNCTION
VOLUME
0X03 (3)
0X09 (9,A)
PIN COMPLEX
0.1UF
CERM
402
20%
10V
C6801
1
2
47K
MF-LF
402
5%
1/16W
R6802
1 2
220K
402
5% 1/16W MF-LF
R6801
1
2
62 63
MF-LF 402
1% 1/16W
39.2K
R6806
1
2
220K
MF-LF
402
5%
1/16W
R6803
1 2
MF-LF 402
5% 1/16W
220K
R6804
1
2
0.01UF
CERM 402
10% 16V
C6802
1
2
58 63
62 63
10K
402
1% 1/16W MF-LF
R6813
1
2
0.1UF
CERM
402
20%
10V
C6811
1
2
270K
MF-LF 402
5% 1/16W
R6811
1
2
47K
MF-LF
402
5%
1/16W
R6812
1 2
62
20.0K
402
1% 1/16W MF-LF
R6805
1
2
SSM6N15FEAPE
SOT563
Q6800
3
5
4
SOT563
SSM6N15FEAPE
Q6800
6
2
1
SOT563
SSM6N15FEAPE
Q6801
3
5
4
SSM6N15FEAPE
SOT563
Q6801
6
2
1
SSM3K15FV
SOD-VESM-HF
Q6802
3
1
2
58 63
1%
2.4K
MF
1/16W 402-1
R6851
1 2
27PF
402
5%
50V
CRITICAL
CERM
C6854
1
2
X5R 402
10% 25V
0.1UF
CRITICAL
C6850
1 2
CERM
402
10%
50V
0.001UF
CRITICAL
C6853
1
2
MF-LF 402
5%
100K
1/16W
R6852
1
2
SM
XW6851
1 2
58
58
58
6
62
6
62
6
62
2.2UF
TANT 402
20%
6.3V
CRITICAL
C6852
1
2
0402
FERR-1000-OHM
L6851
1 2
0402
FERR-1000-OHM
L6850
1 2
62
62
2.2K
1/16W
5%
402
MIKEY
MF-LF
R6882
1
2
CRITICAL
27PF
CERM
MIKEY
402
5%
50V
C6885
1
2
25V
10%
402X7R
0.0082UF
CRITICAL
MIKEY
C6884
1
2
1/16W
5%
402
MF-LF
100K
MIKEY
R6883
1
2
0.1UF
MIKEY
CRITICAL
25V
10% X5R
402
C6883
1 2
SM
XW6880
1 2
58
MIKEY
1/16W
1%
402
MF-LF
1K
R6881
1
2
16V
10%
402
CERM
0.01UF
MIKEY
C6881
1
2
MIKEY
FERR-1000-OHM
CRITICAL
0402
L6880
1 2
MIKEY
10UF
X5R603
20%
6.3V
CRITICAL
C6880
1
2
MIKEY
2.2UF
TANT 402
20%
6.3V
CRITICAL
C6882
1
2
19
17 25 26 28 30 32 42 47 48 88 94
17 25 26 28 30 32 42 47 48 88 94
20 25
2.2K
MF-LF
402
5%
1/16W
MIKEY
R6884
1 2
MIKEY
CRITICAL
0.1UF
X5R 402
10% 25V
C6886
1 2
58
0.1UF
X5R 402
10% 25V
CRITICAL
C6851
1 2
MF-LF
1%
1/16W
100
402
R6850
1 2
2.4K
MF
1/16W
1%
402-1
R6853
1 2
19
SSM6N15FEAPE
SOT563
Q6803
6
2
1
100
MF-LF
402
1/16W
5%
R6861
1 2
0.1UF
20%
10V 402
CERM
C6861
1
2
0402
FERR-1000-OHM
CRITICAL
L6862
1 2
402
MF-LF
220K
5%
1/16W
R6864
1 2
100K
MF-LF
402
5%
1/16W
R6865
1 2
SSM6N15FEAPE
SOT563
Q6803
3
5
4
402
0.1UF
CERM
20%
10V
C6860
1
2
5%
15K
MF-LF
402
1/16W
R6860
1 2
6 7
17 18 19 20 21
23 24 25 26 27 28
30 34 37 40 42 46
47 48 50 51 52 54
58 62 63 68 69 72
73 80 83 84 85 87
88 99
CD3275
DRC
MIKEY
U6880
3
10
2
8
9
4
7
1
6
5
11
SYNC_DATE=07/29/2009
SYNC_MASTER=K18_AUDIO
AUDIO: JACK TRANSLATORS
PP3V3_S0_AUDIO_F MIN_LINE_WIDTH=0.1MM MIN_NECK_WIDTH=0.1MM
VOLTAGE=3.3V
GND_AUDIO_CODEC
AUD_SENSE_A
PP3V3_S0_AUDIO_F
GND_AUDIO_CODEC
BI_MIC_LO_F
AUD_J1_TIPDET_R
AUD_I2C_INT_L
GND_AUDIO_CODEC
PP3V3_S0
AUD_MIC_INP_R
SMBUS_PCH_CLK
BI_MIC_P
AUD_MIC_INN_R
AUD_MIC_INN_L
AUD_J2_DET_RC
GND_AUDIO_CODEC
AUD_J2_TIPDET_R
BI_MIC_N
GND_AUDIO_CODEC
BI_MIC_SHIELD
AUD_CODEC_MICBIAS
MIC_BIAS_FILT
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.1MM MIN_NECK_WIDTH=0.1MM
PP3V3_S0_HS_RX
SMBUS_PCH_DATA
AUD_MIC_INP_L
HS_MIC_BIAS HS_SW_DET
HS_RX_BP
HS_MIC_HI_RC
HS_MIC_N
GND_AUDIO_CODEC
HS_MIC_P
AUD_INJACK_INSERT_L
AUD_IP_PERIPHERAL_DET
PP3V3_S0
AUD_PERPH_DET_R
GND_AUDIO_CODEC
AUD_J1_TIPDET_INV
TIPDET_FILT
AUD_J1_SLEEVEDET_R
PP3V3_S0_AUDIO_F
AUD_PORTB_DET_L
AUD_SENSE_A
AUD_PORTA_DET_L
AUD_OUTJACK_INSERT_L
AUD_J1_SLEEVEDET_INV
AUD_J1_DET_RC
GND_AUDIO_CODEC
PP3V3_S0_AUDIO_F
AUD_J1_SLEEVEDET_R
GND_AUDIO_CODEC
AUD_J1_TIPDET_R
BI_MIC_HI_F
AUD_IPHS_SWITCH_EN
GND_AUDIO_CODEC
68 OF 132
<E4LABEL>
<SCH_NUM>
<BRANCH>
63 OF 101
63
58 59 63
63
58 59 63
62 63
58 59 63
6 7
17 18 19 20 21 23 24 25
26 27 28 30 34 37 40 42 46 47
48 50 51 52 54 58 62 63 68 69
72 73 80 83 84 85 87 88 99
58 59 63
58 59 63
58 59 63
58 59 63
62 63
63
58 59 63
63
58 59 63
58 59 63
Page 64
BI
VCC
EXTINT
NC
GND
Y
B
A
IN
P3 P4 P5 P6 P7 P8
P1 P2
P9
SHLD_PIN SHLD_PIN SHLD_PIN SHLD_PIN
OUT
OUT
NC
NC
BI
BI
SW
FB
BDPG
EN/UVL0
THRM
GND
RT
VIN
PAD
BOOST
NC
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER
SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
PWR GND
1-Wire OverVoltage Protection
BIL CONNECTOR
TO SMC
518-0358
NC
516S0523
GND
PWR
SIG
connected.
BATTERY CONNECTOR
(Switcher limit)
<Rb>
<Ra>
250mA max output
Vout = 3.425
353s2730
3.425V "G3Hot" Supply
Supply needs to guarantee 3.31V delivered to SMC VRef generator
MagSafe DC Power Jack
Vout = 1.25V * (1 + Ra / Rb)
send transients onto ADAPTER_SENSE when AC is
The chassis ground will otherwise float and can
6AMP-24V
CRITICAL
1206-2
F6905
1 2
0.01UF
603
CERM
20% 50V
C6905
1
2
45 46
CRITICAL
33UH
CDPH4D19FHF-SM
L6995
1 2
CERM
50V
5%
47PF
402
C6995
1
2
1%
549K
402
MF-LF
1/16W
R6996
1
2
1%
1.00M
805
MF-LF
1/8W
R6995
1
2
22UF
X5R-CERM
20%
6.3V 603
C6999
1
2
402
X5R
16V
10%
0.1UF
C6994
1
2
CRITICAL
78048-0573
M-RT-SM
J6900
1 2 3 4 5
SC70-5
MAX9940
CRITICAL
U6900
5
2
4
3
1
0.1UF
20% CERM
PLACEMENT_NOTE=PLACE NEAR U6900 and U6901
10V 402
C6908
1
2
TC7SZ08AFEAPE
SOT665
U6901
2
1
3
5
4
45 46 65
CRITICAL
RCLAMP2402B
SC-75
D6950
3
1
2
402
1/16W MF-LF
5%
10K
R6950
1
2
402
10%
0.1UF
X5R
25V
C6950
1
2
M-RT-TH
CRITICAL
BAT-K19
J6950
10 11 12 13
1 2 3 4 5 6 7 8 9
10%
402
50V
0.001UF
CERM
C6954
1
2
50V
CERM
47PF
402
5%
C6953
1
2
CERM
47PF
50V
5%
402
C6952
1
2
F-ST-SM
CPB6312-0101F
CRITICAL
J6955
1
10
1112
1314
1516
2
34 56 78 9
10%
0.1UF
402
25V X5R
C6951
1
2
50V
10%
402
CERM
0.001UF
C6955
1
2
5%
402
1/16W
100
MF-LF
R6961
12
45 46 53
6
45 46
6
45 48 64 65 97
6
45 48 64 65
97
2.0K
5% 1/16W MF-LF 402
R6929
1
2
402
MF-LF
1/16W
1
5%
R6990
1 2
CRITICAL
DFN
LT3970
U6990
8
7
2
1
4
5
9
10
6
11
3
150K
1% 1/16W
402
MF-LF
R6991
1
2
402
MF-LF
5%
0
1/16W
R6992
1 2
0
5%
1/16W MF-LF
402
R6993
1 2
X5R
25V
10%
1UF
603-1
C6990
1
2
DC-In & Battery Connectors
SYNC_MASTER=K18_POWER
SYNC_DATE=06/30/2009
MIN_NECK_WIDTH=0.3 mm VOLTAGE=18.5V
MIN_LINE_WIDTH=0.3 mm
PPDCIN_G3H_OR_PBUS_R
P3V42_EN_R
P3V42_RT
VOLTAGE=18.5V
MIN_NECK_WIDTH=0.4 mm
MIN_LINE_WIDTH=0.6 mm
PPDCIN_G3H_OR_PBUS
P3V42_BD_R
P3V42G3H_FB
PP3V42_G3H
P3V42G3H_BOOST
SWITCH_NODE=TRUE
DIDT=TRUE
MIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.5 mm
P3V42G3H_SW
SMBUS_SMC_BSA_SDA
SYS_ONEWIRE
SMC_BC_ACOK_VCC
PPDCIN_G3H
PP18V5_DCIN_FUSE
MIN_LINE_WIDTH=1mm MIN_NECK_WIDTH=0.20mm VOLTAGE=18.5V
GND
PPVBAT_G3H_CONN
PP3V42_G3H
SMBUS_SMC_BSA_SCL SYS_DETECT_L
SMC_LID
SMC_LID_R
SMC_BC_ACOK
PP3V42_G3H
SMBUS_SMC_BSA_SDA SMBUS_SMC_BSA_SCL
SMC_BIL_BUTTON_L
ADAPTER_SENSE
69 OF 132
<E4LABEL>
<SCH_NUM>
<BRANCH>
64 OF 101
65
6 7
17 21 23 43 45 46 47 48 49
53 64 65 66 73
6 45 48 64 65 97
6 7
65
6
6
65
6 7
17 21 23 43 45 46 47 48 49
53 64 65 66 73
6
45 48 64 65 97
6
6 7
17 21 23 43 45 46 47 48
49 53 64 65 66 73
6
Page 65
OUT
OUT
IN BI
OUT
AMON BMON ACOK
LGATE
PHASE
BOOT
SGATE AGATE
CSIP CSIN
DCIN
VNEG CSOP CSON
THRM_PAD
PGND
VDDP
VDD
BGATE
UGATE ICOMP VCOMP
ACIN
SDA VFRQ CELL
VHST
SCL
SMB_RST_N
IN
D
G
S
D1
D3
D4
S3 S2
GATE
S1
D2
D1
D3
D4
S3 S2
GATE
S1
D2
S
D
G
IN
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER
SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
CRITICAL BOM OPTION
TABLE_5_HEAD
PART#
DESCRIPTION
QTY
REFERENCE DESIGNATOR(S)
TABLE_5_ITEM
ACIN pin threshold is 3.2V, +/- 50mV Divider sets ACIN threshold at 13.55V Input impedance of ~40K meets
(CHGR_CSO_N)
Inrush Limiter
through body diodes: * DCIN through Q7080.
FROM ADAPTER
30mA max load
Reverse-Current Protection
(CHGR_BGATE)
sparkitecture requirements
Float CELL for 1S
(AGND)
(GND)
(CHGR_CSO_P)
(CHGR_DCIN)
353S2392
f = 400 kHz
36V/V
(PPVBAT_G3H_CHGR_R)
(OD)
TO/FROM BATTERY
TO SYSTEM
This node is powered
Q7055.
20V/V
Charger TOP FETs and
* PBUS through Q7085,
(CHGR_SGATE)
Max Current = 8A (L7030 limit)
(CHGR_AGATE)
(PPVBAT_G3H_CHGR_R)
1%
402
MF-LF
1/16W
9.31K
R7011
1
2
402
10% X5R
16V
0.033UF
C7042
1
2
470PF
50V CERM
10% 402
C7016
1
2
3.01K
MF-LF
402
1/16W
1%
R7016
1
2
402
10% 50V
470PF
CERM
C7015
1
2
402
1/16W MF-LF
5%
220K
R7015
1
2
402
10% 10V X5R
1UF
C7002
1
2
10V
10%
1UF
402-1
X5R
C7000
1
2
MF-LF
1/16W
5%
402
4.7
R7001
1 2
30.1K
1%
402
MF-LF
1/16W
R7010
1
2
10%
402
CERM
0.01uF
16V
C7057
1
2
16V
0.1UF
X5R 402
10%
C7056
1
2
SM
PLACE_NEAR=U7000.22:1mm
PLACE_NEAR=U7000.29:1mm
XW7000
1 2
10% 10V
1UF
402
X5R
C7001
1
2
0.1UF
25V X5R 402
10%
C7021
1
2
0.1UF
10%
402
X5R
25V
C7022
1
2
10% 10V
402
CERM
0.047UF
C7020
1
2
10%
0.22UF
CERM
10V
PLACE_NEAR=U7000.25:2mm
402
C7025
1
2
CRITICAL
LFPAK-HF
RJK0305DPB
Q7035
5
4
1 2 3
1/16W
402
10
MF-LF
5%
R7022
1 2
10
MF-LF
5%
1/16W
402
R7021
1 2
CASE-D2-SM
POLY-TANT
25V
20%
22UF
CRITICAL
C7030
1
2
20% POLY-TANT
25V
22UF
CRITICAL
CASE-D2-SM
C7031
1
2
1206
CRITICAL
8AMP-24V
F7040
1 2
MF-LF
5%
1/16W
2.2
402
R7051
1 2
MF-LF
5%
1/16W
0
402
R7052
1 2
1%
1/16W
402
332K
MF-LF
R7086
1
2
MF-LF
1/16W
5%
62K
402
R7081
1
2
20%
0.22UF
603
X5R
25V
C7005
1
2
49
49
6
45 48 64 97
6
45 48 64 97
10%
402
CERM
16V
0.01UF
C7011
1
2
10% X5R
16V
1UF
402
C7050
1
2
50V
CERM
402
10%
0.001UF
C7026
1
2
45 46 64
1%
0.005
0612
1W MF
BATT_2S
R7050
1 2 3 4
MF-LF
1W
0.5%
0.020
CRITICAL
0612
R7020
214
3
50V
0.001UF
10%
402
X7R
C7037
1
2
NO STUFF
402
10% 50V CERM
470PF
C7039
1
2
5%
MF-LF
1/10W
180
603
NO STUFF
R7039
1
2
0.001UF
10% 50V
402
X7R
C7045
1
2
TQFN
ISL6259HRTZ
CRITICAL
U7000
3
14
1
9
16
15
25
6
27
28
17
18
2
5
21
22
23
11 10
26
13
29
24
7
19
20
4
12
8
1/16W
100K
5%
402
MF-LF
NO STUFF
R7002
1
2
73
CRITICAL
SO-8
SI7137DP
Q7055
5
4
1 2 3
MF-LF
1%
402
1K
BATT_2S
1/16W
R7013
1
2
CRITICAL
BAT30CWFILM
SOT-323
D7005
1
2
3
HAT1128R01
SOI
CRITICAL
Q7085
5
6
7
8
4
1
2
3
SOI
HAT1128R01
CRITICAL
Q7080
5
6
7
8
4
1
2
3
10% X5R
25V 402
0.1UF
C7085
1
2
5%
100K
1/16W MF-LF 402
R7080
1
2
470K
1% 1/16W MF-LF
402
R7085
1
2
1/16W
BATT_3S
MF-LF
1%
402
1K
R7012
1
2
FDA1254F-SM
CRITICAL
4.7UH-10.2A
L7030
1
2
3
CRITICAL
RJK0332DPB-01
LFPAK-SM
Q7030
5
4
1 2 3
POLY-TANT
25V
CRITICAL
20%
22UF
CASE-D2-SM
C7040
1
2
MF-LF
1/16W
5%
20
402
R7005
1 2
X5R
25V
10%
1UF
603-1
C7035
1
2
X5R
25V
10%
1UF
603-1
C7036
1
2
603-1
1UF
10% 25V X5R
C7055
1
2
5%
0
1/16W MF-LF
402
R7000
1 2
1
RES,0.010,0.5%,1W,0612-1
R7050
107S0139
BATT_3S
CRITICAL
PBus Supply & Battery Charger
SYNC_MASTER=K18_POWER
SYNC_DATE=06/30/2009
VOLTAGE=18.5V
MIN_LINE_WIDTH=0.6 mm
PPDCIN_G3H_CHGR
MIN_NECK_WIDTH=0.4 mm
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm SWITCH_NODE=TRUE
DIDT=TRUE
CHGR_PHASE
DIDT=TRUE
GATE_NODE=TRUE
CHGR_UGATE
DIDT=TRUE
GATE_NODE=TRUE
CHGR_LGATE CHGR_BGATE
CHGR_VNEG
CHGR_VCOMP
SMBUS_SMC_BSA_SCL
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.4 mm
PPDCIN_G3H_INRUSH
VOLTAGE=18.5V
CHGR_AGATE_DIV
MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.3 mm
CHGR_CSI_R_P
CHGR_CSI_R_N
PPBUS_G3H
PPVBAT_G3H_CONN
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.4 mm VOLTAGE=12.6V
CHGR_SGATE_DIV
MIN_NECK_WIDTH=0.3 mm
MIN_LINE_WIDTH=0.3 mm
CHGR_CSO_R_N
CHGR_VNEG_R
CHGR_CSO_R_P
SMBUS_SMC_BSA_SDA
CHGR_PHASE_RC
DIDT=TRUE
VOLTAGE=12.6V
MIN_NECK_WIDTH=0.4 mm
MIN_LINE_WIDTH=0.6 mm
PPVBAT_G3H_CHGR_REG
CHGR_DCIN_D_R
CHGR_ICOMP
CHGR_CSO_P
CHGR_AGATE
CHGR_BMON
CHGR_AMON
SMC_BC_ACOK
CHGR_SGATE
MIN_LINE_WIDTH=0.2 mm
PP5V1_CHGR_VDDP
MIN_NECK_WIDTH=0.2 mm VOLTAGE=5.1V
CHGR_CSI_N
CHGR_DCIN
DIDT=TRUE
CHGR_BOOT
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.4 mm
PPDCIN_G3H_OR_PBUS
VOLTAGE=18.5V
CHGR_CSI_P
PPVBAT_G3H_CHGR_R
VOLTAGE=12.6V
MIN_NECK_WIDTH=0.4 mm
MIN_LINE_WIDTH=0.6 mm
CHGR_VCOMP_R
GND_CHGR_AGND
SMC_RESET_L
CHGR_CELL
PPDCIN_G3H
CHGR_VFRQ
VOLTAGE=0V
GND_CHGR_AGND
MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm
CHGR_ACIN
PP5V1_CHGR_VDD
MIN_NECK_WIDTH=0.1 mm
MIN_LINE_WIDTH=0.2 mm VOLTAGE=5.1V
CHGR_CSO_N
CHGR_RST_L
PP3V42_G3H
70 OF 132
<E4LABEL>
<SCH_NUM>
<BRANCH>
65 OF 101
99
99
6 7
40 49 66 67 69 70 82
86 89
6
64
49 99
49 99
97
97
64
97
65
6 7
64
65
97
6 7
17 21 23 43 45 46 47 48
49 53 64 66 73
Page 66
DRVH1
SKIPSEL
VBST1
GND
THRM_PAD
ENTRIP1
VFB1
VO1
DRVL1
LL1
EN0
VCLK
ENTRIP2
PGOOD
VO2
VFB2
DRVL2
LL2
DRVH2
VBST2
VREG5
VREG3
VREF
VIN
TONSEL
D
SG
D
SG
S
D
G
OUT
D
SG
G
D
S
D
SG
NC
D1
G1
S2
G2
S1/D2
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
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BRANCH
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DRAWING NUMBER
SIZE
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IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
One master PGOOD for both 5V and 3V3
(P5VS5_VO1)
152S1115
f=365KHz
(L7260 limit)
9.1A MAX OUTPUT
(Q7220 limit)
Vout = 5.0V
.
Vout = 3.3V
7.2A MAX OUTPUT
f=460KHz
(P3V3S5_V02)
402
0.001UF
CERM
10% 50V
C7291
1
2
SM
PLACE_NEAR=L7260.1:1mm
XW7260
1
2
NO STUFF
10
MF-LF
402
5%
1/16W
R7262
1
2
NO STUFF
100PF
CERM
402
5%
50V
C7262
1
2
0.1UF
X7R
50V
10%
603-1
C7264
1
2
5%
0
MF-LF
402
1/16W
R7264
12
6.49K
MF-LF 402
1% 1/16W
R7260
1
2
10K
MF-LF 402
1% 1/16W
R7261
1
2
402
MF-LF
1/16W
1%
88.7K
R7206
1
2
20%
10UF
603
X5R
10V
C7205
1
2
MF-LF
1/16W
100K
402
5%
R7273
1
2
402
CERM
10V
10%
0.22UF
C7201
1
2
NO STUFF
25V
220PF
CERM 402
5%
C7208
1
2
QFN
TPS51125
CRITICAL
U7201
21 10
19 12
13
1 6
15
20 11
23
14
25
4
22 9
18
2 5
16
24 7
3
8
17
SSM6N15FEAPE
SOT563
Q7211
3
5
4
10UF
6.3V
20% X5R
603
C7290
1
2
SM
PLACE_NEAR=U7201.25:1mm
XW7200
1 2
SOT563
SSM6N15FEAPE
Q7210
6
2
1
10K
402
5% 1/16W MF-LF
R7210
1
2
1UF
X5R
603-1
10% 25V
C7200
1
2
402
0
5%
MF-LF
1/16W
R7224
12
88.7K
MF-LF
1% 1/16W
402
R7200
1
2
0.1UF
50V 603-1
X7R
10%
C7224
1
2
1UF
10% 603-1
X5R
25V
C7241
1
2
150UF-.025-OHM
6.3V CASE-B2-SM
20% TANT
CRITICAL
C7292
1
2
CRITICAL
SIS424DN
PWRPK-1212-8-SM
Q7220
5
4
123
CERM
50V 402
5%
100PF
NO STUFF
C7222
1
2
PCMB104E4R7-SM
4.7UH-13A-15MOHM
CRITICAL
L7220
1 2
402
MF-LF
5%
10
1/16W
NO STUFF
R7222
1
2
10UF
X5R
20% 10V
805
C7250
1
2
SM
PLACE_NEAR=L7220.1:1mm
XW7220
1
2
10% 402
50V
CERM
0.001UF
C7282
1
2
73
SOT563
SSM6N15FEAPE
Q7210
3
5
4
1/16W 402
15.0K
1% MF-LF
R7220
1
2
10K
MF-LF 402
1% 1/16W
R7221
1
2
50V
0.001UF
402
10%
CERM
C7243
1
2
50V CERM
10%
0.001UF
402
C7251
1
2
6.3V
POLY-TANT
20%
CRITICAL
CASE-D3L-SM1
330UF
C7252
1
2
CRITICAL
SIS426DN
PWRPK-12128
Q7225
5
4
123
1UF
X5R 603-1
10% 25V
C7281
1
2
SSM6N15FEAPE
SOT563
Q7211
6
2
1
10K
MF-LF
1/16W 402
5%
R7211
1
2
SM
PLACE_NEAR=C7252.1:1mm
XW7221
1
2
PLACE_NEAR=C7292.1:1mm
SM
XW7261
1
2
CRITICAL
68UF
CASE-D2E-SM
POLY-TANT
20% 16V
C7240
1
2
CRITICAL
20%
POLY-TANT
68UF
CASE-D2E-SM
16V
C7280
1
2
25V
603-1
1UF
10% X5R
C7203
1
2
2.2UH-10A-14MOHM
FDVE0830-SM
CRITICAL
L7260
1 2
CRITICAL
WPAK
RJK0384DPA
Q7260
2
1
6
7
345
5V / 3.3V Power Supply
SYNC_MASTER=K18_POWER
SYNC_DATE=07/13/2009
PP5V_S3
P3V3S5_VFB
P5VS3_VFB
P3V3S5_ENTRIP
P3V3_S5_V02_XW
SMC_PM_G2_EN
P5VS3_RC
P5VS3_VBST_R
P5VS3_EN
P5VS3_EN_L
PP3V42_G3H
PP3V42_G3H
P3V3S5_EN
P5V_S3_REG_XW
P3V3_S5_REG_XW
P3V3S5_VBST_R
MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.6 mm
DIDT=TRUE
SWITCH_NODE=TRUE
P5VS3_LL
P5V_S3_V01_XW
P5VP3V3_VREF
DIDT=TRUE
P5VS3_DRVH
MIN_LINE_WIDTH=0.6 mm
GATE_NODE=TRUE
MIN_NECK_WIDTH=0.2 mm
PP3V3_S5
P3V3S5_EN_L
P5VS3_ENTRIP
P5V3V3_PGOOD
PP5V_S5
P5VP3V3_VREG3
GND_P5VP3V3_SGND
VOLTAGE=0V
MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.6 mm
5V3V3_REG_EN
PPBUS_G3H
MIN_NECK_WIDTH=0.2 mm
DIDT=TRUE
P3V3S5_DRVH
GATE_NODE=TRUE
MIN_LINE_WIDTH=0.6 mm
P3V3S5_LL
MIN_NECK_WIDTH=0.2 mm
DIDT=TRUE
MIN_LINE_WIDTH=0.6 mm
SWITCH_NODE=TRUE
P3V3S5_RC
MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.6 mm
P3V3S5_DRVL
GATE_NODE=TRUE
DIDT=TRUE
P3V3S5_VBST
MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.6 mm
P5VS3_VBST
MIN_NECK_WIDTH=0.2 mm
P5VS3_DRVL
DIDT=TRUE
GATE_NODE=TRUE
MIN_LINE_WIDTH=0.6 mm
72 OF 132
<E4LABEL>
<SCH_NUM>
<BRANCH>
66 OF 101
6 7
31 33 42 43 44 46 54 56 58 61 67 72
82
101
45 73
73
6 7
17 21 23 43 45 46 47 48
49 53 64 65 66 73
6 7
17 21 23 43 45 46
47 48 49 53 64 65 66 73
73
6 7
17 18 19
20 21 23 27
31 35 57 71
72 73 83 85
99
6 7
23 72
6 7
40 49 65 67 69 70 82 86
89
Page 67
MODE
VDDQSNS
COMP
NC0 NC1
VTTSNS
VTT
VTTREF
PGOOD
S3 S5
VTTGND
THRM_PAD
GND
CS_GND
PGND
CS
LL
DRVL
DRVH
VDDQSET
VBST
VLDOINV5FILT
V5IN
SYM (2 OF 2)
IN IN OUT
NC NC
S
D
G
OUT
OUT
S
D
G
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
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DRAWING NUMBER
SIZE
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R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
Vout = 0.75V * (1 + Ra / Rb)
(DDRREG_LL)
<Ra>
Vout = 1.5V
(DDRREG_DRVL)
(DDRREG_CSGND)
f = 400 kHz
(Q7335 limit)
13A max output
<Rb>
VDDQ/VTTREF Enable
VTT Enable
VDDQ PGOOD
Vout = VTTREF
(DDRREG_DRVH)
10mA max load Vout = VDDQSNS/2
(DDRREG_FB)
(DDRREG_VDDQSNS)
C7360, C7361 close to memory
0.1UF
X7R
603-1
10% 50V
C7325
1 2
1%
402
MF-LF
15.0K
1/16W
PLACE_NEAR=L7330.2:1mm
R7320
1
2
1/16W
1%
402
15.0K
MF-LF
R7321
1
2
25V
10%
603-1
X5R
1UF
C7332
1
2
CRITICAL
QFN
TPS51116
U7300
6
16
17
21
19
3
20
4
7
12
18
13
10 11
25
14
15
22
9
8
23
24
1
5
2
1UF
10% 10V
402-1
X5R
C7305
1
2
1/16W
5%
402
MF-LF
4.7
R7305
1 2
PLACE_NEAR=C3101.1:3mm
CRITICAL
6.3V
20%
22UF
X5R-CERM 603
C7361
1
2
PLACE_NEAR=C3101.1:1mm
22UF
20%
6.3V
X5R-CERM
603
CRITICAL
C7360
1
2
PLACE_NEAR=C3101.1:1mm
SM
XW7360
1 2
SM
PLACEMENT_NOTE=Place next to Q7335
XW7335
1 2
402
0.033UF
16V
10% X5R
C7350
1
2
8
31
603
20% X5R
10UF
10V
C7300
1
2
73
1% 1/16W MF-LF
402
5.23K
R7310
1
2
73
CRITICAL
20%
POLY-TANT
16V
CASE-D2E-SM
68UF
C7330
1
2
POLY-TANT
20%
CRITICAL
16V
CASE-D2E-SM
68UF
C7331
1
2
1.0UH-21A
CRITICAL
FDU1040D-SM
L7330
1 2
6.3V
20% 603
X5R
10UF
C7355
1
2
SM
XW7300
1
2
CRITICAL
20%
270UF
TANT
2V
CASE-B4-SM
C7341
1
2
CRITICAL
20%
270UF
TANT
2V CASE-B4-SM
C7340
1
2
6.3V
20% 603
X5R
10UF
C7345
1
2
50V
10%
402
X7R
0.001UF
C7333
1
2
50V
10%
402
X7R
0.001UF
C7346
1
2
MLP5X6-LFPAK-Q5A
CRITICAL
CSD58856Q5A
Q7330
5
4
1 2 3
50 99
50 99
MLP5X6-LFPAK-Q5
CRITICAL
CSD58857Q5
Q7335
5
4
1 2 3
0612
1%
0.001
MF-1
1W
CRITICAL
R7350
2 1
4 3
402
MF-LF
0
5%
1/16W
R7325
1 2
SM
XW7301
1
2
1.5V DDR3 Supply
SYNC_DATE=07/14/2009
SYNC_MASTER=K18_POWER
PP0V75_S0_DDRVTT
PPVTTDDR_S3
MIN_NECK_WIDTH=0.17 mm
GND_DDRREG_SGND
VOLTAGE=0V
MIN_LINE_WIDTH=0.6 mm
DDRREG_DRVL
DDRREG_CSGND
MIN_NECK_WIDTH=0.17 mm
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.17 mm
MIN_LINE_WIDTH=0.6 mm
DDRREG_DRVH
DIDT=TRUE
GATE_NODE=TRUE
MIN_NECK_WIDTH=0.17 mm
MIN_LINE_WIDTH=0.6 mm
DDRREG_VBST
PPBUS_G3H
SWITCH_NODE=TRUE
MIN_LINE_WIDTH=0.6 mm
DIDT=TRUE
MIN_NECK_WIDTH=0.17 mm
DDRREG_LL
MIN_NECK_WIDTH=0.1 MM
PPDDR_S3_REG_R
MIN_LINE_WIDTH=0.8 MM
VOLTAGE=1.5V
DDRREG_VBST_R
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.17 mm
ISNS_1V5_S3_N
ISNS_1V5_S3_P
DDRREG_VTTSNS
PP1V5_S3
DDRREG_FB_XW
MIN_NECK_WIDTH=0.17 mm
MIN_LINE_WIDTH=0.2 mm
DDRREG_FB
DDRREG_CS
PP1V5_S3
VOLTAGE=5V
MIN_NECK_WIDTH=0.17 mm
MIN_LINE_WIDTH=0.6 mm
PP5V_S3_DDRREG_V5FILT
DDRREG_PGOOD
DDRREG_EN
MEMVTT_EN
PP5V_S3
73 OF 132
<E4LABEL>
<SCH_NUM>
<BRANCH>
67 OF 101
6 7
28 30 31
6 7
32
6 7
40 49
65 66 69 70
82 86 89
6 7
28 30 31 67 72
32
6 7
28 30 31 67 72
6 7
31 33 42 43 44 46 54 56 58 61 66 72
82
101
Page 68
S
D
G
G
D
S
S
D
G
G
D
S
OSRSEL
TRIPSEL
IMON
TONSEL
PGND
GND
THRM
CSP2 CSN2
CSN1
SLEW
CSP1
VID5 VID6
VID3 VID4
VID2
VID0 VID1
VREF
VSNS GNDSNS
DROOP
PSI*
CLK_EN*
DRVL2
PGOOD
LL2
DRVH2
VBST2
DRVL1
LL1
VBST1 DRVH1
V5IN
V5FILT
VR_ON
DPRSLPVR
MODE
THERM
VR_TT*
PAD
IN
IN
IN
IN
IN
IN
IN
IN IN
IN
IN
IN
OUT OUT
OUT
OUT
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER
SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
(CPUIMVP_PHASE1)
48A max current
(CPUIMVP_PHASE2)
353S2942
IMON output range: 1.1V
Loadline = DCR * K * 5.95 / (R7403 * 2uA/mV)
Loadline = 1.83 mohm
VIMON = Io * DCR * 2uA/mV * R7450 50 A = 1.00 V
K = (R7417 || (R7418 + R7419)) / (R7417 || (R7418 + R7419) + R7416) = 0.66
1
10%
0.22UF
CERM
10V
2
402
C7402
5%
33PF
1 2
C7403
50V
CERM
402
R7403
1% 1/16W MF-LF
402
21
3.92K
1/16W 402
16.9K
1% MF-LF
2
1
R7450
10% CERM
50V
C7450
402
1
2
0.0033UF
Q7420
4
321
5
WPAK
RJK0365DPA-02
CRITICAL
Q7425
5
321
4
WPAK
RJK0208DPA
CRITICAL
Q7410
4
321
5
WPAK
RJK0365DPA-02
CRITICAL
Q7415
5
321
4
WPAK
RJK0208DPA
CRITICAL
C7420
27.0NF
X5R
10V
10%
1 2
402
R7416
22.1K
1% 1/16W MF-LF 402
2
1
1%
294K
1/16W MF-LF
R7417
1 2
402
402
21
1%
41.2K
1/16W MF-LF
R7419
2 1
0402
R7418
150KOHM-5%
MF-LF
1/16W
1%
1 2
402
R7429
41.2K
1%
294K
1/16W MF-LF
2
R7427
402
1
27.0NF
X5R
10%
1 2
402
C7430
10V
22.1K
1/16W
1
2
402
R7426
1% MF-LF
2 1
0402
R7428
150KOHM-5%
XW7400
SM
2 1
C7440
NONE NONE
NOSTUFF
NONE
OMIT
402
1
2
C7441
OMIT
NONE
NOSTUFF
NONE
NONE
402
1
2
C7442
NONE NONE
NOSTUFF
NONE
OMIT
402
1
2
C7443
OMIT
NONE
NOSTUFF
NONE
NONE
402
1
2
MF-LF
1/16W
5%
0
402
2
1
R7430
MF-LF
1/16W
5%
0
402
2
1
R7431
0
5% 1/16W MF-LF
402
2
1
R7421
0
5% 1/16W MF-LF
402
2
1
R7422
1
2
CASE-D2E-SM
68UF
POLY-TANT
16V
20%
CRITICAL
C7415
SM
2
XW7427
1
PLACE_NEAR=L7425.2:4mm
SM
1
PLACE_NEAR=L7415.2:4mm
XW7417
2
C7414
1UF
10% 25V X5R21603-2
CASE-D2E-SM
PLACE_NEAR=Q7410.1:8mm
CRITICAL
20%
POLY-TANT
16V
2
1
C7410
68UF
PLACE_NEAR=Q7410.1:8mm
10% 25V X5R
C7411
1
2
805
10UF
SM
1
2
XW7426
PLACE_NEAR=L7425.1:4mm
PLACE_NEAR=L7415.1:4mm
XW7416
2
1
SM
10%
10UF
X5R
25V 805
C7421
1
2
PLACE_NEAR=Q7420.1:8mm
2
C7401
20%
2.2UF
X5R-CERM
10V 402
1
PLACE_NEAR=Q7410.1:8mm
0.001UF
2
1
C7412
10% 50V
402
X7R
PLACE_NEAR=Q7420.1:8mm
10%
402
X7R
50V
1
2
0.001UF
C7422
31
20
TPS51621
25
CRITICAL
QFN
10
9
1
12
35
38
26
21
22
23 24
29 30 28
33
27
34
13
39
7
8
40
19 18
16
17
14
15
6
37
5
4
3
41
2
36
11
32
U7400
8
8
8
8
8
8
8
68UF
C7413
POLY-TANT
CASE-D2E-SM
16V
20%
CRITICAL
PLACE_NEAR=Q7410.1:8mm
1
2
12
402
5%
1/16W MF-LF
0
R7414
PIMA104E-SM
1 2
L7425
0.36UH-20%-40A-0.00075OHM
CRITICAL
21
0.36UH-20%-40A-0.00075OHM
CRITICAL
L7415
PIMA104E-SM
CRITICAL
C7405
68UF
CASE-D2E-SM
PLACE_NEAR=Q7410.1:8mm
1
2
16V
20%
POLY-TANT
12 91
12 68 91
12 15 91
12 15 91
45
C7424
1
603-2
10%
1UF
25V X5R
2
0
MF-LF1/16W
5%
402
2 1
R7424
10 46 91
12 50 91
MF-LF12402
0
R7440
1/16W
5%
26
27
MF-LF
402
2
1
249K
1%
1/16W
R7400
10%
4.7UF
X5R
10V
C7400
2
1
805
R7445
1
2
402
MF-LF
1/16W
5%
100K
SYNC_DATE=06/29/2009
CPU IMVP VCore Regulator
SYNC_MASTER=K18_POWER
PPBUS_CPU_IMVP_ISNS
PP5V_S0_CPUIMVP_V5FILT
MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=5V
CPUIMVP_VREF CPUIMVP_VID<0>
CPUIMVP_IMON
PP3V3_S0
CPU_VCCSENSE_N
VOLTAGE=0V
MIN_NECK_WIDTH=0.15 mm
MIN_LINE_WIDTH=0.6 mm
CPUIMVP_AGND
PP5V_S0
CPUIMVP_DROOP
CPU_VCCSENSE_N
CPUIMVP_NTC
PM_DPRSLPVR CPU_PSI_L
CPUIMVP_BOOT1
CPUIMVP_PGOOD
CPUIMVP_ISEN2_NTC
MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.15 MM
CPUIMVP_ISEN2N_R
CPUIMVP_ISEN1P_R
MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.15 MM
CPUIMVP_ISEN1_NTC
CPUIMVP_VID<4>
CPUIMVP_VID<2>
CPUIMVP_VID<5> CPUIMVP_VID<6>
CPUIMVP_VID<3>
CPUIMVP_VID<1>
CPU_VCCSENSE_P
CPUIMVP_CLK_EN_L
CPUIMVP_BOOT2
CPUIMVP_VR_ON
CPUIMVP_VR_TT_L
CPU_PROCHOT_L
CPUIMVP_BOOT1_RC
CPUIMVP_PHASE2X
MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.15 MM
CPUIMVP_BOOT2_RC
CPUIMVP_SLEW
CPUIMVP_ISEN1P CPUIMVP_ISEN1N
CPUIMVP_ISEN2P
CPUIMVP_PHASE1X
MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.15 MM
CPUIMVP_ISEN2P_R
MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.15 MM
MIN_NECK_WIDTH=0.15 MM
MIN_LINE_WIDTH=0.25 MM
CPUIMVP_ISEN1N_R
CPUIMVP_ISEN2P
MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.15 MM
MIN_NECK_WIDTH=0.15 MM
MIN_LINE_WIDTH=0.25 MM
CPUIMVP_ISEN1P
PPVCORE_S0_CPU
MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.15 MM
CPUIMVP_ISEN1N
MIN_NECK_WIDTH=0.15 MM
MIN_LINE_WIDTH=0.25 MM
CPUIMVP_ISEN2N
CPUIMVP_ISEN2N
CPUIMVP_UGATE1
MIN_NECK_WIDTH=0.2 MM
GATE_NODE=TRUE
DIDT=TRUE
MIN_LINE_WIDTH=0.5 MM
MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM
GATE_NODE=TRUE
DIDT=TRUE
CPUIMVP_UGATE2
CPUIMVP_PHASE1
SWITCH_NODE=TRUE
DIDT=TRUE
MIN_LINE_WIDTH=1.5 MM MIN_NECK_WIDTH=0.2 MM
CPUIMVP_PHASE2
MIN_LINE_WIDTH=1.5 MM MIN_NECK_WIDTH=0.2 MM
DIDT=TRUE
SWITCH_NODE=TRUE
GATE_NODE=TRUE
MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM
CPUIMVP_LGATE1
DIDT=TRUE
DIDT=TRUE
GATE_NODE=TRUE
MIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.5 MM
CPUIMVP_LGATE2
74 OF 132
<E4LABEL>
<SCH_NUM>
<BRANCH>
68 OF 101
7
49
6 7
17 18 19 20 21
23 24 25 26 27 28 30 34 37
40 42 46 47 48 50 51
52 54 58 62 63 69 72 73 80
83 84 85 87 88 99
12 68 91
6 7
23 42 47 52 54
69 70 72 86 88
68
68
68
68
68
6 7
12 15 49
68
68
68
Page 69
PGND
GND
TRIPSEL
IMON
MODE
DPRSLPVR
VR_ON
CLK_EN*
PGOOD
DRVL
LL
DRVH
CSN
CSP
ISLEW
VID6
VID5
VID4
VID3
VID2
VID1
VID0
VREF
GNDSNS
VSNS
VBST
V5FILT
DROOP TONSEL
V5IN
THERM
VR_TT*
IMONC
IN IN IN IN IN
IN
IN
IN
IN IN
IN
OUT
NC
NC
S
D
G
OUT
S
D
G
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER
SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
GFX IMVP VCORE
Imon= Io xR7540 x2uA/mV x R7515
353S2664
(GND_GFXIMVP_AGND)
Vout = VID controlled f = 350KHz
22A max output
22A => 1V
(GFX_VSENSE_N)
(GND_GFXIMVP_AGND)
Imon= Io x45.2mV/A
TPS51981
CRITICAL
QFN
U7500
24
3
2
9
31
17
20
1
4
8
28
29
19
22
33
23
6
27
26
30
21
18
16 15 14 13 12 11 10
25
7
32
5
8
8
8
8
8
8
8
13 91
13 91
13 91
MF-LF 402
1/16W
1%
1.69K
R7511
1
2
402
33PF
CERM
5%
50V
C7511
1
2
1K
1% 1/16W MF-LF
402
R7512
1
2
13 91
10V 402
CERM
10%
0.22UF
C7512
1
2
2.2UF
10% X5R
603
16V
C7513
1
2
PLACE_NEAR=U7500.3:2mm
5% 1/16W MF-LF
402
0
R7542
1 2
PLACE_NEAR=U7500.2:2mm
MF-LF
1/16W
5%
0
402
R7541
1 2
PLACE_NEAR=U7500.2:2mm
OMIT
402
NONE
NOSTUFF
NONE
NONE
C7541
1
2
PLACE_NEAR=U7500.3:2mm
NOSTUFF
OMIT
402
NONE
NONE
NONE
C7542
1
2
0.0033UF
SIGNAL_MODEL=EMPTY
10% 50V
CERM
402
C7515
1
2
SIGNAL_MODEL=EMPTY
MF-LF
1%
402
1/16W
22.6K
R7515
1
2
73
402
MF-LF
1/16W
5%
0
R7514
1
2
16V
10% X5R
402
1UF
C7514
1
2
16V
10%
603
2.2UF
X5R
C7510
1
2
1UF
10% X5R
603-1
25V
C7523
1
2
POLY-TANT
16V
CASE-D2E-SM
20%
68UF
CRITICAL
C7520
1
2
CRITICAL
20%
68UF
16V
POLY-TANT
CASE-D2E-SM
C7521
1
2
CRITICAL
1%
0.001
1W MF-1 0612
R7540
2 1 4 3
603
X5R
6.3V
20%
10UF
C7556
1
2
NO STUFF
SOT-323
BAT30CWFILM
D7514
1
2
3
SM
PLACE_NEAR=U7500.33:1mm
PLACE_NEAR=U7500.1:1mm
XW7500
12
CRITICAL
CSD58857Q5
MLP5X6-LFPAK-Q5
Q7535
5
4
1 2 3
PLACE_NEAR=U7500.2:2mm
402
50V
CERM
5%
10PF
C7549
1
2
MF-LF 402
1/16W
150K
1%
R7516
1
2
200K
1% MF-LF
402
1/16W
R7517
1
2
13 91
CRITICAL
FDU1040D-SM
0.68UH-27A-1.7MOHM
L7530
1 2
CSD58856Q5A
MLP5X6-LFPAK-Q5A
CRITICAL
Q7530
5
4
1 2 3
NO STUFF
5%
0
1/16W MF-LF 402
R7509
1
2
0
5%
1/16W MF-LF 402
R7510
1
2
5%
1000PF
NP0-C0G
25V 402
C7557
1
2
5%
1000PF
NP0-C0G
25V 402
C7524
1
2
MF-LF
1/16W
1%
100K
402
R7518
1
2
10%
0.022UF
CERM-X5R
16V 402
C7517
1
2
603
46.4K
1% 1/10W MF-LF
R7513
1
2
GFX IMVP VCore Regulator
SYNC_MASTER=K18_POWER
SYNC_DATE=07/08/2009
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0V
GND_GFXIMVP_AGND
GFX_VSENSE_N
GFXIMVP_ISLEW
GFXIMVP_VREF
GFXIMVP_VREF_R
PP3V3_S0
GFXIMVP_CS_P
GFXIMVP_VID<4>
GFXIMVP_VID<3>
GFXIMVP_VID<2>
GFXIMVP_VID<1>
GFXIMVP_VID<0>
GFXIMVP_VID<5> GFXIMVP_VID<6>
GFXIMVP_CS_N
GFXIMVP_IMON
PP3V3_S0
GFXIMVP_THERM
GFX_DPRSLPVR
GFXIMVP_PGOOD
GFXIMVP_V5FILT
DIDT=TRUE
GFXIMVP_UGATE
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm GATE_NODE=TRUE
GFXIMVP_VREF
PP5V_S0
GFXIMVP_IMONC
GFX_VR_EN
GFXIMVP_DROOP
GFXIMVP_VBST
GFXIMVP_VBST_R
DIDT=TRUE
MIN_LINE_WIDTH=0.6 mm
GFXIMVP_PHASE
SWITCH_NODE=TRUE
MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.6MM
DIDT=TRUE
GATE_NODE=TRUE
MIN_NECK_WIDTH=0.2MM
GFXIMVP_LGATE
GFX_VSENSE_P
GFXIMVP_TONSEL
VOLTAGE=1.05V
MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.6 mm
PPVCORE_S0_GFX_REG_R
PPVCORE_S0_GFX
GFXIMVP_CS_R_P
GFXIMVP_CS_R_N
PP5V_S0
PPBUS_G3H
75 OF 132
<E4LABEL>
<SCH_NUM>
<BRANCH>
69 OF 101
69
6 7
17 18 19 20 21 23 24 25 26
27 28 30 34 37 40 42 46 47 48
50 51 52 54 58 62 63 68 69 72
73 80 83 84 85 87
88 99
99
99
6 7
17 18 19 20 21 23 24 25
26 27 28 30 34 37 40 42 46 47
48 50 51 52 54 58 62 63 68
69 72 73 80 83 84 85 87 88
99
69
6 7
23 42 47 52 54 68 69 70 72 86
88
6 7
13 24 49
50 99
50 99
6 7
23 42 47 52 54 68 69 70
72 86 88
6 7
40 49 65 66 67 70 82 86
89
Page 70
IN
S
D
G
S
D
G
BOOT
UGATE
LGATE
PHASE
RTN
FSEL
PGOOD
OCSET
VO
SREF
VCC
PVCC
GND
PGND
EN
FB
IN
IN
OUT
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER
SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
CPU VTT (1.05V S0) Regulator
152S1085
(CPUVTTS0_VO)
(CPUVTTS0_OCSET)
(CPUVTTS0_FB)
(CPUVTTS0_AGND)
Vout = 1.05V 27A max output f = 300 kHz
<Rb>
<Ra>
Vout = 0.5V * (1 + Ra / Rb)
73
CRITICAL
MLP5X6-LFPAK-Q5
CSD58857Q5
Q7635
5
4
1 2 3
CRITICAL
CSD58856Q5A
MLP5X6-LFPAK-Q5A
Q7630
5
4
1 2 3
CRITICAL
1%
0.001
1W MF-1 0612
R7640
2 1 4 3
402
16V X5R
1UF
10%
C7630
1
2
CRITICAL
20%
POLY-TANT
16V
CASE-D2E-SM
2
68UF
1
C7620
10% X7R
50V
0.001UF
C7622
1
2
402
X5R
20%
603
10UF
6.3V
C7647
1
2
CRITICAL
20%
68UF
POLY-TANT
CASE-D2E-SM
2
1
16V
C7623
603
10V X5R
10UF
20%
C7601
1
2
603
MF-LF
2.2
5%
R7601
1
2
1/10W
SM
XW7600
1 2
0.047UF
10%
402
10V CERM
C7603
1
2
402
5%
0
1/16W MF-LF
R7630
12
CPUVTTS0_CS_P
3.48K
1%
MF-LF
402
1/16W
R7641
1
2
1000PF
402
5%
25V
NP0-C0G
C7640
12
3.48K
1/16W 402
MF-LF
1%
R7642
1
2
NO STUFF
MF-LF
1%
100
1/16W
402
SIGNAL_MODEL=EMPTY
R7643
2
1
1% MF-LF
3.01K
1/16W 402
R7644
2
1
402
MF-LF
2.74K
1% 1/16W
R7645
1
2
UTQFN
CRITICAL
ISL95870
U7600
12
3
6
5
1
15
7
16
9
10
14
2
4
11
13
8
SIGNAL_MODEL=EMPTY
NO STUFF
10% 50V
CERM
0.0022UF
402
C7641
1
2
FDU1040D-SM
0.68UH-27A-1.7MOHM
CRITICAL
L7630
1 2
2.2UF
X5R
16V
10%
603
C7602
1
2
402
0
5% 1/16W MF-LF
R7603
1
2
12 91
12 91
10 91
50V 402
0.001UF
X7R
10%
C7605
1
2
402
10% X7R
50V
0.001UF
C7604
1
2
1/16W MF-LF
3.01K
1%
402
R7604
1 2
402
MF-LF
2.74K
1%
1/16W
R7605
1
2
CRITICAL
POLY-TANT
16V
CASE-D2E-SM
2
1
20%
68UF
C7621
SYNC_DATE=07/14/2009
SYNC_MASTER=K18_POWER
CPUVTT (1.05V) Power Supply
CPUVTTS0_PGOOD
CPU_VTTSENSE_P
CPU_VTTSENSE_N
CPUVTTS0_OCSET
CPUVTTS0_VO
CPUVTTS0_AGND
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0V
CPUVTTS0_RTN
CPUVTTS0_SREF
VOLTAGE=5V
MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.6 mm
PP5V_S0_CPUVTTS0_VCC
CPUVTTS0_FB
CPUVTTS0_FB_RC
CPUVTTS0_EN
PP5V_S0
CPUVTTS0_FSEL
DIDT=TRUE
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm GATE_NODE=TRUE
CPUVTTS0_DRVH
DIDT=TRUE
GATE_NODE=TRUE
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm
CPUVTTS0_DRVL
MIN_NECK_WIDTH=0.2 mm
CPUVTTS0_VBST
MIN_LINE_WIDTH=0.3 mm
MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm
CPUVTTS0_BOOT_RC
MIN_NECK_WIDTH=0.2 mm SWITCH_NODE=TRUE
MIN_LINE_WIDTH=0.6 mm
CPUVTTS0_LL
DIDT=TRUE
VOLTAGE=1.05V
MIN_NECK_WIDTH=0.2 mm
PPCPUVTT_S0_REG_R
MIN_LINE_WIDTH=0.6 mm
PP1V05_S0
CPUVTTS0_CS_N
PPBUS_G3H
76 OF 132
<E4LABEL>
<SCH_NUM>
<BRANCH>
70 OF 101
50 99
6 7
23 42 47 52 54 68 69 72
86 88
6 7
10 12 13 15 17 18 20 21 23
24 25 26 40 73 86
50 99
6 7
40 49 65 66 67 69 82 86
89
Page 71
IN
NC
IN
BIAS
NC
OUT
THRM
EN
PADGND
EN
MODE
VID1
LX
VOUT
VIN
VID0
SYNC/PWM
THRM
PGND
GND
PAD
OUT
IN
NC
VFB
LX
SYNCH
PG
EN
SGND
PGND
THRM_PAD
VIN
VDD
LX
NC
NC
NC
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER
SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
152S1088
Freq = ???
Vout = 1.794V Max Current = 2.7A
<Ra>
Vout = 0.8V * (1 + Ra / Rb)
<Rb>
Vout = 1.2V
1.8V S0 Regulator
152S0771
FREQ = 1MHZ
MAX CURRENT = 0.7A
1.2V S3 Regulator
353S2719
Ibex Peak-M requires JTAG pull-ups to be powered at 1.05V in S5.
1.05V S5 LDO
70mA is required to support pull-ups. Alternative is strong voltage dividers (200/100) to 3.3V S5, which burns 100mW in all S-states.
Pull-ups (3) must be 51 ohms to support XDP (not required in production).
Max Current = 0.35A
Vout = 1.05V
CERM
6.3V
22UF
20%
805
C7761
1
2
CRITICAL
PCAA031B-SM
P1V2ENET_SW
2.2UH-1.2A
L7760
1 2
CERM
20%
22UF
6.3V 805
C7760
1
2
8
73
CRITICAL
IHLP2020CZ
1.0UH-6.5A
L7720
1 2
X5R 402
XDP_PCH
6.3V
10%
2.2UF
C7741
1
2
SON
CRITICAL
XDP_PCH
TPS720105
U7740
4
3
5
6
2
1
7
1UF
402
CERM
6.3V
10%
XDP_PCH
C7740
1
2
SC194A
MLP10
CRITICAL
U7760
4
8
10
2
9
3
11
6
7
1
5
PLACE_NEAR=L7760.2:1MM
SM
XW7761
1 2
MF-LF
1/16W
1%
402
90.9K
R7721
1
2
CRITICAL
22UF
805
CERM
6.3V
20%
C7722
1
2
73
73
ISL8014
QFN
CRITICAL
U7720
5 14
15
6
16
13
7
11
12
9
10
4
17
3
8
1
2
20%
805
22UF
CERM
6.3V
CRITICAL
C7720
1
2
402
1/16W
1%
113K
MF-LF
R7720
1
2
CRITICAL
20%
6.3V CERM 805
22UF
C7721
1
2
402
50V CERM
47PF
5%
C7723
1
2
MF-LF
1/16W
5%
10K
402
R7722
1
2
SM
PLACE_NEAR=L7720.2:1MM
XW7700
1 2
402
5%
1000PF
NP0-C0G
25V
C7724
1
2
SYNC_MASTER=K18_POWER
SYNC_DATE=06/29/2009
Misc Power Supplies
PP3V3_S5
PP3V3_S5
PP1V05_S5
MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.4 mm
DIDT=TRUE
SWITCH_NODE=TRUE
PM_ENET_EN
P1V8S0_SW
SWITCH_NODE=TRUE DIDT=TRUE
P1V8S0_EN
P1V8S0_PGOOD
P1V2ENET_FB
PP1V2_ENET
P1V8S0_SYNCH
P1V8S0_FB
PP1V8_S0
P1V8S0_FB_XW
PP3V3_S5
77 OF 132
<E4LABEL>
<SCH_NUM>
<BRANCH>
71 OF 101
6 7
17 18 19 20 21 23 27 31
35 57 66 71 72 73 83 85 99
6 7
17 18 19 20 21 23 27 31
35 57 66 71 72 73 83 85 99
6 7
17
6 7
37 72
6 7
12 16 21 23 24 58 72 87
6 7
17 18 19 20 21 23 27 31
35 57 66 71 72 73 83 85 99
Page 72
IN
IN
IN
IN
D
SG
D
SG
S
D
G
D
G S
D
S
G
D
S
G
D
S
G
IN
D
G S
S
G
D
THRM
GND
G
PG
SHDN*
D
VCC
S
ON
PAD
NC
THRM
GND
G
PG
SHDN*
D
VCC
S
ON
PAD
D
S
G
THRM
GND
G
PG
SHDN*
D
VCC
S
ON
PAD
IN
IN
NC
NC
G
S
D
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER
SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
RDS(ON)
1.568 A (EDP)
3.3V S3 FET
CHANNEL
SI2312BDS N-TYPE 31 mOhm @4.5V
0.3 A (EDP)
1.8V S0 GPU_IFPX FET
3.3V S0 GPU FET
5.0V S0 FET
P-TYPE 8V/5V
23 mOhm @4.5V
LOADING
SiA417 P-TYPE 8V/5V
CHANNEL
RDS(ON)
LOADING
MOSFET
18 MOHM @4.5V
P-TYPE
TPCP8102MOSFET
RDS(ON)
LOADING
5.0V S0 FET
P-TYPE 8V/5V 23 mOhm @4.5V
SiA417
CHANNEL
RDS(ON)
SiA417
MOSFET
3.3V S0 FET
MOSFET
376S0683
3.3V S3 FET
0.8 A (EDP)
3.3V S0 FET
LOADING
23 mOhm @4.5V
2.3 A (EDP)
CHANNEL
3.5 A (EDP)
376S0748
1.5V S3/S0 FET
SI7108DN N-TYPE
3.2 A (EDP)
LOADING
RDS(ON)
CHANNEL
MOSFET
1.2V S0 FET
SI2306BDS-GE3 N-TYPE 65 mOhm @4.5V
6 mOhm @4.5V
LOADING
RDS(ON)
CHANNEL
MOSFET
1.8V S0 GPU_IFPX FET
RDS(ON)
CHANNEL
MOSFET
3.3V S0 GPU FET
APN 376S0651
1.5V S3/S0 FET
0.124 A (EDP)
LOADING
1.2V S0 FET
X5R
1UF
10V
10%
402
C7871
1
2
0.01UF
402
10% 16V
CERM
C7870
1 2
1/16W
402
5%
MF-LF
1K
R7870
1 2
1/16W
402
MF-LF
51K
5%
R7872
1
2
73 87
31
0.01UF
10% 16V
CERM
402
C7810
1 2
10% 16V
402
X5R
0.033UF
C7811
1
2
402
MF-LF
1/16W
5%
47K
R7810
1 2
MF-LF
10K
402
5%
1/16W
R7812
1
2
0.01UF
402
16V
10%
CERM
C7830
1 2
402
16V
0.033UF
10%
X5R
C7831
1
2
47K
5% 1/16W MF-LF
402
R7830
1 2
MF-LF
100K
402
1/16W
5%
R7832
1
2
18 31 43 45
46 73
49 72 73
SSM6N15FEAPE
SOT563
Q7812
6
2
1
SOT563
SSM6N15FEAPE
Q7812
3
5
4
SI7108DN
PWRPK-1212-8-HF
CRITICAL
Q7801
5
4
1 2 3
SOD-VESM-HF
SSM3K15FV
Q7872
3
1
2
SC70-6L
SIA417DJ
CRITICAL
Q7810
1
3
4 7
SIA417DJ
SC70-6L
CRITICAL
Q7830
1
3
4 7
SIA417DJ
SC70-6L
CRITICAL
Q7870
1
3
4 7
49 72 73
SOD-VESM-HF
SSM3K15FV
Q7865
3
1
2
5%
402
MF-LF
1/16W
47K
R7862
1
2
402
MF-LF
47K
1/16W
5%
R7860
1 2
402
10% 16V
0.033UF
X5R
C7861
1
2
0.01UF
10%
402
CERM
16V
C7860
1 2
TPCP8102
CRITICAL
23V1K-SM
Q7860
5 6 7 8
4
1 2 3
CRITICAL
TDFN
SLG5AP020
U7801
5
7
4
2
8
6
3
9
1
CERM
10V
0.1UF
20%
402
C7801
1
2
CRITICAL
SLG5AP020
TDFN
U7850
5
7
4
2
8
6
3
9
1
402
0.1UF
20%
CERM
10V
C7850
1
2
SI2312BDS
CRITICAL
SOT23
Q7880
3
1
2
0.1UF
402
20%
CERM
10V
C7880
1
2
SLG5AP020
TDFN
CRITICAL
U7880
5
7
4
2
8
6
3
9
1
73
73 86 87
CRITICAL
SI2306BDS-GE3
SOT23
Q7850
3
1
2
402
5%
0
1/16W MF-LF
R7801
1 2
402
5%
0
1/16W MF-LF
R7850
1 2
NO STUFF
603
6.3V
X5R-CERM
10%
4.7UF
C7802
1
2
SYNC_DATE=06/10/2009
SYNC_MASTER=K18_POWER
Power FETs
PP5V_S5
PP5V_S5
PP1V8_S0
PP5V_S3
P1V5CPU_EN
P1V5S0FET_GATE_R
P1V5S0FET_GATE
P1V2S0_GATE_R
P1V2S0_GATE
P3V3S3_SS
PP1V5_S3RS0
PP1V2_S0
PM_SLP_S4_L
P3V3S3_EN_L
EG_RAIL4_EN
PP5V_S0
PP1V8_GPUIFPX
P1V2S0_EN
PP3V3_S0GPU
PP3V3_S0
PM_SLP_S3_L_R
PM_SLP_S3_L_R
P5V0S0_EN_L
P5V0S0_SS
PP5V_S0
P3V3GPU_EN_L
PP3V3_S5
P3V3S0_EN_L
PP3V3_S5
EG_RAIL2_EN
P3V3GPU_SS
P3V3S0_SS
P1V8GPUIFPXFET_GATE
PP3V3_S3
PP3V3_S5
PP1V2_ENET
PP1V5_S3
78 OF 132
<E4LABEL>
<SCH_NUM>
<BRANCH>
72 OF 101
6 7
23 66 72
6 7
23 66 72
6 7
12 16 21 23 24 58 71 87
6 7
31 33 42 43 44 46 54 56 58 61 66 67
82
101
6 7
13 16 31 42 73 99
6 7
87
6 7
23 42 47 52
54 68 69 70 72 86
88
6 7
81
6 7
74 79 80 81 82 84
6 7
17 18 19 20 21 23 24 25 26
27 28 30 34 37 40 42 46 47 48
50 51 52 54 58 62 63 68 69 73
80 83 84 85 87 88 99
6 7
23 42 47 52 54 68 69 70 72
86 88
6 7
17 18 19 20 21 23 27 31
35 57 66 71 72 73 83 85 99
6 7
17 18 19 20 21 23 27 31
35 57 66 71 72 73 83 85 99
6 7 8
17 20 31 32 33 34 35 36 48 50 53 54
55 73 87
101
6 7
17 18 19 20 21 23 27 31
35 57 66 71 72 73 83 85 99
6 7
37 71
6 7
28 30 31 67
Page 73
OUT
OUT
IN
IN
IN
OUT
OUT
OUT
OUT
IN
IN
OUT
OUT
OUT
OUT
Y
B
A
NC
G
D
S
IN
IN
IN
G
D
S
G
D
S
G
D
S
OUT
G
D
S
G
D
S
IN
OUT
G
DS
OUT
OUT
IN IN
D
G S
OUT
IN
OUT
D
G S
IN
THRM_PAD
GND
V3MON V4MON
RST*
MR*
VDD
VDDA
V2MON
SENSE
CT
VDD
GND
RESET*
MR*
IN
IN
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER
SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
NOTE: S3 term is guaranteed by source of R7920 & Q7920, MUST BE S3 RAIL.
ENET Enable Generation
"WLAN" = ("S3" && "AP_PWR_EN" && ("AC" || "S0"))
(Need to confirm if SMC can provide 1 pin for control)
3.3V ENET FET
(IPU)
3.3V S5 ENABLE
S5 rail PWRGD
S0 ENABLE
(PM_SLP_S3_L)
V2MON THRESHOLD IS 3.0V
PM_SLP_S3_LPM_SLP_S4_L
Run (S0)
(AC_EN_L)
SMC_PM_G2_ENABLE
Sleep (S3)
State
Battery Off (G3Hot)
1
0
1
0
1
0 0
0
1 0
3.3V,5V S3 ENABLE
(PM_S4_STATE_L)
1
V3MON THRESHOLD IS 0.6V V4MON THRESHOLD IS 0.6V
EG PM_ALL_GPU_PGOOD
1
3.3V 1.05V AND 1.5V S0 RAILS MONITOR CIRCUIT
IG HIGH
PM_ALL_GFX_PGOOD
"ENET" = "S0" || ("S3" && "AC" && "WOL_EN")
up in the following order:
1) 1.05V 2) GPU 3V3 3) GPU Vcore 4) GDDR3 1V8
GT216 GPU requires rails to come
GPU Rail Sequencing
27MHZ OE EN Generation
Other S0 RAILS
EXT GPU PWRGD Pullup
Soft-Off (S5)
(PM_SLP_S3_L)
CHGR VFRQ Generation
WLAN Enable Generation
NOTE: S3 term is guaranteed by S3 pull-up on open-drain AP_PWR_EN signal.
1/16W
10K
MF-LF
5%
402
R7992
1
2
18 31 43 45 46 72 73
67 73
18 31 43 45 46 72 73
NO STUFF
0
1/16W MF-LF
PLACE_NEAR=U7980.1:2mm
5%
402
R7991
1 2
MF-LF
5%
100
402
1/16W
R7902
12
NO STUFF
0.068UF
PLACE_NEAR=Q7211.2:2mm
10V CERM
10%
402
C7902
1
2
PLACE_NEAR=U4900.L13:3mm
100K
1/16W MF-LF
402
5%
R7958
1
2
45 66
71
49 72 73
49 72 73
49 72 73
70 73
66
PLACE_NEAR=U7600.25:6mm
MF-LF
1/16W
33K
5%
402
R7981
1
2
MF-LF
100K
5%
402
1/16W
R7990
1
2
100K
5%
PLACE_NEAR=U1800.P12:5mm
1/16W MF-LF
402
R7979
1
2
6
18 31 45 73 85
402
CERM-X5R
6.3V
10%
0.47UF
PLACE_NEAR=U7600.25:6mm
C7981
1
2
66 73
MF-LF
5.1K
1/16W
5%
402
PLACE_NEAR=U7300.11:3mm
R7911
1
2
0.47UF
6.3V
10%
402
CERM-X5R
PLACE_NEAR=U7300.11:3mm
C7910
1
2
0
PLACE_NEAR=Q7210.2:3mm
MF-LF
5%
1/16W 402
R7912
1
2
0.47UF
6.3V
402
CERM-X5R
10%
NO STUFF
PLACE_NEAR=Q7210.2:3mm
C7912
1
2
1/16W
5%
0
PLACE_NEAR=U7980.1:2mm
402
MF-LF
R7994
1
2
8
73 82 86 87
5.1K
PLACE_NEAR=U7720.5:6mm
1/16W
402
5%
MF-LF
R7986
1
2
402
6.3V CERM
1UF
10%
PLACE_NEAR=U7850.2:6mm
C7985
1
2
PLACE_NEAR=U7720.5:6mm
402
10%
0.47UF
CERM-X5R
6.3V
C7986
1
2
72 73
71 73
402
100
MF-LF
1/16W
5%
R7978
1 2
SOT665
TC7SZ08AFEAPE
U7980
2
1
3
5
4
2N7002DW-X-G
SOT-363
Q7920
6
2
1
18 45 46
20
6
18 31 45 73 85
SOT-363
2N7002DW-X-G
Q7921
3
5
4
402
CERM
10%
0.22UF
10V
C7920
1
2
2N7002DW-X-G
SOT-363
Q7920
3
5
4
2N7002DW-X-G
SOT-363
Q7921
6
2
1
8
71
5%
1/16W
10K
402
MF-LF
R7920
1
2
10K
5%
1/16W
402
MF-LF
R7921
1
2
5%
MF-LF
100K
402
1/16W
R7922
1 2
SOT-363
2N7002DW-X-G
Q7925
3
5
4
2N7002DW-X-G
SOT-363
Q7925
6
2
1
20 33
33
10% 16V
402
X5R
0.033UF
C7921
1
2
CRITICAL
SOT-23-HF
NTR4101P
Q7922
3
1
2
10% 16V
CERM
0.01UF
402
C7922
12
25 27 45 87
402
0.1uF
10V
CERM
20%
PLACE_NEAR=U7971.7:2mm
C7971
1
2
66 73
8
73 82 86 87
8
73 82 86 87
5%
MF-LF
1/16W
402
0
R7997
1 2
402
MF-LF
1/16W
0
5%
R7996
1 2
1/16W MF-LF
402
5%
0
R7995
1 2
SSM3K15FV
SOD-VESM-HF
Q7995
3
1
2
1/16W MF-LF
10K
5%
402
R7999
1 2
26
8
73 82 86 87
65
10K
1/16W MF-LF
5%
402
R7931
1 2
SSM3K15FV
SOD-VESM-HF
Q7931
3
1
2
VFRQ_SLPS4
0
MF-LF
5%
1/16W 402
R7933
1 2
MF-LF
VFRQ_SLPS3
0
5%
1/16W
402
R7932
1 2
18 31 43 45 46 72 73
402
MF-LF
1/16W
5%
0
NO STUFF
R7935
1 2
CRITICAL
ISL88042IRTJJZ
TDFN
RAIL_MON
U7971
4
1
8
9
3 5 6
2
7
0.001UF
50V
20%
402
CERM
C7941
1
2
CRITICAL
TPS3808G33DBVRG4
SOT23-6
U7940
4
2
3
15
6
CERM
402
0.1uF
20% 10V
C7940
1
2
402
MF-LF
5% 1/16W
100K
R7940
1
2
NO STUFF
5%
0
MF-LF
1/16W
402
R7998
1 2
NO STUFF
1/16W MF-LF
402
5%
0
R7988
1 2
69
67
MF-LF
PLACE_NEAR=U7850.2:6mm
402
20K
5% 1/16W
R7985
2
1
CERM 402
0.1UF
10V
20%
C7989
1
2
Power Control
SYNC_MASTER=K17_REF
SYNC_DATE=06/15/2009
VFRQ_EN_GATE
PM_SLP_S3_L
CHGR_VFRQ
CPUVTTS0_EN
MAKE_BASE=TRUE
P1V2S0_EN
MAKE_BASE=TRUE
MAKE_BASE=TRUE
PM_SLP_S3_L_R
PP3V42_G3H
PP3V3_S0
MAKE_BASE=TRUE
PM_SLP_S4_L
P5V3V3_PGOOD
P1V8S0_PGOOD
PM_SLP_S3_L_R
RSMRST_PWRGD
PM_SLP_S3_L_R
PM_ALL_GPU_PGOOD PM_ALL_GPU_PGOOD PM_ALL_GPU_PGOOD
PP3V3_ENET
EG_RAIL2_EN
MAKE_BASE=TRUE
PM_SLP_S4_L
PP3V42_G3H
PM_ALL_GPU_PGOOD
ALL_SYS_PWRGD
ALL_GFX_PGOOD_R
PP3V3_S5
PP3V3_S0
CK505_27MHZ_EN_L
PP3V3_S3
MAKE_BASE=TRUE
EG_RAIL3_EN
EG_RAIL3_EN
EG_RAIL2_EN
EG_RAIL1_EN
MAKE_BASE=TRUE
EG_RAIL1_EN
SMC_ADAPTER_EN
P3V3ENET_SS
WOL_EN
PM_ENET_EN
PM_WLAN_EN_L
EG_RAIL4_EN
EG_RAIL4_EN
MAKE_BASE=TRUE
AC_EN_L
P5VS3_EN
PM_SLP_S4_L
PP3V3_S0
S0PGOOD_PWROK
PP1V05_S0
PP1V5_S3RS0
PP3V3_S0
PM_SLP_S3_L_R
P1V2S0_EN
DDRREG_EN
MAKE_BASE=TRUE
DDRREG_EN
S5_PGOOD_CT
PP3V3_S5
SMC_PM_G2_EN
P1V8S0_EN
P3V3S5_EN
PP3V3_S0
P3V3S5_EN
MAKE_BASE=TRUE
MAKE_BASE=TRUE
PM_ALL_GPU_PGOOD
GFXIMVP_PGOOD
DDRREG_PGOOD
CPUVTTS0_EN
S0_PWR_PGOOD
S0PGOOD_PWROK
MAKE_BASE=TRUE
P5VS3_EN
AP_PWR_EN
P1V8S0_EN
MAKE_BASE=TRUE
PM_SLP_S3_L
PM_ENET_EN_L
79 OF 132
<E4LABEL>
<SCH_NUM>
<BRANCH>
73 OF 101
70 73
72 73
49 72 73
6 7
17 21 23 43 45 46 47 48
49 53 64 65 66 73
6 7
17 18 19 20 21 23 24 25
26 27 28 30 34 37 40 42 46 47
48 50 51 52 54 58 62 63 68
69 72 73 80 83 84 85 87 88
99
45
6 7
27 37
72 73 87
6 7
17 21
23 43 45
46 47 48 49
53 64 65
66 73
8
73 82 86 87
6 7
17 18 19 20 21 23 27 31
35 57 66 71 72 73 83
85 99
6 7
17 18 19 20 21 23 24 25
26 27 28 30 34 37 40 42 46 47
48 50 51 52 54 58 62 63 68 69
72 73 80 83 84 85 87 88 99
6 7 8
17 20 31 32 33 34 35 36
48 50 53 54 55 72 87
101
73 82 87 73 82 87
72 73 87
73 86 87 73 86 87
72 73 86 87 72 73 86 87
6 7
17 18 19 20 21 23 24 25
26 27 28 30 34 37 40 42 46 47
48 50 51 52 54 58 62 63 68 69
72 73 80 83 84 85 87 88 99
73
6 7
10 12 13 15 17 18 20 21
23 24 25 26 40 70 86
6 7
17 18 19 20 21 23 24 25
26 27 28 30 34 37 40 42 46 47
48 50 51 52 54 58 62 63 68 69
72 73 80 83 84 85 87 88 99
67 73
6 7
17 18 19 20 21 23 27 31
35 57 66 71 72 73 83 85 99
6 7
17 18 19 20 21 23 24 25
26 27 28 30 34 37 40 42 46 47
48 50 51 52 54 58 62 63 68 69
72 73 80 83 84 85 87 88 99
66 73
73
66 73
71 73
Page 74
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
PEX_RX2*
PEX_TX15*
PEX_TX15
PEX_TX14*
PEX_TX14
PEX_TX13*
PEX_TX13
PEX_TX12*
PEX_TX12
PEX_TX11*
PEX_TX10*
PEX_TX10
PEX_TX9*
PEX_TX9
PEX_TX8*
PEX_TX8
PEX_TX7*
PEX_TX7
PEX_TX6*
PEX_TX6
PEX_TX5*
PEX_TX4*
PEX_TX4
PEX_TX3*
PEX_TX3
PEX_TX2*
PEX_TX2
PEX_TX1*
PEX_TX1
PEX_TX0*
PEX_TX0
PEX_TSTCLK_OUT
PEX_SVDD_3V3
PEX_RX15*
PEX_RX15
PEX_RX14*
PEX_RX14
PEX_RX13*
PEX_RX13
PEX_RX12*
PEX_RX12
PEX_RX11*
PEX_RX11
PEX_RX10
PEX_RX9*
PEX_RX9
PEX_RX8*
PEX_RX8
PEX_RX7*
PEX_RX7
PEX_RX6*
PEX_RX6
PEX_RX5*
PEX_RX5
PEX_RX4*
PEX_RX4
PEX_RX2
PEX_RX0*
PEX_RX0
PEX_RST*
PEX_REFCLK*
PEX_REFCLK
PEX_CLKREQ*
PEX_TX5
PEX_RX3 PEX_RX3*
PEX_TX11
PEX_RX10*
PEX_RX1 PEX_RX1*
PEX_TERMP
PEX_TSTCLK_OUT*
(1 OF 9)
BUFRST*
VDD_SENSE
PEX_PLLVDD
PEX_IOVDDQ25
PEX_IOVDDQ24
PEX_IOVDDQ23
PEX_IOVDDQ22
PEX_IOVDDQ21
PEX_IOVDDQ20
PEX_IOVDDQ19
PEX_IOVDDQ18
PEX_IOVDDQ10
PEX_IOVDDQ9
PEX_IOVDDQ8
PEX_IOVDDQ7
PEX_IOVDDQ6
PEX_IOVDDQ5
PEX_IOVDDQ4
PEX_IOVDDQ3
PEX_IOVDDQ2
PEX_IOVDDQ1
PEX_IOVDD5
PEX_IOVDD4
PEX_IOVDD3
PEX_IOVDD2
VDD_SENSE
GND_SENSE
NC
PEX_IOVDD1
PEX_IOVDDQ17
PEX_IOVDDQ16
PEX_IOVDDQ15
PEX_IOVDDQ14
PEX_IOVDDQ13
PEX_IOVDDQ12
PEX_IOVDDQ11
GND_SENSE
(2 OF 9)
BI
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER
SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
Page Notes
Signal aliases required by this page:
BOM options provided by this page:
1500mA
- =PP1V2_GPU_PEX_IOVDDQ
250mA
- =PP1V2_GPU_PEX_IOVDD
120 mA: GT216 A01 DG v3 01/09
- =PP1V2_GPU_PEX_PLLXVDD
Power aliases required by this page:
PEX 1.1V Current = 2A
(NONE)
(NONE)
8
91
0.1uF
X5R 40210% 16V
C8081
1 2
0.1uF
X5R 40210% 16V
C8082
1 2
8 9
91
8
91
16V10%
0.1uF
X5R 402
C8079
1 2
0.1uF
X5R 40210% 16V
C8080
1 2
8 9
91
8
91
0.1uF
X5R 40210% 16V
C8077
1 2
0.1uF
X5R 40210% 16V
C8078
1 2
8 9
91
8
91
0.1uF
X5R 40210% 16V
C8075
1 2
0.1uF
X5R 40210% 16V
C8076
1 2
8 9
91
8
91
0.1uF
X5R 40210% 16V
C8073
1 2
0.1uF
X5R 40210% 16V
C8074
1 2
8 9
91
16V X5R
0.1uF
40210%
C8020
1 2
8
91
0.1uF
X5R 40210% 16V
C8071
1 2
0.1uF
X5R 40210% 16V
C8072
1 2
8 9
91
8
91
0.1uF
X5R 40210% 16V
C8069
1 2
0.1uF
X5R 40210% 16V
C8070
1 2
8 9
91
8
91
0.1uF
X5R 40210% 16V
C8067
1 2
10%
0.1uF
X5R 40216V
C8021
1 2
0.1uF
X5R 40210% 16V
C8068
1 2
8 9
91
8
91
0.1uF
X5R 40210% 16V
C8065
1 2
0.1uF
X5R 40210% 16V
C8066
1 2
8 9
91
8
91
0.1uF
X5R 40210% 16V
C8063
1 2
0.1uF
X5R 40210% 16V
C8064
1 2
8 9
91
X5R16V10% 402
0.1uF
C8050
1 2
8
91
0.1uF
X5R 40210% 16V
C8061
1 2
0.1uF
X5R 40210% 16V
C8062
1 2
8 9
91
8
91
0.1uF
X5R 40210% 16V
C8059
1 2
0.1uF
X5R 40210% 16V
C8060
1 2
8 9
91
8
91
0.1uF
X5R 40210% 16V
C8057
1 2
X5R 40210% 16V
0.1uF
C8051
1 2
0.1uF
X5R 40210% 16V
C8058
1 2
16V
0.1uF
X5R 40210%
C8048
1 2
0.1uF
X5R 40210% 16V
C8049
1 2
X5R 40216V
0.1uF
10%
C8046
1 2
4.7UF
CERM 603
20%
6.3V
C8001
1
2
1UF
CERM 402
10%
6.3V
C8003
1
2
0.1UF
CERM 402
20% 10V
C8004
1
2
10% 16V X5R
0.1uF
402
C8047
1 2
402
20%
0.1UF
10V CERM
C8005
1
2
CERM
20%
6.3V
4.7UF
603
C8016
1
2
CERM
603
6.3V
20%
4.7UF
C8015
1
2
22UF
805
20%
6.3V CERM-X5R
C8000
1
2
10% X5R16V 402
0.1uF
C8044
1 2
CERM 402
10%
6.3V
1UF
C8002
1
2
22UF
20%
6.3V 805
CERM-X5R
C8006
1
2
4.7UF
CERM 603
20%
6.3V
C8007
1
2
1UF
402
10%
6.3V CERM
C8008
1
2
CERM 402
10%
6.3V
1UF
C8009
1
2
0.1UF
CERM 402
10V
20%
C8010
1
2
0.1UF
402
CERM
10V
20%
C8011
1
2
X5R16V 40210%
0.1uF
C8045
1 2
100NH-700MA-0.14OHM
0603
L8015
1 2
402X5R10% 16V
0.1uF
C8042
1 2
2.49K
MF-LF
402
1%
1/16W
R8050
1 2
NO STUFF
200
MF-LF
402
1%
1/16W
R8060
1 2
5%
402
MF-LF
0
1/16W
R8020
1 2
X5R10% 16V
0.1uF
402
C8043
1 2
16V
0.1uF
10% X5R 402
C8040
1 2
0.1uF
X5R10% 16V 402
C8041
1 2
0.1uF
X5R 40210% 16V
C8038
1 2
0.1uF
X5R 40210% 16V
C8039
1 2
0.1uF
X5R 40210% 16V
C8036
1 2
0.1uF
X5R 40210% 16V
C8037
1 2
0.1uF
16V X5R 40210%
C8034
1 2
0.1uF
16V10% 402X5R
C8035
1 2
6
OMIT
NV-GT216
BGA
U8000
AR13
AR16 AR17
AM16
AP17 AN17
AN19 AP19
AN28 AP28
AR28 AR29
AP29 AN29
AN31 AP31
AR31 AR32
AR34 AP34
AR19 AR20
AP20 AN20
AN22 AP22
AR22 AR23
AP23 AN23
AN25 AP25
AR25 AR26
AP26 AN26
AG19 F7
AG21
AJ17 AJ18
AL17 AM17
AM18 AM19
AM27 AM28
AL28 AK28
AK29 AL29
AM29 AM30
AM31 AM32
AN32 AP32
AL19 AK19
AL20 AM20
AM21 AM22
AL22 AK22
AL23 AM23
AM24 AM25
AL25 AK25
AL26 AM26
40216V
0.1uF
X5R10%
C8032
1 2
OMIT
NV-GT216
BGA
U8000
A4
AD19
E35
R7
H32
AD6 AF6 AG6 AJ5
AK15
AL7
E7
M7
A2 A7 B7 C5 C7 D5 D6 D7 E5 F4
P6
G5
J18
A5
J19 J25 J26 AA4 AB4 AC5
Y4
AG20
U7 V6
AB7
AK16 AK17 AK21 AK24 AK27
AG11
AG24 AG25 AG26 AJ14 AJ15 AJ19 AJ21 AJ22 AJ24 AJ25
AG12
AJ27 AK18 AK20 AK23 AK26 AL16
AG13 AG15 AG16 AG17 AG18 AG22 AG23
AG14
AD20
D35
P7
0.1UF
16V X5R 402
10%
C8012
1
2
0
MF-LF
5%
402
1/16W
NO STUFF
R8012
1 2
0
MF-LF
5%
1/16W
402
R8013
1 2
1/16W MF-LF
5%
402
10K
R8021
1 2
603
4.7UF
6.3V
10% X5R-CERM
C8013
1
2
10% CERM
402
6.3V
1UF
C8017
1
2
0.1uF
X5R 40210% 16V
C8033
1 2
8
87
603
6.3V X5R
10UF
20%
C8018
1
2
X5R 402
0.1uF
10% 16V
C8030
1 2
402
0.1uF
X5R10% 16V
C8031
1 2
X5R
0.1uF
40210%16V
C8028
1 2
X5R 402
0.1uF
10% 16V
C8029
1 2
16V
0.1uF
X5R 40210%
C8026
1 2
16V
0.1uF
X5R 40210%
C8027
1 2
0.1uF
X5R 40210% 16V
C8024
1 2
0.1uF
X5R 40210% 16V
C8025
1 2
0.1uF
X5R 40210% 16V
C8022
1 2
10%
0.1uF
X5R 40216V
C8023
1 2
8 9
91
8
91
8
91
8 9
91
8
91
8 9
91
8
91
8 9
91
8
91
8 9
91
8
91
8 9
91
8
91
8 9
91
8
91
8 9
91
8
91
8 9
91
8
91
8 9
91
8
91
8 9
91
8
91
8 9
91
8
91
8 9
91
8
91
8 9
91
8
91
8 9
91
8
91
8 9
91
17 94
17 94
8
87
0.1uF
X5R 40210% 16V
C8055
1 2
0.1uF
X5R 40210% 16V
C8056
1 2
8 9
91
8
91
8 9
91
8
91
0.1uF
X5R 40210% 16V
C8085
1 2
0.1uF
X5R10% 16V 402
C8086
1 2
8 9
91
8
91
0.1uF
X5R 40210% 16V
C8083
1 2
0.1uF
X5R 40210% 16V
C8084
1 2
8 9
91
SYNC_DATE=06/15/2009
SYNC_MASTER=K17_REF
NV GT216 PCI-E
PP1V05_S0GPU
MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=1.1V
PP1V1_GPU_PEX_PLLVDD_F
PEG_CLK100M_P
PEG_R2D_C_N<13>
PEG_R2D_C_P<14>
PEG_R2D_C_P<15>
PEG_CLK100M_N
GPU_RESET_R_L
PP3V3_S0GPU
PEG_R2D_C_N<12>
PEG_R2D_C_P<13>
EG_RESET_L
GPU_VDD_SENSE GPU_GND_SENSE
NC_GPU_BUFRST_L
PEG_R2D_N<12>
PEG_R2D_N<10>
PEG_R2D_N<9>
PEG_R2D_N<8>
PEG_R2D_N<1>
PEG_D2R_C_N<9>
PEG_D2R_C_P<10>
PEG_D2R_C_P<9>
PEG_D2R_C_N<10>
PEG_D2R_C_N<11>
PEG_D2R_C_N<12>
PEG_D2R_C_P<11>
PEG_R2D_P<7> PEG_R2D_N<7>
PEG_R2D_P<8>
PEG_R2D_C_N<11>
PP1V05_S0GPU
PEG_D2R_N<15>
PEG_R2D_C_N<10>
PEG_R2D_C_P<11>
PEG_R2D_N<15>
PEG_R2D_N<14>
PEG_R2D_C_P<6>
PEG_R2D_P<11>
PEG_R2D_C_N<15>
PEG_R2D_C_P<5>
PEX_TERMP_PD
PEX_TSTCLK_N
PEG_R2D_C_P<7>
PEG_R2D_C_P<12>
PEG_R2D_P<9>
NC_GPU_DFM
NO_TEST=TRUE
PEG_R2D_C_N<3>
PEG_R2D_P<0>
PEG_D2R_C_P<15>
PEG_R2D_C_P<4>
PEG_R2D_C_P<3>
PEG_R2D_C_N<4>
PEG_R2D_C_N<2>
PEG_D2R_N<0>
PEG_D2R_N<1>
PEG_D2R_P<1>
PEG_D2R_N<2>
PEG_D2R_P<2>
PEG_D2R_N<3>
PEG_D2R_P<3>
PEG_D2R_N<4>
PEG_D2R_P<4>
PEG_D2R_P<5>
PEG_D2R_N<5>
PEG_D2R_P<9>
PEG_D2R_N<6>
PEG_D2R_P<6>
PEG_D2R_P<7>
PEG_D2R_N<7>
PEG_D2R_N<9>
PEG_D2R_N<14>
PEG_D2R_P<13>
PEG_D2R_N<12>
PEG_D2R_N<10>
PEG_D2R_N<11>
PEG_D2R_P<11>
PEG_D2R_P<14>
PEG_D2R_N<13>
PEG_D2R_P<15>
PEG_R2D_C_N<5>
PEG_R2D_C_N<1>
PEG_D2R_P<10>
PEG_D2R_P<8>
PEG_D2R_N<8>
PEG_R2D_P<3>
PEG_D2R_C_P<5>
PEG_R2D_N<0>
PEG_R2D_P<4> PEG_R2D_N<4>
PEX_TSTCLK_P
PEG_D2R_C_P<0>
PEG_D2R_C_P<1> PEG_D2R_C_N<1>
PEG_D2R_C_P<2> PEG_D2R_C_N<2>
PEG_D2R_C_P<3> PEG_D2R_C_N<3>
PEG_D2R_C_P<4> PEG_D2R_C_N<4>
PEG_D2R_C_N<5>
PEG_D2R_C_P<6> PEG_D2R_C_N<6>
PEG_D2R_C_P<7>
PEG_D2R_C_P<8> PEG_D2R_C_N<8>
PEG_D2R_C_P<12>
PEG_D2R_C_P<13>
PEG_D2R_C_N<14>
PEG_D2R_C_N<15>
PEG_R2D_N<2>
PEG_R2D_P<1>
PEG_R2D_C_N<6>
PEG_R2D_C_P<8>
PEG_D2R_C_N<7>
PEG_R2D_P<10>
PEG_R2D_P<14>
PEG_R2D_C_P<10>
PP3V3R1V1_GPU_PEX_SVDD
MIN_LINE_WIDTH=0.30MM
VOLTAGE=3.3V
MIN_NECK_WIDTH=0.20MM
PEG_D2R_C_P<14>
PEG_D2R_C_N<13>
PEG_D2R_P<12>
PEG_R2D_C_N<8>
PEG_R2D_C_P<9>
PEG_R2D_C_N<7>
PEG_R2D_N<6>
PEG_R2D_P<6>
PEG_R2D_N<5>
PEG_R2D_P<5>
PEG_R2D_C_N<0>
PEG_R2D_C_P<0>
PEG_R2D_N<3>
PEG_R2D_P<2>
PEG_D2R_C_N<0>
PEG_D2R_P<0>
PEG_R2D_C_P<1>
PEG_R2D_C_P<2>
PEG_R2D_N<11>
PEG_R2D_P<12>
PEG_R2D_P<13>
PEG_R2D_C_N<9>
PP1V05_S0GPU
PEX_CLKREQ_L
PEG_R2D_P<15>
PEG_R2D_N<13>
PEG_R2D_C_N<14>
PP1V05_S0GPU
80 OF 132
<E4LABEL>
<SCH_NUM>
<BRANCH>
74 OF 101
6 7
74 76 79 81 86
6 7
72 79 80 81 82 84
82
82
91
91
91
91
91
91
91
91
91
91
91
91
91
91
91
6 7
74 76 79 81 86
91
91
91
91
91
91
91
91
91
91
91
91
91
91
91
91
91
91
91
91
91
91
91
91
91
91
91
91
91
91
91
91
91
91
91 91
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74 76 79 81 86
Page 75
VDD VDD
(9 OF 9)
FBVDDQ FBVDDQ
(7 OF 9)
GNDGND
(8 OF 9)
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER
SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
Nvidia PRD for GB-128 uses 4x4.7uF, 8x0.47uF, 16x0.1uF
???A @ ???/???MHz Core/Mem Clk for VDD
(NONE)
(NONE)
???A @ ???MHz 1.8V GDDR3
Power aliases required by this page:
Page Notes
Signal aliases required by this page:
- =PPVCORE_GPU
BOM options provided by this page:
- =PP1V8_GPU_FBVDDQ
402
0.22UF
6.3V CERM-X5R
10%
C8101
1
2
402
10V X5R
1UF
10%
C8100
1
2
402
CERM-X5R
6.3V
0.22UF
10%
C8102
1
2
402
16V CERM-X5R
0.022UF
10%
C8107
1
2
402
25V X7R
0.01UF
10%
C8112
1
2
402
25V X7R
0.01UF
10%
C8117
1
2
402
16V X7R
0.047UF
10%
C8106
1
2
402
16V X7R
0.047UF
10%
C8105
1
2
402
16V X7R
0.015UF
10%
C8110
1
2
402
16V X7R
0.015UF
10%
C8111
1
2
10%
0.01UF
X7R
25V 402
C8116
1
2
402
25V X7R
0.01UF
10%
C8115
1
2
10%
0.047UF
X7R
16V 402
C8104
1
2
402
16V CERM-X5R
0.022UF
10%
C8109
1
2
402
0.01UF
25V X7R
10%
C8114
1
2
402
0.01UF
25V X7R
10%
C8113
1
2
402
16V CERM-X5R
0.022UF
10%
C8108
1
2
402
16V X7R-CERM
0.1UF
10%
C8103
1
2
10V
20%
CERM
0.1UF
402
C8159
1
2
10V
20%
402
CERM
0.1UF
C8158
1
2
4.7UF
CERM
603
6.3V
20%
C8150
1
2
10V
20%
402
CERM
0.1UF
C8157
1
2
402
25V CERM
0.0047UF
10%
C8119
1
2
402
25V CERM
0.0068UF
10%
C8118
1
2
OMIT
NV-GT216
BGA
U8000
L11
L20
AC20 AC21 AC22 AC23 AC24 AC25 AD12 AD14 AD16 AD18
L21
AD22 W20
L22 L23 L24 L25 M12 M14 M16 M18
L12
M20 M22 M24 P11 P13 P15 P17 P19 P21 P23
L13
P25 R11 R12 R13 R14 R15 R16 R17 R18 R19
L14
R20 R21 R22 R23 R24 R25 T12 T14 T16 T18
L15
T20 T22 T24 V11 V13 V15 V17
V19 V21 V23
L16
V25 W11 W12 W13 W14 W15 W16 W17 W18 W19
L17
AD24 W21 W22 W23 W24 W25 Y12 Y14 Y16 Y18
L18
Y20 Y22 Y24 AB11 AB13 AB15 AB17 AB19 AB21 AB23
L19
AB25 AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19
BGA
NV-GT216
OMIT
U8000
B18
E21
G8
G9 G17 G18 G22 H29 J14 J15 J16
J17
J20 J21 J22 J23 J24 J29 N27 P27 R27 T27
U27
U29 V27 V29 V34 W27 Y27 AA27 AA29 AA31
AB27 AB29 AC27 AD27 AE27 AJ28
BGA
NV-GT216
OMIT
U8000
B3
B33
V24 V31 Y11 Y13 Y15 Y17 Y19 Y21 Y23 Y25
C2
AA2 AA5 AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18
C34
AA19 AA20 AA21 AA22 AA23 AA24 AA25 AA34 AB12 AB14
E6
AB16 AB18 AB20 AB22 AB24 AC9 AD2 AD5 AD11 AD13
E9
AD15 AD17 AD21 AD23 AD25 AD31 AD34 AE11 AE12 AE13
E12
AE14 AE15 AE16 AE17 AE18 AE19 AE20 AE21 AE22 AE23
E15
AE24 AE25 AG2 AG5 AG31 AG34 AK2 AK5 AP33 AK31
E18
AK34 AL6 AL9 AL12 AL15 AL18 AL21 AL24 AL27 AL30
E24
AN2 AN34 AP3 AP6 AP9 AP12 AP15 AP18 AP21 AP24
E27
AP27 AP30 K9 AK14
B6
E30
F2
F5 F31 F34
J2
J5 J31 J34
L9
B9
M2
M5 M11 M13 M15 M17 M19 M21 M23 M25
B12
M31 M34 N11 N12 N13 N14 N15 N16 N17 N18
B15
N19 N20 N21 N22 N23 N24 N25 P12 P14 P16
B21
P18 P20 P22 P24
R2
R5 R31 R34 T11 T13
B24
T15 T17 T19 T21 T23 T25 U11 U12 U13 U14
B27
U15 U16 U17 U18 U19 U20 U21 U22 U23 U24
B30
U25
V2
V5
V9 V12 V14 V16
V18 V20 V22
20%
6.3V CERM
4.7UF
603
C8156
1
2
16V X7R
10%
402
0.047UF
C8160
1
2
16V X7R
10%
402
0.047UF
C8162
1
2
16V X7R
0.047UF
10%
402
C8163
1
2
25V X7R
0.01UF
10%
402
C8164
1
2
25V X7R
0.01UF
10%
402
C8165
1
2
25V X7R
0.01UF
10%
402
C8166
1
2
SYNC_DATE=06/15/2009
SYNC_MASTER=K17_REF
NV GT216 CORE/FB POWER
PP1V8R1V55_S0GPU_ISNS
PPVCORE_GPU
81 OF 132
<E4LABEL>
<SCH_NUM>
<BRANCH>
75 OF 101
6 7 8
50 56 76 77 78
6 7 49
82
Page 76
BI
BI BI BI
BI BI
BI
BI
BI
BI
BI
BI
BI BI BI
BI
BI
BI BI
BI BI
BI
BI
BI BI
BI BI BI
BI
BI
BI BI
BI
BI BI BI
BI
BI
BI
BI
BI
BI BI
BI
BI
BI
BI
BI
BI
BI
BI
BI BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI BI
OUT
OUT
OUT
OUT OUT
OUT
OUT
OUT
OUT OUT
OUT
OUT
OUT OUT
BI BI
BI
BI
BI
BI BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI BI
BI
BI
BI
BI BI
BI
BI BI
BI
BI
BI
BI
BI
BI BI
OUT
OUT
OUT
OUT
OUT
OUT
OUT OUT
OUT OUT
OUT
OUT OUT OUT OUT OUT OUT OUT
OUT OUT OUT OUT OUT
OUT
OUT OUT OUT
OUT OUT OUT OUT OUT OUT OUT OUT
OUT
OUT
OUT
OUT
OUT
BI
BI
BI
BI
BI
BI
BI BI
IN
IN
IN
IN
IN
IN
IN
IN
OUT OUT OUT
OUT
OUT
OUT OUT
OUT
OUT
OUT
OUT
BI
BI
BI BI
BI
BI
BI
BI
IN
IN
IN
IN
IN
IN
IN IN
OUT
OUT
OUT OUT
OUT
OUT
OUT OUT
OUT
OUT
OUT
OUT
OUT
OUT
NC
NC
NC
NC
NC
NC
NC
NC
NC NC NC NC NC NC NC
NC
OUT
(3 OF 9)
FBA_DQM3 FBA_DQM4
FBA_CLK1*
FBA_DQM0
FBA_CMD1 FBA_CMD2 FBA_CMD3
FBA_CLK0
FBA_CLK0*
FBA_CLK1
FBA_CMD4 FBA_CMD5 FBA_CMD6 FBA_CMD7 FBA_CMD8
FBA_CMD9 FBA_CMD10 FBA_CMD11 FBA_CMD12 FBA_CMD13 FBA_CMD14 FBA_CMD15 FBA_CMD16 FBA_CMD17 FBA_CMD18 FBA_CMD19 FBA_CMD20 FBA_CMD21 FBA_CMD22 FBA_CMD23 FBA_CMD24 FBA_CMD25 FBA_CMD26 FBA_CMD27 FBA_CMD28 FBA_CMD29 FBA_CMD30
FBA_D00 FBA_D01 FBA_D02 FBA_D03 FBA_D04 FBA_D05 FBA_D06 FBA_D07 FBA_D08 FBA_D09 FBA_D10 FBA_D11 FBA_D12 FBA_D13 FBA_D14 FBA_D15 FBA_D16 FBA_D17 FBA_D18 FBA_D19 FBA_D20 FBA_D21 FBA_D22 FBA_D23 FBA_D24 FBA_D25 FBA_D26 FBA_D27 FBA_D28 FBA_D29 FBA_D30 FBA_D31 FBA_D32 FBA_D33 FBA_D34 FBA_D35 FBA_D36 FBA_D37 FBA_D38 FBA_D39 FBA_D40 FBA_D41 FBA_D42 FBA_D43 FBA_D44 FBA_D45 FBA_D46 FBA_D47 FBA_D48 FBA_D49 FBA_D50 FBA_D51 FBA_D52 FBA_D53 FBA_D54 FBA_D55 FBA_D56 FBA_D57 FBA_D58 FBA_D59 FBA_D60 FBA_D61 FBA_D62 FBA_D63
FBA_DEBUG
FBA_DQM1
FBA_DQM2
FBA_DQM5
FBA_DQM6
FBA_DQM7
FBA_DQS_RN0 FBA_DQS_RN1 FBA_DQS_RN2 FBA_DQS_RN3 FBA_DQS_RN4 FBA_DQS_RN5 FBA_DQS_RN6 FBA_DQS_RN7
FBA_DQS_WP0 FBA_DQS_WP1 FBA_DQS_WP2 FBA_DQS_WP3 FBA_DQS_WP4 FBA_DQS_WP5 FBA_DQS_WP6 FBA_DQS_WP7
FB_CAL_PD_VDDQ
FB_CAL_PU_GND
FB_CAL_TERM_GND
FB_DLLAVDD FB_PLLAVDD
NC
FBA_CMD0
FBC_DQM1
FBC_CLK0
FBC_CLK0*
FBC_CLK1
FBC_CLK1*
FBC_CMD0 FBC_CMD1 FBC_CMD2 FBC_CMD3 FBC_CMD4 FBC_CMD5 FBC_CMD6 FBC_CMD7 FBC_CMD8
FBC_CMD9 FBC_CMD10 FBC_CMD11 FBC_CMD12 FBC_CMD13 FBC_CMD14 FBC_CMD15 FBC_CMD16 FBC_CMD17 FBC_CMD18 FBC_CMD19 FBC_CMD20 FBC_CMD21 FBC_CMD22 FBC_CMD23 FBC_CMD24 FBC_CMD25 FBC_CMD26 FBC_CMD27 FBC_CMD28 FBC_CMD29 FBC_CMD30
FBC_D00 FBC_D01 FBC_D02 FBC_D03 FBC_D04 FBC_D05 FBC_D06 FBC_D07 FBC_D08 FBC_D09 FBC_D10 FBC_D11 FBC_D12 FBC_D13 FBC_D14 FBC_D15 FBC_D16 FBC_D17 FBC_D18 FBC_D19 FBC_D20 FBC_D21 FBC_D22 FBC_D23 FBC_D24 FBC_D25 FBC_D26 FBC_D27 FBC_D28 FBC_D29 FBC_D30 FBC_D31 FBC_D32 FBC_D33 FBC_D34 FBC_D35 FBC_D36 FBC_D37 FBC_D38 FBC_D39 FBC_D40 FBC_D41 FBC_D42 FBC_D43 FBC_D44 FBC_D45 FBC_D46 FBC_D47 FBC_D48 FBC_D49 FBC_D50 FBC_D51 FBC_D52 FBC_D53 FBC_D54 FBC_D55 FBC_D56 FBC_D57 FBC_D58 FBC_D59 FBC_D60 FBC_D61 FBC_D62 FBC_D63
FBC_DEBUG
FBC_DQM0
FBC_DQM2
FBC_DQM3
FBC_DQM4
FBC_DQM5
FBC_DQM6
FBC_DQM7
FBC_DQS_RN0 FBC_DQS_RN1 FBC_DQS_RN2 FBC_DQS_RN3 FBC_DQS_RN4 FBC_DQS_RN5 FBC_DQS_RN6 FBC_DQS_RN7
FBC_DQS_WP0 FBC_DQS_WP1 FBC_DQS_WP2 FBC_DQS_WP3 FBC_DQS_WP4 FBC_DQS_WP5 FBC_DQS_WP6 FBC_DQS_WP7
FB_VREF
NC
(4 OF 9)
OUT
OUT
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER
SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
Page Notes
Signal aliases required by this page:
Power aliases required by this page:
- =PP1V8_GPU_FBIO
(NONE)
(NONE)
BOM options provided by this page:
- =PP1V2_GPU_FBPLLAVDD
77 98
77 98
77 98
77 98
77 98
77 98
77 98
77 98
77 98
77 98
77 98
77 98
77 98
77 98
77 98
77 98
77 98
77 98
77 98
77 98
77 98
77 98
77 98
77 98
77 98
77 98
77 98
77 98
77 98
77 98
77 98
77 98
77 98
77 98
77 98
77 98
77 98
77 98
77 98
77 98
77 98
77 98
77 98
77 98
77 98
77 98
77 98
77 98
77 98
77 98
77 98
77 98
77 98
77 98
77 98
77 98
77 98
77 98
77 98
77 98
77 98
77 98
77 98
77 98
77 98
77 98
77 98
77 98
77 98
77 98
77 98
77 98
77 98
77 98
77 98
77 98
77 98
77 98
78 98
78 98
78 98
78 98
78 98
78 98
78 98
78 98
78 98
78 98
78 98
78 98
78 98
78 98
78 98
78 98
78 98
78 98
78 98
78 98
78 98
78 98
78 98
78 98
78 98
78 98
78 98
78 98
78 98
78 98
78 98
78 98
78 98
78 98
78 98
78 98
78 98
78 98
78 98
78 98
78 98
78 98
78 98
78 98
78 98
78 98
78 98
78 98
78 98
78 98
78 98
78 98
78 98
78 98
78 98
78 98
78 98
78 98
78 98
78 98
78 98
78 98
78 98
78 98
77
77 98
77 98
77 98
77 98
77 98
77 98
77 98
77 98
77 98
77 98
78 98
78 98
78 98
78 98
78 98
78 98
78 98
78 98
78
78 98
78 98
78 98
78 98
78 98
78 98
78 98
78 98
78 98
78 98
78 98
78 98
78 98
78 98
78 98
1/16W
5%
402
MF-LF
10K
R8200
1
2
78 98
1/16W
5%
402
MF-LF
10K
R8250
1
2
PLACE_NEAR=U8000.L27:3mm
402
1/16W MF-LF
1%
31.6
R8291
1
2
1/16W
1%
402
MF-LF
1.07K
R8295
1
2
PLACE_NEAR=U8000.K27:3mm
1% 1/16W MF-LF
402
56.2
R8290
1
2
4.7UF
X5R-CERM 603
10%
6.3V
C8200
1
2
1/16W
5%
402
MF-LF
10K
R8201
1
2
1/16W
5%
402
MF-LF
10K
R8251
1
2
77 98
77 98
77 98
77 98
77 98
77 98
77 98
77 98
77 98
77 98
77 98
77 98
77 98
77 98
77 98
77 98
77 98
77 98
77 98
77 98
77 98
77 98
77 98
77 98
77 98
77 98
77 98
78 98
78 98
78 98
78 98
78 98
78 98
78 98
78 98
78 98
78 98
78 98
78 98
78 98
78 98
78 98
78 98
78 98
78 98
78 98
78 98
78 98
78 98
78 98
78 98
78 98
78 98
78 98
78 98
1/16W
1%
402
MF-LF
2.49K
R8296
1
2
77 98
78 98
77 98
80
78 98
80
PLACE_NEAR=U8000.M27:3mm
1/16W
1%
402
MF-LF
40.2
R8292
1
2
77 98
OMIT
BGA
NV-GT216
U8000
K27 L27 M27
AG27 AF27
T32 T31 AC31 AC30
V32 W31
T35 AB31 Y30 Y34 W32 AA30 AA32 Y33 U32 Y31
U31
U34 Y35 W34 V30 U35 U30 U33 AB30 AB33 T33
Y32
W29
AB35 AB34 W35 W33 W30 T34
L32 N33 L33 N34 N35 P35 P33 P34 K35 K33 K34 H33 G34 G33 E34 E33 G31 F30 G30 G32 K30 K32 H30 K31 L31 L30 M32 N30 M30 P31 R32
R30 AG30 AG32 AH31 AF31 AF30 AE30 AC32 AD30 AN33 AL31 AM33 AL33 AK30 AK32 AJ30 AH30 AH33 AH35 AH34 AH32 AJ33 AL35 AM34 AM35 AF33 AE32 AF34 AE35 AE34 AE33 AB32 AC35
T30
P32 H34 J30 P30 AF32 AL32 AL34 AF35
L35 G35 H31 N32 AD32 AJ31 AJ35 AC34
L34 H35 J32 N31 AE31 AJ32 AJ34 AC33
L29
M29
P29
R29
AD29 AE29 AG29 AH29
BGA
NV-GT216
OMIT
U8000
J27
E17 D17 D23 E23
C17 B19
F19 F23 A22 C22 B17 F24 C25 E22 C20 B22
D18
A19 D22 D20 E19 D19 F18 C19 F22 C23 B20
F21
A20
A23 D21 B23 E20 G21 F20
B13 D13 A13 A14 C16 B16 A17 D16 C13 B11 C11 A11 C10
C8 B8 A8 E8 F8
F10
F9
F12
D8 D11 E11 D12 E13 F13 F14 F15 E16 F16 F17 D29 F27 F28 E28 D26 F25 D24 E25 E32 F32 D33 E31 C33 F29 D30 E29 B29 C31 C29 B31 C32 B32 B35 B34 A29 B28 A28 C28 C26 D25 B25 A25
G19
A16 D10 F11 D15 D27 D34 A34 D28
B14 B10 D9 E14 F26 D31 A31 A26
C14 A10 E10 D14 E26 D32 A32 B26
G11 G12 G14 G15 G24 G25 G27 G28
1/16W
5%
402
MF-LF
10K
R8203
1
2
1/16W
5%
402
MF-LF
10K
R8252
1
2
77 98
78 98
603
4.7UF
10%
6.3V X5R-CERM
C8201
1
2
6.3V
10% CERM
1UF
402
C8202
1
2
0603-1
CRITICAL
300-OHM-0.5A
L8200
1 2
NV GT216 FRAME BUFFER I/F
SYNC_DATE=06/15/2009
SYNC_MASTER=K17_REF
FB_A_MA<6>
FB_A_DQM_L<3>
PP1V05_S0GPU
MIN_NECK_WIDTH=0.2 MM
PP1V1_GPU_FBPLLAVDD_F
MIN_LINE_WIDTH=0.2 MM VOLTAGE=1.1V
FB_B_DQ<5>
FB_B_DQ<26>
FB_B_DQ<31>
FB_B_DQ<48>
FB_A_DQ<53>
FB_A_UMA<5>
FB_A_BA<0>
FB_A_WE_L
FB_A_LCAS_L
FB_A_DRAM_RST
FB_A_MA<11>
FB_B_DQ<32>
FB_A_MA<1>
FB_A_DQ<48>
FBCAL_PU_GND
FB_A_DQ<63>
FB_B_DQ<37>
FB_B_DQ<0>
FB_B_DQ<2> FB_B_DQ<3>
FB_A_UCKE
FB_B_DQ<17>
FB_B_DQ<20>
FB_A_DQM_L<1>
NC_FB_A_LCS1_L
FB_A_LCS0_L
NC_FB_A_UCS1_L
FB_A_LMA<3>
FB_A_LCKE
FB_A_UMA<4>
FB_A_UCS0_L
FB_A_LMA<4> FB_A_RAS_L FB_A_LMA<5>
FB_A_UMA<2>
FB_A_DQ<38>
FB_A_DQ<36>
FB_A_DQ<33>
FB_A_DQ<31>
FB_A_DQ<27>
FB_A_DQ<23>
FB_A_DQ<20>
FB_A_DQ<19>
FB_A_DQ<16>
FB_A_DQ<12>
FB_A_DQ<6>
FB_A_DQ<5>
FB_A_DQ<4>
FB_A_DQ<3>
FB_A_DQ<2>
FB_A_DQ<0> FB_A_DQ<1>
FB_A_DQ<32>
FB_A_DQM_L<5>
FB_B_RDQS<6>
FB_B_LMA<3>
FB_B_MA<12>
FB_B_BA<1>
FB_B_LMA<4>
FB_B_DQM_L<1>
FB_B_CLK_P<0> FB_B_CLK_N<0> FB_B_CLK_P<1> FB_B_CLK_N<1>
FB_B_RAS_L FB_B_LMA<5>
FB_B_UMA<4>
FB_B_UCS0_L FB_B_MA<11>
FB_B_UMA<5>
FB_B_MA<7> FB_B_MA<10>
FB_B_MA<0> FB_B_MA<9> FB_B_MA<6> FB_B_LMA<2> FB_B_MA<8>
NC_FBB_MA<13>
NC_FB_B_LCS1_L
FB_B_DQ<1>
FB_B_DQ<4>
FB_B_DQ<6> FB_B_DQ<7> FB_B_DQ<8> FB_B_DQ<9> FB_B_DQ<10> FB_B_DQ<11> FB_B_DQ<12> FB_B_DQ<13> FB_B_DQ<14>
FB_B_DQ<18> FB_B_DQ<19>
FB_B_DQ<22> FB_B_DQ<23> FB_B_DQ<24> FB_B_DQ<25>
FB_B_DQ<27> FB_B_DQ<28> FB_B_DQ<29> FB_B_DQ<30>
FB_B_DQ<33> FB_B_DQ<34> FB_B_DQ<35> FB_B_DQ<36>
FB_B_DQ<38> FB_B_DQ<39> FB_B_DQ<40> FB_B_DQ<41> FB_B_DQ<42> FB_B_DQ<43>
FB_B_DQ<47>
FB_B_DQ<49> FB_B_DQ<50> FB_B_DQ<51>
FB_B_DQ<54>
FB_B_DQ<56>
FB_B_DQM_L<0>
FB_B_DQM_L<2> FB_B_DQM_L<3> FB_B_DQM_L<4> FB_B_DQM_L<5> FB_B_DQM_L<6> FB_B_DQM_L<7>
FB_B_RDQS<0>
FB_B_RDQS<2> FB_B_RDQS<3> FB_B_RDQS<4> FB_B_RDQS<5>
FB_B_WDQS<0> FB_B_WDQS<1> FB_B_WDQS<2> FB_B_WDQS<3> FB_B_WDQS<4> FB_B_WDQS<5>
FB_B_WDQS<7>
FB_A_DQM_L<4>
FB_A_CLK_N<1>
FB_A_BA<1>
FB_A_CLK_P<1>
FB_A_UMA<3>
FB_A_MA<7>
NC_FBA_MA<13> FB_A_BA<2>
FB_A_DQ<8> FB_A_DQ<9>
FB_A_DQ<14> FB_A_DQ<15>
FB_A_DQ<18>
FB_A_DQ<21> FB_A_DQ<22>
FB_A_DQ<25> FB_A_DQ<26>
FB_A_DQ<28> FB_A_DQ<29> FB_A_DQ<30>
FB_A_DQ<34> FB_A_DQ<35>
FB_A_DQ<37>
FB_A_DQ<39> FB_A_DQ<40> FB_A_DQ<41> FB_A_DQ<42> FB_A_DQ<43> FB_A_DQ<44> FB_A_DQ<45> FB_A_DQ<46> FB_A_DQ<47>
FB_A_DQ<49> FB_A_DQ<50> FB_A_DQ<51> FB_A_DQ<52>
FB_A_DQ<54> FB_A_DQ<55> FB_A_DQ<56> FB_A_DQ<57> FB_A_DQ<58> FB_A_DQ<59> FB_A_DQ<60> FB_A_DQ<61> FB_A_DQ<62>
FB_A_DQM_L<7>
FB_A_WDQS<2> FB_A_WDQS<3> FB_A_WDQS<4> FB_A_WDQS<5>
FB_A_WDQS<7>
FB_A_MA<12>
FB_B_DQ<45>
FB_B_DQ<44>
FB_A_DQM_L<2>
FB_A_DQM_L<6>
FB_A_RDQS<0>
FB_A_RDQS<2> FB_A_RDQS<3> FB_A_RDQS<4>
FB_B_DQ<46>
FB_A_WDQS<6>
FB_A_RDQS<6>
FB_B_DQ<21>
FB_B_BA<0>
FB_B_DRAM_RST
FB_B_UMA<2>
FB_B_UCKE
FB_B_UMA<3>
FB_A_CLK_N<0>
FB_A_MA<8>
FB_B_DQ<15> FB_B_DQ<16>
FB_A_UCAS_L
FB_A_RDQS<1>
FB_A_CLK_P<0>
FB_A_LMA<2>
FB_A_MA<0> FB_A_MA<9>
PP1V8R1V55_S0GPU_ISNS
FB_B_RDQS<7>
FB_B_RDQS<1>
FB_B_LCS0_L
NC_FB_B_UCS1_L
FB_B_BA<2>
FB_B_MA<1>
FB_B_LCKE
FB_B_WE_L
FB_B_LCAS_L
FB_B_UCAS_L
FB_B_WDQS<6>
FB_B_DQ<58>
FB_A_MA<10>
FB_A_DQ<13>
FB_A_DQM_L<0>
FB_A_WDQS<1>
FB_B_DQ<53>
FB_B_DQ<55>
FB_B_DQ<57>
FB_B_DQ<59> FB_B_DQ<60> FB_B_DQ<61> FB_B_DQ<62> FB_B_DQ<63>
FB_A_WDQS<0>
FB_A_RDQS<5>
FB_A_DQ<17>
FB_A_DQ<24>
FBCAL_TERM_GND
FB_A_DQ<10> FB_A_DQ<11>
FB_A_DQ<7>
FBCAL_PD_VDDQ
PP1V8R1V55_S0GPU_ISNS
FB_B_DQ<52>
GPU_FB_VREF
FB_A_RDQS<7>
82 OF 132
<E4LABEL>
<SCH_NUM>
<BRANCH>
76 OF 101
6 7
74 79 81 86
80
77 98
80
80
6 7 8
50
56 75 76 77 78
78 98
80
6 7 8
50 56 75 76 77 78
Page 77
IN
IN
IN
IN
BI
BI BI
BI
BI
BI
BI BI BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI BI BI
BI
BI
BI
BI
BI
BI
BI
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN IN IN
OUT OUT
OUT OUT
IN
IN
IN
IN IN
IN
IN
OUT
OUT OUT
OUT
IN
IN
IN
IN IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
BI
BI
BI
BI
BI
BI
BI BI BI BI BI
BI BI BI BI BI
BI
BI BI BI BI
BI
IN IN
BI
BI
IN IN
IN IN
D
SG
D
SG
D
SG
D
SG
IN IN
CK*
DQ17
CKE
A8/AP
RFU
DQ9
A11
CK
CS0*
DM2
BA2
BA1
BA0
WDQS1
WDQS3
WDQS2
WDQS0
RDQS3
RDQS2
SEN
DQ24
DQ20
DQ1
DQ0
DQ2 DQ3
DQ5 DQ6
DQ4
DQ7
DQ10 DQ11 DQ12 DQ13
DQ15 DQ16
DQ18 DQ19
DQ21
DQ23
DQ22
DQ25 DQ26 DQ27
DQ29
DQ28
DQ30 DQ31
A3 A4
DM3
DM1
DM0
CAS*
WE*
MF
ZQ
RAS*
A5 A6
A9
DQ8
RDQS1
RDQS0
RESET
A10
A7
A2
A1
A0
A12/CS1*
DQ14
MFHIGH
MFHIGH
(1 OF 2)
MFHIGH
CK*
DQ17
CKE
A8/AP
RFU
DQ9
A11
CK
CS0*
DM2
BA2
BA1
BA0
WDQS1
WDQS3
WDQS2
WDQS0
RDQS3
RDQS2
SEN
DQ24
DQ20
DQ1
DQ0
DQ2 DQ3
DQ5 DQ6
DQ4
DQ7
DQ10 DQ11 DQ12 DQ13
DQ15 DQ16
DQ18 DQ19
DQ21
DQ23
DQ22
DQ25 DQ26 DQ27
DQ29
DQ28
DQ30 DQ31
A3 A4
DM3
DM1
DM0
CAS*
WE*
MF
ZQ
RAS*
A5 A6
A9
DQ8
RDQS1
RDQS0
RESET
A10
A7
A2
A1
A0
A12/CS1*
DQ14
MFHIGH
MFHIGH
(1 OF 2)
MFHIGH
VDD0 VDD1
VDD4
VDD3
VDD2
VSS6 VSS7
VSS3
VSS5
VSS2
VSS1
VSS0
VSS4
VSSA0 VSSA1
VDDA0 VDDA1
VDD7
VDD6
VDDQ0 VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8 VDDQ9 VDDQ10 VDDQ11 VDDQ12 VDDQ13 VDDQ14 VDDQ15 VDDQ16 VDDQ17 VDDQ18 VDDQ19 VDDQ20 VDDQ21
VSSQ0
VSSQ3 VSSQ4 VSSQ5 VSSQ6 VSSQ7 VSSQ8
VSSQ9 VSSQ10 VSSQ11 VSSQ12 VSSQ13 VSSQ14 VSSQ15 VSSQ16 VSSQ17 VSSQ18 VSSQ19
VREF0 VREF1
VSSQ2
VSSQ1
VDD5
(2 OF 2)
VDD0 VDD1
VDD4
VDD3
VDD2
VSS6 VSS7
VSS3
VSS5
VSS2
VSS1
VSS0
VSS4
VSSA0 VSSA1
VDDA0 VDDA1
VDD7
VDD6
VDDQ0 VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8 VDDQ9 VDDQ10 VDDQ11 VDDQ12 VDDQ13 VDDQ14 VDDQ15 VDDQ16 VDDQ17 VDDQ18 VDDQ19 VDDQ20 VDDQ21
VSSQ0
VSSQ3 VSSQ4 VSSQ5 VSSQ6 VSSQ7 VSSQ8
VSSQ9 VSSQ10 VSSQ11 VSSQ12 VSSQ13 VSSQ14 VSSQ15 VSSQ16 VSSQ17 VSSQ18 VSSQ19
VREF0 VREF1
VSSQ2
VSSQ1
VDD5
(2 OF 2)
BI
BI
BI
BI BI
BI
BI
BI
NC NC
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER
SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
U8400.J12
Connect to designated pin, then GND Connect to designated pin, then GND
BOM options provided by this page:
(NONE)
U8400.J1 U8400.J1
U8400.J12
VRAM4
Signal aliases required by this page:
- =PP1V8_S0_FB_VDD
Power aliases required by this page:
Page Notes
- =PP1V8_S0_FB_VREFA
549
MF-LF
402
1%
1/16W
R8430
1
2
1.33K
MF-LF
402
1%
1/16W
R8431
1
2
0.1uF
X5R 402
10% 16V
C8403
1
2
0.1uF
X5R 402
10% 16V
C8402
1
2
0.1uF
X5R 402
10% 16V
C8404
1
2
X5R 402
10% 16V
0.1uF
C8401
1
2
0.1uF
X5R 402
10% 16V
C8422
1
2
0.1uF
X5R 402
10% 16V
C8423
1
2
0.1uF
X5R 402
10% 16V
C8424
1
2
0.1uF
X5R 402
10% 16V
C8425
1
2
0.1uF
X5R 402
10% 16V
C8426
1
2
100
MF-LF 402
5% 1/16W
R8449
1
2
243
MF-LF
402
1%
1/16W
R8448
1
2
VRAM4
121
MF-LF 402
1% 1/16W
R8445
1
2
243
MF-LF
402
1%
1/16W
R8446
1
2
0.1uF
X5R 402
10% 16V
C8421
1
2
0.1uF
X5R 402
10% 16V
C8415
1
2
0.1uF
X5R 402
10% 16V
C8410
1
2
1K
MF-LF
402
5%
1/16W
R8440
1
2
243
MF-LF 402
1% 1/16W
R8447
1
2
VRAM4
121
MF-LF
402
1%
1/16W
R8444
1
2
VRAM4
121
MF-LF 402
1% 1/16W
R8443
1
2
VRAM4
121
MF-LF
402
1%
1/16W
R8442
1
2
76 98
76 98
76 98
76 98
76 98
76 98
76 98
76 98
76 98
76 98
76 98
76 98
76 98
76 98
76 98
76 98
76 98
76 98
76 98
76 98
76 98
76 98
76 98
76 98
76 98
76 98
76 98
76 98
76 98
76 98
76 98
76 98
76 98
76 98
76 98
76 98
76 77 98
76 77 98
76 77 98
76 77 98
76 77 98
76 77 98
76 98
76 77 98
76 98
76 98
76 98
76 98
76 77 98
76 77 98
76 77 98
76 77 98
76 77 98
76 77 98
76 98
76 98
76 98
76 98
76 77 98
76 98
76 98
76 98
76 98
76 98
76 98
76 98
76 98
76 77 98
76 77 98
76 77 98
76 98
76 98
76 98
76 98
76 98
76 98
76 98
76 98
76 77 98
76 77 98
76 98
76
76 77 98
76 98
76 98
76 98
76 77 98
76 77 98
76 77 98
76 77 98
76 77 98
76 77 98
76 98
76 98
76 98
76 98
76 77 98
76 77 98
1K
MF-LF
402
5%
1/16W
R8490
1
2
VRAM4
121
MF-LF
402
1%
1/16W
R8492
1
2
0.1uF
X5R 402
10% 16V
C8471
1
2
0.1uF
X5R 402
10% 16V
C8472
1
2
243
MF-LF
402
1%
1/16W
R8498
1
2
100
MF-LF 402
5% 1/16W
R8499
1
2
VRAM4
121
MF-LF 402
1% 1/16W
R8493
1
2
VRAM4
121
MF-LF 402
1% 1/16W
R8495
1
2
VRAM4
121
MF-LF
402
1%
1/16W
R8494
1
2
243
MF-LF 402
1% 1/16W
R8497
1
2
243
MF-LF
402
1%
1/16W
R8496
1
2
0.1uF
X5R 402
10% 16V
C8473
1
2
0.1uF
X5R 402
10% 16V
C8474
1
2
0.1uF
X5R 402
10% 16V
C8475
1
2
0.1uF
X5R 402
10% 16V
C8476
1
2
0.1uF
X5R 402
10% 16V
C8451
1
2
0.1uF
X5R 402
10% 16V
C8452
1
2
0.1uF
X5R 402
10% 16V
C8460
1
2
0.1uF
X5R 402
10% 16V
C8453
1
2
0.1uF
X5R 402
10% 16V
C8465
1
2
0.1uF
X5R 402
10% 16V
C8454
1
2
76 98
76 98
76 98
76 98
76 98
76 98
76 98
76 98
76 98
76 98
76 98
76 98
76 98
76 98
76 98
76 98
76 98
76 98
76 98
76 98
76 98
76 98
76 98
76 98
76 98
76 98
76 98
76 98
10UF
X5R 603
20%
6.3V
C8400
1
2
10UF
X5R 603
20%
6.3V
C8420
1
2
10UF
X5R 603
20%
6.3V
C8450
1
2
10UF
X5R 603
20%
6.3V
C8470
1
2
0.01UF
CERM
402
10% 16V
C8446
1
2
0.01UF
CERM
402
10% 16V
C8496
1
2
931
MF-LF
402
1%
1/16W
R8432
1
2
0.01uF
CERM 402
10% 16V
C8481
1
2
931
MF-LF
402
1%
1/16W
R8482
1
2
549
MF-LF
402
1%
1/16W
R8480
1
2
1.33K
MF-LF
402
1%
1/16W
R8481
1
2
77 78 79 80
77 78 79 80
SSM6N15FEAPE
SOT563
Q8400
6
2
1
SSM6N15FEAPE
SOT563
Q8450
6
2
1
931
MF-LF
402
1%
1/16W
R8435
1
2
549
MF-LF
402
1%
1/16W
R8433
1
2
1.33K
MF-LF
402
1%
1/16W
R8434
1
2
0.01UF
CERM 402
10% 16V
C8431
1
2
SSM6N15FEAPE
SOT563
Q8400
3
5
4
0.01uF
CERM 402
10% 16V
C8482
1
2
931
MF-LF
402
1%
1/16W
R8485
1
2
549
MF-LF
402
1%
1/16W
R8483
1
2
1.33K
MF-LF
402
1%
1/16W
R8484
1
2
SSM6N15FEAPE
SOT563
Q8450
3
5
4
76 77 98 76 77 98
OMIT
CRITICAL
32MX32-900MHZ-MFH
K4J10324QD-HC11
BGA
U8450
K9
H11
K11
L9
J3
K10
M9 K4 H2 K3 L4 K2 M4
G9 G4 H3
F9
J11 J10
H9
F4
E3 E10 N10 N3
B2 B3
C11 C10 E11 F10 F11 G10 M11 L10 N11 M10
C2
R11
R10 T11 T10 M2 L3 N2 M3 R2 R3
C3
T2 T3
E2
F3
F2
G3
B11
B10
A9
H10
D3 D10 P10
P3
V9
J2
V4
D2 D11 P11
P2
H4
A4
32MX32-900MHZ-MFH
BGA
CRITICAL
OMIT
K4J10324QD-HC11
U8400
K9
H11
K11
L9
J3
K10
M9 K4 H2 K3 L4 K2 M4
G9 G4 H3
F9
J11 J10
H9
F4
E3 E10 N10 N3
B2 B3
C11 C10 E11 F10 F11 G10 M11 L10 N11 M10
C2
R11 R10 T11 T10 M2 L3 N2 M3 R2 R3
C3
T2 T3
E2 F3 F2 G3 B11 B10
A9
H10
D3 D10 P10
P3
V9
J2
V4
D2 D11 P11
P2
H4
A4
OMIT
CRITICAL
32MX32-900MHZ-MFH
K4J10324QD-HC11
BGA
U8400
A2
A11
F1
F12
M1
M12
V2
V11
K1
K12
A1
A12
J4 J9 N1 N4 N9
N12
R1 R4 R9
R12
C1
V1
V12
C4 C9
C12
E1 E4 E9
E12
H1
H12
A3 A10 G1 G12 L1 L12 V3 V10
J1 J12
B1 B4
L2 L11 P1 P4 P9 P12 T1 T4 T9 T12
B9 B12 D1 D4 D9 D12 G2 G11
OMIT
CRITICAL
32MX32-900MHZ-MFH
K4J10324QD-HC11
BGA
U8450
A2
A11
F1
F12
M1
M12
V2
V11
K1
K12
A1
A12
J4 J9 N1 N4 N9
N12
R1 R4 R9
R12
C1
V1
V12
C4 C9
C12
E1 E4 E9
E12
H1
H12
A3 A10 G1 G12 L1 L12 V3 V10
J1 J12
B1 B4
L2 L11 P1 P4 P9 P12 T1 T4 T9 T12
B9 B12 D1 D4 D9 D12 G2 G11
76 98
76 98
76 98
76 98
76 98
76 98
0.01UF
CERM 402
10% 16V
C8432
1
2
SYNC_MASTER=K17_REF
SYNC_DATE=06/15/2009
GDDR3 Frame Buffer A (Top)
FB_A_DQM_L<4>
FB_A_DQM_L<5>
FB_A_DQM_L<7>
FB_A_DQM_L<6>
FB_A_DQM_L<0>
FB_A_DQM_L<3>
FB_A_DQM_L<2>
FB_A_DQM_L<1>
FB_VREF_UNTERM
FB_A_DRAM_RST FB_A_RDQS<6>
FB_A1_MF
FB_A_CLK_P<1>
FB_A_MA<12>
FB_A_UCKE
FB_A_CLK_N<1> FB_A_UCS0_L FB_A_WE_L FB_A_UCAS_L FB_A_RAS_L
FB_A_RDQS<0>
FB_A_RDQS<2>
FB_A_DQ<12>
FB_A_DQ<20> FB_A_DQ<23>
FB_A_DQ<25>
FB_A0_SEN
FB_A_MA<9>
FB_A_LMA<2>
FB_A_MA<1>
FB_A_MA<0>
FB_A_MA<6>
FB_A_MA<10> FB_A_MA<11> FB_A_MA<11>
FB_A_MA<7>
FB_A_LMA<5>
FB_A_MA<10>
FB_A_UMA<4>
FB_A_RDQS<5> FB_A_RDQS<4>
FB_A_WDQS<6> FB_A_WDQS<7> FB_A_WDQS<5> FB_A_WDQS<4>
FB_A_BA<0> FB_A_BA<1> FB_A_BA<2>
FB_A1_SEN
FB_A_MA<1>
FB_A_UMA<5>
FB_A_MA<9>
FB_A_DQ<54> FB_A_DQ<52> FB_A_DQ<50>
FB_A_DQ<48> FB_A_DQ<51> FB_A_DQ<55>
FB_A_DQ<53>
FB_A_DQ<57>
FB_A_DQ<49>
FB_A_DQ<56>
FB_A_DQ<62>
FB_A_DQ<38>
FB_A_DQ<33>
FB_A_DQ<35> FB_A_DQ<34>
FB_A_DQ<32> FB_A_DQ<39> FB_A_DQ<36>
PP1V8R1V55_S0GPU_ISNS
FB_A_MA<8>
FB_A_LMA<3>
FB_A_DQ<19>
FB_A_DQ<21>
FB_A_DQ<6> FB_A_DQ<7>
FB_A_DQ<5>
FB_A_DQ<1>
FB_A_WDQS<0>
FB_A_DQ<14>
PP1V8R1V55_S0GPU_ISNS PP1V8R1V55_S0GPU_ISNS
FB_A0_VREF_UNTERM_L
FB_A2_VREF FB_A3_VREF
FB_A_CLK1_TERM
VOLTAGE=0.9V
GPU_FB_A_VREF_DIV
FB_A1_VREF
FB_A2_VREF_UNTERM_L
FB_A0_VREF
FB_A_CLK0_TERM
VOLTAGE=0.9V
FB_A1_VREF_UNTERM_L
FB_A3_VREF_UNTERM_L
FB_A_DQ<37>
FB_A_MA<7>
FB_A_RDQS<7>
FB_VREF_UNTERM
FB_A_UMA<2>
FB_A_DQ<59> FB_A_DQ<61> FB_A_DQ<46>
FB_A_UMA<3>
FB_A_MA<0>
FB_A_MA<6>
FB_A_MA<8>
FB_A_DQ<63> FB_A_DQ<60> FB_A_DQ<58>
FB_A_DQ<47>
FB_A_DQ<43> FB_A_DQ<40>
FB_A_DQ<44> FB_A_DQ<41>
FB_A_DQ<42>
FB_A_DQ<45>
FB_A1_ZQ
PP1V8R1V55_S0GPU_ISNS
FB_A_DQ<22>
FB_A_DQ<17>
FB_A_DQ<10>
FB_A_DQ<13>
FB_A_DQ<9>
FB_A_DQ<15>
FB_A_DQ<11>
FB_A_DQ<16>
FB_A_RDQS<1>
FB_A_BA<2>
FB_A_WDQS<1>
FB_A_LMA<4>
GPU_FB_A_VREF_DIV
FB_A_BA<1>
FB_A_BA<0>
FB_A_WDQS<3>
FB_A_WDQS<2>
FB_A_RDQS<3>
FB_A_DRAM_RST
FB_A0_ZQ
FB_A_LCKE FB_A_MA<12>
FB_A_CLK_P<0> FB_A_CLK_N<0> FB_A_LCS0_L FB_A_WE_L FB_A_LCAS_L FB_A_RAS_L
FB_A0_MF
FB_A_DQ<4>
FB_A_DQ<0>
FB_A_DQ<30>
FB_A_DQ<27>
FB_A_DQ<8>
FB_A_DQ<28>
FB_A_DQ<26>
FB_A_DQ<18>
FB_A_DQ<24>
FB_A_DQ<29>
FB_A_DQ<31> FB_A_DQ<2> FB_A_DQ<3>
84 OF 132
<E4LABEL>
<SCH_NUM>
<BRANCH>
77 OF 101
6 7 8
50 56 75 76 77 78
6 7 8
50 56 75 76
77 78
6 7 8
50 56 75 76 77 78
8
32 77
6 7 8
50 56 75 76
77 78
8
32 77
Page 78
IN
IN IN
IN
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI BI
BI
BI BI
BI
BI
BI
BI BI
BI
BI
BI
BI BI BI BI
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT OUT OUT OUT
IN
IN
IN
IN IN
IN
IN
OUT
OUT OUT
OUT
IN
IN
IN
IN IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
BI BI BI BI
BI BI
BI BI
BI BI BI BI BI
BI BI BI BI BI
BI BI BI BI BI
BI
BI BI BI BI
BI
IN IN
BI
BI
IN IN
IN IN
D
SG
D
SG
D
SG
D
SG
ININ
CK*
DQ17
CKE
A8/AP
RFU
DQ9
A11
CK
CS0*
DM2
BA2
BA1
BA0
WDQS1
WDQS3
WDQS2
WDQS0
RDQS3
RDQS2
SEN
DQ24
DQ20
DQ1
DQ0
DQ2 DQ3
DQ5 DQ6
DQ4
DQ7
DQ10 DQ11 DQ12 DQ13
DQ15 DQ16
DQ18 DQ19
DQ21
DQ23
DQ22
DQ25 DQ26 DQ27
DQ29
DQ28
DQ30 DQ31
A3 A4
DM3
DM1
DM0
CAS*
WE*
MF
ZQ
RAS*
A5 A6
A9
DQ8
RDQS1
RDQS0
RESET
A10
A7
A2
A1
A0
A12/CS1*
DQ14
MFHIGH
MFHIGH
(1 OF 2)
MFHIGH
CK*
DQ17
CKE
A8/AP
RFU
DQ9
A11
CK
CS0*
DM2
BA2
BA1
BA0
WDQS1
WDQS3
WDQS2
WDQS0
RDQS3
RDQS2
SEN
DQ24
DQ20
DQ1
DQ0
DQ2 DQ3
DQ5 DQ6
DQ4
DQ7
DQ10 DQ11 DQ12 DQ13
DQ15 DQ16
DQ18 DQ19
DQ21
DQ23
DQ22
DQ25 DQ26 DQ27
DQ29
DQ28
DQ30 DQ31
A3 A4
DM3
DM1
DM0
CAS*
WE*
MF
ZQ
RAS*
A5 A6
A9
DQ8
RDQS1
RDQS0
RESET
A10
A7
A2
A1
A0
A12/CS1*
DQ14
MFHIGH
MFHIGH
(1 OF 2)
MFHIGH
VDD0 VDD1
VDD4
VDD3
VDD2
VSS6 VSS7
VSS3
VSS5
VSS2
VSS1
VSS0
VSS4
VSSA0 VSSA1
VDDA0 VDDA1
VDD7
VDD6
VDDQ0 VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8 VDDQ9 VDDQ10 VDDQ11 VDDQ12 VDDQ13 VDDQ14 VDDQ15 VDDQ16 VDDQ17 VDDQ18 VDDQ19 VDDQ20 VDDQ21
VSSQ0
VSSQ3 VSSQ4 VSSQ5 VSSQ6 VSSQ7 VSSQ8
VSSQ9 VSSQ10 VSSQ11 VSSQ12 VSSQ13 VSSQ14 VSSQ15 VSSQ16 VSSQ17 VSSQ18 VSSQ19
VREF0 VREF1
VSSQ2
VSSQ1
VDD5
(2 OF 2)
VDD0 VDD1
VDD4
VDD3
VDD2
VSS6 VSS7
VSS3
VSS5
VSS2
VSS1
VSS0
VSS4
VSSA0 VSSA1
VDDA0 VDDA1
VDD7
VDD6
VDDQ0 VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8 VDDQ9 VDDQ10 VDDQ11 VDDQ12 VDDQ13 VDDQ14 VDDQ15 VDDQ16 VDDQ17 VDDQ18 VDDQ19 VDDQ20 VDDQ21
VSSQ0
VSSQ3 VSSQ4 VSSQ5 VSSQ6 VSSQ7 VSSQ8
VSSQ9 VSSQ10 VSSQ11 VSSQ12 VSSQ13 VSSQ14 VSSQ15 VSSQ16 VSSQ17 VSSQ18 VSSQ19
VREF0 VREF1
VSSQ2
VSSQ1
VDD5
(2 OF 2)
BI
NC NC
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER
SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
Connect to designated pin, then GND
VRAM4
Connect to designated pin, then GND
U8500.J12
U8500.J1
U8500.J12
(NONE)
U8500.J1
BOM options provided by this page:
Signal aliases required by this page:
- =PP1V8_S0_FB_VDD
Power aliases required by this page:
Page Notes
- =PP1V8_S0_FB_VREF_B
16V
10%
402
X5R
0.1uF
C8503
1
2
10%
402
X5R
0.1uF
16V
C8502
1
2
16V
10%
402
X5R
0.1uF
C8504
1
2
16V
10%
402
X5R
0.1uF
C8501
1
2
16V
10% 402
X5R
0.1uF
C8522
1
2
16V
10% 402
X5R
0.1uF
C8523
1
2
16V
10% 402
X5R
0.1uF
C8524
1
2
16V
10% 402
X5R
0.1uF
C8525
1
2
16V
10% 402
X5R
0.1uF
C8526
1
2
1/16W
5%
402
MF-LF
100
R8549
1
2
1/16W
1%
402
MF-LF
243
R8548
1
2
16V
10% 402
X5R
0.1uF
C8521
1
2
16V
10%
402
X5R
0.1uF
C8515
1
2
16V
10%
402
X5R
0.1uF
C8510
1
2
76 98
76 98
76 98
76 98
76 98
76 98
76 98
76 98
76 98
76 98
76 98
76 98
76 98
76 98
76 98
76 98
76 98
76 98
76 98
76 98
76 98
76 98
76 98
76 98
76 98
76 98
76 98
76 98
76 98
76 98
76 98
76 98
76 98
76 98
76 98
76 98
76 78 98
76 78 98
76 78 98
76 78 98
76 78 98
76 78 98
76 98
76 78 98
76 98
76 98
76 98
76 98
76 78 98
76 78 98
76 78 98
76 78 98
76 78 98
76 78 98
76 98
76 98
76 98
76 98
76 78 98
76 98
76 98
76 98
76 98
76 98
76 98
76 98
76 98
76 78 98
76 78 98
76 78 98
76 98
76 98
76 98
76 98
76 98
76 98
76 98
76 98
76 78 98
76 78 98
76 98
76
76 78 98
76 98
76 98
76 98
76 78 98
76 78 98
76 78 98
76 78 98
76 78 98
76 78 98
76 98
76 98
76 98
76 98
76 78 98
76 78 98
16V
10% 402
X5R
0.1uF
C8571
1
2
16V
10% 402
X5R
0.1uF
C8572
1
2
1/16W
1%
402
MF-LF
243
R8598
1
2
1/16W
5%
402
MF-LF
100
R8599
1
2
16V
10% 402
X5R
0.1uF
C8573
1
2
16V
10% 402
X5R
0.1uF
C8574
1
2
16V
10% 402
X5R
0.1uF
C8575
1
2
16V
10% 402
X5R
0.1uF
C8576
1
2
16V
10%
402
X5R
0.1uF
C8551
1
2
16V
10%
402
X5R
0.1uF
C8552
1
2
16V
10%
402
X5R
0.1uF
C8560
1
2
16V
10%
402
X5R
0.1uF
C8553
1
2
16V
10%
402
X5R
0.1uF
C8565
1
2
16V
10%
402
X5R
0.1uF
C8554
1
2
76 98
76 98
76 98
76 98
76 98
76 98
76 98
76 98
76 98
76 98
76 98
76 98
76 98
76 98
76 98
76 98
76 98
76 98
76 98
76 98
76 98
76 98
76 98
76 98
76 98
76 98
76 98
76 98
76 98
76 98
76 98
76 98
76 98
6.3V
20%
603
X5R
10UF
C8500
1
2
6.3V
20% 603
X5R
10UF
C8520
1
2
6.3V
20%
603
X5R
10UF
C8550
1
2
6.3V
20% 603
X5R
10UF
C8570
1
2
1/16W
1%
402
MF-LF
243
R8546
1
2
1/16W
1% MF-LF
243
402
R8547
1
2
1/16W
1%
402
MF-LF
121
VRAM4
R8544
1
2
1%
402
MF-LF
121
VRAM4
1/16W
R8545
1
2
1/16W
1%
402
MF-LF
121
VRAM4
R8542
1
2
1/16W
5%
402
MF-LF
1K
R8540
1
2
1/16W 402
MF-LF
121
VRAM4
1%
R8543
1
2
1/16W
1%
402
MF-LF
243
R8596
1
2
1/16W
1%
402
MF-LF
243
R8597
1
2
1/16W
1%
402
MF-LF
121
VRAM4
R8595
1
2
1/16W
1%
402
MF-LF
121
VRAM4
R8594
1
2
1/16W
1%
402
MF-LF
121
VRAM4
R8592
1
2
1/16W
1%
402
MF-LF
121
VRAM4
R8593
1
2
1/16W
5%
402
MF-LF
1K
R8590
1
2
16V
10%
402
CERM
0.01UF
C8596
1
2
0.01UF
16V
10%
402
CERM
C8546
1
2
1/16W
1%
402
MF-LF
1.33K
R8531
1
2
1/16W
1%
402
MF-LF
931
R8532
1
2
16V
10% 402
CERM
0.01uF
C8531
1
2
1/16W
1%
402
MF-LF
549
R8530
1
2
1/16W
1%
402
MF-LF
1.33K
R8581
1
2
931
402
MF-LF
1/16W
1%
R8582
1
2
1/16W
1%
402
MF-LF
549
R8580
1
2
16V
10% 402
CERM
0.01uF
C8581
1
2
77 78 79 80
77 78 79 80
SOT563
SSM6N15FEAPE
Q8500
6
2
1
SOT563
SSM6N15FEAPE
Q8550
6
2
1
0.01uF
16V
10% 402
CERM
C8532
1
2
1/16W
1%
402
MF-LF
931
R8535
1
2
1/16W
1%
402
MF-LF
549
R8533
1
2
1/16W
1%
402
MF-LF
1.33K
R8534
1
2
SOT563
SSM6N15FEAPE
Q8500
3
5
4
16V
10% 402
CERM
0.01uF
C8582
1
2
1/16W
1%
402
MF-LF
931
R8585
1
2
1/16W
1%
402
MF-LF
549
R8583
1
2
1/16W
1%
402
MF-LF
1.33K
R8584
1
2
SOT563
SSM6N15FEAPE
Q8550
3
5
4
76 78 98 76 78 98
BGA
K4J10324QD-HC11
32MX32-900MHZ-MFH
CRITICAL
OMIT
U8550
K9
H11
K11
L9
J3
K10
M9 K4 H2 K3 L4 K2 M4
G9 G4 H3
F9
J11 J10
H9
F4
E3 E10 N10 N3
B2 B3
C11 C10 E11 F10 F11 G10 M11 L10 N11 M10
C2
R11
R10 T11 T10 M2 L3 N2 M3 R2 R3
C3
T2 T3
E2
F3
F2
G3
B11
B10
A9
H10
D3 D10 P10
P3
V9
J2
V4
D2 D11 P11
P2
H4
A4
OMIT
K4J10324QD-HC11
32MX32-900MHZ-MFH
CRITICAL
BGA
U8500
K9
H11
K11
L9
J3
K10
M9 K4 H2 K3 L4 K2 M4
G9 G4 H3
F9
J11 J10
H9
F4
E3 E10 N10 N3
B2 B3
C11 C10 E11 F10 F11 G10 M11 L10 N11 M10
C2
R11 R10 T11 T10 M2 L3 N2 M3 R2 R3
C3
T2 T3
E2 F3 F2 G3 B11 B10
A9
H10
D3 D10 P10
P3
V9
J2
V4
D2 D11 P11
P2
H4
A4
BGA
K4J10324QD-HC11
32MX32-900MHZ-MFH
CRITICAL
OMIT
U8500
A2
A11
F1
F12
M1
M12
V2
V11
K1
K12
A1
A12
J4 J9 N1 N4 N9
N12
R1 R4 R9
R12
C1
V1
V12
C4 C9
C12
E1 E4 E9
E12
H1
H12
A3 A10 G1 G12 L1 L12 V3 V10
J1 J12
B1 B4
L2 L11 P1 P4 P9 P12 T1 T4 T9 T12
B9 B12 D1 D4 D9 D12 G2 G11
BGA
K4J10324QD-HC11
32MX32-900MHZ-MFH
CRITICAL
OMIT
U8550
A2
A11
F1
F12
M1
M12
V2
V11
K1
K12
A1
A12
J4 J9 N1 N4 N9
N12
R1 R4 R9
R12
C1
V1
V12
C4 C9
C12
E1 E4 E9
E12
H1
H12
A3 A10 G1 G12 L1 L12 V3 V10
J1 J12
B1 B4
L2 L11 P1 P4 P9 P12 T1 T4 T9 T12
B9 B12 D1 D4 D9 D12 G2 G11
76 98
GDDR3 Frame Buffer B (Top)
SYNC_DATE=06/15/2009
SYNC_MASTER=K17_REF
FB_B_DQM_L<6>
FB_B_DQM_L<4>
FB_B_DQM_L<7>
FB_B_DQM_L<5>
FB_B_DQM_L<0>
FB_B_DQM_L<3>
FB_B_DQM_L<2>
FB_B_DQM_L<1>
FB_B_DQ<11>
FB_B0_ZQ
FB_B_UMA<2>
FB_B_MA<0> FB_B_MA<1>
FB_B_UMA<3>
FB_B_MA<9>
FB_B_CLK_P<1>
FB_B_UCS0_L
FB_B_RAS_L
FB_B_UCAS_L
FB_B_MA<6>
FB_B_LMA<4>
FB_B_LMA<3>
FB_B_MA<6>
FB_B2_VREF_UNTERM_L
FB_B_WDQS<4>
FB_B_MA<12>
FB_B_LCKE FB_B_MA<12>
FB_B_MA<11>
FB_B_MA<10>
FB_B_DQ<54> FB_B_DQ<49>
FB_B_DQ<50>
FB_B_MA<11>
PP1V8R1V55_S0GPU_ISNS
FB_B_BA<1>
FB_B_MA<0> FB_B_MA<1>
FB_B_WDQS<7>
FB_B_WDQS<6>
FB_B_BA<2>
FB_B1_ZQ
FB_B1_SEN
FB_B_RDQS<5> FB_B_RDQS<7> FB_B_RDQS<4> FB_B_RDQS<6>
FB_B_WDQS<5>
FB_B_BA<1>
FB_B_DQ<43>
FB_B_DQ<46>
FB_B_BA<0>
FB_B_MA<10>
FB_B_UMA<5>
FB_B1_VREF
FB_B3_VREFFB_B2_VREF
FB_B3_VREF_UNTERM_L
FB_VREF_UNTERM
VOLTAGE=0.9V
FB_B_CLK1_TERM
VOLTAGE=0.9V
FB_B_CLK0_TERM
FB_B_DQ<47>
GPU_FB_B_VREF_DIV
PP1V8R1V55_S0GPU_ISNS
GPU_FB_B_VREF_DIV
FB_B_MA<8>
FB_B_LMA<2>
FB_B_MA<7>
FB_B_LMA<5>
FB_B_DQ<20> FB_B_DQ<29>
FB_B_DQ<8>
FB_B_DQ<19> FB_B_DQ<21>
FB_B_DQ<14>
FB_B_DQ<25>
FB_B_DQ<31>
FB_B_DQ<30>
FB_B_DQ<1>
FB_B_DQ<5>
FB_B_DQ<6>
FB_B_DQ<3>
FB_B_BA<2>
FB_B_BA<0>
FB_B_WDQS<0>
FB_B_WDQS<3>
FB_B_WDQS<1>
FB_B0_SEN
FB_B_WDQS<2>
FB_B_DQ<58>
FB_B_DQ<56>
FB_B_DQ<59>
FB_B_DQ<44>
FB_B_DQ<42> FB_B_DQ<40> FB_B_DQ<41>
FB_B_DQ<60>
FB_B_MA<7>
FB_B_UMA<4>
FB_B_CLK_N<1>
FB_B_MA<8>
FB_B_DQ<32>
FB_B_DQ<48>
FB_B_DQ<53>
FB_B_DQ<52>
FB_B_DQ<55>
FB_B_DQ<51>
FB_B_DRAM_RST
FB_B_DQ<9>
FB_B1_MF
FB_B_UCKE
FB_B_WE_L
FB_B_MA<9>
FB_B_LCS0_L FB_B_WE_L
FB_B_RAS_L
FB_B_CLK_N<0>
FB_B_CLK_P<0>
FB_B0_VREF_UNTERM_L
FB_B_DQ<7>
FB_B_DQ<15>
FB_B_DQ<10>
FB_B_DQ<16>
FB_B_DQ<61>
FB_B_DQ<45>
FB_VREF_UNTERM
FB_B0_VREF
PP1V8R1V55_S0GPU_ISNS
FB_B_LCAS_L
FB_B0_MF
FB_B_DRAM_RST FB_B_RDQS<1>
FB_B_RDQS<2> FB_B_RDQS<3> FB_B_RDQS<0>
FB_B_DQ<18>
FB_B_DQ<22>
FB_B_DQ<17>
FB_B_DQ<13> FB_B_DQ<12>
FB_B_DQ<23>
FB_B_DQ<27> FB_B_DQ<24>
FB_B_DQ<28>
FB_B_DQ<26> FB_B_DQ<4>
FB_B_DQ<0> FB_B_DQ<2>
FB_B1_VREF_UNTERM_L
PP1V8R1V55_S0GPU_ISNS
FB_B_DQ<33>
FB_B_DQ<34>
FB_B_DQ<35>
FB_B_DQ<39>
FB_B_DQ<37>
FB_B_DQ<38>
FB_B_DQ<36>
FB_B_DQ<62> FB_B_DQ<57> FB_B_DQ<63>
85 OF 132
<E4LABEL>
<SCH_NUM>
<BRANCH>
78 OF 101
6 7 8
50 56 75 76 77 78
8
32 78
6 7 8
50 56 75 76 77 78
8
32 78
6 7 8
50 56 75 76
77 78
6 7 8
50 56 75 76
77 78
Page 79
BI BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI BI
OUT
IN IN
IN IN
IN
IN
OUT
IN
OUT
OUT
IN
IN
(6 OF 9)
XTAL_SSIN
XTAL_OUTBUFF
XTAL_OUT
XTAL_IN
VID_PLLVDD
VDD33
THERMDP THERMDN
TESTMODE
STRAP2
STRAP1
STRAP0
SP_PLLVDD
ROM_SO
ROM_SI
ROM_SCLK
ROM_CS*
PLLVDD
MULTI_STRAP_REF1_GND
MULTI_STRAP_REF0_GND
MIOB_VSYNC
MIOB_VREF
MIOB_VDDQ_4
MIOB_VDDQ_3
MIOB_VDDQ_2
MIOB_VDDQ_1
MIOB_HSYNC
MIOB_DE
MIOB_D14
MIOB_D13
MIOB_D12
MIOB_D11
MIOB_D10
MIOB_D9
MIOB_D8
MIOB_D7
MIOB_D6
MIOB_D5
MIOB_D4
MIOB_D3
MIOB_D2
MIOB_D1
MIOB_D0
MIOB_CTL3
MIOB_CLKOUT*
MIOB_CLKOUT
MIOB_CLKIN
MIOB_CAL_PU_GND
MIOB_CAL_PD_VDDQ
MIOA_VSYNC
MIOA_VREF
MIOA_VDDQ_4
MIOA_VDDQ_3
MIOA_VDDQ_2
MIOA_VDDQ_1
MIOA_HSYNC
MIOA_DE
MIOA_D14
MIOA_D13
MIOA_D12
MIOA_D11
MIOA_D10
MIOA_D9
MIOA_D8
MIOA_D7
MIOA_D6
MIOA_D5
MIOA_D4
MIOA_D3
MIOA_D2
MIOA_D1
MIOA_D0
MIOA_CTL3
MIOA_CLKOUT*
MIOA_CLKOUT
MIOA_CLKIN
MIOA_CAL_PU_GND
MIOA_CAL_PD_VDDQ
JTAG_TRST*
JTAG_TMS
JTAG_TDO
JTAG_TDI
JTAG_TCK
GPIO23
GPIO21
GPIO19
GPIO18
GPIO17
GPIO15
GPIO14
GPIO13
GPIO12
GPIO11
GPIO10
GPIO9
GPIO8
GPIO7
GPIO6
GPIO5
GPIO4
GPIO3
GPIO2
GPIO1
GPIO0
GPIO16
GPIO22
GPIO20
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER
SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
- =PP1V2_GPU_PLLVDD
(NONE)
Power aliases required by this page:
65mA
25mA
- =PP1V2_GPU_H_PLLVDD
Signal aliases required by this page:
- =PP1V2_GPU_VID_PLLVDD
- =PP3V3_GPU_VDD33
(NONE)
- =PP3V3_GPI_MIO
110mA
Page Notes
50mA
BOM options provided by this page:
40.2K
MF-LF 402
1% 1/16W
R8697
1
2
6.3V
10%
402
X5R
1UF
C8636
1
2
4.7UF
CERM
603
20%
6.3V
C8635
1
2
0603
100NH-700MA-0.14OHM
L8635
1 2
100NH-700MA-0.14OHM
0603
L8640
1 2
16V
10% X5R
0.1uF
402
C8617
1
2
1/16W
5%
402
MF-LF
10K
R8616
1
2
1/16W
5%
402
MF-LF
10K
R8617
1
2
MF-LF
1/16W
402
1%
49.9
R8620
1
2
49.9
MF-LF
402
1%
1/16W
R8622
1
2
49.9
MF-LF 402
1% 1/16W
R8621
1
2
0.1uF
10% 16V X5R 402
C8619
1
2
5% 1/16W
402
MF-LF
10K
R8618
1
2
10K
MF-LF 402
5% 1/16W
R8619
1
2
1UF
CERM
402
10%
6.3V
C8611
1
2
1UF
CERM
402
10%
6.3V
C8610
1
2
MF-LF
49.9
402
1% 1/16W
R8623
1
2
16V
10%
402
X5R
0.1uF
C8631
1
2
603
CERM
6.3V
20%
4.7UF
C8640
1
2
4.7UF
CERM
603
20%
6.3V
C8643
1
2
4.7UF
CERM
603
20%
6.3V
C8637
1
2
40.2K
MF-LF 402
1% 1/16W
R8696
1
2
MF-LF
1/16W
5%
10K
402
R8660
1
2
0.1UF
CERM
20% 10V
402
C8694
1
2
1UF
X5R 402
10%
6.3V
C8696
1
2
20%
4.7UF
X5R-CERM1
6.3V 402
C8698
1
2
80 82
80 84
80
80
80
80
80
80
80
80
80
80 86
80
80
77 78 80
6
80
80
80 82
80 82
80 82
80 87
80 87
80 82
80
80
80
80
80
80
80
80
80
6
80
6
80
6
80
6
80
6
80
6
80
6
80
6
80
6
80
6
80
6
80
80
80
80
80
80
80
80
80
80
80
80
80
80
80
80
80
80
80
80
80
80
80
80
80
80
80
80
80
80
80
80
80
80
51 80 99
51 80 99
80
8
27 80 98
80 98
OMIT
NV-GT216
BGA
U8000
K1 K2
K4 K5 H7 J4 J6 L1 L2 L4 M4 L7
K3
L5 K6 L6 M6
H3 H2 H1 H4 H5 H6 J7
AP14 AN14 AN16 AR14 AP16
U5 T5
N4 R4 T4 P5
N1 P4
U2 U3 R6 T6 N6
P1 P2 P3 T3 T2 T1 U4 U1
N2
N3
P9 R9 T9 U9
N5
L3
AA7 AA6
AE1 V4 W4 W3
Y1 Y2
AE3 AE2 U6 W6 Y6
Y3 AB3 AB2 AB1 AC4 AC1 AC2 AC3
Y5
W1
AA9 AB9
W9 Y9
AF1
W2
N9 M9
AE9
C3 D4 D3 C4
AF9
W5 W7 V7
AP35
B4
B5
J9 J10 J11 J12 J13
AD9
B1
B2
D1
D2
1UF
X5R
10%
6.3V 402
C8641
1
2
SYNC_DATE=06/15/2009
SYNC_MASTER=K17_REF
NV GT216 GPIO/MIO/MISC
PP1V05_S0GPU
PP1V05_S0GPU
VOLTAGE=1.2V
MIN_NECK_WIDTH=0.2 mm
PP1V1_GPU_VID_PLLVDD_F
MIN_LINE_WIDTH=0.2 mm
PP1V1_GPU_H_PLLVDD_F
VOLTAGE=1.2V
MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm
NC_GPU_MIOB_D<6>
PP3V3_S0GPU
NC_GPU_MIOB_D<12>
PP3V3_S0GPU
GPU_MIOA_PU_GND
GPU_MIOA_PD_VDDQ
NC_GPU_MIOA_CLKOUT_N
NC_GPU_MIOA_CLKIN
TP_GPU_JTAG_TDI
GPU_CLK27M_SS
GPU_XTALOUTBUFF
NC_GPU_XTALOUT
GPU_CLK27M
GPU_TDIODE_P GPU_TDIODE_N
GPU_STRAP<2>
GPU_STRAP<1>
GPU_STRAP<0>
GPU_ROM_SO
GPU_ROM_SI
GPU_ROM_SCLK
NC_GPU_ROM_CS_L
GPU_STRAP_REF_MIOB_PD
NC_GPU_MIOB_VSYNC
NC_GPU_MIOB_HSYNC
NC_GPU_MIOB_DE
NC_GPU_MIOB_D<14>
NC_GPU_MIOB_D<13>
NC_GPU_MIOB_D<11>
NC_GPU_MIOB_D<10>
NC_GPU_MIOB_D<9>
NC_GPU_MIOB_D<8>
NC_GPU_MIOB_D<7>
NC_GPU_MIOB_D<5>
NC_GPU_MIOB_D<4>
NC_GPU_MIOB_D<3>
NC_GPU_MIOB_D<2>
NC_GPU_MIOB_D<1>
NC_GPU_MIOB_D<0>
NC_GPU_MIOB_CTL3
NC_GPU_MIOB_CLKOUT_N
NC_GPU_MIOB_CLKOUT_P
NC_GPU_MIOB_CLKIN
GPU_MIOB_PU_GND
GPU_MIOB_PD_VDDQ
NC_GPU_MIOA_VSYNC
NC_GPU_MIOA_HSYNC
TP_GPU_MIOA_DE
GPU_MIOA_D<13>
GPU_MIOA_D<12>
GPU_MIOA_D<11>
TP_GPU_MIOA_D<9>
TP_GPU_MIOA_D<8>
TP_GPU_MIOA_D<7>
TP_GPU_MIOA_D<6>
TP_GPU_MIOA_D<5>
TP_GPU_MIOA_D<4>
TP_GPU_MIOA_D<3>
TP_GPU_MIOA_D<2>
TP_GPU_MIOA_D<1>
TP_GPU_MIOA_D<0>
NC_GPU_MIOA_CTL3
NC_GPU_MIOA_CLKOUT_P
TP_GPU_JTAG_TRST_L
TP_GPU_JTAG_TMS
TP_GPU_JTAG_TDO
TP_GPU_JTAG_TCK
NC_GPU_GPIO_23
NC_GPU_GPIO_21
NC_GPU_GPIO_19
NC_GPU_GPIO_18
NC_GPU_GPIO_17
NC_GPU_GPIO_15
NC_GPU_GPIO_14
FBVDD_ALTVO
SMC_GFX_THROTTLE_R_L
GPU_GPIO_11
FB_VREF_UNTERM
TP_GPU_GSTATE<0>
SMC_GFX_OVERTEMP_R_L
GPU_VCORE_VID2
GPU_VCORE_VID1
GPU_VCORE_VID0
EG_BKLT_EN
EG_LCD_PWR_EN
GPU_VCORE_VID4
DP_EG_HPD
GPU_VCORE_VID3
GPU_GPIO_16
NC_GPU_GPIO_22
NC_GPU_GPIO_20
PP3V3_S0GPU
GPU_STRAP_REF_3V3_PD
GPU_MIOB_PD_VDDQ
GPU_MIOA_D<10>
GPU_MIOA_D<14>
GPU_MIOB_PU_GND
GPU_MIOA_PU_GND
GPU_MIOA_PD_VDDQ
GPU_MIOB_VREF
GPU_MIOA_VREF
GPU_TESTMODE_PD
86 OF 132
<E4LABEL>
<SCH_NUM>
<BRANCH>
79 OF 101
6 7
74 76 79 81 86
6 7
74 76 79 81 86
6 7
72 74 79 80 81 82 84
6 7
72 74 79 80 81 82 84
79
79
80
80
80
80
79
79
6 7
72 74 79 80 81 82 84
79
79
79
79
Page 80
OUT
OUT
D
GS
IN
IN
IN
IN
BI
BI
BI
BI
BI
OUT
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
DESCRIPTION
REFERENCE DES
BOM OPTION
QTY
PART NUMBER
CRITICAL
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER
SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
5 0101 PD 30k 6 0110 PD 35k (HYN 512) 7 0111 PD 45k
2 0010 PD 15k (HYN 256) 3 0011 PD 20k (SAM 256) 4 0100 PD 25k (SAM 512)
Native Func
RAMCFG[2]
8 1000 PU 5k
Unused signals
USER[0]
3GIO_PADCFG[1]
PCI_DEVID[1]
FAN_PWM
STRAP 0
XCLK_417
VGA_DEVICE
PEX_PLL_EN_TERM
USER[2]
SUB_VENDOR
USER[3]
Strapping Bit 3
HPDDVID0
GPIOs
MEM_VREF
C 1100 PU 25k
E 1110 PU 35k
0 0000 PD 5k
VID1
Renamed signals
ROM_SO
Strapping Bit 1
3GIO_PADCFG[0]
HDMI_DETECT1
Isolation FETs for DP MUX inputs
HPDF
G96 MIOA_DE and MIOA_D<9..0> are used as Debug Port.
DVI_MODE0
Unused Clocks
GP
HPDE
GP
B 1011 PU 20k
F 1111 PU 45k
ROM_SI
Native Func
THERM
RAMCFG[0]
Unused I2C Buses
(I2CS requires pullups even if not used)
I2CS ties into SMBus connection page
PCI_DEVID[0]
SWAPRDY_A
DVI_MODE1
HDMI_DETECT0
GPIOs
D 1101 PU 30k
Strap S1/S2 Bit[3:0] PU/PD Rval
USER[1]
AC_DET
PCI_DEVID[2]
LCD0_BL_PWM
HPDC
STRAP 1
STRAP 2
ROM_SCLK
Strap S1/S2 Bit[3:0] PU/PD Rval
PCI_DEVID[4:0]=0x14
VID2/MEM_VID
A 1010 PU 15k
1 0001 PD 10k
PWR_CTL1
PWR_CTL0
SLOT_CLK_CFG
3GIO_PADCFG[3]
PCI_DEVID[3]
RAMCFG[3]
PCI_DEVID[4]
Strapping Pin
Physical
Strapping Bit 0
RAMCFG[1]
3GIO_PADCFG[2]
LCD0_BL_EN
LCD0_VDD
Config Straps
SLI_SYNC
Strapping Bit 2
FB_0_BAR_SIZE
9 1001 PU 10k
SMB_ALT_ADDR
1/16W
5%
402
MF-LF
10K
GPU_SS_INT
R8781
1
2
1/16W
5%
402
MF-LF
10K
R8780
1
2
79 80
79 80 86
402
1%
OMIT
MF-LF
1/16W
45.3K
R8708
1
2
15.0K
1% 1/16W MF-LF
402
R8712
1
2
2.0K
5%
MF-LF
402
NO STUFF
1/16W
R8702
1
2
5%
2.0K
MF-LF
402
1/16W
OMIT
R8707
1
2
NO STUFF
402
MF-LF
1/16W
1%
4.99K
R8709
1
2
NO STUFF
1/16W
402
MF-LF
1%
10K
R8704
1
2
24.9K
1% 1/16W MF-LF
402
NO STUFF
R8706
1
2
1/16W
1%
402
MF-LF
45.3K
R8701
1
2
1% 1/16W MF-LF
402
34.8K
R8703
1
2
10K
1%
402
MF-LF
1/16W
R8705
1
2
SOD-VESM-HF
SSM3K15FV
DP_CA_DET_EG_FET
Q8742
3
1
2
1%
402
1/16W
100K
DP_CA_DET_EG_FET
MF-LF
R8742
1
2
84 85 87
79 80 84
402
1/16W
5%
MF-LF
4.7K
R8752
1
2
MF-LF
1/16W
5%
402
4.7K
R8753
1
2
80 81 84
8
18 84
80 81 84
8
18 84
79
79
79
79
79
79
1/16W
5%
402
MF-LF
0
DP_CA_DET_EG_PLD
R8743
1 2
87
MF-LF
402
NO STUFF
1/16W
5%
0
R8798
1 2
402
1/16W5%MF-LF
0
R8799
1 2
45
45
6
1/16W
5%
402
MF-LF
2.2K
R8797
1
2
2.2K
MF-LF
402
5%
1/16W
R8796
1
2
79 80 87
79 80 87
79 80 86
77 78 79 80
1/16W
5%
MF-LF
10K
402
R8792
1
2
1/16W
5%
402
MF-LF
10K
R8793
1
2
MF-LF
1/16W
5%
10K
402
R8794
1
2
10K
1/16W
NO STUFF
MF-LF
5%
402
R8795
1
2
MF-LF
1%
402
1/16W
10K
R8710
1
2
1/16W
5%
MF-LF
2.2K
402
R8750
1
2
5%
402
1/16W MF-LF
2.2K
R8751
1
2
MF-LF
1/16W
1%
15.0K
402
NO STUFF
R8711
1
2
R8708
1
VRAM_256_SAMSUNG
114S0343
RES,MTL FILM,1/16W,20.0K,1,0402,SMD,LF
GT216 GPIOS & STRAPS
SYNC_DATE=06/15/2009
SYNC_MASTER=K17_REF
1
VRAM_512_HYNIX
R8708
114S0368
RES,MTL FILM,1/16W,35.7K,1,0402,SMD,LF
114S0331
1
VRAM_256_HYNIX
R8708
RES,MTL FILM,1/16W,15.0K,1,0402,SMD,LF
R8708
VRAM_512_SAMSUNG
1
114S0353
RES,MTL FILM,1/16W,24.9K,1,0402,SMD,LF
PP3V3_S0GPU
GPU_ROM_SI
PP3V3_S0GPU
GPU_STRAP<2>
GPU_STRAP<1>
GPU_VCORE_VID3
EG_BKLT_EN GPU_VCORE_VID0
MAKE_BASE=TRUE
GPU_VCORE_VID1
MAKE_BASE=TRUE
GPU_VCORE_VID2
SMC_GFX_OVERTEMP_L
SMC_GFX_THROTTLE_L EG_LCD_PWR_EN EG_BKLT_EN FBVDD_ALTVO FB_VREF_UNTERM
FB_VREF_UNTERM
MAKE_BASE=TRUE
DP_EG_HPD
TP_GPU_GSTATE<1>
MAKE_BASE=TRUE
TP_GPU_GSTATE<0>
MAKE_BASE=TRUE
GPU_GPIO_16
FBVDD_ALTVO
MAKE_BASE=TRUE
MAKE_BASE=TRUE
NC_GPU_GPIO_14
MAKE_BASE=TRUE
GPU_VCORE_VID0
EG_LCD_PWR_EN
SMC_GFX_OVERTEMP_R_L TP_GPU_GSTATE<0>
GPU_GPIO_11
PP3V3_S0GPU
SMC_GFX_OVERTEMP_R_L
GPU_VCORE_VID2
SMC_GFX_THROTTLE_R_L
MAKE_BASE=TRUE
GPU_STRAP<0>
DP_EG_DDC_DATA
DP_EG_DDC_CLK
TP_GPU_JTAG_TCK TP_GPU_JTAG_TDI
TP_GPU_JTAG_TCK
MAKE_BASE=TRUE
TP_GPU_JTAG_TDI
MAKE_BASE=TRUE
TP_GPU_JTAG_TDO
MAKE_BASE=TRUE
TP_GPU_JTAG_TDO
TP_GPU_JTAG_TMS
MAKE_BASE=TRUE
TP_GPU_JTAG_TMS
TP_GPU_JTAG_TRST_L
MAKE_BASE=TRUE
TP_GPU_JTAG_TRST_L
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_GPU_MIOB_CTL3
MAKE_BASE=TRUE
TP_GPU_MIOA_DE
NC_LVDS_EG_B_CLK_P
MAKE_BASE=TRUE
NC_LVDS_EG_B_CLK_P
GPU_ROM_SO
DP_IG_DDC_DATA
FBVDD_ALTVO NC_GPU_GPIO_14
SMC_GFX_THROTTLE_R_L
DP_EG_HPD
MAKE_BASE=TRUE
NC_GPU_GPIO_23
NC_GPU_GPIO_22
MAKE_BASE=TRUE
DP_EG_DDC_CLK
MAKE_BASE=TRUE
LVDS_EG_DDC_DATA
MAKE_BASE=TRUE
LVDS_EG_DDC_CLK
MAKE_BASE=TRUE
NC_GPU_GPIO_18
NC_GPU_GPIO_17
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_GPU_I2CH_SDA
NC_GPU_GPIO_15
NC_GPU_GPIO_17 NC_GPU_GPIO_18
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_GPU_MIOA_CLKOUT_N
NC_GPU_MIOA_CTL3
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_LVDS_EG_B_DATA_N<3>
DP_EG_DDC_DATA
DP_EG_DDC_CLK
LVDS_EG_DDC_DATA
LVDS_EG_DDC_CLK
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_GPU_I2CH_SCL
NC_GPU_GPIO_21
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_GPU_I2CC_SCL
MAKE_BASE=TRUE
DP_EG_DDC_DATA
MAKE_BASE=TRUE
NC_GPU_GPIO_15 EG_DP_CA_DET
NC_GPU_I2CH_SDA
NC_GPU_I2CH_SCL
NC_GPU_I2CC_SDA
MAKE_BASE=TRUE
NC_FBA_MA<13>
NO_TEST=TRUE
NC_GPU_GPIO_19 NC_GPU_GPIO_20
NC_GPU_GPIO_22
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_GPU_GPIO_23
MAKE_BASE=TRUE
DP_IG_DDC_CLK
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_FB_B_UCS1_L
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_FB_B_LCS1_L
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_GPU_ROM_CS_L
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_FBB_MA<13>
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_FB_A_UCS1_L NC_FB_A_UCS1_L
NC_GPU_ROM_CS_L
NC_FB_B_LCS1_L
NC_FB_A_LCS1_L
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_FB_A_LCS1_L
NC_FB_B_UCS1_L
MAKE_BASE=TRUE
NC_GPU_GPIO_20
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_LVDS_EG_B_DATA_P<3>
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_LVDS_EG_A_DATA_N<3>
MAKE_BASE=TRUE
NC_LVDS_EG_B_CLK_N
NC_FBB_MA<13>
NC_GPU_I2CC_SCL
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_GPU_I2CC_SDA
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_GPU_MIOB_CLKIN
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_GPU_MIOB_VSYNC
GPU_XTALOUTBUFF
GPU_TDIODE_N
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_GPU_MIOB_CLKOUT_P
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_GPU_MIOB_D<14..0>
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_GPU_MIOB_CLKOUT_N
GPU_CLK27M_SS
GPU_MIOB_D<14..0> NC_GPU_MIOB_VSYNC NC_GPU_MIOB_HSYNC
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_GPU_MIOB_HSYNC
NC_GPU_MIOB_CLKOUT_P NC_GPU_MIOB_CLKOUT_N
NC_GPU_MIOB_DE
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_GPU_MIOB_DE
NC_GPU_MIOB_CTL3
NC_GPU_MIOB_CLKIN
MAKE_BASE=TRUE
GPU_TDIODE_N
MAKE_BASE=TRUE
GPU_TDIODE_P
MAKE_BASE=TRUE
GPU_CLK27M
MAKE_BASE=TRUE
GPU_CLK27M_SS
GPU_MIOA_D<9..0>
GPU_MIOA_D<14..10>
NC_GPU_MIOA_CLKIN
NC_GPU_MIOA_CLKOUT_P
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_GPU_MIOA_CLKOUT_P
NC_GPU_MIOA_CLKOUT_N
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_GPU_MIOA_CTL3
TP_GPU_MIOA_DE
NC_GPU_MIOA_HSYNC NC_GPU_MIOA_VSYNC
GPU_CLK27M_SS
NC_LVDS_EG_A_DATA_N<3>
NC_LVDS_EG_A_DATA_P<3>
NC_FBA_MA<13>
NC_LVDS_EG_B_CLK_N
NC_LVDS_EG_B_DATA_P<3> NC_LVDS_EG_B_DATA_N<3>
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_GPU_MIOA_D<14..10>
MAKE_BASE=TRUE
NC_GPU_GPIO_21
DP_CA_DET
DP_CA_DET_EG
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_LVDS_EG_A_DATA_P<3>
GPU_CLK27M
GPU_TDIODE_P
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_GPU_MIOA_CLKIN
MAKE_BASE=TRUE
TP_GPU_MIOA_D<9..0>
MAKE_BASE=TRUE
NC_GPU_GPIO_19
MAKE_BASE=TRUE
GPU_VCORE_VID3
FB_VREF_UNTERM
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_GPU_MIOA_HSYNC
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_GPU_MIOA_VSYNC
SMC_GFX_OVERTEMP_R_L
MAKE_BASE=TRUE
EG_DP_CA_DET
PP3V3_S0GPU
MAKE_BASE=TRUE
EG_BKLT_EN
SMC_GFX_THROTTLE_R_L
MAKE_BASE=TRUE
EG_LCD_PWR_EN
MAKE_BASE=TRUE
GPU_VCORE_VID4
GPU_VCORE_VID1
GPU_VCORE_VID4
PP3V3_S0
PP3V3_S0GPU
GPU_ROM_SCLK
87 OF 132
<E4LABEL>
<SCH_NUM>
<BRANCH>
80 OF 101
6 7
72 74 79 80 81 82 84
6 7
72 74 79 80 81 82 84
79 80
82
79 80
87
79 80
82
79 80 82
79 80 82
77 78 79 80
79 80
84
6
79 80
79
79 80
79 80 82
79 80
87
79 80
6
79 80
79
6 7
72 74 79 80 81 82 84
79 80
79 80
82
79 80
79 80
79 80
79 80
79 80 79 80
79 80 79 80
79 80 79 80
79 80
6
79 80
80 81 80 81
79 80
86
79 80
79 80
79 80
79 80 80 81 84
80 81 84
80 81 84
79 80
79 80
80 81
79 80
79 80
79 80
79 80
79 80
80 81 98
80 81 84
80 81 84
80 81 84
80 81 84
80 81
79 80
80 81
80 81 84
79 80
80
80 81
80 81
80 81
79 80
79 80
79 80
79 80
76 80
76 80
79 80
76 80
76 80
79 80
76 80
76 80
76 80
76 80
79 80
80 81 98
80 81 98
80 81
76 80
80 81
80 81
79 80
79 80
79
51 79 80 99
79 80
79
79 80
79 80 98
79 80
79 80 79 80
79 80
79 80
79 80 79 80
79 80
79 80
51 79 80 99
51 79 80 99
27 79 80 98
79 80 98
79
79 80
79 80 79 80
79 80
79 80
6
79 80
79 80
79 80
79 80 98
80 81 98
80 81 98
76 80
80 81
80 81 98
80 81 98
79 80
80 81 98
27 79 80 98
51 79 80 99
79 80
6
79
79 80
79 80 82
77 78
79
80
79 80
79 80
79 80
80
6 7
72 74 79 80 81 82 84
79 80 87
79 80
79 80 87
79 80 82
79 80
82
79 80
82
6 7
17 18 19 20 21 23 24 25
26 27 28 30 34 37 40 42 46 47
48 50 51 52 54 58 62 63 68
69 72 73 83 84 85 87 88 99
6 7
72 74 79 80 81 82 84
Page 81
OUT OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT OUT OUT
OUT OUT OUT OUT OUT OUT OUT OUT
OUT OUT
NC NC
NC NC NC NC NC NC NC NC
NC NC NC
NC NC
NC NC NC
NC NC
NC
NC
NC
NC
BI BI
BI BI
BI BI
BI BI
BI BI
OUT OUT
OUT OUT
(5 OF 9)
IFPD_L2*
IFPA_TXC*
IFPF_IOVDD
IFPAB_PLLVDD IFPAB_RSET
IFPC_PLLVDD IFPC_RSET
IFPEF_PLLVDD IFPEF_RSET
CEC
DACA_BLUE
DACA_GREEN
DACA_HSYNC
DACA_RED
DACA_RSET
DACA_VDD
DACA_VREF
DACA_VSYNC
DACB_GREEN
DACB_HSYNC
DACB_RED
DACB_RSET
DACB_VDD
DACB_VREF
DACB_VSYNC
DACB_BLUE
I2CA_SCL I2CA_SDA
I2CB_SCL I2CB_SDA
I2CC_SCL I2CC_SDA
I2CH_SCL I2CH_SDA
I2CS_SCL I2CS_SDA
IFPA_IOVDD
IFPA_TXC
IFPA_TXD0
IFPA_TXD0*
IFPA_TXD1
IFPA_TXD1*
IFPA_TXD2
IFPA_TXD2*
IFPA_TXD3
IFPA_TXD3*
IFPB_IOVDD
IFPB_TXC
IFPB_TXC*
IFPB_TXD4
IFPB_TXD4*
IFPB_TXD5
IFPB_TXD5*
IFPB_TXD6
IFPB_TXD6*
IFPB_TXD7
IFPB_TXD7*
IFPC_AUX_I2CW_SCL
IFPC_AUX_I2CW_SDA*
IFPC_IOVDD
IFPC_L0
IFPC_L0*
IFPC_L1
IFPC_L1*
IFPC_L2
IFPC_L2*
IFPC_L3
IFPC_L3*
IFPD_AUX_I2CX_SCL
IFPD_AUX_I2CX_SDA*
IFPD_IOVDD
IFPD_L0
IFPD_L0*
IFPD_L1
IFPD_L1*
IFPD_L2
IFPD_L3
IFPD_L3*
IFPD_PLLVDD
IFPD_RSET
IFPE_AUX_I2CY_SCL
IFPE_AUX_I2CY_SDA*
IFPE_IOVDD
IFPE_L0
IFPE_L0*
IFPE_L1
IFPE_L1*
IFPE_L2
IFPE_L2*
IFPE_L3
IFPE_L3*
IFPF_AUX_I2CZ_SCL
IFPF_AUX_I2CZ_SDA*
IFPF_L0
IFPF_L0*
IFPF_L1
IFPF_L1*
IFPF_L2
IFPF_L2*
IFPF_L3
IFPF_L3*
NC NC
NC NC NC NC NC NC NC NC
NC NC
NC NC NC NC NC NC NC NC
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER
SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
BOM options provided by this page:
Place at AJ8
I2CS must be pulled up if not used.
Page Notes
Power aliases required by this page:
- =PP1V8_GPU_IFPX
- =PP3V3_GPU_IFPCD_IOVDD
Signal aliases required by this page:
(NONE)
(NONE)
Place at AG10
I2CS addr fixed at 0x9E,0x9F
?mA peak for all pairs
80mA peak
I2CS addr fixed at 0x9E,0x9F
I2CS must be pulled up if not used
Place at AK8
Power inputs must be pulled down if not used
160mA peak
?mA peak for all pairs
?mA peak per diff pair
Place at AG9
?mA peak per diff pair
Sum of peak currents: 240mA
1% 1/16W
402
MF-LF
1K
R8850
1
2
0603
180-OHM-1.5A
L8805
1 2
80
80
87 98
87 98
87 98
87 98
87 98
87 98
87 98
87 98
87 98
87 98
87 98
87 98
87 98
87 98
6.3V
20%
603
CERM
4.7UF
C8805
1
2
1/16W
5%
402
MF-LF
10K
R8852
1
2
1/16W
5%
402
MF-LF
10K
R8853
1
2
1/16W
5%
402
MF-LF
10K
R8854
1
2
6.3V
20% 603
CERM
4.7UF
C8815
1
2
10V
20% 402
CERM
0.1UF
C8801
1
2
6.3V
20% 603
CERM
4.7UF
C8800
1
2
10V
20% 402
CERM
0.1UF
C8803
1
2
20%
CERM
402
0.1UF
10V
C8813
1
2
402
10V
20%
CERM
0.1UF
C8811
1
2
4.7UF
20%
6.3V 603
CERM
C8810
1
2
180-OHM-1.5A
0603
L8810
1 2
1/16W
1%
402
MF-LF
1K
R8855
1
2
84 98
84 98
84 98
84 98
84 98
84 98
84 98
84 98
84 98
84 98
10K
MF-LF 402
5% 1/16W
R8857
1
2
1/16W
5%
402
MF-LF
10K
R8856
1
2
80 84
80 84
80
80
80
80
80 84
80 84
45 48 51 97
45 48 51 97
80 98
80 98
80 98
80 98
NO STUFF
1K
MF-LF 402
5% 1/16W
R8860
1
2
1K
5%
1/16W
402
MF-LF
NO STUFF
R8861
1
2
OMIT
NV-GT216
BGA
U8000
AB5
AL14
AM14
AM13
AM15
AK13
AJ12
AK12
AL13
AJ4
AL4
AM1
AK4
AH7
AG7
AK6
AM2
G1 G4
G3 G2
E3 E4
F6 G6
E2 E1
AG9
AM11 AM12
AM8 AL8 AM10 AM9 AK10 AL10 AK11 AL11
AK9
AJ11
AG10
AP13 AN13
AN8 AP8 AP10 AN10 AR11 AR10 AN11 AP11
AP2 AN3
AJ8
AM7 AM6 AL5 AM5 AM3 AM4 AP1 AR2
AJ9 AK7
AP4 AN4
AK8
AR8 AR7 AP7 AN7 AN5 AP5 AR5 AR4
AC6
AB6
AE4 AD4
AE7
AH6 AH5 AH4 AG4 AF4 AF5 AE6 AE5
AJ6 AL1
AF3 AF2
AD7
AL2 AL3 AJ3 AJ2 AJ1 AH1 AH2 AH3
MF-LF
1/16W
1K
402
1%
R8858
1
2
402
6.3V
10%
CERM
1UF
C8816
1
2
1UF
402
6.3V
10%
CERM
C8806
1
2
402
10K
MF-LF
5% 1/16W
R8859
1
2
0603-1
300-OHM-0.5A
CRITICAL
L8800
1 2
0603-1
300-OHM-0.5A
CRITICAL
L8815
1 2
MF-LF 402
1% 1/16W
1K
R8851
1
2
NV GT216 VIDEO INTERFACES
SYNC_DATE=06/15/2009
SYNC_MASTER=K17_REF
PP3V3_GPU_IFPC_PLLVDD_F
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm
PP3V3_S0GPU
MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.4 mm
PP1V8_GPU_IFPAB_IOVDD_F
VOLTAGE=1.8V
PP1V8_GPUIFPX
DP_EG_ML_N<1>
GPU_CEC
PP3V3_S0GPU
PP1V05_S0GPU
MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.3 mm VOLTAGE=1.1V
PP1V1_GPU_IFPAB_PLLVDD_F
PP1V05_S0GPU
SMBUS_SMC_0_S0_SCL
DP_EG_DDC_CLK DP_EG_DDC_DATA
LVDS_EG_DDC_CLK
PP1V1_GPU_IFPCD_IOVDD_F
NC_GPU_I2CH_SCL
PP1V1_GPU_IFPEF_IOVDD_F
GPU_IFPD_RSET
NC_GPU_I2CC_SCL
GPU_DACB_VDD
PP1V8_GPU_IFPD_PLLVDD
MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.1 mm
VOLTAGE=1.8V
GPU_DACA_VDD
GPU_IFPD_RSET
GPU_IFPAB_RSET
GPU_IFPC_RSET
PP3V3_GPU_IFPC_PLLVDD_F
GPU_IFPEF_RSET
LVDS_EG_DDC_DATA
LVDS_EG_A_CLK_N
LVDS_EG_A_CLK_P
LVDS_EG_A_DATA_N<0>
LVDS_EG_A_DATA_P<0>
LVDS_EG_A_DATA_P<1> LVDS_EG_A_DATA_N<1> LVDS_EG_A_DATA_P<2> LVDS_EG_A_DATA_N<2> NC_LVDS_EG_A_DATA_P<3> NC_LVDS_EG_A_DATA_N<3>
NC_LVDS_EG_B_CLK_P NC_LVDS_EG_B_CLK_N
LVDS_EG_B_DATA_P<0> LVDS_EG_B_DATA_N<0> LVDS_EG_B_DATA_P<1> LVDS_EG_B_DATA_N<1> LVDS_EG_B_DATA_P<2> LVDS_EG_B_DATA_N<2> NC_LVDS_EG_B_DATA_P<3> NC_LVDS_EG_B_DATA_N<3>
DP_EG_ML_N<0>
DP_EG_ML_P<0>
DP_EG_ML_P<1>
DP_EG_AUX_CH_P
PP1V8_GPU_IFPEF_PLLVDD_F
GPU_IFPC_RSET
GPU_IFPAB_RSET
DP_EG_ML_P<2>
DP_EG_ML_N<3>
DP_EG_ML_P<3>
DP_EG_ML_N<2>
PP1V8_GPU_IFPEF_PLLVDD_F
MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.1 mm VOLTAGE=1.8V
NC_GPU_I2CH_SDA
NC_GPU_I2CC_SDA
PP1V1_GPU_IFPCD_IOVDD_F
VOLTAGE=1.1V
MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.1 mm
SMBUS_SMC_0_S0_SDA
GPU_IFPEF_RSET
PP1V1_GPU_IFPEF_IOVDD_F
MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.1 mm VOLTAGE=1.1V
DP_EG_AUX_CH_N
88 OF 132
<E4LABEL>
<SCH_NUM>
<BRANCH>
81 OF 101
81
6 7
72 74 79 80 81 82 84
6 7
72
6 7
72 74 79 80 81 82 84
6 7
74 76 79 81 86
6 7
74 76 79 81
86
81
81
81
81
81
81
81
81
81
81
81
81
81
81
81
Page 82
PVCC
THRM_PAD
FDE
PGOOD
AF_EN
VR_ON
IMON
VID4
VID3
VID2
VID1
VID0
LGATE
PGND
PHASE
UGATE
BOOT
VSS
VIN
ISP
VO
ISN
ICOMP
RTN
VSEN
VDIFF
FB
COMP
VW
OCSET
SOFT
VDD
RBIAS
OUT
IN
IN
IN
IN
IN
OUT
S
D
G
S
D
G
IN
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER
SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
BOM OPTIONS
BOM GROUP
TABLE_BOMGROUP_HEAD
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
0001 11
Vout = 0.75V - 0.90V
0.82400V
0.90125V
0.74675V
01
K18
K18
K18
K18 Default Vcore Setpoints
GPU VCore Regulator
353S2289
30A max output
-
Max perfBalanced
-
-
Max Batt
-
1
VID1 VID0VID3VID4
1
10 1
0
(PPVCORE_GPU_REG)
1 -
Voltage
VID2
(L8920 limit)
GPU VCore Setpoints
(GFXIMVP6_AGND)
402
1% MF-LF
1/16W
150
R8951
1
2
1/16W 402
1% MF-LF
150K
R8950
1
2
402
PLACE_NEAR=U8900.9:7mm
20
MF-LF
5%
1/16W
R8908
1 2
PLACE_NEAR=U8900.8:7mm
1/16W
5%
402
MF-LF
20
R8920
1 2
10K
MF-LF
402
5%
1/16W
R8907
1
2
MF-LF
1/16W
10K
402
5%
R8910
1
2
402
10%
CERM
25V
0.0068UF
C8951
1 2
MF-LF
1% 1/16W
402
3.01K
R8953
1
2
330PF
10% CERM
50V 402
C8952
1
2
50V
330PF
10%
402
CERM
C8950
12
50V CERM 402
10%
0.001UF
C8920
1
2
CRITICAL
QFN
ISL6263C
U8900
30
17
5
6
32
10
28
11
13
21
3
20
31
19
22
1
9
2
33
18
16
7
23 24
25
26 27
14
12
29
8
15
4
PLACE_NEAR=U8900.15:2mm
PLACE_NEAR=U8900.33:2mm
SM
XW8900
1 2
402
50V
10% CERM
680pF
C8953
1
2
1%
MF-LF
1/16W
402
7.15K
R8909
1
2
50V
10%
402
X7R
0.001UF
C8922
1
2
402
50V
10%
0.001UF
CERM
C8923
1
2
8
73 86 87
0.001UF
50V
10% 402
CERM
C8921
1
2
10
1/16W
1%
MF-LF
402
R8904
1 2
1/16W
1%
402
MF-LF
150K
R8905
2 1
0.033UF
16V
10%
402
X5R
C8904
12
X5R
10V
10% 402
1uF
C8901
1
2
1
5%
402
1/16W MF-LF
R8911
1 2
X5R-CERM
402
20%
2.2UF
10V
C8902
1
2
CERM 402
0.01uF
16V
10%
C8903
1
2
402
0.001UF
CERM
50V
10%
C8972
1
2
5%
68PF
50V
402-1
CERM
C8971
1 2
MF-LF
9.76K
402
1%
1/16W
R8902
2
1
9.09K
402
1% MF-LF
1/16W
R8901
1
2
X7R 603
0.22UF
10% 16V
C8956
1
2
6.3V
20%
603
X5R
10UF
C8965
1
2
10UF
6.3V
20% 603
X5R
C8966
1
2
2.0V
20% D2T-SM2
POLY-TANT
330UF
CRITICAL
C8943
1
23
402
1/16W
5%
1K
MF-LF
R8930
1
2
POLY-TANT
D3L
68UF
16V
20%
CRITICAL
C8930
1
2
25V
10% 603-1
X5R
1UF
C8932
1
2
25V
10%
603-1
X5R
1UF
C8933
1
2
MF-LF
402
1%
1/16W
1K
R8903
1
2
5%
402
COG
330PF
50V
C8906
1
2
2.0V
20%
POLY-TANT
330UF
CRITICAL
D2T-SM2
C8942
1
2 3
6.3V 603
X5R
20%
10UF
C8968
1
2
10%
4.7UF
X5R-CERM
6.3V 603
C8967
1
2
0
1/16W MF-LF
402
5%
R8994
1 2
GPUVID2_0
1/16W
5%
402
MF-LF
2.2K
R8983
1
2
1/16W
GPUVID2_1
5%
2.2K
402
MF-LF
R8982
1
2
GPUVID1_1
2.2K
402
5% 1/16W MF-LF
R8984
1
2
GPUVID1_0
402
MF-LF
2.2K
5%
1/16W
R8985
1
2
79 80
MF-LF
1/16W
5%
402
0
R8990
1 2
79 80
73 87
0
402
5% 1/16W MF-LF
R8986
12
10% 402
0.001UF
50V X7R
C8934
1
2
X7R
0.001UF
50V
10% 402
C8969
1
2
79 80
GPUVID0_1
402
MF-LF
5%
2.2K
1/16W
R8987
1
2
100
1% 1/16W MF-LF
402
R8924
1
2
MF-LF
100
1%
1/16W
402
R8925
12
79 80
0
402
MF-LF
1/16W
5%
R8998
1 2
402
0
1/16W MF-LF
5%
R8993
21
2.2K
GPUVID4_1
1/16W MF-LF
5%
402
R8991
1
2
GPUVID4_0
5%
2.2K
402
1/16W MF-LF
R8992
1
2
GPUVID0_0
2.2K
402
5%
MF-LF
1/16W
R8988
1
2
50
1%
0.001
1W
MF-1
CRITICAL
0612
R8940
12 34
MF-LF
1/16W
402
7.32K
1%
R8900
1 2
CRITICAL
0.56UH-31A
FDU1040D-SM
L8920
1 2
CRITICAL
CSD58856Q5A
MLP5X6-LFPAK-Q5A
Q8950
5
4
1 2 3
CRITICAL
MLP5X6-LFPAK-Q5
CSD58857Q5
Q8951
5
4
1 2 3
TANT
16V
20%
15UF
SM
CRITICAL
C8931
1
2
TANT
16V
20%
15UF
SM
CRITICAL
C8935
1
2
79 80
MF-LF
402
GPUVID3_1
1/16W
5%
2.2K
R8995
1
2
GPUVID3_0
402
1/16W MF-LF
5%
2.2K
R8996
1
2
GPUVID_0P82V
GPUVID4_1,GPUVID3_0,GPUVID2_0,GPUVID1_1,GPUVID0_0
GPUVID4_1,GPUVID3_0,GPUVID2_1,GPUVID1_0,GPUVID0_1
GPUVID_0P75V
GPUVID_0P90V
GPUVID4_0,GPUVID3_1,GPUVID2_1,GPUVID1_1,GPUVID0_1
GPU (GT216) CORE SUPPLY
SYNC_DATE=07/14/2009
SYNC_MASTER=K18_POWER
PP3V3_S0GPU
GPU_VCORE_VID2
GPU_VCORE_VID3
GFXIMVP6_VDIFF
MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM
GPU_VCORE_VID1
GPU_VCORE_VID0
GPU_VCORE_VID4
MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM VOLTAGE=5V
PP5V_S3_GFXIMVP6_VDD
PPBUS_G3H
MIN_LINE_WIDTH=0.6MM
DIDT=TRUE
SWITCH_NODE=TRUE
GFXIMVP6_PHASE
MIN_NECK_WIDTH=0.2MM
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.3MM
GFXIMVP6_VIN
MIN_LINE_WIDTH=0.3MM
GFXIMVP6_FB
MIN_NECK_WIDTH=0.2MM
GFXIMVP6_DFB
MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM
GFXIMVP6_VID2
GPU_VDD_SENSE
MIN_LINE_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.20 mm VOLTAGE=1.25V
PPVCORE_GPU
MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM
GFXIMVP6_RBIAS
GFXIMVP6_VID0 GFXIMVP6_VID1
GFXIMVP6_SOFT
MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM
PPVCORE_GPU
GFXIMVP6_VID3
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.3MM
GFXIMVP6_DROOP
PM_ALL_GPU_PGOOD
GFXIMVP6_VID4
GPU_GND_SENSE
MIN_LINE_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.20 mm VOLTAGE=0V
MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.3MM
GFXIMVP6_VDIFF_RC
GFXIMVP6_IMON
GFXIMVP6_VSUM
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.3MM
PPVCORE_GPU_REG_R
MIN_LINE_WIDTH=0.6MM VOLTAGE=1.2V
MIN_NECK_WIDTH=0.2MM
GFXIMVP6_LGATE
MIN_LINE_WIDTH=0.6MM
DIDT=TRUE
GATE_NODE=TRUE
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.3MM
GFXIMVP6_OCSET
MIN_NECK_WIDTH=0.2MM
GFXIMVP6_FDE
GFXIMVP6_AF_EN
PP3V3_S0GPU
GFXIMVP6_VSEN_P
MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM
GFXIMVP6_VW
MIN_NECK_WIDTH=0.3MM
MIN_LINE_WIDTH=0.3MM
GFXIMVP6_COMP_RC
MIN_NECK_WIDTH=0.2MM
DIDT=TRUE
MIN_LINE_WIDTH=0.3MM
GFXIMVP6_BOOT
MIN_NECK_WIDTH=0.3MM
MIN_LINE_WIDTH=0.3MM
GFXIMVP6_PHASE_VSUM
MIN_LINE_WIDTH=0.6MM
GATE_NODE=TRUE
DIDT=TRUE
MIN_NECK_WIDTH=0.2MM
GFXIMVP6_UGATE
GFXIMVP6_VSEN_N
VOLTAGE=0V
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.6MM
GND_GFXIMVP6_AGND
MIN_LINE_WIDTH=0.3MM
GFXIMVP6_COMP
MIN_NECK_WIDTH=0.2MM
PP5V_S3
GFXIMVP6_VID1 GFXIMVP6_VID2 GFXIMVP6_VID3 GFXIMVP6_VID4
GFXIMVP6_VID0
EG_RAIL3_EN
MIN_LINE_WIDTH=0.3MM
GFXIMVP6_VO
MIN_NECK_WIDTH=0.2MM
PP5V_S3_GFXIMVP6_PVCC
MIN_LINE_WIDTH=0.3MM VOLTAGE=5V
MIN_NECK_WIDTH=0.2MM
89 OF 132
<E4LABEL>
<SCH_NUM>
<BRANCH>
82 OF 101
6 7
72 74 79 80 81 82 84
6 7
40 49 65 66 67 69 70 86
89
82
74
6 7
49 75 82
82
82
6 7
49 75 82
82
82
74
6 7
72 74 79
80 81
82 84
6 7
31
33 42 43
44 46 54
56 58 61
66 67 72
101
82
82
82
82
82
Page 83
IN
SYM_VER-1
SYM_VER-1
NC
NC
GND
THRM
ON
VIN_1
VIN_2
VOUT_1
VOUT_2
PAD
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
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PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
LCD (LVDS) INTERFACE
518S0651
Place close to the connector
Place close to the connector
no-panel case (development).
Panel has 2K pull-ups
100K pull-ups are for
X7R 402
10% 50V
0.001UF
C9010
1
2
0.1UF
X5R 402
10% 16V
C9001
1
2
SM
FERR-250-OHM
CRITICAL
L9000
1 2
MF-LF
1/16W
5%
10K
402
R9094
1
2
100K
MF-LF
5% 1/16W
402
R9011
1
2
MF-LF
402
5%
1/16W
100K
R9010
1
2
87
90-OHM-100MA
CRITICAL
DLP11S
L9010
1 2
34
DLP11S
CRITICAL
90-OHM-100MA
L9011
1 2
34
CRITICAL
20474-040E-11
F-RT-SM
J9000
1
10 11 12 13 14 15 16 17 18 19
2
20 21 22 23 24 25 26 27 28 29
3
30 31 32 33 34 35 36 37 38 39
4
40
41 42
43 44
5 6 7 8 9
0.001UF
X7R 402
10% 50V
C9002
1
2
0.1UF
X5R
16V 402
10%
C9009
1
2
CRITICAL
FPF1009
MFET-2X2
U9000
617
2
3
4
5
0.1UF
10% X5R
16V 402
C9011
1
2
10UF
20%
6.3V X5R 603
C9012
1
2
402
50V
CERM
0.001UF
10%
C9000
1
2
SYNC_MASTER=K19_MLB
SYNC_DATE=05/29/2009
LVDS Display Connector
PPVOUT_S0_LCDBKLT
LCD_PWR_EN
PP3V3_S5
VOLTAGE=3.3V
MIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.5 mm
PP3V3_SW_LCD_UF
LVDS_CONN_B_CLK_F_N
LVDS_CONN_A_CLK_N
LVDS_CONN_B_CLK_N
LVDS_CONN_B_CLK_P
LVDS_CONN_A_CLK_P
LVDS_CONN_B_DATA_N<1>
LVDS_CONN_B_DATA_N<2> LVDS_CONN_B_DATA_P<2>
LVDS_CONN_A_DATA_N<0>
LVDS_CONN_B_DATA_N<0>
LVDS_CONN_A_DATA_P<2>
LVDS_CONN_A_DATA_N<1>
LVDS_CONN_B_DATA_P<1>
LVDS_CONN_B_DATA_P<0>
LVDS_CONN_A_CLK_F_P
LVDS_CONN_A_DATA_N<2>
LVDS_CONN_A_DATA_P<1>
LVDS_CONN_A_DATA_P<0>
LVDS_CONN_B_CLK_F_P LED_RETURN_6 LED_RETURN_5 LED_RETURN_4 LED_RETURN_3 LED_RETURN_2 LED_RETURN_1
LVDS_DDC_CLK LVDS_DDC_DATA
LVDS_CONN_A_CLK_F_N
PP3V3_S0
PP3V3_SW_LCD
VOLTAGE=3.3V
MIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.5 mm
90 OF 132
<E4LABEL>
<SCH_NUM>
<BRANCH>
83 OF 101
6
56 88
6 7
17 18 19 20 21 23 27 31
35 57 66 71 72 73 85 99
6
98
84 98
84 98
84 98
84 98
6
84 98
6
84 98
6
84 98
6
84 98
6
84 98
6
84 98
6
84 98
6
84 98
6
84 98
6
98
6
84 98
6
84 98
6
84 98
6
98
6
88
6
88
6
88
6
88
6
88
6
88
6
84
6
84
6
98
6 7
17 18 19 20 21 23 24 25
26 27 28 30 34 37 40 42 46 47
48 50 51 52 54 58 62 63 68
69 72 73 80 84 85 87 88 99
6
Page 84
IN IN
IN
IN
IN
IN
IN
IN
BI
IN
OUT
OUT OUT
OUT
OUT
OUT
OUT
OUT
OUT
BI
BI
IN
BI
BI
IN
IN
IN
IN
IN
IN
IN IN
BI BI
IN
OUT
BI
IN
IN
XSD*
HPD_1
DIN1_0-
DIN1_1+
DIN1_2-
DAUX1+
DIN1_3+
DDC_DAT2
DAUX2-
DDC_CLK2
HPD_2
GPU_SEL
TST0
DIN1_2+
DIN1_1-
DOUT_0-
DOUT_1+ DDC_CLK1 DDC_DAT1
DOUT_2+
DOUT_2-
DOUT_3+
DOUT_3-
DIN2_1+
DDC_AUX_SEL
DIN2_1-
AUX+ AUX-
HPDIN
DIN2_2+ DIN2_2-
DIN2_3+ DIN2_3-
DAUX2+
DIN2_0-
DIN2_0+
DIN1_0+
DAUX1-
DOUT_1-
DOUT_0+ DIN1_3-
VDD
GND
OUT
VCC
C1
C2
C3
C4
A1 B1
A2 B2
A3 B3
A4 B4
GND
THRM
IN
IN
OUT
IN
IN
BI
BI BI
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
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DRAWING NUMBER
SIZE
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R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
LVDS Transmitter Termination
All emulated LVDS outputs require this termination
LVDS DDC MUX
LO=PORT1 HI=PORT2
DisplayPort Mux
HI=DDC
LO=AUX_CH
8
93
8
93
8
93
8
93
8
93
8
93
8
93
8
93
8
18 80
8
18 80
8
18
85 98
85 98
85 98
85 98
85 98
85 98
85 98
85 98
85 98
85 98
80 85 87
0.1uF
X5R 40210% 16V
C9330
1 2
0.1uF
X5R 40210% 16V
C9331
1 2
8
18 93
8
18 93
10V
20% 402
CERM
0.1UF
C9320
1
2
81 98
81 98
81 98
81 98
81 98
81 98
0.1uF
X5R 40210% 16V
C9335
1 2
X5R10% 402
0.1uF
16V
C9336
1 2
81 98
81 98
81 98
81 98
80 81
79 80
80 81
84 85 87
87
10V
20% 402
CERM
0.1UF
C9321
1
2
CRITICAL
BGA
CBTL06141EE
U9320
H1
H2
J9
H9
J6
H6
C2
H8
H5
J8
J5
A4
B4
A5
B5
A6
B6
A9
A8
B9
B8
D9
D8
E9
E8
F9
F8
B1
B2
D1
D2
E1
E2
F1
F2
B3C8G8H4H7
A1
J2
H3
J1
G2
A2
J4
B7
84 85 87
CRITICAL
QFN1
SN74LV4066A
U9370
1
4
8
11
2
3
9
10
13
5
6
12
7
15
14
87
87
6
83
80 81
18
80 81
18
6
83
20%
0.1UF
402
CERM
10V
C9370
1
2
20K
402
MF-LF
1/16W
5%
R9373
1
2
5%
1/16W
402
MF-LF
20K
R9372
1
2
87
1%
10K
MF-LF
402
1/16W
DPMUX_EN_S0&DPMUX_EN_PLD
R9302
1
2
5%
0
MF-LF
402
1/16W
DPMUX_EN_PLD
R9303
1 2
DPMUX_EN_HPD
1%
10K
1/16W
402
MF-LF
R9301
1
2
87 98
87 98
87 98
87 98
87 98
87 98
87 98
87 98
87 98
87 98
87 98
87 98
87 98
PLACE_NEAR=U9600.A5:7mm
1%
MF-LF
402
1/16W
357
R9357
1 2
PLACE_NEAR=U9600.B3:7mm
1%
402
MF-LF
1/16W
357
R9352
1 2
PLACE_NEAR=U9600.C5:7mm
1%
402
MF-LF
1/16W
357
R9355
1 2
PLACE_NEAR=U9600.A1:7mm
1%
402
MF-LF
1/16W
357
R9350
1 2
PLACE_NEAR=U9600.A3:7mm
1%
402
MF-LF
1/16W
357
R9347
1 2
PLACE_NEAR=U9600.C9:7mm
1%
402
MF-LF
1/16W
357
R9342
1 2
PLACE_NEAR=U9600.A2:7mm
1%
402
MF-LF
1/16W
357
R9345
1 2
PLACE_NEAR=U9600.C8:7mm
357
1/16W MF-LF
402
1%
R9340
1 2
PLACE_NEAR=U9600.A10:7mm
357
1/16W MF-LF
402
1%
R9337
1 2
PLACE_NEAR=U9600.C10:7mm
402
MF-LF
1/16W
1%
357
R9332
1 2
PLACE_NEAR=U9600.B10:7mm
MF-LF
357
402
1/16W
1%
R9335
1 2
PLACE_NEAR=U9600.A9:7mm
357
402
MF-LF
1/16W
1%
R9330
1 2
PLACE_NEAR=U9600.B9:7mm
357
402
MF-LF
1/16W
1%
R9327
1 2
87 98
87 98
87 98
PLACE_NEAR=U9600.A7:7mm
357
1%
1/16W
402
MF-LF
R9322
1 2
PLACE_NEAR=U9600.A8:7mm
357
1%
MF-LF
402
1/16W
R9325
1 2
PLACE_NEAR=U9600.A6:7mm
MF-LF
357
1%
1/16W
402
R9320
1 2
DPMUX_EN_HPD
402
CERM-X5R
6.3V
10%
1UF
C9301
1
2
83 98
83 98
6
83 98
6
83 98
6
83 98
6
83 98
6
83 98
6
83 98
83 98
83 98
6
83 98
6
83 98
6
83 98
6
83 98
6
83 98
6
83 98
5%
100K
1/16W
402
MF-LF
R9305
1
2
5%
100K
1/16W
402
MF-LF
R9304
1
2
1K
5%
MF-LF
402
1/16W
PLACE_NEAR=U9320.J1:3mm
R9307
1 2
5% MF-LF
1/16W 402
20K
R9371
1
2
5%
20K
MF-LF
402
1/16W
R9370
1
2
Muxed Graphics Support
SYNC_DATE=06/15/2009
SYNC_MASTER=K17_REF
DP_CA_DET
LVDS_A_DATA_P<2>
LVDS_CONN_B_DATA_N<2>
LVDS_CONN_B_DATA_P<2>
LVDS_CONN_B_DATA_N<1>
LVDS_CONN_B_DATA_P<1>
LVDS_CONN_B_DATA_N<0>
LVDS_CONN_B_DATA_P<0>
LVDS_CONN_B_CLK_N
LVDS_CONN_B_CLK_P
LVDS_CONN_A_DATA_N<2>
LVDS_CONN_A_DATA_N<1>
LVDS_CONN_A_DATA_P<1>
LVDS_CONN_A_CLK_N
LVDS_B_CLK_N
LVDS_B_CLK_P
LVDS_B_DATA_N<2>
LVDS_A_DATA_P<1>
LVDS_B_DATA_P<2>
DP_EG_AUX_CH_P DP_EG_AUX_CH_N
DP_MUX_SEL_EG
PP3V3_S0
DP_MUX_EN
DP_MUX_XSD_L
DP_IG_ML_N<3>
DP_IG_ML_P<3>
DP_EG_ML_P<1>
DP_HOTPLUG_DET
MAKE_BASE=TRUE
LVDS_EG_DDC_DATA
LVDS_DDC_DATA
LVDS_DDC_SEL_IG
LVDS_A_DATA_N<1>
LVDS_B_DATA_N<1>
LVDS_A_CLK_N
DP_EG_AUX_CH_C_P
DP_IG_AUX_CH_C_P
DP_ML_N<0>
DP_ML_P<1> DP_ML_N<1>
DP_EG_ML_P<0> DP_EG_ML_N<0>
PP3V3_S0
LVDS_EG_DDC_CLK
LVDS_IG_DDC_CLK
LVDS_DDC_SEL_EG
LVDS_IG_DDC_DATA
LVDS_DDC_CLK
PP3V3_S0GPU
DP_ML_P<0>
DP_HPD_R
DP_IG_ML_P<0>
DP_IG_ML_P<1>
DP_IG_ML_P<2>
PP3V3_S0
DP_HOTPLUG_DET
DP_EG_ML_N<2>
DP_EG_ML_N<1>
DP_IG_DDC_CLK
DP_IG_AUX_CH_C_N
LVDS_B_DATA_P<1>
LVDS_B_DATA_N<0>
LVDS_B_DATA_P<0>
LVDS_A_DATA_N<0>
LVDS_A_DATA_P<0>
DP_ML_P<3>
DP_ML_N<2>
DP_ML_N<3>
DP_AUX_CH_C_P DP_AUX_CH_C_N
DP_EG_ML_P<3>
DP_IG_ML_N<2>
DP_IG_ML_N<1>
DP_IG_ML_N<0>
DP_ML_P<2>
DP_EG_DDC_DATA
DP_EG_DDC_CLK
DP_EG_AUX_CH_C_N
DP_EG_ML_N<3>
DP_EG_ML_P<2>
DP_IG_HPD
DP_IG_DDC_DATA
DP_IG_AUX_CH_P
DP_EG_HPD
LVDS_A_CLK_P
LVDS_A_DATA_N<2>
DP_IG_AUX_CH_N
LVDS_CONN_A_DATA_P<2>
LVDS_CONN_A_DATA_N<0>
LVDS_CONN_A_DATA_P<0>
LVDS_CONN_A_CLK_P
93 OF 132
<E4LABEL>
<SCH_NUM>
<BRANCH>
84 OF 101
6 7
17 18 19 20 21 23 24 25
26 27 28 30 34 37 40 42 46 47
48 50 51 52 54 58 62 63 68
69 72 73 80 83 84 85 87 88
99
98
99
6 7
17 18 19 20 21 23 24 25
26 27 28 30 34 37 40 42 46 47
48 50 51 52 54 58 62 63 68 69
72 73 80 83 84 85 87 88 99
6 7
72 74 79 80 81 82
6 7
17 18 19 20 21 23 24 25
26 27 28 30 34 37 40 42 46 47
48 50 51 52 54 58 62 63 68 69
72 73 80 83 84 85 87 88 99
99
98
Page 85
BI
IN
IN
IO NC NC
IO
GND
OUT
IO NC NC
IO
GND
IO NC NC
IO
GND
IO NC NC
IO
GND
IN
IN
IN
IN
IN
IN
G
D
S
G
D
S
SYM_VER-2
SYM_VER-2
SYM_VER-2
SYM_VER-2
OUT
G
D
S
G
D
S
BI
IN
OC*
OUT
EN
GND
IN
GND
GND
ML_LANE0N
ML_LANE0P
ML_LANE1P
GND
ML_LANE1N
GND
GND
DP_PWR
ML_LANE2P
AUX_CHP
RETURN
HOT_PLUG_DETECT
AUX_CHN
ML_LANE3P ML_LANE3N
ML_LANE2N
CONFIG1 CONFIG2
BOT ROW TOP ROW
TH PINS SM PINS
SHIELD PINS
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
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SHEET
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A
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PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
Port Power Switch
Q9440 must have Drain to Gate leakage of <500nA and Gate to Source resistance of >5MOhm
pull-up to DP_PWR.
(CA) has 100k
Cable Adapter
DP to DVI/HDMI
to 100K (DPv1.1a).
greater than or equal
down HPD input with
DP Source must pull
84 98
84 98
84 98
MF-LF
100K
1/16W
5%
402
R9421
1
2
RCLAMP0524P
CRITICAL
SLP2510P8
DP_ESD
D9411
3
2 1 9
10
40216V
0.1uF
X5R10%
C9415
1 2
40216V
0.1uF
X5R10%
C9414
1 2
80 84 87
0.1uF
X5R 40216V10%
C9411
1 2
0.1uF
X5R 40210% 16V
C9410
1 2
MF-LF
5%
1/16W
402
100K
R9420
1
2
RCLAMP0524P
CRITICAL
DP_ESD
SLP2510P8
D9410
3
2 1 9
10
DP_ESD
SC70-6-1
CRITICAL
RCLAMP0504F
D9400
1
3
4
6
2 5
RCLAMP0524P
SLP2510P8
DP_ESD
CRITICAL
D9411
3
5 4 6 7
5%
402
1/16W
1M
MF-LF
R9425
1
2
DP_ESD
CRITICAL
SLP2510P8
RCLAMP0524P
D9410
3
5 4 6 7
X5R 40210% 16V
0.1uF
C9417
1 2
0.1uF
X5R 40210% 16V
C9416
1 2
0.1uF
X5R 40210% 16V
C9413
1 2
X5R 40210% 16V
0.1uF
C9412
1 2
84 98
84 98
84 98
84 98
0.01UF
CERM 603
50V
20%
C9400
1
2
0603
FERR-120-OHM-3A
L9400
1 2
84 98
84 98
SOT-363
2N7002DW-X-G
Q9440
3
5
4
SOT-363
2N7002DW-X-G
Q9440
6
2
1
100K
MF-LF
402
1/16W
5%
R9443
1
2
MF-LF
100K
402
1/16W
5%
R9442
1
2
12-OHM-100MA
TCM1210-4SM
CRITICAL
FL9403
1
23
4
TCM1210-4SM
12-OHM-100MA
CRITICAL
FL9402
1
2 3
4
12-OHM-100MA
TCM1210-4SM
CRITICAL
FL9401
1
2 3
4
TCM1210-4SM
12-OHM-100MA
CRITICAL
FL9400
1
2 3
4
0
1/16W
5% 402
MF-LF
NO STUFF
R9403
1 2
NO STUFF
5% 402
MF-LF
0
1/16W
R9413
1 2
0
1/16W
5% 402
MF-LF
NO STUFF
R9402
1 2
0
1/16W
5% 402
MF-LF
NO STUFF
R9432
1 2
MF-LF
5%
0
402
1/16W
NO STUFF
R9401
1 2
NO STUFF
5%
0
MF-LF
402
1/16W
R9431
1 2
0
1/16W
5% 402
MF-LF
NO STUFF
R9400
1 2
NO STUFF
MF-LF
4025%
1/16W
0
R9430
1 2
84 87
2N7002DW-X-G
SOT-363
Q9441
6
2
1
2N7002DW-X-G
SOT-363
Q9441
3
5
4
5%
MF-LF
402
1/16W
1M
R9422
1
2
10K
MF-LF
402
1/16W
5%
R9445
1
2
10K
MF-LF
5%
402
1/16W
R9444
1
2
5%
MF-LF
1/16W
402
100K
R9423
1
2
6.3V
20% X5R
10UF
603
C9480
1
2
0.1UF
402
CERM
10V
20%
C9481
1
2
84 98
20% X5R-CERM
6.3V 603
22UF
CRITICAL
C9486
1
2
0.1UF
CERM
20% 10V
402
C9485
1
2
TPS2051B
SOT23
CRITICAL
U9480
4
2
5
3
1
6
18 31 45 73
CRITICAL
100UF
POLY-TANT
20%
6.3V CASE-B2-SM
C9487
1
2
DSPLYPRT-M97-1
CRITICAL
F-RT-THSM
J9400
18
16
4 6
20
1
78
1314
2
2122
5
3
11
9
17
15
12
10
19
SYNC_DATE=06/15/2009
SYNC_MASTER=K17_REF
DisplayPort Connector
DP_ML_CONN_N<0>
DP_ML_CONN_P<0>
DP_ML_CONN_P<1>
DP_ML_CONN_N<1>
PP3V3_S0_DPPWR
MIN_LINE_WIDTH=0.38 MM VOLTAGE=3.3V
MIN_NECK_WIDTH=0.20 MM
DP_ML_CONN_P<2>
DP_AUX_CH_C_P
DP_HPD_Q
DP_AUX_CH_C_N
DP_ML_CONN_P<3>
DP_ML_CONN_N<3>
DP_ML_CONN_N<2>
DP_CA_DET_Q
HDMI_CEC
DP_ML_C_N<1>
TP_DPPWR_OC_L
DP_HOTPLUG_DET
DP_HPD_L_Q
DP_ML_C_P<1>
DP_ML_C_P<0>
DP_ML_C_N<0>
DP_ML_C_P<2>
DP_ML_C_N<2>
DP_ML_P<3>
DP_ML_N<2>
DP_ML_P<2>
DP_ML_N<1>
DP_ML_P<1>
DP_ML_N<0>
DP_ML_P<0>
PP3V3_S0
DP_CA_DET_L_Q
DP_CA_DET
DP_ML_N<3>
DP_ML_C_P<3>
PP3V3_S0
DP_ML_C_N<3>
PM_SLP_S3_L
PP3V3_S5
PP3V3_S0_DPILIM
MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=3.3V
94 OF 132
<E4LABEL>
<SCH_NUM>
<BRANCH>
85 OF 101
98
98
98
98
98
98
98
98
98
98
98
98
98
98
6 7
17 18 19 20 21 23 24 25
26 27 28 30 34 37 40 42
46 47 48 50 51 52 54 58
62 63 68 69 72 73 80 83
84 85 87 88 99
98
6 7
17 18 19 20 21 23 24 25
26 27 28 30 34 37 40
42 46 47 48 50 51 52
54 58 62 63 68 69 72
73 80 83 84 85 87 88
99
98
6 7
17 18 19 20 21 23 27 31
35 57 66 71 72 73 83 99
Page 86
OUT
IN
THRM
GND
G
PG
SHDN*
D
VCC
S
ON
PAD
OUT
IN
D
G S
PGOOD
DRVH
DRVL
SW
VFB
TRIP
VBST
THRM
EN
TRAN
V5IN
PAD
S
D
G
IN
D1
G1
S2
G2
S1/D2
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
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A
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Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
TABLE_5_ITEM
TABLE_5_ITEM
CRITICAL BOM OPTION
TABLE_5_HEAD
PART#
DESCRIPTION
QTY
REFERENCE DESIGNATOR(S)
1V8 / 1V55 / 1V35 S0 FRAMEBUFFER REGULATOR
353S2739
152S0518
f = 340 kHz
Vout = 1.806V
(Q9560 limit?)
(GND)
376S0827
LOADING
3.83 A (EDP)
7A max output
(FB_1V8_S0_VFB)
RDS(ON)
CHANNEL
MOSFET
1.05V FB FET
N-TYPE
AON6400L
1.8 mOhm @4.5V
1.80 V
FB VDD
FBVDD_ALTVO 0
1
Regulator Output
1.35 / 1.55 V
1V05 S0 GPU FET
1UF
25V 603-1
X5R
10%
C9595
1
2
8
73 82 86 87
50V X7R 603-1
10%
FB_1V8_S0_VBST_RC
0.1UF
C9580
1
2
1/16W MF-LF
5%
0
402
R9580
1 2
20%
10UF
X5R
10V 603
1
2
C9501
72 73 87
PLACE_NEAR=U9500.2:3mm
40.2K
1% 1/16W MF-LF 402
R9585
1
2
0.1UF
20% 10V
CERM
402
C9550
1
2
CRITICAL
TDFN
SLG5AP020
U9550
5
7
4
2
8
6
3
9
1
CRITICAL
2.0V
POLY-TANT
330UF
B2-SM
20%
C9560
1
2
8
73 82 86 87
73 87
402
5%
1K
MF-LF
R9587
2
1/16W
1
FB1V55
51.1K
1% 1/16W MF-LF 402
R9589
1
2
SOD-VESM-HF
SSM3K15FV
Q9581
3
1
2
CASE-D2E-SM
16V
POLY-TANT
68UF
20%
CRITICAL
C9590
1
2
TPS51217
CRITICAL
DSC
U9500
9
6
3 1
8
11
5
2
7
10
4
AON6400L
DFN5X6
CRITICAL
Q9550
5
4
1 2 3
402
50V
5%
CERM
47PF
C9586
1
2
1K
5% 1/16W MF-LF 402
R9586
1
2
25V NP0-C0G 402
5%
1000PF
C9570
1
2
6.3V
20% 603
X5R
10UF
C9565
1
2
MF-LF
1/16W 402
20.5K
1%
R9571
1
2
79 80
RJK0384DPA
WPAK
CRITICAL
Q9560
2
1
6
7
345
PLACE_NEAR=L9560.2:3mm
SM
XW9565
1
2
2.2UH-8.0A
PCMB065T-SM
CRITICAL
L9560
1 2
13K
FB1V55
402
1% MF-LF
1/16W
R9588
1
2
FB1V35
1
R9588
114S0336
RES,1/16W,16.9K,1%,0402,LF
FB1V35
1
R9589
114S0357
RES,1/16W,27.4K,1%,0402,LF
SYNC_DATE=06/26/2009
SYNC_MASTER=K18_POWER
1V8 / 1V55 FB Power Supply
PP1V05_S0
FBVDD_ALTVO
PM_ALL_GPU_PGOOD
EG_RAIL1_EN
PM_ALL_GPU_PGOOD
FB_1V8_S0_VFB_R
PP5V_S0
FB_1V8_S0_TRAN_R
FB_1V8_S0_TRAN
EG_RAIL4_EN
PP1V8R1V55_S0GPU_ISNS_R
FB_1V8_S0_VFB_XW
MIN_LINE_WIDTH=0.6 mm
FB_1V8_S0_VBST
MIN_NECK_WIDTH=0.2 mm
P1V05_FB_GATE
PP1V05_S0GPU
PPBUS_G3H
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.6MM
DIDT=TRUE
FB_1V8_S0_DRVH
GATE_NODE=TRUE
MIN_NECK_WIDTH=0.2MM
GATE_NODE=TRUE
MIN_LINE_WIDTH=0.6MM
FB_1V8_S0_DRVL
DIDT=TRUE
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM
SWITCH_NODE=TRUE
FB_1V8_S0_LL
DIDT=TRUE
FB_1V8_S0_TRIP
FB_1V8_S0_VFB
P1V8FB_EN_R
PP5V_S0
GND
95 OF 132
<E4LABEL>
<SCH_NUM>
<BRANCH>
86 OF 101
6 7
10 12 13 15 17 18 20 21
23 24 25 26 40 70 73
6 7
23 42 47 52 54 68 69 70
72 86 88
6 7
50
6 7
74 76 79 81
6 7
40 49 65 66 67 69 70 82
89
6 7
23 42 47 52 54 68 69 70
72 86 88
Page 87
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
IN IN
IN
IN
OUT
D
SG
D
SG
IN
IN
IN IN
IN
IN
IN
IN IN
IN
IN
IN
IN
PB14B PB15A PB15B PB16A
PB17A
PT19A
PT16A
PB18B
PT7A
PR11B
PR24A PR24B
PR14A PR14B
PR12B
PR12A
PR11A
PR10B
PR10A
PR6A PR6B PR7A PR7B PR8A
PR9A PR9B
PR8B
PT28A
PT8B
PT8A
PT7B
PT9A PT9B
PL25A PL25B
PL15A
PL14B
PL14A
PL12B
PL11B PL12A
PL9A
PL8A PL8B
PL6B
PL7B
PL7A
PL6A
PB28B
PB27A
PB28A
PB27B
PB26A
PB7B
PB7A
VCCIO2
PT17B
PT17A
PT16B
PT15A
PT14B
PT20B
PT19B
CFG0
GND
GNDIO0
GNDIO1
GNDIO2
GNDIO3
GNDIO4
GNDIO5
GNDIO6
GNDIO7
LRC_GNDPLL
LRC_VCCPLL
PB18A
PB19A PB19B PB20A PB20B
PL2A PL2B
PR2A PR2B
PT14A
PT15B
PT18B
PT20A
TCK TDI TDO TMS TOE
ULC_GNDPLL
ULC_VCCPLL
VCCAUX
VCCIO0
VCCIO1
VCCIO3
VCCIO4
VCCIO5
VCCIO6
VCCIO7
VCCJ
PT18A
VCC
PT28B
PB26B
PL11A
PL10B
PL10A
PL9B
PB16B
PL15B
PB14A
PB17B
BANK6
BANK2 BANK0
BANK5 BANK7BANK4
BANK3 BANK1
(OD)
(OD)
IN
IN
OUT
IN
BI BI
BI
BI
BI
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
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REVISION
DRAWING NUMBER
SIZE
D
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SHEET
PAGE TITLE
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Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
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345678
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8 7 5 4 2 1
GMUX CPLD
LVDS Receiver Termination
(Use open-drain PGOOD output to hold off the start of the GPU PWRSEQ until the first GPU rail’s source is valid)
Required Pulldowns
(Tie/strap low if EGPU doesn’t provide CLKREQ_L output, provide pullup to GPU rail if using CLKREQ_L output from EGPU)
Required Pullups
81 87 98
84 85
80 84 85
84 98
84 98
84 98
84 98
84 98
84 98
84 98
4V X5R 402
4.7UF
20%
C9600
1
2
84 98
84 98
84 98
87
87
84 98
84 98
84 98
84 98
84 98
402
10K
1% 1/16W MF-LF
NO STUFF
R9670
1
2
84 98
MF-LF
402
1/16W
5%
100K
R9693
1 2
NO STUFF
5% 402
MF-LF1/16W
100K
R9691
1 2
5%
1/16W MF-LF
10K
402
R9683
1 2
MF-LF
4025%
10K
1/16W
R9682
1 2
8
73 82 86
1/16W MF-LF
10K
5% 402
R9681
1 2
1K
5% 402
MF-LF1/16W
R9680
1 2
402
CERM
20% 10V
0.1UF
C9630
1
2
0.1UF
CERM
10V 402
20%
C9631
1
2
PLACE_NEAR=U9600.H12:5mm
SIGNAL_MODEL=EMPTY
100
402
1%
MF-LF1/16W
R9666
1 2
PLACE_NEAR=U9600.G13:5mm
100
402
MF-LF1/16W
1%
SIGNAL_MODEL=EMPTY
R9665
1 2
PLACE_NEAR=U9600.G14:5mm
402
100
MF-LF1/16W
1%
SIGNAL_MODEL=EMPTY
R9664
1 2
PLACE_NEAR=U9600.F12:5mm
1/16W MF-LF
100
402
1%
SIGNAL_MODEL=EMPTY
R9663
1 2
8
74
100
402
MF-LF1/16W
1%
SIGNAL_MODEL=EMPTY
PLACE_NEAR=U9600.B2:5mm
R9656
1 2
PLACE_NEAR=U9600.E14:5mm
100
402
MF-LF1/16W
1%
SIGNAL_MODEL=EMPTY
R9662
1 2
100
402
MF-LF1/16W
1%
SIGNAL_MODEL=EMPTY
PLACE_NEAR=U9600.D13:5mm
R9661
1 2
1%
1/16W MF-LF
402
100
SIGNAL_MODEL=EMPTY
PLACE_NEAR=U9600.J12:5mm
R9660
1 2
PLACE_NEAR=U9600.G3:5mm
100
402
MF-LF
1%
SIGNAL_MODEL=EMPTY
1/16W
R9655
1 2
PLACE_NEAR=U9600.E1:5mm
100
402
MF-LF1/16W
1%
SIGNAL_MODEL=EMPTY
R9651
1 2
PLACE_NEAR=U9600.E3:5mm
1/16W
100
402
MF-LF
1%
SIGNAL_MODEL=EMPTY
R9652
1 2
100
402
MF-LF
1%
SIGNAL_MODEL=EMPTY
1/16W
PLACE_NEAR=U9600.G1:5mm
R9653
1 2
1%
100
402
MF-LF
SIGNAL_MODEL=EMPTY
1/16W
PLACE_NEAR=U9600.G2:5mm
R9654
1 2
PLACE_NEAR=U9600.H3:5mm
100
402
MF-LF1/16W
1%
SIGNAL_MODEL=EMPTY
R9650
1 2
NO STUFF
SILK_PART=GMUX_RST
1/16W
10K
1%
MF-LF
402
R9679
1
2
27
18 87 93
402
MF-LF
5% 1/16W
4.7K
R9674
1
2
4.7K
5% MF-LF
1/16W 402
R9673
1
2
402
1/16W
5%
4.7K
MF-LF
R9672
1
2
402
1/16W
5%
4.7K
MF-LF
R9671
1
2
FERR-220-OHM
0402
L9621
1 2
0402
FERR-220-OHM
L9620
1 2
8
SSM6N15FEAPE
SOT563
Q9607
6
2
1
SOT563
SSM6N15FEAPE
Q9607
3
5
4
MF-LF
1/16W
5%
402
100K
R9676
1
2
5%
0
402
1/16W MF-LF
NO STUFF
R9675
1
2
18 87 93
4.7K
MF-LF
5%
402
1/16W
R9678
1
2
25 27 45 73
GMUX_JTAG_CONN
M-RT-SM
1909782
CRITICAL
J9600
7
8
1 2 3 4 5 6
402
MF-LF
0
5%
1/16W
R9600
1 2
402
MF-LF
1/16W
0
5%
R9610
1 2
1K
5% 402
MF-LF1/16W
R9684
1 2
18 87 93
GMUXPLL_3V3
402
MF-LF
1/16W
0
5%
R9612
1 2
GMUXPLL_1V8
402
MF-LF
1/16W
0
5%
R9611
1 2
18 87 93
18 87 93
18 87 93
18 87 93
18 87 93
18 87 93
18 87 93
18 87 93
18 87 93
18 87 93
OMIT
CRITICAL
XP25-5
CSBGA
U9600
K1
J1B8C6
C12
C13
E13
M14
N10
N6P3M2C1E2
M11
P11
P4 N4 N3 M4 P5 M5 P6 M6 P7 M7 N7 N8 P9
N9 P10 M10 P12 P13 N12 P14
P2
N2
F3
G2
H2
G3
H1
H3
L1
L3
K3
L2
N1
P1
B1
B2
C2
D3
D1
E1
D2
E3
F1
G1
G12 G13 H13 H12 H14 J12 L14 M13 N14 N13
A14 B14 D12 D13 D14 E14 E12 F12 F14 G14
B6 C7 A6 A7 C8 C9 A8 B9 A9 C10 B10 A10 A11 B12 B13 A13
A2 A3 A1 B3 C5 A5
K14 L13 K13 L12
K2
B4
A4
B11C4J3
J13
N11P8C11J2J14M8B5B7A12
C14
F13
M12M9M3N5M1C3F2
K12
18 87 93
27
20
6
27 47 94
6
17 45 47 94
6
17 45 47 94
6
17 45 47 94
6
17 45 47 94
MF-LF
1/16W
1%
10K
402
NO STUFF
R9647
1
2
6
17 45 47 94
83 87
80
8
17
72 73 86 87
73 82 87
72 73 87
73 86 87
8
74 87
84 87
84
402
CERM
10V
20%
0.1UF
C9604
1
2
0.1UF
20% CERM
402
10V
C9605
1
2
84 87
84 87
6
87 88
8
89
1%
402
NO STUFF
10K
MF-LF
1/16W
R9641
1
2
CERM
10V
0.1UF
402
20%
C9606
1
2
0.1UF
402
10V CERM
20%
C9607
1
2
CERM 402
20% 10V
0.1UF
C9608
1
2
0.1UF
20% 10V CERM 402
C9609
1
2
402
CERM
20% 10V
0.1UF
C9610
1
2
10V
20%
402
CERM
0.1UF
C9611
1
2
0.1UF
10V
20%
402
CERM
C9621
1
2
CERM
20% 10V
402
0.1UF
C9622
1
2
402
0.1UF
20% 10V CERM
C9612
1
2
402
CERM
10V
20%
0.1UF
C9613
1
2
MF-LF
1/16W
1%
402
10K
NO STUFF
R9646
1
2
0.1UF
402
20% CERM
10V
C9623
1
2
CERM
20%
402
10V
0.1UF
C9624
1
2
0.1UF
CERM
20% 10V
402
C9614
1
2
0.1UF
20% 10V CERM 402
C9625
1
2
CERM
0.1UF
10V
20%
402
C9615
1
2
0.1UF
20% 10V
402
CERM
C9616
1
2
402
CERM
0.1UF
20% 10V
C9626
1
2
20%
0.1UF
CERM
10V 402
C9627
1
2
0.1UF
CERM 402
20% 10V
C9617
1
2
10K
MF-LF
402
1%
1/16W
R9640
1
2
CERM 402
0.1UF
20% 10V
C9628
1
2
402
10V
20%
0.1UF
CERM
C9629
1
2
79 80
8
18
79 80
8
18
81 87 98
81 87 98
81 87 98
MF-LF
1% 1/16W
10K
402
R9645
1
2
81 87 98
81 87 98
81 87 98
81 87 98
81 87 98
81 87 98
81 87 98
81 87 98
81 87 98
81 87 98
SYNC_DATE=06/15/2009
Graphics MUX (GMUX)
SYNC_MASTER=K17_REF
EG_PWRSEQ_EN
PP3V3_S0
GMUX_DEBUG_RESET_L
LVDS_IG_B_DATA_N<1> LVDS_IG_B_DATA_N<2>
LVDS_EG_B_DATA_P<1> LVDS_EG_B_DATA_P<2>
LVDS_IG_A_DATA_N<0>
LVDS_IG_A_CLK_P LVDS_IG_A_CLK_N TP_LVDS_MUX_SEL_EG
GMUX_VSYNC
GMUX_VSYNC
PP3V3_S0
GMUX_PL10A
LPC_CLK33M_GMUX
LPC_AD<3>
LPC_AD<2>
LPC_AD<1>
LPC_AD<0>
LCD_PWR_EN
DP_CA_DET_EG
PEG_CLKREQ_L
GMUX_S3_PD_GND
GMUX_CFG0
LCD_BKLT_PWM
GND
ALL_SYS_PWRGD
PEX_CLKREQ_L
LVDS_IG_B_DATA_P<1>
PP3V3_S0
GMUX_RESET_L
LVDS_DDC_SEL_IG
EG_RAIL2_EN
DP_MUX_SEL_EG
LVDS_EG_A_DATA_N<2>
LVDS_B_DATA_P<1>
PP3V3_S0
LCD_BKLT_EN
GMUX_VSYNC
LVDS_EG_B_DATA_N<0>
LVDS_EG_A_DATA_P<2>
LVDS_DDC_SEL_EG
LVDS_EG_B_DATA_N<1>
LVDS_EG_B_DATA_P<0>
LVDS_DDC_SEL_EG
EG_RAIL3_EN EG_RAIL4_EN
JTAG_GMUX_TMS
DP_HOTPLUG_DET
JTAG_GMUX_TDO
JTAG_GMUX_TDI
JTAG_GMUX_TDO
EG_RESET_L
LVDS_IG_A_DATA_P<0>
LVDS_IG_B_DATA_P<1>
LVDS_IG_A_DATA_P<1> LVDS_IG_A_DATA_P<2> LVDS_IG_A_DATA_N<2>
LVDS_IG_B_DATA_P<0> LVDS_IG_B_DATA_N<0>
LVDS_IG_B_DATA_P<2>
LVDS_EG_A_CLK_P LVDS_EG_A_CLK_N
LVDS_EG_B_DATA_N<1>
LVDS_EG_B_DATA_P<0>
LVDS_IG_A_DATA_N<1>
LVDS_IG_A_CLK_N LVDS_IG_A_DATA_N<0>
LVDS_EG_A_DATA_P<1>
LVDS_EG_A_DATA_P<0>
PP3V3_S3
GMUX_S3_PD_EN
LCD_PWR_EN
LVDS_EG_B_DATA_N<2>
LVDS_EG_A_DATA_N<2>
LVDS_EG_A_DATA_N<1>
LVDS_EG_A_DATA_N<0>
LVDS_IG_A_CLK_P
LVDS_DDC_SEL_IG
LVDS_A_DATA_P<2>
LVDS_B_DATA_P<0>
LVDS_EG_B_DATA_N<2>
LVDS_IG_BKL_ON EG_BKLT_EN
LVDS_IG_PANEL_PWR EG_LCD_PWR_EN
LVDS_EG_A_CLK_N
LVDS_EG_B_DATA_P<2>
LVDS_EG_A_DATA_P<0> LVDS_EG_A_DATA_N<0>
LVDS_EG_B_DATA_N<0>
GND
LVDS_B_DATA_P<2>
LVDS_IG_B_DATA_N<1>
LVDS_IG_A_DATA_P<2>
LVDS_IG_A_DATA_P<1> LVDS_IG_A_DATA_N<1>
TP_GMUX_PL10B LVDS_IG_A_DATA_P<0>
GMUX_INT
LPC_FRAME_L LPCPLUS_RESET_L
LCD_BKLT_PWM
LVDS_A_DATA_N<0>
LVDS_B_CLK_N
GND
LVDS_A_DATA_N<2>
LVDS_IG_B_DATA_P<2> LVDS_IG_B_DATA_N<2>
DP_CA_DET
EG_PWRSEQ_EN
GND
LVDS_A_DATA_P<1>
LVDS_IG_B_DATA_N<0>
LVDS_IG_B_DATA_P<0>
LVDS_IG_A_DATA_N<2>
EG_RAIL4_EN
EG_RAIL1_EN
EG_RAIL3_EN
EG_RAIL2_EN
DP_MUX_SEL_EG
DP_MUX_EN
JTAG_GMUX_TMS
JTAG_GMUX_TDI
JTAG_GMUX_TCK
GMUX_DEBUG_RESET_L
LVDS_A_DATA_P<0>
LVDS_A_DATA_N<1>
LVDS_A_CLK_N LVDS_B_CLK_P
LVDS_EG_A_CLK_P
LVDS_EG_B_DATA_P<1>
LVDS_EG_A_DATA_N<1> LVDS_EG_A_DATA_P<2>
LVDS_EG_A_DATA_P<1>
EG_RESET_L EG_RAIL1_EN
PP3V3_S0
JTAG_GMUX_TCK
PM_ALL_GPU_PGOOD
GMUX_TOE
PP1V2_S0
PP1V8_S0
PP3V3R1V8_S0_GMUX
MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V
MIN_LINE_WIDTH=0.4 mm
PP3V3_S0
PP1V8_S0
VOLTAGE=3.3V
MIN_NECK_WIDTH=0.09 mm
MIN_LINE_WIDTH=0.4 mm
PP3V3R1V8_S0_GMUX_ULC_VCCPLL
LVDS_B_DATA_N<0>
LVDS_A_CLK_P
LVDS_B_DATA_N<1>
LVDS_B_DATA_N<2>
PP3V3R1V8_S0_GMUX_LRC_VCCPLL
MIN_NECK_WIDTH=0.09 mm
MIN_LINE_WIDTH=0.4 mm VOLTAGE=3.3V
MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.09 mm
VOLTAGE=1.8V
PP1V8_S0_GMUX_R
MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.09 mm
PP3V3_S0_GMUX_R
VOLTAGE=3.3V
96 OF 132
<E4LABEL>
<SCH_NUM>
<BRANCH>
87 OF 101
87
87
18 87 93
18 87 93
81 87 98
81 87 98
87 88
87 88
6 7
17 18 19 20 21 23 24 25
26 27 28 30 34 37 40 42 46 47
48 50 51 52 54 58 62 63 68 69
72 73 80 83 84 85 87 88 99
6
87 88
6 7
17 18 19 20 21 23 24 25 26
27 28 30 34 37 40 42 46 47 48
50 51 52 54 58 62 63 68 69 72
73 80 83 84 85 87 88 99
84 87
84 87
6 7
17 18 19 20
21 23 24 25 26 27
28 30 34 37 40 42
46 47 48 50 51 52
54 58 62 63 68 69
72 73 80 83 84 85
87 88 99
87 88
81 87 98
81 87 98
84 87
19 87
20 87
19 87
8
74 87
18 87 93
18 87 93
18 87 93
18 87 93 18 87 93
18 87 93 18 87 93
18 87 93
81 87 98 81 87 98
81 87 98
81 87 98
18 87 93
18 87 93
18 87 93
81 87 98
81 87 98
6 7 8
17
20 31 32 33 34 35 36 48 50 53 54 55 72
73
101
83 87
81 87 98
81 87 98
81 87 98
81 87 98
18 87 93
72 73 86 87
73 86 87
73 82 87
72 73 87
19 87
19 87
20 25 87
6 7
17 18 19
20 21 23 24
25 26 27 28
30 34 37 40
42 46 47 48
50 51 52 54
58 62 63 68
69 72 73 80
83 84 85 87
88 99
20 25 87
6 7
72
6 7
12 16
21 23 24 58
71 72 87
6 7
17
18 19 20
21 23
24 25 26
27 28
30 34 37
40 42
46 47 48
50 51
52 54 58
62 63
68 69 72
73 80
83 84 85
87 88
99
6 7
12 16 21 23 24 58 71 72
87
Page 88
OUT
OUT
OUT
OUT
OUT
OUT
NC
OUT1
FSET
GD
FILTER
ISET
PWM
EN
FAULT
THRM
GND_L
GND_SW
OUT6
VIN
VDDIO VLDO
FB
SW
OUT2
OUT4
OUT5
VSYNC
OUT3SCLK
SDA
GND_S
PAD
IN
IN
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER
SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
Fpwm=9.62KhZ details in spec
*PPVOUT_S0_LCDBKLT_PWR_SW SHOULD BE KEPT AS SHORT AS POSSIBLE.
* LVDS_IG_BKL_PWM SHOULD BE AWAY FROM BOOST CIRCUIT
*L9701, D9701, C9796, C9797, C9799, C9712 AND C9713 SHOULD ALL BE PLACED NEAR EACHOTHER.
R9704 SHOULD BE 47K IF RC FILTER IS USED
I_LED=369/Riset
(EEPROM should set EN_I_RES=1)
I_LED=23.2Ma
603
20%
6.3V X5R
NO STUFF
10UF
C9740
1 2
402
47.0K
1% 1/16W MF-LF
NO STUFF
R9740
1 2
10K
1/16W MF-LF
5%
402
R9741
1 2
SM
21
XW9700
1/16W
5%
0
MF-LF
402
R9757
1 2
CRITICAL
10%
805
10UF
25V X5R
C9712
1
2
X5R
10%
0.1UF
25V 402
C9713
1
2
402
X7R-CERM
220PF
10% 50V
C9796
1
2
CRITICAL
10%
10UF
X5R
50V 1210-1
C9797
1
2
CRITICAL
10%
10UF
X5R
50V 1210-1
C9799
1
2
CRITICAL
RB160M-60G
SOD-123
D9701
1 2
10.2
TF
402
0.1%
1/16W
R9722
1 2
1/16W
0.1%
402
TF
10.2
R9721
1 2
1/16W
0.1%
402
TF
10.2
R9720
1 2
6
83
6
83
5% 402
1/16W MF-LF
0
R9753
1 2
6
83
6
83
6
83
6
83
1/16W
0.1%
402
TF
10.2
R9718
1 2
1/16W
0.1%
402
TF
10.2
R9719
1 2
10.2
TF
402
1/16W
0.1%
R9717
1 2
MF-LF
402
1/16W
1%
100K
R9715
1 2
1%
402
MF-LF
301K
1/16W
R9731
1 2
10% X5R
402
25V
NO STUFF
0.1UF
C9723
1
2
25V 603-1
X5R
1UF
10%
C9710
1
2
16V X5R 402
10%
0.1UF
C9711
1
2
SM
XW9710
1 2
CRITICAL
U9701
LP8545SQX
LLP
9
11
10 14
19
17
16
13
24
21
22
8
23
18
1
15
25
7
4
2
3
20
6
5
12
90.9K
402
MF-LF
1/16W
1%
R9716
1
2
CERM
10% 16V
0.01UF
402
C9714
1
2
NO STUFF
1/16W MF-LF
0
5%
402
R9703
1
2
0
MF-LF 402
1/16W
5%
R9702
1
2
6
87
402
MF-LF
1/16W
5%
0
R9704
1 2
402
CERM
50V
5%
NO STUFF
33PF
C9704
1
2
1/16W
402
MF-LF
1%
16.2K
R9714
1
2
1/16W
402
0
5%
MF-LF
R9701
1 2
6.3V 402
10% X5R
NO STUFF
1UF
C9741
1 2
0
5% 1/16W MF-LF 402
NO STUFF
R9754
1
2
10K
5% 1/16W MF-LF 402
R9755
1
2
87
CRITICAL
IHLP2525CZ-SM
22UH-2.5A
L9701
1 2
LCD BACKLIGHT DRIVER
SYNC_DATE=07/29/2009SYNC_MASTER=K18_BKLT
PP3V3_S0
BKL_ISEN1
MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm
BKL_FSET BKL_FLTR
BKL_ISET
LVDS_BKL_PWM_RC
BKLT_EN
TP_BKL_FAULT
BKL_SGND
BKL_ISEN6
MIN_NECK_WIDTH=0.20 mm
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=5V
MIN_LINE_WIDTH=0.5 MM
PPVIN_BKL_R
BKL_VLDO
VOLTAGE=5V
MIN_NECK_WIDTH=0.2 MM
MIN_LINE_WIDTH=0.4 MM
VOLTAGE=50V
MIN_NECK_WIDTH=0.2 MM
MIN_LINE_WIDTH=0.5 MM
PPVOUT_S0_LCDBKLT
MIN_LINE_WIDTH=0.5 MM VOLTAGE=50V
SWITCH_NODE=TRUE
PPBUS_S0_LCDBKLT_PWR_SW
MIN_NECK_WIDTH=0.375 MM
BKL_ISEN2
MIN_NECK_WIDTH=0.20 mm
MIN_LINE_WIDTH=0.5 mm
BKL_ISEN4
MIN_NECK_WIDTH=0.20 mm
MIN_LINE_WIDTH=0.5 mm
BKL_ISEN5
MIN_NECK_WIDTH=0.20 mm
MIN_LINE_WIDTH=0.5 mm
BKL_VSYNC_R
BKL_ISEN3
MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm
BKL_SCL BKL_SDA
PPBUS_S0_LCDBKLT_PWR
MIN_NECK_WIDTH=0.375 MM
MIN_LINE_WIDTH=0.5 MM
PPVIN_BKL
VOLTAGE=8.4V
BKL_FLTR_RC
MIN_LINE_WIDTH=0.5 mm
LED_RETURN_2
MIN_NECK_WIDTH=0.20 mm
GMUX_VSYNC
LCD_BKLT_PWM
LED_RETURN_5
MIN_NECK_WIDTH=0.20 mm
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm
MIN_LINE_WIDTH=0.5 mm
LED_RETURN_1
SMBUS_PCH_CLK
PPBUS_S0_LCDBKLT_PWR
SMBUS_PCH_DATA
MIN_NECK_WIDTH=0.20 mm
MIN_LINE_WIDTH=0.5 mm
LED_RETURN_3
MIN_NECK_WIDTH=0.20 mm
MIN_LINE_WIDTH=0.5 mm
LED_RETURN_6
MIN_LINE_WIDTH=0.5 mm
LED_RETURN_4
MIN_NECK_WIDTH=0.20 mm
PP5V_S0
97 OF 132
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<SCH_NUM>
<BRANCH>
88 OF 101
6 7
17 18 19 20 21 23 24 25
26 27 28 30 34 37 40 42 46 47
48 50 51 52 54 58 62 63 68
69 72 73 80 83 84 85 87 99
6
6
56 83 88 89
17 25 26 28 30 32 42 47 48 63 94
88 89
17 25 26 28 30 32 42 47 48 63 94
6 7
23 42 47 52 54 68 69 70
72 86
Page 89
OUT
IN
D
SG
D
SG
IN
IN
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER
SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
CHANNEL
.
MOSFET
RDS(ON)
FDC638APZ
PPBUS S0 LCDBkLT FET
P-TYPE
0.4 A (EDP)LOADING
43 mOhm @4.5V
0402-HF
CRITICAL
2AMP-32V
F9800
1 2
88
1/16W
1%
402
MF-LF
301K
R9808
1
2
MF-LF
1/16W
1%
402
147K
R9809
1
2
16V
10%
402
X5R
0.1UF
C9802
1
2
6 7
40 49 65 66 67 69 70 82
86
CRITICAL
FDC638APZ_SBMS001
SSOT6-HF
Q9806
1 2 5 6
3
4
1/16W
5%
402
MF-LF
4.7K
R9840
1
2
SSM6N15FEAPE
SOT563
Q9807
3
5
4
SOT563
SSM6N15FEAPE
Q9807
6
2
1
8
87 89
27
SYNC_DATE=05/29/2009
SYNC_MASTER=K19_MLB
LCD Backlight Support
PPBUS_G3H
LCD_BKLT_EN
PBUS_S0_LCDBKLT_EN_DIV
MIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.4 mm VOLTAGE=12.6V
PPBUS_S0_LCDBKLT_PWR
PBUS_S0_LCDBKLT_EN_L
BKLT_PLT_RST_L
BKLT_EN_L
LCD_BKLT_EN
MIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.4 mm VOLTAGE=12.6V
PPBUS_S0_LCDBKLT_FUSED
98 OF 132
<E4LABEL>
<SCH_NUM>
<BRANCH>
89 OF 101
8
87 89
Page 90
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER
SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
Blank Page, was 1.2V/1.8V in K19
SYNC_DATE=06/10/2009
SYNC_MASTER=K18_POWER
Misc Power Supplies
99 OF 132
<E4LABEL>
<SCH_NUM>
<BRANCH>
90 OF 101
Page 91
LINE-TO-LINE SPACING
LAYER
SPACING_RULE_SET
WEIGHT
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
MINIMUM LINE WIDTH
ALLOW ROUTE ON LAYER?
LAYER
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
LINE-TO-LINE SPACING
LAYER
SPACING_RULE_SET
WEIGHT
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
LINE-TO-LINE SPACING
LAYER
SPACING_RULE_SET
WEIGHT
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
LINE-TO-LINE SPACING
LAYER
SPACING_RULE_SET
WEIGHT
TABLE_SPACING_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER
SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
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2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
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345678
D
B
8 7 5 4 2 1
MINIMUM LINE WIDTH
ALLOW ROUTE ON LAYER?
LAYER
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
SOURCE: Calpella SFF DG (DG-407364_v1.5), Section 2.1 and Table 4-184.
NOTE: 7 mil gap is for VCCSense pair, which Intel says to route with 7 mil spacing without specifying a target impedance.
Most CPU signals with impedance requirements are 50-ohm single-ended. Some signals require 27.4-ohm single-ended impedance.
SOURCE: Calpella SFF DG (DG-407364_v1.5), Section 2.8
CPU Signal Constraints
(FSB_CPURST_L)
NET_TYPE
PHYSICAL
SPACING
ELECTRICAL_CONSTRAINT_SET
CPU Net Properties
PCI-Express
=3X_DIELECTRIC
?
PCIE
*
20 MIL
?
CLK_PCIE
*
=90_OHM_DIFF
=90_OHM_DIFF =90_OHM_DIFF
=90_OHM_DIFF =90_OHM_DIFF*
CLK_PCIE_90D =90_OHM_DIFF
=27P4_OHM_SE
CPU_27P4S
*
=27P4_OHM_SE
7 MIL
=27P4_OHM_SE =27P4_OHM_SE
7 MIL
=50_OHM_SE =50_OHM_SE
=STANDARD
CPU_50S
=STANDARD*
=50_OHM_SE =50_OHM_SE
=55_OHM_SE
*
CPU_55S
=55_OHM_SE =55_OHM_SE =55_OHM_SE
=STANDARD=STANDARD
CPU Constraints
SYNC_DATE=06/15/2009
SYNC_MASTER=K17_REF
=85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF
=85_OHM_DIFF =85_OHM_DIFF* =85_OHM_DIFF
PCIE_85D
CPU_AGTL
TOP,BOTTOM
=2x_DIELECTRIC
?
PCIE
?
TOP,BOTTOM
=4X_DIELECTRIC
CPU_VCCSENSE
*
25 MIL
?
=2:1_SPACING
*
CPU_ITP
?
20 MIL
*
CPU_COMP
?
8 MIL
*
CPU_8MIL
?
=STANDARD
*
?
CPU_AGTL
CPU_VCCSENSE
CPU_27P4S
CPU_VTTSENSE_N
CPU_VCCSENSE
PEG_D2R_C_N<15..0>
PCIEPCIE_85D
PEG_D2R_C_P<15..0>
PCIEPCIE_85D
PEG_D2R_N<15..0>
PCIE_85D PCIE
PEG_D2R_P<15..0>
PCIE
PEG_D2R
PCIE_85D
PEG_R2D_C_N<15..0>
PCIEPCIE_85D
PEG_R2D_C_P<15..0>
PEG_R2D
PCIEPCIE_85D
PEG_R2D_N<15..0>
PCIE_85D PCIE
PEG_R2D_P<15..0>
PCIEPCIE_85D
CPU_27P4S
CPU_VCCSENSE
CPU_VCCSENSE_P
CPU_VCCSENSE
CPU_27P4S
CPU_VCCSENSE CPU_VCCSENSE
CPU_VCCSENSE_N
FDI_LSYNC<1..0>
CPU_50S
CPU_AGTL
PCIE_85DFDI_DATA
FDI_DATA_P<7:0>
PCIE
DMI_S2N
PCIE_85D
DMI_S2N_P<3:0>
PCIE
PCIE_85DFDI_DATA
FDI_DATA_N<7:0>
PCIE
CPU_50S
CPU_AGTL
FDI_INT
PCIE_85D
DMI_N2S
PCIE
DMI_N2S_N<3:0>
DMI_S2N
PCIEPCIE_85D
DMI_S2N_N<3:0>
PCIE_85D
DMI_N2S
DMI_N2S_P<3:0>
PCIE
CPU_50S
FDI_FSYNC<1..0>
CPU_AGTL
CPU_AGTL
CPU_50S
CPU_PWRGD
CPU_PWRGD
CPU_50S
TP_CPU_VTT_SELECT
CPU_AGTL
CPU_50S
CPU_PROCHOT_L
CPU_PROCHOT_L
CPU_AGTL
CPU_CATERR_L
CPU_50S
CPU_AGTLCPU_CATERR_L
CPU_CFG<17..0>
CPU_ITPCPU_50SCPU_CFG
CPU_SM_RCOMP2
CPU_COMP
CPU_27P4S
CPU_SM_RCOMP
CPU_SM_RCOMP
CPU_SM_RCOMP0
CPU_COMP
CPU_27P4S
CPU_SM_RCOMP
CPU_SM_RCOMP1
CPU_COMP
CPU_27P4S
CPU_AGTL
CPU_50S
PM_EXT_TS_L<1>
CPU_AGTL
CPU_50S
PM_EXT_TS_L<0>
CPU_ITP
XDP_PREQ_L
CPU_50S
XDP_PREQ_l
XDP_PRDY_L
XDP_PRDY_L
CPU_ITPCPU_50S
XDP_BDRESET_L
CPU_ITP
XDP_DBRESET_L
CPU_50S
XDP_XPU_PWRGOOD
CPU_ITPCPU_50S
XDP_CPUPWRGD
CPU_VTT_S0_PGOOD
CPU_AGTL
CPUVTTS0_PGOOD
CPU_50S
CPU_AGTL
PM_SYNC CPU_50S
PM_SYNC
CPU_50S
CPU_AGTL
PM_MEM_PWRGD
PM_MEM_PWRGD
CPU_PECI PCIE
CPU_50S
CPU_PECI
CPU_50S
CPU_AGTLFSB_CPURST_L
FSB_CPURST_L
CPU_8MIL
PM_THRMTRIP_L
CPU_50S
PM_THRMTRIP_L
GFXIMVP_IMON
CPU_50S
CPU_AGTL
GFX_VR_EN
CPU_AGTL
CPU_50S
GFX_DPRSLPVR
PM_DPRSLPVR
CPU_50S
CPU_AGTL
GFX_VID<6..0>
CPU_8MIL
CPU_55S
CPU_27P4S
CPU_VCCSENSE
GFX_VSENSE_N
CPU_VCCSENSE
CPU_VCCSENSE
CPU_27P4S
GFX_VSENSE_P
CPU_VCCSENSE
CPU_VCCSENSE
CPU_27P4S
CPU_VTTSENSE_P
CPU_VCCSENSE
CPU_AGTL
CPU_50S
CPUIMVP_IMON
CPU_55S
CPU_VID<6..0>
CPU_8MIL
CPU_50S
XDP_CPURST_L
CPU_ITP
CPU_50S
XDP_BPM_L
XDP_BPM_L<7>
CPU_ITP
CPU_50S
XDP_BPM_L
XDP_BPM_L<6..0>
CPU_ITP
XDP_TRST_L
CPU_50S
XDP_TRST_L
CPU_ITP
CPU_50SXDP_TMS CPU_ITP
XDP_TMS
CPU_50S CPU_ITPXDP_TCK
XDP_TCK
CPU_50S CPU_ITPXDP_TDI
XDP_TDI
CPU_50S CPU_ITP
XDP_TDO
XDP_TDO
CPU_27P4S
CPU_COMP CPU_COMP
CPU_COMP0
CPU_27P4S
CPU_COMP CPU_COMP
CPU_COMP1
CPU_27P4S
CPU_COMP
CPU_COMP2
CPU_COMP
CPU_COMP
CPU_27P4S
CPU_PEG_RBIAS
CPU_27P4S
CPU_COMP
CPU_COMP3
CPU_COMP
CPU_COMP
CPU_27P4S
CPU_PEG_COMP
PM_DPRSLPVR
CPU_50S
CPU_AGTL
PM_DPRSLPVR
PCIE_CLK100M_CPU
PCIE_CLK100M_CPU_N
CLK_PCIE_90D CLK_PCIE
CPU_55S
CPU_PSI_L
CPU_8MIL
FSB_CLK_ITP
CLK_PCIE
FSB_CLK133M_ITP_N
CLK_PCIE_90D
PCIE_CLK100M_CPU
PCIE_CLK100M_CPU_P
CLK_PCIE_90D CLK_PCIE
FSB_CLK_ITP
CLK_PCIE
FSB_CLK133M_ITP_P
CLK_PCIE_90D
FSB_CLK133M_CPU_N
CLK_PCIECLK_PCIE_90D
FSB_CLK_CPU
CLK_PCIE_90D
FSB_CLK133M_CPU_P
CLK_PCIE
FSB_CLK_CPU
100 OF 132
<E4LABEL>
<SCH_NUM>
<BRANCH>
91 OF 101
12 70
74
74
8
74
8 9
74
8
74
8 9
74
74
74
12 68
12 68
9
18
9
18
9
18
9
18
9
18
9
18
9
18
9
18
9
18
10 20 25
8
12
10 46 68
10
8 9
25
10
10
10
10 46
10 46
10 25
10 25
10 25 27
10 25
10 70
10 18
10 18 31
10 20
10 25
10 20 46
13 69
13 69
13 69
8
13
13 69
13 69
12 70
12 50 68
8
12 15
25
10 25
10 25
10 25
10 25
10 25
25
25
10
10
10
9
10
9
12 15 68
10 17
12 15 68
10 25
10 17
10 25
10 20
10 20
Page 92
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
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REVISION
DRAWING NUMBER
SIZE
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Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
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C
345678
D
B
8 7 5 4 2 1
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
AREA_TYPE
SPACING_RULE_SET
NET_SPACING_TYPE1 NET_SPACING_TYPE2
TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
AREA_TYPE
SPACING_RULE_SET
NET_SPACING_TYPE1 NET_SPACING_TYPE2
TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
AREA_TYPE
SPACING_RULE_SET
NET_SPACING_TYPE1 NET_SPACING_TYPE2
TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
AREA_TYPE
SPACING_RULE_SET
NET_SPACING_TYPE1 NET_SPACING_TYPE2
TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
AREA_TYPE
SPACING_RULE_SET
NET_SPACING_TYPE1 NET_SPACING_TYPE2
TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
AREA_TYPE
SPACING_RULE_SET
NET_SPACING_TYPE1 NET_SPACING_TYPE2
TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
LINE-TO-LINE SPACING
LAYER
SPACING_RULE_SET
WEIGHT
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
MINIMUM LINE WIDTH
ALLOW ROUTE ON LAYER?
LAYER
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
Memory Net Properties
ELECTRICAL_CONSTRAINT_SET
DDR3:
DQ/DM signals should be matched within 0.508mm of associated DQS pair.
CLK intra-pair matching should be within 0.127mm, inter-pair matching should be within 0.508mm.
Memory Bus Spacing Group Assignments
DQS intra-pair matching should be within 0.127mm, no inter-pair matching requirement.
CONTROL signals should be matched within [CLK-12.7mm] to [CLK+0.0mm] of CLK pairs.
DQS to clock matching should be within [CLK-12.7mm] and [CLK+25.4mm].
DQ/DQS/A/BA/cmd signal spacing is 4x dielectric, CLK is 5x dielectric.
A/BA/CMD signals should be matched within [CLK-12.7mm] to [CLK+12.7mm] of CLK pairs.
SOURCE: Calpella SFF Platform DG, Rev 1.5 (#407364), Section 2.2
Need to support MEM_*-style wildcards!
Maximum length of any signal from die pad to SODIMM pad is 139.7mm, from procesor ball to SODIMM pad is 114.3mm.
Memory Bus Constraints
PHYSICAL
SPACING
NET_TYPE
MEM_50S
=50_OHM_SE=50_OHM_SE=50_OHM_SE
=STANDARD* =STANDARD
=50_OHM_SE
*
?
MEM_CLK2MEM
=4:1_SPACING
=2.5:1_SPACING
MEM_CTRL2MEM
?
*
MEM_CTRL2CTRL
=3:1_SPACING
*
?
MEM_CMD2MEM
MEM_CLK
*
MEM_CMD MEM_CMD
MEM_CTRL
MEM_CMD2MEM
*
MEM_CMD
MEM_CMD2CMD
MEM_CMD
*
MEM_CMD
MEM_DATA
MEM_CMD2MEM
*
MEM_DQS
*
MEM_CMD
MEM_CMD2MEM
*
MEM_CLK
MEM_DATA
MEM_DATA2MEM MEM_DATA2MEM
MEM_CTRL
*
MEM_DATA
MEM_DATA2MEM
MEM_CMD
*
MEM_DATA
* *
MEM_CLK
MEM_2OTHER
MEM_CTRL
**
MEM_2OTHER
* *
MEM_DQS
MEM_2OTHER
MEM_DATA
**
MEM_2OTHER
* *
MEM_CMD
MEM_2OTHER
?
=1.5:1_SPACING
*
MEM_CMD2CMD
=3:1_SPACING
MEM_DQS2MEM
*
?
MEM_CLK
*
MEM_CLK
MEM_CLK2MEM
MEM_CTRL
*
MEM_CLK
MEM_CLK2MEM
MEM_DQS
*
MEM_CLK
MEM_CLK2MEM
MEM_CLK2MEM
MEM_DATA
MEM_CLK
*
MEM_CMD
*
MEM_CLK
MEM_CLK2MEM
MEM_CTRL2MEM
MEM_CLK
*
MEM_CTRL
MEM_CTRLMEM_CTRL
*
MEM_CTRL2CTRL
MEM_CMD
MEM_CTRL
*
MEM_CTRL2MEM
MEM_DATAMEM_CTRL
*
MEM_CTRL2MEM MEM_CTRL2MEM
MEM_DQS
*
MEM_CTRL
*
MEM_DQS
MEM_DQS2MEM
MEM_CLK
*
MEM_CTRL
MEM_DQS
MEM_DQS2MEM
*
MEM_DQS2MEM
MEM_CMDMEM_DQS
MEM_DQS
*
MEM_DQS
MEM_DQS2MEM
MEM_DQS
*
MEM_DATA
MEM_DQS2MEM
25 MILS
*
MEM_2OTHER
?
=3:1_SPACING
?
*
MEM_DATA2MEM
=1.5:1_SPACING
*
?
MEM_DATA2DATA
MEM_CMD2MEM
=3:1_SPACING
?
*
MEM_72D
=72_OHM_DIFF=72_OHM_DIFF
=72_OHM_DIFF=72_OHM_DIFF=72_OHM_DIFF
=72_OHM_DIFF*
* =STANDARD =STANDARD
MEM_37S
=37_OHM_SE =37_OHM_SE=37_OHM_SE=37_OHM_SE
MEM_40S
=STANDARD* =STANDARD
=40_OHM_SE =40_OHM_SE=40_OHM_SE =40_OHM_SE
=85_OHM_DIFF=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF*
=85_OHM_DIFF
MEM_85D
=85_OHM_DIFF
MEM_DQS
*
MEM_DATA
MEM_DATA2MEM
MEM_DATA
*
MEM_DATA2DATA
MEM_DATA
SYNC_DATE=06/15/2009
SYNC_MASTER=K17_REF
Memory Constraints
MEM_50S
MEM_B_DM<5>
MEM_DATA
MEM_B_DQ_BYTE5
MEM_50S
MEM_B_DM<4>
MEM_DATA
MEM_B_DQ_BYTE4
MEM_50SMEM_B_DQ_BYTE7
MEM_B_DM<7>
MEM_DATA
MEM_85D
MEM_A_DQS_P<6>
MEM_DQS
MEM_A_DQS6
MEM_85D
MEM_A_DQS5
MEM_A_DQS_N<5>
MEM_DQS
MEM_85D
MEM_A_DQS6
MEM_A_DQS_N<6>
MEM_DQS
MEM_85D
MEM_A_DQS7
MEM_A_DQS_N<7>
MEM_DQS
MEM_B_CLK_P<5..0>
MEM_CLKMEM_72D
MEM_B_CLK
MEM_A_CNTL
MEM_A_CKE<3..0>
MEM_CTRL
MEM_37S
MEM_50S
MEM_DATA
MEM_A_DM<3>
MEM_A_DQ_BYTE3
MEM_50S
MEM_B_DM<6>
MEM_DATA
MEM_B_DQ_BYTE6
MEM_85D
MEM_B_DQS1
MEM_B_DQS_P<1>
MEM_DQS
MEM_85D
MEM_B_DQS3
MEM_B_DQS_P<3>
MEM_DQS
MEM_B_DQS3
MEM_B_DQS_N<3>
MEM_DQSMEM_85D
MEM_85D
MEM_B_DQS2
MEM_B_DQS_N<2>
MEM_DQS
MEM_B_DQS2
MEM_B_DQS_P<2>
MEM_DQSMEM_85D
MEM_85D
MEM_B_DQS1
MEM_B_DQS_N<1>
MEM_DQS
MEM_85D
MEM_B_DQS0
MEM_B_DQS_N<0>
MEM_DQS
MEM_85D
MEM_B_DQS0
MEM_B_DQS_P<0>
MEM_DQS
MEM_50SMEM_B_DQ_BYTE3
MEM_B_DM<3>
MEM_DATA
MEM_50SMEM_B_DQ_BYTE2
MEM_B_DM<2>
MEM_DATA
MEM_50SMEM_B_DQ_BYTE1
MEM_B_DM<1>
MEM_DATA
MEM_50SMEM_B_DQ_BYTE0
MEM_B_DM<0>
MEM_DATA
MEM_50SMEM_B_DQ_BYTE6
MEM_B_DQ<55..48>
MEM_DATA
MEM_50SMEM_B_DQ_BYTE4
MEM_B_DQ<39..32>
MEM_DATA
MEM_50SMEM_B_DQ_BYTE3
MEM_DATA
MEM_B_DQ<31..24>
MEM_50SMEM_B_DQ_BYTE2
MEM_B_DQ<23..16>
MEM_DATA
MEM_50SMEM_B_DQ_BYTE1
MEM_B_DQ<15..8>
MEM_DATA
MEM_50SMEM_B_DQ_BYTE0
MEM_B_DQ<7..0>
MEM_DATA
MEM_B_CMD
MEM_B_WE_L
MEM_CMDMEM_40S
MEM_85D
MEM_A_DQS7
MEM_A_DQS_P<7>
MEM_DQS
MEM_85D
MEM_A_DQS_P<5>
MEM_DQS
MEM_A_DQS5
MEM_85D
MEM_A_DQS3
MEM_A_DQS_N<3>
MEM_DQS
MEM_85D
MEM_A_DQS3
MEM_A_DQS_P<3>
MEM_DQS
MEM_85D
MEM_A_DQS2
MEM_A_DQS_N<2>
MEM_DQS
MEM_85D
MEM_A_DQS_P<2>
MEM_DQS
MEM_A_DQS2
MEM_85D
MEM_A_DQS4
MEM_A_DQS_N<4>
MEM_DQS
MEM_85D
MEM_A_DQS4
MEM_A_DQS_P<4>
MEM_DQS
MEM_85D
MEM_A_DQS_P<1>
MEM_A_DQS1
MEM_DQS
MEM_85D
MEM_A_DQS0
MEM_A_DQS_N<0>
MEM_DQS
MEM_85D
MEM_A_DQS0
MEM_DQS
MEM_A_DQS_P<0>
MEM_50S
MEM_DATA
MEM_A_DM<7>
MEM_A_DQ_BYTE7
MEM_50S
MEM_DATA
MEM_A_DM<6>
MEM_A_DQ_BYTE6
MEM_50S
MEM_A_DM<5>
MEM_DATA
MEM_A_DQ_BYTE5
MEM_50S
MEM_A_DM<4>
MEM_DATA
MEM_A_DQ_BYTE4
MEM_50S
MEM_A_DM<2>
MEM_DATA
MEM_A_DQ_BYTE2
MEM_50S
MEM_DATA
MEM_A_DM<1>
MEM_A_DQ_BYTE1
MEM_50S
MEM_DATA
MEM_A_DQ_BYTE6
MEM_A_DQ<55..48>
MEM_50S
MEM_DATA
MEM_A_DQ_BYTE5
MEM_A_DQ<47..40>
MEM_50S
MEM_A_DQ<31..24>
MEM_A_DQ_BYTE3
MEM_DATA
MEM_85D
MEM_B_DQS_N<5>
MEM_DQS
MEM_B_DQS5
MEM_85D
MEM_B_DQS4
MEM_B_DQS_N<4>
MEM_DQS
MEM_85D
MEM_B_DQS_P<5>
MEM_DQS
MEM_B_DQS5
MEM_85D
MEM_B_DQS6
MEM_B_DQS_P<6>
MEM_DQS
MEM_85D
MEM_B_DQS7
MEM_B_DQS_P<7>
MEM_DQS
MEM_85D
MEM_B_DQS_N<6>
MEM_DQS
MEM_B_DQS6
MEM_50SMEM_B_DQ_BYTE7
MEM_B_DQ<63..56>
MEM_DATA
MEM_50S
MEM_A_DQ<39..32>
MEM_DATA
MEM_A_DQ_BYTE4
MEM_50SMEM_A_DQ_BYTE2
MEM_A_DQ<23..16>
MEM_DATA
MEM_50SMEM_A_DQ_BYTE7
MEM_A_DQ<63..56>
MEM_DATA
MEM_50S
MEM_DATA
MEM_A_DM<0>
MEM_A_DQ_BYTE0
MEM_85D
MEM_A_DQS1
MEM_A_DQS_N<1>
MEM_DQS
MEM_A_CLK_N<5..0>
MEM_A_CLK
MEM_CLKMEM_72D
MEM_A_CLK_P<5..0>
MEM_A_CLK
MEM_CLKMEM_72D
MEM_B_CMD
MEM_B_RAS_L
MEM_CMDMEM_40S
MEM_85D
MEM_B_DQS_N<7>
MEM_B_DQS7
MEM_DQS
MEM_85D
MEM_B_DQS4
MEM_B_DQS_P<4>
MEM_DQS
MEM_B_CMD
MEM_CMD
MEM_B_A<15..0>
MEM_40S
MEM_B_CS_L<3..0>
MEM_B_CNTL
MEM_CTRL
MEM_37S
MEM_50SMEM_B_DQ_BYTE5
MEM_DATA
MEM_B_DQ<47..40>
MEM_B_CMD
MEM_B_CAS_L
MEM_CMDMEM_40S
MEM_B_CMD
MEM_B_BA<2..0>
MEM_40S MEM_CMD
MEM_B_ODT<3..0>
MEM_B_CNTL
MEM_CTRL
MEM_37S
MEM_B_CKE<3..0>
MEM_CTRL
MEM_37S
MEM_B_CNTL
MEM_CLK
MEM_B_CLK_N<5..0>
MEM_72D
MEM_B_CLK
MEM_50S
MEM_DATA
MEM_A_DQ_BYTE1
MEM_A_DQ<15..8>
MEM_50S
MEM_DATA
MEM_A_DQ_BYTE0
MEM_A_DQ<7..0>
MEM_A_CMD
MEM_A_WE_L
MEM_40S MEM_CMD
MEM_CMD
MEM_A_CMD
MEM_A_CAS_L
MEM_40S
MEM_A_RAS_L
MEM_A_CMD
MEM_CMDMEM_40S
MEM_A_BA<2..0>
MEM_A_CMD
MEM_CMDMEM_40S
MEM_A_CMD
MEM_A_A<15..0>
MEM_CMDMEM_40S
MEM_A_CNTL
MEM_CTRL
MEM_A_ODT<3..0>
MEM_37S
MEM_A_CNTL
MEM_CTRL
MEM_A_CS_L<3..0>
MEM_37S
101 OF 132
<E4LABEL>
<SCH_NUM>
<BRANCH>
92 OF 101
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11 29
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11 29
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11 28
11 29
11 29
11 29
11 29
11 29
11 29
11 29
11 29
11 29 30
11 29 30
11 29
11 29
11 29
11 29 30
11 29
11 29 30
11 29
11 29
11 29
11 29
11 30
11 29
11 29
11 29
11 29
11 29
11 29
11 29
11 29
11 29
11 28 29
11 28 29
11 29
11 29
11 29
11 29
11 29
11 29
11 29
11 29
11 29
11 29
11 29
11 29
11 29
11 29
11 29
11 29
11 28 29
11 29
11 29
11 28 29
11 29
11 28
11 28
11 30
11 29
11 29
11 30
11 30
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Page 93
LINE-TO-LINE SPACING
LAYER
SPACING_RULE_SET
WEIGHT
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM
LINE-TO-LINE SPACING
LAYER
SPACING_RULE_SET
WEIGHT
TABLE_SPACING_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
LINE-TO-LINE SPACING
LAYER
SPACING_RULE_SET
WEIGHT
TABLE_SPACING_RULE_HEAD
MINIMUM LINE WIDTH
ALLOW ROUTE ON LAYER?
LAYER
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTH
ALLOW ROUTE ON LAYER?
LAYER
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_SPACING_RULE_ITEM
LINE-TO-LINE SPACING
LAYER
SPACING_RULE_SET
WEIGHT
TABLE_SPACING_RULE_HEAD
MINIMUM LINE WIDTH
ALLOW ROUTE ON LAYER?
LAYER
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER
SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
LINE-TO-LINE SPACING
LAYER
SPACING_RULE_SET
WEIGHT
TABLE_SPACING_RULE_HEAD
LINE-TO-LINE SPACING
LAYER
SPACING_RULE_SET
WEIGHT
TABLE_SPACING_RULE_HEAD
LVDS intra-pair matching should be 5 mils. Pairs should be within 100 mils of clock length.
DIsplayPort AUX CH intra-pair matching should be 5 ps. No relationship to other signals.
ELECTRICAL_CONSTRAINT_SET
NET_TYPE
SPACING
PHYSICAL
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.7.1.
SATA Interface Constraints
Max length of LVDS/DisplayPort/TMDS traces: 12 inches.
DisplayPort/TMDS intra-pair matching should be 5 ps. Inter-pair matching should be within 150 ps.
Digital Video Signal Constraints
PCH Net Properties
SOURCE: Calpella Platform Design Guide for Ibex Peak M (DG-398905-398905_v1.5), Section 3.8
USB 2.0 Interface Constraints
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Sections 2.5.3 & 2.5.4.
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
USB_85D
*
=85_OHM_DIFF
=85_OHM_DIFF=85_OHM_DIFF
=4x_DIELECTRIC
TOP,BOTTOM
?
USB
SYNC_DATE=06/15/2009
SYNC_MASTER=K17_REF
PCH Constraints 1
?
TOP,BOTTOM
SATA
=3x_DIELECTRIC
=90_OHM_DIFF
SATA_90D
=90_OHM_DIFF =90_OHM_DIFF
=90_OHM_DIFF=90_OHM_DIFF=90_OHM_DIFF
*
=3x_DIELECTRIC
?
*
LVDS
*
LVDS_85D
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF =85_OHM_DIFF
=85_OHM_DIFF=85_OHM_DIFF
=85_OHM_DIFF =85_OHM_DIFF*
DP_85D
=85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF
=85_OHM_DIFF
SATA_ICOMP 8 MIL
*
?
USB
=2x_DIELECTRIC
?
*
=STANDARD
8 MIL
=STANDARD
8 MIL
* =STANDARD
PCH_USB_RBIAS
=STANDARD
TOP,BOTTOM
=4x_DIELECTRIC
?
DISPLAYPORTDISPLAYPORT
=3x_DIELECTRIC
*
?
?
LVDS
=4x_DIELECTRIC
TOP,BOTTOM
=4x_DIELECTRIC
?
SATA
*
USB
USB_85D
USB_CAMERA_CONN_N
USB
USB_85D
USB_CAMERA
USB_CAMERA_CONN_P
USB
USB_MINI_N
USB_85D
SATA
SATA_ODD_D2R_N
SATA_90D SATA_90D
SATA_ODD_D2R_C_P
SATA
SATA_90D
SATA_ODD_D2R_C_N
SATA
USB_HUB2_UP_N
USB
USB_85D
USB_HUB1_UP_N
USB_85D
USB
SATA_HDD_R2D
SATA_HDD_R2D_RDRV_IN_P
SATA_90D SATA
SATA_90D
SATA_HDD_D2R_RDRV_OUT_P
SATA
SATA_90D
SATA_HDD_D2R_RDRV_OUT_N
SATA
SATA_HDD_D2R_RDRV_IN_N
SATA_90D SATA
SATA_90D
SATA_HDD_R2D_RDRV_OUT_N
SATA
SATA_90D
SATA_HDD_R2D_RDRV_OUT_P
SATA
SATA_HDD_R2D_RDRV_IN_N
SATA_90D SATA
SATA_90D
SATA_HDD_D2R_RDRV_IN_P
SATA_HDD_D2R SATA
USB_HUB1_UP_P
USB_HUB1_UP
USB
USB_85D
USB_HUB2_UP_P
USB_HUB2_UP
USB
USB_85D
USB_85D
USB
USB_EXTA_P
USB_EXTA
USB_85D
USB_EXTB
USB
USB_EXTB_P
USB_85D
USB_EXTA_N
USB
GFX_CLK_DPLLSS
CLK_PCIE_90D CLK_PCIE
GFX_CLK120M_DPLLSS_N
GFX_CLK_DPLLSS
CLK_PCIE_90D CLK_PCIE
GFX_CLK120M_DPLLSS_P
CPU_50S
PCH_CLK14P3M_REFCLK
CLK_PCIE
PCH_CLK33M_PCIIN
CPU_50S
CLK_PCIE
PCH_CLK100M_SATA_P
PCH_CLK100M_SATA
CLK_PCIE_90D CLK_PCIE
PCH_CLK100M_SATA
CLK_PCIE
PCH_CLK100M_SATA_N
CLK_PCIE_90D
CLK_PCIE_90D CLK_PCIE
PCH_CLK96M_DOT_N
CLK_PCIE_90D CLK_PCIE
FSB_CLK133M_PCH_N
CLK_PCIE_90D CLK_PCIE
PCH_CLK96M_DOT_P
CLK_PCIECLK_PCIE_90D
FSB_CLK133M_PCH_P
PCH_CLK100M_PCH
CLK_PCIE_90D CLK_PCIE
PCIE_CLK100M_PCH_N
CLK_PCIE_90D CLK_PCIE
PCIE_CLK100M_PCH_P
PCH_USB_RBIASPCH_USB_RBIAS
PCH_USB_RBIAS
USB_85D
USB
USB_BRCRYPT_N
USB_SDCARD_N
USB
USB_85D
USB
USB_BRCRYPT_P
USB_BRCRYPT
USB_85D
USB_IR_N
USB
USB_85D
USB_SDCARD
USB_SDCARD_P
USB
USB_85D
USB_IR
USB
USB_IR_P
USB_85D
USB
USB_85D
USB_BT
USB_BT_P USB_BT_N
USB
USB_85D
USB_WM_N
USB
USB_85D
USB_WM_P
USB_85D
USB
USB_WM
USB_MINI_P
USB
USB_85D
USB_MINI
USB_EXTD_P
USB
USB_EXTD
USB_85D
USB_EXTD_N
USB
USB_85D
USB_EXTC_N
USB_85D
USB
USB_EXTB_N
USB_85D
USB
USB_EXTC_P
USB
USB_85D
USB_EXTC
SATA_90D
SATA_HDD_D2R_N
SATA
SATA_ODD_R2D_P
SATA_90D SATA
DP_IG_AUX_CH_P
DISPLAYPORT
DP_AUX_CH
DP_85D
DP_IG_ML_P<3..0>
DP_ML
DISPLAYPORT
DP_85D
DP_IG_ML_N<3..0>
DP_ML
DISPLAYPORT
DP_85D
DP_IG_AUX_CH_N
DP_AUX_CH
DISPLAYPORT
DP_85D
LVDS_85D
LVDS_IG_A_CLK_N
LVDS
LVDS_IG_A_CLK
LVDS_IG_A_DATA_N<2..0>
LVDS_85D
LVDS_IG_A_DATA
LVDS
NC_LVDS_IG_A_DATAP<3>
LVDS_85D LVDS
LVDS_IG_A_DATA3
NC_LVDS_IG_A_DATAN<3>
LVDS_85D LVDS
LVDS_IG_A_DATA3
TP_LVDS_IG_B_CLKP
LVDS_85D LVDS
LVDS_IG_B_CLK
TP_LVDS_IG_B_CLKN
LVDS_85D LVDS
LVDS_IG_B_CLK
LVDS_IG_B_DATA_P<2..0>
LVDS_85D LVDS
LVDS_IG_B_DATA
LVDS_IG_B_DATA_N<2..0>
LVDS_85D
LVDS_IG_B_DATA
LVDS
NC_LVDS_IG_B_DATAP<3>
LVDS_85D LVDS
LVDS_IG_B_DATA3
NC_LVDS_IG_B_DATAN<3>
LVDS_85D LVDS
LVDS_IG_B_DATA3
SATA_90D
SATA_ODD_R2D_C_P
SATASATA_ODD_R2D
SATA_90D
SATA_HDD_D2R_C_P
SATA
SATA_90D
SATA_HDD_D2R_C_N
SATA
SATA_ODD_R2D_N
SATA_90D SATA
SATA_90D
SATA_ODD_R2D_C_N
SATA
SATA_90D
SATA_ODD_D2R_P
SATASATA_ODD_D2R
PCH_SATAICOMP
SATA_ICOMP
PCH_SATA_ICOMP
SATA_90D
SATA_HDD_D2R_P
SATA_HDD_D2R SATA
SATA_90D
SATA_HDD_R2D_N
SATA
SATA_90D
SATA_HDD_R2D_P
SATA
SATA_90D
SATA_HDD_R2D_C_N
SATA
SATA_90D
SATA_HDD_R2D_C_P
SATA_HDD_R2D SATA
LVDS_85D LVDS
LVDS_IG_A_DATA_P<2..0>
LVDS_IG_A_DATA
LVDS_85D
LVDS_IG_A_CLK_P
LVDS
LVDS_IG_A_CLK
USB_TPAD_P
USB
USB_TPAD
USB_85D
USB_TPAD_N
USB
USB_85D
102 OF 132
<E4LABEL>
<SCH_NUM>
<BRANCH>
93 OF 101
6
33
6
33
17 42
6
42
6
42
19 36
19 35
42
42
42
42
42
42
42
42
19 35
19 36
36 43
35 43
36 43
10 17
10 17
17 26
17 27
17 26
17 26
17 26
17 26
17 26
17 26
17 26
17 26
19
19
101
8
34 36
19
101
35 44
8
34 36
35 44
33 36
33 36
8
35
35 43
8
35
17 42
6
42
8
18 84
8
84
8
84
8
18 84
18 87
18 87
8
18
8
18
6 8
18
6 8
18
18 87
18 87
8
18
8
18
17 42
6
42
6
42
6
42
17 42
17 42
17
17 42
6
42
6
42
17 42
17 42
18 87
18 87
36 53
36 53
Page 94
MINIMUM LINE WIDTH
ALLOW ROUTE ON LAYER?
LAYER
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
LINE-TO-LINE SPACING
LAYER
SPACING_RULE_SET
WEIGHT
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTH
ALLOW ROUTE ON LAYER?
LAYER
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
LINE-TO-LINE SPACING
LAYER
SPACING_RULE_SET
WEIGHT
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
LINE-TO-LINE SPACING
LAYER
SPACING_RULE_SET
WEIGHT
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
LINE-TO-LINE SPACING
LAYER
SPACING_RULE_SET
WEIGHT
TABLE_SPACING_RULE_HEAD
MINIMUM LINE WIDTH
ALLOW ROUTE ON LAYER?
LAYER
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTH
ALLOW ROUTE ON LAYER?
LAYER
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTH
ALLOW ROUTE ON LAYER?
LAYER
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
LINE-TO-LINE SPACING
LAYER
SPACING_RULE_SET
WEIGHT
TABLE_SPACING_RULE_HEAD
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER
SIZE
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R
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SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
SIO Signal Constraints
SOURCE: Calpella Platform Design Guide for Ibex Peak M (DG-398905-398905_v1.5), Section 3.15
SPI Interface Constraints
SMBus Interface Constraints
PHYSICAL
LPC Bus Constraints
SPACING
ELECTRICAL_CONSTRAINT_SET
HD Audio Interface Constraints
PCH Net Properties
NET_TYPE
SOURCE: Calpella Platform Design Guide for Ibex Peak M (DG-398905-398905_v1.5), Section 3.15
I235
I236
I237 I238
I239 I240
I241
I242 I243
I244
I245 I246
I247
I248 I249
I250
SYNC_MASTER=K17_REF
SYNC_DATE=06/15/2009
PCH Constraints 2
*
LPC
6 MIL
?
CLK_LPC
8 MIL
*
?
*
=50_OHM_SE =50_OHM_SE =50_OHM_SE
HDA_50S
=STANDARD=STANDARD
=50_OHM_SE
=50_OHM_SE=50_OHM_SE=50_OHM_SE
LPC_50S
* =STANDARD
=50_OHM_SE
=STANDARD
=50_OHM_SE=50_OHM_SE=50_OHM_SE
CLK_LPC_50S
* =STANDARD
=50_OHM_SE
=STANDARD
SMB_50S
=50_OHM_SE
=STANDARD* =STANDARD
=50_OHM_SE =50_OHM_SE=50_OHM_SE
*
?
SMB
=2x_DIELECTRIC
?
=2x_DIELECTRIC
HDA
*
8 MIL
*
CLK_SLOW
?
=55_OHM_SE=55_OHM_SE =55_OHM_SE
=STANDARD*
=55_OHM_SE
CLK_SLOW_55S
=STANDARD
* =STANDARD =STANDARD
=55_OHM_SE
SPI_55S
=55_OHM_SE=55_OHM_SE=55_OHM_SE
8 MIL
?
SPI
*
HDA_SDOUT
HDA_50S
HDA
HDA_SDOUT
HDA_50S
HDA
AUD_SDI_R
HDA_SDIN0
HDA_50S
HDA
HDA_SDIN0
HDA_50S
HDA
HDA_RST_L
PM_SUS_CLK
CLK_SLOWCLK_SLOW_55S
PM_CLK32K_SUSCLK
SPI_55SSPI_CLK
SPI
SPI_CLK_R SPI_CLK
SPI_55S
SPI
SPI_MOSI
SPI_55S
SPI_MOSI_R
SPI
SPI_MISO
SPI_55S
SPI
SPI_MISO
PCIEPCIE_85D
PCIE_ENET_R2D
PCIE_ENET_R2D_C_P
PCIEPCIE_85D
PCIE_ENET_D2R_C_N
PCIE
PCIE_FW_R2D
PCIE_85D
PCIE_FW_R2D_C_P
MCP_PE3_REFCLK
CLK_PCIE_90D
NC_PCIE_CLK100M_EXCARD_P
CLK_PCIE
HDA_50S
HDA_RST_R_L
HDA
HDA_RST_L
CPU_27P4S
CPU_COMP
PCH_VSS_NCTF<29>
PCIEPCIE_85D
PCIE_FW_D2R_C_P
PCIEPCIE_85D
PCIE_FW_R2D_C_N
PCIE_85D PCIE
PCIE_AP_R2D_C_P
PCIE_AP_R2D
PCIE_85D PCIE
CONN_PCIE_AP_D2R_N
PCIEPCIE_85D
PCIE_ENET_D2R_C_P
SPI
SPI_55S
SPI_CS0_L
SPI_55S
SPI_MOSI
SPI
SMBUS_PCH_CLK
SMBUS_PCH_CLK
SMB_50S
SMB
SMBUS_PCH_DATA
SMBUS_PCH_DATA
SMB_50S
SMB
PCIEPCIE_85D
PCIE_ENET_R2D_P
HDA_50S
HDA
HDA_SDOUT_R
HDA_SYNC
HDA_50S
HDA_SYNC
HDA
HDA_50S
HDA_BIT_CLK_R
HDA
LPC_50S
LPC
LPCPLUS_RESET_L
LPC_RESET_L
SMBUS_PCH_0_DATA
SMB
SMB_50S
SML_PCH_0_DATA
LPC_50S
LPC_AD
LPC
LPC_AD<3..0>
MCP_LPC_CLK0
CLK_LPC_50S
LPC_CLK33M_SMC_R
CLK_LPC
MCP_PE2_REFCLK
CLK_PCIE_90D
PCIE_CLK100M_FW_P
CLK_PCIE
CLK_PCIE_90D
PCIE_CLK100M_AP_N
CLK_PCIE
PCIEPCIE_85D
CONN_PCIE_AP_R2D_N
PCIE_85D PCIE
CONN_PCIE_AP_D2R_P
PCIE_AP_D2R
PCIE_85D PCIE
PCIE_FW_D2R_C_N
PCIEPCIE_85D
PCIE_FW_D2R_N
PCIE_FW_D2R
PCIEPCIE_85D
PCIE_FW_D2R_P
PCIE_85D PCIE
PCIE_FW_R2D_N
PCIE_85D PCIE
PCIE_FW_R2D_P
PCIE_85D PCIE
PCIE_AP_D2R_N
PCIEPCIE_85D
PCIE_AP_D2R_P
PCIE_AP_D2R
PCIE_85D PCIE
PCIE_AP_R2D_C_N
PCIEPCIE_85D
PCIE_AP_R2D_N
PCIEPCIE_85D
PCIE_AP_R2D_P
PCIEPCIE_85D
PCIE_ENET_D2R_N
PCIEPCIE_85D
PCIE_ENET_D2R
PCIE_ENET_D2R_P
PCIEPCIE_85D
PCIE_ENET_R2D_C_N
PCIEPCIE_85D
PCIE_ENET_R2D_N
SPI_CS0
SPI
SPI_55S
SPI_CS0_R_L
HDA_50S
HDA
HDA_SYNC_R
HDA_BIT_CLK
HDA_50S
HDA
HDA_BIT_CLK
SMBUS_PCH_1_DATA
SML_PCH_1_DATA
SMB_50S
SMB
SMBUS_PCH_1_CLK
SML_PCH_1_CLK
SMB_50S
SMB
SMB_50S
SMBUS_PCH_0_CLK
SMB
SML_PCH_0_CLK
CLK_LPC_50S
LPC_CLK33M_LPCPLUS
CLK_LPC
CLK_LPC_50S
LPC_CLK33M_SMC
CLK_LPC
LPC_FRAME_L
LPC_50S
LPC
LPC_FRAME_L
CLK_PCIE
PEG_CLK100M_P
MCP_PE0_REFCLK
CLK_PCIE_90D
PCIEPCIE_85D
CONN_PCIE_AP_R2D_P
PCIE_AP_R2D
MCP_PE1_REFCLK
CLK_PCIE_90D
PCIE_CLK100M_AP_P
CLK_PCIE
CLK_PCIECLK_PCIE_90D
PCIE_CLK100M_ENET_N
PCIE_CLK100M_ENET
PCIE_CLK100M_ENET_P
CLK_PCIECLK_PCIE_90D
CPU_27P4S
CPU_COMP
PCH_VSS_NCTF<1>
CPU_COMP
CPU_27P4S
PCH_VSS_NCTF<9>
CPU_COMP
CPU_27P4S
PCH_VSS_NCTF<12>
CPU_COMP
CPU_27P4S
PCH_VSS_NCTF<15>
CPU_COMP
CPU_27P4S
PCH_VSS_NCTF<2>
CPU_27P4S
CPU_COMP
PCH_VSS_NCTF<5>
CPU_COMP
CPU_27P4S
PCH_VSS_NCTF<11>
CPU_COMP
CPU_27P4S
PCH_VSS_NCTF<17>
CPU_COMP
CPU_27P4S
PCH_VSS_NCTF<19>
CPU_COMP
CPU_27P4S
PCH_VSS_NCTF<9>
CPU_27P4S
CPU_COMP
TP_PCH_VSS_NCTF<7>
NC_PCIE_CLK100M_EXCARD_N
CLK_PCIE_90D CLK_PCIE
CLK_PCIE_90D
PCIE_CLK100M_FW_N
CLK_PCIE
PEG_CLK100M_N
CLK_PCIECLK_PCIE_90D
CPU_27P4S
CPU_COMP
PCH_VSS_NCTF<21>
CPU_COMP
CPU_27P4S
PCH_VSS_NCTF<22>
CPU_27P4S
CPU_COMP
PCH_VSS_NCTF<27>
CPU_COMP
CPU_27P4S
PCH_VSS_NCTF<25>
103 OF 132
<E4LABEL>
<SCH_NUM>
<BRANCH>
94 OF 101
17 58
58
17 58
17 58
18 46
17 47
47
17 47
17 47
17 37
37
17 39
8
17
17
6
20
39
17 39
17 33
37
47
47
17 25 26 28 30 32 42 47 48 63 88
17 25 26 28 30 32 42 47 48 63 88
37
17
17 58
17
6
27 47 87
17 48
6
17 45 47 87
19 27
17 39
17 33
39
17 39
17 39
39
39
6
17 33
6
17 33
17 33
6
33
6
33
17 37
17 37
17 37
37
17 47
17
17 58
17 48
17 48
17 48
6
27 47
27 45
6
17 45 47 87
17 74
17 33
17 37
17 37
6
20
6
20 94
6
20
6
20
6
20
6
20
6
20
6
20
6
20
6
20 94
20
8
17
17 39
17 74
6
20
20
6
20
6
20
Page 95
LINE-TO-LINE SPACING
LAYER
SPACING_RULE_SET
WEIGHT
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTH
ALLOW ROUTE ON LAYER?
LAYER
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_SPACING_RULE_ITEM
MINIMUM LINE WIDTH
ALLOW ROUTE ON LAYER?
LAYER
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
LINE-TO-LINE SPACING
LAYER
SPACING_RULE_SET
WEIGHT
TABLE_SPACING_RULE_HEAD
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER
SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
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PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
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B
C
345678
D
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8 7 5 4 2 1
SOURCE: Broadcom 5764-DS04-RDS Page 38
SOURCE: Broadcom 5764-DS04-RDS Page 38
CAESAR II (Ethernet PHY) Constraints
CAESAR II (Ethernet) Constraints
Ethernet Net Properties
SPACING
PHYSICAL
NET_TYPE
ELECTRICAL_CONSTRAINT_SET
Ethernet Constraints
SYNC_MASTER=K17_REF
SYNC_DATE=06/15/2009
* =STANDARD=STANDARD
=50_OHM_SE=50_OHM_SE=50_OHM_SE
=50_OHM_SE
ENET_50S
ENET_3X
?
*
=3:1_SPACING
ENET_100D
=100_OHM_DIFF =100_OHM_DIFF
=100_OHM_DIFF=100_OHM_DIFF=100_OHM_DIFF
*
=100_OHM_DIFF
ENET_MDI
0.6 MM
*
?
ENET_100D
ENET_MDI_N<3..0>
ENET_MDI
ENET_100D
ENET_MDI
ENET_MDI_P<3..0>
ENET_MDI
BCM5764_CLK25M_XTALO
ENET_3X
ENET_50S
ENET_50S
BCM5764_CLK25M_XTALI
ENET_3X
ENET_3X
ENET_RESET_L
ENET_50S
104 OF 132
<E4LABEL>
<SCH_NUM>
<BRANCH>
95 OF 101
37 38
37 38
27 37
27 37
27 37
Page 96
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER
SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
MINIMUM LINE WIDTH
ALLOW ROUTE ON LAYER?
LAYER
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
LINE-TO-LINE SPACING
LAYER
SPACING_RULE_SET
WEIGHT
TABLE_SPACING_RULE_HEAD
Port 2 Not Used
PHYSICAL
FireWire Interface Constraints
NET_TYPE
SPACING
FireWire Net Properties
ELECTRICAL_CONSTRAINT_SET
=110_OHM_DIFF
*
=110_OHM_DIFF
=110_OHM_DIFF =110_OHM_DIFF
FW_110D
=110_OHM_DIFF =110_OHM_DIFF
FW_TP
?
=3:1_SPACING
*
SYNC_DATE=06/15/2009
SYNC_MASTER=K17_REF
FireWire Constraints
FW_TP
FW_110D
NC_FW0_TPAP
FW_P0_TPA
FW_110D
FW_TP
NC_FW0_TPAN
FW_P0_TPA
FW_110D
FW_TP
NC_FW0_TPBP
FW_P0_TPB
FW_110D
FW_TP
NC_FW0_TPBN
FW_P0_TPB
FW_PORT1_TPB_N
FW_110D
FW_TP
FW_P1_TPB
FW_PORT1_TPB_P
FW_110D
FW_TP
FW_P1_TPB
FW_PORT1_TPA_N
FW_110D
FW_TP
FW_P1_TPA
FW_PORT1_TPA_P
FW_110D
FW_TP
FW_P1_TPA
105 OF 132
<E4LABEL>
<SCH_NUM>
<BRANCH>
96 OF 101
6
39 41
39 41
6
39 41
6
39 41
39 40 41
39 40 41
39 40 41
39 40 41
Page 97
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTH
ALLOW ROUTE ON LAYER?
LAYER
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER
SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
SMBus Charger Net Properties
ELECTRICAL_CONSTRAINT_SET
NET_TYPE
PHYSICAL
SPACING
SMC SMBus Net Properties
SPACING
PHYSICAL
NET_TYPE
ELECTRICAL_CONSTRAINT_SET
SYNC_DATE=06/15/2009
SYNC_MASTER=K17_REF
SMC Constraints
1TO1_DIFFPAIR
=STANDARD =STANDARD
* 0.1 MM0.1 MM
=STANDARD=STANDARD
SMB_50S
SMBUS_SMC_B_S0_SDA
SMBUS_SMC_B_S0_SDA
SMB
SMB_50S
SMB
SMBUS_SMC_0_S0_SCL
SMBUS_SMC_0_S0_SCL
SMB_50S
SMB
SMBUS_SMC_0_S0_SDA
SMBUS_SMC_0_S0_SDA
SMB_50S
SMBUS_SMC_BSA_SCL
SMBUS_SMC_BSA_SCL
SMB
SMB_50S
SMBUS_SMC_MGMT_SCL
SMBUS_SMC_MGMT_SCL
SMB
SMB_50S
SMBUS_SMC_MGMT_SDA
SMBUS_SMC_MGMT_SDA
SMB
SMB_50S
SMB
SMBUS_SMC_BSA_SDA
SMBUS_SMC_BSA_SDA
1TO1_DIFFPAIR
CHGR_CSI_N
CHGR_CSI
1TO1_DIFFPAIR
CHGR_CSI_P
CHGR_CSO
1TO1_DIFFPAIR
CHGR_CSO_P
1TO1_DIFFPAIR
CHGR_CSO_N
SMB_50S
SMBUS_SMC_B_S0_SCL
SMBUS_SMC_B_S0_SCL
SMB
SMB_50S
SMB
SMBUS_SMC_A_S3_SDA
SMBUS_SMC_A_S3_SDA
SMB_50S
SMBUS_SMC_A_S3_SCL
SMB
SMBUS_SMC_A_S3_SCL
106 OF 132
<E4LABEL>
<SCH_NUM>
<BRANCH>
97 OF 101
45 48 51
45 48 51 81
45 48 51 81
6
45 48 64 65
45 48 56
45 48 56
6
45 48 64 65
65
65
65
65
45 48 51
6
33 45 48 54
6
33 45 48 54
Page 98
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
LINE-TO-LINE SPACING
LAYER
SPACING_RULE_SET
WEIGHT
TABLE_SPACING_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
LINE-TO-LINE SPACING
LAYER
SPACING_RULE_SET
WEIGHT
TABLE_SPACING_RULE_HEAD
LINE-TO-LINE SPACING
LAYER
SPACING_RULE_SET
WEIGHT
TABLE_SPACING_RULE_HEAD
MINIMUM LINE WIDTH
ALLOW ROUTE ON LAYER?
LAYER
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER
SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTH
ALLOW ROUTE ON LAYER?
LAYER
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
MUXGFX Net Properties
SPACING
GDDR3 FB A/B Net Properties
ELECTRICAL_CONSTRAINT_SET ELECTRICAL_CONSTRAINT_SET
(CK505_DOT96)
PHYSICAL
NET_TYPE
SPACING
PHYSICAL
NET_TYPE
SPACING
NET_TYPE
SPACING
PHYSICAL
G96 Net Properties
ELECTRICAL_CONSTRAINT_SET
ELECTRICAL_CONSTRAINT_SET
PHYSICAL
GDDR3 FB C/D Net Properties
NET_TYPE
GDDR3 Frame Buffer Signal Constraints
Digital Video Signal Constraints
LVDS intra-pair matching should be 0.127 mm. Pairs should be within 0.508mm of entire channel. DisplayPort/TMDS intra-pair matching should be 0.127mm. Inter-pair matching should be within 2.54cm. Max Length 241.3mm.
Max length of LVDS/DisplayPort/TMDS traces: 13 inches.
DIsplayPort AUX CH intra-pair matching should be 0.127mm. Max length 330.2mm.
SOURCE: Calpella SFF DG Rev 1.5 (407364) and Family GPU DG-04202-001-v04.
I138
I139
I142
I143
I144
I145
I148
I149
I152
I153
I155
I157
I158
I159
I160
I161
I182
I183
I184
I185
I190
I191
I192
I193
I194
I195
I196
I197
I198
I199
I200
I201
I202
I203
I204I205
I206
I207
I208 I209
I210
I211
=STANDARD=STANDARD
0.095 MM
=40_OHM_SE=40_OHM_SE
*
GDDR3_40SE
=40_OHM_SE
SYNC_DATE=06/15/2009
SYNC_MASTER=K17_REF
GPU (GT216) CONSTRAINTS
LVDS
TOP,BOTTOM
=4x_DIELECTRIC
?
DISPLAYPORT
TOP,BOTTOM
=4x_DIELECTRIC
?
LVDS
*
=3x_DIELECTRIC
?
DISPLAYPORT
*
=3x_DIELECTRIC
?
=85_OHM_DIFF=85_OHM_DIFF
=85_OHM_DIFF =85_OHM_DIFF
LVDS_85D
=85_OHM_DIFF
*
=85_OHM_DIFF
=85_OHM_DIFF=85_OHM_DIFF
=85_OHM_DIFF =85_OHM_DIFF
DP_85D
=85_OHM_DIFF
*
=85_OHM_DIFF
GDDR3_DATA
*
=2.5:1_SPACING
?
GDDR3_DQS
*
=2.5:1_SPACING
?
=85_OHM_DIFF=85_OHM_DIFF
0.095 MM
=85_OHM_DIFF
GDDR3_80D
=85_OHM_DIFF
*
=85_OHM_DIFF
GDDR3_CMD
*
?
=2.5:1_SPACING
GDDR3_CLK
*
=2.5:1_SPACING
?
=STANDARD=STANDARD
0.095 MM
12.7 MM
GDDR3_40R55SE
=40_OHM_SE
*
=55_OHM_SE
GDDR3_CMD
FB_A_CMD
GDDR3_40SE
FB_A_LMA<5..2>
GDDR3_DATA
FB_A_DQM_L<0>
FB_A_DQM0
GDDR3_40SE
FB_B_LCAS_L
FB_CD_CMD GDDR3_CMD
GDDR3_40R55SE
FB_AB_CMD
FB_A_LCAS_L
GDDR3_CMD
GDDR3_40R55SE
GDDR3_40R55SE
GDDR3_CMDFB_CD_CMD
FB_B_UCAS_L
GDDR3_CLK
FB_B_CLK
FB_A_CLK_P<1>
GDDR3_80D
GDDR3_CLK
FB_A_CLK_N<1>
GDDR3_80D
GDDR3_40R55SE
GDDR3_CMDFB_CD_CMD
FB_B_MA<1..0>
GDDR3_40R55SE
GDDR3_CMDFB_CD_CMD
FB_B_BA<2..0>
GDDR3_40R55SE
GDDR3_CMDFB_CD_CMD
FB_B_MA<12..6>
GDDR3_40R55SE
GDDR3_CMDFB_CD_CMD
FB_B_RAS_L
FB_B_CLK_P<1>
GDDR3_CLKGDDR3_80D
FB_D_CLK
FB_B_CLK_N<1>
GDDR3_CLKGDDR3_80D
GDDR3_40SE
GDDR3_DQS
FB_A_WDQS<2>
FB_A_WDQS2
GDDR3_DQS
FB_A_WDQS1 GDDR3_40SE
FB_A_WDQS<1>
GDDR3_CMD
FB_B_CMD
GDDR3_40SE
FB_A_UMA<5..2>
GDDR3_DQS
FB_A_RDQS<6>
FB_B_RDQS2 GDDR3_40SE
FB_A_RDQS<4>
FB_B_RDQS0
GDDR3_DQS
GDDR3_40SE
GDDR3_DQS
FB_A_WDQS<6>
FB_B_WDQS2 GDDR3_40SE
FB_A_WDQS<4>
GDDR3_DQS
FB_B_WDQS0 GDDR3_40SE
FB_A_DQM_L<3>
GDDR3_DATA
FB_A_DQM3
GDDR3_40SE
FB_A_DQ<47..40>
GDDR3_DATAGDDR3_40SE
FB_B_DQ_BYTE1
LVDS_85D
LVDS_EG_A_CLK_P
LVDS
LVDS_EG_A_CLK
LVDS_85D
LVDS_EG_B_DATA
LVDS
LVDS_EG_B_DATA_N<2..0>
LVDS_85D LVDS
NC_LVDS_EG_B_DATA_P<3>
LVDS_EG_B_DATA3
LVDS_85D
LVDS_EG_B_DATA
LVDS
LVDS_EG_B_DATA_P<2..0>
CLK_SLOWCLK_SLOW_55S
GPU_CLK27M
CLK_SLOWCLK_SLOW_55S
CK505_CLK27MSS
GPU_CLK27M_SS
LVDS_85D LVDS
LVDS_EG_A_CLK
LVDS_EG_A_CLK_N
LVDS_85D LVDS
LVDS_EG_A_DATA
LVDS_EG_A_DATA_N<2..0>
LVDS_85D LVDS
NC_LVDS_EG_A_DATA_N<3>
LVDS_EG_A_DATA3
DP_85D
DISPLAYPORT
DP_ML
DP_EG_ML_P<3..0>
DP_85D
DISPLAYPORT
DP_ML
DP_EG_ML_N<3..0>
LVDS
LVDS_CONN_B_CLK_F_P
LVDS_85D
LVDS_85D
LVDS_CONN_A_DATA_P<2..0>
LVDS
LVDS_85D LVDS
LVDS_CONN_B_CLK_N
LVDS_85D LVDS
LVDS_CONN_A_CLK_F_P
LVDS
LVDS_CONN_A_CLK_F_N
LVDS_85D
DP_85D
DISPLAYPORT
DP_AUX_CH
DP_AUX_CH_C_N
FB_B_CLK_P<0>
GDDR3_CLKGDDR3_80D
FB_C_CLK
GDDR3_CMD
GDDR3_40R55SE
FB_A_BA<2..0>
FB_AB_CMD
GDDR3_CMD
GDDR3_40R55SE
FB_A_MA<12..6>
FB_AB_CMD
GDDR3_CLK
FB_A_CLK
FB_A_CLK_P<0>
GDDR3_80D
FB_B_CLK_N<0>
GDDR3_CLKGDDR3_80D
GDDR3_40R55SE
GDDR3_CMD
FB_B_WE_L
FB_CD_CMD
GDDR3_40R55SE
GDDR3_CMD
FB_B_UCKE
FB_CD_CMD_PD
LVDS_85D LVDS
LVDS_A_CLK
LVDS_A_CLK_N
LVDS_85D LVDS
LVDS_B_DATA
LVDS_B_DATA_P<2..0>
LVDS_85D LVDS
LVDS_B_DATA
LVDS_B_DATA_N<2..0>
LVDS_85D LVDS
LVDS_A_CLK
LVDS_A_CLK_P
DP_85D
DISPLAYPORT
DP_AUX_CH
DP_EG_AUX_CH_P
DP_85D
DISPLAYPORT
DP_EG_AUX_CH_C_N
DP_85D
DISPLAYPORT
DP_EG_AUX_CH_C_P
DP_85D
DISPLAYPORT
DP_AUX_CH
DP_EG_AUX_CH_N
GDDR3_CMD
GDDR3_40R55SE
FB_AB_CMD
FB_A_MA<1..0>
GDDR3_CMD
GDDR3_40R55SE
FB_AB_CMD
FB_A_RAS_L
GDDR3_40R55SE
FB_B_DRAM_RST
FB_CD_CMD_PD
GDDR3_CMD
FB_B_LMA<5..2>
GDDR3_CMD
FB_C_CMD
GDDR3_40SE
FB_B_UMA<5..2>
GDDR3_CMD
FB_D_CMD
GDDR3_40SE
FB_B_WDQS<0>
GDDR3_DQS
FB_C_WDQS0 GDDR3_40SE
FB_B_WDQS<3>
GDDR3_DQS
GDDR3_40SEFB_C_WDQS3
FB_B_WDQS<2>
GDDR3_DQS
GDDR3_40SEFB_C_WDQS2
FB_B_RDQS<1>
GDDR3_DQS
GDDR3_40SEFB_C_RDQS1
FB_B_RDQS<0>
GDDR3_DQS
GDDR3_40SEFB_C_RDQS0
FB_B_DQ<23..16>
GDDR3_DATA
FB_C_DQ_BYTE2
GDDR3_40SE
FB_B_DQM_L<0>
GDDR3_DATA
FB_C_DQM0
GDDR3_40SE
FB_B_DQ<31..24>
GDDR3_DATA
FB_C_DQ_BYTE3
GDDR3_40SE
FB_B_DQM_L<2>
GDDR3_DATA
FB_C_DQM2
GDDR3_40SE
FB_B_WDQS<7>
GDDR3_DQS
FB_D_WDQS3 GDDR3_40SE
FB_B_RDQS<5>
GDDR3_DQS
FB_D_RDQS1 GDDR3_40SE
FB_B_DQM_L<6>
GDDR3_DATA
FB_D_DQM2
GDDR3_40SE
GDDR3_40SE
FB_B_DQM_L<5>
GDDR3_DATA
FB_D_DQM1
FB_B_DQM_L<7>
GDDR3_DATAGDDR3_40SE
FB_D_DQM3
FB_B_RDQS<7>
GDDR3_DQS
FB_D_RDQS3 GDDR3_40SE
FB_B_RDQS<6>
GDDR3_DQS
FB_D_RDQS2 GDDR3_40SE
FB_D_DQ_BYTE1
FB_B_DQ<47..40>
GDDR3_DATAGDDR3_40SE
FB_B_DQ<39..32>
GDDR3_DATA
FB_D_DQ_BYTE0
GDDR3_40SE
FB_B_DQ<55..48>
GDDR3_DATA
FB_D_DQ_BYTE2
GDDR3_40SE
FB_B_DQ<63..56>
GDDR3_DATA
FB_D_DQ_BYTE3
GDDR3_40SE
FB_B_DQM_L<4>
GDDR3_DATA
FB_D_DQM0
GDDR3_40SE
FB_B_DQ<15..8>
GDDR3_DATA
FB_C_DQ_BYTE1
GDDR3_40SE
FB_B_DQM_L<3>
GDDR3_DATA
FB_C_DQM3
GDDR3_40SE
FB_B_WDQS<5>
GDDR3_DQS
FB_D_WDQS1 GDDR3_40SE
GDDR3_40R55SE
FB_B_LCS0_L
GDDR3_CMDFB_CD_CS0
GDDR3_40R55SE
FB_B_LCKE
GDDR3_CMD
FB_CD_CMD_PD
GDDR3_DQS
FB_A_RDQS<1>
FB_A_RDQS1 GDDR3_40SE
GDDR3_DQS
FB_A_RDQS<2>
FB_A_RDQS2 GDDR3_40SE
FB_A_DQ<7..0>
GDDR3_DATA
FB_A_DQ_BYTE0
GDDR3_40SE
FB_A_DQM_L<2>
FB_A_DQM2
GDDR3_40SE GDDR3_DATA
GDDR3_DQS
FB_A_RDQS<5>
FB_B_RDQS1 GDDR3_40SE
GDDR3_CLK
FB_A_CLK_N<0>
GDDR3_80D
FB_A_UCAS_L
GDDR3_CMD
GDDR3_40R55SE
FB_AB_CMD
GDDR3_CMD
FB_A_WE_L
GDDR3_40R55SE
FB_AB_CMD
GDDR3_DQS
FB_A_WDQS<5>
FB_B_WDQS1 GDDR3_40SE
GDDR3_DQS
FB_A_WDQS<7>
FB_B_WDQS3 GDDR3_40SE
FB_A_DQ<39..32>
GDDR3_DATAGDDR3_40SE
FB_B_DQ_BYTE0
FB_A_DQ<31..24>
FB_A_DQ_BYTE3
GDDR3_DATAGDDR3_40SE
GDDR3_DATA
FB_A_DQ<23..16>
FB_A_DQ_BYTE2
GDDR3_40SE
GDDR3_DATA
FB_A_DQ_BYTE1
FB_A_DQ<15..8>
GDDR3_40SE
GDDR3_DQS
FB_A_RDQS<0>
FB_A_RDQS0 GDDR3_40SE
GDDR3_40SE
GDDR3_DQS
FB_A_WDQS<3>
FB_A_WDQS3
GDDR3_CMD
FB_A_LCKE
GDDR3_40R55SE
FB_AB_CMD_PD
GDDR3_CMD
FB_A_UCKE
GDDR3_40R55SE
FB_AB_CMD_PD
FB_AB_CS0 GDDR3_CMD
FB_A_LCS0_L
GDDR3_40R55SE
GDDR3_DQS
FB_A_RDQS<3>
FB_A_RDQS3 GDDR3_40SE
LVDS_85D LVDS
LVDS_EG_A_DATA
LVDS_EG_A_DATA_P<2..0>
GDDR3_DQS
FB_A_RDQS<7>
GDDR3_40SEFB_B_RDQS3
FB_A_DQM_L<1>
FB_A_DQM1
GDDR3_40SE GDDR3_DATA
LVDS_85D LVDS
NC_LVDS_EG_A_DATA_P<3>
LVDS_EG_A_DATA3
LVDS_85D LVDS
NC_LVDS_EG_B_DATA_N<3>
LVDS_EG_B_DATA3
GDDR3_DQS
FB_A_WDQS0
FB_A_WDQS<0>
GDDR3_40SE
GDDR3_CMD
FB_A_DRAM_RST
GDDR3_40R55SE
FB_AB_CMD_PD
LVDS_85D LVDS
LVDS_A_DATA
LVDS_A_DATA_P<2..0>
LVDS_85D LVDS
LVDS_A_DATA
LVDS_A_DATA_N<2..0>
LVDS_85D LVDS
LVDS_B_CLK
LVDS_B_CLK_P
LVDS_85D LVDS
LVDS_B_CLK
LVDS_B_CLK_N
LVDS
LVDS_CONN_B_CLK_F_N
LVDS_85D
DP_85D
DISPLAYPORT
DP_AUX_CH
DP_AUX_CH_C_P
FB_B_RDQS<4>
GDDR3_DQS
FB_D_RDQS0 GDDR3_40SE
FB_B_WDQS<6>
GDDR3_DQS
FB_D_WDQS2 GDDR3_40SE
FB_B_WDQS<4>
GDDR3_DQS
FB_D_WDQS0 GDDR3_40SE
FB_B_DQM_L<1>
GDDR3_DATA
FB_C_DQM1
GDDR3_40SE
FB_B_DQ<7..0>
GDDR3_DATA
FB_C_DQ_BYTE0
GDDR3_40SE
FB_B_RDQS<3>
GDDR3_DQS
FB_C_RDQS3 GDDR3_40SE
FB_B_RDQS<2>
GDDR3_DQS
FB_C_RDQS2 GDDR3_40SE
FB_B_WDQS<1>
GDDR3_DQS
FB_C_WDQS1 GDDR3_40SE
GDDR3_DATA
FB_A_DQM_L<7>
FB_B_DQM3
GDDR3_40SE
GDDR3_DATA
FB_A_DQM_L<6>
FB_B_DQM2
GDDR3_40SE
GDDR3_DATA
FB_A_DQM_L<5>
FB_B_DQM1
GDDR3_40SE
GDDR3_DATA
FB_A_DQM_L<4>
FB_B_DQM0
GDDR3_40SE
GDDR3_DATA
FB_A_DQ<63..56>
FB_B_DQ_BYTE3
GDDR3_40SE
GDDR3_DATA
FB_A_DQ<55..48>
FB_B_DQ_BYTE2
GDDR3_40SE
DP_85D
DISPLAYPORT
DP_ML_CONN_N<3..0>
DP_85D
DISPLAYPORT
DP_ML
DP_ML_CONN_P<3..0>
DP_85D
DISPLAYPORT
DP_ML_N<3..0>
DP_85D
DISPLAYPORT
DP_ML
DP_ML_P<3..0>
DP_85D
DISPLAYPORT
DP_ML_C_N<3..0>
DP_85D
DISPLAYPORT
DP_ML
DP_ML_C_P<3..0>
LVDS_85D LVDS
LVDS_CONN_B_DATA_N<2..0>
LVDS_85D LVDS
LVDS_CONN_B_DATA_P<2..0>
LVDS_85D LVDS
LVDS_CONN_B_CLK_P
LVDS_85D LVDS
LVDS_CONN_A_DATA_N<2..0>
LVDS_85D LVDS
LVDS_CONN_A_CLK_N
LVDS
LVDS_CONN_A_CLK_P
LVDS_85D
107 OF 132
<E4LABEL>
<SCH_NUM>
<BRANCH>
98 OF 101
76 77
76 77
76 78
76 77
76 78
76 77
76 77
76 78
76 78
76 78
76 78
76 78
76 78
76 77
76 77
76 77
76 77
76 77
76 77
76 77
76 77
76 77
81 87
81 87
80 81
81 87
27 79 80
79 80
81 87
81 87
80 81
81 84
81 84
6
83
6
83 84
83 84
6
83
6
83
84 85
76 78
76 77
76 77
76 77
76 78
76 78
76 78
84 87
84 87
84 87
84 87
81 84
84
84
81 84
76 77
76 77
76 78
76 78
76 78
76 78
76 78
76 78
76 78
76 78
76 78
76 78
76 78
76 78
76 78
76 78
76 78
76 78
76 78
76 78
76 78
76 78
76 78
76 78
76 78
76 78
76 78
76 78
76 78
76 78
76 78
76 77
76 77
76 77
76 77
76 77
76 77
76 77
76 77
76 77
76 77
76 77
76 77
76 77
76 77
76 77
76 77
76 77
76 77
76 77
76 77
81 87
76 77
76 77
80 81
80 81
76 77
76 77
84 87
84 87
84 87
84 87
6
83
84 85
76 78
76 78
76 78
76 78
76 78
76 78
76 78
76 78
76 77
76 77
76 77
76 77
76 77
76 77
85
85
84 85
84 85
85
85
6
83 84
6
83 84
83 84
6
83 84
83 84
83 84
Page 99
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
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REVISION
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SHEET
PAGE TITLE
C
A
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PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
MINIMUM LINE WIDTH
ALLOW ROUTE ON LAYER?
LAYER
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
LINE-TO-LINE SPACING
LAYER
SPACING_RULE_SET
WEIGHT
TABLE_SPACING_RULE_HEAD
LINE-TO-LINE SPACING
LAYER
SPACING_RULE_SET
WEIGHT
TABLE_SPACING_RULE_HEAD
AREA_TYPE
SPACING_RULE_SET
NET_SPACING_TYPE1 NET_SPACING_TYPE2
TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE
TABLE_PHYSICAL_RULE_ITEM
OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE
TABLE_PHYSICAL_RULE_ITEM
OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE
TABLE_PHYSICAL_RULE_ITEM
OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE
TABLE_PHYSICAL_RULE_ITEM
LINE-TO-LINE SPACING
LAYER
SPACING_RULE_SET
WEIGHT
TABLE_SPACING_RULE_HEAD
OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
AREA_TYPE
SPACING_RULE_SET
NET_SPACING_TYPE1 NET_SPACING_TYPE2
TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
AREA_TYPE
SPACING_RULE_SET
NET_SPACING_TYPE1 NET_SPACING_TYPE2
TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTH
ALLOW ROUTE ON LAYER?
LAYER
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_ASSIGNMENT_ITEM
TABLE_PHYSICAL_ASSIGNMENT_ITEM
TABLE_PHYSICAL_ASSIGNMENT_ITEM
TABLE_PHYSICAL_ASSIGNMENT_ITEM
PHYSICAL_RULE_SET
AREA_TYPE
NET_PHYSICAL_TYPE
TABLE_PHYSICAL_ASSIGNMENT_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
LINE-TO-LINE SPACING
LAYER
SPACING_RULE_SET
WEIGHT
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
AREA_TYPE
SPACING_RULE_SET
NET_SPACING_TYPE1 NET_SPACING_TYPE2
TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
MINIMUM LINE WIDTH
ALLOW ROUTE ON LAYER?
LAYER
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
AREA_TYPE
SPACING_RULE_SET
NET_SPACING_TYPE1 NET_SPACING_TYPE2
TABLE_SPACING_ASSIGNMENT_HEAD
K18 Specific Net Properties
(USB_EXTA) (USB_EXTA) (USB_EXTA)
ELECTRICAL_CONSTRAINT_SET
PHYSICAL
NET_TYPE
SPACING SPACING
NET_TYPE
PHYSICAL
(USB_EXTA)
Allow 0.127 mm necks for >0.127 mm lines for ARD fanout.
Memory Constraint Relaxations
Alternate diffpair width/gap through BGA fanout areas (95-ohm diff)
Graphics ,SATA Constraint Relaxations
ELECTRICAL_CONSTRAINT_SET
K18 Specific Net Properties
I249
I250
I251
I252
I253
I254
I255
I256
I281
I282 I283
I284
I285 I286
I287
I288
I291
I292
GND_P2MM
GND
*
CPU_VCCSENSE
GND_P2MM
USB GND
*
*
PCIE
GND_P2MM
GND
* ?
THERM
=2:1_SPACING
LVDS
GND
GND_P2MM
*
* ?
SENSE
=2:1_SPACING
*
?
AUDIO
=2:1_SPACING
* ?
25 MILS
ENETCONN
1000
*
GND_P2MM
0.20 MM
GND =STANDARD
?*
1000
*
PWR_P2MM
0.20 MM
LVDS_85DLVDS_85D
BGA
BGA
100_DIFF_BGA
DP_85D
SATA_90D
BGA
100_DIFF_BGA
CLK_PCIE_90D 100_DIFF_BGA
BGA
0.1 MMTOP
MEM_85D 6.35 MM
MEM_72D 6.35 MM
0.127 MM
BOTTOM
USB
SB_POWER
*
PWR_P2MM
SB_POWER
*
PWR_P2MM
SATA
ENET_MDI
*
GND_P2MM
GND
*
CLK_PCIE SB_POWER PWR_P2MM
*
GND
GND_P2MMCPU_COMP
DIFFPAIR
*
=1:1_DIFFPAIR
=1:1_DIFFPAIR =1:1_DIFFPAIR
=1:1_DIFFPAIR
THERM_1TO1_55S
=55_OHM_SE
=1:1_DIFFPAIR
*
=1:1_DIFFPAIR=1:1_DIFFPAIR
=55_OHM_SE =55_OHM_SE
=55_OHM_SE
SENSE_1TO1_55S
=1:1_DIFFPAIR
=55_OHM_SE
*
=1:1_DIFFPAIR=1:1_DIFFPAIR
=55_OHM_SE
0.09 MM 100 MIL
*
MEM_40S
CPU_27P4S
0.23 MM 100 MIL
BOTTOM
0.1 MM
500 MILUSB_85D
TOP
PCIE_85D
*
0.09 MM
10 mm
100 MILMEM_72D
*
0.09 MM
GND_P2MM
MEM_DQS
*
GND
MEM_DATA
GND
*
GND_P2MM
MEM_CTRL
*
GND_P2MM
GND
GND
*
GND_P2MM
MEM_CMD
MEM_CLK
GND
*
GND_P2MM
GND
GND_P2MM
*
SATA
GND_P2MM
*
GND
CLK_PCIE
SYNC_DATE=06/15/2009
SYNC_MASTER=K17_REF
Project Specific Constraints
SATA_90D
SATA_ODD_R2D_UF_P
SATA
SATA_ODD_D2R_UF_N
SATA_90D SATA
THERM
THERM_1TO1_55S
CPUTHMSNS_D2_N
THERM
THERM_1TO1_55S
GPU_TDIODE_N
GFX_ISNS_R_P
SENSE
SENSE_1TO1_55S
SENSE
CPUVTTISNS_R_N
SENSE_DIFFPAIR SENSE_1TO1_55S
CPUVTTISNS_R_P
SENSE
SENSE_1TO1_55S
CPU_THERMD_P
THERM_1TO1_55S
THERM
SENSE_DIFFPAIR
THERM_1TO1_55S
THERM
CPU_THERMD_N
GPUTHMSNS_D_P
THERM
SENSE_DIFFPAIR THERM_1TO1_55S
GPUTHMSNS_D_N
THERM
THERM_1TO1_55S
GPU_TDIODE_P
THERM
SENSE_DIFFPAIR THERM_1TO1_55S
CPUVTTS0_CS_P
SENSE
SENSE_1TO1_55S
ISNS_P1V8GPU_R_N
SENSE_DIFFPAIR
SENSE
SENSE_1TO1_55S
ISNS_P1V8GPU_R_P
SENSE_1TO1_55S
SENSE
ISNS_P1V8GPU_N
SENSE_1TO1_55SSENSE_DIFFPAIR
SENSE
SENSE_1TO1_55S
SENSE
ISNS_P1V8GPU_P
ISNS_ODD_R_P
SENSE_1TO1_55S
SENSE
ISNS_ODD_P
SENSE_1TO1_55S
SENSE
ISNS_ODD_N
SENSE_1TO1_55S
SENSE
SENSE_DIFFPAIR
ISNS_ODD_R_N
SENSE
SENSE_DIFFPAIR SENSE_1TO1_55S
ISNS_HDD_R_N
SENSE_1TO1_55SSENSE_DIFFPAIR
SENSE
SENSE_DIFFPAIR SENSE_1TO1_55S
SENSE
ISNS_CPU_N ISNS_CPU_P
SENSE_1TO1_55S
SENSE
GPUISENS_N
SENSE
SENSE_DIFFPAIR SENSE_1TO1_55S
GPUISENS_P
SENSE
SENSE_1TO1_55S
ISNS_1V5_S3_N
SENSE
SENSE_DIFFPAIR SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
ISNS_1V5_S3_P
ISNS_AIRPORT_P
SENSE
SENSE_1TO1_55S
CPUVTTS0_CS_N
SENSE
SENSE_1TO1_55SSENSE_DIFFPAIR
USB_85D
USB
USB_TPAD_R_N
USB_TPAD_R_P
USB_85D
USB
GFXIMVP_CS_P
SENSE
SENSE_1TO1_55S
GFXIMVP_CS_R_N
SENSE_1TO1_55SSENSE_DIFFPAIR
SENSE
GFXIMVP_CS_R_P
SENSE_1TO1_55S
SENSE
GFX_ISNS_R_N
SENSE_1TO1_55S
SENSE
SENSE_DIFFPAIR
ISNS_AIRPORT_N
SENSE
SENSE_1TO1_55SSENSE_DIFFPAIR
ISNS_AIRPORT_N
SENSE
SENSE_1TO1_55S
ISNS_AIRPORT_P
SENSE
SENSE_1TO1_55SSENSE_DIFFPAIR
ISNS_AIRPORT_R_P
SENSE
SENSE_1TO1_55S
ISNS_AIRPORT_R_N
SENSE_1TO1_55S
SENSE
SENSE_DIFFPAIR
GFXIMVP_CS_N
SENSE_1TO1_55S
SENSE
SENSE_DIFFPAIR
DDRISNS_R_N
SENSE
SENSE_1TO1_55SSENSE_DIFFPAIR
DDRISNS_R_P
SENSE
SENSE_1TO1_55S
SATA_ODD_D2R_UF_P
SATASATA_90D
SATASATA_90D
SATA_HDD_D2R_UF_P
SATASATA_90D
SATA_HDD_D2R_UF_N
SATA
SATA_HDD_R2D_UF_P
SATA_90D
SATA
SATA_HDD_R2D_UF_N
SATA_90D
THERM
THERM_1TO1_55S
CPUTHMSNS_D2_P
SENSE_DIFFPAIR
PCIE_CLK100M_AP_CONN_N
CLK_PCIECLK_PCIE_90D
CHGR_CSI_R_N
1TO1_DIFFPAIR
USB
USB2_EXTA_MUXED_N
USB_85D
USB
USB2_LT1_N
USB_85D
CHGR_CSO_R_N
1TO1_DIFFPAIR
CHGR_CSO_R_P
1TO1_DIFFPAIR
SPKRCONN_S_OUT_N
DIFFPAIR
AUDIO
SPKRCONN_L_OUT_N
DIFFPAIR
AUDIO
DISPLAYPORT
DP_85D
DP_IG_AUX_CH_C_P
DISPLAYPORT
DP_IG_AUX_CH_C_N
DP_85D
SPKRCONN_S_OUT_P
DIFFPAIR
SPK_OUT
AUDIO
SPKRCONN_R_OUT_N
DIFFPAIR
AUDIO
SPKRCONN_R_OUT_P
DIFFPAIR
AUDIO
SPK_OUT
SPKRCONN_L_OUT_P
SPK_OUT
DIFFPAIR
AUDIO
ENETCONN_P<3..0>
ENET_100D
ENETCONN
SB_POWER
PP3V3_S5
PP1V5_S3RS0
SB_POWER
PP3V3_S0
SB_POWER
SENSE_1TO1_55S
SENSE
SENSE_DIFFPAIR
ISNS_LCDBKLT_N
ISNS_HDD_N
SENSE_DIFFPAIR SENSE_1TO1_55S
SENSE
USB
USB2_EXTA_MUXED_P
USB_85D
USB_LT2_N
USB
USB_85D
USB_LT2_P
USB
USB_85D
CONN_USB2_BT_N
USB
USB_85D
CONN_USB2_BT_P
USB
USB_85D
USB2_LT1_P
USB
USB_85D
CHGR_CSI_R_P
1TO1_DIFFPAIR
PCIE_CLK100M_AP
PCIE_CLK100M_AP_CONN_P
CLK_PCIECLK_PCIE_90D
ISNS_LCDBKLT_P
SENSE_1TO1_55S
SENSE
ISNS_HDD_R_P
SENSE_1TO1_55S
SENSE
ISNS_HDD_P
SENSE
SENSE_1TO1_55S
SATA_ODD_R2D_UF_N
SATASATA_90D
ENETCONN_N<3..0>
ENET_100D
ENETCONN
GND
GND
108 OF 132
<E4LABEL>
<SCH_NUM>
<BRANCH>
99 OF 101
42
42
51
51 79 80
50
50
50
9
51
9
51
51
51
51 79 80
50 70
50
50
50
50
56
56
56
49
49
50
50
50 67
50 67
99
50 70
53
53
69
50 69
50 69
50
99
99
99
56
56
69
50
50
42
42
42
42
42
51
6
33
65
43
6
43
49 65
49 65
6
61 62
6
61 62
84
84
6
61 62
6
61 62
6
61 62
6
61 62
38
6 7
17 18 19 20 21 23 27 31 35
57 66 71 72 73 83 85
6 7
13 16 31 42 72 73
6 7
17 18 19 20 21 23 24 25 26
27 28 30 34 37 40 42 46 47 48
50 51 52
54 58 62 63 68 69 72 73 80 83
84
85
87
88
43
6
43
6
43
6
33
6
33
6
43
65
6
33
56
42
38
Page 100
MINIMUM LINE WIDTH
ALLOW ROUTE ON LAYER?
LAYER
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTH
ALLOW ROUTE ON LAYER?
LAYER
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_BOARD_INFO
VERSION
ALLEGRO
(MIL or MM)
BOARD UNITS
BOARD LAYERS
BOARD AREAS
MINIMUM LINE WIDTH
ALLOW ROUTE ON LAYER?
LAYER
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTH
ALLOW ROUTE ON LAYER?
LAYER
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTH
ALLOW ROUTE ON LAYER?
LAYER
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTH
ALLOW ROUTE ON LAYER?
LAYER
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTH
ALLOW ROUTE ON LAYER?
LAYER
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
LINE-TO-LINE SPACING
LAYER
SPACING_RULE_SET
WEIGHT
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
LINE-TO-LINE SPACING
LAYER
SPACING_RULE_SET
WEIGHT
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
AREA_TYPE
SPACING_RULE_SET
NET_SPACING_TYPE1 NET_SPACING_TYPE2
TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
LINE-TO-LINE SPACING
LAYER
SPACING_RULE_SET
WEIGHT
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTH
ALLOW ROUTE ON LAYER?
LAYER
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER
SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTH
ALLOW ROUTE ON LAYER?
LAYER
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTH
ALLOW ROUTE ON LAYER?
LAYER
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTH
ALLOW ROUTE ON LAYER?
LAYER
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTH
ALLOW ROUTE ON LAYER?
LAYER
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTH
ALLOW ROUTE ON LAYER?
LAYER
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
K18 Board-Specific Spacing & Physical Constraints
NOTE: 100_DIFF_BGA is 100-ohms differential impedance on outer layers and 95-ohms on inner layers.
NOTE: 110_DIFF is 110-ohms differential impedance on outer layers and 105-ohms on inner layers.
=STANDARD
=STANDARD
Y*
=STANDARD
27P4_OHM_SE
0.250 MM
0.1 MM
Y
TOP,BOTTOM
27P4_OHM_SE
0.310 MM 0.095 MM
37_OHM_SE
Y
0.095 MM0.185 MM
TOP,BOTTOM
0.090 MM0.155 MM
37_OHM_SE
Y*
=STANDARD
=STANDARD
=STANDARD
0.090 MM
40_OHM_SE
=STANDARD
=STANDARD
Y*
=STANDARD
0.135 MM
0.095 MM0.165 MM
40_OHM_SE
Y
TOP,BOTTOM
0.200 MM0.200 MM
0.175 MM0.175 MM
72_OHM_DIFF
Y
TOP,BOTTOM
Y
0.090 MM0.125 MM
85_OHM_DIFF
TOP,BOTTOM
0.190 MM0.190 MM
0.090 MM0.115 MM
0.230 MM0.230 MM
Y
90_OHM_DIFF
TOP,BOTTOM
0.220 MM
0.089 MM
0.220 MM
Y
0.089 MM
100_OHM_DIFF
TOP,BOTTOM
0.330 MM0.330 MM
Y
0.075 MM0.075 MM
110_OHM_DIFF
TOP,BOTTOM
=STANDARD
=STANDARD
=STANDARD
*
=STANDARD
=STANDARD
N
72_OHM_DIFF
=STANDARD
N
=STANDARD
*
=STANDARD
=STANDARD
=STANDARD
85_OHM_DIFF
0.180 MM 0.180 MM
Y
ISL9,ISL10
85_OHM_DIFF
0.110 MM 0.090 MM
0.180 MM0.180 MM
Y
ISL3,ISL4
85_OHM_DIFF
0.110 MM 0.090 MM
PCB Rule Definitions
SYNC_DATE=06/15/2009
SYNC_MASTER=K17_REF
DEFAULT
0 MM
10 MM
=50_OHM_SE
0 MM
* Y
=50_OHM_SE
STANDARD
?*
=DEFAULT
?
1.5:1_SPACING
*
0.15 MM
0.25 MM
* ?
2.5:1_SPACING
?
0.3 MM
3:1_SPACING
*
0.4 MM
4:1_SPACING
* ?
=DEFAULT
10 MM
Y
=DEFAULT
*
=DEFAULTSTANDARD =DEFAULT
BGA
CLK_PCIE
*
BGA_P2MM
BGA
MEM_CLK
BGA_P2MM
*
**
BGA_P1MM
BGA0.1 MM
DEFAULT
* ?
*
BGA_P1MM
?
=DEFAULT
2X_DIELECTRIC
*
?
0.140 MM
4X_DIELECTRIC
?
*
0.280 MM
3X_DIELECTRIC
?
*
0.210 MM
?*
0.2 MM
2:1_SPACING
BGA_P2MM
* ?
=DEFAULT CLK_SLOW
*
BGA_P2MM
BGA
=STANDARD =STANDARD
0.1 MM 0.1 MM
Y*
1:1_DIFFPAIR
=STANDARD
Y
ISL3,ISL4
72_OHM_DIFF
0.154 MM
0.200 MM 0.200 MM
0.154 MM
Y
ISL9,ISL10
72_OHM_DIFF
0.154 MM
0.200 MM
0.154 MM
0.200 MM
100_DIFF_BGA
0.075 MM
Y
ISL3,ISL4 0.125 MM0.125 MM
0.075 MM
100_DIFF_BGA
=100_OHM_DIFF
=100_OHM_DIFF
*
=100_OHM_DIFF=100_OHM_DIFF
=100_OHM_DIFF=100_OHM_DIFF
100_DIFF_BGA
0.075 MM
ISL9,ISL10
Y
0.125 MM0.125 MM
0.075 MM
N
90_OHM_DIFF
*
=STANDARD
=STANDARD =STANDARD
=STANDARD
=STANDARD
ISL9,ISL10
90_OHM_DIFF
Y
0.220 MM 0.220 MM
0.102 MM 0.090 MM
=STANDARD
100_OHM_DIFF
=STANDARD
N
=STANDARD =STANDARD
*
=STANDARD
ISL9,ISL10
0.080 MM
100_OHM_DIFF
Y
0.200 MM0.200 MM
0.080 MM
ISL3,ISL4
110_OHM_DIFF
Y
0.330 MM0.330 MM
0.075 MM 0.075 MM
* N
110_OHM_DIFF
=STANDARD =STANDARD
=STANDARD
=STANDARD
=STANDARD
ISL9,ISL10
110_OHM_DIFF
0.330 MM
Y
0.330 MM
0.075 MM 0.075 MM
ISL3,ISL4
100_OHM_DIFF
Y
0.080 MM
0.200 MM 0.200 MM
0.080 MM
Y
ISL3,ISL4
90_OHM_DIFF
0.220 MM0.220 MM
0.102 MM 0.090 MM
NO_TYPE,BGA
MM
15.5.1
TOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,ISL8,ISL9,ISL10,ISL11,BOTTOM
=STANDARD=STANDARD
* Y
=STANDARD
0.090 MM0.090 MM
50_OHM_SE
50_OHM_SE
Y
0.095 MM
TOP,BOTTOM
0.110 MM
Y
55_OHM_SE
=STANDARD
*
=STANDARD
=STANDARD
0.076 MM0.076 MM
Y
TOP,BOTTOM
55_OHM_SE
0.090 MM 0.090 MM
109 OF 132
<E4LABEL>
<SCH_NUM>
<BRANCH>
100 OF 101
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