Apple J44 SCHEMATIC

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_HEAD

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_HEAD

TABLE_TABLEOFCONTENTS_ITEM

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

8

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

II NOT TO REPRODUCE OR COPY IT

3

B

7

BRANCH

DRAWING NUMBER

SIZE

D

SHEET

R

DATE

D

A

C

PAGE

A

C

3456

D

B

87

6 5 4 21

12

APPD

CK

3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.

DRAWING TITLE

DESCRIPTION OF REVISION

REV

ECN

REVISION

PROPRIETARY PROPERTY OF APPLE INC.

Schematic / PCB #’s

08/20/2013

J44 MLB-4GB SCHEMATIC

ALIASES RESOLVED

1 OF 78

<PART_DESCRIPTION>

<SCH_NUM>

<ECO_DESCRIPTION>

1 OF 120

LPC+SPI Debug Connector

45

08/12/2013

61

J44

Fan

44

08/12/2013

60

J44

Thermal Sensors

43

08/12/2013

58

J44

Power Sensors: Extended

42

08/12/2013

56

J44

Power Sensors: Load Side

41

08/12/2013

55

J44

Power Sensors: High Side

40

08/12/2013

54

J44

SMBus Connections

39

08/12/2013

53

J44

SMC Project Support

38

08/12/2013

52

J44

SMC Shared Support

37

08/12/2013

51

J44

SMC

36

08/12/2013

50

J44

KEYBOARD/TRACKPAD (2 OF 2)

35

08/12/2013

49

J44

KEYBOARD/TRACKPAD (1 OF 2)

34

08/12/2013

48

J44

External A USB3 Connector

33

08/12/2013

46

J44

Camera 2 of 2

32

08/12/2013

40

J44

Camera 1 of 2

31

08/12/2013

39

J44

SSD Connector

30

08/12/2013

37

J44

WIRELESS SUPPORT

29

08/12/2013

35

J44

DDC Crossbar

28

08/12/2013

34

J44

Thunderbolt Connector B

27

08/12/2013

33

J44

Thunderbolt Connector A

26

08/12/2013

32

J44

Thunderbolt Mobile Support

25

08/12/2013

30

J44

Thunderbolt Host (2 of 2)

24

08/12/2013

29

J44

Thunderbolt Host (1 of 2)

23

08/12/2013

28

J44

DDR3 Termination

22

04/02/2013

27

J44_YONAS-4GB

DDR3 SDRAM BANK B (RANK 0)

21

MASTER

25

MASTER

DDR3 SDRAM Bank A (Rank 0)

20

MASTER

23

MASTER

DDR3 VREF MARGINING

19

08/12/2013

22

J44

Project Chipset Support

18

08/12/2013

20

J44

Chipset Support

17

08/12/2013

19

J44

CPU/PCH Merged XDP

16

08/12/2013

18

J44

PCH GPIO/MISC/LPIO

15

08/12/2013

16

J44

PCH PCIe/USB/LPC/SPI/SMBus

14

08/12/2013

15

J44

PCH PM/PCI/GFX

13

08/12/2013

14

J44

PCH Audio/JTAG/SATA/CLK

12

08/12/2013

13

J44

PCH Decoupling

11

08/12/2013

12

J44

CPU Decoupling

10

08/12/2013

10

J44

CPU/PCH GROUNDS

9

08/12/2013

9

J44

CPU/PCH POWER

8

08/12/2013

8

J44

CPU DDR3/LPDDR3 Interfaces

7

08/12/2013

7

J44

CPU Misc/JTAG/CFG/RSVD

6

08/12/2013

6

J44

CPU GFX/NCTF/RSVD

5

08/12/2013

5

J44

PD Parts

4

08/12/2013

4

J44

BOM Configuration

3

01/03/2013

3

J44

BOM Configuration

2

08/20/2013

2

J44

120

78

Reference

08/12/2013

J44

118

77

Project Specific Constraints

08/12/2013

J44

117

76

SMC Constraints

08/12/2013

J44

116

75

Camera Constraints

08/12/2013

J44

115

74

TBT,DP,HDMI Constraints

08/12/2013

J44

114

73

Memory Constraints

01/03/2013

J44

113

72

PCH Constraints

08/12/2013

J44

112

71

USB Constraints

08/12/2013

J44

111

70

CPU & PCIe Constraints

08/12/2013

J44

110

69

PCB Rule Definitions

08/12/2013

J44

104

68

Functional / ICT Test

08/12/2013

J44

103

67

Memory Bit/Byte Swizzle

01/03/2013

J44

102

66

Signal Aliases

MASTER

100

65

Power Aliases

08/12/2013

J44

97

64

Display Mux: HDMI vs DP

08/12/2013

J44

95

63

RIO Connector

08/12/2013

J44

83

62

eDP Display Connector

08/12/2013

J44

81

61

Power Control

08/12/2013

J44

80

60

Power FETs

08/12/2013

J44

78

59

Misc Power Supplies

08/12/2013

J44

77

58

LCD AND KBD BKLT DRIVER

08/12/2013

J44

76

57

1.05V S0 Power Supply

08/12/2013

J44

75

56

5V / 3.3V Power Supply

08/12/2013

J44

74

55

1.35V DDR3 SUPPLY

08/12/2013

J44

73

54

CPU VR12.5 VCC Power Stage

08/12/2013

J44

72

53

CPU VR12.6 VCC Regulator IC

08/12/2013

J44

71

52

PBus Supply & Battery Charger

08/12/2013

J44

70

51

DC-In & Battery Connectors

08/12/2013

J44

66

50

AUDIO: JACK TRANSLATORS

08/12/2013

J44

65

49

AUDIO: JACK

08/12/2013

J44

64

48

AUDIO: SPEAKER AMP

08/12/2013

J44

63

47

AUDIO:CODEC, DIGITAL

08/12/2013

J44

Contents

SyncPage

Date

(.csa)

Table of Contents

1

01/13/2012

1

D2_KEPLER

Sync

Contents

Page

(.csa)

Date

62

46

AUDIO:CODEC, ANALOG

08/12/2013

J44

SCHEM,MLB-4GB,J44

051-0052 CRITICAL

1

SCH

820-3536 CRITICAL

1

PCB

PCBF,MLB-4GB,J44

w w w . c h i n a f i x . c o m

TABLE_ALT_ITEM

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

TABLE_ALT_ITEM

PART NUMBER

ALTERNATE FOR

PART NUMBER

BOM OPTION

REF DES

COMMENTS:

TABLE_ALT_HEAD

TABLE_ALT_ITEM

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM GROUP

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_ALT_ITEM

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87

6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

PSOC

EFI ROM

SMC

Programmables (All Builds)

TBT

Module Parts

Alternate Parts

BOM Groups

BOM Configuration

SYNC_DATE=08/20/2013

SYNC_MASTER=J44

128S0329128S0311

ALL

NEC alt to Sanyo

ALL

138S0739

138S0706

Samsung alt to Murata Epson alt to NDK197S0480197S0481

ALL

Cyntec alt to Vishay

152S1645

ALL

152S0461

Sanyo 2nd Factory alt

128S0264

ALL

128S0364

353S1286

Maxim alt to Microchip

ALL

353S3452

NXP Alt for Diodes Single

376S1128376S1089

ALL

LOADISNS,OTHERISNS,DDRISNS,TBTISNS,BMONISNS

ENGISNS

ALTERNATE,COMMON,J44_COMMON1,J44_COMMON2,J44_COMMON3,J44_COMMON4,J44_PROGPARTS

J44_COMMON

J44_COMMON1

TBTHV:P15V,SKIP_5V3V3:AUDIBLE,SPI:DUAL_IO

J44_COMMON2

EDP,EDP_LS_CAP,CAMERA_3V3:S0,CAM_WAKE:NO,CAM_XTAL:NO,MEM_ODT:PU,VCORE_FETS

J44_COMMON3

XDP,LPCPLUS,BKLT:PROD,CPUTHRM:ALRT,LOADRC:NO,OTHERRC:NO,DDRRC:NO,TBTRC:NO,BMONRC:NO SMC_PROG:PVT,BOOTROM:PVT,TBTROM:PVT,TPAD_PSOC:PROG

J44_PROGPARTS

376S1194

2

Q7310,Q7320

CRITICAL

VCORE_FET:VSHY

MOSFET,N-CH,30V,15.3A,12M,8P 3.3X3.3 DFN

338S1186

U3900

CRITICAL

1

IC,BCM15700A2,S2 PCIE CAMERA PROCESSOR

HSWULT,SR188,PRQ,C0,2.8,28W,2+3,4M,BGA

CPU_HSW:2.8G

CRITICAL

U0500

337S4598

1

CPU_HSW:2.4G

U0500

CRITICAL337S4596

1

HSWULT,SR18A,PRQ,C0,2.4,28W,2+3,3M,BGA

353S3812

TI alt to NXP

ALL

353S3814

353S4069

ALL

353S4068

NXP alt to TI DP Mux U9750

ALL

353S4070

353S4069

Pericom alt to TI DP Mux U9750

Cyntec alt to TFT

ALL

107S0248107S0250

Rohm alt to Vishay

127S0162

ALL

127S0164

Cyntec alt to TFT

107S0255

ALL

107S0240

TDK alt to Toko

152S1876

ALL

152S1804

Epson alt to TXC

ALL

197S0545

197S0544

NDK alt to TXC

197S0542

197S0544

ALL

Samsung alt to Murata (BKLT)

ALL

138S0846

138S0811

Samsung alt to Murata (BKLT)

ALL

138S0803

138S0639

138S0843

ALL

138S0674

Samsung alt to Murata (BKLT)

Cyntec alt to TFT

107S0241107S0254

ALL

Renesas alt to Vishay

ALL

376S1180

376S0761

376S0855376S1032

ALL

Toshiba alt for Diodes Dual

138S0724138S0725

ALL

Samsung alt to Murata

Diodes alt to Fairchild

376S1053

376S0604

ALL

U2800

CRITICAL

1

338S1247

IC,TBT,FR-4C,A0,PRQ,CIO,SR1JC,FCBGA288

CPU_HSW:2.6G

U0500

CRITICAL337S4597

1

HSWULT,SR189,PRQ,C0,2.6,28W,2+3,3M,BGA

376S1193

Q7311,Q7321

VCORE_FET:VSHY

CRITICAL

2

MOSFET,N-CH,30V,22A,6.0M,8P 3.3X3.3 DFN

Q7310,Q7320

MOSFET,N-CH,25V,30A,9.6M,8P 3.3X3.3 DFN

376S0964

VCORE_FET:REN

CRITICAL

2

Q7311,Q7321

CRITICAL376S1104

MOSFET,N-CH,25V,30A,6.1M,8P 3.3X3.3 DFN

2

VCORE_FET:REN

EPROM,FALCON RIDGE (V13.7) J44

TBTROM:PVT

341S3918

1

CRITICAL

U2890

SMC_PROG:PVT

IC,SMC-B1,EXT(V2.16F39),PVT,J44

341S3922 CRITICAL

U5000

1

BOOTROM:PVT

IC,EFI ROM (V0116),PVT,J44

341S3924

1

CRITICAL

U6100

IC,TRKPD/KYBD PSOC,CU ONLY(V224) J44

1

CRITICAL341S3862

U4801

TPAD_PSOC:PROG

ALL

NXP Alt for Diodes Dual

376S0855376S1129

376S1080

Diodes alt to On Semi

376S0820

ALL

Panasonic alt to TDK

ALL

155S0583155S0667

ONsemi alt to Toshiba

ALL

311S0649

311S0541

ALL

128S0392128S0436

Kemet alt to Sanyo

<SCH_NUM>

2 OF 120

2 OF 78

w w w . c h i n a f i x . c o m

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87

6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

BOM OPTIONS

BOM NAME

BOM NUMBER

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

PART NUMBER

ALTERNATE FOR

PART NUMBER

BOM OPTION

REF DES

COMMENTS:

TABLE_ALT_HEAD

TABLE_ALT_ITEM

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM GROUP

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM GROUP

TABLE_BOMGROUP_HEAD

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM GROUP

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

Alternate Parts

DRAM PARTS

DRAM SPD Straps

NOTE: 1866 PARTS BEING STRAPPED TO RUN AT 1600

13" MBP VARIABLE BOM GROUPS

DEVELOPMENT/BASE BOM

SUB-BOMS

DRAM SPD Straps

DRAM Parts

BOM Variants

J44_COMMON

685-0054

COMMON,MLB-4GB,J44

985-0053

DEV,MLB-4GB,J44

XDP_CONN

CAMDRAM:MICRON

CAMDRAM_TYPE:MICRON

IC,SDRAM,4GBIT,DDR3L-1600,HUMA,96B FBGA

333S0700

CAMDRAM_TYPE:HYNIX_H

1 CRITICALU4000

333S0704

IC,SDRAM,4GBIT,DDR3L-1600,DIE F,96B FBGA

U40001

CAMDRAM_TYPE:ELPIDA

CRITICAL

1 U4000333S0698

IC,SDRAM,4GBIT,DDR3L-1600,REV E,96B FBGA

CAMDRAM_TYPE:MICRON

CRITICAL

CAMDRAM_TYPE:ELPIDA

CAMDRAM:ELPIDA

CAMDRAM_TYPE:HYNIX_H

CAMDRAM:HYNIX_H

639-5275

PCBA,MLB-4GB,2.8G,4GB-HYNIX,J44

BASE_BOM,CPU_HSW:2.8G,RAM_4G_HYNIX_H,CAMDRAM:HYNIX_H

VCORE_FET:VSHY

VCORE,FET,VSHY,J44

685-0074

VCORE_FETS

VCOREFETSVCORE,FET,VSHY,J44

685-0074

1

CRITICAL

985-0053

DEVEL_BOM

CRITICAL

DEVEL1

J44 MLB DEVEL BOM

685-0054 CRITICAL

BASE1

BASE_BOM

J44 MLB COMMON BOM

SMCBOARDID:8

J44_COMMON4

RAM_4G_ELPIDA_1866

4G_ELPIDA_1866,RAMCFG3:L,RAMCFG2:L,RAMCFG1:L,RAMCFG0:L,PPDDR:1V5

RAM_4G_HYNIX_H_1866

4G_HYNIX_H_1866,RAMCFG3:L,RAMCFG2:L,RAMCFG1:L,RAMCFG0:H,PPDDR:1V5

RAM_4G_MICRON_1866

4G_MICRON_1866,RAMCFG3:L,RAMCFG2:L,RAMCFG1:H,RAMCFG0:L,PPDDR:1V5

RAM_4G_MICRON

4G_MICRON,RAMCFG3:L,RAMCFG2:L,RAMCFG1:H,RAMCFG0:L,PPDDR:1V35

RAM_4G_HYNIX_H

4G_HYNIX_H,RAMCFG3:L,RAMCFG2:L,RAMCFG1:L,RAMCFG0:H,PPDDR:1V35

4G_ELPIDA,RAMCFG3:L,RAMCFG2:L,RAMCFG1:L,RAMCFG0:L,PPDDR:1V35

RAM_4G_ELPIDA

4G_MICRON_1866

CRITICAL

IC,SDRAM,4GBIT,256MX16,DDR3-1866,REV E,96FBGA

U2300,U2320,U2340,U2360,U2500,U2520,U2540,U2560

8

333S0720

4G_ELPIDA_1866

CRITICAL

IC,SDRAM,4GBIT,256MX16,DDR3-1866,F DIE,96FBGA

333S0715

U2300,U2320,U2340,U2360,U2500,U2520,U2540,U2560

8

4G_HYNIX_H_1866

CRITICAL

IC,SDRAM,4GBIT,256MX16,DDR3-1866,HUMA,96FBGA

U2300,U2320,U2340,U2360,U2500,U2520,U2540,U2560

8

333S0717

4G_MICRON

CRITICAL

IC,SDRAM,4GBIT,256MX16,DDR3-1600,REV E,96FBGA

333S0698

8

U2300,U2320,U2340,U2360,U2500,U2520,U2540,U2560

4G_ELPIDA

CRITICAL

IC,SDRAM,4GBIT,256MX16,DDR3-1600,F DIE,96FBGA

333S0704

8

U2300,U2320,U2340,U2360,U2500,U2520,U2540,U2560

4G_HYNIX_H

CRITICAL

IC,SDRAM,4GBIT,256MX16,DDR3-1600,HUMA,96FBGA

333S0700

8

U2300,U2320,U2340,U2360,U2500,U2520,U2540,U2560

RENESAS ALT TO VISHAY

685-0074685-0075

ALL

639-5272

BASE_BOM,CPU_HSW:2.6G,RAM_4G_HYNIX_H,CAMDRAM:HYNIX_H

PCBA,MLB-4GB,2.6G,4GB-HYNIX,J44

639-5273 PCBA,MLB-4GB,2.6G,4GB-ELPIDA,J44

BASE_BOM,CPU_HSW:2.6G,RAM_4G_ELPIDA,CAMDRAM:ELPIDA

639-5274 PCBA,MLB-4GB,2.6G,4GB-MICRON,J44

BASE_BOM,CPU_HSW:2.6G,RAM_4G_MICRON,CAMDRAM:MICRON

639-5276 PCBA,MLB-4GB,2.8G,4GB-ELPIDA,J44

BASE_BOM,CPU_HSW:2.8G,RAM_4G_ELPIDA,CAMDRAM:ELPIDA

639-5277 PCBA,MLB-4GB,2.8G,4GB-MICRON,J44

BASE_BOM,CPU_HSW:2.8G,RAM_4G_MICRON,CAMDRAM:MICRON

VCORE_FET:REN

685-0075

VCORE,FET,REN,J44

639-4878

BASE_BOM,CPU_HSW:2.4G,RAM_4G_HYNIX_H,CAMDRAM:HYNIX_H

PCBA,MLB-4GB,2.4G,4GB-HYNIX,J44

639-4879

BASE_BOM,CPU_HSW:2.4G,RAM_4G_ELPIDA,CAMDRAM:ELPIDA

PCBA,MLB-4GB,2.4G,4GB-ELPIDA,J44

639-4880

BASE_BOM,CPU_HSW:2.4G,RAM_4G_MICRON,CAMDRAM:MICRON

PCBA,MLB-4GB,2.4G,4GB-MICRON,J44

SYNC_MASTER=J44

BOM Configuration

SYNC_DATE=01/03/2013

<SCH_NUM>

3 OF 120

3 OF 78

w w w . c h i n a f i x . c o m

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87

6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

SH0435 & SH0436 removed.

POGO PINS (870-2451)

SSD STANDOFF (806-5375)

USB can Ground slot

Rubber Mount Standoffs (860-1448)

THERMAL MODULE STANDOFF (860-1645)

FAN STANDOFF (806-5376)

SNOWMAN-SHAPED SLOT AT RIGHT OF MEMORY BANK

ABOVE GUMSTICK CARD IN MIDDLE OF BOARD

(862-0118)

(998-5879)

Upper TBT can Ground slot

Lower TBT can Ground slot

(862-0118)

(998-3975)

USB can Ground slot

(998-5879)

SNOWMAN-SHAPED SLOT AT LEFT OF MEMORY BANK

Shield Cans

RIO FLEX BRACKET BOSSES (860-2354)

Mounting Holes & Slots

(998-1195)

USB Cage TBT Cage

2.9OD1.2ID-1.35H-SM

SH0466

1

2

2.9OD1.2ID-1.35H-SM

SH0461

1

2

2.9OD1.2ID-1.35H-SM

SH0465

1

2

2.9OD1.2ID-1.35H-SM

SH0463

1

2

2.9OD1.2ID-1.35H-SM

SH0467

1

2

POGO-2.3OD-5.5H-SM-LOW-FORCE

SM

SH0432

1

THERMAL-4.50-J44-SM

SH0426

1

THERMAL-4.50-J44-SM

SH0420

1

THERMAL-4.50-J44-SM

SH0421

1

THERMAL-4.50-J44-SM

SH0427

1

5.0OD2.0H-SM

SH0440

1

3.5OD2.0H-SM

SH0443

1

3.5OD2.0H-SM

SH0444

1

POGO-2.3OD-5.5H-SM-LOW-FORCE

SM

SH0433

1

OMIT

4P5R2P3-3P5B

ZT0411

1

SHLD-J44-MLB

SM

SH0451

1

SM

SHLD-J44-MLB-T29

SH0450

1

STDOFF-4.5OD1.73H-SM-1.33-3.2

SH0441

1

OMIT

6.19X4.60-SNOWMAN

ZT0413

1

OMIT

6.19X4.60-SNOWMAN

ZT0414

1

SL-1.1X0.45-1.4x0.75

TH-NSP

TH0405

1

SL-1.1X0.45-1.4x0.75

TH-NSP

TH0404

1

SL-1.1X0.5-1.4x0.8

TH-NSP

TH0403

1

TH-NSP

SL-1.1X0.5-1.4x0.8

TH0400

1

2.9OD1.2ID-1.35H-SM

SH0460

1

2

2.9OD1.2ID-1.35H-SM

SH0462

1

2

2.9OD1.2ID-1.35H-SM

SH0464

1

2

SYNC_DATE=08/12/2013

SYNC_MASTER=J44

PD Parts

<SCH_NUM>

4 OF 120

4 OF 78

w w w . c h i n a f i x . c o m

OUT

OUT OUT OUT OUT

BI BI

EDP_TXN0

EDP_TXP1

EDP_TXN1

EDP_TXP0

DDI1_TXP2

DDI1_TXN2

DDI2_TXP3

DDI2_TXN3

DDI2_TXP2

DDI2_TXN2

DDI2_TXP1

DDI2_TXN1

DDI2_TXP0

DDI1_TXP1

DDI1_TXN1

DDI1_TXP0

DDI1_TXN0

DDI2_TXN0

DDI1_TXP3

DDI1_TXN3

EDP_RCOMP

EDP_DISP_UTIL

EDP_AUXN EDP_AUXP

EDP_TXP3

EDP_TXN3

EDP_TXP2

EDP_TXN2

DDI

EDP

SYM 1 OF 19

SYM 17 OF 19

DAISY_CHAIN_NCTF

DAISY_CHAIN_NCTF DAISY_CHAIN_NCTF DAISY_CHAIN_NCTF

DAISY_CHAIN_NCTF

DAISY_CHAIN_NCTF DAISY_CHAIN_NCTF

DAISY_CHAIN_NCTF

DAISY_CHAIN_NCTF DAISY_CHAIN_NCTF DAISY_CHAIN_NCTF DAISY_CHAIN_NCTF

DAISY_CHAIN_NCTF

RSVD

RSVD RSVD

RSVD

RSVD RSVD

RSVD RSVD RSVD RSVD

RSVD RSVD RSVD

SPARE

SYM 18 OF 19

TP

NC NC

NCNC NCNC NCNC

NCNC NCNC NCNC NC NC NC NC

OUT

OUT OUT OUT

OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

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NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

(MUXed with HDMI

TBT Sink 1

TBT Sink 0

DDI Port Assignments:

Internal panel

eDP Port Assignment:

exist between both TP’s on each corner.

daisy-chain fashion. Continuity should

NO_TEST NO_TEST

Each corner of CPU has two testpoints.

MCP Daisy-Chain Strategy:

Other corner test signals connected in

if necessary)

66

62

74

62 74

CRITICAL

HASWELL-ULT

BGA-TSP

OMIT_TABLE

2C+GT2

U0500

C54

B58

B55

A57

C55

C58

A55

B57

C51

C53

C49

A53

C50

B54

B50

B53

A45

B45

A43

D20

C45

A47

C47

A49

B46

B47

C46

B49

2C+GT2

HASWELL-ULT

BGA-TSP

OMIT_TABLE

CRITICAL

U0500

A3 A4

A60

A61

A62 AV1

AW1

AW2 AW3

AW61

AW62 AW63

AY2 AY3

AY60

AY61 AY62

B2

B3 B61

B62

B63

C1

C2

HASWELL-ULT

OMIT_TABLE

CRITICAL

2C+GT2

BGA-TSP

U0500

AL1

AM11

AP7

AT2

AU10

AU15

AU44

AV44

AW14

AY14

D15

F22

H22

J21

N23

R23

T23 U10

TP-P6

TP0531

1

TP-P6

TP0500

1

TP-P6

TP0510

1

TP-P6

TP0501

1

TP-P6

TP0511

1

TP-P6

TP0520

1

TP-P6

TP0521

1

TP-P6

TP0530

1

24.9

1%

MF 201

1/20W

R0530

1

2

23

74

23 74

66

SYNC_DATE=08/12/2013

SYNC_MASTER=J44

CPU GFX/NCTF/RSVD

MCP_DC_AW3_AY3

TRUE

MCP_DC_AW3_AY3

TRUE

MCP_DC_AW2_AY2

MCP_DC_AW61_AY61

TRUE

MCP_DC_B62_B63

TRUE

MCP_DC_A3_B3

TRUE

MCP_DC_A61_B61

MCP_DC_AW62_AY62

TRUE

MCP_DC_AW62_AY62

MCP_DC_AW61_AY61

TRUE

MCP_DC_AW2_AY2

TRUE

MCP_DC_A61_B61

MCP_DC_A3_B3

TRUE

DP_INT_ML_C_P<3>

MCP_EDP_RCOMP

DP_INT_ML_C_P<1>

=DP_TBTSNK1_ML_C_N<2> =DP_TBTSNK1_ML_C_P<2> =DP_TBTSNK1_ML_C_N<3>

=DP_TBTSNK1_ML_C_P<1>

DP_TBTSNK0_ML_C_P<3>

DP_TBTSNK0_ML_C_N<0>

DP_TBTSNK0_ML_C_P<2>

DP_TBTSNK0_ML_C_P<1>

DP_TBTSNK0_ML_C_N<1>

DP_TBTSNK0_ML_C_P<0>

=DP_TBTSNK1_ML_C_N<0> =DP_TBTSNK1_ML_C_P<0> =DP_TBTSNK1_ML_C_N<1>

=DP_TBTSNK1_ML_C_P<3>

DP_TBTSNK0_ML_C_N<2>

DP_TBTSNK0_ML_C_N<3>

PPVCOMP_S0_CPU

TP_EDP_DISP_UTIL

DP_INT_ML_C_N<0> DP_INT_ML_C_P<0> DP_INT_ML_C_N<1>

DP_INT_ML_C_N<2> DP_INT_ML_C_P<2> DP_INT_ML_C_N<3>

DP_INT_AUXCH_C_N DP_INT_AUXCH_C_P

MCP_DC_A4

MCP_DC_A62

MCP_DC_AW1

MCP_DC_AY60

MCP_DC_B2

MCP_DC_A60

MCP_DC_AW63

MCP_DC_AV1

MCP_DC_C1_C2

TRUE

<SCH_NUM>

5 OF 120

5 OF 78

5

70

8

w w w . c h i n a f i x . c o m

SM_PG_CNTL1

SM_DRAMRST*

SM_RCOMP1 SM_RCOMP2

SM_RCOMP0

PROCHOT*

PROCPWRGD

PECI

CATERR*

BPM7*

BPM6*

BPM5*

BPM4*

BPM3*

BPM2*

BPM1*

BPM0*

PROC_TDO

PROC_TDI

PROC_TRST*

PROC_TMS

PROC_TCK

PREQ*

PRDY*

PROC_DETECT*

SYM 2 OF 19

MISC

THERMAL

JTAG

DDR3

PWR

BI BI

BI

NC NC

NC

BI

OUT

NC

BI

OUT

IN

OUT

VSS VSS

RSVD

CFG_RCOMP

RSVD

RSVD RSVD

TD_IREF

CFG0 CFG1

CFG5

CFG4

CFG3

CFG2

CFG6

CFG10

CFG9

CFG8

CFG7

CFG11

CFG15

CFG14

CFG13

CFG12

CFG18

CFG16

CFG17 CFG19

RSVD RSVD

RSVD_TP RSVD_TP

EDP_SPARE

RSVD_TP RSVD_TP

RSVD_TP

RSVD

RSVD RSVD

PROC_OPI_COMP

RSVD RSVD

RESERVED

SYM 19 OF 19

NC NC

NC NC NC

NC NC

NC

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

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C

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A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

CFG<0> :RESET SEQUENCE STALL 1 = NORMAL OPERATION 0 = STALL AFTER PCU PLL LOCK

CFG<10>:SAFE MODE BOOT 1 = NORMAL OPERATION 0 = POWER FEATURES NOT ACTIVE

and are only for debug access

CFG<1> :PCH-LESS MODE 1 = NORMAL OPERATION 0 = PCH-LESS MODE

issue, but this locks CPU VR at 1.7V Vboot (CPU Sighting #4391569).

NOTE: Pre-ES2 CPUs have issue with Sx cycling, must set CFG<9> low to avoid

(IPU)

CFG<9> :NO SVID-CAPABLE VR 1 = VR SUPPORTS SVID 0 = VR DOES NOT SUPPORT SVID

(IPU)

(IPU) (IPU)

(IPU)

(IPU) (IPU)

(IPU)

CFG<4> :eDP ENABLE/DISABLE 1 = DISABLED 0 = ENABLED

CFG<8> :ALLOW NOA ON LOCKED UNITS 1 = NORMAL OPERATION 0 = NOA ALWAYS UNLOCKED

(IPU)

(IPD)

(IPU)

These can be placed close to J1800

BGA-TSP

2C+GT2

HASWELL-ULT

OMIT_TABLE

CRITICAL

U0500

J60

H60 H61

H62

K59 H63

K60 J61

K61

N62

J62 K62

D61

E60

F63

F62

E61

E59

K63

C61

AV15

AV61

AU60

AV60 AU61

NOSTUFF

1K

5%

201

1/20W

MF

R0640

1

2

HSW_PRE_ES2

1K

5%

201

1/20W MF

R0639

1

2

MF

1/20W

201

5%

1K

NOSTUFF

R0638

1

2

MF

1/20W

201

5%

1K

NOSTUFF

R0631

1

2

1K

NOSTUFF

5%

201

1/20W MF

R0630

1

2

6

16

70

6

16

70

16 70

6

16

70

16 70

6

16

70

6

16

70

16 70

6

16

70

16 70

36 37 53 70

5%

1/20W

MF

201

62

R0610

1

2

201

5%

MF

56

1/20W

R0611

12

37

70

36 70

PLACE_NEAR=U0500.C61:12.7mm

201

MF

1/20W

5%

10K

R0620

1

2

16

70

16 70

12 16 70

16 70

PLACE_NEAR=U0500.AU61:12.7mm

MF

1/20W

201

100

1%

R0652

1

2

MF

1/20W

201

1%

PLACE_NEAR=U0500.AV60:12.7mm

121

R0651

1

2

1%

200

201

1/20W

MF

PLACE_NEAR=U0500.AU60:12.7mm

R0650

1

2

22

66

17

1%

49.9

1/20W

201

MF

R0680

1

2

CRITICAL

OMIT_TABLE

HASWELL-ULT

2C+GT2

BGA-TSP

U0500

AC60

AC62

V60 U60

T63

T62 T61

T60

AA62

AA61

U63

U62

AC63 AA63

AA60

Y62 Y61

Y60

V62 V61

V63

B43

AY15

A5

AV62

D1

D58

E1

H18

J20

N60

P20 R20

A51

AU63

AV63

B51

C62

C63

L60

W23

Y22

B12

N21

P22

201

MF

1/20W

1%

49.9

R0690

1

2

1% 1/20W

201

MF

8.25K

R0685

1

2

EDP

MF

1/20W

201

5%

1K

R0634

1

2

CPU Misc/JTAG/CFG/RSVD

SYNC_MASTER=J44

SYNC_DATE=08/12/2013

CPU_CFG<18>

CPU_CFG<1>

CPU_CFG<8>

CPU_CFG<10>

CPU_CFG<0>

CPU_PROCHOT_L

CPU_PROCHOT_R_L

CPU_PECI

CPU_MEMVTT_PWR_EN_LSVDDQ

MEM_RESET_HSW_L

CPU_SM_RCOMP<1>

CPU_PWRGD

CPU_CFG<12>

CPU_CFG_RCOMP

PCH_TD_IREF

TP_MCP_RSVD_L60

XDP_BPM_L<7>

XDP_BPM_L<6>

XDP_BPM_L<5>

XDP_BPM_L<4>

XDP_BPM_L<3>

XDP_BPM_L<2>

XDP_BPM_L<1>

XDP_BPM_L<0>

XDP_CPU_TDO

XDP_CPU_TDI

XDP_CPUPCH_TRST_L

XDP_CPU_TMS

XDP_CPU_TCK

XDP_CPU_PREQ_L

XDP_CPU_PRDY_L

CPU_OPI_RCOMP

TP_MCP_RSVD_A51

TP_MCP_RSVD_C62

TP_MCP_RSVD_C63

TP_MCP_RSVD_AU63

TP_MCP_RSVD_AV63

CPU_CFG<19>

CPU_CFG<17>

CPU_CFG<16>

CPU_CFG<13> CPU_CFG<14> CPU_CFG<15>

CPU_CFG<11>

CPU_CFG<7> CPU_CFG<8>

CPU_CFG<10>

CPU_CFG<6>

CPU_CFG<2> CPU_CFG<3> CPU_CFG<4> CPU_CFG<5>

CPU_CFG<1>

CPU_CFG<0>

TP_MCP_RSVD_B51

CPU_CFG<9>

CPU_CATERR_L

CPU_SM_RCOMP<2>

PP1V05_S0

CPU_SM_RCOMP<0>

CPU_CFG<4>

CPU_CFG<9>

<SCH_NUM>

6 OF 120

6 OF 78

6

16 70

6

16 70

6

16 70

6

16 70

70

8

11

15 16 17 37 53 57 60 61

65 68

70

6

16

70

6

16 70

w w w . c h i n a f i x . c o m

BI BI

BI

BI BI BI

BI BI

BI BI BI

BI

BI BI

BI

BI BI

BI

BI BI

BI

BI BI

BI

BI BI

BI

BI BI BI

BI

BI BI BI

BI

BI BI

BI

BI BI

BI

BI BI

BI

BI BI

OUT

OUT OUT

OUT

OUT OUT

OUT

OUT OUT OUT

OUT

OUT OUT OUT

OUT

OUT OUT OUT

BI

BI BI BI

BI

SA_DQ63

SA_DQ62

SA_DQ61

SA_DQ60

SA_DQ59

SA_DQ58

SA_DQ57

SA_DQ55 SA_DQ56

SA_DQ54

SA_DQ53

SA_DQ52

SA_DQ51

SA_DQ50

SA_DQ49

SA_DQ48

SA_DQ47

SA_DQ45 SA_DQ46

SA_DQ42 SA_DQ43 SA_DQ44

SA_DQ40 SA_DQ41

SA_DQ39

SA_DQ37 SA_DQ38

SA_DQ34

SA_DQ36

SA_DQ32 SA_DQ33

SA_DQ29 SA_DQ30 SA_DQ31

SA_DQ27 SA_DQ28

SA_DQ24 SA_DQ25

SA_DQ22 SA_DQ23

SA_DQ21

SA_DQ19 SA_DQ20

SA_DQ17 SA_DQ18

SA_DQ16

SA_DQ14 SA_DQ15

SA_DQ11

SA_DQ13

SA_DQ10

SA_DQ9

SA_DQ7 SA_DQ8

SA_DQ6

SA_DQ4 SA_DQ5

SA_DQ3

SA_DQ1

SA_DQ0

SA_CLK1*

SA_CLK0

SA_CLK0*

SA_DQ12

SM_VREF_DQ1

SM_VREF_CA

SM_VREF_DQ0

SA_DQ35

SA_DQ26

SA_DQ2

SA_CLK1

SA_CS0* SA_CS1*

SA_CKE0 SA_CKE1 SA_CKE2 SA_CKE3

SA_ODT0

SA_RAS*

SA_WE*

SA_CAS*

SA_MA0

SA_MA2

SA_MA1

SA_MA3 SA_MA4 SA_MA5

SA_MA7

SA_MA6

SA_MA8

SA_MA10

SA_MA9

SA_MA12

SA_MA11

SA_MA13 SA_MA14 SA_MA15

SA_BA2

SA_BA0 SA_BA1

SA_DQSP0

SA_DQSP2

SA_DQSP1

SA_DQSP3 SA_DQSP4 SA_DQSP5 SA_DQSP6 SA_DQSP7

SA_DQSN1

SA_DQSN0

SA_DQSN2

SA_DQSN4

SA_DQSN3

SA_DQSN5 SA_DQSN6 SA_DQSN7

SYM 3 OF 19

MEMORY CHANNEL A

OUT OUT

OUT

OUT OUT

OUT OUT OUT OUT

OUT OUT

OUT

OUT OUT OUT

OUT OUT OUT OUT OUT OUT OUT OUT

OUT

OUT OUT OUT OUT OUT OUT

BI

BI BI

BI

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

SB_DQ0 SB_DQ1 SB_DQ2 SB_DQ3 SB_DQ4 SB_DQ5

SB_CKE0

SB_DQ6

SB_CKE1

SB_DQ7

SB_CKE2

SB_DQ8

SB_CKE3 SB_DQ9 SB_DQ10 SB_CS0* SB_DQ11 SB_CS1* SB_DQ12 SB_DQ13 SB_ODT0 SB_DQ14 SB_DQ15 SB_RAS* SB_DQ16

SB_WE* SB_DQ17 SB_CAS* SB_DQ18 SB_DQ19

SB_BA0 SB_DQ20

SB_BA1 SB_DQ21

SB_BA2 SB_DQ22 SB_DQ23

SB_MA0 SB_DQ24

SB_MA1 SB_DQ25

SB_MA2 SB_DQ26

SB_MA3 SB_DQ27

SB_MA4 SB_DQ28

SB_MA5 SB_DQ29

SB_MA6 SB_DQ30

SB_MA7 SB_DQ31

SB_MA8 SB_DQ32

SB_MA9 SB_DQ33 SB_MA10 SB_DQ34 SB_MA11 SB_DQ35 SB_MA12

SB_MA13 SB_DQ37 SB_MA14 SB_DQ38 SB_MA15 SB_DQ39 SB_DQ40

SB_DQSN0

SB_DQ41

SB_DQSN1

SB_DQ42

SB_DQSN2

SB_DQ43

SB_DQSN3

SB_DQ44

SB_DQSN4

SB_DQ45

SB_DQSN5

SB_DQ46

SB_DQSN6

SB_DQ47

SB_DQSN7 SB_DQ48 SB_DQ49

SB_DQSP0 SB_DQ50

SB_DQSP1 SB_DQ51

SB_DQSP2 SB_DQ52

SB_DQSP3 SB_DQ53

SB_DQSP4 SB_DQ54

SB_DQSP5 SB_DQ55

SB_DQSP6 SB_DQ56

SB_DQSP7 SB_DQ57 SB_DQ58 SB_DQ59 SB_DQ60 SB_DQ61 SB_DQ62 SB_DQ63

SB_DQ36

SB_CK0*

SB_CK0

SB_CK1*

SB_CK1

SYM 4 OF 19

MEMORY CHANNEL B

BI BI BI

BI

BI BI BI

BI BI

BI

BI BI

BI

BI BI BI

BI

BI BI BI BI BI

BI

BI BI BI BI BI BI

BI

BI BI BI BI BI BI BI BI

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87

6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

RSVD4

RSVD3

CAA4

CAA2

CAA0

CAA8

CAA9

CAB0

CAA6

CAA7

CAB7

CAA1

CAA3

LPDDR3

CAB6

CAB4

CAB1

CAB2

CAB3

CAB5

CAB8

CAB9

CAA5

LPDDR3

CAB6

CAB4

CAB1

CAB2

CAB3

CAA4

CAA2

CAA0

RSVD2

RSVD1

CAB5

CAB8

CAB9

CAA5

CAA8

CAA9

CAB0

CAA6

CAA7

CAB7

CAA1

CAA3

67

68 73

67 68 73

20 67 68 73

67 68 73

67 73

20 67 73

67 73

22

66

22 66

20 22 73

22

66

20 22 73

66

20 22 66 73

66

20 22 66 73

66

20 22 66 73

66

67 73

20 67 73

67 73

2C+GT2

CRITICAL

OMIT_TABLE

BGA-TSP

HASWELL-ULT

U0500

AU35

AV35 AY41

AU34

AU43

AW43 AY42

AY43

AV37

AU37

AY36

AW36

AP33

AR32

AH63

AH62

AP63

AP62

AM61 AM60

AP61

AP60 AP58

AR58 AM57

AK57

AK63

AL58 AK58

AR57

AN57 AP55

AR55

AM54 AK54

AL55 AK55

AK62

AR54

AN54 AY58

AW58

AY56 AW56

AV58

AU58 AV56

AU56

AH61

AY54

AW54

AY52 AW52

AV54

AU54 AV52

AU52

AK40 AK42

AH60

AM43 AM45

AK45

AK43 AM40

AM42

AM46 AK46

AM49

AK49

AK61

AM48

AK48 AM51

AK51

AK60

AM63

AM62

AJ61

AN62

AM58 AM55

AV57

AV53 AL43

AL48

AJ62

AN61 AN58

AN55

AW57 AW53

AL42

AL49

AU36 AY37

AP35

AW41 AU41

AR35

AV42 AU42

AR38

AP36 AU39

AR36 AV40

AW39

AY39 AU40

AP32

AY34 AW34

AP49

AR51

AP51

66

19

73

19 73

21 22 73

66

21 22 73

22

66

21 22 73

22

22 66

21 22 66 73

66

21 22 66 73

66

21 22 66 73

66

22

67 73

21 67 73

67 73

21 67 73

67 73

67 68 73

OMIT_TABLE

CRITICAL

HASWELL-ULT

2C+GT2

BGA-TSP

U0500

AL35

AM36 AU49

AM33

AN38

AM38

AL38

AK38

AY49

AU50 AW49

AV50

AM32

AK32

AY31

AW31

AY25

AW25

AV27 AU27

AV25

AU25 AM29

AK29 AL28

AK28

AY29

AR29 AN29

AR28

AP28 AN26

AR26

AR25 AP25

AK26 AM26

AW29

AK25

AL25 AY23

AW23

AY21 AW21

AV23

AU23 AV21

AU21

AV31

AY19

AW19

AY17 AW17

AV19

AU19 AV17

AU17

AR21 AR22

AU31

AL21 AM22

AN22

AP21 AK21

AK22

AN20 AR20

AK18

AL18

AV29

AK20

AM20 AR18

AP18

AU29

AY27

AW27

AW30

AV26

AN28 AN25

AW22

AV18 AN21

AN18

AV30

AW26 AM28

AM25

AV22 AW18

AM21

AM18

AP40 AR40

AK36

AV47 AU47

AK33

AR46 AP46

AP42

AR42 AR45

AP45 AW46

AY46

AY47 AU46

AL32

AM35 AK35

67

68 73

67 68 73

21 67 68 73

67 68 73

SYNC_DATE=08/12/2013

SYNC_MASTER=J44

CPU DDR3/LPDDR3 Interfaces

MEM_A_DQS_N<7>

MEM_A_DQS_P<7>

MEM_A_DQ<63>

MEM_A_DQ<62>

MEM_A_DQ<61>

MEM_A_DQ<60>

MEM_A_DQ<59>

MEM_A_DQ<58>

MEM_A_DQ<57>

MEM_A_DQ<55> MEM_A_DQ<56>

MEM_A_DQ<54>

MEM_A_DQ<53>

MEM_A_DQ<52>

MEM_A_DQ<51>

MEM_A_DQ<50>

MEM_A_DQ<49>

MEM_A_DQ<48>

MEM_A_DQ<47>

MEM_A_DQ<45> MEM_A_DQ<46>

MEM_A_DQ<42> MEM_A_DQ<43> MEM_A_DQ<44>

MEM_A_DQ<40> MEM_A_DQ<41>

MEM_A_DQ<39>

MEM_A_DQ<37> MEM_A_DQ<38>

MEM_A_DQ<34>

MEM_A_DQ<36>

MEM_A_DQ<32> MEM_A_DQ<33>

MEM_A_DQ<29> MEM_A_DQ<30> MEM_A_DQ<31>

MEM_A_DQ<27> MEM_A_DQ<28>

MEM_A_DQ<24> MEM_A_DQ<25>

MEM_A_DQ<22> MEM_A_DQ<23>

MEM_A_DQ<21>

MEM_A_DQ<35>

MEM_A_DQ<26>

MEM_A_DQ<19> MEM_A_DQ<20>

MEM_A_DQ<17> MEM_A_DQ<18>

MEM_A_DQ<16>

MEM_A_DQ<14> MEM_A_DQ<15>

MEM_A_DQ<11>

MEM_A_DQ<13>

MEM_A_DQ<10>

MEM_A_DQ<9>

MEM_A_DQ<7> MEM_A_DQ<8>

MEM_A_DQ<6>

MEM_A_DQ<4> MEM_A_DQ<5>

MEM_A_DQ<3>

MEM_A_DQ<1>

MEM_A_DQ<0>

MEM_A_DQ<12>

MEM_A_DQ<2>

MEM_B_DQ<36>

MEM_B_DQ<63>

MEM_B_DQ<62>

MEM_B_DQ<61>

MEM_B_DQ<60>

MEM_B_DQ<59>

MEM_B_DQ<58>

MEM_B_DQ<57>

MEM_B_DQ<56>

MEM_B_DQ<55>

MEM_B_DQ<54>

MEM_B_DQ<53>

MEM_B_DQ<52>

MEM_B_DQ<51>

MEM_B_DQ<48>

MEM_B_DQ<47>

MEM_B_DQ<46>

MEM_B_DQ<45>

MEM_B_DQ<43>

MEM_B_DQ<42>

MEM_B_DQ<41>

MEM_B_DQ<40>

MEM_B_DQ<39>

MEM_B_DQ<38>

MEM_B_DQ<35>

MEM_B_DQ<34>

MEM_B_DQ<33>

MEM_B_DQ<32>

MEM_B_DQ<31>

MEM_B_DQ<27>

MEM_B_DQ<26>

MEM_B_DQ<25>

MEM_B_DQ<24>

MEM_B_DQ<23>

MEM_B_DQ<22>

MEM_B_DQ<21>

MEM_B_DQ<20>

MEM_B_DQ<19>

MEM_B_DQ<18>

MEM_B_DQ<16>

MEM_B_DQ<15>

MEM_B_DQ<14>

MEM_B_DQ<13>

MEM_B_DQ<12>

MEM_B_DQ<11>

MEM_B_DQ<10>

MEM_B_DQ<9>

MEM_B_DQ<8>

MEM_B_DQ<7>

MEM_B_DQ<6>

MEM_B_DQ<5>

MEM_B_DQ<4>

MEM_B_DQ<3>

MEM_B_DQ<2>

MEM_B_DQ<1>

MEM_B_DQ<0>

MEM_B_DQ<28> MEM_B_DQ<29> MEM_B_DQ<30>

MEM_B_DQ<44>

MEM_B_DQ<50>

MEM_B_DQ<49>

MEM_B_DQ<37>

MEM_B_DQ<17>

MEM_B_CLK_P<0>

MEM_B_CLK_N<0>

NC_MEM_B_CLKN<1>

MEM_B_CKE<0>

NC_MEM_B_CKE<3>

MEM_B_CS_L<0>

MEM_B_ODT_CPU0

MEM_B_WE_L MEM_B_CAS_L

=MEM_B_BA<0> MEM_B_BA<1>

=MEM_B_A<0> =MEM_B_A<1> =MEM_B_A<2> =MEM_B_A<3> =MEM_B_A<4> =MEM_B_A<5> MEM_B_A<6> =MEM_B_A<7>

=MEM_B_A<9>

=MEM_B_A<8>

=MEM_B_A<10> =MEM_B_A<11> =MEM_B_A<12> =MEM_B_A<13> =MEM_B_A<14> NC_MEM_B_A15

MEM_B_DQS_N<0>

MEM_B_DQS_N<2>

MEM_B_DQS_N<1>

MEM_B_DQS_N<3>

MEM_B_DQS_N<5>

MEM_B_DQS_N<4>

MEM_B_DQS_N<6> MEM_B_DQS_N<7>

MEM_B_DQS_P<1>

MEM_B_DQS_P<4>

MEM_B_DQS_P<3>

MEM_B_DQS_P<6>

MEM_B_DQS_P<5>

MEM_B_DQS_P<7>

NC_MEM_A_CKE1

NC_MEM_A_CLKN<1> NC_MEM_A_CLKP<1>

MEM_A_CLK_P<0>

MEM_A_CKE<0>

MEM_A_CLK_N<0>

MEM_A_CKE<2> NC_MEM_A_CKE<3>

MEM_A_ODT_CPU0

MEM_A_CS_L<0> NC_MEM_A_CS_L1

=MEM_A_BA<0>

MEM_A_CAS_L

MEM_A_WE_L

MEM_A_RAS_L

MEM_A_BA<1> =MEM_A_BA<2>

=MEM_A_A<0>

=MEM_A_A<3>

=MEM_A_A<2>

=MEM_A_A<1>

=MEM_A_A<5>

=MEM_A_A<4>

MEM_A_A<6> =MEM_A_A<7>

NC_MEM_A_A15

=MEM_A_A<14>

=MEM_A_A<8>

=MEM_A_A<10>

=MEM_A_A<9>

=MEM_A_A<11> =MEM_A_A<12> =MEM_A_A<13>

MEM_A_DQS_N<0>

MEM_A_DQS_P<0> MEM_A_DQS_P<1>

MEM_A_DQS_N<1> MEM_A_DQS_N<2> MEM_A_DQS_N<3> MEM_A_DQS_N<4>

MEM_A_DQS_N<6>

MEM_A_DQS_N<5>

MEM_A_DQS_P<5> MEM_A_DQS_P<6>

MEM_A_DQS_P<3> MEM_A_DQS_P<4>

MEM_A_DQS_P<2>

CPU_DIMM_VREFCA

CPU_DIMMA_VREFDQ

CPU_DIMMB_VREFDQ

MEM_B_CKE<2>

NC_MEM_B_CLKP<1>

NC_MEM_B_CKE1

NC_MEM_B_CS_L1

=MEM_B_BA<2>

MEM_B_DQS_P<0>

MEM_B_DQS_P<2>

MEM_B_RAS_L

<SCH_NUM>

7 OF 120

7 OF 78

w w w . c h i n a f i x . c o m

VCC

VCCST

RSVD

RSVD RSVD

RSVD

RSVD_TP

VSS

PWR_DEBUG*

VSS

VCC_SENSE

RSVD

VCC RSVD

VDDQ VDDQ

VDDQ

RSVD

VCC

VCC VCC VCC

VCC VCC

VCC VCC VCC

VCC

VCC VCC VCC

VCC VCC

VCC

VCC VCC

VCC

VCC VCC

VCC

VCC VCC VCC

VCC VCC

VCC VCC VCC

VCC

VCC VCC VCC

VCC VCC

VCC

VCC VCC

VCC VCC VCC

VCC VCC

VCC

VCC VCC

VCC VCC VCC

VCC VCC

VCC

VDDQ

VCCIOA_OUT RSVD RSVD

VIDALERT*

RSVD

VIDSOUT

VIDSCLK

VR_EN

VCCST_PWRGD

VR_READY

VCCIO_OUT

RSVD

HSW ULT POWER

SYM 12 OF 19

OUT

IN

NC NC

NC

VCCHSIO VCCHSIO VCCHSIO

VCCIO VCCIO

VCCUSB3PLL

VCCSATA3PLL

VCCAPLL VCCAPLL VCCAPLL

DCPSUS3

VCCHDA

DCPSUS2

VCCSUS3 VCCSUS3

VCC3 VCC3

VCCDSW3_3

VCC1P05 VCC1P05

VCCCLK

VCCACLKPLL

VCCSUS3

VCCIO

VCCAPLL

DCPSUS4

VCCSUS3

VCCRTC

DCPRTC

VCCSPI

VCCASW

VCC1P05 VCC1P05

VCC1P05

DCPSUSBYP DCPSUSBYP

VCCASW VCCASW VCCASW

DCPSUS1

VCC3

VCCTS1_5

VCCSDIO

SUS OSCILLATOR

SERIAL IO

THERMAL SENSOR

SYM 13 OF 19

USB2

LPT LP POWER

CORE

SPI RTC

HSIO

OPI

USB3

AZALIA/HDA

VRM/USB2/AZALIA

GPIO/LCC

ICC

NC

BI

NC NC

IN OUT IN

NC NC NC

NC

OUT

NC

NC NC

NC

NC NC NC

IN

NC

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

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NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

R0810.2: R0800.2:

R0802.2:

NOTE: Aliases not used on CPU supply outputs

473mA Max[1]

Powered in DeepSx

LPT-LP current estimates from Lynx Point-LP PCH EDS, doc #503118, v1.0. Note [1] current numbers from clarification email, from Srini, dated 9/10/2012 2:11pm.

1499mA Max[1]

57mA Max

1838mA Max

WF: RSVD on Sawtooth Peak rev 1.0

41mA Max

59mA Max[1]

0.3mA Max[1]

29mA Max[1]

185mA Max[1]

40mA Max[1]

1mA Max[1]

213mA Max[1]

HSW-ULT current estimates from Haswell Mobile ULT Processor EDS vol 1, doc #502406, v0.9.

1.1A Max (LPDDR3: 1.2V)

1.4A Max (DDR3: 1.5-1.35V)

32A Max

???mA Max

18mA Max

11mA Max

3mA Max

17mA Max

42mA Max

Max load: 300mA

114mA Max

3.3mA Max[1]

WF: RSVD on Sawtooth Peak rev 1.0

VCCCLK: 200mA Max

31mA Max

VCCCLK: 200mA Max

to avoid any extraneous connections.

OMIT_TABLE

2C+GT2

HASWELL-ULT

BGA-TSP

CRITICAL

U0500

H59

AA23

AA59

AB23

AC58

AC59

AD23

AD59

AD60

AE59

AE60

AG58

J58

L59

N58

T59

N59 N61

P60 P61

U59 V59

F59

AB57

AD57 AG57

C24

C28 C32

C36

C40 C44

C48

C52 C56

E23 E25

E27

E29 E31

E33

E35 E37

E39

E41 E43

E45 E47

E49

E51 E53

E55

E57 F24

F28

F32 F36

F40 F44

F48

F52 F56

G23

G25 G27

G29

G31 G33

G35 G37

G39

G41 G43

G45

G47 G49

G51

G53 G55

G57 H23

J23

K23 K57

L22

M23 M57

P57

E63

U57 W57

A59

E20

AC22

AE22

AE23

B59

AH26

AJ31 AJ33

AJ37 AN33

AP43

AR48 AY35

AY40

AY44 AY50

L62

N63

L63

F60

C59

D63

P62

PLACE_NEAR=U0500.L63:2.54mm

1% 1/20W

130

MF 201

R0802

1

2

53

70

16

PLACE_NEAR=U0500.C50:50.8mm

100

MF

1/20W

201

5%

R0860

1

2

CRITICAL

OMIT_TABLE

HASWELL-ULT

2C+GT2

BGA-TSP

U0500

AE7

AD10 AD8

AH13

J13

AB8

AG19

AG20

AE8

AF22

H11

H15

J11

J18 K19

K14

K16

V8 W9

A20

AA21

AC20

W21

Y20

AE9

AF9

AG13

AG14

AG8

J17

K18

M20

R21 T21

V21

AH10

AH14

K9

L10

M9

AG16

AG17

N8

P9

AG10

B11

T9

U8

Y8

AA9

AC9

AE20

AE21

AH11

J15

B18

53

70

16 17 70

17 53

53 70

BYPASS=R0899:U0500:2.54mm

402

CERM

1UF

10%

6.3V

C0899

1

2

PLACE_NEAR=U0500.AG19:2.54mm

1%

MF-LF

5.11

1/20W

201

R0899

12

53

70

0.1UF

CERM 402

10V

20%

BYPASS=U0500.AE7:6.35mm

C0895

1

2

402

CERM

10V

20%

0.1UF

BYPASS=U0500.AG10:6.35mm

C0892

1

2

BYPASS=U0500.AG10:6.35mm

0.1UF

402

CERM

10V

20%

C0891

1

2

BYPASS=U0500.AG10:6.35mm

1UF

402

CERM

6.3V

10%

C0890

1

2

MF

1/20W

0201

0

5%

R0811

12

MF

1/20W

0201

0

5%

R0812

12

PLACE_NEAR=U0500.L62:38.1mm

1/20W

43

MF

201

5%

R0810

12

PLACE_NEAR=R0810.1:2.54mm

MF

1%

75

1/20W

201

R0800

1

2

CPU/PCH POWER

SYNC_MASTER=J44

SYNC_DATE=08/12/2013

PPVCOMP_S0_CPU

MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V

MIN_LINE_WIDTH=0.4 mm

PP1V05_S0_PCH_VCCACLKPLL

PP1V05_S0

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.2 mm

PPVOUT_S5_PCH_DCPSUSBYP_R

VOLTAGE=1.05V

PPVOUT_S5_PCH_DCPSUSBYP

MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V

MIN_LINE_WIDTH=0.2 mm

PPVOUT_S0_PCH_DCPRTC

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.2 mm

PP3V3_SUS

PP3V3_S0

PP1V05_S0

PP3V3_S0

PP1V05_S0

PP1V5_S0

PP3V3_SUS

PP1V05_S0

PPVRTC_G3H

CPU_VIDSCLK

CPU_VIDSOUT

PP1V05_S0SW_PCH_VCCSATA3PLL

PP1V05_S0SW_PCH_VCCUSB3PLL

PP3V3_S0

PP1V5_S0SW_AUDIO_HDA

PP1V05_S0_PCH_VCCAPLL_OPI

PP1V05_S0SW_PCH_HSIO

PP3V3_S5

PP1V05_S0

PP1V05_S0_PCH_VCC_ICC

PP1V05_S0

TP_CPU_RSVDN61

TP_CPU_RSVD_N59

TP_CPU_RSVDP61

TP_CPU_RSVD_P60

CPU_PWR_DEBUG

PPVCC_S0_CPU

PP1V35_S3_CPUDDR

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.4 mm

TP_PPVCCIO_S0_CPU

CPU_VCCSENSE_P

CPU_VCCST_PWRGD

CPU_VR_READY

CPU_VR_EN

CPU_VIDSCLK_R

PP1V05_S0

CPU_VIDALERT_R_L

CPU_VIDSOUT_R

CPU_VIDALERT_L

8 OF 120

8 OF 78

<SCH_NUM>

5

11

12

6 8 11

15 16 17 37 53 57

60 61 65 68

8

11

14 45 59 60 61 65

8

11

14 45 59 60 61 65

8

11 14

45 59 60 61 65

8

11 12

13 15 17 18 24 28 30 37

38 39 40 41 42 43 44 46 47 50

61 62 64 65 68 77

6 8 11

15 16 17 37 53 57 60 61

65 68

8

11 12

13 15 17 18 24 28 30 37

38 39 40 41 42 43 44 46 47 50

61 62 64 65 68 77

6 8 11

15 16 17 37 53 57 60 61

65 68

47 59 60 61 63 65 68

8

11 14

45 59 60 61 65

6 8 11

15 16 17 37 53 57

60 61 65 68

12 13 17 65

11 12

11 14

8

11

12 13 15 17 18 24 28

30 37 38 39 40 41 42 43 44

46 47 50 61 62 64 65 68 77

11 17 60

11

11 60 65

11 13 15 16 17 18 26 27 29 56 59 60 61 65 68 77

6 8 11

15 16 17 37 53 57

60 61 65 68

11

6 8 11

15 16 17 37 53 57 60 61

65 68

6 8 11

15 16 17 37 53 57 60

61 65 68

18

8

10

42 54 65 68

8

10

42 54 65 68

10 41 65 73

70

6 8 11

15 16 17 37 53 57 60

61 65 68

70

w w w . c h i n a f i x . c o m

SYM 14 OF 19

VSS

VSS VSS

VSS

VSS VSS

VSS

VSS VSS

VSS

VSS VSS

VSS

VSS VSS

VSS VSS VSS

VSS

VSS VSS VSS

VSS VSS

VSS VSS VSS

VSS

VSS VSS

VSS

VSS VSS

VSS

VSS VSS VSS

VSS VSS

VSS

VSS VSS

VSS

VSS VSS

VSS

VSS VSS

VSS

OUT

SYM 15 OF 19

VSS

VSS VSS VSS

VSS

VSS VSS VSS

VSS VSS

VSS

VSS VSS

VSS

VSS VSS

VSS

VSS VSS

VSS

VSS VSS

VSS

VSS VSS VSS

VSS

VSS VSS

VSS

VSS VSS

VSS

VSS VSS

VSS

VSS VSS

VSS

VSS VSS

VSS

VSS VSS VSS

VSS VSS VSS VSS VSS

VSS

VSS VSS VSS

VSS

VSS VSS VSS VSS

VSS

VSS VSS VSS VSS

VSS

VSS VSS VSS

SYM 16 OF 19

VSS

VSS VSS

VSS

VSS VSS

VSS

VSS VSS

VSS

VSS VSS VSS

VSS

VSS VSS VSS

VSS

VSS VSS

VSS

VSS VSS

VSS

VSS VSS

VSS

VSS VSS

VSS

VSS VSS

VSS

VSS VSS

VSS

VSS VSS

VSS VSS VSS VSS VSS

VSS

VSS_SENSE

VSS

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

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PAGE

12

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C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

2C+GT2

BGA-TSP

HASWELL-ULT

OMIT_TABLE

CRITICAL

U0500

A11

A14 A18

A24

A28 A32

A36

A40 A44

A48

A52 A56

AA1 AA58

AB10

AB20 AB22

AB7

AC61 AD21

AD3

AD63 AE10

AE5 AE58

AF11

AF12 AF14

AF15

AF17 AF18

AG1

AG11 AG21

AG23 AG60

AG61

AG62 AG63

AH17

AH19 AH20

AH22

AH24 AH28

AH30 AH32

AH34

AH36 AH38

AH40

AH42 AH44

AH49

AH51 AH53

AH55 AH57

AJ13

AJ14 AJ23

AJ25

AJ27 AJ29

AJ35

AJ39 AJ41

AJ43

AJ45 AJ47

AJ50

AJ52 AJ54

AJ56

AJ58 AJ60

AJ63 AK23

AK3

AK52 AL10

AL13

AL17 AL20

AL22

AL23 AL26

AL29 AL31

AL33

AL36 AL39

AL40

AL45 AL46

AL51

AL52 AL54

AL57 AL60

AL61

AM1 AM17

AM23

AM31 AM52

AN17

AN23 AN31

AN32 AN35

AN36

AN39 AN40

AN42

AN43 AN45

AN46

AN48 AN49

AN51 AN52

AN60

AN63 AN7

AP10

AP17 AP20

201

MF

1/20W

100

5%

PLACE_NEAR=U0500.E62:50.8mm

R0960

1

2

53

70

2C+GT2

BGA-TSP

HASWELL-ULT

OMIT_TABLE

CRITICAL

U0500

AP22

AP23 AP26

AP29

AP3 AP31

AP38

AP39 AP48

AP52

AP54 AP57

AR11 AR15

AR17

AR23 AR31

AR33

AR39 AR43

AR49

AR5 AR52

AT13 AT35

AT37

AT40 AT42

AT43

AT46 AT49

AT61

AT62 AT63

AU1 AU16

AU18

AU20 AU22

AU24

AU26 AU28

AU30

AU33 AU51

AU53 AU55

AU57

AU59 AV14

AV16

AV20 AV24

AV28

AV33 AV34

AV36 AV39

AV41

AV43 AV46

AV49

AV51 AV55

AV59

AV8 AW16

AW24

AW33 AW35

AW37

AW4 AW40

AW42

AW44 AW47

AW50 AW51

AW59

AW60 AY11

AY16

AY18 AY22

AY24

AY26 AY30

AY33 AY4

AY51

AY53 AY57

AY59

AY6 B20

B24

B26 B28

B32 B36

B4

B40 B44

B48

B52 B56

B60

C11 C14

C18 C20

C25

C27 C38

C39

C57 D12

D14

D18 D2

D21 D23

D25

D26 D27

D29

D30 D31

2C+GT2

BGA-TSP

HASWELL-ULT

OMIT_TABLE

CRITICAL

U0500

AH16

AH46

D33

D34 D35

D37

D38 D39

D41

D42 D43

D45

D46 D47

D49

D5

D50

D51 D53

D54

D55 D57

D59

D62

D8

E11 E17

F20

F26 F30

F34

F38 F42

F46

F50 F54

F58 F61

G18

G22

G3

G5

G6 G8

H13

H17

H57 J10

J22

J59 J63

K1

K12 L13

L15

L17 L18

L20 L58

L61

L7 M22

N10

N3 P59

P63

R10 R22

R8

E62

T1

T58

U20 U22

U61

U9 V10

V23

V3

V58

V7 W20

W22 Y10

Y59

Y63

CPU/PCH GROUNDS

SYNC_MASTER=J44

SYNC_DATE=08/12/2013

CPU_VCCSENSE_N

9 OF 78

9 OF 120

<SCH_NUM>

w w w . c h i n a f i x . c o m

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

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87

6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Intel recommendation (Table 5-1): 23x 22uF 0805 stuff, 7x 22uF 0805 nostuff Apple implementation : 18x 22uF 0603 stuff, 80x 22uF 0603 nostuff

All Intel recommendations from Intel doc #503160 Shark Bay Ultrabook Platform Power Delivery Design Guide Rev 0.9 unless stated otherwise

1x Bulk nostuff, Harris Beach has 2x nostuff

Added 2 extra 2.2uF per Harris Beach v0.9 schematic

CPU VDDQ DECOUPLING

Intel recommendation (Table 5-4): 2x 2.2uF 0402, 6x 10uF 0603

CPU VCC Decoupling

Apple implementation : 2x 2.2uF 0402, 6x 10uF 0402

CPU VCC Decoupling

CRITICAL

0402

X6S

4V

10UF

20%

C1000

1

2

20%

6.3V CERM-X5R 0402-1

10UF

C1050

1

2

20%

6.3V

10UF

0402-1

CERM-X5R

C1051

1

2

CERM-X5R

20%

6.3V

10UF

0402-1

C1052

1

2

CERM-X5R

20%

6.3V

0402-1

10UF

C1053

1

2

20%

6.3V CERM-X5R 0402-1

10UF

C1054

1

2

20%

6.3V CERM-X5R 0402-1

10UF

C1055

1

2

20%

2.2UF

402-LF

CERM

6.3V

C1040

1

2

20%

2.2UF

CERM

6.3V

402-LF

C1041

1

2

2.2UF

20%

402-LF

CERM

6.3V

C1042

1

2

CERM 402-LF

2.2UF

20%

6.3V

C1043

1

2

TANT

2V

CASE-B2-SM

270UF

20%

C1060

1

2

TANT

2V

270UF

20%

CASE-B2-SM

NO STUFF

C1061

1

2

CRITICAL

NO STUFF

X6S 0402

4V

10UF

20%

C1001

1

2

NO STUFF

0402

10UF

CRITICAL

20%

X6S

4V

C1002

1

2

10UF

NO STUFF

20%

CRITICAL

X6S

4V

0402

C1003

1

2

CRITICAL

10UF

0402

20%

X6S

4V

C1004

1

2

X6S

20%

CRITICAL

4V

0402

10UF

C1008

1

2

NO STUFF

20% 4V

CRITICAL

10UF

X6S 0402

C1009

1

2

NO STUFF

X6S

20%

CRITICAL

4V

0402

10UF

C1010

1

2

X6S

4V

0402

20%

CRITICAL

10UF

NO STUFF

C1011

1

2

CRITICAL

10UF

X6S

4V

0402

20%

C1012

1

2

20%

CRITICAL

10UF

4V

NO STUFF

0402

X6S

C1014

1

2

CRITICAL

20% 4V X6S

10UF

0402

C1018

1

2

CRITICAL

4V

0402

X6S

20%

10UF

C1019

1

2

CRITICAL

10UF

0402

4V X6S

20%

C1020

1

2

4V

CRITICAL

20%

10UF

X6S 0402

NO STUFF

C1021

1

2

CRITICAL

10UF

20%

X6S

4V

0402

NO STUFF

C1084

1

2

CRITICAL

0402

10UF

20% 4V X6S

NO STUFF

C1083

1

2

CRITICAL

0402

10UF

20%

X6S

4V

NO STUFF

C1082

1

2

CRITICAL

20%

0402

4V X6S

NO STUFF

10UF

C1081

1

2

NO STUFF

CRITICAL

10UF

20% 4V X6S 0402

C1077

1

2

20%

10UF

NO STUFF

CRITICAL

0402

X6S

4V

C1075

1

2

CRITICAL

10UF

20% 4V X6S 0402

C1074

1

2

4V

10UF

20%

X6S

CRITICAL

NO STUFF

0402

C1073

1

2

0402

20% 4V X6S

10UF

NO STUFF

CRITICAL

C1072

1

2

4V X6S

CRITICAL

0402

10UF

20%

C1070

1

2

4V X6S

20%

0402

CRITICAL

NO STUFF

10UF

C1097

1

2

CRITICAL

10UF

20%

X6S

4V

0402

NO STUFF

C1096

1

2

4V X6S

20%

0402

NO STUFF

10UF

CRITICAL

C1095

1

2

CRITICAL

4V X6S

10UF

20%

0402

NO STUFF

C1094

1

2

CRITICAL

4V X6S

20%

0402

10UF

NO STUFF

C1093

1

2

4V X6S

20%

10UF

0402

NO STUFF

CRITICAL

C1092

1

2

NO STUFF

10UF

X6S

20% 4V

0402

CRITICAL

C1091

1

2

CRITICAL

4V X6S

10UF

20%

0402

NO STUFF

C1090

1

2

NO STUFF

CRITICAL

20%

0402

4V X6S

10UF

C1089

1

2

20%

0402

4V X6S

CRITICAL

10UF

NO STUFF

C1088

1

2

NO STUFF

4V X6S

20%

0402

10UF

CRITICAL

C1087

1

2

NO STUFF

0402

10UF

X6S

4V

20%

CRITICAL

C1086

1

2

X6S

10UF

NO STUFF

0402

4V

20%

CRITICAL

C1085

1

2

X6S

4V

20%

10UF

0402

NO STUFF

C1038

1

2

NO STUFF

20%

10UF

X6S

4V

0402

C1037

1

2

NO STUFF

10UF

20%

X6S 0402

4V

C1036

1

2

NO STUFF

X6S

4V

10UF

20%

0402

C1035

1

2

CRITICAL

4V

20%

X6S 0402

10UF

C1034

1

2

NO STUFF

10UF

X6S

4V

20%

0402

C1033

1

2

NO STUFF

10UF

4V X6S

20%

0402

C1032

1

2

NO STUFF

10UF

4V

20%

0402

X6S

C1029

1

2

X6S

4V

20%

10UF

0402

NO STUFF

C109A

1

2

4V

20%

10UF

X6S 0402

NO STUFF

C1099

1

2

10UF

20%

X6S

4V

0402

NO STUFF

C1098

1

2

0402

10UF

4V X6S

20%

NO STUFF

C107B

1

2

NO STUFF

0402

X6S

10UF

4V

20%

C107A

1

2

0402

20% 4V X6S

10UF

NO STUFF

C1069

1

2

NO STUFF

20%

10UF

4V X6S 0402

C1068

1

2

10UF

0402

X6S

4V

20%

NO STUFF

C108F

1

2

10UF

20%

X6S

4V

0402

NO STUFF

C1067

1

2

0402

10UF

X6S

4V

20%

NO STUFF

C108E

1

2

20%

10UF

NO STUFF

X6S

4V

0402

C1066

1

2

NO STUFF

10UF

0402

20% 4V X6S

C108D

1

2

0402

10UF

20% 4V X6S

NO STUFF

C108C

1

2

10UF

X6S

4V

0402

CRITICAL

20%

C1065

1

2

NO STUFF

20%

X6S

4V

10UF

0402

C1028

1

2

NO STUFF

20%

X6S

4V

10UF

0402

C1027

1

2

20%

NO STUFF

10UF

4V X6S 0402

C1049

1

2

NO STUFF

10UF

X6S

20% 4V

0402

C1048

1

2

20%

0402

X6S

CRITICAL

10UF

4V

C1026

1

2

NO STUFF

20%

10UF

X6S 0402

4V

C1047

1

2

NO STUFF

0402

X6S

4V

20%

10UF

C1025

1

2

NO STUFF

20%

X6S

4V

0402

10UF

C1024

1

2

NO STUFF

20% 4V X6S 0402

10UF

C1046

1

2

NO STUFF

X6S

20% 4V

10UF

0402

C1045

1

2

NO STUFF

20% 4V

10UF

X6S 0402

C1023

1

2

4V

0402

10UF

20%

X6S

CRITICAL

C1022

1

2

NO STUFF

10UF

4V X6S

20%

0402

C1044

1

2

20% 4V X6S

10UF

0402

NO STUFF

C1039

1

2

10UF

4V

20%

0402

X6S

NO STUFF

C1064

1

2

NO STUFF

10UF

0402

4V

20%

X6S

C108B

1

2

NO STUFF

20%

10UF

4V X6S 0402

C1063

1

2

NO STUFF

10UF

0402

4V X6S

20%

C108A

1

2

X6S

4V

0402

20%

NO STUFF

10UF

C1062

1

2

NO STUFF

0402

20% 4V

10UF

X6S

C109F

1

2

NO STUFF

0402

10UF

20% 4V X6S

C109E

1

2

NO STUFF

10UF

X6S

4V

20%

0402

C1059

1

2

NO STUFF

20%

X6S

4V

10UF

0402

C1058

1

2

NO STUFF

0402

X6S

4V

20%

10UF

C109D

1

2

4V

20%

10UF

X6S

NO STUFF

0402

C1057

1

2

0402

4V

10UF

NO STUFF

20%

X6S

C109C

1

2

NO STUFF

4V

0402

10UF

X6S

20%

C1056

1

2

NO STUFF

10UF

0402

20% 4V X6S

C109B

1

2

470UF-0.0045OHM

CRITICAL

20%

POLY-TANT

2.5V

SM

C1031

1

2

3

20% 4V

CRITICAL

10UF

0402

X6S

NO STUFF

C1030

1

2

CRITICAL

0402

X6S

NO STUFF

4V

10UF

20%

C104E

1

2

20%

10UF

4V

CRITICAL

0402

X6S

C104F

1

2

20%

10UF

X6S

4V

CRITICAL

NO STUFF

0402

C106D

1

2

20%

10UF

4V

0402

NO STUFF

X6S

CRITICAL

C106E

1

2

CRITICAL

4V X6S 0402

20%

10UF

C105A

1

2

CRITICAL

X6S

10UF

0402

4V

20%

NO STUFF

C105B

1

2

CRITICAL

0402

4V

20%

X6S

10UF

C105C

1

2

CRITICAL

0402

X6S

4V

20%

10UF

C105D

1

2

20%

X6S

4V

CRITICAL

10UF

NO STUFF

0402

C105E

1

2

10UF

0402

CRITICAL

20% 4V X6S

C105F

1

2

SYNC_DATE=08/12/2013

SYNC_MASTER=J44

CPU Decoupling

PP1V35_S3_CPUDDR

PPVCC_S0_CPU

10 OF 120

<SCH_NUM>

10 OF 78

8

41

65 73

8

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54 65 68

w w w . c h i n a f i x . c o m

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87

6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

as well as from clarification email, from Srini, dated 9/10/2012 2:11pm.

LPT-LP current estimates from Lynx Point-LP PCH EDS, doc #503118, v1.0

PCH VCCSUSHDA BYPASS

(PCH 3.3V/1.8V SDIO PWR)

PCH VCCSDIO BYPASS

(PCH 3.3V/1.5V HDA PWR)

(PCH 3.3V SUSPEND RTC PWR)

(PCH 3.3V SPI PWR)

PCH VCCSPI BYPASS

(PCH 3.3V SUSPEND PWR)

PCH VCCSUS3_3 BYPASS

(PCH 3.3V DSW PWR)

(PCH 1.05V ACLK PLL PWR)

PCH VCCACLKPLL FILTER/BYPASS

PCH VCCCLK FILTER/BYPASS (PCH 1.05V VCCCLK PWR)

PCH VCCIO BYPASS (PCH 1.05V USB2 PWR)

(PCH 3.3V THERMAL PWR)

PCH VCC3_3 BYPASS

(PCH 3.3V GPIO/LPC PWR)

PCH VCC3_3 BYPASS

PCH VCCCLK BYPASS (PCH 1.05V CLK PWR)

(PCH 1.05V OPI PLL PWR)

(PCH 1.05V ME CORE PWR)

PCH VCCASW BYPASS

(PCH 1.05V CORE PWR)

PCH VCC BYPASS

PCH VCCSUS3_3 BYPASS

PCH VCCDSW3_3 BYPASS

PCH VCCSATA3PLL FILTER/BYPASS (PCH 1.05V SATA3 PLL PWR)

41mA Max

83mA Max 42mA Max

??mA Max

31mA Max

57mA Max

PCH OPI VCCAPLL FILTER/BYPASS

??mA Max

(PCH 1.05V USB3 PLL PWR)

PCH VCCUSB3PLL FILTER/BYPASS

(PCH 1.05V PCIe/SATA/USB3 PWR)

PCH VCCHSIO BYPASS

NO STUFF

10V

20%

0.1UF

402

CERM

BYPASS=U0500.Y8:6.35mm

C1202

1

2

NO STUFF

CRITICAL

2.2UH-240MA-0.221OHM

0603

L1280

12

1/16W

5%

402

MF-LF

0

R1280

12

BYPASS=U0500.B18:12.7mm

CERM-X5R

4V

20%

0805-1

47UF

C1295

1

2

BYPASS=U0500.B18:12.7mm

CERM-X5R

4V

20%

0805-1

47UF

NO STUFF

C1296

1

2

47UF

20%

BYPASS=U0500.B11:12.7mm

0805-1

CERM-X5R

4V

C1290

1

2

4V

20%

CERM-X5R

0805-1

BYPASS=U0500.B11:12.7mm

NO STUFF

47UF

C1291

1

2

NO STUFF

CERM-X5R

4V

20%

47UF

0805-1

BYPASS=U0500.AA21:12.7mm

C1280

1

2

NO STUFF

0805-1

47UF

20%

4V

CERM-X5R

BYPASS=U0500.AA21:12.7mm

C1281

1

2

CERM-X5R

0805-1

47UF

20%

4V

BYPASS=U0500.J18:12.7mm

C1275

1

2

BYPASS=U0500.J18:12.7mm

CERM-X5R

4V

20%

47UF

0805-1

C1276

1

2

4V

20%

47UF

0805-1

BYPASS=U0500.A20:12.7mm

CERM-X5R

C1270

1

2

BYPASS=U0500.A20:12.7mm

0805-1

47UF

20%

4V

CERM-X5R

C1271

1

2

NO STUFF

BYPASS=U0500.AH10:6.35mm

1UF

CERM

402

10%

6.3V

C1200

1

2

402

CERM

1UF

10%

BYPASS=U0500.AH14:6.35mm

6.3V

C1210

1

2

0.1UF

20% 10V

402

CERM

BYPASS=U0500.K14:6.35mm

C1214

1

2

10%

1UF

6.3V CERM

402

BYPASS=U0500.AH11:6.35mm

C1206

1

2

6.3V

10%

1UF

BYPASS=U0500.AG16:6.35mm

CERM

402

C1264

1

2

BYPASS=U0500.L10:6.35mm

402

CERM

1UF

10%

6.3V

C1261

1

2

6.3V

BYPASS=U0500.M9:6.35mm

20%

10UF

0402-1

CERM-X5R

C1262

1

2

BYPASS=U0500.J17:6.35mm

10%

1UF

402

CERM

6.3V

C1266

1

2

10UF

X5R 603

20%

6.3V

BYPASS=U0500.J11:12.7mm

C1255

1

2

NO STUFF

603

22UF

20%

6.3V

X5R-CERM-1

BYPASS=U0500.AE9:12.7mm

C1250

1

2

CERM

1UF

10%

402

6.3V

BYPASS=U0500.J11:6.35mm

C1256

1

2

1UF

CERM 402

10%

6.3V

BYPASS=U0500.AE8:6.35mm

C1257

1

2

1UF

CERM 402

10%

6.3V

BYPASS=U0500.AE9:6.35mm

C1251

1

2

BYPASS=U0500.R21:6.35mm

10%

1UF

402

CERM

6.3V

C1267

1

2

BYPASS=U0500.AC9:12.7mm

603

22UF

20%

X5R-CERM-1

6.3V

C1204

1

2

603

BYPASS=U0500.V8:12.7mm

X5R-CERM-1

6.3V

20%

22UF

C1212

1

2

10%

1UF

6.3V CERM

402

BYPASS=U0500.U8:6.35mm

C1208

1

2

CERM

6.3V

10%

402

BYPASS=U0500.K9:6.35mm

1UF

C1260

1

2

BYPASS=U0500.J18:6.35mm

1UF

X5R 402

10% 10V

C1277

1

2

CRITICAL

0603

2.2UH-240MA-0.221OHM

L1275

12

BYPASS=U0500.B18:6.35mm

1UF

X5R 402

10% 10V

C1297

1

2

0603

CRITICAL

2.2UH-240MA-0.221OHM

L1295

12

1UF

X5R 402

10% 10V

BYPASS=U0500.B11:6.35mm

C1292

1

2

0603

CRITICAL

2.2UH-240MA-0.221OHM

L1290

12

MF-LF

402

5%

0

1/16W

R1275

12

BYPASS=U0500.A20:6.35mm

10V

10%

402

X5R

1UF

C1272

1

2

2.2UH-240MA-0.221OHM

CRITICAL

0603

L1270

12

0

1/16W MF-LF

402

5%

R1270

12

BYPASS=U0500.AA21:6.35mm

10V

10%

402

X5R

1UF

C1282

1

2

PCH Decoupling

SYNC_MASTER=J44

SYNC_DATE=08/12/2013

PP1V05_S0SW_PCH_HSIO

PP1V05_S0SW_PCH_VCCSATA3PLL

MIN_LINE_WIDTH=0.2 MM VOLTAGE=1.05V

MIN_NECK_WIDTH=0.075 MM

PP1V05_S0_PCH_VCCACLKPLL_R

MIN_LINE_WIDTH=0.2 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V

MIN_LINE_WIDTH=0.2 MM VOLTAGE=1.05V

MIN_NECK_WIDTH=0.075 MM

PP1V05_S0SW_PCH_VCCUSB3PLL

MIN_NECK_WIDTH=0.2 MM

PP1V05_S0_PCH_VCC_ICC_R

MIN_LINE_WIDTH=0.2 MM VOLTAGE=1.05V

PP1V05_S0_PCH_VCCACLKPLL

MIN_LINE_WIDTH=0.2 MM

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.075 MM

PP1V05_S0_PCH_VCC_ICC

MIN_LINE_WIDTH=0.2 MM

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.075 MM

PP1V05_S0_PCH_VCCAPLL_OPI

MIN_NECK_WIDTH=0.075 MM VOLTAGE=1.05V

MIN_LINE_WIDTH=0.2 MM

PP1V05_S0

PP3V3_S0

PP1V05_S0

PP3V3_SUS

PP3V3_S5

PP1V5_S0SW_AUDIO_HDA

PP3V3_S0

PP3V3_SUS

11 OF 78

12 OF 120

<SCH_NUM>

8

11

60 65

8

11

60 65

8

12

8

14

8

12

8

6

8

11

15 16 17 37 53 57 60

61 65 68

6 8 11

15 16 17 37 53 57 60

61 65 68

6 8 11

15 16 17 37 53 57 60

61 65 68

6 8 11

15 16 17 37 53 57 60

61 65 68

8

11

12 13 15 17 18 24 28 30

37 38 39 40 41 42 43 44 46 47

50 61 62 64 65 68 77

8

11

12 13 15 17 18 24 28 30

37 38 39 40 41 42 43 44 46 47

50 61 62 64 65 68 77

6 8 11

15 16 17 37 53 57 60

61 65 68

8

11

14 45 59 60 61 65

8

11

14 45 59 60 61 65

8

13

15 16 17 18 26 27 29 56

59 60 61 65 68 77

8

17

60

8

11

12 13 15 17 18 24 28 30

37 38 39 40 41 42 43 44 46 47

50 61 62 64 65 68 77

8

11

14 45 59 60 61 65

w w w . c h i n a f i x . c o m

IN IN

IN

OUT

BI

OUT

IN

NC NC

NC

IN

OUT

RSVD

HDA_DOCK_EN*/I2S1_TXD

HDA_BCLK/I2S0_SCLK

RTCX1 RTCX2

RTCRST*

INTVRMEN

INTRUDER*

SRTCRST*

HDA_RST*/I2S_MCLK

HDA_SYNC/I2S0_SFRM

HDA_SDI0/I2S0_RXD HDA_SDI1/I2S1_RXD

HDA_SDO/I2S0_TXD

HDA_DOCK_RST*/I2S1_SFRM

I2S1_SCLK

SATA_RN0/PERN6_L3 SATA_RP0/PERP6_L3

SATA_TN0/PETN6_L3 SATA_TP0/PETP6_L3

SATA_RN1/PERN6_L2 SATA_RP1/PERP6_L2

SATA_TN1/PETN6_L2 SATA_TP1/PETP6_L2

SATA_RN2/PERN6_L1 SATA_RP2/PERP6_L1

SATA_TN2/PETN6_L1 SATA_TP2/PETP6_L1

SATA_RN3/PERN6_L0 SATA_RP3/PERP6_L0

SATA_TN3/PETN6_L0 SATA_TP3/PETP6_L0

SATA0GP/GPIO34 SATA1GP/GPIO35 SATA2GP/GPIO36 SATA3GP/GPIO37

SATA_IREF

PCH_TRST*

PCH_TDI

PCH_TCK

PCH_TDO

RSVD

PCH_TMS

JTAGX

RSVD

RSVD SATALED*

SATA_RCOMP

AUDIO

SYM 5 OF 19

SATA

JTAG

RTC

OUT

IN

OUT

IN

NC NC

OUT

CLKOUT_LPC_1

CLKOUT_LPC_0

CLKOUT_ITPXDP_N CLKOUT_ITPXDP_P

PCIECLKRQ5*/GPIO23

PCIECLKRQ4*/GPIO22

CLKOUT_PCIE_N5 CLKOUT_PCIE_P5

PCIECLKRQ3*/GPIO21

CLKOUT_PCIE_P4

CLKOUT_PCIE_N4

PCIECLKRQ2*/GPIO20

CLKOUT_PCIE_P3

CLKOUT_PCIE_N3

PCIECLKRQ1*/GPIO19

CLKOUT_PCIE_P2

CLKOUT_PCIE_N2

PCIECLKRQ0*/GPIO18

CLKOUT_PCIE_P1

CLKOUT_PCIE_N1

CLKOUT_PCIE_N0

XTAL24_OUT

XTAL24_IN

CLKOUT_PCIE_P0

TESTLOW

TESTLOW TESTLOW

DIFFCLK_BIASREF

RSVD

SYM 6 OF 19

CLOCK SIGNALS

OUT

OUT OUT

IN IN

IN

OUT OUT

OUT

IN

OUT

OUT OUT

IN

OUT OUT

IN

NC NC

OUT

IN

OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87

6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

(IPU)

(IPD-PLTRST#)

SSD Lane 1

SATA Port assignments:

Reserved: ODD

Primary HDD/SSD

Unused

Secondary HDD/SSD

(IPD)

(IPU)

(IPD-PLTRST#)

(IPD-PWROK)

SSD Lane 3

PCIe Port assignments:

SSD Lane 2

SSD Lane 0

(IPD)

16

70

100K

1/20W

5%

201

MF

R1345

12

201

1/20W

5% MF

100K

R1375

12

16

100K

5%

201

MF

1/20W

R1343

12

16

70

16 70

47 72

PLACE_NEAR=U0500.AU8:1.27mm

1/20W

5% MF33201

R1312

12

1/20W

5%

33

MF

PLACE_NEAR=U0500.AV11:1.27mm

201

R1311

12

47

68 72

MF

201

5%

1/20W

33

PLACE_NEAR=U0500.AW8:1.27mm

R1310

12

17

72

330K

1/20W

5%

201

MF

R1302

1

2

1/20W

5%

201

MF

1M

R1301

1

2

1UF

X5R 402

10% 10V

C1300

1

2

20K

MF

201

5%

1/20W

R1300

1

2

X5R 402

1UF

10% 10V

C1303

1

2

MF

1/20W

20K

201

5%

R1303

1

2

6

16

70

201

MF

3.01K

1/20W

1%

PLACE_NEAR=U0500.C12:2.54mm

R1370

1

2

30

68 70

CRITICAL

OMIT_TABLE

2C+GT2

HASWELL-ULT

BGA-TSP

U0500

AW8

AW10 AV10

AU8

AY10

AU12

AU11

AV11

AY8

AU6

AV7

AE63

AE62

AD61

AE61

AD62

AU62

AC4

AL11

AV2

K10

L11

AU7

AW5

AY5

V1

U1 V6

AC1

A12

C12

J5

J8

J6

F5

H5

H8

H6

E5

B15

A17

B14

C17

A15

B17

C15

D17

U3

AV6

30

68 70

30 68 70

OMIT_TABLE

CRITICAL

2C+GT2

HASWELL-ULT

BGA-TSP

U0500

B35

A35

AN15

AP15

C43

B41

C41

B38

A39

B37

C42

A41

B42

C37

B39

A37

C26

U2

Y5

AD1

N1

U5

T2

K21 M21

AK8 AL8

C34

C35

A25 B25

30

68 70

30 68 70

12 63

63 68 70

47 72

12 31

32 68 70

23 68 70

12 23

30 68 70

12 30

3.01K

MF 201

1%

PLACE_NEAR=U0500.C26:2.54mm

1/20W

R1380

1

2

17

72

17 72

201

5%

1/20W

MF

10K

R1390

12

5%

10K

1/20W

201

MF

R1391

12

5%

10K

1/20W

MF

201

R1392

12

201

MF

1/20W

10K

5%

R1393

12

17

72

17 72

17

MF5%

1/20W

33

PLACE_NEAR=U0500.AU11:1.27mm

201

R1313

12

1/20W

100K

MF

201

5%

R1341

12

1/20W

5%

201

MF

100K

R1344

12

100K

MF

201

5%

1/20W

R1340

12

1/20W

100K

201

MF5%

R1342

12

SYNC_MASTER=J44

SYNC_DATE=08/12/2013

PCH Audio/JTAG/SATA/CLK

SSD_CLKREQ_L

TBT_CLKREQ_L

FW_CLKREQ_L

XDP_SSD_PCIE1_SEL_L

XDP_SSD_PCIE2_SEL_L

XDP_SSD_PCIE3_SEL_L

PCIE_SSD_R2D_C_P<2>

PCIE_SSD_D2R_P<2>

PCIE_SSD_D2R_N<2>

PP1V05_S0SW_PCH_VCCSATA3PLL

PCIE_SSD_R2D_C_N<0>

PCH_JTAGX

XDP_PCH_TDI

XDP_PCH_TMS

XDP_PCH_TDO

PCH_SRTCRST_L

PCH_INTVRMEN

RTC_RESET_L

PPVRTC_G3H

PP1V05_S0_PCH_VCCACLKPLL

PCH_SATALED_L

PCH_DIFFCLK_BIASREF

LPC_CLK24M_LPCPLUS_R

PP3V3_S0

HDA_RST_R_L

HDA_SDOUT

PCH_TESTLOW_C35

PCIE_SSD_R2D_C_P<0>

HDA_SYNC

PCH_CLK32K_RTCX1

PCH_TESTLOW_AL8

PCH_TESTLOW_AK8

LPC_CLK24M_SMC_R

TP_ITPXDP_CLK100MP

TP_ITPXDP_CLK100MN

PCIE_SSD_R2D_C_N<1> PCIE_SSD_R2D_C_P<1>

PCIE_SSD_D2R_N<1> PCIE_SSD_D2R_P<1>

PCIE_SSD_D2R_N<3> PCIE_SSD_D2R_P<3>

PCIE_SSD_R2D_C_P<3>

PCIE_SSD_R2D_C_N<3>

PCIE_SSD_R2D_C_N<2>

HDA_SDOUT_R

PCH_TESTLOW_C34

PCIE_SSD_D2R_N<0> PCIE_SSD_D2R_P<0>

HDA_BIT_CLK

PCH_INTRUDER_L

XDP_SSD_PCIE0_SEL_L

NC_HDA_SDIN1

PCH_SATALED_L

ENETSD_CLKREQ_L CAMERA_CLKREQ_L AP_CLKREQ_L

HDA_RST_L

XDP_CPUPCH_TRST_L

TP_PCH_I2S1_SCLK

XDP_PCH_TCK

TP_PCH_I2S1_SFRM

TP_PCH_I2S1_TXD

NC_RTC_CLK32K_RTCX2

HDA_SDIN0

HDA_SYNC_R

HDA_BIT_CLK_R

PCH_CLK24M_XTALIN PCH_CLK24M_XTALOUT

PCH_SATA_RCOMP

NC_PCIE_CLK100M_FWP

FW_CLKREQ_L

NC_PCIE_CLK100M_FWN

NC_PCIE_CLK100M_ENETSDN NC_PCIE_CLK100M_ENETSDP

ENETSD_CLKREQ_L

PCIE_CLK100M_CAMERA_N PCIE_CLK100M_CAMERA_P

CAMERA_CLKREQ_L

PCIE_CLK100M_AP_N

AP_CLKREQ_L

PCIE_CLK100M_AP_P

PCIE_CLK100M_TBT_N PCIE_CLK100M_TBT_P

TBT_CLKREQ_L

PCIE_CLK100M_SSD_N PCIE_CLK100M_SSD_P

SSD_CLKREQ_L

12 OF 78

<SCH_NUM>

13 OF 120

12

30

12 23

12

8

11

72

8

13

17 65

8

11

12

8

11 13

15 17 18 24 28 30 37 38

39 40 41 42 43 44 46 47 50 61

62 64 65 68 77

72

17 72

72

66

12

12 68

12 31

12 63

72

66

12

66

12 68

w w w . c h i n a f i x . c o m

IN

OUT

IN

OUT

IN

OUT

SLP_WLAN*/GPIO29

SLP_S0*

BATLOW*/GPIO72

ACPRESENT/GPIO31

PWRBTN*

SUSWARN*/SUSPWRDNACK/GPIO30

RSMRST*

PCH_PWROK

APWROK

SYS_RESET*

SUSACK*

PLTRST*

SYS_PWROK

DPWROK

DSWVRMEN

CLKRUN*/GPIO32

WAKE*

SLP_S5*/GPIO63

SUSCLK/GPIO62

SUS_STAT*/GPIO61

SLP_S4*

SLP_S3*

SLP_A*

SLP_SUS*

SLP_LAN*

SYSTEM POWER MANAGEMENT

SYM 8 OF 19

OUT

BI

IN

OUT

GPIO53

GPIO51

GPIO54

GPIO52

GPIO55

PME*

PIRQC*/GPIO79 PIRQD*/GPIO80

PIRQA*/GPIO77 PIRQB*/GPIO78

EDP_BKLEN

EDP_BKLCTL

EDP_HPD

DDPC_HPD

DDPC_AUXP

DDPB_AUXP

DDPB_HPD

DDPB_AUXN DDPC_AUXN

DDPC_CTRLCLK

DDPC_CTRLDATA

DDPB_CTRLCLK

DDPB_CTRLDATA

EDP_VDDEN

SIDEBAND

eDP

DISPLAY

PCI

SYM 9 OF 19

OUT

BI BI

BI

OUT

IN

IN IN IN IN

OUT OUT OUT

OUT

IN

OUT

IN

NC

08

NC

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87

6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

SLP_S0# Isolation

SLP_S0# can be driven high outside of S0 U1420 ensures signal will only be high in S0.

(IPD-PLTRST#)

(IPU)

(IPD-DeepSx)

(IPD-PLTRST#)

(IPU)

R1400 kept for debug purposes.

61

72

13 18 36

38

15 16 18

13 17 72

16 17 36 72

17 36 68 72

13 40 61

13 17 18 36 61 63 68

OMIT_TABLE

CRITICAL

HASWELL-ULT

2C+GT2

BGA-TSP

U0500

AJ8

AB5

AN4

V5

AV5

AW7

AY7

AG7

AL7

AW6

AL5

AJ7AF3

AT4

AJ6

AP5

AP4

AM5

AG4

AK2

AE6

AV4

AG2

AC3

AJ5

13

18 29 36 61 63

13 36 61

37

36 45 68

13 36 45 68

13 29 31 72

5%

201

1/20W MF

100K

R1451

1

2

36

72

5%

201

1/20W MF

330K

R1450

1

2

13

62

62 68

2C+GT2

BGA-TSP

CRITICAL

OMIT_TABLE

HASWELL-ULT

U0500

C5

B5

B9 C9

C8

B6

A6

D9 D11

A8

B8

A9

D6

C6

R5

L1

L4

L3

U7

U6 P4 N4 N2

AD4

13

62

23 74

64 66 74

23 74

28

64 66

28

23

64 66

62

5% 201

1/20W

MF

100K

R1446

12

5% 201

1/20W

MF

100K

R1445

12

5% 201

1/20W

MF

100K

R1442

12

5% 201

1/20W

MF

100K

R1443

12

5% 201

1/20W

MF

10K

R1441

12

5%

0

0201

1/20W

MF

NO STUFF

R1400

1

2

5% 201

1/20W

MF

100K

R1440

12

13

24

13 36

13 68

13 64 66

13 68

13 25 36

5%

201

1/20W

MF

10K

R1455

12

5%

201

1/20W

MF

10K

R1410

12

5% 201

1/20W

MF

100K

R1447

12

5% 201

1/20W

MF

100K

R1448

12

5% 201

1/20W

MF

100K

R1449

12

5%

201

1/20W

MF

100K

R1431

12

5%

201

1/20W

MF

100K

R1430

12

36

37

13 61

5%

201

1/20W

MF

1K

R1405

12

5%

201

1/20W

MF

10K

R1452

12

5%

201

1/20W

MF

100K

R1460

12

5%

201

1/20W

MF

100K

R1461

12

5%

201

1/20W

MF

100K

R1462

12

5%

201

1/20W

MF

100K

R1464

12

5%

201

1/20W

MF

100K

R1463

12

13

16 36 72

SOT891

74LVC1G08

CRITICAL

U1420

2

1

35

6

4

0.1UF

10V

10% X5R-CERM

0201

C1420

1

2

SYNC_MASTER=J44

SYNC_DATE=08/12/2013

PCH PM/PCI/GFX

PCH_SUSWARN_L

PCH_SUSACK_L

DPMUX_HPD_OUT

DP_HDMI_TBT_AUX_P

NC_PM_SLP_A_L

DP_HDMI_TBT_AUX_N DP_TBTSNK0_AUXCH_C_P

DP_TBTSNK0_AUXCH_C_N

DP_TBTSNK0_DDC_DATA DP_HDMI_TBT_DDC_CLK

DP_TBTSNK0_HPD

DP_INT_HPD

PPVRTC_G3H

PM_SLP_S3_L

PM_SLP_S4_L

PM_CLK32K_SUSCLK_R PM_SLP_S5_L

PCIE_WAKE_L

DP_HDMI_TBT_DDC_DATA

DP_TBTSNK0_DDC_CLK

TP_PCH_SLP_LAN_L

PM_SLP_SUS_L

NC_PCI_PME_L

TBT_PWR_REQ_L SMC_RUNTIME_SCI_L AUD_IP_PERIPHERAL_DET AUD_I2C_INT_L

HDMITBTMUX_LATCH ENET_LOW_PWR

AUD_IPHS_SWITCH_EN

AUD_PWR_EN

ODD_PWR_EN_L

PM_BATLOW_L

SMC_ADAPTER_EN

PM_PWRBTN_L

PM_RSMRST_L

PLT_RESET_L

PM_PCH_PWROK

PM_PCH_SYS_PWROK

PM_SYSRST_L

LPC_PWRDWN_L

PM_CLKRUN_L

PM_DSW_PWRGD

PCH_DSWVRMEN

EDP_PANEL_PWR

PCIE_WAKE_L PM_CLKRUN_L PM_SLP_S5_L

SMC_RUNTIME_SCI_L

TBT_PWR_REQ_L

AUD_I2C_INT_L ODD_PWR_EN_L

HDMITBTMUX_LATCH ENET_LOW_PWR

AUD_IPHS_SWITCH_EN

AUD_PWR_EN

PP3V3_S5

PM_PWRBTN_L PM_BATLOW_L

TP_PCH_SLP_WLAN_L

EDP_BKLT_PWM

PP3V3_S0

PCH_PM_SLP_S0_L

PM_SLP_S0_L

EDP_BKLT_EN

PM_SLP_S4_L PM_SLP_S3_L PM_SLP_S0_L

AUD_IP_PERIPHERAL_DET

EDP_PANEL_PWR

EDP_BKLT_EN

PM_SLP_SUS_L

PP3V3_S0

13 OF 78

<SCH_NUM>

14 OF 120

68

8

12

17 65

66

72

13 29 31 72

13 36 45 68

13 36 61

13 36

13 24

13 68

13 64 66

13 68

13 61

8

11 15

16 17 18 26 27 29 56 59

60 61 65 68 77

13 16 36 72

13 25 36

8

11

12 13 15 17 18 24 28 30

37 38 39 40 41 42 43 44 46 47

50 61 62 64 65 68 77

13 18 29 36 61 63

13 17 18 36 61 63 68

13 18 36

13 68

13 62

13 40 61

8

11 12

13 15 17 18 24 28 30 37

38 39 40 41 42 43 44 46 47 50

61 62 64 65 68

77

w w w . c h i n a f i x . c o m

SPI_IO3

SPI_MISO

SPI_IO2

SPI_CS2*

SPI_MOSI

SPI_CS0*

SPI_CS1*

LFRAME*

LAD2 LAD3

LAD1

SPI_CLK

LAD0

SMBALERT*/GPIO11

SMBCLK

SMBDATA

SML0ALERT*/GPIO60

SML0CLK

SML0DATA

SML1CLK_GPIO75

SML1ALERT*/PCHHOT*/GPIO73

SML1DATA/GPIO74

CL_CLK

CL_DATA

CL_RST*

SYM 7 OF 19

LPC

SMBUS

SPI

C-LINK

OUT

IN IN IN

OUT

IN

OUT

IN IN

OUT OUT

IN IN

OUT OUT

IN

OUT

IN

OUT

PCIE_RCOMP PCIE_IREF

RSVD

PETP1/USB3TP2

PETN1/USB3TN2

PERP1/USB3RP2

PERN1/USB3RN2

PETP4

PETN4

PERP4

PERN4

PETP3

PETN3

PERP3

PERN3

PETP5_L3

PETN5_L3

PETP5_L2

PETN5_L2

PERP5_L2

PERN5_L2

PETP5_L1

PETN5_L1

PERP5_L1

PERN5_L1

PERN2/USB3RN3 PERP2/USB3RP3

PETN2/USB3TN3 PETP2/USB3TP3

USB2P7

USB2N7

PERP5_L3

PERN5_L3

PETP5_L0

PETN5_L0

PERP5_L0

PERN5_L0

OC1*/GPIO41

OC0*/GPIO40

OC2*/GPIO42 OC3*/GPIO43

RSVD RSVD

USBRBIAS*

USBRBIAS

USB3TP1

USB3TN1

USB3RP1

USB3RN1

USB3TP0

USB3TN0

USB3RP0

USB3RN0

USB2N0 USB2P0

USB2N1 USB2P1

USB2N2 USB2P2

USB2N3 USB2P3

USB2N4 USB2P4

USB2N5 USB2P5

USB2N6 USB2P6

USB

PCI-E

SYM 11 OF 19

IN

NC NC

OUT

IN

OUT

IN

OUT

IN

NC NC

BI

IN

BI

OUT

BI

OUT

BI BI

BI

OUT

IN

BI

OUT

BI

OUT

BI

IN

BI

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87

6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

page, may be wire-ORed into other signals.

SML1ALERT# pull-up not provided on this

Unused

(& Ethernet if combo)

Thunderbolt lane 3

Thunderbolt lane 2

Thunderbolt lane 1

PCIe Port Assignments:

USB3 Port Assignments:

Thunderbolt lane 0

Reserved: FireWire

AirPort

Camera

Ext B (SS)

USB Port Assignments:

Ext A (LS/FS/HS)

Ext B (LS/FS/HS)

BT

IR

Reserved: SD (HS)

(IPU/IPD)

(IPU)

(IPU/IPD)

(IPU)

Trackpad

Reserved: Camera

(IPD)

SD Card Reader

Ext A (SS)

Otherwise, 100k pull-up to 3.3V SUS required.

(IPU)

CRITICAL

2C+GT2

BGA-TSP

OMIT_TABLE

HASWELL-ULT

U0500

AF2

AD2

AF4

AU14

AW12 AY12

AW11

AV12

AN2

AP2 AH1

AL2

AN1 AK1

AU4

AU3 AH3

AA3

Y7

Y4

AC2

Y6

AF1

AA4

AA2

23

68 70

100K

5% MF

1/20W

201

R1580

12

100K

5%

1/20W

MF

201

R1581

12

14

16 33

14 16 63

14 16

38

14 16

23 68 70

14 68

23 68 70

63 71

63 68 71

32 70

32 68 70

63 68 70

OMIT_TABLE

2C+GT2

BGA-TSP

HASWELL-ULT

CRITICAL

U0500

AL3

AT1 AH2

AV3B27

A27

G17

F15

G11

F13

F10

F8

H10

E6

F17

G15

F11

G13

E10

E8

G10

F6

C30

B31

C29

B29

C23

B23

B21

B22

C31

A31

B30

A29

C22

A23

C21

A21

AM10

AN10

E13

E15

AN8

AR7

AR8

AR10

AM15

AM13

AP11

AR13

AM8

AT7

AP8

AT10

AL15

AN13

AN11

AP13

G20

E18

H20

F18

C33

B33

B34

A33

AJ11

AJ10

63

68 70

63 68 70

3.01K

201

MF

1%

PLACE_NEAR=U0500.A27:2.54mm

1/20W

R1500

1

2

63

68 71

63 68 71

33 68 71

23 68 70

33 68 71

22.6

201

1% 1/20W MF

PLACE_NEAR=U0500.AJ10:2.54mm

R1570

1

2

34

71

34 71

66 71

23 68 70

66 71

29 71

63 71

23 68 70

33 71

36 45 68 72

1/20W

5%

201

MF

33

R1543

12

201

1/20W

MF5%

33

R1542

12

23

68 70

33

MF

201

5%

1/20W

R1544

12

5%

1/20W

201

MF

33

R1540

12

1/20W

5%

201

MF

33

R1541

12

45

72

45 72

32 36 39 43 68 72 76

23 68 70

32 36 39 43 68 72 76

39 72

16 19 39 63 68 72

45 72

23 68 70

14 45 72

201

1/20W

MF5%

100K

R1591

12

1K

5% MF

1/20W

201

R1549

12

100K

5%

1/20W

MF

201

R1590

12

1K

5% MF

1/20W

201

R1548

12

100K

5%

1/20W

MF

201

R1582

12

100K

201

MF5%

1/20W

R1583

12

SYNC_DATE=08/12/2013

SYNC_MASTER=J44

PCH PCIe/USB/LPC/SPI/SMBus

PP3V3_SUS

XDP_USB_EXTD_OC_L

XDP_USB_EXTC_OC_L

XDP_USB_EXTB_OC_L

XDP_USB_EXTA_OC_L

WOL_EN

LPC_AD_R<0>

LPC_AD<2>

PCH_SML1ALERT_L

PP1V05_S0SW_PCH_VCCUSB3PLL

PCH_PCIE_RCOMP

USB_EXTA_P

USB_EXTB_P

USB_BT_N

NC_USB_IRP

USB_TPAD_N USB_TPAD_P

TP_USB_5N

USB_BT_P

NC_PCIE_FW_R2D_CN

LPC_AD_R<2>

LPC_AD_R<1>

LPC_FRAME_L

NC_USB_IRN

USB3_EXTA_D2R_P

USB_EXTB_N

PCIE_TBT_D2R_P<0>

PCIE_TBT_R2D_C_N<0>

USB3_EXTB_R2D_C_P

PCIE_AP_D2R_N

PCH_SMBALERT_L

TP_USB_5P

NC_USB_CAMERAN NC_USB_CAMERAP

NC_USB_SDP

NC_USB_SDN

USB_EXTA_N

USB3_EXTB_R2D_C_N

USB3_EXTB_D2R_P

USB3_EXTB_D2R_N

USB3_EXTA_R2D_C_N USB3_EXTA_R2D_C_P

USB3_EXTA_D2R_N

USB3RPCIE_SD_R2D_C_N

USB3RPCIE_SD_D2R_P

USB3RPCIE_SD_D2R_N

NC_PCIE_FW_R2D_CP

NC_PCIE_FW_D2RP

PCIE_AP_R2D_C_N

PCIE_AP_D2R_P

PCIE_TBT_R2D_C_P<3>

PCIE_TBT_R2D_C_N<3>

PCIE_TBT_R2D_C_P<2>

PCIE_TBT_R2D_C_N<2>

PCIE_TBT_D2R_P<2>

PCIE_TBT_D2R_N<2>

PCIE_TBT_R2D_C_P<1>

PCIE_TBT_R2D_C_N<1>

PCIE_TBT_D2R_P<1>

PCIE_TBT_D2R_N<1>

PCIE_CAMERA_D2R_N PCIE_CAMERA_D2R_P

PCIE_CAMERA_R2D_C_N

PCIE_TBT_D2R_P<3>

PCIE_TBT_D2R_N<3>

PCIE_TBT_R2D_C_P<0>

PCIE_AP_R2D_C_P

NC_PCIE_FW_D2RN

USB3RPCIE_SD_R2D_C_P

SPI_CLK_R

LPC_AD<0> LPC_AD<1>

LPC_AD<3>

SML_PCH_0_CLK

SMBUS_PCH_DATA

SMBUS_PCH_CLK

NC_CLINK_DATA

NC_CLINK_RESET_L

NC_CLINK_CLK

PCIE_TBT_D2R_N<0>

PCH_USB_RBIAS

TP_SPI_CS2_L

TP_SPI_CS1_L

SPI_CS0_R_L

PCIE_CAMERA_R2D_C_P

LPC_FRAME_R_L

LPC_AD_R<3>

SPI_MOSI_R

SPI_MISO

SPI_IO<3>

SPI_IO<2>

XDP_USB_EXTA_OC_L XDP_USB_EXTB_OC_L XDP_USB_EXTC_OC_L XDP_USB_EXTD_OC_L

SMBUS_SMC_1_S0_SDA

SMBUS_SMC_1_S0_SCL

SML_PCH_0_DATA

PP3V3_SUS

SPI_IO<2> SPI_IO<3>

PCH_SMBALERT_L WOL_EN

14 OF 78

15 OF 120

<SCH_NUM>

8

11

14 45 59 60 61 65

14 16

14 16 63

14 16 33

8

11

72

71

66

14

71

66

71

66 71

66

71

8

11

14 45 59 60 61 65

14 45 72

14

14 68

w w w . c h i n a f i x . c o m

IN

OUT

BI

OUT

IN

OUT

SERIRQ

THRMTRIP*

RCIN*/GPIO82

PCH_OPI_COMP

RSVD

GSPI0_CS*/GPIO83

GSPI0_MISO/GPIO85

GSPI0_CLK/GPIO84

GSPI1_CLK/GPIO88

GSPI1_CS*/GPIO87

GSPI0_MOSI/GPIO86

GSPI_MOSI/GPIO90

GSPI1_MISO/GPIO89

UART0_RXD/GPIO91

UART0_TXD/GPIO92

UART1_RXD/GPIO0

UART0_CTS*/GPIO94

UART0_RTS*/GPIO93

UART1_CTS*/GPIO3

UART1_RST*/GPIO2

UART1_TXD/GPIO1

I2C0_SCL/GPIO5

I2C1_SDA/GPIO6

I2C0_SDA/GPIO4

I2C1_SCL/GPIO7

SDIO_CMD/GPIO65

SDIO_CLK/GPIO64

SDIO_D1/GPIO67

SDIO_D2/GPIO68

SDIO_D0/GPIO66

SDIO_D3/GPIO69

BMBUSY*/GPIO76

GPIO8

LAN_PHY_PWR_CTRL/GPIO12

GPIO15

GPIO17

GPIO16

GPIO24

GPIO28

GPIO27

GPIO26

GPIO56

GPIO57

GPIO58

GPIO59

GPIO47

GPIO44

GPIO48

GPIO49

GPIO50

HSIOPC/GPIO71

GPIO13

GPIO25

GPIO14

GPIO45

GPIO46

GPIO9

GPIO10

DEVSLP0*/GPIO33

DEVSLP1*/GPIO38

SDIO_POWER_EN/GPIO70

DEVSLP2*/GPIO39

SPKR/GPIO81

SYM 10 OF 19

CPU/MISC

GPIO

LPIO

OUT

IN

BI

NC

OUT

NC

OUT

BI

OUT

IN

OUT

IN

BI

IN

BI

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87

6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

BOM OPTIONS

BOM GROUP

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

RR/FR: DPHDMIMUX_SEL_TBT, requires 100k pull-up to TBTLC

CR: TBT_GO2SX_BIDIR, requires 100k pull-up to SUS

Requires connection to SMC via 1K series R

platform does not use SD card

R1616 should also be stuffed if

(IPD-PLTRST#)

GPIO12:

Redwood Ridge: Alias to TBT_CIO_PLUG_EVENT_L, requires pull-up (S0).

Cactus Ridge: Alias to TBT_CIO_PLUG_EVENT, requires pull-down.

Pull-up/down on chipset support page (depends on TBT controller)

(IPD-PLTRST#)

(IPD-DeepSx)

(IPD-RSMRST#)

(IPD)

TBTLC for CR, S0 for RR

Pull-up on TBT page

1/20W

5% 201

MF

10K

R1652

12

MF5%

1/20W

100K

201

R1668

12

MF

2015%

1/20W

100K

R1669

12

MF

2015%

100K

1/20W

R1672

12

MF

2015%

1/20W

100K

R1674

12

MF

2015%

100K

1/20W

R1673

12

MF

2015%

1/20W

100K

R1675

12

MF

2015%

1/20W

100K

R1676

12

100K

1/20W

5% 201

MF

R1678

12

MF

2015%

1/20W

100K

R1677

12

100K

1/20W

5% 201

MF

R1679

12

5%

1/20W

MF

201

100K

R1639

1

2

1/20W

MF1K2015%

R1641

12

1/20W

MF

100K

2015%

R1629

12

201

MF

5%

100K

1/20W

R1621

1

2

13

15 16 18

18 23

23 64 66

15 36 45 68

63

15 29

MF

1/20W

100K

5%

201

R1671

1

2

13

15 16 18

15 64

15 18

100K

MF

2015%

1/20W

R1670

12

RAMCFG3:H

1/20W

5%

201

MF

100K

R1631

1

2

1/20W

5%

201

MF

100K

RAMCFG2:H

R1636

1

2

RAMCFG1:H

1/20W

5% MF

201

100K

R1635

1

2

RAMCFG0:H

100K

1/20W MF 201

5%

R1611

1

2

24

15

68

2C+GT2

HASWELL-ULT

BGA-TSP

CRITICAL

OMIT_TABLE

U0500

P1

P2

L2

N5

AM2

AT3

AH4

AD6

Y1

T3

AD5

AM4

AN3

AN5

AD7

AK4

AG5

AG3

AB6

U4

Y3

P3

AG6

AP1

AL4

AT5

AU2

AM3

L6

R6

N6

L8

L5

R7

N7

K2

Y2

F3

F2

F1

G4

AM7

AW15

V4

AB21

AF20

E3

F4

D3

E4

C3

E2

C4

T4

V2

D60

G1

J2

J1

K3

J4

J3

K4

G2

15

62

15 68

15 62 68

38

15 68

15 16

15 16 18

15 16 45 68

55

15 30 60 61

15 68

15 63

15 23

15 16

15 18

15 60

15 45 68 72

15 18

15 68

15 30

15 29

30

15 36

15 63

37 72

15 16

15 16 18

18 23 72

15 16 18

201

MF

1/20W

1K

5%

R1650

1

2

100K

1/20W

5% MF

201

R1610

12

100K

5% 201

1/20W

MF

R1614

12

100K

1/20W

201

MF5%

R1615

12

SD_ON_MLB

1/20W

MF

2015%

100K

R1616

12

201

MF5%

1/20W

100K

R1617

12

MF

2015%

1/20W

100K

R1618

12

5% MF

201

1/20W

100K

R1619

12

MF

1/20W

2015%

100K

R1620

12

MF

201

1/20W

5%

100K

R1622

12

MF

100K

5% 201

1/20W

R1623

12

100K

1/20W

201

MF5%

R1624

12

201

100K

1/20W

MF5%

R1625

12

1/20W

100K

201

MF5%

R1626

12

201

MF

1/20W

100K

5%

R1627

12

100K

1/20W

2015% MF

R1628

12

MF

100K

2015%

1/20W

R1630

12

MF

2015%

1/20W

100K

NO STUFF

R1632

12

100K

1/20W

201

MF5%

R1633

12

1/20W

5% 201

MF

100K

R1634

12

5% MF

1/20W

100K

201

R1640

12

MF

2015%

100K

1/20W

R1637

12

MF

2015%

100K

1/20W

R1638

12

100K

MF

2015%

1/20W

R1691

12

10K

MF

2015%

1/20W

R1694

12

100K

1/20W

5% 201

MF

R1693

12

PLACE_NEAR=U0500.AW15:2.54mm

49.9

201

1% 1/20W MF

R1655

1

2

100K

MF5%

1/20W

201

R1695

12

MF

2015%

1/20W

100K

R1660

12

100K

MF

2015%

1/20W

R1661

12

100K

1/20W

5% 201

MF

R1662

12

MF

2015%

1/20W

100K

R1663

12

MF

2015%

1/20W

47K

R1664

12

2015%

1/20W

47K

MF

R1665

12

1/20W

5% 201

MF

47K

R1666

12

MF

2015%

1/20W

47K

R1667

12

RAMCFG3:H,RAMCFG2:H,RAMCFG1:H,RAMCFG0:H

RAMCFG_SLOT

PCH GPIO/MISC/LPIO

SYNC_MASTER=J44

SYNC_DATE=08/12/2013

SPIROM_USE_MLB

XDP_SDCONN_STATE_CHANGE_L

PP3V3_S3RS0_CAMERA

TPAD_SPI_IF_EN

JTAG_TBT_TMS_PCH

CAMERA_PWR_EN_PCH

SD_PWR_EN

XDP_JTAG_ISP_TDI

PCH_HSIO_PWR_EN

XDP_JTAG_ISP_TCK

FW_PWR_EN SSD_DEVSLP

AP_S0IX_WAKE_SEL

PP3V3_S3

PP3V3_S0

PP3V3_S3

PP3V3_S0

PP3V3_S3

HDMITBTMUX_FLAG_L

TPAD_SPI_CS_L

PCH_GSPI0_MOSI

PCH_GSPI0_MISO

PCH_GSPI0_CLK

PCH_GSPI0_CS_L

PCH_UART1_CTS_L

PCH_I2C1_SDA

PCH_I2C0_SCL

PCH_I2C0_SDA

PCH_UART1_RTS_L

PCH_UART1_RXD PCH_UART1_TXD

TPAD_SPI_CS_L

TPAD_SPI_MOSI

AP_S0IX_WAKE_L HDMITBTMUX_FLAG_L JTAG_ISP_TDO AP_RESET_L

XDP_PCH_GPIO76 XDP_LPCPLUS_GPIO

XDP_PCH_GPIO17

TBT_PWR_EN

XDP_MLB_RAMCFG1

XDP_MLB_RAMCFG3

PP3V3_S0

HDMITBTMUX_SEL_TBT

XDP_JTAG_ISP_TDI

SD_RESET_L

XDP_MLB_RAMCFG1

XDP_MLB_RAMCFG0

XDP_MLB_RAMCFG2

PP1V05_S0

PM_THRMTRIP_L

LPC_SERIRQ

TBT_CIO_PLUG_EVENT_L

PCH_GSPI0_CS_L

PCH_GSPI0_MISO

TPAD_SPI_MISO

PCH_UART1_CTS_L

PCH_UART1_RTS_L

PCH_I2C0_SDA

PCH_HSIO_PWR_EN

FW_PWR_EN

XDP_PCH_GPIO76

MEM_VDD_SEL_1V5_L

XDP_MLB_RAMCFG0

XDP_LPCPLUS_GPIO

JTAG_TBT_TMS_PCH

TPAD_SPI_IF_EN XDP_MLB_RAMCFG3

CAMERA_PWR_EN_PCH

PCH_STRP_TOPBLK_SWP_L

LCD_PSR_EN

LCD_IRQ_L

ENET_MEDIA_SENSE

PCH_UART1_RXD

PCH_I2C1_SCL

PCH_I2C1_SDA

PCH_I2C0_SCL

PLT_RESET_L

TPAD_SPI_CLK

PCH_OPI_COMP

BT_PWRRST_L ENET_MEDIA_SENSE

LCD_IRQ_L

PCH_UART1_TXD

PCH_GSPI0_MOSI

PCH_GSPI0_CLK

XDP_PCH_GPIO17

TPAD_SPI_INT_L

SD_RESET_L SMC_WAKE_SCI_L

SSD_PWR_EN

TPAD_USB_IF_EN

TPAD_SPI_INT_L

FW_PME_L LPC_SERIRQ JTAG_ISP_TDO

AP_S0IX_WAKE_SEL

FW_PME_L

SSD_RESET_L

HDD_PWR_EN

PP3V3_S5

LCD_PSR_EN

PCH_I2C1_SCL

TPAD_SPI_CLK

AP_S0IX_WAKE_L

TPAD_SPI_MISO

PP3V3_S0

TPAD_SPI_MOSI

XDP_JTAG_ISP_TCK

PLT_RESET_L

BT_PWRRST_L

TBT_POC_RESET_L

TBT_PWR_EN

SD_PWR_EN

XDP_SDCONN_STATE_CHANGE_L

HDD_PWR_EN

PCH_TBT_PCIE_RESET_L

SSD_PWR_EN

TPAD_USB_IF_EN

SMC_WAKE_SCI_L

PP3V3_S0

SPIROM_USE_MLB

PCH_TCO_TIMER_DISABLE

XDP_MLB_RAMCFG2 SSD_DEVSLP

16 OF 120

<SCH_NUM>

15 OF 78

15

45 68 72

15 16 18

31 42

15

15 18

15 63

15 16

15 60

15 16

15 68

15 30

15 29

15 18 19 39 42 60 65 68

8

11

12 13 15 17 18 24 28 30 37

38 39 40 41 42 43 44 46 47 50

61 62 64 65 68 77

15 18 19 39 42 60 65 68

8

11

12 13 15 17 18 24 28 30 37

38 39 40 41

42 43 44 46 47 50 61 62 64 65

68

77

15 18 19 39 42 60 65 68

15 64

15

15 16

15 16 45 68

15 16

15 23

15 16 18

8

11

12 13 15 17 18 24 28 30 37

38 39 40 41 42 43 44 46 47 50

61 62 64 65 68 77

15 16 18

6 8 11

16 17 37 53 57 60 61

65 68

15

72

15 68

15 62 68

15

15 63

15 36

15 30 60 61

15

15 68

15 36 45 68

15 18

15 68

8

11

13 16 17 18 26 27 29 56 59

60 61 65 68 77

15 62

15

15 29

15

8

11

12 13 15 17 18 24 28 30

37 38 39 40 41 42 43 44 46 47

50 61 62 64 65 68 77

15

8

11

12 13 15 17 18 24 28 30

37 38 39 40 41 42 43 44 46 47

50 61 62 64 65 68 77

w w w . c h i n a f i x . c o m

IN

IN IN

IN

OUT

IN

OUT

IN

OUT OUT

IN

NC NC

IN IN

IN

TP

OUT

G

D

S G

D

SG

D

S G

D

S

OUT

IN

OUT

IN

OUT

IN

TP

OUT

IN

BI

OUT

TP

BI

TP

BI

TP

BI

OUT

BI

IN

OUT

BI

IN

BI

IN

OUT

IN

OUT

BI

TP

IN

OUT

GND

VCC

NCNC

YA

NC

IN

NC

IN

TP

IN

TP

IN IN

BI

IN

OUT

IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87

6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

NOTE: Should force PCH GPIO47 high to ensure TBT router powered to avoid leakage/clamping of signals.

These signals do not connect to XDP connector in this architecture, only accessible via Top-Side Probe. Nets are listed here to show XDP associations and to make clear what restrictions exist on PCH GPIOs when Top-Side Probe is used for PCH debug.

PCH/XDP Signals

USB Overcurrents are aliased, do not cause USB OC# events during PCH debug. SDCONN_STATE_CHANGE_L is aliased, do not plug/unplug SD Cards during PCH debug.

PCH XDP Signals

VCC_OBS_AB

SSD_PCIEx_SEL_L straps are connected via 1K to common net. LPCPLUS_GPIO is aliased, do not attempt use during PCH debug.

Unused & MLB_RAMCFGx GPIOs have TPs.

NOTE: Must not short XDP pins together!

Non-XDP Signals

NOTE: XDP_DBRESET_L pulled-up to 3.3V on PCH Support Page

TDI and TMS are terminated in CPU.

HOOK2

TDO TRSTn

Merged (CPU/PCH) Micro2-XDP

OBSFN_D0

SCL

OBSDATA_D2

OBSDATA_A1

Use with 921-0133 Adapter Flex to

NOTE: This is not the standard XDP pinout.

TCK0

TCK1

SDA

HOOK1

HOOK3

OBSDATA_B3

OBSDATA_B2

PWRGD/HOOK0

OBSDATA_B1

OBSDATA_B0

OBSFN_B0

OBSDATA_A2 OBSDATA_A3

OBSFN_B1

OBSDATA_A0

TDI TMS

ITPCLK/HOOK4

XDP_PRESENT#

DBR#/HOOK7

OBSDATA_D3

ITPCLK#/HOOK5

OBSFN_D1

OBSDATA_D1

OBSDATA_D0

OBSDATA_C2 OBSDATA_C3

OBSDATA_C1

OBSFN_C1

OBSDATA_C0

OBSFN_C0

518S0847

support chipset debug.

Extra BPM Testpoints

RESET#/HOOK6

VCC_OBS_CD

OBSFN_A1

OBSFN_A0

CPU JTAG Isolation

JTAG_ISP (non-TMS) nets are aliased, do not attempt bit-banged JTAG during PCH debug.

6

70

13

15 18

6

70

6

70

6

70

6

70

6

70

6

70

13

36 72

13 17 36 72

12 16 70

17 72

6

70

12

16 70

12 16 70

5% 201

1/20W

MF

XDP

1K

PLACE_NEAR=U0500.AG7:2.54mm

R1805

12

5% 201

1/20W

MF

XDP

51

PLACE_NEAR=U0500.E60:28mm

R1813

21

5%

0

402

MF-LF

XDP

1/16W

R1804

12

5%

0

0201

1/20W

MF

XDP

PLACE_NEAR=U5000.J3:2.54mm

R1802

12

5% 201

1/20W

MF

1K

XDP

PLACE_NEAR=U0500.C61:2.54mm

R1800

12

6

70

M-ST-SM1

CRITICAL

DF40RC-60DP-0.4V

XDP_CONN

J1800

1

10

1112 1314 1516 1718 19

2

20

2122 2324 2526 2728 29

3

30

3132 3334 3536 3738 39

4

40

4142 4344 4546 4748 49

5

50

5152 5354 5556 5758 59

6

60

61

62

6364

78 9

6

70

6

70

6

70

6

70

6

70

6

70

6

70

6

70

6

70

6

70

TP-P6

TP1806

1

TP-P6

TP1807

1

TP-P6

TP1805

1

TP-P6

TP1804

1

TP-P6

TP1803

1

TP-P6

TP1802

1

8

5%

150

402

MF-LF

1/16W

R1830

1

2

5% 201

1/20W

MF

51

XDP

PLACE_NEAR=U0500.F62:28mm

R1810

12

16 70

5%

XDP

MF-LF 402

1/16W

1K

R1831

1

2

5% 201

1/20W

MF

51

PLACE_NEAR=U0500.AE62:28mm

NO STUFF

R1896

21

5% 201

1/20W

MF

51

XDP

PLACE_NEAR=U0500.AD62:28mm

R1892

21

5% 201

1/20W

MF

51

XDP

PLACE_NEAR=U0500.AD61:28mm

R1891

21

5% 201

1/20W

MF

XDP

51

PLACE_NEAR=U0500.AE61:28mm

R1890

21

5% 201

1/20W

MF

1K

PLACE_NEAR=U0500.AE63:28mm

NO STUFF

R1899

21

5%

0

0201

1/20W

MF

XDP

PLACE_NEAR=J1800.58:28mm

R1835

12

16 70

PLACE_NEAR=J1800.57:28mm

XDP

SOT-563

DMN5L06VK-7

CRITICAL

Q1842

6

2

1

XDP

SOT-563

DMN5L06VK-7

CRITICAL

PLACE_NEAR=J1800.51:28mm

Q1840

3

5

4

PLACE_NEAR=J1800.55:28mm

CRITICAL

XDP

DMN5L06VK-7

SOT-563

Q1842

3

5

4

CRITICAL

XDP

DMN5L06VK-7

SOT-563

PLACE_NEAR=J1800.53:28mm

Q1840

6

2

1

6

12

16 70

6

70

6

70

6

16

70

XDP

CERM-X5R 0201

6.3V

0.1UF

10%

C1801

1

2

15

16 18

14

14 16 63

6

70

14 16

63

TP-P6

TP1870

1

14

16 33 14 16 33

15 18

14

TP-P6

TP1874

1

XDP

CERM-X5R

0201

6.3V

0.1UF

10%

C1800

1

2

TP-P6

TP1876

1

15

18

TP-P6

TP1877

1

15

18

TP-P6

TP1878

1

15

18

12

15

15 18 23

12

5% 201

1/20W

MF

1K

R1881

12

5% 201

1/20W

MF

1K

R1882

12

6

70

5% 201

1/20W

MF

1K

R1883

12

5% 201

1/20W

MF

1K

R1884

12

30

15

16 45 68

6

70

15

15 18

23

15 16 45 68

TP-P6

TP1887

1

XDP

CERM-X5R

0201

6.3V

0.1UF

10%

C1804

1

2

XDP

CERM-X5R 0201

6.3V

0.1UF

10%

C1806

1

2

6

70

6

12

16 70

5% 201

1/20W

MF

PLACE_NEAR=U0500.AU62:28mm

NO STUFF

51

R1897

21

74LVC1G07GF

SOT891

U1845

2

3

1

5

6

4

16V

0201

X5R-CERM

0.1UF

10%

C1845

1

2

6

70

5%

201

1/20W MF

330K

R1845

1

2

17

36 61

TP-P6

TP1873

1

15

16 18

TP-P6

TP1886

1

6

70

6

70

14

19 39 63 68 72

14 19 39 63 68 72

6

16

70

6

70

8

17

70

6

70

6

70

6

70

SYNC_MASTER=J44

CPU/PCH Merged XDP

SYNC_DATE=08/12/2013

CPU_PWR_DEBUG

CPU_CFG<4>

XDP_SYS_PWROK

PP3V3_S5

ALL_SYS_PWRGD

PP5V_S0

XDP_PCH_TMS

XDP_CPUPCH_TRST_L

CPU_CFG<1>

XDP_PCH_TDO

XDP_PCH_TDI

XDP_CPU_PRESENT_L

MAKE_BASE=TRUE

XDP_CPUPCH_TRST_L

XDP_CPU_TCK

XDP_BPM_L<6> XDP_BPM_L<7>

XDP_BPM_L<5>

XDP_BPM_L<4>

XDP_BPM_L<3>

XDP_BPM_L<2>

PP1V05_SUS

PCH_JTAGX

XDP_PCH_TDI

XDP_CPU_TDO

XDP_PCH_TDO

PP1V05_S0

XDP_CPU_PRDY_L

XDP_CPU_PREQ_L

CPU_CFG<0>

CPU_CFG<2>

XDP_BPM_L<1>

XDP_BPM_L<0>

CPU_CFG<5>

CPU_CFG<6> CPU_CFG<7>

SMBUS_PCH_CLK XDP_PCH_TCK

CPU_VCCST_PWRGD

XDP_CPU_PWRBTN_L

PP1V05_S0

CPU_CFG<3>

PM_PWRBTN_L

PCH_JTAGX

PM_PCH_SYS_PWROK

CPU_CFG<17> CPU_CFG<16>

CPU_CFG<8> CPU_CFG<9>

CPU_CFG<18>

CPU_CFG<12> CPU_CFG<13>

CPU_CFG<14> CPU_CFG<15>

XDP_CPURST_L

PLT_RESET_L

XDP_CPU_TDO

XDP_CPUPCH_TRST_L XDP_CPUPCH_TRST_L

XDP_CPU_TDI

XDP_CPU_TMS

CPU_CFG<10> CPU_CFG<11>

CPU_CFG<19>

XDP_PCH_TCK

XDP_TRST_L

XDP_DBRESET_L

XDP_JTAG_CPU_ISOL_L

XDP_CPU_VCCST_PWRGD

XDP_CPU_TCK

SSD_PCIE_SEL_L

XDP_USB_EXTA_OC_L XDP_USB_EXTB_OC_L

XDP_SDCONN_STATE_CHANGE_L

JTAG_ISP_TCK

XDP_LPCPLUS_GPIO

XDP_MLB_RAMCFG0 XDP_USB_EXTA_OC_L

MAKE_BASE=TRUE

XDP_USB_EXTB_OC_L

MAKE_BASE=TRUE

XDP_USB_EXTC_OC_L

MAKE_BASE=TRUE

XDP_SDCONN_STATE_CHANGE_L

XDP_USB_EXTD_OC_L

XDP_MLB_RAMCFG1

MAKE_BASE=TRUE

XDP_JTAG_ISP_TCK

XDP_SSD_PCIE1_SEL_L

XDP_PCH_GPIO76

MAKE_BASE=TRUE

XDP_JTAG_ISP_TDI

SMBUS_PCH_DATA

JTAG_ISP_TDI

MAKE_BASE=TRUE

XDP_LPCPLUS_GPIO

XDP_SSD_PCIE0_SEL_L

XDP_SSD_PCIE2_SEL_L

XDP_PCH_GPIO17

XDP_SSD_PCIE3_SEL_L

XDP_MLB_RAMCFG3

XDP_MLB_RAMCFG2

18 OF 120

<SCH_NUM>

16 OF 78

72

8

11

13 15 17 18 26 27 29 56

59 60 61 65 68 77

17 32 41 44 45 53 54 58 60 61 65 68

12 16 70

6

12

16 70

6

12

16 70

6

16

70

59 65

12 16 70

6

16

70

12 16 70

6 8 11

15 16 17 37 53 57 60

61 65 68

72

6 8 11

15 16 17 37 53 57 60

61 65 68

12 16 70

70

w w w . c h i n a f i x . c o m

OUT

IN

BIIN

OUT

IN

S

D

G

SDG

OUT

NC

NC NC

OUT

IN

NC

OUT

IN

NC

AY

NC NC

VCC

GND

NC

IN

OUT

IN

Y

A

B

08

Y

A

B

08

OUT

IN

OUT

IN

YA

B

NC

GND

VCC

32.768K

GND

THRM

VOUT

X2 X1

25M_A 25M_B 25M_C

VIOE_25M_A VIOE_25M_B VIOE_25M_C

VG3HOT

NC

VDD

PAD

NC NC

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87

6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

NOTE: 30 PPM or better required for RTC accuracy

PCH 24MHz Crystal

System RTC Power Source & 32kHz / 25MHz Clock Generator

Chipset uses 24MHz crystal, GreenCLK kept to save 1x 25MHz crystal & 1x 32kHz crystal

Must be powered if any VDDIO is powered.

This looks a little ugly to support

PCH ME Disable Strap

For SB RTC Power

to reduce VBAT draw.

+V3.3A should be first

create VDD_RTC_OUT.

internally ORed to

VBAT and +V3.3A are

Coin-Cell: VBAT (300-ohm & 10uF RC) No Coin-Cell: 3.42V G3Hot (no RC)

Coin-Cell & G3Hot: 3.42V G3Hot

GreenCLK 25MHz Power

TBT XTAL Power

Coin-Cell & No G3Hot: 3.3V S5 No Coin-Cell: 3.3V S5

No bypass necessary

PCH 24MHz Outputs

CAM XTAL Power

If high, ME is disabled. This allows for full re-flashing of SPI ROM.

Q1920 & 5V pull-up allows circuit to work regardless of HDA voltage.

PCH Reset Button

PCH uses HDA_SDO as a power-up strap. If low, ME functions normally.

IPD = 9-50k

VCCST (1.05V S0) PWRGD

SMC controls strap enable to allow in-field control of strap setting.

Memory VTT Enable Level-Shifter

CPU output is on VDDQ rail (1.2V), TPS51916 has 1.8V Vih(min).

33uW when driven-low

Vih(min) = 1.8V

TPS51916 I(leak) = +/- 1uA,

WF: Do we need this?

available ~3.3V power

PCH PWROK Generation

pin 5 must receive S5 power (Stuff R2042)

new and old parts. With GreenCLK Rev C

12

72

23 71

6.3V

20%

0201

1UF

X5R

C1902

1

2

X5R

1UF

20%

6.3V 0201

C1910

1

2

12PF

5% 25V

0201

NP0-C0G-CERM

C1905

12

25V

12PF

NP0-C0G-CERM

0201

5%

C1906

12

17

36 68 72

45 68 72

22

PLACE_NEAR=U0500.AN15:5.1mm

MF

1/20W

201

5%

R1927

12

22

PLACE_NEAR=U0500.AP15:5.1mm

MF

1/20W

201

5%

R1926

12

72

12 72

13 36 68 72 16 72

10% 16V

X5R-CERM

0201

0.1UF

C1924

1

2

MF

1/20W

0201

0

5%

R1905

12

1M

MF

1/20W 201

5%

NO STUFF

R1906

1

2

XDP

MF

1/20W

0201

0

5%

R1996

12

402

NO STUFF

SILK_PART=SYS RESET

MF-LF

1/16W

0

5%

R1997

1

2

10K

MF

1/20W 201

5%

R1995

1

2

100K

MF

1/20W 201

5%

R1920

1

2

1K

MF

1/20W 201

5%

R1921

1

2

12

72

36

SOT-563

DMN5L06VK-7

Q1920

3

5

4

DMN5L06VK-7

SOT-563

Q1920

6

2

1

X5R-CERM

0201

16V

10%

0.1UF

C1922

1

2

32

71

1M

MF

1/20W 201

5%

R1916

1

2

MF

1/20W

0

5%

0201

R1915

12

25V

+/-0.1PF

0201

6.8PF

C0G

C1915

12

25V

+/-0.1PF

C0G

0201

6.8PF

C1916

12

72

12 72

12 17

8

16 70

10K

MF

1/20W 201

5%

R1931

1

2

0.1UF

10%

X5R-CERM

16V

0201

C1930

1

2

13

18 36 61 63 68

330K

MF

1/20W 201

5%

R1970

1

2

74AUP1G07GF

SOT891

U1970

2

3

1

5

6

4

X5R-CERM

0201

16V

10%

0.1UF

C1970

1

2

6

17 55

24

25 36 37 72

16 17 36 61

SOT833

74LVC2G08GT/S505

U1950

1

2

4

8

7

0.1UF

16V 0201

10% X5R-CERM

BYPASS=U1950:5MM

C1950

1

2

CKPLUS_WAIVE=UNCONNECTED_PINS

SOT833

CKPLUS_WAIVE=UNCONNECTED_PINS

74LVC2G08GT/S505

U1950

5

6

4

8

3

MF

1/20W

0201

0

5%

R1963

2

1

NO STUFF

MF

1/20W 0201

0

5%

R1960

2

1

1K

MF

201

5%

1/20W

R1962

12

13

16 36 72

13 17 72

NO STUFF

MF

1/20W

0201

0

5%

R1951

12

10K

MF

1/20W

201

5%

R1950

1

2

10K

MF

1/20W

201

5%

R1955

1

2

8

53

8

17

53

8

17

53

100K

NO STUFF

MF

1/20W

201

5%

R1961

1

2

CRITICAL

SOT891

74AUP1G09

U1930

2

1

3

5

6

4

CKPLUS_WAIVE=PwrTerm2Gnd

TQFN

CRITICAL

SLG3NB148CV

U1900

9 8 15

12

71016217

5

13

11

6

14

1

4

3

24.000MHZ-20PPM-6PF

3.20X2.50MM-SM1

CRITICAL

Y1915

2 4

13

SM-3.2X2.5MM

25.000MHZ-12PF-20PPM

CRITICAL

OMIT

Y1905

24

13

SYNC_MASTER=J44

SYNC_DATE=08/12/2013

Chipset Support

1

Y1905

197S0480

XTAL,25MHZ,20PPM,12PF,3.2X2.5X.6MM,85C

PP1V2_CAM_XTALPCIEVDD

PP3V3_S5RS3RS0_SYSCLKGEN

MAKE_BASE=TRUE

PM_PCH_PWROK

SYSCLK_CLK25M_TBT

SYSCLK_CLK25M_CAMERA

SYSCLK_CLK25M_X2_R

PPVRTC_G3H

MAKE_BASE=TRUE

LPC_CLK24M_SMC LPC_CLK24M_SMC

NC_RTC_CLK32K_RTCX2

MAKE_BASE=TRUE

NO_TEST=TRUE

PP3V3_S0

CPUVR_PGOOD_R

PM_PCH_PWROK

PM_S0_PGOOD

PM_PCH_SYS_PWROK

MEMVTT_PWR_EN

PP3V3_S0

MAKE_BASE=TRUE

MEMVTT_PWR_EN

PP1V35_S3

CPU_MEMVTT_PWR_EN_LSVDDQ

SPI_DESCRIPTOR_OVERRIDE_LS5V

PP5V_S0

SYS_PWROK_R

LPC_CLK24M_LPCPLUS_R

LPC_CLK24M_SMC_R

PCH_CLK24M_XTALOUT

LPC_CLK24M_LPCPLUS

HDA_SDOUT_R

SPI_DESCRIPTOR_OVERRIDE

SPI_DESCRIPTOR_OVERRIDE_L

PP1V5_S0SW_AUDIO_HDA

PP3V3_S0

PM_SYSRST_L

XDP_DBRESET_L

PP3V42_G3H

CPU_VR_READY

CPU_VR_EN

CPU_VR_READY

MAKE_BASE=TRUE

ALL_SYS_PWRGD

SMC_DELAYED_PWRGD

PP1V05_S0

CPU_VCCST_PWRGD

PP3V3_S5

ALL_SYS_PWRGD

PCH_CLK24M_XTALOUT_R

PP3V42_G3H

PP3V3_TBTLC

PCH_CLK32K_RTCX1

NC_RTC_CLK32K_RTCX2

PP3V3_S5

PM_SLP_S3_L

SYSCLK_CLK25M_X2

SYSCLK_CLK25M_X1

PCH_CLK24M_XTALIN

<SCH_NUM>

19 OF 120

17 OF 78

31

18

71

8

12

13 65

17 36 68 72

12 17

8

11

12 13 15 17 18 24 28 30

37 38 39 40 41 42 43 44 46 47

50 61 62 64 65 68 77

72

8

11

12 13 15 17 18 24 28 30 37

38 39 40 41 42 43 44 46 47 50

61 62 64 65 68 77

17 55

19 20 21 22 41 55 65 73

16 32 41 44 45 53 54 58 60 61 65 68

72

8

11

60

8

11

12 13 15 17 18 24 28 30

37 38 39 40 41 42 43 44 46 47

50 61 62 64 65 68 77

17 30 33 34 36 37 38 39 45 51 52 61 65 68

6 8 11

15 16 37 53 57 60 61 65

68

8

11

13 15 16 17 18 26 27 29

56 59 60 61 65 68 77

16 17 36 61

72

17 30 33 34 36 37 38 39 45 51 52 61 65 68

18 23 24 65

8

11

13 15

16 17 18 26 27 29 56 59 60

61 65 68 77

71

w w w . c h i n a f i x . c o m

SDG SDG

OUT

IN IN IN IN

SDG SDG

IN

OUT

IN

OUT

IN

OUT

YA

B

NC

GND

VCC

NC

G

D

S

G

D

S

IN

OUT

IN

NC

08

OUT

IN

OUT

VCC

1A 1Y

2A 2Y

GND

IN

OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87

6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Renaming the pins N61 and P61 to remove automatic diffpari property

Pin N61 needs a TP for Power to perform iFDIM test

S0 pull-up on PCH page

NOTE: Solution shown is for LPT-LP. Other PCH’s may require isolation on TCK and TDI as well for PCH glitch-prevention.

NOTE: This reference schematic assumes PCH JTAG GPIOs are only used for Thunderbolt. If other ASIC JTAG signals are wired into these GPIOs different isolation techniques will likely be necessary. Multi-router designs also require different circuitry.

RAM Configuration Straps

Pull-downs for chip-down RAM systems

To RR

To SMC

To PCH

Scrub for Layout Optimization

Unbuffered

R2041/2 should be stuffed for

Buffered

REDWOOD RIDGE PLUG_EVENT IS ACTIVE-LOW, ALWAYS DRIVEN (PULL-UP)

THUNDERBOLT PULL-UP

Power State Debug LEDs

(For development only)

MAKE_BASE

Platform Reset Connections

GreekCLK A or B depending on S2 rail

To PCH

From PCH

S0 pull-up on PCH page

SDCONN_STATE_CHANGE Isolation

TBTLC can be on when S0 is off, and vice-versa

Redwood Ridge JTAG Isolation

Isolation ensures no leakage to RR or PCH

From RR

GreenCLK 25MHz Power

R2042 should be stuffed for GreenCLK C

RAMCFG3:L

10K

MF

1/20W

201

5%

R2050

1

2

10K

RAMCFG2:L

MF

1/20W

201

5%

R2051

1

2

RAMCFG1:L

10K

MF

1/20W

201

5%

R2052

1

2

RAMCFG0:L

10K

MF

1/20W

201

5%

R2053

1

2

SOT-563

DMN5L06VK-7

DBGLED

Q2090

6

2

1

SOT-563

DBGLED

DMN5L06VK-7

Q2090

3

5

4

PLACE_SIDE=BOTTOM

DBGLED

SILK_PART=S5_ON

LTQH9G-SM

GREEN-56MCD-2MA-2.65V

D2090

A

K

PLACE_SIDE=BOTTOM

DBGLED

SILK_PART=STBY_ON

LTQH9G-SM

GREEN-56MCD-2MA-2.65V

D2091

A

K

20K

DBGLED

MF

5%

201

1/20W

R2090

1

2

DBGLED

PLACE_SIDE=BOTTOM

1/16W MF-LF

402

0

5%

R2094

12

20K

MF

1/20W

201

5%

DBGLED

R2091

1

2

DBGLED

PLACE_SIDE=BOTTOM SILK_PART=S3_ON

LTQH9G-SM

GREEN-56MCD-2MA-2.65V

D2092

A

K

20K

DBGLED

MF

1/20W

201

5%

R2092

1

2

DBGLED

SILK_PART=S0I3_ON

PLACE_SIDE=BOTTOM

LTQH9G-SM

GREEN-56MCD-2MA-2.65V

D2093

A

K

20K

DBGLED

MF

1/20W

201

5%

R2093

1

2

15

16

15 16

26 27 60 61

13 18 29 36 61 63

13 17 36 61 63 68

20K

DBGLED

MF

1/20W

201

5%

R2095

1

2

SILK_PART=S0_ON

DBGLED

PLACE_SIDE=BOTTOM

LTQH9G-SM

GREEN-56MCD-2MA-2.65V

D2095

A

K

13

36

DMN5L06VK-7

SOT-563

DBGLED

Q2091

6

2

1

DMN5L06VK-7

SOT-563

DBGLED

Q2091

3

5

4

10%

0.1UF

16V 0201

X5R-CERM

C2071

1

2

CRITICAL MC74VHC1G08

SC70-HF

U2071

3

2

1

4

5

100K

MF

1/20W

201

5%

R2070

1

2

MF

1/20W

0201

0

5%

R2072

12

13

15 16

MF

1/20W

0201

0

5%

R2071

12

33

MF

1/20W

201

5%

R2081

12

36

19

45

68

15 18 23 72

100K

MF

1/20W

201

5%

R2015

1

2

15

18 23 72

MF

1/20W

0201

0

5%

R2089

12

31

15

18 23

15 16

10%

0.1UF

6.3V 0201

CERM-X5R

BYPASS=U2030.5:5MM

C2031

1

2

SOT891

74AUP1G09

CRITICAL

U2031

2

1

3

5

6

4

SOT-563

DMN5L06VK-7

Q2030

3

5

4

DMN5L06VK-7

SOT-563

Q2030

6

2

1

470K

MF

1/20W

201

5%

R2031

1

2

470K

MF

1/20W 201

5%

R2032

1

2

63

15

18 23

MF

1/20W

0201

0

5%

R2030

12

13

18 29 36 61 63

15

SOT891

CRITICAL

NOSTUFF

74LVC1G08

U2030

2

1

3

5

6

4

10%

0.1UF

10V

0201

X5R-CERM

NOSTUFF

BYPASS=U2030:3mm

C2030

1

2

31

MF

1/20W

0201

0

5%

R2042

12

NO STUFF

MF

1/20W

0201

0

5%

R2040

12

I1608

NO STUFF

MF

1/20W

0201

0

5%

R2041

12

23

15

100K

MF

1/20W

201

5%

R2061

1

2

0.1UF

20%

10V

CERM 402

C2060

1

2

100K

MF

1/20W 201

5%

R2062

1

2

23

15

74LVC2G07

SOT891

U2060

1

6

3

4

25

16

18 23

16 18 23

SYNC_MASTER=J44

SYNC_DATE=08/12/2013

Project Chipset Support

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.25 MM

PP3V3_S5_DBGLED

DBGLED_S4DBGLED_S5

DBGLED_S4_D

PCH_TBT_PCIE_RESET_L

PLT_RST_BUF_L

JTAG_TBT_TMS

JTAG_TBT_TDO JTAG_TBT_TMS_PCH

PP3V3_TBTLC

JTAG_ISP_TDO

PP3V3_S4

DBGLED_S0

CAMERA_PWR_EN_PCH

PM_SLP_S4_L

SMC_PME_S4_DARK_L

PP3V3_S5

PP3V3_S3

PP3V3_S0

PLT_RESET_L

PCA9557D_RESET_L

DBGLED_S3

PM_SLP_S4_L PM_SLP_S3_L

LPCPLUS_RESET_L

DBGLED_S0_D

DBGLED_S0I3_D

DBGLED_S3_D

PP3V3_S5

S4_PWR_EN

PM_SLP_S0_L

DBGLED_S0I3

PP3V3_S0

TRUE

TBT_CIO_PLUG_EVENT_L

PP3V3_S0

TBT_CIO_PLUG_EVENT_L

PP3V3_S5

PP3V3_S5RS3RS0_SYSCLKGEN PP3V3_S5RS3RS0_SYSCLKGEN

MIN_NECK_WIDTH=0.2 MM MAKE_BASE=TRUE

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.5 MM

PCH_TBT_PCIE_RESET_L

MAKE_BASE=TRUE

CAM_PCIE_RESET_L

SMC_LRESET_L

SMC_PME_S4_DARK_L

XDP_SDCONN_STATE_CHANGE_L

SMC_PME_SDCONN

JTAG_ISP_TCK

SDCONN_STATE_CHANGE_RIO

XDP_MLB_RAMCFG1

XDP_MLB_RAMCFG0

XDP_MLB_RAMCFG3

XDP_MLB_RAMCFG2

JTAG_ISP_TDI

MAKE_BASE=TRUE

JTAG_ISP_TDI

JTAG_ISP_TCK

MAKE_BASE=TRUE

TP_CPU_RSVDN61

TP_CPU_RSVDP61

TP_CPU_RSVDN61

MAKE_BASE=TRUE

TP_CPU_RSVDP61

CAMERA_PWR_EN

<SCH_NUM>

20 OF 120

18 OF 78

17

23 24 65

29 34 37 38 42 60 63 64 65 68

18 23 36 37

8

11

13 15 16 17 18 26 27 29

56 59 60 61 65 68 77

15 18 19 39 42 60 65 68

8

11

12 13 15 17 18 24 28 30

37 38 39 40 41 42 43 44 46 47

50 61 62 64 65 68 77

8

11

13

15 16 17

18 26 27

29 56 59

60 61 65

68 77

8

11

12 13 15 17 18 24 28 30

37 38 39 40 41 42 43 44 46 47

50 61 62 64 65 68 77

8

11

12 13

15 17 18 24

28 30 37 38

39 40 41 42

43 44 46 47

50 61 62 64

65 68 77

8

11

13 15 16 17 18 26 27 29

56 59 60 61 65 68 77

17 18

18 23 36 37

8

18

8

18

8

18

8

18

w w w . c h i n a f i x . c o m

OUT

V-

V+

V-

V+

IN

G

D

SG

D

SG

D

S G

D

S

G

D

SG

D

SG

D

S G

D

S

RESET*

A0 A1 A2

SCL SDA

P0 P1 P2

P5 P6 P7

P3 P4

THRM

VCC

GND

PAD

NC

IN

BI

VDD

VOUTD

VOUTC

VOUTB

VOUTA

SCL

SDA

A0

A1

GND

IN

BI

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

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NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

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C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

FETs for CPU isolation during DAC margining

VREFCA. Split into two

DAC margining VREFCA ensure

NOTE: MEMVREG and SPARE share a

soft-resets and sleep/wake cycles.

NOTE: Margining will be disabled across all

watchdog will disable margining.

RST* on ’platform reset’ so that system

- =I2C_VREFDACS_SDA

3.53mV / step @ output

CPU-Based Margining

Addr=0x98(WR)/0x99(RD)

NOTE: CPU DAC output step sizes: DDR3 (1.5V) 7.70mV per step

- DDRVREF_DAC - Stuffs DAC margining circuit.

BOM options provided by this page:

May not be necessary due to C22x0

EN RC’s to avoid drain glitches

to remove short due to CPU.

4.28mV / step @ output

Addr=0x30(WR)/0x31(RD)

+25uA - -25uA (- = sourced)

1.343V (DAC: 0x68)

0.972V - 1.714V (+/- 371mV)

DDR3L (1.35V)

0.000V - 2.694V (0x00 - 0xD1)

DDR3L assumes TPS51916 supply with 19.6k/57.6k divider

Always used, regardless

NOTE: LPDDR3 assumes TPS51916 supply with 28.7k/57.6k divider

+21uA - -21uA (- = sourced)

1.200V (DAC: 0x5D)

5

D

MEM VREG

0.000V - 2.397V (0x00 - 0xBA)

LPDDR3 (1.2V)

0.800V - 1.600V (+/- 400mV)

LPDDR3 (1.2V)

DAC Channel:

PCA9557D Pin:

MEM A VREF DQ

1

A

MEM B VREF DQ

B

2

MEM A VREF CA

C

3

MEM B VREF CA

DDR3L (1.35V)

C

4

6.36mV / step @ output 6.36mV / step @ output

+82uA - -82uA (- = sourced)

0.337V - 1.013V (+/- 337.5mV)

DAC output, cannot enable

+73uA - -73uA (- = sourced)

0.000V - 1.354V (0x00 - 0x69)

0.675V (DAC: 0x34)

0.000V - 1.199V (0x00 - 0x5D)

- =I2C_PCA9557D_SDA

- =I2C_PCA9557D_SCL

Power aliases required by this page:

Pins B1 & B4:

both at the same time!

(OD)

VREFMRGN_CPU_EN is low

- =I2C_VREFDACS_SCL

DAC range:

Nominal value

VRef current:

DAC step size:

- =PP3V3_S3_VREFMRGN

- =PPDDR_S3_MEMVREF

VRef Dividers

of margining option.

DAC sets voltage level, PCA9557 & FETs enable outputs and disables margining after platform reset.

margining support. When

signals for independent DAC

NOTE: CPU has single output for

LPDDR3 (1.2V) ?.??mV per step

DDR3L (1.35V) 6.99mV per step

Signal aliases required by this page:

Page Notes

R22x6 pin 2:

(All 4 R’s)

0.600V (DAC: 0x2E.5)

0.300V - 0.900V (+/- 300mV)

Margined target:

DAC-Based Margining

55

10%

6.3V

DDRVREF_DAC

CERM-X5R

0201

0.1UF

C2202

1

2

PLACE_NEAR=R7415.2:1mm

1%

DDRVREF_DAC

1/20W

MF

33.2K

201

R2214

12

201

DDRVREF_DAC

MF

1/20W

100K

5%

R2213

1

2

201

DDRVREF_DAC

MF

1/20W

100K

5%

R2212

1

2

DDRVREF_DAC

CRITICAL

UCSP

MAX4253

CKPLUS_WAIVE=unconnected_pinsCKPLUS_WAIVE=unconnected_pins

U2204

A3

A2

A1

A4

B1

B4

CRITICAL

MAX4253

DDRVREF_DAC

UCSP

U2204

C3

C2

C1

C4

B1

B4

402

OMIT

NONE

SHORT

R2218

12

18

7

73

7

73

201

DDRVREF_DAC

100K

MF

5%

1/20W

R2202

1

2

7

73

201

DDRVREF_DAC

MF

1/20W

5%

100K

R2201

1

2

201

100K

5%

DDRVREF_DAC

1/20W

MF

R2225

12

10%

6.3V

DDRVREF_DAC

CERM-X5R

0201

0.1UF

C2225

1

2

10%

6.3V

DDRVREF_DAC

CERM-X5R

0201

0.1UF

C2245

1

2

201

1/20W

100K

5%

DDRVREF_DAC

MF

R2245

12

201

DDRVREF_DAC

100K

5%

1/20W

MF

R2265

12

10%

6.3V

DDRVREF_DAC

CERM-X5R

0201

0.1UF

C2265

1

2

10%

6.3V

CERM-X5R

0201

DDRVREF_DAC

0.1UF

C2285

1

2

201

DDRVREF_DAC

MF

1/20W

5%

100K

R2215

1

2

201

DDRVREF_DAC

100K

5%

1/20W

MF

R2285

12

201

DDRVREF_DAC

MF

1/20W

5%

100K

R2207

1

2

201

1%

1/20W

MF

DDRVREF_DAC

332

PLACE_NEAR=Q2225.1:2.54mm

R2226

12

201

1%

1/20W

MF

DDRVREF_DAC

332

PLACE_NEAR=Q2265.4:2.54mm

R2246

12

201

1%

1/20W

MF

DDRVREF_DAC

332

PLACE_NEAR=Q2265.1:2.54mm

R2266

12

201

1%

1/20W

MF

DDRVREF_DAC

332

PLACE_NEAR=Q2225.4:2.54mm

R2286

12

201

1M

DDRVREF_DAC

5% 1/20W MF

R2217

1

2

201

MF

1/20W

5%

100K

R2200

1

2

201

MF

1% 1/20W

PLACE_NEAR=Q2220.6:4mm

1K

R2221

1

2

201

24.9

1%

1/20W

MF

R2280

12

PLACE_NEAR=Q2220.3:2mm

6.3V X5R-CERM 0201

0.022UF

10%

C2280

1

2

201

MF

1/20W

2

5%

R2283

12

201

PLACE_NEAR=Q2220.3:4mm

1% 1/20W MF

1K

R2281

1

2

201

PLACE_NEAR=R2281.2:1mm

1K

1%

1/20W

MF

R2282

1

2

201

PLACE_NEAR=R2261.2:1mm

1%

1/20W

MF

1K

R2262

1

2

201

24.9

1%

1/20W

MF

R2260

12

201

2

1/20W

MF

5%

R2263

12

PLACE_NEAR=Q2260.6:2mm

10%

0.022UF

6.3V

0201

X5R-CERM

C2260

1

2

201

1% 1/20W MF

PLACE_NEAR=Q2260.6:4mm

1K

R2261

1

2

201

PLACE_NEAR=R2241.2:1mm

1%

1/20W

MF

1K

R2242

1

2

201

1%

1/20W

MF

24.9

R2240

12

201

1/20W

MF

2

5%

R2243

12

10%

0.022UF

6.3V

PLACE_NEAR=Q2260.3:2mm

0201

X5R-CERM

C2240

1

2

201

1% 1/20W MF

PLACE_NEAR=Q2260.3:4mm

1K

R2241

1

2

201

MF

1/20W

2

5%

R2223

12

201

PLACE_NEAR=R2221.2:1mm

1%

MF

1/20W

1K

R2222

1

2

201

24.9

1%

1/20W

MF

R2220

12

10%

0.022UF

6.3V

0201

X5R-CERM

PLACE_NEAR=Q2220.6:2mm

C2220

1

2

PLACE_NEAR=Q2220.6:2.54mm

CRITICAL

DMN5L06VK-7

DDRVREF_DAC

SOT-563

Q2225

6

2

1

PLACE_NEAR=Q2260.6:2.54mm

DMN5L06VK-7

SOT-563

CRITICAL DDRVREF_DAC

Q2265

6

2

1

DMN5L06VK-7

DDRVREF_DAC

CRITICAL

SOT-563

Q2225

3

5

4

DDRVREF_DAC

CRITICAL

DMN5L06VK-7

SOT-563

Q2265

3

5

4

CRITICAL

DMN5L06VK-7

SOT-563

Q2220

6

2

1

DMN5L06VK-7

CRITICAL

SOT-563

Q2260

6

2

1

CRITICAL

DMN5L06VK-7

SOT-563

Q2220

3

5

4

CRITICAL

DMN5L06VK-7

SOT-563

Q2260

3

5

4

DDRVREF_DAC

PCA9557

QFN

CRITICAL

U2201

3

4

5

8

6

7

9

10

11

12

13

14

15

1

2

17

16

14

16 19 39 63 68 72

14 16 19 39 63 68 72

MSOP

DAC5574

CRITICAL DDRVREF_DAC

U2200

9

10

3

6

7

8

1

2

4

5

14

16 19 39 63

68 72

14 16 19 39 63 68 72

10%

6.3V

DDRVREF_DAC

CERM-X5R 0201

0.1UF

C2201

1

2

6.3V

402-LF

DDRVREF_DAC

2.2UF

CERM

20%

C2200

1

2

10%

6.3V

DDRVREF_DAC

CERM-X5R

0201

0.1UF

C2205

1

2

SYNC_MASTER=J44

DDR3 VREF MARGINING

SYNC_DATE=08/12/2013

VREFMRGN_MEMVREG_BUF

MEM_VREFCA_B_RC

CPU_DIMM_VREFCA_B_ISOL

VREFMRGN_DQ_A_RDIV

VREFMRGN_CA_A_RDIV

VREFMRGN_CA_A_EN

PP0V675_S3_MEM_VREFDQ_A

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm

PP0V675_S3_MEM_VREFDQ_B

VREFMRGN_DQ_A

VREFMRGN_CA_AB

PP3V3_S3

VREFMRGN_SPARE_EN

VREFMRGN_MEMVREG_EN

VREFMRGN_SPARE_BUF

MEM_VREFDQ_B_RC

SMBUS_PCH_CLK SMBUS_PCH_DATA

SMBUS_PCH_CLK

SMBUS_PCH_DATA

DDRREG_FB

VREFMRGN_DQ_B

VREFMRGN_MEMVREG

PCA9557D_RESET_L

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.3 mm

PP0V675_S3_MEM_VREFCA_A

VREFMRGN_CA_B_EN_RC

CPU_DIMMB_VREFDQ

CPU_DIMM_VREFCA

VREFMRGN_CA_A_EN_RC

VREFMRGN_DQ_B_EN

VREFMRGN_DQ_B_EN_RC

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.3 mm

PP3V3_S3_VREFMRGN_DAC

VOLTAGE=3.3V

MEM_VREFCA_A_RC

VREFMRGN_CA_B_RDIV

VREFMRGN_DQ_B_RDIV

VREFMRGN_CA_B_EN

VREFMRGN_DQ_A_EN

PP1V35_S3

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.3 mm

PP0V675_S3_MEM_VREFCA_B

VREFMRGN_CPU_EN

CPU_DIMMA_VREFDQ

CPU_DIMMA_VREFDQ_A_ISOL

VREFMRGN_DQ_A_EN_RC

MEM_VREFDQ_A_RC

CPU_DIMMB_VREFDQ_B_ISOL

CPU_DIMM_VREFCA_A_ISOL

19 OF 78

<SCH_NUM>

22 OF 120

73

20 65

73

21 65 73

15 18 19 39 42 60 65 68

20 65 73

17 20 21 22 41 55 65 73

21 65 73

73

w w w . c h i n a f i x . c o m

UDQS

UDQS*

LDQS*

LDQS

DQ15

DQ14

DQ13

DQ10

DQ12

DQ11

DQ9

DQ8

DQ7

DQ6

DQ5

DQ4

DQ3

DQ2

DQ1

DQ0

UDM

LDM

A14

VDD

A2 A3

A1

A0

NC

A6

ODT

RESET*

VSSQ

VSS

CAS*

RAS*

BA2

BA0 BA1

ZQ

CS*

CKE

A13

A11

A10/AP

A8

A4 A5

A9

CK

VREFCA

VREFDQ

CK*

WE*

A12/BC*

A7

VDDQ

NC NC NC NC NC

NC

UDQS

UDQS*

LDQS*

LDQS

DQ15

DQ14

DQ13

DQ10

DQ12

DQ11

DQ9

DQ8

DQ7

DQ6

DQ5

DQ4

DQ3

DQ2

DQ1

DQ0

UDM

LDM

A14

VDD

A2 A3

A1

A0

NC

A6

ODT

RESET*

VSSQ

VSS

CAS*

RAS*

BA2

BA0 BA1

ZQ

CS*

CKE

A13

A11

A10/AP

A8

A4 A5

A9

CK

VREFCA

VREFDQ

CK*

WE*

A12/BC*

A7

VDDQ

UDQS

UDQS*

LDQS*

LDQS

DQ15

DQ14

DQ13

DQ10

DQ12

DQ11

DQ9

DQ8

DQ7

DQ6

DQ5

DQ4

DQ3

DQ2

DQ1

DQ0

UDM

LDM

A14

VDD

A2 A3

A1

A0

NC

A6

ODT

RESET*

VSSQ

VSS

CAS*

RAS*

BA2

BA0 BA1

ZQ

CS*

CKE

A13

A11

A10/AP

A8

A4 A5

A9

CK

VREFCA

VREFDQ

CK*

WE*

A12/BC*

A7

VDDQ

NC

NC NC

NC

UDQS

UDQS*

LDQS*

LDQS

DQ15

DQ14

DQ13

DQ10

DQ12

DQ11

DQ9

DQ8

DQ7

DQ6

DQ5

DQ4

DQ3

DQ2

DQ1

DQ0

UDM

LDM

A14

VDD

A2 A3

A1

A0

NC

A6

ODT

RESET*

VSSQ

VSS

CAS*

RAS*

BA2

BA0 BA1

ZQ

CS*

CKE

A13

A11

A10/AP

A8

A4 A5

A9

CK

VREFCA

VREFDQ

CK*

WE*

A12/BC*

A7

VDDQ

NC

NC NC

NC

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87

6 5 4 3

C

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A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

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C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

SDRAM BYPASSING (NOTE: 4X 2.2UF AND 6X 0.1UF PER CHIP)

OMIT_TABLE

FBGA

MT41K256M16HA-125:E

4GB-DDR3L-1600-256MX16

U2300

N3 P7

L7 R7 N7 T3 T7

P3 N2 P8 P2 R8 R2 T8 R3

M2 N8 M3

K3

J7 K7

K9 L2

E3 F7

C8 C2 A7 A2 B8 A3

F2 F8 H3 H8 G2 H7 D7 C3

E7

F3 G3

J1 J9 L1 L9 M7

K1

J3

T2

D3

C7 B7

B2D9G7K2K8N1N9R1R9

A1A8C1C9D2E9F1H2H9

M8

H1

A9

B3

T1

T9

E1G8J2J8M1M9P1

P9

B1B9D1D8E2E8F9G1G9

L3

L8

1/20W

1% MF

240

201

R2300

12

0.047UF

6.3V X5R 201

10%

C2309

1

2

0.047UF

6.3V X5R 201

10%

C2308

1

2

4V

20%

0.47UF

CERM-X5R-1

201

C2307

1

2

0.047UF

6.3V X5R 201

10%

C2349

1

2

0.047UF

6.3V X5R 201

10%

C2348

1

2

CERM-X5R-1

0.47UF

20%

4V

201

C2347

1

2

MT41K256M16HA-125:E

FBGA

OMIT_TABLE

4GB-DDR3L-1600-256MX16

U2340

N3 P7

L7 R7 N7 T3 T7

P3 N2 P8 P2 R8 R2 T8 R3

M2 N8 M3

K3

J7 K7

K9 L2

E3 F7

C8 C2 A7 A2 B8 A3

F2 F8 H3 H8 G2 H7 D7 C3

E7

F3 G3

J1 J9 L1 L9 M7

K1

J3

T2

D3

C7 B7

B2D9G7K2K8N1N9R1R9

A1A8C1C9D2E9F1H2H9

M8

H1

A9

B3

T1

T9

E1G8J2J8M1M9P1

P9

B1B9D1D8E2E8F9G1G9

L3

L8

OMIT_TABLE

FBGA

MT41K256M16HA-125:E

4GB-DDR3L-1600-256MX16

U2360

N3 P7

L7 R7 N7 T3 T7

P3 N2 P8 P2 R8 R2 T8 R3

M2 N8 M3

K3

J7 K7

K9 L2

E3 F7

C8 C2 A7 A2 B8 A3

F2 F8 H3 H8 G2 H7 D7 C3

E7

F3 G3

J1 J9 L1 L9 M7

K1

J3

T2

D3

C7 B7

B2D9G7K2K8N1N9R1R9

A1A8C1C9D2E9F1H2H9

M8

H1

A9

B3

T1

T9

E1G8J2J8M1M9P1

P9

B1B9D1D8E2E8F9G1G9

L3

L8

4V

20%

CERM-X5R-1

0.47UF

201

C2367

1

2

MT41K256M16HA-125:E

4GB-DDR3L-1600-256MX16

FBGA

OMIT_TABLE

U2320

N3 P7

L7 R7 N7 T3 T7

P3 N2 P8 P2 R8 R2 T8 R3

M2 N8 M3

K3

J7 K7

K9 L2

E3 F7

C8 C2 A7 A2 B8 A3

F2 F8 H3 H8 G2 H7 D7 C3

E7

F3 G3

J1 J9 L1 L9 M7

K1

J3

T2

D3

C7 B7

B2D9G7K2K8N1N9R1R9

A1A8C1C9D2E9F1H2H9

M8

H1

A9

B3

T1

T9

E1G8J2J8M1M9P1

P9

B1B9D1D8E2E8F9G1G9

L3

L8

0.047UF

6.3V X5R 201

10%

C2368

1

2

0.047UF

6.3V X5R 201

10%

C2369

1

2

CERM-X5R-1

0.47UF

20%

4V

201

C2327

1

2

0.047UF

6.3V X5R 201

10%

C2328

1

2

0.047UF

6.3V X5R 201

10%

C2329

1

2

10V

20%

402

X5R-CERM

2.2UF

C2331

1

2

10V

20%

402

X5R-CERM

2.2UF

C2330

1

2

10V

20%

402

X5R-CERM

2.2UF

C2321

1

2

10V

20%

402

X5R-CERM

2.2UF

C2320

1

2

10V

20%

402

X5R-CERM

2.2UF

C2311

1

2

10V

20%

402

X5R-CERM

2.2UF

C2310

1

2

10V

20%

402

X5R-CERM

2.2UF

C2301

1

2

10V

20%

2.2UF

X5R-CERM

402

C2300

1

2

10V

20%

402

X5R-CERM

2.2UF

C2371

1

2

10V

20%

402

X5R-CERM

2.2UF

C2370

1

2

10V

20%

402

X5R-CERM

2.2UF

C2361

1

2

10V

20%

402

X5R-CERM

2.2UF

C2360

1

2

10V

20%

402

X5R-CERM

2.2UF

C2351

1

2

10V

20%

402

2.2UF

X5R-CERM

C2350

1

2

10V

20%

402

X5R-CERM

2.2UF

C2341

1

2

10V

20%

402

X5R-CERM

2.2UF

C2340

1

2

6.3V CERM-X5R 0201

0.1UF

10%

C2324

1

2

6.3V CERM-X5R 0201

0.1UF

10%

C2323

1

2

6.3V CERM-X5R 0201

0.1UF

10%

C2364

1

2

6.3V CERM-X5R 0201

0.1UF

10%

C2363

1

2

6.3V CERM-X5R 0201

0.1UF

10%

C2315

1

2

6.3V CERM-X5R 0201

0.1UF

10%

C2314

1

2

6.3V CERM-X5R 0201

0.1UF

10%

C2355

1

2

6.3V CERM-X5R 0201

0.1UF

10%

C2354

1

2

6.3V CERM-X5R 0201

0.1UF

10%

C2313

1

2

6.3V CERM-X5R 0201

0.1UF

10%

C2353

1

2

6.3V CERM-X5R 0201

0.1UF

10%

C2345

1

2

6.3V CERM-X5R 0201

0.1UF

10%

C2305

1

2

6.3V CERM-X5R 0201

0.1UF

10%

C2304

1

2

6.3V CERM-X5R 0201

0.1UF

10%

C2344

1

2

6.3V CERM-X5R 0201

0.1UF

10%

C2303

1

2

6.3V CERM-X5R 0201

0.1UF

10%

C2343

1

2

6.3V CERM-X5R 0201

0.1UF

10%

C2335

1

2

6.3V CERM-X5R 0201

0.1UF

10%

C2375

1

2

6.3V CERM-X5R 0201

0.1UF

10%

C2334

1

2

6.3V CERM-X5R 0201

0.1UF

10%

C2333

1

2

6.3V CERM-X5R 0201

0.1UF

10%

C2374

1

2

6.3V CERM-X5R 0201

0.1UF

10%

C2373

1

2

6.3V CERM-X5R 0201

0.1UF

10%

C2325

1

2

6.3V CERM-X5R 0201

0.1UF

10%

C2365

1

2

240

MF

1%

1/20W

201

R2320

12

240

MF

1%

1/20W

201

R2340

12

240

MF

1%

1/20W

201

R2360

12

SYNC_DATE=MASTERSYNC_MASTER=MASTER

DDR3 SDRAM Bank A (Rank 0)

PP1V35_S3

=MEM_A_DQS_N<3>

MEM_RESET_L

MEM_A_ZQ<3>

MEM_RESET_L

MEM_A_ZQ<2>

MEM_RESET_L

MEM_A_ZQ<1>MEM_A_ZQ<0>

MEM_RESET_L

PP1V35_S3

=MEM_A_DQ<13>

=MEM_A_DQS_N<1>

MEM_A_A<3>

MEM_A_A<5> MEM_A_A<6>

MEM_A_A<9>

MEM_A_A<12>

=MEM_A_DQ<0>

MEM_A_A<5>

MEM_A_A<4>

MEM_A_CLK_N<0>

MEM_A_CKE<0> MEM_A_CS_L<0>

MEM_A_BA<2>

=MEM_A_DQ<30>

PP0V675_S3_MEM_VREFCA_A PP0V675_S3_MEM_VREFDQ_A

PP1V35_S3

PP0V675_S3_MEM_VREFCA_A PP0V675_S3_MEM_VREFDQ_A

PP1V35_S3

=MEM_A_DQS_P<3>

=MEM_A_DQS_N<2>

=MEM_A_DQS_P<2>

=MEM_A_DQ<31>

=MEM_A_DQ<29>

=MEM_A_DQ<26>

MEM_A_DQ<32>

=MEM_A_DQ<27>

=MEM_A_DQ<25>

=MEM_A_DQ<24>

=MEM_A_DQ<23>

=MEM_A_DQ<22>

=MEM_A_DQ<21>

=MEM_A_DQ<20>

=MEM_A_DQ<19>

=MEM_A_DQ<18>

=MEM_A_DQ<17>

=MEM_A_DQ<16>

MEM_A_A<14>

MEM_A_A<2> MEM_A_A<3>

MEM_A_A<1>

MEM_A_A<0>

MEM_A_A<6>

MEM_A_ODT<0>

MEM_A_CAS_L

MEM_A_RAS_L

MEM_A_BA<2>

MEM_A_BA<0> MEM_A_BA<1>

MEM_A_CS_L<0>

MEM_A_CKE<0>

MEM_A_A<13>

MEM_A_A<11>

MEM_A_A<10>

MEM_A_A<8> MEM_A_A<9>

MEM_A_CLK_P<0> MEM_A_CLK_N<0>

MEM_A_WE_L

MEM_A_A<12>

MEM_A_A<7>

=MEM_A_DQS_P<7> =MEM_A_DQS_N<7>

MEM_A_DQS_N<6>

MEM_A_DQS_P<6>

=MEM_A_DQ<63>

=MEM_A_DQ<62>

=MEM_A_DQ<61>

=MEM_A_DQ<58>

=MEM_A_DQ<60>

=MEM_A_DQ<59>

=MEM_A_DQ<57>

=MEM_A_DQ<56>

=MEM_A_DQ<55>

=MEM_A_DQ<54>

=MEM_A_DQ<53>

=MEM_A_DQ<52>

=MEM_A_DQ<51>

=MEM_A_DQ<50>

=MEM_A_DQ<49>

=MEM_A_DQ<48>

MEM_A_A<14>

MEM_A_A<2> MEM_A_A<3>

MEM_A_A<1>

MEM_A_A<0>

MEM_A_A<6>

MEM_A_ODT<0>

MEM_A_CAS_L

MEM_A_RAS_L

MEM_A_BA<2>

MEM_A_BA<0> MEM_A_BA<1>

MEM_A_A<13>

MEM_A_A<11>

MEM_A_A<10>

MEM_A_A<8>

MEM_A_A<4> MEM_A_A<5>

MEM_A_A<9>

MEM_A_CLK_P<0>

MEM_A_WE_L

MEM_A_A<12>

MEM_A_A<7>MEM_A_A<7>

MEM_A_A<12>

MEM_A_WE_L

MEM_A_CLK_N<0>

MEM_A_CLK_P<0>

MEM_A_A<9>

MEM_A_A<5>

MEM_A_A<4>

MEM_A_A<8>

MEM_A_A<10> MEM_A_A<11>

MEM_A_A<13>

MEM_A_CKE<0> MEM_A_CS_L<0>

MEM_A_BA<1>

MEM_A_BA<0>

MEM_A_RAS_L MEM_A_CAS_L

MEM_A_ODT<0>

MEM_A_A<6>

MEM_A_A<0> MEM_A_A<1>

MEM_A_A<3>

MEM_A_A<2>

MEM_A_A<14>

=MEM_A_DQ<32> =MEM_A_DQ<33> =MEM_A_DQ<34> =MEM_A_DQ<35> =MEM_A_DQ<36> =MEM_A_DQ<37> =MEM_A_DQ<38> =MEM_A_DQ<39> =MEM_A_DQ<40> =MEM_A_DQ<41>

=MEM_A_DQ<43> =MEM_A_DQ<44>

=MEM_A_DQ<42>

=MEM_A_DQ<45> =MEM_A_DQ<46> =MEM_A_DQ<47>

=MEM_A_DQS_P<4> =MEM_A_DQS_N<4>

=MEM_A_DQS_N<5>

=MEM_A_DQS_P<5>

MEM_A_A<7>

MEM_A_WE_L

MEM_A_CLK_N<0>

MEM_A_CLK_P<0>

MEM_A_A<4>

MEM_A_A<8>

MEM_A_A<10> MEM_A_A<11>

MEM_A_A<13>

MEM_A_CKE<0> MEM_A_CS_L<0>

MEM_A_BA<1>

MEM_A_BA<0>

MEM_A_BA<2>

MEM_A_RAS_L MEM_A_CAS_L

MEM_A_ODT<0>

MEM_A_A<0> MEM_A_A<1> MEM_A_A<2>

MEM_A_A<14>

=MEM_A_DQ<1> =MEM_A_DQ<2> =MEM_A_DQ<3> =MEM_A_DQ<4> =MEM_A_DQ<5> =MEM_A_DQ<6> =MEM_A_DQ<7> =MEM_A_DQ<8> =MEM_A_DQ<9>

=MEM_A_DQ<11> =MEM_A_DQ<12>

=MEM_A_DQ<10>

=MEM_A_DQ<14> =MEM_A_DQ<15>

=MEM_A_DQS_P<0> =MEM_A_DQS_N<0>

=MEM_A_DQS_P<1>

PP0V675_S3_MEM_VREFDQ_A

PP0V675_S3_MEM_VREFCA_A

PP1V35_S3

PP0V675_S3_MEM_VREFDQ_A

PP0V675_S3_MEM_VREFCA_A

<SCH_NUM>

23 OF 120

20 OF 78

17

19 20 21 22 41 55 65 73

67

20 21 22 70

17 19 20 21 22 41 55 65 73

67

20 22 66 73

7 20 22 66 73

20 22 66 73

67

20 22 66 73

7 20 22 73

20 22 66 73

67

19 20 65 73

17 19 20 21 22 41 55 65 73

19 20 65 73

17 19 20 21 22 41 55 65 73

67

7 67 68 73

67

20 22 66 73

7 20 22 66 73

20 22 73

7 20 22 66 73

20 22 66 73

7 20 22 66 73

7 20 22 73

20 22 66 73

7 20 22 73

7 20 22 66 73

20 22 66 73

67

7 67 73

67

20 22 66 73

7 20 22 66 73

20 22 73

7 20 22 66 73

20 22 66 73

7 20 22 66 73

20 22 66 73

7 20 22 73

7 20 22 66 73

20 22 66 73

20 22 66 73 20 22 66 73

20 22 66 73

7 20 22 66 73

7 20 22 73

20 22 66 73

7 20 22 73

7 20 22 66 73

20 22 66 73

7 20 22 66 73

20 22 73

7 20 22 66 73

20 22 66 73

67

20 22 66 73

7 20 22 66 73

7 20 22 73

20 22 66 73

7 20 22 73

7 20 22 66 73

20 22 66 73

7 20 22 66 73

20 22 73

20 22 66 73

67

19 20 65 73

17 19 20 21 22 41 55 65 73

19 20 65 73

w w w . c h i n a f i x . c o m

NC

NC NC

UDQS

UDQS*

LDQS*

LDQS

DQ15

DQ14

DQ13

DQ10

DQ12

DQ11

DQ9

DQ8

DQ7

DQ6

DQ5

DQ4

DQ3

DQ2

DQ1

DQ0

UDM

LDM

A14

VDD

A2 A3

A1

A0

NC

A6

ODT

RESET*

VSSQ

VSS

CAS*

RAS*

BA2

BA0 BA1

ZQ

CS*

CKE

A13

A11

A10/AP

A8

A4 A5

A9

CK

VREFCA

VREFDQ

CK*

WE*

A12/BC*

A7

VDDQ

NC

NC NC

UDQS

UDQS*

LDQS*

LDQS

DQ15

DQ14

DQ13

DQ10

DQ12

DQ11

DQ9

DQ8

DQ7

DQ6

DQ5

DQ4

DQ3

DQ2

DQ1

DQ0

UDM

LDM

A14

VDD

A2 A3

A1

A0

NC

A6

ODT

RESET*

VSSQ

VSS

CAS*

RAS*

BA2

BA0 BA1

ZQ

CS*

CKE

A13

A11

A10/AP

A8

A4 A5

A9

CK

VREFCA

VREFDQ

CK*

WE*

A12/BC*

A7

VDDQ

UDQS

UDQS*

LDQS*

LDQS

DQ15

DQ14

DQ13

DQ10

DQ12

DQ11

DQ9

DQ8

DQ7

DQ6

DQ5

DQ4

DQ3

DQ2

DQ1

DQ0

UDM

LDM

A14

VDD

A2 A3

A1

A0

NC

A6

ODT

RESET*

VSSQ

VSS

CAS*

RAS*

BA2

BA0 BA1

ZQ

CS*

CKE

A13

A11

A10/AP

A8

A4 A5

A9

CK

VREFCA

VREFDQ

CK*

WE*

A12/BC*

A7

VDDQ

NC NC

NC

UDQS

UDQS*

LDQS*

LDQS

DQ15

DQ14

DQ13

DQ10

DQ12

DQ11

DQ9

DQ8

DQ7

DQ6

DQ5

DQ4

DQ3

DQ2

DQ1

DQ0

UDM

LDM

A14

VDD

A2 A3

A1

A0

NC

A6

ODT

RESET*

VSSQ

VSS

CAS*

RAS*

BA2

BA0 BA1

ZQ

CS*

CKE

A13

A11

A10/AP

A8

A4 A5

A9

CK

VREFCA

VREFDQ

CK*

WE*

A12/BC*

A7

VDDQ

NC

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87

6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

SDRAM BYPASSING (NOTE: 4X 2.2UF AND 6X 0.1UF PER CHIP)

1/20W

1% MF

240

201

R2540

12

0.047UF

6.3V X5R 201

10%

C2548

1

2

0.047UF

6.3V X5R 201

10%

C2549

1

2

0.47UF

CERM-X5R-1

4V

20%

201

C2567

1

2

4GB-DDR3L-1600-256MX16

MT41K256M16HA-125:E

FBGA

OMIT_TABLE

U2540

N3 P7

L7 R7 N7 T3 T7

P3 N2 P8 P2 R8 R2 T8 R3

M2 N8 M3

K3

J7 K7

K9 L2

E3 F7

C8 C2 A7 A2 B8 A3

F2 F8 H3 H8 G2 H7 D7 C3

E7

F3 G3

J1 J9 L1 L9 M7

K1

J3

T2

D3

C7 B7

B2D9G7K2K8N1N9R1R9

A1A8C1C9D2E9F1H2H9

M8

H1

A9

B3

T1

T9

E1G8J2J8M1M9P1

P9

B1B9D1D8E2E8F9G1G9

L3

L8

MF

1%

1/20W

240

201

R2520

12

CERM-X5R-1

4V

20%

0.47UF

201

C2507

1

2

0.047UF

6.3V X5R 201

10%

C2508

1

2

0.047UF

6.3V X5R 201

10%

C2509

1

2

0.47UF

CERM-X5R-1

4V

20%

201

C2527

1

2

OMIT_TABLE

FBGA

MT41K256M16HA-125:E

4GB-DDR3L-1600-256MX16

U2560

N3 P7

L7 R7 N7 T3 T7

P3 N2 P8 P2 R8 R2 T8 R3

M2 N8 M3

K3

J7 K7

K9 L2

E3 F7

C8 C2 A7 A2 B8 A3

F2 F8 H3 H8 G2 H7 D7 C3

E7

F3 G3

J1 J9 L1 L9 M7

K1

J3

T2

D3

C7 B7

B2D9G7K2K8N1N9R1R9

A1A8C1C9D2E9F1H2H9

M8

H1

A9

B3

T1

T9

E1G8J2J8M1M9P1

P9

B1B9D1D8E2E8F9G1G9

L3

L8

OMIT_TABLE

MT41K256M16HA-125:E

FBGA

4GB-DDR3L-1600-256MX16

U2520

N3 P7

L7 R7 N7 T3 T7

P3 N2 P8 P2 R8 R2 T8 R3

M2 N8 M3

K3

J7 K7

K9 L2

E3 F7

C8 C2 A7 A2 B8 A3

F2 F8 H3 H8 G2 H7 D7 C3

E7

F3 G3

J1 J9 L1 L9 M7

K1

J3

T2

D3

C7 B7

B2D9G7K2K8N1N9R1R9

A1A8C1C9D2E9F1H2H9

M8

H1

A9

B3

T1

T9

E1G8J2J8M1M9P1

P9

B1B9D1D8E2E8F9G1G9

L3

L8

CERM-X5R-1

0.47UF

20%

4V

201

C2547

1

2

0.047UF

6.3V X5R 201

10%

C2568

1

2

0.047UF

6.3V X5R 201

10%

C2569

1

2

CERM-X5R 0201

6.3V

0.1UF

10%

C2565

1

2

CERM-X5R 0201

6.3V

0.1UF

10%

C2525

1

2

CERM-X5R 0201

6.3V

0.1UF

10%

C2543

1

2

CERM-X5R 0201

6.3V

0.1UF

10%

C2503

1

2

1/20W

MF

1%

240

201

R2500

12

0.047UF

6.3V X5R 201

10%

C2528

1

2

0.047UF

6.3V X5R 201

10%

C2529

1

2

10V

20%

402

X5R-CERM

2.2UF

C2540

1

2

10V

20%

2.2UF

X5R-CERM

402

C2500

1

2

CERM-X5R 0201

6.3V

0.1UF

10%

C2573

1

2

MT41K256M16HA-125:E

4GB-DDR3L-1600-256MX16

OMIT_TABLE

FBGA

U2500

N3 P7

L7 R7 N7 T3 T7

P3 N2 P8 P2 R8 R2 T8 R3

M2 N8 M3

K3

J7 K7

K9 L2

E3 F7

C8 C2 A7 A2 B8 A3

F2 F8 H3 H8 G2 H7 D7 C3

E7

F3 G3

J1 J9 L1 L9 M7

K1

J3

T2

D3

C7 B7

B2D9G7K2K8N1N9R1R9

A1A8C1C9D2E9F1H2H9

M8

H1

A9

B3

T1

T9

E1G8J2J8M1M9P1

P9

B1B9D1D8E2E8F9G1G9

L3

L8

CERM-X5R 0201

6.3V

0.1UF

10%

C2533

1

2

CERM-X5R 0201

6.3V

0.1UF

10%

C2544

1

2

CERM-X5R 0201

6.3V

0.1UF

10%

C2504

1

2

CERM-X5R 0201

6.3V

0.1UF

10%

C2574

1

2

CERM-X5R 0201

6.3V

0.1UF

10%

C2575

1

2

CERM-X5R 0201

6.3V

0.1UF

10%

C2534

1

2

CERM-X5R 0201

6.3V

0.1UF

10%

C2545

1

2

CERM-X5R 0201

6.3V

0.1UF

10%

C2535

1

2

CERM-X5R 0201

6.3V

0.1UF

10%

C2553

1

2

CERM-X5R 0201

6.3V

0.1UF

10%

C2505

1

2

CERM-X5R 0201

6.3V

0.1UF

10%

C2513

1

2

CERM-X5R 0201

6.3V

0.1UF

10%

C2554

1

2

CERM-X5R 0201

6.3V

0.1UF

10%

C2514

1

2

10V

20%

402

X5R-CERM

2.2UF

C2541

1

2

10V

20%

402

X5R-CERM

2.2UF

C2501

1

2

2.2UF

X5R-CERM

402

20% 10V

C2550

1

2

X5R-CERM

2.2UF

402

20% 10V

C2510

1

2

X5R-CERM

2.2UF

402

20% 10V

C2551

1

2

X5R-CERM

2.2UF

402

20% 10V

C2511

1

2

2.2UF

X5R-CERM

402

20% 10V

C2560

1

2

1/20W

1% MF

240

201

R2560

12

2.2UF

X5R-CERM

402

20% 10V

C2520

1

2

CERM-X5R 0201

6.3V

0.1UF

10%

C2555

1

2

CERM-X5R 0201

6.3V

0.1UF

10%

C2515

1

2

10V

20%

402

X5R-CERM

2.2UF

C2561

1

2

10V

20%

402

X5R-CERM

2.2UF

C2521

1

2

CERM-X5R 0201

6.3V

0.1UF

10%

C2563

1

2

CERM-X5R 0201

6.3V

0.1UF

10%

C2523

1

2

CERM-X5R 0201

6.3V

0.1UF

10%

C2564

1

2

CERM-X5R 0201

6.3V

0.1UF

10%

C2524

1

2

10V

20%

402

X5R-CERM

2.2UF

C2570

1

2

10V

20%

402

X5R-CERM

2.2UF

C2530

1

2

X5R-CERM

2.2UF

10V 402

20%

C2571

1

2

X5R-CERM

2.2UF

402

10V

20%

C2531

1

2

SYNC_MASTER=MASTER

SYNC_DATE=MASTER

DDR3 SDRAM BANK B (RANK 0)

MEM_B_CLK_N<0>

MEM_B_ODT<0>

MEM_B_CS_L<0>

MEM_B_CKE<0>

MEM_RESET_L

MEM_B_ZQ<2>

MEM_B_A<14>

MEM_B_A<6>

MEM_B_CAS_L

MEM_B_RAS_L

MEM_B_BA<0> MEM_B_BA<1>

MEM_B_A<13>

MEM_B_A<11>

MEM_B_A<10>

MEM_B_A<8>

MEM_B_A<5>

MEM_B_A<9>

MEM_B_CLK_P<0>

MEM_B_WE_L

MEM_B_A<12>

MEM_B_A<7>

MEM_B_BA<2>

MEM_B_A<2> MEM_B_A<3>

MEM_B_A<1>

MEM_B_A<0>

MEM_B_A<4>

MEM_B_ODT<0>

MEM_B_CAS_L

MEM_B_RAS_L

MEM_B_BA<2>

MEM_B_BA<0> MEM_B_BA<1>

MEM_B_CS_L<0>

MEM_B_CKE<0>

MEM_B_CLK_P<0> MEM_B_CLK_N<0>

MEM_B_WE_L

MEM_RESET_L

MEM_B_ZQ<0>

=MEM_B_DQS_P<5> =MEM_B_DQS_N<5>

MEM_B_DQS_N<6>

MEM_B_DQS_P<6>

=MEM_B_DQ<47>

=MEM_B_DQ<46>

=MEM_B_DQ<45>

=MEM_B_DQ<42>

MEM_B_DQ<32>

=MEM_B_DQ<43>

=MEM_B_DQ<41>

=MEM_B_DQ<40>

=MEM_B_DQ<39>

=MEM_B_DQ<38>

=MEM_B_DQ<37>

=MEM_B_DQ<36>

=MEM_B_DQ<35>

=MEM_B_DQ<34>

=MEM_B_DQ<33>

=MEM_B_DQ<32>

PP1V35_S3

=MEM_B_DQS_P<1>

=MEM_B_DQS_N<0>

=MEM_B_DQS_P<0>

=MEM_B_DQ<15>

=MEM_B_DQ<14>

=MEM_B_DQ<10>

=MEM_B_DQ<12>

=MEM_B_DQ<11>

=MEM_B_DQ<9>

=MEM_B_DQS_N<1>

=MEM_B_DQ<13>

PP0V675_S3_MEM_VREFDQ_B

PP0V675_S3_MEM_VREFCA_B

MEM_B_A<14>

MEM_B_A<2>

MEM_B_A<1>

MEM_B_A<0>

MEM_B_A<13>

MEM_B_A<11>

MEM_B_A<10>

MEM_B_A<8>

MEM_B_A<4>

MEM_B_A<7>

MEM_B_A<12>

MEM_B_A<9>

MEM_B_A<6>

MEM_B_A<5>

MEM_B_A<3>

PP1V35_S3

=MEM_B_DQ<8>

=MEM_B_DQ<7>

=MEM_B_DQ<6>

=MEM_B_DQ<5>

=MEM_B_DQ<4>

=MEM_B_DQ<3>

=MEM_B_DQ<2>

=MEM_B_DQ<1>

=MEM_B_DQ<0>

PP0V675_S3_MEM_VREFDQ_B

PP0V675_S3_MEM_VREFCA_B

MEM_B_A<7>

MEM_B_A<12>

MEM_B_WE_L

MEM_B_CLK_P<0>

MEM_B_A<9>

MEM_B_A<5>

MEM_B_A<4>

MEM_B_A<8>

MEM_B_A<10> MEM_B_A<11>

MEM_B_A<13>

MEM_B_BA<1>

MEM_B_BA<0>

MEM_B_BA<2>

MEM_B_RAS_L MEM_B_CAS_L

MEM_B_ODT<0>

MEM_B_A<6>

MEM_B_A<0> MEM_B_A<1>

MEM_B_A<3>

MEM_B_A<2>

MEM_B_A<14>

MEM_B_A<7>

MEM_B_A<12>

MEM_B_WE_L

MEM_B_CLK_N<0>

MEM_B_CLK_P<0>

MEM_B_A<9>

MEM_B_A<8>

MEM_B_A<10> MEM_B_A<11>

MEM_B_A<13>

MEM_B_CKE<0> MEM_B_CS_L<0>

MEM_B_BA<1>

MEM_B_BA<0>

MEM_B_BA<2>

MEM_B_RAS_L MEM_B_CAS_L

MEM_B_ODT<0>

MEM_B_A<6>

MEM_B_A<0> MEM_B_A<1>

MEM_B_A<3>

MEM_B_A<2>

MEM_B_A<14>

MEM_B_CS_L<0>

MEM_B_CKE<0>

MEM_B_CLK_N<0>

MEM_B_A<4> MEM_B_A<5>

MEM_RESET_L

MEM_B_ZQ<1>

MEM_B_ZQ<3>

=MEM_B_DQS_N<7>

=MEM_B_DQS_P<7>

=MEM_B_DQ<48> =MEM_B_DQ<49> =MEM_B_DQ<50> =MEM_B_DQ<51> =MEM_B_DQ<52> =MEM_B_DQ<53> =MEM_B_DQ<54> =MEM_B_DQ<55> =MEM_B_DQ<56> =MEM_B_DQ<57>

=MEM_B_DQ<59> =MEM_B_DQ<60>

=MEM_B_DQ<58>

=MEM_B_DQ<61> =MEM_B_DQ<62> =MEM_B_DQ<63>

=MEM_B_DQS_P<6> =MEM_B_DQS_N<6>

PP1V35_S3

PP0V675_S3_MEM_VREFDQ_B

PP0V675_S3_MEM_VREFCA_B

=MEM_B_DQ<25>

=MEM_B_DQ<27> =MEM_B_DQ<28>

=MEM_B_DQ<26>

=MEM_B_DQ<29>

=MEM_B_DQ<31>

=MEM_B_DQS_P<2> =MEM_B_DQS_N<2>

=MEM_B_DQS_N<3>

=MEM_B_DQS_P<3>

=MEM_B_DQ<30>

PP1V35_S3

=MEM_B_DQ<16> =MEM_B_DQ<17> =MEM_B_DQ<18> =MEM_B_DQ<19> =MEM_B_DQ<20> =MEM_B_DQ<21> =MEM_B_DQ<22> =MEM_B_DQ<23> =MEM_B_DQ<24>

PP0V675_S3_MEM_VREFDQ_B

PP0V675_S3_MEM_VREFCA_B

PP1V35_S3

<SCH_NUM>

25 OF 120

21 OF 78

7

21 22 73

7 21 22 73

20 21 22 70

21 22 66 73

7 21 22 66 73

21 22 66 73

7 21 22 66 73

21 22 66 73

7 21 22 73

7 21 22 66 73

21 22 66 73

21 22 73

7 21 22 66 73

21 22 66 73

7 21 22 66 73

7 21 22 73

7 21 22 66 73

20 21 22 70

67

7 67 73

67

7 67 68 73

67

17 19 20 21 22 41 55 65 73

67

19 21 65 73

21 22 66 73

7 21 22 66 73

21 22 66 73

17 19 20 21 22 41 55 65 73

67

19 21 65 73

21 22 66 73

7 21 22 66 73

7 21 22 73

21 22 66 73

7 21 22 66 73

21 22 66 73

7 21 22 66 73

21 22 73

7 21 22 66 73

21 22 66 73

7 21 22 66 73

7 21 22 73

21 22 66 73

7 21 22 73

7 21 22 66 73

21 22 66 73

7 21 22 66 73

21 22 73

7 21 22 66 73

21 22 66 73

7 21 22 73

21 22 66 73

20 21 22 70

67

17 19 20 21 22 41 55 65 73

19 21 65 73

67

17 19 20 21 22 41 55 65 73

67

19 21 65 73

17 19 20 21 22 41 55 65 73

w w w . c h i n a f i x . c o m

IN

NC

IN

IN IN

IN

NC

IN

NC

IN IN

NC

IN

NC NC

IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87

6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

MEM_ODT:PU disconnect ODT from CPU, ODT pins on DRAM pulled up to 1.35V VDDQ.

Memory ODT Option

MEMORY RPACK SPARES

(Connects to DRAM)

(Connects to CPU)

Memory CMD/CTL Termination - Channel B

Memory CMD/CTL Termination - Channel A

Memory Clock Far-End Termination

Place RC end termination after last DRAM

Place Source C termination before first DRAM

Near-End Termination

Memory Reset Pull Up

Reset is an open drain in Haswell ULT and needs pull up

Memory Clock

MEM_ODT:CPU drives ODT from CPU, terminated to 0.675V VTT.

201

4V

0.47UF

20% CERM-X5R-1

C2704

1

2

201

4V

0.47UF

CERM-X5R-1

20%

C2702

1

2

201

20%

0.47UF

4V CERM-X5R-1

C2700

1

2

201

0.47UF

CERM-X5R-1

20% 4V

C2723

1

2

201

0.47UF

CERM-X5R-1

20% 4V

C2727

1

2

201

0.47UF

CERM-X5R-1

20% 4V

C2725

1

2

201

0.47UF

CERM-X5R-1

20% 4V

C2707

1

2

201

20%

0.47UF

CERM-X5R-1

4V

C2703

1

2

201

0.47UF

CERM-X5R-1

20% 4V

C2705

1

2

201

0.47UF

20% 4V CERM-X5R-1

C2730

1

2

201

0.47UF

CERM-X5R-1

20% 4V

C2728

1

2

201

0.47UF

CERM-X5R-1

20% 4V

C2726

1

2

MEM_ODT:CPU

0.00

MF

0201

PLACE_NEAR=U0500.AP32:8MM

1%

1/20W

R2780

12

7

66

201

5%

36

MF

1/20W

MEM_ODT:CPU

R2781

12

20

73

201

MEM_ODT:PU

5%

36

1/20W

MF

R2782

12

201

36

MEM_ODT:PU

MF

1/20W

5%

R2792

12

201

MF

36

5%

MEM_ODT:CPU

1/20W

R2791

12

MF

0201

1/20W

1%

0.00

MEM_ODT:CPU

PLACE_NEAR=U0500.AL32:8MM

R2790

12

21

73

7

66

36

5%

4X0201

1/32W

RP2701

18

36

4X0201

1/32W

5%

RP2701

27

5%

1/32W

4X0201

36

RP2720

36

5%

1/32W

4X0201

RP2728

27

20

66 73

20 66 73

7

20

66 73

20 66 73

7

20

73

20 66 73

7

20

66 73

20 66 73

7

20

66 73

7

20

73

7

20

66 73

7

20

66 73

4X0201

36

5%

1/32W

RP2701

45

1/32W

36

4X0201

5%

RP2705

18

5%

4X0201

1/32W

36

RP2702

27

5%

1/32W

36

4X0201

RP2706

27

5%

4X0201

1/32W

36

RP2703

18

5%361/32W

4X0201

RP2702

18

1/32W

5%

4X0201

36

RP2703

27

1/32W

36

4X0201

5%

RP2705

27

1/32W

5%

4X0201

36

RP2706

18

4X0201

5%361/32W

RP2707

36

4X0201

1/32W

5%

36

RP2705

36

4X0201

1/32W

5%

36

RP2706

45

1/32W

5%

4X0201

36

RP2702

36

5%

4X0201

36

1/32W

RP2703

45

1/32W

36

5%

4X0201

RP2704

36

1/32W

5%

36

4X0201

RP2707

27

36

5%

1/32W

4X0201

RP2704

18

1/32W

5%

36

4X0201

RP2702

45

5%361/32W

4X0201

RP2707

18

36

1/32W

5%

4X0201

RP2703

36

1/32W

36

4X0201

5%

RP2705

45

1/32W

5%

4X0201

36

RP2707

45

4X0201

36

5%

1/32W

RP2701

36

1/32W

5%

4X0201

36

RP2704

45

1/32W

5%

36

4X0201

RP2704

27

36

5%

1/32W

4X0201

RP2706

36

7

21

66 73

21 66 73

7

21

66 73

21 66 73

7

21

73

7

21

66 73

7

21

66 73

7

21

73

1/32W

5%

4X0201

36

RP2722

27

1/32W

5%

4X0201

36

RP2728

18

1/32W

5%

4X0201

36

RP2725

18

36

1/32W

5%

4X0201

RP2725

27

1/32W

5%

4X0201

36

RP2720

27

36

4X0201

1/32W

5%

RP2725

36

1/32W

5%

4X0201

36

RP2730

27

1/32W

5%

4X0201

36

RP2726

45

1/32W

5%

4X0201

36

RP2730

18

1/32W

5%

4X0201

36

RP2730

36

1/32W

5%

4X0201

36

RP2726

27

1/32W

5%

4X0201

36

RP2724

45

1/32W

5%

4X0201

36

RP2724

18

1/32W

5%

4X0201

36

RP2726

36

1/32W

5%

4X0201

36

RP2722

36

1/32W

5%

4X0201

36

RP2730

45

1/32W

5%

4X0201

36

RP2726

18

1/32W

5%

4X0201

36

RP2724

36

4X0201

5%

1/32W

RP2725

45

1/32W

5%

4X0201

36

RP2724

27

36

5%

1/32W

4X0201

RP2720

45

1/32W

5%

4X0201

36

RP2722

18

1/32W

5%

4X0201

36

RP2720

18

36

4X0201

1/32W

5%

RP2728

45

5%

1/32W

4X0201

36

RP2728

36

1/32W

5%

4X0201

36

RP2722

45

21

66 73

21 66 73

7

21

66 73

21 66 73

7

22

7

22

7

22

7

22

7

22

7

22

7

21

22 73

7

21

22 73

7

20

22 73

7

20

22 73

5%

201

CERM

3.3PF

25V

C2760

1

2

5%

201

3.3PF

CERM

25V

C2750

1

2

7

21

22 73

7

21

22 73

7

20

22 73

7

20

22 73

30

MF

1/20W

201

5%

R2761

12

30

MF

1/20W

201

5%

R2760

12

30

MF

1/20W

201

5%

R2751

12

30

MF

1/20W

201

5%

R2750

12

MF

0201

1/20W

5%

0

R2711

12

201

4V CERM-X5R-1

20%

0.47UF

NO STUFF C2711

1

2

470

1% 1/20W MF 201

R2710

1

2

10%

0.1UF

0201

CERM-X5R

6.3V

C2761

12

10%

0.1UF

0201

CERM-X5R

6.3V

C2751

12

CERM-X5R-1 201

0.47UF

20% 4V

C2724

1

2

201

0.47UF

CERM-X5R-1

20% 4V

C2722

1

2

201

4V

20% CERM-X5R-1

0.47UF

C2720

1

2

201

0.47UF

CERM-X5R-1

20% 4V

C2710

1

2

201

0.47UF

CERM-X5R-1

20% 4V

C2708

1

2

201

CERM-X5R-1

20% 4V

0.47UF

C2706

1

2

SYNC_DATE=04/02/2013

SYNC_MASTER=J44_YONAS-4GB

DDR3 Termination

PP0V675_S0_DDRVTT

MEM_B_CLK_N<0>

MEM_B_CLK_P<0>

MEM_A_CLK_N<0>

MEM_A_CLK_P<0>

MEM_B_CLK_P<0>

MEM_B_CLK_N<0>

MEM_A_CLK_P<0>

MEM_A_CLK_N<0>

MEM_B_CLK0_TERM_R

MEM_RESET_HSW_L

MEM_RESET_L

MEM_A_CLK0_TERM_R

PP1V35_S3

NO_TEST=TRUEMAKE_BASE=TRUE

NC_MEM_B_A15NC_MEM_B_A15

NO_TEST=TRUEMAKE_BASE=TRUE

NC_MEM_A_A15NC_MEM_A_A15

PP0V675_S0_DDRVTT

NO_TEST=TRUEMAKE_BASE=TRUE

NC_MEM_B_CS_L1

NC_MEM_B_CKE1

NC_MEM_B_CS_L1

NO_TEST=TRUEMAKE_BASE=TRUE

NC_MEM_B_CKE1

NC_MEM_A_CKE1

MEM_B_A<10>

MEM_B_A<12> MEM_B_BA<1>

MEM_B_A<8>

MEM_B_A<6>

MEM_B_A<4>

MEM_B_A<11>

MEM_B_CKE<0>

MEM_B_A<7>

MEM_B_A<5>

MEM_B_A<3>

MEM_B_BA<0>

MEM_B_CS_L<0>

MEM_B_A<14>

MEM_B_A<1>

MEM_B_A<13>

MEM_B_A<9>

MEM_B_A<2>

MEM_B_A<0>

MEM_B_BA<2>

MEM_B_WE_L

MEM_B_CAS_L

MEM_B_RAS_L

PP1V35_S3

MEM_A_ODT<0>

MAKE_BASE=TRUE

MEM_B_ODT<0>

MEM_A_ODT_CPU0

MEM_B_ODT_CPU0

MEM_A_RAS_L MEM_A_CAS_L MEM_A_WE_L MEM_A_BA<2>

MEM_A_A<2> MEM_A_A<9> MEM_A_A<13>

MEM_A_BA<1> MEM_A_A<4> MEM_A_A<6>

MEM_A_A<1> MEM_A_A<11>

MEM_A_CS_L<0> MEM_A_BA<0> MEM_A_A<3> MEM_A_A<5>

MEM_A_CKE<0>

MEM_A_A<0>

MEM_A_A<14>

MEM_A_A<12>

MEM_A_A<10>

MEM_A_A<8>

NC_MEM_A_CKE1

NO_TEST=TRUEMAKE_BASE=TRUE

NO_TEST=TRUE

NC_MEM_A_CS_L1

MAKE_BASE=TRUE

NC_MEM_A_CS_L1

MEM_A_A<7>

<SCH_NUM>

27 OF 120

22 OF 78

22

55 65 68 73

6

66 20

21 70

17 19 20 21 22 41 55 65 73

7

22

7

22

55 65 68 73

22 55 65 68 73

7

22

7

22

17

19 20 21 22 41 55 65 73

7

22

7

22

w w w . c h i n a f i x . c o m

OUT

IN

OUT

IN

OUT

IN

OUT OUT

IN

OUT

IN IN

OUT

BI

IN

BI

OUT IN

OUT

IN

OUT OUT

BI BI

IN

IN IN IN OUT

OUT OUT

BI BI

IN

OUT OUT OUT

OUT

IN

IN IN

IN

OUT

PORTS

MISC

(1 OF 2)

PCIE GEN2

DISPLAY PORT

DPSNK1_2_N

DPSNK1_2_P

DPSNK1_3_P

PERP_2 PERN_2

PETN_3

PETP_3

PETN_1

PETP_1

PETP_0 PETN_0

XTAL_25_OUT

XTAL_25_IN

EE_CS_N

DPSNK0_0_N

DPSNK0_0_P

DPSNK0_1_N

DPSNK0_1_P

DPSNK0_2_N

DPSNK0_2_P

DPSNK0_AUX_N

DPSNK0_AUX_P

DPSNK0_HPD

DPSNK1_0_N

DPSNK1_0_P

DPSNK1_1_N

DPSNK1_1_P

DPSNK1_3_N

DPSNK1_AUX_N

DPSNK1_AUX_P

DPSNK1_HPD

DPSRC_0_N

DPSRC_0_P

DPSRC_1_N

DPSRC_1_P

DPSRC_2_N

DPSRC_2_P

DPSRC_3_N

DPSRC_3_P

DPSRC_AUX_N

DPSRC_AUX_P

DPSRC_HPD_OD

EE_CLK

EE_DI EE_DO

GPIO_0/PA_HV_EN/BYP0 GPIO_1/PB_HV_EN/BYP0 GPIO_10/PA_CIO_SEL/BYP1 GPIO_11/PB_CIO_SEL/BYP1 GPIO_12/PA_DP_PWRDN/BYP2 GPIO_13/PB_DP_PWRDN/BYP2

GPIO_14 GPIO_15

GPIO_2/TMU_CLK_IN/AC_PRESENT

GPIO_3/FORCE_PWR GPIO_4/WAKE_OD_N

GPIO_5/CIO_PLUG_EVENT_N/HV_OK_OD

GPIO_6_OD/CIO_SDA_OD GPIO_7_OD/CIO_SCL_OD

GPIO_8/EN_CIO_PWR_OD*

GPIO_9/SX_CTRL_OD*

MONDC0

MONOBSN

MONOBSP

PA_AUX_N

PA_AUX_P

PA_CIO0_RX_N

PA_CIO0_RX_P

PA_CIO0_TX_N/DPSRC_0_N

PA_CIO0_TX_P/DPSRC_0_P

PA_CIO1_RX_N

PA_CIO1_RX_P

PA_CIO1_TX_N/DPSRC_2_N

PA_CIO1_TX_P/DPSRC_2_P

PA_CONFIG1/CIO_0_LSEO PA_CONFIG2/CIO_0_LSOE

PA_DPSRC_1_N

PA_DPSRC_1_P

PA_DPSRC_3_N

PA_DPSRC_3_P

PA_DPSRC_HPD

PA_LSRX/CIO_1_LSOE

PA_LSTX/CIO_1_LSEO

PB_AUX_N

PB_AUX_P

PB_CIO2_RX_N

PB_CIO2_RX_P

PB_CIO2_TX_N/DPSRC_0_N

PB_CIO2_TX_P/DPSRC_0_P

PB_CIO3_RX_N

PB_CIO3_RX_P

PB_CIO3_TX_N/DPSRC_2_N

PB_CIO3_TX_P/DPSRC_2_P

PB_CONFIG1/CIO_2_LSEO PB_CONFIG2/CIO_2_LSOE

PB_DPSRC_1_N

PB_DPSRC_1_P

PB_DPSRC_3_N

PB_DPSRC_3_P

PB_DPSRC_HPD

PB_LSRX/CIO_3_LSOE

PB_LSTX/CIO_3_LSEO

PCIE_CLKREQ_OD_N

PCIE_RST_0_N PCIE_RST_1_N PCIE_RST_2_N PCIE_RST_3_N

PERN_0

PERN_1

PERN_3

PERP_0

PERP_1

PERP_3

PERST_OD_N

PETN_2

PETP_2

PWR_ON_POC_RSTN

RBIAS

REFCLK_100_IN_N

REFCLK_100_IN_P

RSENSE

RSVD

TCK

TDI

TDO TEST_EN

THERMDA

TMS

TMU_CLK_OUT

MONDC1

TEST_PWR_GOOD

DPSNK0_3_P DPSNK0_3_N

VCC

DO/IO1

GND

THRM_PAD

CS*

CLK

WP*

HOLD*

DI/IO0

IN

OUT

IN

OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87

6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

DEBUG: For monitoring current/voltage

SNK0 AC Coupling

SNK1 AC Coupling

(TBT_SPI_MISO)(TBT_SPI_MOSI)

(TBT_SPI_CLK)

Used for straps in host mode

depends on the code in the flash.

bit in the flash, so the active-level

Security strap setting is XORed with

If strap != bit then security is enabled?

(TBT_SPI_CS_L)

Use AA8 GND ball for THERM_DN

DEBUG: For monitoring clock

Divides 3.3V to 1.8V

NOTE: The following pins require testpoints:

8 - GPIO_15 9 - GPIO_11

15 - PB_LSRX

14 - PB_LSTX

13 - GPIO_10

12 - GPIO_12

10 - GPIO_14 11 - GPIO_0

5 - PCIE_RST_1_N

0 - GPIO_13

3 - GPIO_3

2 - GPIO_2

4 - GPIO_5

1 - GPIO_1

7 - PCIE_RST_3_N

6 - PCIE_RST_2_N

For unused port, pull CONFIG1, CONFIG2, LSRX, HPD and CIO_SEL low (10k). All other port signals can be NC.

5%

3.3K

201

1/20W

MF

R2890

1

2

13

64

201

1/20W MF

5%

100

R2825

1

2

26

68 74

26 68 74

26

26 68 74

27

27 68 74

27

27 68 74

5%

100K

201

1/20W

MF

R2830

1

2

5%

100K

201

1/20W

MF

R2831

1

2

26

74

26 74

5%

3.3K

201

1/20W MF

R2893

1

2

10%

16V

X5R-CERM

0.1UF

0201

C2829

12

13

74

13 74

5

74

5

74

5

74

5

74

5

74

5

74

5

74

5

74

16V

10% X5R-CERM

0.1UF

0201

C2828

12

10%

16V

X5R-CERM

0.1UF

0201

C2827

12

16V

10% X5R-CERM

0.1UF

0201

C2826

12

10%

16V

X5R-CERM

0.1UF

0201

C2825

12

16V

10%

0.1UF

X5R-CERM

0201

C2824

12

10%

16V

X5R-CERM

0.1UF

0201

C2823

12

16V

10% X5R-CERM

0.1UF

0201

C2822

12

MF

1/20W 201

1K

1%

R2855

1

2

10%

16V

X5R-CERM

0.1UF

0201

C2821

12

10%

16V

X5R-CERM

0.1UF

0201

C2820

12

10%

16V

X5R-CERM

0.1UF

0201

C2830

12

10%

16V

X5R-CERM

0.1UF

0201

C2831

12

10%

16V

X5R-CERM

0.1UF

0201

C2832

12

10%

16V

X5R-CERM

0.1UF

0201

C2833

12

10%

16V

0.1UF

X5R-CERM

0201

C2834

12

10%

16V

X5R-CERM

0.1UF

0201

C2835

12

10%

16V

X5R-CERM

0.1UF

0201

C2836

12

10%

16V

X5R-CERM

0.1UF

0201

C2837

12

10%

16V

X5R-CERM

0.1UF

0201

C2838

12

10%

16V

0.1UF

X5R-CERM

0201

C2839

12

64

74

64 74

402

CERM

6.3V

10%

1UF

BYPASS=U2890:2mm

C2890

1

2

64

74

64 74

26

27

15 18

27 74

27

16 18

18

16 18

18

26 74

26

23 25 26

26

23 26

23 27 28

27

23 27

23 24

18 36 37

12

17 71

806

1%

1/20W

MF

201

R2895

12

5%

1K

201

MF

1/20W

R2896

1

2

201

10K

NO STUFF

1/20W

5% MF

R2899

1

2

12

68 70

12 68 70

24

0201

OMIT

NONE

NOSTUFF

NONE

R2815

1

2

MF

1/20W

201

10K

5%

R2888

1

2

5% 1/20W MF 201

10K

R2887

1

2

10K

MF

1/20W 201

5%

NO STUFF

R2886

1

2

MF

1/20W

201

10K

5%

NO STUFF

R2885

1

2

5%

201

1/20W

MF

100K

R2880

1

2

15

23

28

15 18 72

100K

MF

1/20W 201

5%

R2883

1

2

OMIT_TABLE

CRITICAL

REDWOOD-RIDGE

FCBGA

U2800

D19

E20

D17

E18

D15

E16

D13

E14

G2

G4

AB5

D11

E12

D9

E10

D7

E8

D5

E6

H1

H3

U4

B9

A8

B11

A10

B13

A12

B15

A14

J2

J4

AC2

U8

T5

AA2

Y3

R8 N2 R2 P3 F3

T1 T3

F1

U2 L6 H5 Y7 Y1 T7 V7 M7

AD23 AC24

W16

W18

L2

L4

E22

G22

E24

G24

J22

L22

J24

L24

P1 K5

B17

A16

B19

A18

M3

J6

N8

K1

K3

N22

R22

N24

R24

U22

W22

U24

W24

D3 M1

B21

A20

B23

A22

N6

P7

M5

V3

W6 AB3 AD3 V1

AA10

AB13

AA16

AB19

AB9

AA12

AB15

AA18

P5

AD7

AD11

AD15

AD19

AD5

AD9

AD13

AD17

R4

W20

AD21

AB21

U20

AD1 L8

AA6

W2

U6 R6 W8

AB7

AB1

AA4

AA24 AB23

CRITICAL OMIT_TABLE

W25X40CLXIG

4MBIT

USON

U2890

6

1

52

479

8

3

23

25

23 26 27

MF

1/20W 201

10K

5%

R2861

1

2

5%

10K

201

1/20W MF

R2863

1

2

NO STUFF

5%

10K

201

1/20W MF

R2867

1

2

5%

10K

201

1/20W MF

R2862

1

2

100K

5%

201

1/20W

MF

R2881

1

2

5% MF

1/20W

201

10K

R2829

1

2

5%

201

1/20W

MF

100K

R2884

1

2

100K

5%

201

1/20W MF

R2882

1

2

15

23 64 66

5%

201

1/20W

MF

100K

R2878

1

2

100K

MF

1/20W 201

5%

R2879

1

2

100K

MF

1/20W

201

5%

R2832

1

2

X5R-CERM

16V

10%

0201

0.1UF

C2801

12

X5R-CERM

16V

0.1UF

10%

0201

C2800

12

X5R-CERM

16V

0.1UF

10%

0201

C2802

12

0.1UF

X5R-CERM

16V

10%

0201

C2803

12

5%

3.3K

201

1/20W

MF

R2892

1

2

16V

0201

X5R-CERM

10%

0.1UF

C2804

12

X5R-CERM

16V

10%

0.1UF

0201

C2805

12

X5R-CERM

16V

0.1UF

10%

0201

C2806

12

X5R-CERM

16V

0.1UF

10%

0201

C2807

12

0201

0.1UF

X5R-CERM

10% 16V

C2840

12

0201

0.1UF

X5R-CERM

10%

16V

C2841

12

0201

0.1UF

X5R-CERM

10%

16V

C2842

12

5%

3.3K

201

1/20W MF

R2891

1

2

0201

0.1UF

X5R-CERM

10%

16V

C2843

12

0201

0.1UF

X5R-CERM

10% 16V

C2845

12

0201

X5R-CERM

0.1UF

10%

16V

C2844

12

0201

X5R-CERM

0.1UF

16V10%

C2846

12

0201

X5R-CERM

0.1UF

16V

10%

C2847

12

14

68 70

14 68 70

Thunderbolt Host (1 of 2)

SYNC_MASTER=J44

SYNC_DATE=08/12/2013

TBT_B_CONFIG1_BUFTBT_A_CONFIG1_BUF

TBT_A_LSRX

DP_TBTPA_ML_C_P<3> DP_TBTPA_ML_C_N<3>

DP_TBTPA_AUXCH_C_P DP_TBTPA_AUXCH_C_N

DP_TBTPA_HPD TBT_A_HV_EN

TBT_A_DP_PWRDN

PP3V3_TBTLC

TBT_GPIO2

TBT_GPIO7

DP_TBTSRC_HPD

PP3V3_S4_TBT

TBT_EN_CIO_PWR_L

HDMITBTMUX_SEL_TBT

TBT_DDC_XBAR_EN_L

TBTDP_AUXIO_EN

PP3V3_S4_TBT

TBT_BATLOW_L

TBT_B_HV_EN

TBT_A_DP_PWRDN

TBT_ROM_SECURITY_XOR

SMC_PME_S4_DARK_L

HDMITBTMUX_SEL_TBT

TBT_CIO_PLUG_EVENT_L

TBT_PWR_EN

TP_DP_TBTSRC_AUXCH_CP

JTAG_TBT_TMS JTAG_ISP_TCK JTAG_TBT_TDO TBT_TEST_EN TBT_TEST_PWR_GOOD

TBT_SPI_MOSI

TBT_SPI_CS_L TBT_SPI_CLK

TBT_SPI_MISO

TBT_MONOBSP TBT_MONOBSN

TP_TBT_MONDC1

PCIE_TBT_R2D_N<1>

DP_TBTSNK0_ML_P<1> DP_TBTSNK0_ML_N<1>

TP_DP_TBTSRC_ML_CN<1>

TBT_A_R2D_C_P<0>

PP3V3_TBTLC

PCIE_TBT_R2D_P<2>

TBT_DFT_STRAP_1

TBT_DFT_STRAP_3

TBTDP_AUXIO_EN

TBT_BATLOW_L

TBTROM_WP_L TBTROM_HOLD_L

DP_TBTSNK1_ML_N<2>

DP_TBTSNK1_ML_P<2>

DP_TBTSNK1_ML_P<3>

PCIE_TBT_R2D_N<2>

PCIE_TBT_D2R_C_N<3>

PCIE_TBT_D2R_C_P<3>

PCIE_TBT_D2R_C_N<1>

PCIE_TBT_D2R_C_P<1>

PCIE_TBT_D2R_C_P<0> PCIE_TBT_D2R_C_N<0>

TP_TBT_XTAL25OUT

DP_TBTSNK0_ML_N<0>

DP_TBTSNK0_ML_P<0>

DP_TBTSNK0_ML_N<2>

DP_TBTSNK0_ML_P<2>

DP_TBTSNK0_AUXCH_N

DP_TBTSNK0_AUXCH_P

DP_TBTSNK0_HPD

DP_TBTSNK1_ML_N<0>

DP_TBTSNK1_ML_P<0>

DP_TBTSNK1_ML_N<1>

DP_TBTSNK1_ML_P<1>

DP_TBTSNK1_ML_N<3>

DP_TBTSNK1_AUXCH_N

DP_TBTSNK1_AUXCH_P

DP_TBTSNK1_HPD

TP_DP_TBTSRC_ML_CP<0>

TP_DP_TBTSRC_ML_CP<2>

TBT_B_HV_EN

TBT_A_CIO_SEL TBT_B_CIO_SEL

TBT_B_DP_PWRDN

TP_TBT_MONDC0

TBT_A_D2R_N<0>

TBT_A_D2R_P<0>

TBT_A_R2D_C_N<0>

TBT_A_D2R_N<1>

TBT_A_D2R_P<1>

TBT_A_R2D_C_N<1>

TBT_A_R2D_C_P<1>

TBT_A_CONFIG2_RC

DP_TBTPA_ML_C_N<1>

DP_TBTPA_ML_C_P<1>

TBT_A_LSTX

DP_TBTPB_AUXCH_C_N

DP_TBTPB_AUXCH_C_P

TBT_B_D2R_N<0>

TBT_B_D2R_P<0>

TBT_B_R2D_C_P<0>

TBT_B_D2R_N<1>

TBT_B_D2R_P<1>

TBT_B_R2D_C_N<1>

TBT_B_R2D_C_P<1>

TBT_B_CONFIG2_RC

DP_TBTPB_ML_C_N<1>

DP_TBTPB_ML_C_P<1>

DP_TBTPB_ML_C_N<3>

DP_TBTPB_ML_C_P<3>

DP_TBTPB_HPD

TBT_B_LSRX

TBT_B_LSTX

TP_TBT_PCIE_RESET0_L

PCIE_TBT_R2D_N<3>

PCIE_TBT_R2D_P<0>

PCIE_TBT_R2D_P<3>

PCIE_TBT_D2R_C_N<2>

PCIE_TBT_D2R_C_P<2>

TBT_RBIAS

PCIE_CLK100M_TBT_N

TBT_RSENSE

JTAG_ISP_TDI

TBTTHMSNS_D1_P

DP_TBTSNK0_ML_P<3> DP_TBTSNK0_ML_N<3>

PCIE_TBT_D2R_P<2>

DP_TBTSNK0_AUXCH_C_P

DP_TBTSNK0_AUXCH_N

DP_TBTSNK0_ML_C_N<3>

DP_TBTSNK0_ML_N<3>

DP_TBTSNK1_ML_C_P<3>

PCIE_TBT_D2R_P<3>

PCIE_TBT_R2D_C_P<1>

PCIE_TBT_R2D_C_N<1>

PCIE_TBT_R2D_C_N<2>

PCIE_TBT_R2D_C_P<2>

PCIE_TBT_R2D_C_P<0>

DP_TBTSNK1_ML_N<2>

DP_TBTSNK1_AUXCH_P

DP_TBTSNK1_ML_N<3>

DP_TBTSNK1_ML_P<3>

DP_TBTSNK1_ML_P<2>

DP_TBTSNK1_ML_P<1>

DP_TBTSNK0_ML_P<2>

DP_TBTSNK0_ML_N<2>

DP_TBTSNK0_ML_P<0>

DP_TBTSNK0_ML_N<0>

DP_TBTSNK0_ML_P<1>

DP_TBTSNK0_ML_N<1>

DP_TBTSNK1_AUXCH_C_N

DP_TBTSNK1_AUXCH_C_P

DP_TBTSNK1_ML_C_N<3>

DP_TBTSNK1_ML_C_P<2>

DP_TBTSNK1_ML_C_P<1>

DP_TBTSNK1_ML_C_N<0>

DP_TBTSNK1_ML_C_P<0>

DP_TBTSNK0_ML_C_P<3>

DP_TBTSNK0_ML_C_N<2>

DP_TBTSNK0_ML_C_P<2>

DP_TBTSNK0_ML_C_N<0>

PCIE_TBT_D2R_N<1>

PCIE_TBT_D2R_P<1>

PCIE_TBT_D2R_N<0>

PCIE_TBT_D2R_P<0>

DP_TBTSNK1_ML_N<1>

DP_TBTSNK1_ML_C_N<2>

DP_TBTSNK0_AUXCH_P

DP_TBTSNK1_AUXCH_N

PCIE_TBT_R2D_C_N<3>

DP_TBTSNK1_ML_P<0>

DP_TBTSNK0_ML_C_N<1>

DP_TBTSNK0_ML_C_P<1>

DP_TBTSNK0_AUXCH_C_N

DP_TBTSNK1_ML_C_N<1>

DP_TBTSNK1_ML_N<0>

DP_TBTSNK0_ML_P<3>

PCIE_TBT_R2D_C_P<3>

PCIE_TBT_D2R_N<2>

PCIE_TBT_D2R_N<3>

DP_TBTSNK0_ML_C_P<0>

PP3V3_TBTLC

SYSCLK_CLK25M_TBT

PCIE_TBT_R2D_N<0>

PCIE_TBT_R2D_P<1>

TBT_EN_CIO_PWR_L

TBT_B_R2D_C_N<0>

TBT_DDC_XBAR_EN_L

PCIE_TBT_R2D_C_N<0>

TP_DP_TBTSRC_ML_CP<1>

TP_DP_TBTSRC_ML_CN<2>

TP_DP_TBTSRC_ML_CN<3>

TP_DP_TBTSRC_ML_CP<3>

TBT_TMU_CLK_OUT

PCH_TBT_PCIE_RESET_L TBT_PWR_ON_POC_RST_L

PCIE_CLK100M_TBT_P

SYSCLK_CLK25M_TBT_R

TBT_A_HV_EN

TBT_B_DP_PWRDN

TP_DP_TBTSRC_AUXCH_CN

TP_DP_TBTSRC_ML_CN<0>

PP3V3_TBTLC

TBT_CLKREQ_L

23 OF 78

28 OF 120

<SCH_NUM>

17

18 23 24 65

23

23 24 25 42 65

23 24

15 23 64 66

23 28

23 26 27

23 24 25 42 65

23 25

23 27 28

23 26

74

68 70

23 74

17 18 23 24 65

68

70

23 74

68 70

68

70

68

70

68

70

68 70

70

23 74

68 70

68

70

68

70

68

70

68

70

43 77

23 74

17 18 23 24 65

68 70

68

70

71

23 25 26

23 27

17 18 23 24 65

w w w . c h i n a f i x . c o m

GND

VCC

(2 OF 2)

VSSVSS

VCC3P3_RDV_DECAP

VCC3P3_LC

VCC3P3

VCC1P0_RDV_DECAP

VCC1P0_CIO

SVR_VCC1P0

SVR_AMON

SVR_IND0

NC

SDG

VOUT

GND

ON

VIN

IN

OUT

IN

D

SYM_VER_3

SG

G

D

S

OUT

GND

SENSE

ENABLE SENSE_OUT

CT

VCC

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87

6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

U2950

TPS22920

Push-pull output

Isolated to reduce noise from SVR

Part

Type

R(on) @ 1.05V

Max Current = 4A (85C)

8 mOhm Typ

11.5 mOhm Max

Load Switch

Pull-up (S0) on PCH page

1.05V TBT "CIO" Switch

EDP: 1.25 A

25 mA EDP

1200 mA EDP

700 mA EDP

1900 mA EDP

SVR input to RR - 1100 mA EDP

POC input to RR - 150 mA EDP

2.4 W (Single-Port)

3.1 W (Dual-Port)

100 mA EDP

Internal switch not functional on RR.

Delay = 4.04ms nominal

TBT "POC" Power-up Reset

Vth = 2.508V nominal

EDP current / power consumption figures copied from R68 schematic (Rev 2, dated October 28, 2012, not available on IBL).

20%

1.0UF

X5R

6.3V

0201-1

C2906

1

2

FCBGA

REDWOOD-RIDGE

OMIT_TABLE

CRITICAL

U2800

B5

A4 A6

B3

J8 K9

L14 M15

M17

P17 V19

J10 J12

R14

T11 T15

U10 U14

V11

K11 L10

M11

N10 N14

P11

P15 R10

G10 G12

K19

K7 L16

M19 P19

T19

U18 V15

V17

W12

G14

W14

G16

G18

H19

H9

J18

K15 K17

D1

E2

H11 N4

V5

W4

Y5

H13

H15 H17

H7

L18 N18

R18

W10

A2

A24

AC14 AC16

AC18

AC20 AC22

AC4

AC6 AC8

B1

B7

AA14

C10

C12 C14

C16

C18

C2

C20

C22 C24

C4

AA20

C6

C8

D21 D23

E4

F11 F13

F15

F17 F19

AA22

F21

F23

F5

F7

F9

G20

G6

G8 H21

H23

AA8 J14

J16

J20

K13 K21

K23 L12

L20

M13 M21

AB11

M23

M9 N12

N16

N20 P13

P21 P23

P9

R12

AB17

R16

R20

T13 T17

T21

T23 T9

U12 U16

V13

AC10

V21 V23

V9

Y11 Y13

Y15

Y17 Y19

Y21 Y23

AC12

Y9

20%

1.0UF

X5R

6.3V

0201-1

C2911

1

2

0201-1

X5R

6.3V

1.0UF

20%

C2910

1

2

SM

680NH-30%-3.6A-35MOHM

CRITICAL

L2920

12

6.3V

CERM-X5R

0402-1

10UF

20%

C2922

1

2

6.3V

CERM-X5R

0402-1

10UF

20%

C2923

1

2

NSR1020MW2T1G

SOD-323

CRITICAL

D2920

A

K

DMN5L06VK-7

SOT-563

Q2945

6

2

1

100K

201

MF

1/20W

5%

R2945

1

2

CSP

TPS22920

CRITICAL

U2940

D1

D2

A2 B2

C2

A1 B1

C1

20% X5R

6.3V 0201-1

1.0UF

C2940

1

2

20%

1.0UF

X5R

6.3V

0201-1

C2981

1

2

20%

1.0UF

X5R

6.3V

0201-1

C2980

1

2

0201-1

6.3V X5R

20%

1.0UF

C2970

1

2

23

0201-1

6.3V X5R

1.0UF

20%

C2960

1

2

20%

1.0UF

X5R

6.3V

0201-1

C2961

1

2

20%

10UF

0402-1

CERM-X5R

6.3V

C2953

1

2

6.3V

CERM-X5R

0402-1

10UF

20%

C2952

1

2

6.3V

CERM-X5R

0402-1

10UF

20%

C2951

1

2

6.3V

CERM-X5R

0402-1

10UF

20%

C2950

1

2

PLACE_NEAR=C2953.1:1mm

SM

XW2960

1

2

23

X7R-CERM

0201

10%

330PF

16V

C2995

1

2

1/20W MF 201

24.9K

1%

R2991

1

2

X5R

10%

0.1UF

25V

402

C2990

1

2

15

MF

201

100K

1/20W

5%

R2995

1

2

17

25 36 37 72

100K

1/20W MF 201

5%

R2990

1

2

DFN1006H4-3

DMN32D2LFB4

Q2995

3

1

2

X7R-CERM

10% 50V

0.001UF

0402

C2991

1

2

SOT-563

DMN5L06VK-7

Q2945

3

5

4

13

TPS3895ADRY

USON

CRITICAL

U2990

5

1

2

3

4

6

1/20W

100K

201

MF

5%

R2992

1

2

0201-1

6.3V X5R

1.0UF

20%

C2903

1

2

20%

10UF

0402-1

CERM-X5R

6.3V

C2920

1

2

6.3V

CERM-X5R

0402-1

10UF

20%

C2921

1

2

20%

6.3V X5R

0201-1

1.0UF

C2904

1

2

20%

1.0UF

X5R

6.3V

0201-1

C2905

1

2

0201-1

6.3V X5R

1.0UF

20%

C2900

1

2

1.0UF

X5R

6.3V

20%

0201-1

C2901

1

2

0201-1

6.3V X5R

1.0UF

20%

C2902

1

2

20%

1.0UF

X5R

6.3V

0201-1

C2932

1

2

20%

1.0UF

X5R

6.3V

0201-1

C2931

1

2

20%

1.0UF

X5R

6.3V

0201-1

C2930

1

2

Thunderbolt Host (2 of 2)

SYNC_MASTER=J44

SYNC_DATE=08/12/2013

TBT_POC_RESET_L

TBTPOCRST_MR_L

SMC_DELAYED_PWRGD

PP3V3_S0

PP3V3_S4_TBT

TBTPOCRST_SENSE

TBT_PWR_REQ_L

PP3V3_S0

PP1V05_TBT

MIN_NECK_WIDTH=0.20 MM

MIN_LINE_WIDTH=0.50 MM

VOLTAGE=1.05V

PP3V3_S4_TBT

PP3V3_S4_TBT_F

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.20 MM

MIN_LINE_WIDTH=0.38 MM

PP1V05_TBTCIO

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.4 mm

MIN_LINE_WIDTH=0.50 MM

SWITCH_NODE=TRUE

DIDT=TRUE

MIN_NECK_WIDTH=0.20 MM

P1V05TBT_SW

MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM

PP3V3_TBTRDV

VOLTAGE=3.3V

PP1V05_TBTRDV

MIN_LINE_WIDTH=0.38 MM VOLTAGE=1.05V

MIN_NECK_WIDTH=0.20 MM

PP1V05_TBT

TBT_EN_CIO_PWR

TBT_EN_CIO_PWR_L

TBTPOCRST_CT

TBT_PWR_ON_POC_RST_L

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.3V

PP3V3_TBTLC

<SCH_NUM>

29 OF 120

24 OF 78

8

11

12 13 15 17 18 24 28 30

37 38 39 40 41 42 43 44 46 47

50 61 62 64 65 68 77

23 24 25 42 65

8

11

12 13 15 17 18 24 28 30

37 38 39 40 41 42 43 44 46 47

50 61 62 64 65 68 77

24

23 24 25 42 65

24

17 18 23 24 65

w w w . c h i n a f i x . c o m