8
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.
2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.
7
6 5 4 3
2 1
REV ECN
DESCRIPTION OF REVISION
CK
APPD
DATE
6
0001395489
ENGINEERING RELEASED
2012-03-13
SCHEM,MLB,J30
03/12/12
D
C
B
Sync
Date
02/15/2011
02/15/2011
03/26/2009
02/15/2011
02/15/2011
02/15/2011
02/15/2011
02/15/2011
02/15/2011
02/15/2011
02/15/2011
02/15/2011
02/15/2011
09/27/2011
02/15/2011
06/13/2011
06/13/2011
06/13/2011
06/13/2011
06/13/2011
06/13/2011
02/15/2011
06/13/2011
02/15/2011
09/19/2011
02/15/2011
02/15/2011
02/15/2011
02/15/2011
11/03/2011
06/13/2011
02/15/2011
02/15/2011
02/15/2011
02/15/2011
06/15/2011
02/15/2011
02/15/2011
06/23/2011
02/15/2011
11/08/2011
07/08/2011
07/08/2011
02/15/2011
12/21/2011
Page
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
(.csa)
50
SMC Support
51
LPC+SPI Debug Connector
52
SMBus Connections
53
Power Sensors: Load Side
54
Power Sensors: High Side
55
Thermal Sensors
56
Fan
57
WELLSPRING 1
58
WELLSPRING 2
59
Digital Accelerometer
61
SPI ROM
62
AUDIO: CODEC/REGULATOR
64
AUDIO: DETECT/MIC BIAS
65
AUDIO: HEADPHONE FILTER
66
AUDI0: SPEAKER AMP
67
AUDIO: JACK
68
AUDIO:Jack Translators
69
DC-In & Battery Connectors
70
PBus Supply & Battery Charger
71
System Agent Supply
72
5V/3.3V SUPPLY
73
1.5V DDR3 Supply
74
CPU IMVP7 & AXG VCore Regulator
75
CPU IMVP7 & AXG VCore Output
76
CPUVCCIO (1.05V) Power Supply
77
Misc Power Supplies
78
Power FETs
79
Power Control 1/ENABLE
90
LVDS CONNECTOR
93
DisplayPort/T29 A MUXing
94
Thunderbolt Connector A
97
LCD Backlight Driver
100
CPU Constraints
101
Memory Constraints
102
PCH Constraints 1
103
PCH Constraints 2
104
Ethernet/FW Constraints
105
T29 Constraints
106
SMC Constraints
108
Project Specific Constraints
109
PCB Rule Definitions
Contents
Sync
YONAS_J30
J31_MLB
K90I_MLB
LINDA_J30
YONAS_J30
YONAS_J30
K90I_MLB
J31_MLB
JACK_J30
K90I_MLB
K90I_MLB
KAVITHA_J30
DIRK_J30
KAVITHA_J30
KAVITHA_J30
DIRK_J30
DIRK_J30
JACK_J30
JACK_J30
JACK_J30
JACK_J30
JACK_J30
JACK_J30
JACK_J30
JACK_J30
JACK_J30
K90I_MLB
K90I_MLB
K90I_MLB
K90I_MLB
K90I_MLB
J31_MLB
K90I_MLB
K90I_MLB
K90I_MLB
K90I_MLB
K90I_MLB
K90I_MLB
K90I_MLB
K90I_MLB
K90I_MLB
Date
01/02/2012
06/15/2011
02/15/2011
09/28/2011
11/03/2011
08/01/2011
02/15/2011
07/01/2011
09/28/2011
02/15/2011
02/15/2011
07/25/2011
02/16/2012
07/25/2011
07/25/2011
11/10/2011
02/20/2012
07/29/2011
09/27/2011
09/28/2011
08/22/2011
07/28/2011
08/03/2011
07/28/2011
09/28/2011
07/28/2011
02/15/2011
02/15/2011
02/15/2011
02/15/2011
02/15/2011
07/08/2011
02/15/2011
02/15/2011
02/15/2011
02/15/2011
02/15/2011
02/15/2011
02/15/2011
02/15/2011
02/15/2011
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
(.csa)
1
1
2
3
4
5
6
7
8
9
Table of Contents
2
System Block Diagram
3
Revision History
4
Revision History
5
BOM Configuration
7
FUNC TEST
8
Power Aliases
9
Signal Aliases
10
CPU DMI/PEG/FDI/RSVD
11
CPU CLOCK/MISC/JTAG
12
CPU DDR3 INTERFACES
13
CPU POWER
14
CPU GROUNDS
16
CPU DECOUPLING-I
17
CPU DECOUPLING-II
18
PCH SATA/PCIe/CLK/LPC/SPI
19
PCH DMI/FDI/PM/Graphics
20
PCH PCI/USB/TP/RSVD
21
PCH GPIO/MISC/NCTF
22
PCH POWER
23
PCH GROUNDS
24
PCH DECOUPLING
25
CPU & PCH XDP
26
Chipset Support
27
USB HUB & MUX
28
CPU Memory S3 Support
29
DDR3 SO-DIMM Connector A
30
DDR3 Byte/Bit Swaps
31
DDR3 SO-DIMM Connector B
33
SD Card Connector
34
DDR3/FRAMEBUF VREF MARGINING
35
X19/ALS/CAMERA CONNECTOR
36
T29 Host (1 of 2)
37
T29 Host (2 of 2)
38
T29 Power Support
39
ETHERNET PHY (CAESAR IV)
40
Ethernet Connector
41
FireWire LLC/PHY (FW643E)
42
FireWire Port & PHY Power
43
FireWire Connector
45
SATA/IR/SIL Connectors
46
External A USB3 Connector
47
External B USB3 Connector
48
Front Flex Support
49
SMC
Contents
K90I_MLB
MASTER
K20A_MLB
K90I_MLB
K90I_MLB
K90I_MLB
K90I_MLB
K90I_MLB
MASTER
MASTER
MASTER
MASTER
MASTER
JACK_J30
MASTER
J31_MLB
J31_MLB
J31_MLB
J31_MLB
J31_MLB
J31_MLB
K90I_MLB
J31_MLB
K90I_MLB
LINDA_J30
K90I_MLB
K90I_MLB
K90I_MLB
K90I_MLB
YONAS_J30
J31_MLB
K90I_MLB
K90I_MLB
K90I_MLB
K90I_MLB
J31_MLB
K90I_MLB
K90I_MLB
K90I_MLB
K90I_MLB
YONAS_J30
J31_MLB
J31_MLB
K90I_MLB
YONAS_J30
D
C
B
Page
TABLE_TABLEOFCONTENTS_HEAD TABLE_TABLEOFCONTENTS_HEAD
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
A
Schematic / PCB #’s
PART NUMBER
051-9058
820-3115
DRAWING
TITLE=MLB
ABBREV=DRAWING
LAST_MODIFIED=Tue Mar 13 14:00:17 2012
QTY
1
1
DESCRIPTION
SCHEM,MLB,J30
PCBF,MLB,J30
REFERENCE DES
SCH
PCB
CRITICAL
CRITICAL
CRITICAL
BOM OPTION
SIZE
A
D
DRAWING TITLE
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
3
SCHEM,MLB,J30
Apple Inc.
R
DRAWING NUMBER
051-9058
REVISION
6.0.0
BRANCH
PAGE
1 OF 109
SHEET
1 OF 86
1245678
8 7 6 5 4 3
12
U1000
INTEL CPU
2.X GHz
IVY BRIDGE 2C-35W
PG 9-13
DDR3-1333/1600MHZ
D
GPIO
PG 19
U2600
SYSTEM
CLOCK
PG 24
J4501
SATA
CONN
HDD
PG 41
J4500
SATA
CONN
ODD
PG 41
U9390
MUX
PG 75
0
1
DP/TMDS
4 LANEs
U3600
CIO
PCIe x4
C
J9400
Display Port
/ T29
CONN
PG 76
1.05V/6GHZ.
1.05V/1.5GHZ.
T29 Host
PG 33,34
DP
J9000
LVDS
CONN
B
PG 74
BUFFER
PG 16
0
SATA
PG 16
1
eDP OUT
HDMI OUT
RGB OUT
DP OUT
DVI OUT
TMDS OUT
PG 17
LVDS OUT
PG 17
PG 18
PCI-E
PG 16
JTAG
PG 16
CLK
PCI
PEG
PG 16
FDI
PG 17
DMI
PG 17
INTEL
PANTHER POINT-MPCH
U1800
PG 16-21
PCI-E
(UP TO 8 LINES)
PG 16
2 3 1
PG 16
MISC
PG 19
SPI
PG 16
LPC
PG 16
PWR
CTRL
PG 17
USB
SMBUS
PG 16
HDA
PG 16
J2500
2 DIMMs
RTC
J3502
13
12
1011
8 9
6 70
543
21
(UP TO 14 DEVICES)
4
2 3
PG 18 PG 18
1
USB 3
XDP CONN
PG 23
J3100
PG 29
J2900
PG 27
DIMM
CAMERA
PG 32
DIMM’s
U6100
SPI
Boot ROM
PG 56
J3501
X19
Bluetooth
1 2 3
U2700
USB
HUB
PG 25
U4900
U5701
TP/KB
PSOC
From PCH
I2C
SMS ADC Ser
SMC
PG 45
J5800, J5713
J6900, J6950
DC/BATT
U5511
TEMP SENSOR
U5920
Sudden Motion Sensor
U5400,U5410,U5340,U5360,U5370,Q5480,Q5490
POWER SENSE
J5601
FAN CONN AND CONTROL
Fan
Prt
SPI
PG 63
PG 51
PG 55
PG 49, 50
PG 52
J5100
LPC+SPI Conn
Port80,serial
POWER SUPPLY
PG 63-73
PG 47
D
C
TRACKPAD/
PG 53PG 32
KEYBOARD
PG 54, 53
U4800
IR
Controller
PG 44 PG 41
U2760
USB
EHCI
MUX
XHCI
PG 25
J2550
J4501
IR
J4700
EXTERNAL B
USB 3
PG 43
J4600
EXTERNAL A
USB 3
PG 42
B
PCH XDP
CONN
PG 23
U6201
EXTMIC LINEIN HPOUT SPDIF MICIN LINEOUT
U4100
A
J3501
X19
AirPort
PG 32
FW643E
PG 38
J4310
FW800
CONN
PG 40
U3900
E-NET
BCM57765
PG 36
J4000
E-NET
CONN
PG 37
J3300
SD Card
CONN
PG 30
U6400
MIC BIAS
PG58
6 3
AUDIO
Codec
PG 57
J6700 J6701
AUDIO
CONNs
PG 61
U6610, U6620, U6630
SPEAKER
AMPs
PG 60
J6702
J6703
SYNC_MASTER=MASTER
PAGE TITLE
System Block Diagram
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
SYNC_DATE=02/15/2011
DRAWING NUMBER
051-9058
REVISION
6.0.0
BRANCH
PAGE
2 OF 109
SHEET
2 OF 86
124578
SIZE
A
D
8 7 6 5 4 3
12
R6905
Q5300
V
PP5V_S3_REG
PP3V3_S5_REG
D6990
R5400
A
22
PP3V3_S5
8
PP3V3_ENET
Q7922
PM_SLP_S3_L&&WOL_EN||SMC_ADAPTER_EN//WOL_EN
R7803
Q7800
P3V3S4_EN
Q7810
P3V3S3_EN
Q7820
P5V_3V3_SUS_EN
Q7830
PM_SLP_S3_L_R
2
15
PP5V_S0_CPUVCCIOS0
CPUVCCIOS0_EN
21
24
CPUIMVP_VR_ON
DDRREG_EN
DDRVTT_EN
PP5V_S0_FET
PVCCSA_EN
CPU_VCCSA_VID<1>
CPU_VCCSA_VID<0>
14
BCM57765
EN
U3900
CAESAR IV
(PAGE 36)
PP3V3_S4_FET
PP3V3_S3
PP3V3_SUS_FET
TPS720105
U7740
(PAGE 71)
14
VCC
EN
VR_ON
Q7860
P5VS0_EN
Q4590
ODD_PWR_EN_L
12
14
10-3
PP1V05_SUS_LDO
ENABLE
3.425V G3HOT
PM6640
U6990
(PAGE 63)
1.05V
ISL95870
U7600
(PAGE 70)
VIN
CPU VCORE
MAX15119GTM
U7400
(PAGE 68)
1.5V
S5
S3
0.75V
TPS51916
U7300
(PAGE 67)
VCC
EN
ISL95870A
VID0
VID1
(PAGE 65)
PP5V_S0_FET
PP5V_SW_ODD
PP1V2_ENET_PHY
VOUT
PGOOD
VOUT
VOUT
PGOOD
PGOODG
VLDOIN
VIN
VOUT1
VOUT2
PGOOD
VOUT
U7100
PGOOD
15
P1V8_S0_EN
17
P1V5S0_EN
9
19
PP3V3_FW_P3V3FWFET
PP3V42_G3H_REG
R7640
A
CPUVCCIOS0_PGOOD
CPUIMVP_PGOOD
CPUIMVP_AXG_PGOOD
PPDDR_S3_REG
PPVTT_S0_DDR_LDO
DDRREG_PGOOD
PP1V5S0FET_GATE
PPVCCSA_S0_REG
PVCCSA_PGOOD
PP5V_S0_VMON
PP1V5_S3RS0_VMON
PP1V05_S0_VMON
PP3V3_S0
16
MAX15053EWL
EN
U7760
(PAGE 71)
TPS62201
EN
U7770
(PAGE8 71)
TPS22924
EN
U4201
(PAGE 39)
PPCPUVCCIO_S0_REG
SMC_CPU_FSB_ISENSE
22-1
R5320
SMC_CPU_VSENSE
V
PPVCORE_S0_CPU_REG
R5330
SMC_GFX_VSENSE
V
PPVCORE_S0_AXG_REG
25-1
26-1
Q7801
PP1V5_S3RS0_FET
23
23-1
PP3V3_S0_VMON
VMON_Q2
ISL88042IRTEZ
VMON_Q3
VMON_Q4
(PAGE 73)
PP1V8_S0_REG
PP1V5_S0_REG
PP3V3_FW_FE5T
3
16
U7960
P1V05_S0_LDO_EN
SMC PWRGD
SN0903048
(PAGE 44)
22
18
EN
20
U5010
25
26
CPUIMVP_AXG_PGOOD
P1V8S0_PGOOD
P5V3V3_PGOOD
CPUVCCIOS0_PGOOD
PVCCSA_PGOOD
ALL_SYS_PWRGD
TPS720105
U7780
(PAGE 71)
PP1V05_S0_LDO
SMC_RESET_L
TPS22924
U4202
(PAGE 39)
EN
FW_PWR_EN
RSMRST_PWRGD
SMC_ONOFF_L
4
PP1V0_FW_FWPHY
COUGAR-POINT
(PCH)
SYS_RERST#
27
U2850
25
9
5
PM_SLP_S5_L
PM_SLP_S4_L
PM_SLP_S3_L
19
SYNC_MASTER=K20A_MLB
PAGE TITLE
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
U1800
PM_PCH_PWRGD
(PAGE 16~21)
SM_DRAMPWROK
CPU
U1000
UNCOREPWRGOOD
(PAGE 9~13)
SMC
PWRGD(P12)
RSMRST_IN(P13)
PWR_BUTTON(P90)
SLP_S5_L(P95)
SLP_S4_L(P94)
SLP_S3_L(P93)
U4900
(PAGE 43)
RSMRST_OUT(P15)
99ms DLY
IMVP_VR_ON(P16)
Revision History
Apple Inc.
R
PWRBTN#
RSMRST#
PLTRST#
PROCPWRGD
DRAMPWROK
RESET*
SYSRST(PA2)
P17(BTN_OUT)
RES*
PM_PWRBTN_L
PM_SYSRST_L
PM_RSMRST_L
PM_DSW_PWRGD
PLT_RERST_L
CPU_PWRGD
PM_MEM_PWRGD
30
PM_DSW_PWRGD
PM_RSMRST_L
CPUIMVP_VR_ON
PM_SYSRST_L
PM_PWRBTN_L
SMC_RESET_L
29
28
10
12
DRAWING NUMBER
REVISION
BRANCH
PAGE
SHEET
124578
26
6-1
4
SYNC_DATE=03/26/2009
051-9058
6.0.0
3 OF 109
3 OF 86
SIZE
D
C
B
A
D
J30 POWER SYSTEM ARCHITECTURE
PPDCIN_G3H
V
1
R7020
A
SMC_RESET_L
VIN
BATTERY CHARGER
Q7055
CHGR_BGATE
U7000
ISL6259HRTZ
PBUS SUPPLY/
(PAGE 63)
D
J6900
AC
ADAPTER
DCIN(16.5V)
F6905
6A FUSE
IN
J6950
PPVBATT_G3H_CONN
3S2P
(9 TO 12.6V)
Q5310
SMC_DCIN_ISENSE
R6990
VOUT
PPVBAT_G3H_CHGR_R
PPVBAT_G3H
R7050
SMC_BATT_ISENSE
PPDCIN_S5_P3V42G3H
F7040
1
A
PPBUS_G3H
C
SMC
U4900
P60
(PAGE 44)
SLP_S5#(E4)
COUGAR-POINT
(PCH)
B
A
U1800
(PAGE 16~21)
RC
DELAY
RC
DELAY
RC
DELAY
RC
DELAY
SLP_S4#(H4)
SLP_S3#(F4)
1V05_S0_LDO_EN
CPUVCCIOS0_EN
PVCCSA_EN
P1V5S0_EN
P1V8S0_EN
SMC_PM_G2_EN
SLP_SUS
PM_SLP_S3_L_R
21
21
22
19
17
6
R7916
PM_SLP_S5_L
R7917
RC
DELAY
RC
DELAY
R7978
P5VS0_EN
P3V3S0_EN
PBUSVSENS_EN
RC
DELAY
P3V3S4_EN
P5V_3V3_SUS_EN
P5VS3_EN
DDRREG_EN
P3V3S3_EN
PM_SLP_S4_L
PM_SLP_S3_L
PG73
P3V3S5_EN
PG73
PG 17
PG73
PG73
PG73
PG 17
PG 17
14-1
14-1
14-1
7
11
11
10-1
PG73
13-1
15
13-2
13
14
F9700
LCD_BKLT_EN
BKLT_PLT_RST_L
&&
PPBUS_SW_LCDBKLT_PWR
Q4260
FWP5ORT_PWR_EN
T29_A_HV_EN
www.qdzbwx.com
R5410
A
13
Q9706
VIN
LP8550
U9701
EN
(PAGE 76)
Q3880
PPBUS_S5_HS_OTHER_ISNS
P5VS3_EN_L
P3V3S5_EN_L
7
PP5V_S5_LDO
PPVOUT_SW_LCDBKLT
VOUT
F4260
LT3957
U3890
(PAGE 35)
PPBUS_FW_FET
VIN
VOUT
EN1
EN2
VREG5
P5V_3V3_SUS_EN
PP15V_T29_REG
VIN
5V
(L/H)
3.3V
(R/H)
TPS51125
U7200
(PAGE 66)
PGOOD
P5V3V3_PGOOD
Q7840
VOUT1
VOUT2
14-1
PP5V_SUS_FET
10-2
6 3
PROTO:
8 7 6 5 4 3
12
D
C
D
C
SIZE
B
A
D
B
A
6 3
SYNC_MASTER=K90I_MLB SYNC_DATE=02/15/2011
PAGE TITLE
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
Revision History
Apple Inc.
R
DRAWING NUMBER
051-9058
REVISION
6.0.0
BRANCH
PAGE
4 OF 109
SHEET
4 OF 86
124578
8 7 6 5 4 3
12
BOM Variants
BOM NUMBER
607-8895
085-3092
607-8721
607-8722
607-8723
D
607-9309
607-9310
607-9311
639-3752
639-3756
639-3753
639-3755
639-3751
639-3754
C
J30 BOM GROUPS
BOM GROUP
J30_COMMON
J30_COMMON1
J30_COMMON2
J30_PROGPARTS
J30_DEVEL:ENG BKLT:ENG,XDP_CONN,XDP_CPU:BPM,XDP_PCH,LPCPLUS_CONN:YES,LOADISNS:YES,DDRVREF_DAC,S0PGOOD_ISL
J30_DEVEL:PVT
J30_DEBUG:ENG
J30_DEBUG:PVT
J30_DEBUG:PROD
Module Parts
PART NUMBER
337S4113
B
337S4264
337S4265
337S4269
343S0534
338S0753
338S1072 CRITICAL
353S3055 CRITICAL
946-3827
516S0806
516-0246 CRITICAL
516S0805 CRITICAL SODIMM:MOLEX
516-0245 SODIMM:MOLEXCRITICAL
516S0805
516-0246
BOM NAME
CMN PTS,PCBA,MLB,J30
J30 MLB DEVELOPMENT BOM
POWER FETS PAIR,FAIRCHILD,DDR,J30
POWER FETS PAIR,FAIRCHILD,5V_S3,J30
POWER FETS PAIR,FAIRCHILD,PBUS_CHARGER,J30
POWER FETS PAIR,RENESAS,DDR,J30
POWER FETS PAIR,RENESAS,5V_S3,J30
POWER FETS PAIR,RENESAS,PBUS_CHARGER,J30
PCBA,MLB,MOL,2.9G,J30
PCBA,MLB,HYB,2.9G,J30
PCBA,MLB,FOX,2.5G,J30
PCBA,MLB,HYB,2.5G,J30
PCBA,MLB,MOL,2.5G,J30
PCBA,MLB,FOX,2.9G,J30
ALTERNATE,COMMON,J30_COMMON1,J30_COMMON2,J30_DEBUG:ENG,J30_PROGPARTS,T29BST:Y,TBTHV:P15V
BATT_3S,CPUMEM_S0,USBHUB2513B,HUB_3NONREM,T29:YES,SDRV_PD,SDRVI2C:MCU,AXG_PHASE1,BTPWR:S4,UV_GLUE_J30
BOOTROM_PROG,SMC_PROG,TPAD_PROG,ENET_PROG,T29ROM:PROG,T29MCU:PROG
DEVEL_BOM,BKLT:PROD,MOJO:YES,XDP,LPCPLUS_R:YES,VREFDQ:M1_M3,VREFCA:LDO,USBHUB2514B
BKLT:PROD,MOJO:YES,XDP,LPCPLUS_R:YES,LOADISNS:NO,VREFDQ:M1_M3,VREFCA:LDO,USBHUB2513B
QTY
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
DESCRIPTION
IC,IVB,2C,35W,1023BGA
IVB,S R0N0,PRQ,L1,2.5,35W,2+2,1.1,3M,BGA
IVB,S R0MU,PRQ,L1,2.9,35W,2+2,1.25,4M,BGA
PANTHERPOINT,C1,SLJ8C,PRQ,BD82HM77
IC,BCM57765B0,ENET&SD,8X8
IC,FW643E,1394B PHY/OHCI LINK/PCI-E,12
IC,T29,PRQ,S LJJY,FCBGA,15x15MM,C1
IC,PI3VEDP212,X2 DISPLAYPORT 2:1 MUX,QFN
J30 MLB DYMAX ADHESIVE 29993-SC 0.48G
CONN,204P,SODIMM,SOCKET,DDR3,RAM,BGA,FOXCONN
CONN,204P,SODIMM,DDR3,P=0.6MM,FOXCONN
CONN,204P,SODIMM,SOCKET,DDR3,RAM,BGA,MOLEX
CONN,204P,SODIMM,DDR3,P=0.6MM,MOLEX
CONN,204P,SODIMM,SOCKET,DDR3,RAM,BGA,MOLEX
CONN,204P,SODIMM,DDR3,P=0.6MM,FOXCONN
BOM OPTIONS
J30_COMMON,FET_PAIR
J30_DEVEL:ENG
DDR_POWER_FET:FAIR
5V_S3_POWER_FET:FAIR
CHARGER_POWER_FET:FAIR
DDR_POWER_FET:REN
5V_S3_POWER_FET:REN
CHARGER_POWER_FET:REN
J30_CMNPTS,CPU_2_9GHZ,SODIMM:MOLEX,EEEE_F1YK
J30_CMNPTS,CPU_2_9GHZ,SODIMM:HYBRID,EEEE_F1YH
J30_CMNPTS,CPU_2_5GHZ,SODIMM:FOXCONN,EEEE_F1YL
J30_CMNPTS,CPU_2_5GHZ,SODIMM:HYBRID,EEEE_F1YJ
J30_CMNPTS,CPU_2_5GHZ,SODIMM:MOLEX,EEEE_F1YM
J30_CMNPTS,CPU_2_9GHZ,SODIMM:FOXCONN,EEEE_F1YG
BOM OPTIONS
MIKEY,TPAD:Z2,RAMCFG_SLOT
LPCPLUS_CONN:YES,XDP_CONN
DEVEL_BOM,MOJO:YES,XDP,LPCPLUS_R:YES,VREFDQ:M1_M3,VREFCA:LDO_DAC
REFERENCE DES
U1000
U1000
U1000
U1800
U3900
U4100
U3600
U9390
UV_GLUE_J30
J3100
J2900
J3100
J2900
J3100
J2900
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
BOM OPTION
CPU_IVB_2C
CPU_2_5GHZ
CPU_2_9GHZ
UV_GLUE_J30
SODIMM:FOXCONN
SODIMM:FOXCONN
SODIMM:HYBRID
SODIMM:HYBRID
T29:YES
TABLE_BOMGROUP_HEAD
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_HEAD
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
Bar Code Labels / EEEE #’s
PART NUMBER
826-4393
826-4393
826-4393
826-4393
826-4393
QTY
1
1
1
1
1
1
DESCRIPTION
LBL,P/N LABEL,PCB,28MM X 6 MM
LBL,P/N LABEL,PCB,28MM X 6 MM
LBL,P/N LABEL,PCB,28MM X 6 MM
LBL,P/N LABEL,PCB,28MM X 6 MM
LBL,P/N LABEL,PCB,28MM X 6 MM
LBL,P/N LABEL,PCB,28MM X 6 MM
REFERENCE DES
[EEEE:F1YG]
[EEEE:F1YH]
[EEEE:F1YJ]
[EEEE:F1YK]
[EEEE:F1YL]
[EEEE:F1YM]
Programmable Parts
PART NUMBER
335S0862
341S3096
335S0550
341S3430
337S3997 CRITICAL
341S3365 CRITICAL
338S1098
341S3300 CRITICAL
335S0807
335S0812
341S3558
341S2384
341S3522
QTY
1
1
1
1
1
1
1
1
1
1
1
1
1
DESCRIPTION
IC,FLASH,SERIAL,SPI,!MBIT,2V7,REV F
IC ENET,1!MBITFLAH,CIV REV01,K9x
IC,EEPROM,SERIAL,SPI,4Kx8,1.8V,MLP8,LF
IC,T29 EEPROM,LR,J30/J31
IC,MCU,32B,LPC1112A,16KB/2KB,HVQFN25
IC,PROGRMD,T29,PORT MCU,K90IA,K91A,K92A
IC,SMC12-A3,40MHZ/50DMIPS MCU,9x9,157BGA
IC,SMC,EXTERNAL,FSB,A3,J30
IC,SPI SRL 50MHZ FLASH,64MBT,8SOP,FUSE=1
64 MBIT SPI SRL DUAL I/O FLSH,SOIC8
IC,EFI,V00C7,J30/J31
IR,ENCORE II, CY7C63803-LQXC
IC,PSOC,TP/KB,J30/J31
Alternate Parts
PART NUMBER
138S0603
128S0303 128S0353 138S0648
138S0676 138S0691
152S0778
376S0855
376S0977 376S0859
376S0972
376S0777
376S0953
377S0107
371S0709
607-9310
607-9311
ALTERNATE FOR
PART NUMBER
138S0602
157S0084
152S0693
376S1032
376S1017
376S0845376S0937
376S0761
376S0958376S0957
376S0958
377S0126
371S0652
514-0671514-0788
607-8722
607-8723
BOM OPTION
REF DES
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
COMMENTS:
Murata alt to Samsung
Delta alt to TDK Magnetics157S0058
Panasonic alt to Sanyo
Murata alt to Samsung
Cyntec alt to Vishay
Diodes alt to Toshiba
Diodes alt to Toshiba
Rohm alt to Toshiba
Fairchild alt to Renesas
AON alt to Siliconix
Fairchild alt to Fairchild
Fairchild alt to Renesas
ONsemi alt to Semtech
NXP alt to Infineon
Acon(w liteon) alt to Acon
Renesas alternate to fairchild
Renesas alternate to fairchild
REFERENCE DES
U3990
U3990
U3690
U3690
U9330
U9330
U4900
U4900
U6100
U6100
U6100
U4800
U5701
TABLE_ALT_HEAD
PART NUMBER
TABLE_ALT_ITEM
152S1499
TABLE_ALT_ITEM
152S1493
TABLE_ALT_ITEM TABLE_ALT_ITEM
138S0652
TABLE_ALT_ITEM
TABLE_ALT_ITEM
152S1512
TABLE_ALT_ITEM
152S1019
TABLE_ALT_ITEM
376S1023 376S0960
TABLE_ALT_ITEM
353S3312
TABLE_ALT_ITEM
353S3238
TABLE_ALT_ITEM
353S3519
TABLE_ALT_ITEM
TABLE_ALT_ITEM
138S0681
TABLE_ALT_ITEM
138S0671
TABLE_ALT_ITEM
TABLE_ALT_ITEM
377S0124
TABLE_ALT_ITEM
341S3492
TABLE_ALT_ITEM
376S1053
376S1076
CRITICAL
CRITICAL826-4393
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
ALTERNATE FOR
PART NUMBER
152S0864
152S1300
138S0660138S0684
152S1295
152S1271
353S3055
353S1428
353S2179
155S0367155S0578
138S0638
138S0673
376S0796376S0903
377S0057
341S3096
376S0604
376S0634
BOM OPTION
EEEE_F1YG
EEEE_F1YH
EEEE_F1YJ
EEEE_F1YK
EEEE_F1YL
EEEE_F1YM
BOM OPTION
ENET_BLANK
ENET_PROG
T29ROM:BLANK
T29ROM:PROG
T29MCU:BLANK
T29MCU:PROG
SMC_BLANK
BOOTROM_BLANK
BOOTROM_BLANK
BOOTROM_PROG
TPAD_PROG
BOM OPTION
SMC_PROG
REF DES
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
COMMENTS:
Coilcraft alt to Murata
Coilcraft alt to Murata
Samsung/Murata alt to Taiyo
Murata alt to Taiyo
Cyntec alt to NEC
Cyntec alt to TOKO
Siliconix alt to Renesas
NXP alt to Pericom
Intersil alt to TI
Intersil alt to TI
Taiyo alt to Murata
Taiyo alt to Samsung
Taiyo alt to Murata
Fairchidl alt to Vishay
Amotech alt to Tdk
Numonix alt to Atmel (ENET ROM)
Diodes alt to fairchild
Diodes alt to onsemi
D
C
TABLE_ALT_HEAD
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
B
Sub BOM
A
PART NUMBER
607-8895
607-8721
607-8722
607-8723 CSET3 CRITICAL
QTY
1
1
1
1
1
DESCRIPTION
J30 MLB DEVELOPMENT
CMN PTS,PCBA,MLB,J30
POWER_FETS PAIR,FAIRCHILD,DDR,J30
POWER_FETS PAIR,FAIRCHILD,5V_S3,J30
POWER_FETS PAIR,FAIRCHILD,PBUS_CHARGER,J30
6 3
REFERENCE DES
DEVEL
CMNPTS
CSET2 CRITICAL
CRITICAL
CRITICAL085-3092
CRITICAL
CRITICAL
BOM OPTION
DEVEL_BOM
J30_CMNPTS
FET_PAIRCSET1
FET_PAIR
FET_PAIR
PAGE TITLE
BOM Configuration
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
SYNC_DATE=02/15/2011SYNC_MASTER=K90I_MLB
DRAWING NUMBER
051-9058
REVISION
6.0.0
BRANCH
PAGE
5 OF 109
SHEET
5 OF 86
124578
SIZE
A
D
8 7 6 5 4 3
12
NC_EDP_TXP<0..3>
Functional Test Points
NC NO_TESTs
Fan Connectors
I12
I15
I16
D
I554
I553
I555
TRUE
TRUE
TRUE
MIC FUNC_TEST
TRUE
TRUE
TRUE
PP5V_S0
FAN_RT_PWM
FAN_RT_TACH
(NEED TO ADD 1 GND TP)
BI_MIC_LO
BI_MIC_HI
BI_MIC_SHIELD
(NEED TO ADD 1 GND TP)
6 7
52
52
61 62
61 62
61 62
SPEAKER FUNC_TEST
I227
I226
I228
I230
I229
I231
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
SPKRAMP_L_N_OUT
SPKRAMP_L_P_OUT
SPKRAMP_R_N_OUT
SPKRAMP_R_P_OUT
SPKRAMP_SUB_N_OUT
SPKRAMP_SUB_P_OUT
60 61 85
60 61 85
60 61 85
60 61 85
60 61 85
60 61 85
LVDS FUNC_TEST
I259
I258
I260
I407
C
I262
I261
I256
I257
I255
I252
I253
I254
I250
I251
I313
I246
I247
I248
I249
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
PP3V3_LCDVDD_SW_F
PP3V3_S0_LCD_F
PPVOUT_SW_LCDBKLT
LVDS_DDC_CLK
LVDS_DDC_DATA
LVDS_IG_A_DATA_N<0>
LVDS_IG_A_DATA_P<0>
LVDS_IG_A_DATA_N<1>
LVDS_IG_A_DATA_P<1>
LVDS_IG_A_DATA_N<2>
LVDS_IG_A_DATA_P<2>
LVDS_CONN_A_CLK_F_N
LVDS_CONN_A_CLK_F_P
LED_RETURN_1
LED_RETURN_2
LED_RETURN_3
LED_RETURN_4
LED_RETURN_5
LED_RETURN_6
(NEED TO ADD 5 GND TP)
(NEED 2 TP)
(NEED 2 TP)
6
74
6
74
74 77
8
74
8
74
17 74 80
17 74 80
17 74 80
17 74 80
17 74 80
17 74 80
74 85
74 85
74 77
74 77
74 77
74 77
74 77
74 77
SATA ODD CONN
I264
I268
I269
I267
B
I265
I266
I628
I627
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
PP5V_SW_ODD
SMC_ODD_DETECT
SATA_ODD_D2R_C_P
SATA_ODD_D2R_C_N
SATA_ODD_R2D_P
SATA_ODD_R2D_N
SMC_SSD_TEMP_CTL_R
HDD_OOB_TEMP
(NEED TO ADD 3 GND TP)
(NEED 2 TP)
41 45
41 85
41 85
41 80
41 80
6
41
SATA HDD/IR/SIL
I319
I314
I315
I318
I317
I307
I309
I625
I311
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
PP5V_S0_HDD_FLT
SATA_HDD_R2D_P
SATA_HDD_R2D_N
SATA_HDD_D2R_C_P
SATA_HDD_D2R_C_N
SYS_LED_ANODE_R
IR_RX_OUT
SMC_SSD_THROTTLE_R
PP5V_S3_IR_R
(NEED TO ADD 3 GND TP)
(NEED 2 TP)
41 80
41 80
41 80
41 80
41
41 44
41
6
41
BATT POWER CONN
I322
I321
I320
A
I305
TRUE
TRUE
TRUE
TRUE
SMBUS_SMC_5_G3_SCL
SMBUS_SMC_5_G3_SDA
SYS_DETECT_L
PPVBAT_G3H_CONN
(NEED TO ADD 5 GND TP)
(NEED 5 TP)
6
45 48 84
6
45 48 84
63
63 64
BIL CONN
I326
I323
I324
I325
I308
TRUE
TRUE
TRUE
TRUE
TRUE
PP3V42_G3H
SMBUS_SMC_5_G3_SCL
SMBUS_SMC_5_G3_SDA
SMC_BIL_BUTTON_L
SMC_LID_R
(NEED TO ADD 2 GND TP)
6 7
6
45 48 84
6
45 48 84
45 46 63
63
I303
I301
I302
I300
I299
I298
I293
I288
I292
I295
I290
I271
I289
I595
I594
I593
I375
I374
I372
I370
I371
I369
I368
I361
I366
I365
I363
I364
I362
I360
I359
I357
I358
I377
I564
I626
I354
I355
I344
I345
I346
I347
I349
I348
I350
I352
I351
I353
I327
I328
I329
I343
I342
I341
I339
I340
I338
I336
I337
I333
I335
I334
I332
I330
I331
I356
I394
I408
I409
I410
I297
I294
X19 CONN
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
PP3V3_WLAN
PCIE_AP_D2R_PI_P
PCIE_AP_D2R_PI_N
PCIE_AP_R2D_P
PCIE_AP_R2D_N
PCIE_CLK100M_AP_CONN_P
PCIE_CLK100M_AP_CONN_N
PP3V3_S3RS4_BT_F
PCIE_WAKE_L
USB_BT_CONN_P
USB_BT_CONN_N
AP_CLKREQ_Q_L
AP_RESET_CONN_L
AP_TEMP_SMB_SDA_R
AP_TEMP_SMB_SCL_R
WIFI_EVENT_L_R
(NEED TO ADD 5 GND TP)
IPD_FLEX_CONN
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
PP3V3_S4
PP18V5_Z2
Z2_CS_L
Z2_DEBUG3
Z2_MOSI
Z2_MISO
Z2_SCLK
Z2_BOOST_EN
Z2_HOST_INTN
Z2_CLKIN
Z2_KEY_ACT_L
Z2_RESET
PSOC_MISO
PSOC_MOSI
PSOC_SCLK
SMBUS_SMC_2_S3_SCL
SMBUS_SMC_2_S3_SDA
PSOC_F_CS_L
PICKB_L
PP5V_S5_CUMULUS
(NEED TO ADD 2 GND TP)
KEYBOARD CONN
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
PP3V3_S4
PP3V42_G3H
WS_KBD1
WS_KBD2
WS_KBD3
WS_KBD4
WS_KBD5
WS_KBD6
WS_KBD7
WS_KBD8
WS_KBD9
WS_KBD10
WS_KBD11
WS_KBD12
WS_KBD13
WS_KBD14
WS_KBD15_CAP
WS_KBD16_NUM
WS_KBD17
WS_KBD18
WS_KBD19
WS_KBD20
WS_KBD21
WS_KBD22
WS_KBD23
WS_KBD_ONOFF_L
WS_LEFT_SHIFT_KBD
WS_LEFT_OPTION_KBD
WS_CONTROL_KBD
KBD BACKLIGHT CONN
TRUE
TRUE
KBDLED_ANODE
SMC_KDBLED_PRESENT_L
CAMERA/ALS CONN
TRUE
TRUE
TRUE
TRUE
TRUE
PP5V_S3_ALSCAMERA_F
SMBUS_SMC_2_S3_SCL
SMBUS_SMC_2_S3_SDA
USB_CAMERA_CONN_P
USB_CAMERA_CONN_N
(NEED 3 TP)
(NEED TO ADD 2 GND TP)
(NEED TO ADD 1 GND TP)
(NEED TO ADD 2 GND TP)
6
32 46
32 81
32 81
32 81
32 81
32 85
32 85
32
17 24 32
32 80
32 80
32
32
32
32
32
6 7
6
54
53 54
53 54
53 54
53 54
53 54
54
53 54
53 54
53 54
53 54
53 54
53 54
53 54
6
45 48 84
6
45 48 84
53 54
53 54
54
6 7
6 7
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
54
54
32
6
45 48 84
6
45 48 84
32 80
32 80
I287
I285
I414
I280
I281
I282
I283
I376
I278
I270
I416
I273
I274
I275
I417
I392
I391
I390
I388
I418
I386
I383
I419
I382
I565
I380
I598
I597
I596
I599
I600
I601
I602
I603
I604
I605
I606
I607
I608
I610
I611
I612
I614
I613
I617
I616
I618
I620
I619
I622
DEBUG VOLTAGE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
DC POWER CONN
I312
I304
TRUE
TRUE
PPVCORE_S0_CPU
PPVCORE_S0_AXG
PP1V2_S3_ENET_INTREG
PP1V05_S0
PP1V5_S3RS0
PP1V8_S0
PP3V3_S0
PP5V_S0
PP3V3_S3
PP5V_S3
PPVCCSA_S0_CPU
PP3V3_S5
PP3V42_G3H
PPBUS_G3H
PP3V3_ENET
PP3V3_WLAN
PP5V_SW_ODD
PP5V_S0_HDD_FLT
PP18V5_Z2
PP3V3_S0_LCD_F
PP3V3_LCDVDD_SW_F
PP4V5_AUDIO_ANALOG
PP1V5_S3
SMC_PM_G2_EN
PM_SLP_S4_L
PM_SLP_S3_L
(NEED TO ADD 6 GND TP)
(NEED 3 TP)
PP18V5_DCIN_FUSE
ADAPTER_SENSE
(NEED TO ADD 4 GND TP)
7
7
71
7
7
85
7
7
85
6 7
7
7
7
16
7
85
16
6 7
16
7
7
6
32 46
6
41
6
41
6
54
6
74
6
74
57 62
7
45 73
17 26 32 45 73
8
17 26 45 73
63
63
18
18
LPC+SPI DEBUG_CONN
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
LPC_AD<0>
LPC_AD<1>
LPC_AD<2>
LPC_AD<3>
LPC_CLK33M_LPCPLUS
LPC_FRAME_L
LPC_PWRDWN_L
LPC_SERIRQ
LPCPLUS_GPIO
LPCPLUS_RESET_L
PM_CLKRUN_L
PP3V42_G3H
PP5V_S0
SMC_RX_L
SMC_TCK
SMC_TDI
SMC_TDO
SMC_TMS
SMC_TX_L
SPI_ALT_CLK
SPI_ALT_CS_L
SPI_ALT_MISO
SPI_ALT_MOSI
SPIROM_USE_MLB
(NEED TO ADD 2 GND TP)
16 45 47 81
16 45 47 81
16 45 47 81
16 45 47 81
24 47 81
16 45 47 81
17 45 47
16 45 47
19 47
24 47
17 45 47
6 7
6 7
45 46 47
45 46 47
45 46 47
45 46 47
45 46 47
45 46 47
47
47
47
47
19 47 56
TP_SDVO_TVCLKINN
17
TP_SDVO_TVCLKINP
17
TP_SDVO_STALLN
17
TP_SDVO_STALLP
17
TP_SDVO_INTN
17
TP_SDVO_INTP
17
NO_TEST
TP_CRT_IG_BLUE
17
TP_CRT_IG_GREEN
17
TP_CRT_IG_RED
17
TP_CRT_IG_DDC_CLK
17
TP_CRT_IG_DDC_DATA
17
TP_CRT_IG_HSYNC
17
TP_CRT_IG_VSYNC
17
TP_LVDS_IG_CTRL_CLK
17
TP_LVDS_IG_CTRL_DATA
17
TP_PCH_LVDS_VBG
17
TP_HDA_SDIN2
TP_HDA_SDIN3
TP_PCI_PME_L
TP_PCI_CLK33M_OUT3
TP_CLINK_CLK
16
TP_CLINK_DATA
16
TP_CLINK_RESET_L
16
TP_PCIE_CLK100M_PEBN
16
TP_PCIE_CLK100M_PEBP
16
TP_FW643_SDA
38
TP_FW643_SM
38
TP_FW643_TCK
38
TP_FW643_TMS
38
TP_FW643_FW620_L
38
TP_FW643_VBUF
38
TP_FW643_OCR10_CTL
38
TP_FW643_AVREG
38
TP_FW643_TDI
38
TP_XDP_PCH_OBSFN_A<0..1>
23
TP_XDP_PCH_OBSFN_B<0..1>
23
TP_XDPPCH_HOOK2
23
TP_XDPPCH_HOOK3
23
TP_XDP_PCH_OBSFN_D<0..1>
23
TP_XDP_PCH_HOOK4
23
TP_XDP_PCH_HOOK5
23
TP_PCH_GPIO64_CLKOUTFLEX0
16
TP_PCH_GPIO65_CLKOUTFLEX1
16
TP_PCH_GPIO66_CLKOUTFLEX2
16
TP_PCH_GPIO67_CLKOUTFLEX3
16
I500
I499
I498
I497
I495
I496
I494
I493
I492
I491
I581
I580
I582
I583
I584
I585
I586
I588
I587
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
NO_TEST
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
NC NO_TESTs
NC_FW2_TPBP
NC_FW2_TPBN
NC_FW2_TPBIAS
NC_FW2_TPAP
NC_FW2_TPAN
NC_FW0_TPBP
NC_FW0_TPBN
NC_FW0_TPAP
XDP_PCH_AP_PWR_EN
XDP_PCH_USB_HUB_SOFT_RST_L
XDP_PCH_SDCONN_STATE_RST_L
XDP_PCH_ENET_PWR_EN
XDP_PCH_SDCONN_DET_L
XDP_PCH_S5_PWRGD
XDP_PCH_PWRBTN_L
XDP_PCH_ISOLATE_CPU_MEM_L
XDP_FW_CLKREQ_L
XDP_AP_CLKREQ_L
XDP_PCH_AUD_IPHS_SWITCH_EN
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
NC_LVDS_IG_CTRL_CLK
TRUE
MAKE_BASE=TRUE
NC_LVDS_IG_CTRL_DATA
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
NC_CRT_IG_BLUE
NC_CRT_IG_GREEN
NC_CRT_IG_RED
NC_CRT_IG_DDC_CLK
NC_CRT_IG_DDC_DATA
NC_CRT_IG_HSYNC
NC_CRT_IG_VSYNC
NC_PCH_LVDS_VBG
NC_HDA_SDIN1TP_HDA_SDIN1
NC_HDA_SDIN2
NC_HDA_SDIN3
NC_PCI_PME_L
NC_PCI_CLK33M_OUT3
NC_CLINK_CLK
NC_CLINK_DATA
NC_CLINK_RESET_L
NC_PCIE_CLK100M_PEBN
NC_PCIE_CLK100M_PEBP
NC_FW643_SDA
NC_FW643_SM
NC_FW643_TCK
NC_FW643_TMS
NC_FW643_FW620_L
NC_FW643_VBUF
NC_FW643_OCR10_CTL
NC_FW643_AVREG
NC_FW643_TDI
NC_TP_XDP_PCH_OBSFN_A<0..1>
NC_TP_XDP_PCH_OBSFN_B<0..1>
NC_TP_XDPPCH_HOOK2
NC_TP_XDPPCH_HOOK3
NC_TP_XDP_PCH_OBSFN_D<0..1>
NC_TP_XDP_PCH_HOOK4
NC_TP_XDP_PCH_HOOK5
NC_PCH_GPIO64_CLKOUTFLEX0
NC_PCH_GPIO65_CLKOUTFLEX1
NC_PCH_GPIO66_CLKOUTFLEX2
NC_PCH_GPIO67_CLKOUTFLEX3
40
40
40
40
40
40
40
40
23
23
NC_SDVO_TVCLKINN
NC_SDVO_TVCLKINP
NC_SDVO_STALLN
NC_SDVO_STALLP
NC_SDVO_INTN
NC_SDVO_INTP
MAKE_BASE=TRUE
NC_EDP_TXN<0..3>
MAKE_BASE=TRUE
NC_EDP_AUXP
MAKE_BASE=TRUE
NC_EDP_AUXN
MAKE_BASE=TRUE
NC_CPU_THERMDA
MAKE_BASE=TRUE
NC_CPU_THERMDC
MAKE_BASE=TRUE
NC_CPU_RSVD<30..45>
MAKE_BASE=TRUE
NC_CPU_RSVD<8..27>
MAKE_BASE=TRUE
NC_PEG_R2D_CP<0..7>
MAKE_BASE=TRUE
NC_PEG_R2D_CN<0..7>
MAKE_BASE=TRUE
NC_PEG_D2RP<0..7>
MAKE_BASE=TRUE
NC_PEG_D2RN<0..7>
MAKE_BASE=TRUE
NC_PEG_R2D_CP<8..11>
MAKE_BASE=TRUE
NC_PEG_R2D_CN<8..11>
MAKE_BASE=TRUE
NC_PEG_D2RP<8..11>
MAKE_BASE=TRUE
NC_PEG_D2RN<8..11>
MAKE_BASE=TRUE
TP_PCIE_CLK100M_PE4N
16
TP_PCIE_CLK100M_PE4P
16
TP_PCIE_CLK100M_PE5N
16
TP_PCIE_CLK100M_PE5P
16
TP_PCIE_CLK100M_PE6N
TP_PCIE_CLK100M_PE6P
TP_PCIE_CLK100M_PE7N
TP_PCIE_CLK100M_PE7P
TP_PSOC_P1_3
53
TP_SATA_C_D2RN
16
TP_SATA_C_D2RP
16
TP_SATA_C_R2D_CN
16
TP_SATA_C_R2D_CP
16
TP_SATA_D_D2RN
16
TP_SATA_D_D2RP
16
TP_SATA_D_R2D_CN
16
TP_SATA_D_R2D_CP
16
TP_SATA_E_D2RN
16
TP_SATA_E_D2RP
16
TP_SATA_E_R2D_CN
16
TP_SATA_E_R2D_CP
16
TP_SATA_F_D2RN
16
TP_SATA_F_D2RP
16
TP_SATA_F_R2D_CN
16
TP_SATA_F_R2D_CP
16
TP_TBT_MONDC0
33
TP_TBT_MONDC1
33
TP_TBT_MONOBSP
33
TP_TBT_MONOBSN
33
TP_DP_T29SRC_ML_CP<0..3>
33
TP_DP_T29SRC_ML_CN<0..3>
33
TP_DP_T29SRC_AUXCH_CP
33
TP_DP_T29SRC_AUXCH_CN
33
TP_T29_PCIE_RESET0_L
6
33
TP_T29_PCIE_RESET1_L
6
33
TP_T29_PCIE_RESET2_L
6
33
TP_T29_PCIE_RESET3_L
6
33
PCH_VSS_NCTF<1>
TRUE
I522
I521
I520
I519
I518
I517
PCH_VSS_NCTF<2>
TRUE
PCH_VSS_NCTF<5>
TRUE
PCH_VSS_NCTF<9>
TRUE
PCH_VSS_NCTF<11>
TRUE
PCH_VSS_NCTF<12>
TRUE
TP_LVDS_IG_B_CLKN
8
TP_LVDS_IG_B_CLKP
8
TP_LVDS_IG_BKL_PWM
SMC_BS_ALRT_L
SYNC_MASTER=K90I_MLB
PAGE TITLE
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
Apple Inc.
R
6 3
TP_EDP_TX_P<0..3>
TP_EDP_TX_N<0..3>
TP_EDP_AUX_P
TP_EDP_AUX_N
TP_CPU_THERMDA
TP_CPU_THERMDC
TP_CPU_RSVD<30..45>
TP_CPU_RSVD<8..27>
=PEG_R2D_C_P<0..7>
=PEG_R2D_C_N<0..7>
=PEG_D2R_P<0..7>
=PEG_D2R_N<0..7>
=PEG_R2D_C_P<8..11>
=PEG_R2D_C_N<8..11>
=PEG_D2R_P<8..11>
=PEG_D2R_N<8..11>
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
I547
81
I546
81
I545
81
I544
I543
81
I542
81
I541
81
I540
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
FUNC TEST
NC_PCIE_CLK100M_PE4N
NC_PCIE_CLK100M_PE4P
NC_PCIE_CLK100M_PE5N
NC_PCIE_CLK100M_PE5P
NC_PCIE_CLK100M_PE6N
NC_PCIE_CLK100M_PE6P
NC_PCIE_CLK100M_PE7N
NC_PCIE_CLK100M_PE7P
NC_PSOC_P1_3
NC_SATA_C_D2RN
NC_SATA_C_D2RP
NC_SATA_C_R2D_CN
NC_SATA_C_R2D_CP
NC_SATA_D_D2RN
NC_SATA_D_D2RP
NC_SATA_D_R2D_CN
NC_SATA_D_R2D_CP
NC_SATA_E_D2RN
NC_SATA_E_D2RP
NC_SATA_E_R2D_CN
NC_SATA_E_R2D_CP
NC_SATA_F_D2RN
NC_SATA_F_D2RP
NC_SATA_F_R2D_CN
NC_SATA_F_R2D_CP
NC_TBT_MONDC0
NC_TBT_MONDC1
NC_TBT_MONOBSP
NC_TBT_MONOBSN
NC_DP_T29SRC_ML_CP<0..3>
NC_DP_T29SRC_ML_CN<0..3>
NC_DP_T29SRC_AUXCH_CP
NC_DP_T29SRC_AUXCH_CN
TP_T29_PCIE_RESET0_L
TP_T29_PCIE_RESET1_L
TP_T29_PCIE_RESET2_L
TP_T29_PCIE_RESET3_L
PCH_VSS_NCTF<15>
TRUE
PCH_VSS_NCTF<17>
TRUE
PCH_VSS_NCTF<19>
TRUE
PCH_VSS_NCTF<19>
TRUE
PCH_VSS_NCTF<21>
TRUE
PCH_VSS_NCTF<25>
TRUE
PCH_VSS_NCTF<27>
TRUE
PCH_VSS_NCTF<29>
TRUE
NC_LVDS_IG_B_CLKN
NC_LVDS_IG_B_CLKP
NC_LVDS_IG_BKL_PWM
NC_SMC_BS_ALRT_L
DRAWING NUMBER
051-9058
REVISION
6.0.0
BRANCH
PAGE
7 OF 109
SHEET
6 OF 86
124578
9
9
9
9
D
9
9
9
9
9
9
9
9
C
6
33
6
33
B
6
33
6
33
81
81
6
81
6
81
81
81
81
81
A
SIZE
D
8 7 6 5 4 3
=PPBUS_G3H
63 64
PPVIN_SW_T29BST
35
VOLTAGE=12.8V
=PPVIN_S5_HS_COMPUTING_ISNS
50
D
=PPVIN_S5_HS_OTHER_ISNS
50
=PP18V5_DCIN_CONN
63
=PP3V42_G3H_REG
63
C
=PPVRTC_G3_OUT
24
=PP5V_S5_LDO
66
=PP5V_SUS_FET
72
B
=PP5V_S3_REG
66
=PP5V_S0_FET
72
A
=PP5V_S0_HDD_ISNS
49
"G3Hot" (Always-Present) Rails
PPBUS_G3H
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=12.8V
MAKE_BASE=TRUE
=PPBUS_S0_LCDBKLT
=PPBUS_S5_FWPWRSW
=PPBUS_S0_VSENSE
=PPVIN_SW_T29BST
=PPVIN_S5_HS_COMPUTING_ISNS_R
=PPVIN_S5_HS_OTHER_ISNS_R
PPBUS_S5_HS_COMPUTING_ISNS
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=12.8V
MAKE_BASE=TRUE
=PPVIN_S0_CPUIMVP
=PPVIN_S3_DDRREG
=PPVIN_S0_CPUVCCIOS0
=PPVIN_S0_VCCSAS0
=PPVIN_S0_CPUAXG
PPBUS_S5_HS_OTHER_ISNS
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=12.8V
MAKE_BASE=TRUE
=PPVIN_S5_5VS3
=PPVIN_S5_3V3S5
PPDCIN_G3H
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 MM
VOLTAGE=18.5V
MAKE_BASE=TRUE
=PPDCIN_S5_CHGR
=PPDCIN_S5_VSENSE
PP3V42_G3H
MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.42V
MAKE_BASE=TRUE
=PP3V3_S5_LPCPLUS
=PP3V3_S5_SMC
=PP3V42_G3H_BATT
=PP3V42_G3H_CHGR
=PP3V42_G3H_ONEWIREPROT
=PP3V42_G3H_PWRCTL
=PP3V42_G3H_SMBUS_SMC_BSA
=PP3V42_G3H_SMCUSBMUX
=PP3V42_G3H_TPAD
=PPVIN_S5_SMCVREF
=PPVBAT_G3_SYSCLK
=PP3V42_G3H_AUDIO
PPVRTC_G3H
MIN_LINE_WIDTH=0.2 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3V
MAKE_BASE=TRUE
=PPVRTC_G3_PCH
5V Rails
PP5V_S5
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=5V
MAKE_BASE=TRUE
=PP5V_S5_P1V5DDRFET
=PP5V_S5_TPAD
=PP5V_S5_P5VSUSFET
PP5V_SUS
MIN_LINE_WIDTH=0.50MM
MIN_NECK_WIDTH=0.20MM
VOLTAGE=3.3V
MAKE_BASE=TRUE
=PP5V_SUS_PCH
PP5V_S3
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=5V
MAKE_BASE=TRUE
=PP5V_S3_ALSCAMERA
=PP5V_S3_AUDIO
=PP5V_S3_AUDIO_AMP
=PP5V_S3_DDRREG
=PP5V_S3_IR
=PP5V_S3_MEMRESET
=PP5V_S3_ODD
=PP5V_S3_P5VS0FET
=PP5V_S3_USB
=PP5V_S3_SYSLED
PP5V_S0
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=5V
MAKE_BASE=TRUE
=PP5V_S0_BKL
=PP5V_S0_CPUIMVP
=PP5V_S0_CPUVCCIOS0
=PP5V_S0_FAN_RT
=PP5V_S0_HDD_ISNS_R
=PP5V_S0_KBDLED
=PP5V_S0_LPCPLUS
=PP5V_S0_VCCSAS0
=PP5V_S0_PCH
=PP5V_S0_VMON
=PP5V_S0_ISNS
=PP5V_S0_AUDIO
PP5V_S0_HDD
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.4MM
VOLTAGE=5V
MAKE_BASE=TRUE
=PP5V_S0_HDD
=PP3V3_S5_REG
66
6
77
39
50
8
35
50 39
50
68 69
67
70
65
69
=PP3V3_SUS_FET
72
66
66
64
50
6
=PP3V3_S4_FET
72
47
45 46
63
64
63
73
48
42
53
46
24
58
16 17 20
72
54
72
22
6
32
57
60
67
41 44
26
41
72
42
46
6
77
68 69
70
52
49
54
47
65
22 24
73
49
41
=PP3V3_S3_FET
72
=PP3V3_S0_FET
72
3.3V Rails
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
MIN_LINE_WIDTH=0.50MM
MIN_NECK_WIDTH=0.20MM
MIN_LINE_WIDTH=0.50MM
MIN_NECK_WIDTH=0.20MM
MIN_LINE_WIDTH=0.50MM
MIN_NECK_WIDTH=0.20MM
=PP3V3_S3_USB_HUB
=PP3V3_S0_KBDLED
=PP3V3_S0_VMON
PP3V3_S5
=PP3V3_S5_XDP
=PP3V3_S0_P3V3S0FET
=PP3V3_S3_P3V3S3FET
=PP3V3_S5_CPU_VCCDDR
=PP3V3_S4_P3V3S4FET
=PP3V3_S5_LCD
=PP3V3_S5_PCH
=PP3V3_S5_PCHPWRGD
=PP3V3_S5_SMCBATLOW
=PP3V3_S5_PCH_VCCDSW
=PP3V3_S5_SYSCLK
=PP3V3_S5_VMON
=PP3V3_S5_PWRCTL
=PP3V3_S5_P3V3SUSFET
=PP3V3_S4_TBTAPWRSW
=PP3V3_S5_PCH_GPIO
PP3V3_SUS
=PP3V3_SUS_PCH_VCCSUS_USB
=PP3V3_SUS_PCH_VCCSUS_GPIO
=PP3V3_SUS_PCH_VCCSUS
=PP3V3_SUS_PCH_GPIO
=PP3V3_SUS_PCH
=PP3V3_SUS_PWRCTL
=PP3V3_SUS_P1V05SUSLDO
=PP3V3_SUS_SMC
=PP3V3_SUS_ROM
=PP3V3_SUS_PCH_VCC_SPI
PP3V3_S4
=PP3V3_S4_TPAD
=PP3V3_S4_SMC
=PP3V3_S4_SD_HPD
=PP3V3_S4_BT
PP3V3_S3
=PP3V3_S3_BT
=PP3V3_S3_MEMRESET
=PP3V3_S3_SMBUS_SMC_A_S3
=PP3V3_S3_SMBUS_SMC_MGMT
=PP3V3_S3_SMS
=PP3V3_S3_USB_RESET
=PP3V3_S3_VREFMRGN
=PP3V3_S3_WLAN
=PP3V3_S3_SDBUF
=PP3V3_S3_P3V3ENETFET
=PP3V3_S3_PCH_GPIO
=PP3V3_S3_ISNS
=PP3V3_S3_USBMUX
PP3V3_S0
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.20MM
=PP3V3_S0_HDD
=PP3V3_S0_AUDIO
=PP3V3_S0_BKL_VDDIO
=PP3V3_S0_ISNS
=PP3V3_S0_HS_COMPUTING_ISNS
=PP3V3_S0_CPUTHMSNS
=PP3V3_S0_LCD
=PP3V3_S0_DP_DDC
=PP3V3_S0_ENETPHY
=PP3V3_S0_FAN_RT
=PP3V3_S0_FWPWRCTL
=PP3V3_S0_FWLATEVG
=PP3V3_S0_P3V3T29FET
=PP3V3_S0_SDCARD
=PP3V3_S0_P1V8S0
=PP3V3_S0_ODD
=PP3V3_FW_P3V3FWFET
=PP3V3_S0_PCH
=PP3V3_S0_PCH_GPIO
=PP3V3_S0_PCH_VCC3_3_CLK
=PP3V3_S0_PCH_VCC3_3_GPIO
=PP3V3_S0_PCH_VCC3_3_HVCMOS
=PP3V3_S0_PCH_VCC3_3_PCI
=PP3V3_S0_PCH_VCC3_3_SATA
=PP3V3_S0_PCH_VCCADAC
=PP3V3_S0_PCH_VCCA_LVDS
=PP3V3_S0_PWRCTL
=PP3V3_S0_RSTBUF
=PP3V3_S0_SB_PM
=PP3V3_S0_SMBUS_PCH
=PP3V3_S0_SMBUS_SMC_0_S0
=PP3V3_S0_SMBUS_SMC_B_S0
=PP3V3_S0_SMC
=PPSPD_S0_MEM_A
=PPSPD_S0_MEM_B
=PP3V3_S0_P1V5S0
=PP3V3_S0_T29PWRCTL
=PP3V3_S0_HS_OTHER_ISNS
=PP3V3_S0_DPSDRVA
=PP3V3_S0_P1V05S0LDO
=PP3V3_S0_IMVPISNS
=PP3V3_S0_XDP
=PP3V3_S0_T29I2C
VOLTAGE=3.3V
MAKE_BASE=TRUE
VOLTAGE=3.3V
MAKE_BASE=TRUE
VOLTAGE=3.3V
MAKE_BASE=TRUE
VOLTAGE=3.3V
MAKE_BASE=TRUE
VOLTAGE=3.3V
MAKE_BASE=TRUE
6
85
23
72
72
26
72
74
17
24
46
20 22
24
73
73
72
76
19
20 22
20 22
20
16 17 18 19
22
73
71
46
56
20 22
6
53 54
46
30
32
6
32
26
48
48
55
25
25
31
32
24
73
18 24
49
25
6
85
41
57 61 62
77
49
50
51
74
8
36
52
39
39 40
35
30
71
41
39
16 22
16 17 18 19 30
22
20 22
20 22
20 22
20 22
22
20
73
24
24
48
48
48
41
54
73
27
29
71
35
50
75
71
49
23
48
=PP1V8_S0_REG
71
2A max supply
=PP1V5_S3_DDR_ISNS
49
=PPDDR_S3_REG
67
=PP1V5_S3RS0_FET
72
=PP1V5_S0_REG
71
=PPVTT_S3_DDR_BUF
31 67
=PPVTT_S0_DDR_LDO
67
=PPVCCSA_S0_REG
65
=PP1V05_SUS_LDO
71
=PPCPUVCCIO_S0_REG
70
? mA
=PP3V3_ENET_FET
73
1.8V/1.5V/1.2V/1.05V Rails
PP1V8_S0
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.8V
MAKE_BASE=TRUE
=PP1V8_S0_CPU_VCCPLL
=PP1V8_S0_PCH_VCCTX_LVDS
=PP1V8_S0_PCH_VCC_DFTERM
=PP1V8_S0_P1V05S0LDO
=PP1V8R1V5_S0_PCH_VCCVRM
=PPVDDIO_S0_SBCLK
PP1V5_S3_DDR
MIN_LINE_WIDTH=0.8 MM
MIN_NECK_WIDTH=0.1 MM
VOLTAGE=1.5V
MAKE_BASE=TRUE
=PP1V5_S3_MEMRESET
=PP1V5_S3_MEM_A
=PP1V5_S3_MEM_B
=PPVIN_S0_DDRREG_LDO
=PPDDR_S3_MEMVREF
PP1V5_S3
MIN_LINE_WIDTH=0.8 MM
MIN_NECK_WIDTH=0.1 MM
VOLTAGE=1.5V
MAKE_BASE=TRUE
=PP1V5_S3_P1V5S3RS0_FET
=PP1V5_S3_DDR_ISNS_R
PP1V5_S3RS0
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.5V
MAKE_BASE=TRUE
=PP1V5_S3_CPU_VCCDDR
PP1V5_S0
MIN_LINE_WIDTH=2 mm
MIN_NECK_WIDTH=0.17 mm
VOLTAGE=1.5V
MAKE_BASE=TRUE
=PP1V5_S0_RDRVR
=PP1V8R1V5_S0_AUDIO
=PP3V3R1V5_S0_AUDIO
=PP3V3R1V5_S0_PCH_VCCSUSHDA
=PP1V5_S0_VMON
PPVTTDDR_S3
MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=0.75V
MAKE_BASE=TRUE
PP0V75_S0_DDRVTT
MIN_LINE_WIDTH=2 mm
MIN_NECK_WIDTH=0.17 mm
VOLTAGE=0.75V
MAKE_BASE=TRUE
=PP0V75_S0_MEM_VTT_A
=PP0V75_S0_MEM_VTT_B
=PPVTT_S0_VTTCLAMP
PPVCCSA_S0_CPU
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=0.9V
MAKE_BASE=TRUE
=PPVCCSA_S0_CPU
PP1V05_SUS
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
MAKE_BASE=TRUE
=PP1V05_SUS_PCH_JTAG
PP1V05_S0
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1V
MAKE_BASE=TRUE
=PP1V05_S0_CPU_VCCIO
=PPVCCIO_S0_CPUIMVP
=PPVCCIO_S0_XDP
=PPVCCIO_S0_SMC
=PP1V05_S0_FWPWRCTL
=PP1V05_FW_P1V0FWFET
=PP1V05_S0_VMON
XW0800
SM
XW0801
SM
21
21
ENET Rails
=PP1V05_S0_P1V05T29FET
PP1V05_S0_PCH
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1V
MAKE_BASE=TRUE
=PP1V05_S0_PCH_VCCIO_PLLPCIE
=PP1V05_S0_PCH
=PP1V05_S0_PCH_VCCIO
=PP1V05_S0_PCH_VCCIO_PCIE
=PP1V05_S0_PCH_VCCIO_SATA
=PP1V05_S0_PCH_VCCASW
=PP1V05_S0_PCH_VCCIO_USB
=PP1V05_S0_PCH_VCC_CORE
=PP1V05_S0_PCH_VCCIO_CLK
=PP1V05_S0_PCH_VCCDIFFCLK
=PP1V05_S0_PCH_VCCSSC
=PP1V05_S0_PCH_V_PROC_IO
=PP1V05_S0_PCH_VCCIO_PLLUSB
=PP1V05_S0_PCH_VCC_DMI
=PP1V05_S0_PCH_VCCIO_PLLFDI
=PP1V05_S0_PCH_VCCDMI_FDI
PP3V3_ENET
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V
MAKE_BASE=TRUE
=PP3V3_ENET_PHY
=PP3V3_ENET_SYSCLK
=PPVDDIO_ENET_CLK
6
14
22
19 20 22
71
20
24
26
27
29
67
31
6
72
49
6
85
10 12 15 26
41
57
57
20 22 24
73
27
29
26
6
12 15
23
6
9
10 12 14
68
23
46
39
39
73
35
20
16 22
20 22
17
16 20 22
20 22
20 22
20 22
20 22
16 20 22
20 22
20 22
20
20 22
20
20
6
24 36 71
24
24
=PPBUS_FW_FET
39
=PP3V3_FW_FET
=PP1V0_FW_FET_R
39
=PP15V_T29_REG
8
35
=PP3V3_T29_FET
35
=PP1V05_T29_FET
35
=PP1V05_S0_LDO
71
=PPVCORE_S0_CPU_REG
69
=PPVCORE_S0_AXG_REG
69
=PP1V5_S3_CPU_VCCDQ
12 15
=PP1V05_S0_CPU_VCCPQE
8
12 14
=PP1V8_S0_CPU_VCCPLL_R
12 14
"FW" (FireWire) Rails
PPVP_FW
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=12.8V
MAKE_BASE=TRUE
=PPVP_FW_PORT1
=PPVP_FW_PHY_CPS_FET
PP3V3_FW_FWPHY
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V
MAKE_BASE=TRUE
=PP3V3_FW_FWPHY
=PP3V3_S0_P1V05FWFET
PP1V0_FW_FWPHY
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.0V
MAKE_BASE=TRUE
=PP1V0_FW_FWPHY
T29 Rails (off when no cable)
PP15V_T29
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=17.8V
MAKE_BASE=TRUE
=PPHV_SW_TBTAPWRSW
PP3V3_T29
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V
MAKE_BASE=TRUE
=PPVDDIO_T29_CLK
=PP3V3_T29_RTR
=PP3V3_T29_PCH_GPIO
PP1V05_T29
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
MAKE_BASE=TRUE
=PP1V05_T29_RTR
1V05 S0 LDO
PP1V05_S0_PCH_VCCADPLL
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
MAKE_BASE=TRUE
=PP1V05_S0_PCH_VCCADPLL
Chipset "VCore" Rails
SYNC_MASTER=K90I_MLB
PAGE TITLE
PPVCORE_S0_CPU
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 MM
VOLTAGE=1.25V
MAKE_BASE=TRUE
=PPVCORE_S0_CPU
=PPCPUVCORE_S0_VSENSE
PPVCORE_S0_AXG
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
MAKE_BASE=TRUE
=PPVCORE_S0_CPU_VCCAXG
=PPAXGVCORE_S0_VSENSE
PP1V5_S3_CPU_VCCDQ
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.5V
MAKE_BASE=TRUE
PP1V05_S0_CPU_VCCPQE
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
MAKE_BASE=TRUE
PP1V8_S0_CPU_VCCPLL_R
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.8V
MAKE_BASE=TRUE
Power Aliases
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
6 3
12
40
40
38 39 40
38 39
76
24
33 34 35
16 19
35
34
22
SYNC_DATE=02/15/2011
DRAWING NUMBER
051-9058
REVISION
6.0.0
BRANCH
PAGE
8 OF 109
SHEET
7 OF 86
124578
D
C
6
9
12 14
49
B
6
9
12 15
49
A
SIZE
D
8 7 6 5 4 3
CPU signals
HEATSINK STANDOFFS
STDOFF-4.5OD.98H-1.1-3.48-TH
D
STDOFF-4.5OD.98H-1.1-3.48-TH
Z0902
1
Z0904
1
BELOW CPU
Z0920
STDOFF-4.5OD.98H-1.1-3.48-TH
1
LEFT OF CPU
FAN STANDOFF
STDOFF-4.5OD.98H-1.1-3.48-TH
Z0905
1
MLB MOUNTING (TO C. BRACKET) SCREW HOLES
OMIT
Z0906
3R2P5
1
OMIT
Z0907
3R2P5
1
MEMVTT_EN
26
MAKE_BASE=TRUE
DP_EXTA_ML_C_P<3..0>
75 81
MAKE_BASE=TRUE
DP_EXTA_ML_C_N<3..0>
75 81
MAKE_BASE=TRUE
DP_EXTA_AUXCH_C_P
75 81
MAKE_BASE=TRUE
DP_EXTA_AUXCH_C_N
75 81
MAKE_BASE=TRUE
FW_PLUG_DET_L
MAKE_BASE=TRUE
FW643_WAKE_L
39
MAKE_BASE=TRUE
16
16
16
16
16 81
16 81
16 81
16 81
TP_SMC_EXCARD_PWR_EN
MAKE_BASE=TRUE
PCIE_EXCARD_D2R_N
PCIE_EXCARD_D2R_P
PCIE_EXCARD_R2D_C_N
PCIE_EXCARD_R2D_C_P
PCIE_CLK100M_EXCARD_N
PCIE_CLK100M_EXCARD_P
PCIE_PCH_D2R_N<5..8>
PCIE_PCH_D2R_P<5..8>
PCIE_PCH_R2D_C_N<5..8>
PCIE_PCH_R2D_C_P<5..8>
PEG_CLK100M_P
PEG_CLK100M_N
MLB MOUNTING (TO TOPCASE) SCREW HOLES
OMIT
Z0908
3R2P5
C
1
OMIT
Z0911
3R2P5
1
OMIT
Z0909
3R2P5
1
OMIT
Z0912
3R2P5
1
OMIT
Z0910
3R2P5
1
TP_PCH_CLKOUT_DPN
16
TP_PCH_CLKOUT_DPP
16
=DDRVTT_EN
TP_DP_IG_B_MLP<3..0>
TP_DP_IG_B_MLN<3..0>
DPA_IG_AUX_CH_P
DPA_IG_AUX_CH_N
FW_PME_L
=FW_PME_L
SMC_EXCARD_PWR_EN
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
26 67
17
17
17
17
NC_PCIE_EXCARD_D2RN
NC_PCIE_EXCARD_D2RP
NC_PCIE_EXCARD_R2D_CN
NC_PCIE_EXCARD_R2D_CP
NC_PCIE_CLK100M_EXCARDN
TRUE
MAKE_BASE=TRUE
NC_PCIE_CLK100M_EXCARDP
TRUE
MAKE_BASE=TRUE
NC_PCIE_PCH_D2RN<5..8>
NC_PCIE_PCH_D2RP<5..8>
NC_PCIE_PCH_R2D_CN<5..8>
NC_PCIE_PCH_R2D_CP<5..8>
NC_PEG_CLK100MP
NC_PEG_CLK100MN
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
NC_PCH_CLKOUT_DPN
NC_PCH_CLKOUT_DPP
19 39
38 39
17
17
=PEG_R2D_C_P<12..15>
9
=PEG_R2D_C_N<12..15>
9
=PEG_D2R_P<12..15>
9
=PEG_D2R_N<12..15>
9
TP_DP_IG_C_CTRL_CLK
TP_DP_IG_C_CTRL_DATA
TP_DP_IG_D_CTRL_CLK
TP_DP_IG_D_CTRL_DATA
PPBUS_SW_LCDBKLT_PWR
77
MAKE_BASE=TRUE
NC_CPU_VCCIO_SEL
MAKE_BASE=TRUE
DP_EXTA_DDC_CLK
75
MAKE_BASE=TRUE
DP_EXTA_DDC_DATA
MAKE_BASE=TRUE
DP_EXTA_HPD
75
MAKE_BASE=TRUE
7 8
NO_TEST=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
=PP3V3_S0_DP_DDC
R0920
2.2K
5%
1/16W
MF-LF
402
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
1
R0908
100K
5%
1/16W
MF-LF
402
2
R0910
1/16W
MF-LF
PCIE_T29_R2D_C_P<3..0>
PCIE_T29_R2D_C_N<3..0>
PCIE_T29_D2R_P<3..0>
PCIE_T29_D2R_N<3..0>
1
2
1
R0921
2.2K
5%
1/16W
MF-LF
402
2
DPB_IG_DDC_CLK
DPB_IG_DDC_DATA
DP_IG_D_CTRL_CLK
DP_IG_D_CTRL_DATA
7 8
DPA_IG_DDC_CLK
DPA_IG_DDC_DATA
DPA_IG_HPD
0
21
5%
402
CPU_VCCIO_SEL
1
R0922
2.2K
1/16W
MF-LF
R0923
5%
402
2
=PP3V3_S0_DP_DDC
1
2.2K
1/16W
MF-LF
R0925
5%
402
2
R0924
PPBUS_SW_BKL
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.375 MM
VOLTAGE=12.6V
MAKE_BASE=TRUE
=PPBUS_SW_BKL
2.2K
1/16W
MF-LF
2.2K
1/16W
MF-LF
33 81
33 81
33 81
33 81
1
5%
402
2
17
17
1
5%
402
2
17
17 75
17
77
12 78
DPB_IG_HPD
17
TP_DP_IG_C_MLP<3..0>
17
TP_DP_IG_C_MLN<3..0>
17
DPB_IG_AUX_CH_P
17
DPB_IG_AUX_CH_N
17
TP_DP_IG_D_HPD
17
TP_DP_IG_D_MLP<3..0>
17
TP_DP_IG_D_MLN<3..0>
17
TP_DP_IG_D_AUXP
17
TP_DP_IG_D_AUXN
17
NC_BCM57765_CE_L_MS_INS_L
MAKE_BASE=TRUE
TP_LVDS_IG_B_CLKP
6
MAKE_BASE=TRUE
TP_LVDS_IG_B_CLKN
6
MAKE_BASE=TRUE
NC_LVDS_IG_B_DATAP<0..3>
MAKE_BASE=TRUE
NC_LVDS_IG_B_DATAN<0..3>
MAKE_BASE=TRUE
NC_LVDS_IG_A_DATAP<3>
MAKE_BASE=TRUE
NC_LVDS_IG_A_DATAN<3>
MAKE_BASE=TRUE
LVDS_DDC_CLK
6
74
MAKE_BASE=TRUE
LVDS_DDC_DATA
6
74
MAKE_BASE=TRUE
LCD_BKLT_PWM
77
MAKE_BASE=TRUE
LCD_IG_PWR_EN
74
MAKE_BASE=TRUE
LCD_BKLT_EN
77
MAKE_BASE=TRUE
T29 DP Ports
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
DP_T29SNK0_HPD
DP_T29SNK0_ML_C_P<3..0>
DP_T29SNK0_ML_C_N<3..0>
DP_T29SNK0_AUXCH_C_P
DP_T29SNK0_AUXCH_C_N
DP_T29SNK1_HPD
DP_T29SNK1_ML_C_P<3..0>
DP_T29SNK1_ML_C_N<3..0>
DP_T29SNK1_AUXCH_C_P
DP_T29SNK1_AUXCH_C_N
BCM57765_CE_L_MS_INS_L
LVDS_IG_B_CLK_P
LVDS_IG_B_CLK_N
LVDS_IG_B_DATA_P<0..3>
LVDS_IG_B_DATA_N<0..3>
LVDS_IG_A_DATA_P<3>
LVDS_IG_A_DATA_N<3>
LVDS_IG_DDC_CLK
LVDS_IG_DDC_DATA
LVDS_IG_BKL_PWM
LVDS_IG_PANEL_PWR
LVDS_IG_BKL_ON
12
33
33 83
33 83
33 83
33 83
33
D
33 83
33 83
33 83
33 83
17 80
17 80
17 80
17 80
17 80
17 80
17
17
17
17
17
C
USB Signals
NC_USB3_EXTD_TXN
=PPVIN_SW_T29BST
7
35
T29BST:N
R0960
0
5%
1/8W
MF-LF
805
21
=PP15V_T29_REG
MAKE_BASE=TRUE
NC_USB3_EXTD_TXP
MAKE_BASE=TRUE
NC_USB3_EXTD_RXN
MAKE_BASE=TRUE
NC_USB3_EXTD_RXP
MAKE_BASE=TRUE
7
35
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
=PP1V05_S0_CPU_VCCPQE
7
12 14
Unused eDP CLK
DPLL_REF_CLK_P
6
17 26 45 73
MAKE_BASE=TRUE
10
DPLL_REF_CLK_N
10
PM_SLP_S3_L
33
OUT
19 33
OUT
33
IN
33 83
OUT
33 83
OUT
33 83
IN
33 83
IN
33 33
IN
IN
TP_P1V5S3RS0_RAMP_DONE
MAKE_BASE=TRUE
TP_DDRREG_PGOOD
MAKE_BASE=TRUE
T29_A_BIAS
8
75 76
EMI IO (SHORT) POGO PINS
B
ZS0900
1.4DIA-SHORT-SILVER-K99
SM
1
ZS0901
1.4DIA-SHORT-SILVER-K99
SM
1
ZS0902
1.4DIA-SHORT-SILVER-K99
SM
1
ZS0910
1.4DIA-SHORT-SILVER-K99
SM
1
C0960
0.01UF
X5R-CERM
0201
1
10%
10V
2
DP_A_BIAS0
75
C0962
0.01UF
X5R-CERM
0201
10%
10V
T29_A_BIAS_R2DP1
C0970
0.01UF
X5R-CERM
0201
C0972
0.01UF
X5R-CERM
0201
JTAG_ISP_TCK
IN
MAKE_BASE=TRUE
JTAG_ISP_TDI
IN
MAKE_BASE=TRUE
JTAG_ISP_TDO
OUT
MAKE_BASE=TRUE
21
5%
10%
10V
21
5%
10%
10V
T29_A_BIAS_R2DN0
R0971
T29_A_BIAS_R2DP0
MF
VOLTAGE=3.3V
1
2
R0973
T29_A_BIAS_D2RP1
MF
VOLTAGE=3.3V
1
2
ZS0903
1.4DIA-SHORT-SILVER-K99
SM
1
ZS0909
1.4DIA-SHORT-SILVER-K99
SM
1
T29_A_BIAS
8
75 76
R0970
1/20W
51
201
EMI TALL POGO PINS
ZS0904
POGO-2.0OD-3.5H-K86-K87
SM
1
ZS0905
POGO-2.0OD-3.5H-K86-K87
SM
1
ZS0906
POGO-2.0OD-3.5H-K86-K87
SM
1
ZS0907
POGO-2.0OD-3.5H-K86-K87
SM
1
R0972
1/20W
51
201
TALL POGO PINS close to DIMM conn.
ZS0920
A
POGO-2.0OD-3.5H-K86-K87
SM
1
NO STUFF
ZS0921
POGO-2.0OD-3.5H-K86-K87
SM
1
NO STUFF
ZS0922
POGO-2.0OD-3.5H-K86-K87
SM
1
NO STUFF
ZS0923
POGO-2.0OD-3.5H-K86-K87
SM
1
NO STUFF
ZS0924
POGO-2.0OD-3.5H-K86-K87
SM
1
NO STUFF
19 23
19
19
75
1
2
51
201
1/20W
51
201
1/20W
TBT JTAG
DP_A_BIAS2
C0964
0.01UF
X5R-CERM
75
75
21
5%
MF
C0971
0.01UF
10%
10V
X5R-CERM
0201
21
5%
MF
C0973
0.01UF
10%
10V
X5R-CERM
0201
JTAG_TBT_TCK
JTAG_TBT_TDI
JTAG_TBT_TDO
1
10%
10V
2
0201
T29_A_BIAS_R2DN1
VOLTAGE=3.3V
1
2
T29_A_BIAS_D2RN1
VOLTAGE=3.3V
1
2
USB3_EXTD_TX_N
USB3_EXTD_TX_P
USB3_EXTD_RX_N
USB3_EXTD_RX_P
DPLL_REF_CLKP
MAKE_BASE=TRUE
DPLL_REF_CLKN
MAKE_BASE=TRUE
=TBT_S0_EN
Unused T29 Ports
T29_D2R_P<2..3>
T29_D2R_N<2..3>
T29_R2D_C_P<2..3>
T29_R2D_C_N<2..3>
T29_LSEO<2>
T29_LSEO<3>
Unused PGOOD signal
18
18
18
18
1
R0940
1K
5%
1/16W
MF-LF
402
2
1
R0941
1K
5%
1/16W
MF-LF
402
2
76
NC_T29_D2RP<2..3>
MAKE_BASE=TRUE
NC_T29_D2RN<2..3>
MAKE_BASE=TRUE
NC_T29_R2D_CP<2..3>
MAKE_BASE=TRUE
NC_T29_R2D_CN<2..3>
MAKE_BASE=TRUE
T29_LSOE<2>
MAKE_BASE=TRUE
T29_LSOE<3>
MAKE_BASE=TRUE
P1V5S3RS0_RAMP_DONE
DDRREG_PGOOD
USB_BT_N
32 80
MAKE_BASE=TRUE
USB_BT_P
32 80
MAKE_BASE=TRUE
USB_TPAD_N
53 80
MAKE_BASE=TRUE
USB_TPAD_P
53 80
MAKE_BASE=TRUE
USB_IR_N
44 80
MAKE_BASE=TRUE
USB_IR_P
44 80
MAKE_BASE=TRUE
USB_SMC_N
45 80
USB_SMC_P
45 80
NC_USB_EXTD_EHCIN
MAKE_BASE=TRUE
NC_USB_EXTD_EHCIP
MAKE_BASE=TRUE
NC_USB_EXTCN
MAKE_BASE=TRUE
NC_USB_EXTCP
MAKE_BASE=TRUE
NC_USB3_EXTC_TXN
MAKE_BASE=TRUE
NC_USB3_EXTC_TXP
MAKE_BASE=TRUE
NC_USB3_EXTC_RXN
MAKE_BASE=TRUE
NC_USB3_EXTC_RXP
MAKE_BASE=TRUE
NC_USB_EXTD_XHCIN
MAKE_BASE=TRUE
NC_USB_EXTD_XHCIP
MAKE_BASE=TRUE
TP_CPU_THERMDP
MAKE_BASE=TRUE
TP_CPU_THERMDN
MAKE_BASE=TRUE
TP_CPU_VTT_SELECT
MAKE_BASE=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
IN
IN
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
SYNC_MASTER=K90I_MLB SYNC_DATE=02/15/2011
OUT
PAGE TITLE
33 33
OUT
NOTICE OF PROPRIETARY PROPERTY:
72
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
67
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
6 3
USBHUB_DN1_N
USBHUB_DN1_P
USBHUB_DN3_N
USBHUB_DN3_P
USBHUB_DN2_N
USBHUB_DN2_P
NC_USB_SMCN
MAKE_BASE=TRUE
NC_USB_SMCP
MAKE_BASE=TRUE
USB_EXTD_EHCI_N
NO_TEST=TRUE
NO_TEST=TRUE
USB_EXTD_EHCI_P
USB_EXTC_N
USB_EXTC_P
USB3_EXTC_TX_N
USB3_EXTC_TX_P
USB3_EXTC_RX_N
USB3_EXTC_RX_P
USB_EXTD_XHCI_N
USB_EXTD_XHCI_P
CPU_THERMD_P
CPU_THERMD_N
CPU_VTTSELECT
Digital Ground
GND
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=0V
Signal Aliases
Apple Inc.
R
25
25
25
25
25
25
18
18
18 80
18 80
18
18
18
18
18 80
18 80
9
85
9
85
DRAWING NUMBER
051-9058
REVISION
6.0.0
BRANCH
PAGE
9 OF 109
SHEET
8 OF 86
124578
SIZE
B
A
D
8 7 6 5 4 3
NOTE: Intel provides an internal pull-up OF 5-15k to VCCIO on all CFG signals.
12
DMI_S2N_N<0>
17 78
IN
DMI_S2N_N<1>
17 78
IN
DMI_S2N_N<2>
17 78
IN
DMI_S2N_N<3>
17 78
IN
DMI_S2N_P<0>
17 78
D
C
=PP1V05_S0_CPU_VCCIO
7 9
10 12 14
R1030
24.9
1%
1/16W
MF-LF
402
EDP
R1031
10K
1%
1/16W
MF-LF
402
21
21
B
Intel Doc 467283 ChiefRiver Platform design guild rev0.71 section 2.2.12 recommendation.
NOTE: eDP_COMPIO and eDP_ICOMPO can not be left floating
even if internal Graphics is disabled since they are
shared with other interfaces.
NOTE: The EDP_HPD processor input is a low voltage active low signal.
Therefore, an inverting level shifter is required on the motherboard
to convert the active high signal from Embedded DisplayPort sink device
to low voltage signals for the processor
(refer to latest Processor EDS for DC specifications).
If HPD is disabled while eDP interface is still enabled,
connect it to CPU VCCIo via a 10-kOhm pull-up resistor on the motherboard.
This signal can be left as no-connect if entire eDP interface is disabled.
IN
17 78
IN
17 78
IN
17 78
IN
17 78
OUT
17 78
OUT
17 78
OUT
17 78
OUT
17 78
OUT
17 78
OUT
17 78
OUT
17 78
OUT
17 78
OUT
17 78
OUT
17 78
OUT
17 78
OUT
17 78
OUT
17 78
OUT
17 78
OUT
17 78
OUT
17 78
OUT
17 78
OUT
17 78
OUT
17 78
OUT
17 78
OUT
17 78
OUT
17 78
OUT
17 78
OUT
17 78
IN
17 78
IN
17 78
IN
17 78
IN
17 78
IN
PLACE_NEAR=U1000.AF3:12.7MM
PLACE_NEAR=U1000.AG11:12.7MM
DMI_S2N_P<1>
DMI_S2N_P<2>
DMI_S2N_P<3>
DMI_N2S_N<0>
DMI_N2S_N<1>
DMI_N2S_N<2>
DMI_N2S_N<3>
DMI_N2S_P<0>
DMI_N2S_P<1>
DMI_N2S_P<2>
DMI_N2S_P<3>
FDI_DATA_N<0>
FDI_DATA_N<1>
FDI_DATA_N<2>
FDI_DATA_N<3>
FDI_DATA_N<4>
FDI_DATA_N<5>
FDI_DATA_N<6>
FDI_DATA_N<7>
FDI_DATA_P<0>
FDI_DATA_P<1>
FDI_DATA_P<2>
FDI_DATA_P<3>
FDI_DATA_P<4>
FDI_DATA_P<5>
FDI_DATA_P<6>
FDI_DATA_P<7>
FDI_FSYNC<0>
FDI_FSYNC<1>
FDI_INT
FDI_LSYNC<0>
FDI_LSYNC<1>
EDP_COMP
78
EDP_HPD
TP_EDP_AUX_N
6
TP_EDP_AUX_P
6
TP_EDP_TX_N<0>
6
TP_EDP_TX_N<1>
6
TP_EDP_TX_N<2>
6
TP_EDP_TX_N<3>
6
TP_EDP_TX_P<0>
6
TP_EDP_TX_P<1>
6
TP_EDP_TX_P<2>
6
TP_EDP_TX_P<3>
6
AA11
AC12
AA10
AG11
AE11
AE10
P10
P11
W11
AA6
AC9
W10
AA7
AA3
AC8
U11
AG8
AD2
AF3
AG4
AF4
AC3
AC4
AE7
AC1
AA4
AE6
M2
P6
P1
N3
P7
P3
K1
M8
N4
R2
K3
M7
P4
T3
U7
W1
W6
V4
Y2
U6
W3
W7
T4
DMI_RX_0*
DMI_RX_1*
DMI_RX_2*
DMI_RX_3*
DMI_RX_0
DMI_RX_1
DMI_RX_2
DMI_RX_3
DMI_TX_0*
DMI_TX_1*
DMI_TX_2*
DMI_TX_3*
DMI_TX_0
DMI_TX_1
DMI_TX_2
DMI_TX_3
FDI0_TX_0*
FDI0_TX_1*
FDI0_TX_2*
FDI0_TX_3*
FDI1_TX_0*
FDI1_TX_1*
FDI1_TX_2*
FDI1_TX_3*
FDI0_TX_0
FDI0_TX_1
FDI0_TX_2
FDI0_TX_3
FDI1_TX_0
FDI1_TX_1
FDI1_TX_2
FDI1_TX_3
FDI0_FSYNC
FDI1_FSYNC
FDI_INT
FDI0_LSYNC
FDI1_LSYNC
EDP_ICOMPO
EDP_COMPIO
EDP_HPD
EDP_AUX*
EDP_AUX
EDP_TX_0*
EDP_TX_1*
EDP_TX_2*
EDP_TX_3*
EDP_TX_0
EDP_TX_1
EDP_TX_2
EDP_TX_3
OMIT_TABLE
CRITICAL
U1000
IVY-BRIDGE
2C-35W
BGA
(1 OF 9)
DMI
INTEL FLEXIBLE DISPLAY INTERFACE SIGNALS
PCI EXPRESS BASED INTERFACE SIGNALS
EMBEDDED DISPLAY PORT
PEG_ICOMPI
PEG_ICOMPO
PEG_RCOMPO
PEG_RX_0*
PEG_RX_1*
PEG_RX_2*
PEG_RX_3*
PEG_RX_4*
PEG_RX_5*
PEG_RX_6*
PEG_RX_7*
PEG_RX_8*
PEG_RX_9*
PEG_RX_10*
PEG_RX_11*
PEG_RX_12*
PEG_RX_13*
PEG_RX_14*
PEG_RX_15*
PEG_RX_0
PEG_RX_1
PEG_RX_2
PEG_RX_3
PEG_RX_4
PEG_RX_5
PEG_RX_6
PEG_RX_7
PEG_RX_8
PEG_RX_9
PEG_RX_10
PEG_RX_11
PEG_RX_12
PEG_RX_13
PEG_RX_14
PEG_RX_15
PEG_TX_0*
PEG_TX_1*
PEG_TX_2*
PEG_TX_3*
PEG_TX_4*
PEG_TX_5*
PEG_TX_6*
PEG_TX_7*
PEG_TX_8*
PEG_TX_9*
PEG_TX_10*
PEG_TX_11*
PEG_TX_12*
PEG_TX_13*
PEG_TX_14*
PEG_TX_15*
PEG_TX_0
PEG_TX_1
PEG_TX_2
PEG_TX_3
PEG_TX_4
PEG_TX_5
PEG_TX_6
PEG_TX_7
PEG_TX_8
PEG_TX_9
PEG_TX_10
PEG_TX_11
PEG_TX_12
PEG_TX_13
PEG_TX_14
PEG_TX_15
G3
G1
G4
H22
J21
B22
D21
A19
D17
B14
D13
A11
B10
G8
A8
B6
H8
E5
K7
K22
K19
C21
D19
C19
D16
C13
D12
C11
C9
F8
C8
C5
H6
F6
K6
G22
C23
D23
F21
H19
C17
K15
F17
F14
A15
J14
H13
M10
F10
D9
J4
F22
A23
D24
E21
G19
B18
K17
G17
E14
C15
K13
G13
K10
G10
D8
K4
CPU_PEG_COMP
78
PLACE_NEAR=U1000.G3:12.7MM
=PEG_D2R_N<0>
=PEG_D2R_N<1>
=PEG_D2R_N<2>
=PEG_D2R_N<3>
=PEG_D2R_N<4>
=PEG_D2R_N<5>
=PEG_D2R_N<6>
=PEG_D2R_N<7>
=PEG_D2R_N<8>
=PEG_D2R_N<9>
=PEG_D2R_N<10>
=PEG_D2R_N<11>
=PEG_D2R_N<12>
=PEG_D2R_N<13>
=PEG_D2R_N<14>
=PEG_D2R_N<15>
=PEG_D2R_P<0>
=PEG_D2R_P<1>
=PEG_D2R_P<2>
=PEG_D2R_P<3>
=PEG_D2R_P<4>
=PEG_D2R_P<5>
=PEG_D2R_P<6>
=PEG_D2R_P<7>
=PEG_D2R_P<8>
=PEG_D2R_P<9>
=PEG_D2R_P<10>
=PEG_D2R_P<11>
=PEG_D2R_P<12>
=PEG_D2R_P<13>
=PEG_D2R_P<14>
=PEG_D2R_P<15>
=PEG_R2D_C_N<0>
=PEG_R2D_C_N<1>
=PEG_R2D_C_N<2>
=PEG_R2D_C_N<3>
=PEG_R2D_C_N<4>
=PEG_R2D_C_N<5>
=PEG_R2D_C_N<6>
=PEG_R2D_C_N<7>
=PEG_R2D_C_N<8>
=PEG_R2D_C_N<9>
=PEG_R2D_C_N<10>
=PEG_R2D_C_N<11>
=PEG_R2D_C_N<12>
=PEG_R2D_C_N<13>
=PEG_R2D_C_N<14>
=PEG_R2D_C_N<15>
=PEG_R2D_C_P<0>
=PEG_R2D_C_P<1>
=PEG_R2D_C_P<2>
=PEG_R2D_C_P<3>
=PEG_R2D_C_P<4>
=PEG_R2D_C_P<5>
=PEG_R2D_C_P<6>
=PEG_R2D_C_P<7>
=PEG_R2D_C_P<8>
=PEG_R2D_C_P<9>
=PEG_R2D_C_P<10>
=PEG_R2D_C_P<11>
=PEG_R2D_C_P<12>
=PEG_R2D_C_P<13>
=PEG_R2D_C_P<14>
=PEG_R2D_C_P<15>
R1010
24.9
21
=PP1V05_S0_CPU_VCCIO
1%
1/16W
MF-LF
402
6
IN
6
IN
6
IN
6
IN
6
IN
6
IN
6
IN
6
IN
6
IN
6
IN
6
IN
6
IN
8
IN
8
IN
8
IN
8
IN
6
IN
6
IN
6
IN
6
IN
6
IN
6
IN
6
IN
6
IN
6
IN
6
IN
6
IN
6
IN
8
IN
8
IN
8
IN
8
IN
6
OUT
6
OUT
6
OUT
6
OUT
6
OUT
6
OUT
6
OUT
6
OUT
6
OUT
6
OUT
6
OUT
6
OUT
8
OUT
8
OUT
8
OUT
8
OUT
6
OUT
6
OUT
6
OUT
6
OUT
6
OUT
6
OUT
6
OUT
6
OUT
6
OUT
6
OUT
6
OUT
6
OUT
8
OUT
8
OUT
8
OUT
8
OUT
7 9
10 12 14
PLACE_NEAR=U1000.H43:50.8MM
PLACE_SIDE=BOTTOM
=PPVCORE_S0_CPU
NOSTUFF
R1064
NOSTUFF
R1065
NOTE: Intel validation sense lines per
doc 439028 rev1.0 HR_PPDG sections 6.2.1 and 6.3.1.
=PPVCORE_S0_CPU_VCCAXG
NOSTUFF
1
1
49.9
49.9
R1070
49.9
1%
1/16W
MF-LF
1/16W
MF-LF
1%
1/16W
MF-LF
402
402
2
2
PLACE_NEAR=U1000.H45:50.8MM
PLACE_SIDE=BOTTOM
Note. VOLTAGE=1.25V
Note. VOLTAGE=0V
Note. VOLTAGE=1.05V
Note. VOLTAGE=0V
NOSTUFF
1
1
R1071
49.9
1%
1%
1/16W
MF-LF
402
402
2
2
PLACE_NEAR=U1000.K45:50.8MM
PLACE_SIDE=BOTTOM
PLACE_NEAR=U1000.K43:50.8MM
PLACE_SIDE=BOTTOM
7
12 14
7
12 15
NOTE: Intel does not recommend to use
this alnalog sense due to accuracy concern.
CPU_CFG<0>
9
23 78
IN
CPU_CFG<1>
9
23 78
IN
CPU_CFG<2>
9
23 78
IN
CPU_CFG<3>
9
23 78
IN
CPU_CFG<4>
9
23 78
IN
CPU_CFG<5>
9
23 78
IN
CPU_CFG<6>
9
23 78
IN
CPU_CFG<7>
9
23 78
IN
CPU_CFG<8>
23 78
IN
CPU_CFG<9>
23 78
IN
CPU_CFG<10>
23 78
IN
CPU_CFG<11>
23 78
IN
CPU_CFG<12>
23
IN
78
CPU_CFG<13>
23 78
IN
CPU_CFG<14>
23 78
IN
CPU_CFG<15>
23 78
IN
CPU_CFG<16>
9
23
IN
CPU_CFG<17>
23
IN
CPU_VCC_VALSENSE_P
CPU_VCC_VALSENSE_N
CPU_AXG_VALSENSE_P
CPU_AXG_VALSENSE_N
TP_CPU_VCC_DIE_SENSE
CPU_THERMD_P
8
85
OUT
CPU_THERMD_N
8
85
OUT
B50
C51
B54
D53
A51
C53
C55
H49
A55
H51
K49
K53
F53
G53
L51
F51
D52
L53
H43
K43
H45
K45
F48
H48
K48
BA19
NC
AV19
NC
AT21
NC
BB21
NC
BB19
NC
AY21
NC
BA22
NC
AY22
NC
AU19
NC
AU21
NC
BD21
NC
BD22
NC
BD25
NC
BD26
NC
BG22
NC
BE22
NC
BG26
NC
BE26
NC
BF23
NC
BE24
NC
OMIT_TABLE
CRITICAL
CFG_0
CFG_1
CFG_2
CFG_3
CFG_4
CFG_5
CFG_6
CFG_7
CFG_8
CFG_9
CFG_10
CFG_11
CFG_12
CFG_13
CFG_14
CFG_15
CFG_16
CFG_17
VCC_VAL_SENSE
VSS_VAL_SENSE
VAXG_VAL_SENSE
VSSAXG_VAL_SENSE
U1000
VCC_DIE_SENSE
RSVD_6
RSVD_7
RSVD_8
RSVD_9
RSVD_10
RSVD_11
RSVD_12
RSVD_13
RSVD_14
RSVD_15
RSVD_16
RSVD_17
RSVD_18
RSVD_19
RSVD_20
RSVD_21
RSVD_22
RSVD_23
RSVD_24
RSVD_25
RSVD_26
RSVD_27
SA_DIMM_VREFDQ
SB_DIMM_VREFDQ
BGA
(5 OF 9)
RESERVED
2C-35W
IVY-BRIDGE
RSVD_30
RSVD_31
RSVD_32
RSVD_33
RSVD_34
RSVD_35
RSVD_36
RSVD_37
RSVD_38
RSVD_39
RSVD_40
RSVD_41
RSVD_42
RSVD_43
RSVD_44
RSVD_45
DC_TEST_A4
DC_TEST_C4
DC_TEST_D3
DC_TEST_D1
DC_TEST_A58
DC_TEST_A59
DC_TEST_C59
DC_TEST_A61
DC_TEST_C61
DC_TEST_D61
DC_TEST_BD61
DC_TEST_BE61
DC_TEST_BE59
DC_TEST_BG61
DC_TEST_BG59
DC_TEST_BG58
DC_TEST_BG4
DC_TEST_BG3
DC_TEST_BE3
DC_TEST_BG1
DC_TEST_BE1
DC_TEST_BD1
MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.2 MM
BE7
BG7
N42
L42
L45
L47
M13
M14
U14
W14
P13
AT49
K24
AH2
AG13
AM14
AM15
N50
A4
C4
D3
D1
A58
A59
C59
A61
C61
D61
BD61
BE61
BE59
BG61
BG59
BG58
BG4
BG3
BE3
BG1
BE1
BD1
VOLTAGE=0.75V
PPCPU_MEM_VREFDQ_A
PPCPU_MEM_VREFDQ_B
MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.2 MM
NC
VOLTAGE=0.75V
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
TP_CPU_DC_TEST_A4
CPU_DC_TEST_C4_D3
TP_CPU_DC_TEST_D1
TP_CPU_DC_TEST_A58
CPU_DC_TEST_C59_A59
CPU_DC_TEST_C61_A61
TP_CPU_DC_TEST_D61
TP_CPU_DC_TEST_BD61
CPU_DC_TEST_BE59_BE61
CPU_DC_TEST_BG59_BG61
TP_CPU_DC_TEST_BG58
TP_CPU_DC_TEST_BG4
CPU_DC_TEST_C4_BE3_BG3
CPU_DC_TEST_C4_BE1_BG1
TP_CPU_DC_TEST_BD1
31
OUT
31
OUT
D
C
B
CPU_CFG<16>
9
CPU_CFG<7>
9
23 78
CPU_CFG<6>
9
23 78
CPU_CFG<5>
9
23 78
CPU_CFG<4>
9
23 78
CPU_CFG<2>
9
23 78
EDP
1
R1042
1/20W
A
1
R1044
1K
1K
5%
5%
1/20W
MF
MF
201
201
2
2
NOSTUFF
R1045
NOSTUFF
NOSTUFF
1
1
R1046
1K
5%
1/20W
1/20W
MF
201
201
2
1
R1047
1K
1K
5%
5%
1/20W
MF
MF
201
2
2
FOR IVYBRIDGE PROCESSOR
CFG [7] :PEG DEFER TRAINING 1 = (DEFAULT) IMMEDIATELY AFTER xxRESETB 0 = WAIT FOR BIOS
CFG [6:5] :PCIE BIFURCATION 11 = 1 X16 (DEFAULT) 10 = 2 X8 01 = RSVD 00 = X8, X4, X4
CFG [4] :eDP ENABLE/DISABLE 1 = DISABLED 0 = ENABLED
CFG [3] :PCIE x4 LANE REVERSAL 1 = NORMAL OPERATION 0 = LANES REVERSED
CFG [2] :PCIE x16 LANE REVERSAL 1 = NORMAL OPERATION 0 = LANES REVERSED
23
CPU_CFG<3>
9
23 78
CPU_CFG<1>
9
23 78
CPU_CFG<0>
9
23 78
R1040
NOSTUFF
1
1K
5%
1/20W
MF
201
2
NOSTUFF
These can be Placed close to J2500 and Only for debug access
R1041
NOSTUFF
R1043
1
1K
5%
1/20W
MF
201
2
1
1K
5%
1/20W
MF
201
2
NOSTUFF
1
R1049
1K
5%
1/20W
MF
201
2
6 3
SYNC_MASTER=MASTER
PAGE TITLE
CPU DMI/PEG/FDI/RSVD
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
SYNC_DATE=02/15/2011
DRAWING NUMBER
051-9058
REVISION
6.0.0
BRANCH
PAGE
10 OF 109
SHEET
9 OF 86
124578
SIZE
A
D
8 7 6 5 4 3
12
D
=PP1V05_S0_CPU_VCCIO
7 9
10 12 14
NOSTUFF
1
R1100
1
R1101
62
5%
1/20W
MF
201
2
C
R1103
56
45 46 68 78
=PP1V5_S3_CPU_VCCDDR
7
12 15 26
PM_MEM_PWRGD
17 26 78
IN
=PP1V05_S0_CPU_VCCIO
7 9
10 12 14
CPU_PROCHOT_L
BI
R1120
1/16W
MF-LF
200
1
1%
402
2
2 1
5%
1/20W
MF
201
R1121
2 1
130
1/16W
MF-LF
CPU_PROCHOT_R_L
1%
402
19
OUT
45 78
OUT
19 46 78
BI
19 46 78
OUT
17 78
IN
19 23 78
IN
26
OUT
1K
5%
1/20W
MF
201
2
CPU_PROC_SEL_L
CPU_CATERR_L
CPU_PECI
PM_THRMTRIP_L
PM_SYNC
CPU_PWRGD
PM_MEM_PWRGD_R
PLT_RESET_LS1V1_L
=MEM_RESET_L
78
78
78
NOSTUFF
1
1
R1104
51
5%
1/20W
MF
201
2
2
CPU_SM_RCOMP<0>
CPU_SM_RCOMP<1>
CPU_SM_RCOMP<2>
NOSTUFF
R1102
1K
5%
1/20W
201
MF
C57
PROC_DETECT*
NC
F49
PROC_SELECT*
C49
CATERR*
A48
PECI
C45
PROCHOT*
D45
THERMTRIP*
C48
PM_SYNC
B46
UNCOREPWRGOOD
BE45
SM_DRAMPWROK
D44
RESET*
AT30
SM_DRAMRST*
BF44
SM_RCOMP_0
BE43
SM_RCOMP_1
BG43
SM_RCOMP_2
OMIT_TABLE
CRITICAL
U1000
IVY-BRIDGE
2C-35W
BGA
(2 OF 9)
THERMAL
PWR MGMT
DDR3 MISC
DPLL_REF_CLK
DPLL_REF_CLK*
BCLK_ITP
CLOCKS
BCLK_ITP*
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
JTAG & BPM
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
BCLK
BCLK*
PRDY*
PREQ*
TRST*
DBR*
BPM_0*
BPM_1*
BPM_2*
BPM_3*
BPM_4*
BPM_5*
BPM_6*
BPM_7*
TCK
TMS
TDI
TDO
J3
H2
AG3
AG1
N59
N58
N53
N55
L56
L55
J58
M60
L59
K58
G58
E55
E59
G55
G59
H60
J59
J61
DMI_CLK100M_CPU_P
DMI_CLK100M_CPU_N
DPLL_REF_CLK_P
DPLL_REF_CLK_N
ITPCPU_CLK100M_P
ITPCPU_CLK100M_N
XDP_CPU_PRDY_L
XDP_CPU_PREQ_L
XDP_CPU_TCK
XDP_CPU_TMS
XDP_CPU_TRST_L
XDP_CPU_TDI
XDP_CPU_TDO
XDP_DBRESET_L
XDP_BPM_L<0>
XDP_BPM_L<1>
XDP_BPM_L<2>
XDP_BPM_L<3>
XDP_BPM_L<4>
XDP_BPM_L<5>
XDP_BPM_L<6>
XDP_BPM_L<7>
16 78
IN
16 78
IN
8
IN
8
IN
16 78
IN
16 78
IN
23 78
OUT
23 78
IN
23 78
IN
23 78
IN
23 78
IN
23 78
IN
23 78
OUT
23 24 78
OUT
23 78
BI
23 78
BI
23 78
BI
23 78
BI
23
BI
23
BI
23
BI
23
BI
D
C
1
1
B
CPU_RESET_L
23 24
IN
R1126
1/16W
MF-LF
75
1%
402
2
R1125
43.2
2 1
1%
1/20W
MF
201
R1112
140
1%
1/16W
MF-LF
402
2
R1113
25.5
2
R1114
200
1%
1%
1/16W
1/16W
MF-LF
MF-LF
402
402
2
1
1
A
6 3
1
R1111
10K
5%
1/20W
MF
201
2
SYNC_MASTER=MASTER
PAGE TITLE
CPU CLOCK/MISC/JTAG
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
SYNC_DATE=02/15/2011
DRAWING NUMBER
051-9058
REVISION
6.0.0
BRANCH
PAGE
11 OF 109
SHEET
10 OF 86
124578
SIZE
B
A
D
8 7 6 5 4 3
12
OMIT_TABLE
CRITICAL
MEM_A_DQ<0>
28 79
BI
MEM_A_DQ<1>
28 79
BI
MEM_A_DQ<2>
28 79
BI
MEM_A_DQ<3>
28 79
BI
MEM_A_DQ<4>
28 79
D
C
B
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
27 79
OUT
27 79
OUT
27 79
OUT
27 79
OUT
27 79
OUT
27 79
OUT
MEM_A_DQ<5>
MEM_A_DQ<6>
MEM_A_DQ<7>
MEM_A_DQ<8>
MEM_A_DQ<9>
MEM_A_DQ<10>
MEM_A_DQ<11>
MEM_A_DQ<12>
MEM_A_DQ<13>
MEM_A_DQ<14>
MEM_A_DQ<15>
MEM_A_DQ<16>
MEM_A_DQ<17>
MEM_A_DQ<18>
MEM_A_DQ<19>
MEM_A_DQ<20>
MEM_A_DQ<21>
MEM_A_DQ<22>
MEM_A_DQ<23>
MEM_A_DQ<24>
MEM_A_DQ<25>
MEM_A_DQ<26>
MEM_A_DQ<27>
MEM_A_DQ<28>
MEM_A_DQ<29>
MEM_A_DQ<30>
MEM_A_DQ<31>
MEM_A_DQ<32>
MEM_A_DQ<33>
MEM_A_DQ<34>
MEM_A_DQ<35>
MEM_A_DQ<36>
MEM_A_DQ<37>
MEM_A_DQ<38>
MEM_A_DQ<39>
MEM_A_DQ<40>
MEM_A_DQ<41>
MEM_A_DQ<42>
MEM_A_DQ<43>
MEM_A_DQ<44>
MEM_A_DQ<45>
MEM_A_DQ<46>
MEM_A_DQ<47>
MEM_A_DQ<48>
MEM_A_DQ<49>
MEM_A_DQ<50>
MEM_A_DQ<51>
MEM_A_DQ<52>
MEM_A_DQ<53>
MEM_A_DQ<54>
MEM_A_DQ<55>
MEM_A_DQ<56>
MEM_A_DQ<57>
MEM_A_DQ<58>
MEM_A_DQ<59>
MEM_A_DQ<60>
MEM_A_DQ<61>
MEM_A_DQ<62>
MEM_A_DQ<63>
MEM_A_BA<0>
MEM_A_BA<1>
MEM_A_BA<2>
MEM_A_CAS_L
MEM_A_RAS_L
MEM_A_WE_L
AG6
AJ6
AP11
AL6
AJ10
AJ8
AL8
AL7
AR11
AP6
AU6
AV9
AR6
AP8
AT13
AU13
BC7
BB7
BA13
BB11
BA7
BA9
BB9
AY13
AV14
AR14
AY17
AR19
BA14
AU14
BB14
BB17
BA45
AR43
AW48
BC48
BC45
AR45
AT48
AY48
BA49
AV49
BB51
AY53
BB49
AU49
BA53
BB55
BA55
AV56
AP50
AP53
AV54
AT54
AP56
AP52
AN57
AN53
AG56
AG53
AN55
AN52
AG55
AK56
BD37
BF36
BA28
BE39
BD39
AT41
SA_DQ_0
SA_DQ_1
SA_DQ_2
SA_DQ_3
SA_DQ_4
SA_DQ_5
SA_DQ_6
SA_DQ_7
SA_DQ_8
SA_DQ_9
SA_DQ_10
SA_DQ_11
SA_DQ_12
SA_DQ_13
SA_DQ_14
SA_DQ_15
SA_DQ_16
SA_DQ_17
SA_DQ_18
SA_DQ_19
SA_DQ_20
SA_DQ_21
SA_DQ_22
SA_DQ_23
SA_DQ_24
SA_DQ_25
SA_DQ_26
SA_DQ_27
SA_DQ_28
SA_DQ_29
SA_DQ_30
SA_DQ_31
SA_DQ_32
SA_DQ_33
SA_DQ_34
SA_DQ_35
SA_DQ_36
SA_DQ_37
SA_DQ_38
SA_DQ_39
SA_DQ_40
SA_DQ_41
SA_DQ_42
SA_DQ_43
SA_DQ_44
SA_DQ_45
SA_DQ_46
SA_DQ_47
SA_DQ_48
SA_DQ_49
SA_DQ_50
SA_DQ_51
SA_DQ_52
SA_DQ_53
SA_DQ_54
SA_DQ_55
SA_DQ_56
SA_DQ_57
SA_DQ_58
SA_DQ_59
SA_DQ_60
SA_DQ_61
SA_DQ_62
SA_DQ_63
SA_BS_0
SA_BS_1
SA_BS_2
SA_CAS*
SA_RAS*
SA_WE*
U1000
BGA
(3 OF 9)
2C-35W
IVY-BRIDGE
MEMORY CHANNEL A
SA_CK_0
SA_CK_0*
SA_CKE_0
SA_CK_1
SA_CK_1*
SA_CKE_1
SA_CS_0*
SA_CS_1*
SA_ODT_0
SA_ODT_1
SA_DQS_0*
SA_DQS_1*
SA_DQS_2*
SA_DQS_3*
SA_DQS_4*
SA_DQS_5*
SA_DQS_6*
SA_DQS_7*
SA_DQS_0
SA_DQS_1
SA_DQS_2
SA_DQS_3
SA_DQS_4
SA_DQS_5
SA_DQS_6
SA_DQS_7
SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8
SA_MA_9
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13
SA_MA_14
SA_MA_15
AU36
AV36
AY26
AT40
AU40
BB26
BB40
BC41
AY40
BA41
AL11
AR8
AV11
AT17
AV45
AY51
AT55
AK55
AJ11
AR10
AY11
AU17
AW45
AV51
AT56
AK54
BG35
BB34
BE35
BD35
AT34
AU34
BB32
AT32
AY32
AV32
BE37
BA30
BC30
AW41
AY28
AU26
MEM_A_CLK_P<0>
MEM_A_CLK_N<0>
MEM_A_CKE<0>
MEM_A_CLK_P<1>
MEM_A_CLK_N<1>
MEM_A_CKE<1>
MEM_A_CS_L<0>
MEM_A_CS_L<1>
MEM_A_ODT<0>
MEM_A_ODT<1>
MEM_A_DQS_N<0>
MEM_A_DQS_N<1>
MEM_A_DQS_N<2>
MEM_A_DQS_N<3>
MEM_A_DQS_N<4>
MEM_A_DQS_N<5>
MEM_A_DQS_N<6>
MEM_A_DQS_N<7>
MEM_A_DQS_P<0>
MEM_A_DQS_P<1>
MEM_A_DQS_P<2>
MEM_A_DQS_P<3>
MEM_A_DQS_P<4>
MEM_A_DQS_P<5>
MEM_A_DQS_P<6>
MEM_A_DQS_P<7>
MEM_A_A<0>
MEM_A_A<1>
MEM_A_A<2>
MEM_A_A<3>
MEM_A_A<4>
MEM_A_A<5>
MEM_A_A<6>
MEM_A_A<7>
MEM_A_A<8>
MEM_A_A<9>
MEM_A_A<10>
MEM_A_A<11>
MEM_A_A<12>
MEM_A_A<13>
MEM_A_A<14>
MEM_A_A<15>
MEM_B_DQ<0>
27 79
OUT
27 79
OUT
27 79
OUT
27 79
OUT
27 79
OUT
27 79
OUT
27 79
OUT
27 79
OUT
27 79
OUT
27 79
OUT
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
27 79
OUT
27 79
OUT
27 79
OUT
27 79
OUT
27 79
OUT
27 79
OUT
27 79
OUT
27 79
OUT
27 79
OUT
27 79
OUT
27 79
OUT
27 79
OUT
27 79
OUT
27 79
OUT
27 79
OUT
27 79
OUT
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
29 79
OUT
29 79
OUT
29 79
OUT
29 79
OUT
29 79
OUT
29 79
OUT
MEM_B_DQ<1>
MEM_B_DQ<2>
MEM_B_DQ<3>
MEM_B_DQ<4>
MEM_B_DQ<5>
MEM_B_DQ<6>
MEM_B_DQ<7>
MEM_B_DQ<8>
MEM_B_DQ<9>
MEM_B_DQ<10>
MEM_B_DQ<11>
MEM_B_DQ<12>
MEM_B_DQ<13>
MEM_B_DQ<14>
MEM_B_DQ<15>
MEM_B_DQ<16>
MEM_B_DQ<17>
MEM_B_DQ<18>
MEM_B_DQ<19>
MEM_B_DQ<20>
MEM_B_DQ<21>
MEM_B_DQ<22>
MEM_B_DQ<23>
MEM_B_DQ<24>
MEM_B_DQ<25>
MEM_B_DQ<26>
MEM_B_DQ<27>
MEM_B_DQ<28>
MEM_B_DQ<29>
MEM_B_DQ<30>
MEM_B_DQ<31>
MEM_B_DQ<32>
MEM_B_DQ<33>
MEM_B_DQ<34>
MEM_B_DQ<35>
MEM_B_DQ<36>
MEM_B_DQ<37>
MEM_B_DQ<38>
MEM_B_DQ<39>
MEM_B_DQ<40>
MEM_B_DQ<41>
MEM_B_DQ<42>
MEM_B_DQ<43>
MEM_B_DQ<44>
MEM_B_DQ<45>
MEM_B_DQ<46>
MEM_B_DQ<47>
MEM_B_DQ<48>
MEM_B_DQ<49>
MEM_B_DQ<50>
MEM_B_DQ<51>
MEM_B_DQ<52>
MEM_B_DQ<53>
MEM_B_DQ<54>
MEM_B_DQ<55>
MEM_B_DQ<56>
MEM_B_DQ<57>
MEM_B_DQ<58>
MEM_B_DQ<59>
MEM_B_DQ<60>
MEM_B_DQ<61>
MEM_B_DQ<62>
MEM_B_DQ<63>
MEM_B_BA<0>
MEM_B_BA<1>
MEM_B_BA<2>
MEM_B_CAS_L
MEM_B_RAS_L
MEM_B_WE_L
AL4
AL1
AN3
AR4
AK4
AK3
AN4
AR1
AU4
AT2
AV4
BA4
AU3
AR3
AY2
BA3
BE9
BD9
BD13
BF12
BF8
BD10
BD14
BE13
BF16
BE17
BE18
BE21
BE14
BG14
BG18
BF19
BD50
BF48
BD53
BF52
BD49
BE49
BD54
BE53
BF56
BE57
BC59
AY60
BE54
BG54
BA58
AW59
AW58
AU58
AN61
AN59
AU59
AU61
AN58
AR58
AK58
AL58
AG58
AG59
AM60
AL59
AF61
AH60
BG39
BD42
AT22
AV43
BF40
BD45
SB_DQ_0
SB_DQ_1
SB_DQ_2
SB_DQ_3
SB_DQ_4
SB_DQ_5
SB_DQ_6
SB_DQ_7
SB_DQ_8
SB_DQ_9
SB_DQ_10
SB_DQ_11
SB_DQ_12
SB_DQ_13
SB_DQ_14
SB_DQ_15
SB_DQ_16
SB_DQ_17
SB_DQ_18
SB_DQ_19
SB_DQ_20
SB_DQ_21
SB_DQ_22
SB_DQ_23
SB_DQ_24
SB_DQ_25
SB_DQ_26
SB_DQ_27
SB_DQ_28
SB_DQ_29
SB_DQ_30
SB_DQ_31
SB_DQ_32
SB_DQ_33
SB_DQ_34
SB_DQ_35
SB_DQ_36
SB_DQ_37
SB_DQ_38
SB_DQ_39
SB_DQ_40
SB_DQ_41
SB_DQ_42
SB_DQ_43
SB_DQ_44
SB_DQ_45
SB_DQ_46
SB_DQ_47
SB_DQ_48
SB_DQ_49
SB_DQ_50
SB_DQ_51
SB_DQ_52
SB_DQ_53
SB_DQ_54
SB_DQ_55
SB_DQ_56
SB_DQ_57
SB_DQ_58
SB_DQ_59
SB_DQ_60
SB_DQ_61
SB_DQ_62
SB_DQ_63
SB_BS_0
SB_BS_1
SB_BS_2
SB_CAS*
SB_RAS*
SB_WE*
OMIT_TABLE
CRITICAL
2C-35W
SB_CK_0
SB_CK_0*
SB_CKE_0
SB_CK_1
SB_CK_1*
U1000
BGA
(4 OF 9)
SB_CKE_1
IVY-BRIDGE
SB_CS_0*
SB_CS_1*
SB_ODT_0
SB_ODT_1
SB_DQS_0*
SB_DQS_1*
SB_DQS_2*
SB_DQS_3*
SB_DQS_4*
SB_DQS_5*
SB_DQS_6*
SB_DQS_7*
SB_DQS_0
MEMORY CHANNEL B
SB_DQS_1
SB_DQS_2
SB_DQS_3
SB_DQS_4
SB_DQS_5
SB_DQS_6
SB_DQS_7
SB_MA_0
SB_MA_1
SB_MA_2
SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8
SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13
SB_MA_14
SB_MA_15
BA34
AY34
AR22
BA36
BB36
BF27
BE41
BE47
AT43
BG47
AL3
AV3
BG11
BD17
BG51
BA59
AT60
AK59
AM2
AV1
BE11
BD18
BE51
BA61
AR59
AK61
BF32
BE33
BD33
AU30
BD30
AV30
BG30
BD29
BE30
BE28
BD43
AT28
AV28
BD46
AT26
AU22
MEM_B_CLK_P<0>
MEM_B_CLK_N<0>
MEM_B_CKE<0>
MEM_B_CLK_P<1>
MEM_B_CLK_N<1>
MEM_B_CKE<1>
MEM_B_CS_L<0>
MEM_B_CS_L<1>
MEM_B_ODT<0>
MEM_B_ODT<1>
MEM_B_DQS_N<0>
MEM_B_DQS_N<1>
MEM_B_DQS_N<2>
MEM_B_DQS_N<3>
MEM_B_DQS_N<4>
MEM_B_DQS_N<5>
MEM_B_DQS_N<6>
MEM_B_DQS_N<7>
MEM_B_DQS_P<0>
MEM_B_DQS_P<1>
MEM_B_DQS_P<2>
MEM_B_DQS_P<3>
MEM_B_DQS_P<4>
MEM_B_DQS_P<5>
MEM_B_DQS_P<6>
MEM_B_DQS_P<7>
MEM_B_A<0>
MEM_B_A<1>
MEM_B_A<2>
MEM_B_A<3>
MEM_B_A<4>
MEM_B_A<5>
MEM_B_A<6>
MEM_B_A<7>
MEM_B_A<8>
MEM_B_A<9>
MEM_B_A<10>
MEM_B_A<11>
MEM_B_A<12>
MEM_B_A<13>
MEM_B_A<14>
MEM_B_A<15>
29 79
OUT
29 79
OUT
29 79
OUT
29 79
OUT
29 79
OUT
29 79
OUT
29 79
OUT
29 79
OUT
29 79
OUT
29 79
OUT
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
29 79
OUT
29 79
OUT
29 79
OUT
29 79
OUT
29 79
OUT
29 79
OUT
29 79
OUT
29 79
OUT
29 79
OUT
29 79
OUT
29 79
OUT
29 79
OUT
29 79
OUT
29 79
OUT
29 79
OUT
29 79
OUT
D
C
B
A
6 3
SYNC_MASTER=MASTER
PAGE TITLE
CPU DDR3 INTERFACES
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
SYNC_DATE=02/15/2011
DRAWING NUMBER
051-9058
REVISION
6.0.0
BRANCH
PAGE
12 OF 109
SHEET
11 OF 86
124578
SIZE
A
D
8 7 6 5 4 3
12
=PPVCORE_S0_CPU_VCCAXG
7 9
12 15
=PPVCORE_S0_CPU
7 9
12 14
A26
VCC_1
A29
D
C
B
A31
A34
A35
A38
A39
A42
C26
C27
C32
C34
C37
C39
C42
D27
D32
D34
D37
D39
D42
E26
E28
E32
E34
E37
E38
F25
F26
F28
F32
F34
F37
F38
F42
G42
H25
H26
H28
H29
H32
H34
H35
H37
H38
H40
J25
J26
J28
J29
J32
J34
J35
J37
J38
J40
J42
K26
K27
K29
K32
K34
K35
K37
K39
K42
L25
L28
L33
L36
L40
N26
N30
N34
N38
VCC_2
VCC_3
VCC_4
VCC_5
VCC_6
VCC_7
VCC_8
VCC_9
VCC_10
VCC_11
VCC_12
VCC_13
VCC_14
VCC_15
VCC_16
VCC_17
VCC_18
VCC_19
VCC_20
VCC_21
VCC_22
VCC_23
VCC_24
VCC_25
VCC_26
VCC_27
VCC_28
VCC_29
VCC_30
VCC_31
VCC_32
VCC_33
VCC_34
VCC_35
VCC_36
VCC_37
VCC_38
VCC_39
VCC_40
VCC_41
VCC_42
VCC_43
VCC_44
VCC_45
VCC_46
VCC_47
VCC_48
VCC_49
VCC_50
VCC_51
VCC_52
VCC_53
VCC_54
VCC_55
VCC_56
VCC_57
VCC_58
VCC_59
VCC_60
VCC_61
VCC_62
VCC_63
VCC_64
VCC_66
VCC_67
VCC_68
VCC_69
VCC_70
VCC_71
VCC_72
VCC_73
VCC_74
VCC_75
VCC_76
A
OMIT_TABLE
CRITICAL
U1000
BGA
(6 OF 9)
IVY-BRIDGE
PEG AND DDR
CORE SUPLLY
VSS_SENSE_VCCIO
2C-35W
RAIL
LINES
SENSE SVID QUIET
VCCIO_SENSE
VCCIO_1
VCCIO_3
VCCIO_4
VCCIO_5
VCCIO_6
VCCIO_7
VCCIO_8
VCCIO_9
VCCIO_10
VCCIO_11
VCCIO_12
VCCIO_13
VCCIO_14
VCCIO_15
VCCIO_16
VCCIO_17
VCCIO_18
VCCIO_19
VCCIO_20
VCCIO_21
VCCIO_22
VCCIO_23
VCCIO_24
VCCIO_25
VCCIO_26
VCCIO_27
VCCIO_28
VCCIO_29
VCCIO_30
VCCIO_31
VCCIO_32
VCCIO_33
VCCIO_34
VCCIO_35
VCCIO_36
VCCIO_37
VCCIO_38
VCCIO_39
VCCIO_40
VCCIO_41
VCCIO_42
VCCIO_43
VCCIO_44
VCCIO_45
VCCIO_46
VCCIO_47
VCCIO_48
VCCIO_49
VCCIO_50
VCCIO_51
VCCIO_SEL
VCCPQE_1
VCCPQE_2
VIDALERT*
VIDSCLK
VIDSOUT
VCC_SENSE
VSS_SENSE
=PP1V05_S0_CPU_VCCIO
(NOT controlled by VCCIO_SEL)
Fixed at 1.05V
AF46
AG48
AG50
AG51
AJ17
AJ21
AJ25
AJ43
AJ47
AK50
AK51
AL14
AL15
AL16
AL20
AL22
AL26
AL45
AL48
AM16
AM17
AM21
AM43
AM47
AN20
AN42
AN45
AN48
AA14
AA15
AB17
AB20
AC13
AD16
AD18
AD21
AE14
AE15
AF16
AF18
AF20
AG15
AG16
AG17
AG20
AG21
AJ14
AJ15
W16
W17
IVB supports 1.05V VCCIO.
VCCIO_SEL can be NC.
BC22
CPU_VCCIO_SEL
AM25
=PP1V05_S0_CPU_VCCPQE
AN22
A44
B43
C44
F43
G43
AN16
AN17
CPU_VIDALERT_L_R
CPU_VIDSCLK_R
CPU_VIDSOUT_R
CPU_VCCSENSE_P
CPU_VCCSENSE_N
CPU_VCCIOSENSE_P
CPU_VCCIOSENSE_N
AA46
VAXG_1
AB47
VAXG_2
AB50
VAXG_3
AB51
VAXG_4
AB52
VAXG_5
AB53
VAXG_6
AB55
VAXG_7
AB56
VAXG_8
AB58
VAXG_9
AB59
VAXG_10
AC61
VAXG_11
AD47
VAXG_12
AD48
VAXG_13
AD50
VAXG_14
AD51
VAXG_15
AD52
VAXG_16
AD53
VAXG_17
AD55
VAXG_18
AD56
VAXG_19
AD58
VAXG_20
AD59
VAXG_21
AE46
VAXG_22
N45
VAXG_23
P47
VAXG_24
P48
VAXG_25
P50
VAXG_26
P51
VAXG_27
P52
VAXG_28
P53
VAXG_29
P55
VAXG_30
P56
VAXG_31
P61
VAXG_32
T48
VAXG_33
T58
VAXG_34
T59
VAXG_35
T61
VAXG_36
U46
VAXG_37
V47
VAXG_38
V48
VAXG_39
V50
VAXG_40
V51
VAXG_41
V52
VAXG_42
V53
VAXG_43
V55
VAXG_44
V56
VAXG_45
V58
VAXG_46
V59
VAXG_47
W50
=PP1V05_S0_CPU_VCCIO
1
R1302
130
PLACE_NEAR=U1000.C44:2.54mm
1%
1/16W
MF-LF
402
8
78
2
7 8
14
201
201
201
PLACE_NEAR=U1000.F43:50.8mm
Note. VOLTAGE=1.25V
Note. VOLTAGE=0V
Note. VOLTAGE=1.05V
Note. VOLTAGE=0V
PLACE_NEAR=U1000.G43:50.8mm
R1310
1/20W
R1311
1/20W
0
R1312
1/20W
0
PLACE_SIDE=BOTTOM
PLACE_SIDE=BOTTOM
NOSTUFF
R1360
NOSTUFF
R1361
PLACE_NEAR=R1310.2:2.54mm
1
R1300
75
1%
1/20W
MF
201
2
21
MF435%
MF5%
MF5%
CPU_VIDALERT_L
CPU_VIDSCLK
CPU_VIDSOUT
PLACE_NEAR=U1000.A44:38mm
21
21
=PP1V05_S0_CPU_VCCIO
NOSTUFF
1
1
R1362
100
100
1%
1%
1/16W
1/16W
MF-LF
MF-LF
402
402
2
2
NOSTUFF
1
1
R1363
100
100
1%
1%
1/16W
1/16W
MF-LF
MF-LF
402
402
2
2
=PPVCORE_S0_CPU
PLACE_NEAR=U1000.AN16:50.8mm
PLACE_SIDE=BOTTOM
PLACE_NEAR=U1000.AN17:50.8mm
PLACE_SIDE=BOTTOM
7 9
10 12 14
68 78
IN
68 78
OUT
68 78
BI
7 9
12 14
7 9
10 12 14
PLACEMENT NOTE: Please place all sense line resistors on BOTTOM side.
68 78
OUT
68 78
OUT
70 78
OUT
70 78
OUT
=PPVCORE_S0_CPU_VCCAXG
7 9
12 15
PLACE_NEAR=U1000.F45:50.8mm
PLACE_SIDE=BOTTOM
68 78
CPU_AXG_SENSE_P
OUT
68 78
CPU_AXG_SENSE_N
OUT
14
PLACE_NEAR=U1000.G45:50.8mm
PLACE_SIDE=BOTTOM
NOSTUFF
1
R1370
100
1%
1/16W
MF-LF
402
2
Note. VOLTAGE=1.05V
Note. VOLTAGE=0V
=PP1V8_S0_CPU_VCCPLL_R
7
NOSTUFF
R1371
1/16W
MF-LF
100
1%
402
12 15
1
2
=PPVCCSA_S0_CPU
7
VAXG_48
W51
VAXG_49
W52
VAXG_50
W53
VAXG_51
W55
VAXG_52
W56
VAXG_53
W61
VAXG_54
Y48
VAXG_55
Y61
VAXG_56
F45
VAXG_SENSE
G45
VSSAXG_SENSE
BB3
VCCPLL_1
BC1
VCCPLL_2
BC4
VCCPLL_3
L17
VCCSA_1
L21
VCCSA_2
N16
VCCSA_3
N20
VCCSA_4
N22
VCCSA_5
P17
VCCSA_6
P20
VCCSA_7
R16
VCCSA_8
R18
VCCSA_9
R21
VCCSA_10
U15
VCCSA_11
V16
VCCSA_12
V17
VCCSA_13
V18
VCCSA_14
V21
VCCSA_15
W20
VCCSA_16
PLACEMENT NOTE: Please place all sense line resistors on BOTTOM side.
6 3
OMIT_TABLE
CRITICAL
U1000
BGA
(7 OF 9)
IVY-BRIDGE
GRPHICS
DDR3-1.5V RAILS
(IPU)
QUIET
SENSE
(IPU)
LINE
SENSE
1.8V
RAIL
SA RAIL
VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
2C-35W
VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8
VDDQ_9
VDDQ_10
VDDQ_11
VDDQ_12
VDDQ_13
VDDQ_14
VDDQ_15
VDDQ_16
VDDQ_17
VDDQ_18
VDDQ_19
VDDQ_20
VDDQ_21
VDDQ_22
VDDQ_23
VDDQ_24
VDDQ_25
VDDQ_26
VCCDQ_1
VCCDQ_2
RAIL
VDDQ_SENSE
VSS_SENSE_VDDQ
VCCSA_SENSE
LINE
VCCSA_VID_0
VCCSA_VID_1
SM_VREF
=PP1V5_S3_CPU_VCCDDR
AJ28
AJ33
AJ36
AJ40
AL30
AL34
AL38
AL42
AM33
AM36
AM40
AN30
AN34
AN38
AR26
AR28
AR30
AR32
AR34
AR36
AR40
AV41
AW26
BA40
BB28
BG33
AM28
AN26
BC43
BA43
U10
D48
D49
AY43
R1314
=PP1V5_S3_CPU_VCCDQ
CPU_VDDQ_SENSE_P
CPU_VDDQ_SENSE_N
CPU_VCCSASENSE
CPU_VCCSA_VID<0>
CPU_VCCSA_VID<1>
CPU_SM_VREF
VOLTAGE=0.75V
1
1
R1313
10K
10K
1/20W
MF
5%
201
5%
1/20W
MF
201
2
2
=PP1V5_S3_CPU_VCCDDR
7
10 12 15 26
PLACE_NEAR=U1000.U10:50.8mm
PLACE_NEAR=U1000.BC43:50.8mm
PLACE_SIDE=BOTTOM
Note. VOLTAGE=1.05V
Note. VOLTAGE=0V
PLACE_NEAR=U1000.BA43:50.8mm
PLACE_SIDE=BOTTOM
12 15
65
OUT
12
=PPVCCSA_S0_CPU
7
R1382
1
R1380
100
1%
1/16W
MF-LF
402
2
7
15
65
1
R1381
100
1%
1/16W
MF-LF
402
2
100
1/16W
MF-LF
1
1%
402
2
OUT
PLACEMENT NOTE: Please place all sense line resistors on BOTTOM side.
=PP1V5_S3_CPU_VCCDDR
7
10 12 15 26
1
R1330
PLACE_NEAR=U1000.BJ44:2.54mm
PLACE_NEAR=U1000.BJ44:2.54mm
1/16W
MF-LF
R1331
1/16W
MF-LF
1K
5%
402
2
1
1K
5%
402
2
CPU_SM_VREF
1
C1330
0.1UF
10%
16V
2
X7R-CERM
0402
PLACE_NEAR=U1000.BJ44:2.54mm
SYNC_MASTER=MASTER
PAGE TITLE
CPU POWER
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
SYNC_DATE=02/15/2011
DRAWING NUMBER
051-9058
REVISION
6.0.0
BRANCH
PAGE
13 OF 109
SHEET
12 OF 86
124578
D
C
65
B
12
A
SIZE
D
8 7 6 5 4 3
OMIT_TABLE
OMIT_TABLE
CRITICAL
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
M11
M15
M58
N1
N17
N21
N25
N28
N33
N36
N40
N43
N47
N48
N51
N52
N56
N61
P9
P14
P16
P18
P21
P58
P59
R4
R17
R20
R46
T1
T47
T50
T51
T52
T53
T55
T56
U8
U13
V20
V61
W8
W13
W15
W18
W21
W46
Y4
Y47
Y58
Y59
A5
A57
BC61
BD3
BD59
BE4
BE58
BG5
BG57
C3
C58
D59
E1
E61
BG13
VSS
BG17
VSS
BG21
VSS
BG24
VSS
BG28
VSS
D
C
B
BG37
BG41
BG45
BG49
BG53
C29
C35
C40
D10
D14
D18
D22
D26
D29
D35
D40
D43
D46
D50
D54
D58
E25
E29
E35
E40
F13
F15
F19
F29
F35
F40
F55
G48
G51
G61
H10
H14
H17
H21
H53
H58
J49
J55
K11
K21
K51
L16
L20
L22
L26
L30
L34
L38
L43
L48
L61
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
D4
VSS
D6
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
E3
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
G6
VSS
VSS
VSS
VSS
H4
VSS
VSS
VSS
VSS
VSS
VSS
VSS
J1
VSS
VSS
VSS
K8
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
M4
VSS
M6
VSS
U1000
BGA
(9 OF 9)
VSS
2C-35W
IVY-BRIDGE
A
AA13
AA50
AA51
AA52
AA53
AA55
AA56
AB16
AB18
AB21
AB48
AB61
AC10
AC14
AC46
AD17
AD20
AD61
AE13
AF17
AF21
AF47
AF48
AF50
AF51
AF52
AF53
AF55
AF56
AF58
AF59
AG10
AG14
AG18
AG47
AG52
AG61
AH58
AJ13
AJ16
AJ20
AJ22
AJ26
AJ30
AJ34
AJ38
AJ42
AJ45
AJ48
AK52
AL10
AL13
AL17
AL21
AL25
AL28
AL33
AL36
AL40
AL43
AL47
AL61
AM13
AM20
AM22
AM26
AM30
A13
A17
A21
A25
A28
A33
A37
A40
A45
A49
A53
AA1
AA8
AC6
AD4
AE8
AF1
AG7
AH4
AJ7
AK1
AM4
A9
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
CRITICAL
U1000
BGA
(8 OF 9)
VSS
IVY-BRIDGE
2C-35W
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AM34
AM38
AM42
AM45
AM48
AM58
AN1
AN21
AN25
AN28
AN33
AN36
AN40
AN43
AN47
AN50
AN54
AP7
AP10
AP51
AP55
AR7
AR13
AR17
AR21
AR41
AR48
AR61
AT4
AT14
AT19
AT36
AT45
AT52
AT58
AU1
AU7
AU11
AU28
AU32
AU51
AV17
AV21
AV22
AV34
AV40
AV48
AV55
AW7
AW13
AW43
AW61
AY4
AY9
AY14
AY19
AY30
AY36
AY41
AY45
AY49
AY55
AY58
BA1
BA11
BA17
BA21
BA26
BA32
BA48
BA51
BB53
BC5
BC13
BC57
BD8
BD12
BD16
BD19
BD23
BD27
BD32
BD36
BD40
BD44
BD48
BD52
BD56
BE5
BG9
SYNC_MASTER=MASTER
PAGE TITLE
CPU GROUNDS
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
6 3
12
SYNC_DATE=02/15/2011
DRAWING NUMBER
051-9058
REVISION
6.0.0
BRANCH
PAGE
14 OF 109
SHEET
13 OF 86
124578
SIZE
D
C
B
A
D
8 7 6 5 4 3
All INTEL recommendations from Intel doc #4439028 Huron River Platform Power Design Guide
CPU VCORE DECOUPLING
Intel recommendation (Section 6.2): 35x 2.2uF, 25x 22uF, 4x 470uF
=PPVCORE_S0_CPU
7 9
12
D
CRITICAL
1
C1600
2.2UF
20%
4V
2
X5R
402
CRITICAL
1
C1625
2.2UF
20%
4V
2
X5R
402
CRITICAL
1
2
CRITICAL
1
2
C1604
2.2UF
20%
4V
X5R
402
C1627
2.2UF
20%
4V
X5R
402
CRITICAL
1
C1606
2.2UF
20%
4V
2
X5R
402
CRITICAL
1
C1628
2.2UF
20%
4V
2
X5R
402
CRITICAL
1
C1607
2.2UF
20%
4V
2
X5R
402
CRITICAL
1
C1631
2.2UF
20%
4V
2
X5R
402
CRITICAL
1
C1608
2.2UF
20%
4V
2
X5R
402
CRITICAL
1
C1632
2.2UF
20%
4V
2
X5R
402
CRITICAL
1
C1609
2.2UF
20%
4V
2
X5R
402
CRITICAL
1
C1635
2.2UF
20%
4V
2
X5R
402
CRITICAL
1
C1610
2.2UF
20%
4V
2
X5R
402
CRITICAL
1
C1637
2.2UF
20%
4V
2
X5R
402
CRITICAL
1
C1612
2.2UF
20%
4V
2
X5R
402
CRITICAL
1
C1638
2.2UF
20%
4V
2
X5R
402
CRITICAL
1
C1613
2.2UF
20%
4V
2
X5R
402
CRITICAL
1
C1639
2.2UF
20%
4V
2
X5R
402
CRITICAL
1
C1615
2.2UF
20%
4V
2
X5R
402
CRITICAL
1
C1640
2.2UF
20%
4V
2
X5R
402
CRITICAL
1
C1617
2.2UF
20%
4V
2
X5R
402
CRITICAL
1
C1641
2.2UF
20%
4V
2
X5R
402
CRITICAL
1
C1623
2.2UF
20%
4V
2
X5R
402
CRITICAL
1
C1642
2.2UF
20%
4V
2
X5R
402
CRITICAL
1
C1624
2.2UF
20%
4V
2
X5R
402
CRITICAL
1
C1643
2.2UF
20%
4V
2
X5R
402
CRITICAL
1
C1644
2.2UF
20%
4V
2
X5R
402
CRITICAL
1
C1645
2.2UF
20%
4V
2
X5R
402
CRITICAL
1
C1647
2.2UF
20%
4V
2
X5R
402
CRITICAL
1
C1648
2.2UF
20%
4V
2
X5R
402
12
D
CRITICAL
1
C1650
2.2UF
20%
4V
2
X5R
402
PLACEMENT_NOTE (C1655-C1666):
Place close to U1000 on top side.
CRITICAL
OMIT
1
C1655
22UF
20%
6.3V
2
X5R-CERM-1
603
C
PLACEMENT_NOTE (C1667-C1679):
Place close to U1000 on bottom side.
CRITICAL
OMIT
1
C1667
22UF
20%
6.3V
2
X5R-CERM-1
603
CRITICAL
1
C1651
2.2UF
20%
4V
2
X5R
402
CRITICAL
OMIT
1
C1656
22UF
20%
6.3V
2
X5R-CERM-1
603
CRITICAL
OMIT
1
C1668
22UF
20%
6.3V
2
X5R-CERM-1
603
CRITICAL
1
C1652
2.2UF
20%
4V
2
X5R
402
CRITICAL
OMIT
1
C1657
22UF
20%
6.3V
2
X5R-CERM-1
603
CRITICAL
OMIT
1
C1669
22UF
20%
6.3V
2
X5R-CERM-1
603
CRITICAL
1
C1653
2.2UF
20%
4V
2
X5R
402
CRITICAL
OMIT
1
C1658
22UF
20%
6.3V
2
X5R-CERM-1
603
CRITICAL
OMIT
1
C1670
22UF
20%
6.3V
2
X5R-CERM-1
603
CRITICAL
1
C1654
2.2UF
20%
4V
2
X5R
402
CRITICAL
NOSTUFF
1
C1659
22UF
20%
6.3V
2
X5R-CERM-1
603
CRITICAL
NOSTUFF
1
C1671
22UF
20%
6.3V
2
X5R-CERM-1
603
CRITICAL
OMIT
1
C1660
22UF
20%
6.3V
2
X5R-CERM-1
603
CRITICAL
OMIT
1
C1672
22UF
20%
6.3V
2
X5R-CERM-1
603
CRITICAL
OMIT
1
C1661
22UF
20%
6.3V
2
X5R-CERM-1
603
CRITICAL
NOSTUFF
1
C1673
22UF
20%
6.3V
2
X5R-CERM-1
603
CRITICAL
NOSTUFF
1
C1662
22UF
20%
6.3V
2
X5R-CERM-1
603
CRITICAL
NOSTUFF
1
C1674
22UF
20%
6.3V
2
X5R-CERM-1
603
CRITICAL
NOSTUFF
1
C1663
22UF
20%
6.3V
2
X5R-CERM-1
603
CRITICAL
NOSTUFF
1
C1675
22UF
20%
6.3V
2
X5R-CERM-1
603
CRITICAL
OMIT
1
C1664
22UF
20%
6.3V
2
X5R-CERM-1
603
CRITICAL
NOSTUFF
1
C1676
22UF
20%
6.3V
2
X5R-CERM-1
603
CRITICAL
NOSTUFF
1
C1665
22UF
20%
6.3V
2
X5R-CERM-1
603
CRITICAL
OMIT
1
C1677
22UF
20%
6.3V
2
X5R-CERM-1
603
CRITICAL
OMIT
1
C1666
22UF
20%
6.3V
2
X5R-CERM-1
603
CRITICAL
OMIT
1
C1678
22UF
20%
6.3V
2
X5R-CERM-1
603
CRITICAL
OMIT
1
C1679
22UF
20%
6.3V
2
X5R-CERM-1
603
PART NUMBER
138S0691
QTY
16
DESCRIPTION
CAP,CER,X5R,22uF,20%,6.3V,0603,SAMSUNG
C1655,C1660,C1661,C1664,C1666,C1667,C1670,C1677,C1678,C1679,C1657,C1672,C1658,C1669,C1668,C1656
REFERENCE DES
CRITICAL
CRITICAL
BOM OPTION
C
PLACEMENT_NOTE (C1640-C1645):
Place near inductors on bottom side.
Place near inductors on bottom side.
Place near inductors on bottom side.
Place near inductors on bottom side.
1
3 2
C1680
470UF-4MOHM
20%
2.0V
POLY-TANT
D2T-SM1
1
3 2
C1681
470UF-4MOHM
20%
2.0V
POLY-TANT
D2T-SM1
1
C1682
470UF-4MOHM
3 2
20%
2.0V
POLY-TANT
D2T-SM1
1
3 2
C1683
470UF-4MOHM
20%
2.0V
POLY-TANT
D2T-SM1
CPU VCCIO/VCCPQ DECOUPLING
Intel recommendation (Section 6.5): 26x 1uF, 10x 10uF, 2x 330uF
PLACEMENT_NOTE (C1684-C167F):
Place on bottom side of U1000
Place on bottom side of U100.
Place on bottom side of U1000
=PP1V05_S0_CPU_VCCIO
7 9
10 12
B
Place on bottom side of U1000
1
C1684
1UF
2
1
C1697
1UF
2
10%
10V
X5R
402
10%
10V
X5R
402
1
C1685
1UF
10%
10V
2
X5R
402
1
C1698
1UF
10%
2
X5R
402
10V
1
C1686
2
1
C1699
2
1UF
10%
10V
X5R
402
1UF
10%
10V
X5R
402
1
2
1
C169A
2
C1687
1UF
10%
10V
X5R
402
1UF
10%
10V
X5R
402
1
C1688
2
1
C169B
2
1UF
10%
10V
X5R
402
1UF
10%
10V
X5R
402
1
C1689
1UF
2
1
C169C
1UF
2
1
C1690
10%
10V
X5R
402
10%
10V
X5R
402
2
1
C169D
2
1UF
10%
10V
X5R
402
1UF
10%
10V
X5R
402
1
2
1
2
C1691
1UF
10%
10V
X5R
402
C169E
1UF
10%
10V
X5R
402
1
C1692
1UF
2
1
C169F
1UF
2
1
C1693
10%
10V
X5R
402
10%
10V
X5R
402
2
1
2
1UF
10%
10V
X5R
402
C161A
1UF
10%
10V
X5R
402
1
2
1
2
C1694
1UF
10%
10V
X5R
402
C161B
1UF
10%
10V
X5R
402
1
2
1
C161C
2
C1695
1UF
10%
10V
X5R
402
1UF
10%
10V
X5R
402
1
2
1
2
C1696
1UF
10%
10V
X5R
402
C161D
1UF
10%
10V
X5R
402
=PP1V8_S0_CPU_VCCPLL
7
PLACEMENT_NOTE (C1672-C1681):
Place near U1000 on bottom side
Place near U1000 on bottom side
Place near U1000 on bottom side
Place near U1000 on bottom side
Place near U1000 on bottom side
Place near U1000 on bottom side
Place near U1000 on bottom side
Place near U1000 on bottom side
Place near U1000 on bottom side
Place near U1000 on bottom side
1
C161E
10UF
2
1
C161F
20%
6.3V
X5R
603
2
10UF
20%
6.3V
CERM-X5R
0402-1
1
C162A
2
10UF
20%
6.3V
CERM-X5R
0402-1
1
C162B
2
10UF
20%
6.3V
CERM-X5R
0402-1
1
C162C
10UF
20%
6.3V
2
CERM-X5R
0402-1
1
C162D
2
10UF
20%
6.3V
CERM-X5R
0402-1
1
C162E
10UF
20%
6.3V
2
CERM-X5R
0402-1
1
C167A
10UF
20%
6.3V
2
CERM-X5R
0402-1
1
C167B
10UF
20%
6.3V
2
CERM-X5R
0402-1
1
C167C
10UF
20%
6.3V
2
CERM-X5R
0402-1
CPU VCCPLL DECOUPLING
Intel recommendation (section 6.4): 2x 1uF, 1x 330uF
PLACE_NEAR=U1000.AK63:2.54 mm:NO_VIA
PLACEMENT_NOTE (C1646-C1671):
Place near U1000 on top side
R1600
0
21
5%
1/16W
MF-LF
402
1
C160X
1UF
10%
10V
2
X5R
402
PLACE_NEAR=U1000.AK65:2.54 mm:NO_VIA
1
2
C160Y
1UF
10%
10V
X5R
402
CPU VCCPLL Low pass filter
=PP1V8_S0_CPU_VCCPLL_R
PLACE_NEAR=U1000.BC1:5mm
1
C160Z
330UF-0.006OHM
20%
2V
2
POLY
CASE-D2-SM
7
12
B
1
C167D
330UF
20%
2.5V
2
TANT
A
CASE-B2-SM1
1
C167E
330UF
20%
2.5V
2
TANT
CASE-B2-SM1
Intel recommendation: 1x 10mOhn resistor, 1x 1uF 0402
R1601
0.010
21
=PP1V05_S0_CPU_VCCPQE
1%
1/4W
MF
0603
1
2
C167F
1UF
10%
10V
X5R
402
1
C167G
330UF
20%
2.5V
2
TANT
CASE-B2-SM1
1
C167H
330UF
20%
2.5V
2
TANT
CASE-B2-SM1
7 8
1
C167J
330UF
20%
2.5V
2
TANT
CASE-B2-SM1
12
Note:The smallest 10mOhm available in the library are 0805s
6 3
SYNC_MASTER=JACK_J30
PAGE TITLE
CPU DECOUPLING-I
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
SYNC_DATE=09/27/2011
DRAWING NUMBER
051-9058
REVISION
6.0.0
BRANCH
PAGE
16 OF 109
SHEET
14 OF 86
124578
SIZE
A
D
8 7 6 5 4 3
VAXG DECOUPLING
Intel recommendation (section 6.3): 21x 1uF, 6x 10uF, 6x 22uF, 2x 470uF
12
=PPVCORE_S0_CPU_VCCAXG
7 9
12
D
PLACEMENT_NOTE (C1700-C1710):
Place on bottom side of U1000
Place on bottom side of U100.
Place on bottom side of U1000
Place on bottom side of U1000
CRITICAL
1
C1700
1UF
10%
10V
2
X5R
402
CRITICAL
1
C1701
1UF
10%
10V
2
X5R
402
CRITICAL
1
C1702
1UF
10%
10V
2
X5R
402
CRITICAL
1
C1703
1UF
10%
10V
2
X5R
402
CRITICAL
1
C1704
1UF
10%
10V
2
X5R
402
CRITICAL
1
C1705
1UF
10%
10V
2
X5R
402
CRITICAL
1
C1706
1UF
10%
10V
2
X5R
402
CRITICAL
1
C1707
1UF
10%
10V
2
X5R
402
CRITICAL
1
C1708
1UF
10%
10V
2
X5R
402
CRITICAL
1
C1709
1UF
10%
10V
2
X5R
402
CRITICAL
1
C1710
1UF
10%
10V
2
X5R
402
D
PLACEMENT_NOTE (C1711-C1716):
CRITICAL
1
C1711
10UF
20%
6.3V
2
CERM-X5R
0402-1
CRITICAL
1
C1712
10UF
20%
6.3V
2
CERM-X5R
0402-1
CRITICAL
1
C1713
10UF
20%
6.3V
2
CERM-X5R
0402-1
CRITICAL
1
C1714
10UF
20%
6.3V
2
CERM-X5R
0402-1
CRITICAL
1
C1715
10UF
20%
6.3V
2
CERM-X5R
0402-1
CRITICAL
1
C1716
10UF
20%
6.3V
2
CERM-X5R
0402-1
PLACEMENT_NOTE (C1717-C1722):
CRITICAL
OMIT
1
C1717
22UF
20%
6.3V
2
X5R-CERM-1
603
CRITICAL
OMIT
1
C1718
22UF
20%
6.3V
2
X5R-CERM-1
603
CRITICAL
OMIT
1
C1719
22UF
20%
6.3V
2
X5R-CERM-1
603
CRITICAL
OMIT
1
C1720
22UF
20%
6.3V
2
X5R-CERM-1
603
CRITICAL
OMIT
1
C1721
22UF
20%
6.3V
2
X5R-CERM-1
603
CRITICAL
OMIT
1
C1722
22UF
20%
6.3V
2
X5R-CERM-1
603
PART NUMBER
138S0691 CRITICAL
QTY
6
DESCRIPTION
CAP,CER,X5R,22uF,20%,6.3V,0603,SAMSUNG
REFERENCE DES
C1717,C1718,C1719,C1720,C1721,C1722
CRITICAL
BOM OPTION
PLACEMENT_NOTE (C1723-C1724):
Place near inductors on bottom side.
Place near inductors on bottom side.
1
C1723
470UF-4MOHM
C
3 2
20%
2.0V
POLY-TANT
D2T-SM1
1
3 2
C1724
470UF-4MOHM
20%
2.0V
POLY-TANT
D2T-SM1
C
CPU VDDQ/VCCDQ DECOUPLING
Intel recommendation (Section 6.5): 10x 1uF, 8x 10uF, 1x 330uF
=PP1V5_S3_CPU_VCCDDR
7
10 12 26
B
A
PLACEMENT_NOTE (C1738-C1747):
Place on bottom side of U1000
Place on bottom side of U1000
Place on bottom side of U1000
Place on bottom side of U100.
1
C1738
1UF
10%
10V
2
X5R
402
Place close to U1000 on bottom side
Place close to U1000 on bottom side
Place close to U1000 on bottom side
Place close to U1000 on bottom side
Place close to U1000 on bottom side
Place close to U1000 on bottom side
Place close to U1000 on bottom side
Place close to U1000 on bottom side
1
C1748
10UF
20%
6.3V
2
CERM-X5R
0402-1
1
C1756
330UF-0.006OHM
20%
2V
2
POLY
CASE-D2-SM
1
C1739
2
1
C1749
2
1UF
10%
10V
X5R
402
10UF
20%
6.3V
CERM-X5R
0402-1
1
2
1
C1750
2
C1740
1UF
10%
10V
X5R
402
10UF
20%
6.3V
X5R
603
1
2
1
C1751
2
C1741
1UF
10%
10V
X5R
402
10UF
20%
6.3V
CERM-X5R
0402-1
Intel recommendation: 1x 10mOhn resistor, 1x 1uF 0402
R1702
0.010
21
1/4W
MF
0603
1
2
C1757
1UF
10%
10V
X5R
402
=PP1V5_S3_CPU_VCCDQ
1%
7
12
6 3
1
2
1
2
C1742
1UF
10%
10V
X5R
402
C1752
10UF
20%
6.3V
CERM-X5R
0402-1
1
C1743
1UF
10%
10V
2
X5R
402
1
C1753
10UF
20%
6.3V
2
CERM-X5R
0402-1
1
2
1
2
C1744
1UF
10%
10V
X5R
402
C1754
10UF
20%
6.3V
X5R
603
1
2
1
C1755
10UF
20%
6.3V
2
CERM-X5R
0402-1
C1745
1UF
10%
10V
X5R
402
1
C1746
1UF
10%
10V
2
X5R
402
1
C1747
2
1UF
10%
10V
X5R
402
=PPVCCSA_S0_CPU
7
12
CPU VCCSA DECOUPLING
Intel recommendation (Section 6.6): 6x 1uf, 5x 10uf, 1x 330uf
PLACEMENT_NOTE (C1758-C1762):
Place on bottom side of U1000
Place on bottom side of U100.
Place on bottom side of U1000
Place on bottom side of U1000
1
C1758
1UF
10%
10V
2
X5R
402
1
C1763
10UF
20%
6.3V
2
CERM-X5R
0402-1
1
C1768
330UF-0.006OHM
20%
2V
2
POLY
CASE-D2-SM
1
2
1
2
C1759
1UF
10%
10V
X5R
402
C1764
10UF
20%
6.3V
CERM-X5R
0402-1
1
2
1
2
C1760
1UF
10%
10V
X5R
402
C1765
10UF
20%
6.3V
CERM-X5R
0402-1
1
C1761
1UF
10%
10V
2
X5R
402
1
C1766
10UF
20%
6.3V
2
CERM-X5R
0402-1
SYNC_MASTER=MASTER
PAGE TITLE
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
1
C1762
1UF
10%
10V
2
X5R
402
1
C1767
10UF
20%
6.3V
2
CERM-X5R
0402-1
CPU DECOUPLING-II
Apple Inc.
R
SYNC_DATE=02/15/2011
DRAWING NUMBER
051-9058
REVISION
6.0.0
BRANCH
PAGE
17 OF 109
SHEET
15 OF 86
124578
SIZE
B
A
D
8 7 6 5 4 3
12
SYSCLK_CLK32K_RTC
24 81
IN
RTC_RESET_L
16
PCH_SRTCRST_L
16
PCH_INTRUDER_L
16
PCH_INTVRMEN_L
D
VSel strap not functional (VCCVRM = 1.8V)
C
16
HDA_BIT_CLK_R
16 81
HDA_SYNC_R
16 81
PCH_SPKR
16
HDA_RST_R_L
16 81
HDA_SDIN0
57 81
IN
TP_HDA_SDIN1
6
TP_HDA_SDIN2
6
TP_HDA_SDIN3
6
HDA_SDOUT_R
16 24 81
JTAG_TBT_TMS
16 33
OUT
ENET_MEDIA_SENSE_RDIV
16 24
IN
XDP_PCH_TCK
23
IN
XDP_PCH_TMS
23
IN
XDP_PCH_TDI
23
IN
XDP_PCH_TDO
23
OUT
SPI_CLK_R
47 81
OUT
SPI_CS0_R_L
47 81
OUT
TP_SPI_CS1_L
SPI_MOSI_R
47 81
OUT
SPI_MISO
47 81
IN
=PPVRTC_G3_PCH
1
330K
1/20W
1
R1801
1M
5%
5%
1/20W
MF
MF
201
201
2
2
R1800
B
=PP3V3_SUS_PCH_GPIO
=PP3V3_S0_PCH_GPIO
=PP3V3_T29_PCH_GPIO
R1876
R1877
R1878
R1834
R1833
R1842
R1869
R1844
R1845
R1847
A
R1814
R1815
R1843
R1846
R1848
R1853
R1854
R1855
R1879
A20
OMIT_TABLE
RTCX1
C20
RTCX2
NC
D20
RTCRST*
G22
SRTCRST*
K22
INTRUDER*
C17
INTVRMEN
N34
HDA_BCLK
L34
HDA_SYNC
T10
SPKR
(IPD-PLTRST#)
K34
HDA_RST*
E34
HDA_SDIN0
G34
HDA_SDIN1
C34
HDA_SDIN2
A34
HDA_SDIN3
A36
HDA_SDO
C36
HDA_DOCK_EN*/GPIO33
N32
HDA_DOCK_RST*/GPIO13
J3
JTAG_TCK
H7
JTAG_TMS
K5
JTAG_TDI
H1
JTAG_TDO
T3
SPI_CLK
Y14
SPI_CS0*
T1
SPI_CS1*
V4
SPI_MOSI
U3
SPI_MISO
7
17 20
1
R1802
1/20W
C1802
1UF
10K
4.7K
10K
10K
10K
10K
10K
10K
10K
10K
10K
10K
10K
10K
10K
10K
10K
10K
10K
Connect to ENET_MEDIA_SENSE via alias if HDA = 3.3V.
Connect to ENET_MEDIA_SENSE via 12K R if HDA = 1.5V.
If HDA = S0, must also ensure that signal cannot be high in S3.
1
5%
MF
2
1
2
21
21
21
21
21
21
21
21
21
21
12
21
21
21
21
21
21
21
21
R1803
20K
5%
1/20W
MF
201
2
RTC_RESET_L
PCH_SRTCRST_L
PCH_INTRUDER_L
PCH_INTVRMEN_L
1
C1803
1UF
10%
10V
2
X5R
402
7
17 18 19
7
17 18 19 30
7
19
5%
1/20W
5%
1/20W
1/20W
5%
5%
1/20W
5%
1/20W
5%
1/20W
5%
1/20W
5%
1/20W
5%
1/20W
5%
1/20W
5%
1/20W
5%
1/20W
5%
1/20W
5%
1/20W
5%
1/20W
5%
1/20W
5%
1/20W
5%
1/20W
5%
1/20W
MF
201
MF
201
201
MF
MF
201
MF
201
MF
201
MF
201
MF
201
MF
201
MF
201
MF
201
MF
201
MF
201
MF
201
MF
201
MF
201
MF
201
MF
201
MF
201
16
16
16
16
JTAG_TBT_TMS
PCH_SPKR
PCH_SATALED_L
DP_AUXCH_ISOL
SATARDRVR_EN
FW_CLKREQ_L
AP_CLKREQ_L
EXCARD_CLKREQ_L
JTAG_DPMUXUC_TRST_L
ENET_CLKREQ_L
PEG_CLKREQ_L
TBT_CLKREQ_L
PCIECLKRQ0_L_GPIO73
PEGCLKRQA_L_GPIO47
PEGCLKRQB_L_GPIO56
PCH_GPIO11
USB_EXTB_SEL_XHCI
USB_EXTD_SEL_XHCI
ENET_MEDIA_SENSE_RDIV
20K
201
10%
10V
X5R
402
PANTHERPOINT
(IPD-BOOT)
(IPD)
(IPD)
(IPD)
(IPD)
(IPD-BOOT)
(IPD)
(IPU)
(IPU)
(IPD-BOOT)
(IPU)
U1800
MOBILE
FCBGA
(1 OF 10)
RTC
IHDA
JTAG
SPI
FWH4/LFRAME*
(IPU)
LDRQ1*/GPIO23
(IPU)
LPC
SATA
SATAICOMPO
SATAICOMPI
SATA3RCOMPO
SATA3COMPI
SATA3RBIAS
SATA0GP/GPIO21
SATA1GP/GPIO19
(IPU)
LPC_AD_R<0>
16
LPC_AD_R<1>
16
LPC_AD_R<2>
16
LPC_AD_R<3>
16
LPC_FRAME_R_L
16
HDA_BIT_CLK_R
16 81
HDA_SYNC_R
16 81
HDA_RST_R_L
16 81
HDA_SDOUT_R
16 24 81
16 33
16
16
23 75
23 41
16 39
16 32
16
16
16 36
16
16 35
16
16
16
16
16 25
16
16 24
LDRQ0*
SERIRQ
SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP
SATA1RXN
SATA1RXP
SATA1TXN
SATA1TXP
SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP
SATA3RXN
SATA3RXP
SATA3TXN
SATA3TXP
SATA4RXN
SATA4RXP
SATA4TXN
SATA4TXP
SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP
SATALED*
C38
A38
B37
C37
D36
E36
K36
V5
AM3
AM1
AP7
AP5
AM10
AM8
AP11
AP10
AD7
AD5
AH5
AH4
AB8
AB10
AF3
AF1
Y7
Y5
AD3
AD1
Y3
Y1
AB3
AB1
Y11
Y10
AB12
AB13
AH1
P3
V14
P1
FWH0/LAD0
FWH1/LAD1
FWH2/LAD2
FWH3/LAD3
(IPU)
PLACE_NEAR=U1800.N34:1.27mm
PLACE_NEAR=U1800.L34:1.27mm
PLACE_NEAR=U1800.K34:1.27mm
PLACE_NEAR=U1800.A36:1.27mm
LPC_AD_R<0>
LPC_AD_R<1>
LPC_AD_R<2>
LPC_AD_R<3>
LPC_FRAME_R_L
TP_LPC_DREQ0_L
TBT_PWR_EN_PCH
LPC_SERIRQ
SATA_HDD_D2R_N
SATA_HDD_D2R_P
SATA_HDD_R2D_C_N
SATA_HDD_R2D_C_P
SATA_ODD_D2R_N
SATA_ODD_D2R_P
SATA_ODD_R2D_C_N
SATA_ODD_R2D_C_P
TP_SATA_C_D2RN
TP_SATA_C_D2RP
TP_SATA_C_R2D_CN
TP_SATA_C_R2D_CP
TP_SATA_D_D2RN
TP_SATA_D_D2RP
TP_SATA_D_R2D_CN
TP_SATA_D_R2D_CP
TP_SATA_E_D2RN
TP_SATA_E_D2RP
TP_SATA_E_R2D_CN
TP_SATA_E_R2D_CP
TP_SATA_F_D2RN
TP_SATA_F_D2RP
TP_SATA_F_R2D_CN
TP_SATA_F_R2D_CP
PCH_SATAICOMP
80
PCH_SATA3COMP
PCH_SATA3RBIAS
PCH_SATALED_L
XDP_DC2_PCH_GPIO21_DP_AUXCH_ISOL
XDP_DC3_PCH_GPIO19_SATARDRVR_EN
R1860
R1861
R1862
R1863
R1864
R1810
R1811
R1812
R1813
33
33
33
33
33
33
33
33
33
21
21
21
21
21
21
21
21
21
16
16
16
16
16
24
OUT
41 80
IN
41 80
IN
41 80
OUT
41 80
OUT
41 80
IN
41 80
IN
41 80
OUT
41 80
OUT
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
16
5%
1/20W
5%
1/20W
5%
1/20W
5%
1/20W
5%
1/20W
5%
1/20W
5%
1/20W
1/20W
5%
5%
1/20W
ITPCPU_CLK100M_N
10 78
ITPCPU_CLK100M_P
10 78
=PP3V3_S0_PCH
1
R1820
10K
5%
1/20W
MF
201
2
6
45 47
BI
=PP1V05_S0_PCH_VCCIO_SATA
PLACE_NEAR=U1800.Y11:2.54mm
1
R1830
37.4
1%
1/20W
MF
201
2
=PP1V05_S0_PCH
1
R1831
49.9
1%
1/20W
MF
201
2
PLACE_NEAR=U1800.AB12:2.54mm
PLACE_NEAR=U1800.AH1:2.54mm
1
R1832
750
1%
23
OUT
OUT
MF
201
MF
201
MF
201
MF
201
MF
201
MF
201
MF
201
MF
201
MF
201
23
2
LPC_AD<0>
LPC_AD<1>
LPC_AD<2>
LPC_AD<3>
LPC_FRAME_L
HDA_BIT_CLK
HDA_SYNC
HDA_RST_L
HDA_SDOUT
1/20W
MF
201
NO STUFF
R1841
0
5%
1/20W
MF
201
7
22
7
20 22
7
22
6
45 47 81
BI
6
45 47 81
BI
6
45 47 81
BI
6
45 47 81
BI
6
45 47 81
OUT
57 81
OUT
57 81
OUT
57 81
OUT
57 81
OUT
NO STUFF
R1840
0
21
5%
1/20W
MF
201
21
36 81
IN
36 81
IN
36 81
OUT
36 81
OUT
32 81
IN
32 81
IN
32 81
OUT
32 81
OUT
38 81
IN
38 81
IN
38 81
OUT
38 81
OUT
8
IN
8
IN
8
OUT
8
OUT
36 81
OUT
36 81
OUT
16
38 81
OUT
38 81
OUT
16 39
IN
32 81
OUT
32 81
OUT
16 32
IN
8
81
OUT
8
81
OUT
16
IN
6
6
16
OUT
6
6
16 36
IN
6
6
16
8
81
OUT
8
81
OUT
16
IN
33 81
OUT
33 81
OUT
16 35
IN
23 78
23 78
PCIE_ENET_D2R_N
PCIE_ENET_D2R_P
PCIE_ENET_R2D_C_N
PCIE_ENET_R2D_C_P
PCIE_AP_D2R_N
PCIE_AP_D2R_P
PCIE_AP_R2D_C_N
PCIE_AP_R2D_C_P
PCIE_FW_D2R_N
PCIE_FW_D2R_P
PCIE_FW_R2D_C_N
PCIE_FW_R2D_C_P
PCIE_EXCARD_D2R_N
PCIE_EXCARD_D2R_P
PCIE_EXCARD_R2D_C_N
PCIE_EXCARD_R2D_C_P
NC_PCIE_5_D2RN
NC_PCIE_5_D2RP
NC_PCIE_5_R2D_CN
NC_PCIE_5_R2D_CP
NC_PCIE_6_D2RN
NC_PCIE_6_D2RP
NC_PCIE_6_R2D_CN
NC_PCIE_6_R2D_CP
NC_PCIE_7_D2RN
NC_PCIE_7_D2RP
NC_PCIE_7_R2D_CN
NC_PCIE_7_R2D_CP
NC_PCIE_8_D2RN
NC_PCIE_8_D2RP
NC_PCIE_8_R2D_CN
NC_PCIE_8_R2D_CP
PCIE_CLK100M_ENET_N
PCIE_CLK100M_ENET_P
PCIECLKRQ0_L_GPIO73
PCIE_CLK100M_FW_N
PCIE_CLK100M_FW_P
FW_CLKREQ_L
PCIE_CLK100M_AP_N
PCIE_CLK100M_AP_P
AP_CLKREQ_L
PCIE_CLK100M_EXCARD_N
PCIE_CLK100M_EXCARD_P
EXCARD_CLKREQ_L
TP_PCIE_CLK100M_PE4N
TP_PCIE_CLK100M_PE4P
JTAG_DPMUXUC_TRST_L
TP_PCIE_CLK100M_PE5N
TP_PCIE_CLK100M_PE5P
ENET_CLKREQ_L
TP_PCIE_CLK100M_PEBN
TP_PCIE_CLK100M_PEBP
PEGCLKRQB_L_GPIO56
PEG_CLK100M_N
PEG_CLK100M_P
PEG_CLKREQ_L
PCIE_CLK100M_T29_N
PCIE_CLK100M_T29_P
TBT_CLKREQ_L
ITPXDP_CLK100M_N
ITPXDP_CLK100M_P
24 81
IN
Unused clock terminations for FCIM Mode
PCH_CLK96M_DOT_P
16 80
PCH_CLK96M_DOT_N
16 80
PCH_CLK100M_SATA_P
16 80
PCH_CLK100M_SATA_N
16 80
PCIE_CLK100M_PCH_P
16 80
PCIE_CLK100M_PCH_N
16 80
PCH_CLK14P3M_REFCLK
16 80
PCH_CLKIN_GNDP1
16
PCH_CLKIN_GNDN1
16
R1891
R1892
R1893
R1894
R1895
R1896
R1897
R1870
R1871
10K
10K
10K
10K
10K
10K
10K
10K
10K
6 3
BG34
PERN1
BJ34
PERP1
AV32
PETN1
AU32
PETP1
BE34
PERN2
BF34
PERP2
BB32
PETN2
AY32
PETP2
BG36
PERN3
BJ36
PERP3
AV34
PETN3
AU34
PETP3
BF36
PERN4
BE36
PERP4
AY34
PETN4
BB34
PETP4
BG37
PERN5
BH37
PERP5
AY36
PETN5
BB36
PETP5
BJ38
PERN6
BG38
PERP6
AU36
PETN6
AV36
PETP6
BG40
PERN7
BJ40
PERP7
AY40
PETN7
BB40
PETP7
BE38
PERN8
BC38
PERP8
AW38
PETN8
AY38
PETP8
Y40
CLKOUT_PCIE0N
Y39
CLKOUT_PCIE0P
J2
PCIECLKRQ0*/GPIO73
AB49
CLKOUT_PCIE1N
AB47
CLKOUT_PCIE1P
M1
PCIECLKRQ1*/GPIO18
AA48
CLKOUT_PCIE2N
AA47
CLKOUT_PCIE2P
V10
PCIECLKRQ2*/GPIO20
Y37
CLKOUT_PCIE3N
Y36
CLKOUT_PCIE3P
A8
PCIECLKRQ3*/GPIO25
Y43
CLKOUT_PCIE4N
Y45
CLKOUT_PCIE4P
L12
PCIECLKRQ4*/GPIO26
V45
CLKOUT_PCIE5N
V46
CLKOUT_PCIE5P
L14
PCIECLKRQ5*/GPIO44
(IPU-RSMRST#)
AB42
CLKOUT_PEG_B_N
AB40
CLKOUT_PEG_B_P
E6
PEG_B_CLKRQ*/GPIO56
V40
CLKOUT_PCIE6N
V42
CLKOUT_PCIE6P
T13
PCIECLKRQ6*/GPIO45
V38
CLKOUT_PCIE7N
V37
CLKOUT_PCIE7P
K12
PCIECLKRQ7*/GPIO46
(IPU-RSMRST#)
AK14
CLKOUT_ITPXDP_N
AK13
CLKOUT_ITPXDP_P
SYSCLK_CLK25M_SB
21
5%
1/20W
21
5%
1/20W
21
5%
1/20W
21
5%
1/20W
21
5%
1/20W
21
5%
1/20W
21
5%
1/20W
21
5%
1/20W
21
5%
1/20W
OMIT_TABLE
U1800
PANTHERPOINT
MOBILE
FCBGA
(2 OF 10)
SMBUS
SML1ALERT*/PCHHOT*/GPIO74
PCI-E*
C-LINK
Controlled by PCIECLKRQ5#
CLOCKS
FLEX
CLOCKS
R1872
604
21
1%
1/16W
MF-LF
402
MF
201
MF
201
201
MF
MF
201
MF
201
MF
201
MF
201
MF
201
MF
201
SMBALERT*/GPIO11
SMBCLK
SMBDATA
SML0ALERT*/GPIO60
SML0CLK
SML0DATA
SML1CLK/GPIO58
SML1DATA/GPIO75
(IPU/IPD)
(IPU/IPD)
CL_CLK1
CL_DATA1
CL_RST1*
PEG_A_CLKRQ*/GPIO47
CLKOUT_PEG_A_N
CLKOUT_PEG_A_P
CLKOUT_DMI_N
CLKOUT_DMI_P
CLKOUT_DP_N
CLKOUT_DP_P
CLKIN_DMI_N
CLKIN_DMI_P
CLKIN_GND1_N
CLKIN_GND1_P
CLKIN_DOT_96N
CLKIN_DOT_96P
CLKIN_SATA_N
CLKIN_SATA_P
REFCLK14IN
CLKIN_PCILOOPBACK
XTAL25_IN
XTAL25_OUT
XCLK_RCOMP
CLKOUTFLEX0/GPIO64
(IPD-PWROK)
CLKOUTFLEX1/GPIO65
(IPD-PWROK)
CLKOUTFLEX2/GPIO66
(IPD-PWROK)
CLKOUTFLEX3/GPIO67
(IPD-PWROK)
SYSCLK_CLK25M_SB_R
1.8V -> 1.1V
1
R1873
1K
1%
1/20W
MF
201
2
SYNC_MASTER=J31_MLB
PAGE TITLE
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
E12
H14
C9
A12
C8
G12
C13
E14
M16
M7
T11
P10
M10
AB37
AB38
AV22
AU22
AM12
AM13
BF18
BE18
BJ30
BG30
G24
E24
AK7
AK5
K45
H45
V47
V49
Y47
K43
F47
H47
K49
PCH_GPIO11
SMBUS_PCH_CLK
SMBUS_PCH_DATA
USB_EXTB_SEL_XHCI
SML_PCH_0_CLK
SML_PCH_0_DATA
USB_EXTD_SEL_XHCI
SML_PCH_1_CLK
SML_PCH_1_DATA
TP_CLINK_CLK
TP_CLINK_DATA
TP_CLINK_RESET_L
PEGCLKRQA_L_GPIO47
TP_PCIE_CLK100M_PEGAN
TP_PCIE_CLK100M_PEGAP
DMI_CLK100M_CPU_N
DMI_CLK100M_CPU_P
TP_PCH_CLKOUT_DPN
TP_PCH_CLKOUT_DPP
PCIE_CLK100M_PCH_N
PCIE_CLK100M_PCH_P
PCH_CLKIN_GNDN1
PCH_CLKIN_GNDP1
PCH_CLK96M_DOT_N
PCH_CLK96M_DOT_P
PCH_CLK100M_SATA_N
PCH_CLK100M_SATA_P
PCH_CLK14P3M_REFCLK
PCH_CLK33M_PCIIN
DOES THIS NEED LENGTH MATCH???
SYSCLK_CLK25M_SB_R
NC
=PP1V05_S0_PCH_VCCDIFFCLK
7
20 22
PLACE_NEAR=U1800.Y47:2.54mm
PCH_XCLK_RCOMP
TP_PCH_GPIO64_CLKOUTFLEX0
TP_PCH_GPIO65_CLKOUTFLEX1
TP_PCH_GPIO66_CLKOUTFLEX2
TP_PCH_GPIO67_CLKOUTFLEX3
16 81
SYNC_DATE=06/13/2011
PCH SATA/PCIe/CLK/LPC/SPI
Apple Inc.
R
DRAWING NUMBER
051-9058
REVISION
BRANCH
PAGE
18 OF 109
SHEET
124578
16
48 81
OUT
48 81
BI
16 25
OUT
48 81
OUT
48 81
BI
16
OUT
48 81
OUT
48 81
BI
6
6
6
16
10 78
OUT
10 78
OUT
8
OUT
8
OUT
16 80
IN
16 80
IN
16
16
16 80
IN
16 80
IN
16 80
IN
16 80
IN
16 80
IN
24 80
IN
16 81
1
R1890
90.9
1%
1/20W
MF
201
2
6
6
6
6
6.0.0
16 OF 86
SIZE
D
C
B
A
D
8 7 6 5 4 3
12
=PP3V3_SUS_PCH_GPIO
=PP1V05_S0_PCH_VCCIO_PCIE
PLACE_NEAR=U1800.BJ24:12.7mm
1
1
10K
R1900
49.9
1%
5%
1/20W
MF
MF
201
201
2
2
DMI_N2S_N<0>
9
78
IN
DMI_N2S_N<1>
9
78
IN
DMI_N2S_N<2>
9
78
IN
DMI_N2S_N<3>
9
78
IN
DMI_N2S_P<0>
9
78
IN
DMI_N2S_P<1>
9
78
IN
DMI_N2S_P<2>
9
78
IN
DMI_N2S_P<3>
9
78
IN
DMI_S2N_N<0>
9
78
OUT
DMI_S2N_N<1>
9
78
OUT
DMI_S2N_N<2>
9
78
OUT
DMI_S2N_N<3>
9
78
OUT
DMI_S2N_P<0>
9
78
OUT
DMI_S2N_P<1>
9
78
OUT
DMI_S2N_P<2>
9
78
OUT
DMI_S2N_P<3>
9
78
OUT
R1905
1/20W
D
PCH_DMI_COMP
24 45
IN
23 24 45
IN
24
IN
24
IN
10 26 78
OUT
73
IN
17 23 45
IN
45 46 73
IN
46
IN
PCH_DMI2RBIAS
PCH_SUSACK_L
17
PM_SYSRST_L
PM_PCH_SYS_PWROK
PM_PCH_PWROK
PM_PCH_APWROK
PM_MEM_PWRGD
PM_RSMRST_L
PCH_SUSWARN_L
17
PM_PWRBTN_L
SMC_ADAPTER_EN
PM_BATLOW_L
PLACE_NEAR=U1800.BH21:2.54mm
1
R1920
750
1%
1/20W
MF
201
2
C
PCH_RI_L
=PP3V3_SUS_PCH_GPIO
7
16 17 18 19
PCH_SUSWARN_L
17
B
7
16 17 18 19
7
R1983
1/20W
10K
OMIT_TABLE
BC24
BE20
BG18
BG20
BE24
BC20
BJ18
BJ20
AW24
AW20
BB18
AV18
AY24
AY20
AY18
AU18
BJ24
BG25
BH21
C12
DMI0RXN
DMI1RXN
DMI2RXN
DMI3RXN
DMI0RXP
DMI1RXP
DMI2RXP
DMI3RXP
DMI0TXN
DMI1TXN
DMI2TXN
DMI3TXN
DMI0TXP
DMI1TXP
DMI2TXP
DMI3TXP
DMI_ZCOMP
DMI_IRCOMP
DMI2RBIAS
SUSACK*
PANTHERPOINT
(IPU)
U1800
MOBILE
FCBGA
(3 OF 10)
DMI
FDI
FDI_FSYNC0
FDI_FSYNC1
FDI_LSYNC0
FDI_LSYNC1
SYS_RESET*
P12
SYS_PWROK
L22
PWROK
L10
APWROK
B13
DRAMPWROK
C21
RSMRST*
K16
SUSWARN*/SUSPWRDNACK/GPIO30
E20
PWRBTN*
(IPU)
H20
ACPRESENT/GPIO31
(IPD-DeepS4/S5)
E10
BATLOW*/GPIO72
A10
RI*
1
5%
MF
201
R1986
2
0
2 1
1/20W
201
5%
MF
PCH_SUSACK_L
CLKRUN*/GPIO32
SUS_STAT*/GPIO61
SUSCLK/GPIO62
SLP_S5*/GPIO63
MANAGEMENT
SYSTEM POWER
(IPU)
SLP_LAN*/GPIO29
17
FDI_RXN0
FDI_RXN1
FDI_RXN2
FDI_RXN3
FDI_RXN4
FDI_RXN5
FDI_RXN6
FDI_RXN7
FDI_RXP0
FDI_RXP1
FDI_RXP2
FDI_RXP3
FDI_RXP4
FDI_RXP5
FDI_RXP6
FDI_RXP7
FDI_INT
DSWVRMEN
DPWROK
WAKE*
SLP_S4*
SLP_S3*
SLP_A*
SLP_SUS*
PMSYNCH
BJ14
AY14
BE14
BH13
BC12
BJ12
BG10
BG9
BG14
BB14
BF14
BG13
BE12
BG12
BJ10
BH9
AW16
AV12
BC10
AV14
BB10
A18
E22
B9K3
N3
G8
N14
D10
H4
F4
G10
G16
AP14
K14
FDI_DATA_N<0>
FDI_DATA_N<1>
FDI_DATA_N<2>
FDI_DATA_N<3>
FDI_DATA_N<4>
FDI_DATA_N<5>
FDI_DATA_N<6>
FDI_DATA_N<7>
FDI_DATA_P<0>
FDI_DATA_P<1>
FDI_DATA_P<2>
FDI_DATA_P<3>
FDI_DATA_P<4>
FDI_DATA_P<5>
FDI_DATA_P<6>
FDI_DATA_P<7>
FDI_INT
FDI_FSYNC<0>
FDI_FSYNC<1>
FDI_LSYNC<0>
FDI_LSYNC<1>
PCH_DSWVRMEN
PM_DSW_PWRGD
PCIE_WAKE_L
PM_CLKRUN_L
LPC_PWRDWN_L
PM_CLK32K_SUSCLK_R
PM_SLP_S5_L
PM_SLP_S4_L
PM_SLP_S3_L
TP_PM_SLP_A_L
PM_SLP_SUS_L
PM_SYNC
GPIO29
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
IN
BI
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
9
78
9
78
9
78
9
78
9
78
9
78
9
78
9
78
9
78
9
78
9
78
9
78
9
78
9
78
9
78
9
78
9
78
9
78
9
78
9
78
9
78
6
17 24 32
6
17 45 47
6
45 47
46
17 45 73
6
17 26 32 45 73
6 8
17 26 45 73
17 73
10 78
17
PLACE_NEAR=U1800.AF37:2.54mm
=PPVRTC_G3_PCH
1
R1915
390K
5%
1/20W
MF
201
2
45
IN
1
R1909
100K
5%
1/20W
MF
201
2
7
R1950
16 20
2.37K
1/20W
AF37
AF36
AE48
AE47
AK39
AK40
AN48
AM47
AK47
AJ48
AN47
AM49
AK49
AJ47
AF40
AF39
AH45
AH47
AF49
AF45
AH43
AH49
AF47
AF43
J47
M45
P45
T40
K47
T45
P39
N48
P49
T49
T39
M40
M47
M49
T43
T42
L_BKLTEN
L_VDD_EN
L_BKLTCTL
L_DDC_CLK
L_DDC_DATA
(IPD-PLTRST#)
L_CTRL_CLK
L_CTRL_DATA
LVD_IBG
LVD_VBG
LVD_VREFH
LVD_VREFL
LVDSA_CLK*
LVDSA_CLK
LVDSA_DATA0*
LVDSA_DATA1*
LVDSA_DATA2*
LVDSA_DATA3*
LVDSA_DATA0
LVDSA_DATA1
LVDSA_DATA2
LVDSA_DATA3
LVDSB_CLK*
LVDSB_CLK
LVDSB_DATA0*
LVDSB_DATA1*
LVDSB_DATA2*
LVDSB_DATA3*
LVDSB_DATA0
LVDSB_DATA1
LVDSB_DATA2
LVDSB_DATA3
CRT_BLUE
CRT_GREEN
CRT_RED
CRT_DDC_CLK
CRT_DDC_DATA
CRT_HSYNC
CRT_VSYNC
DAC_IREF
CRT_IRTN
LVDS_IG_BKL_ON
8
17
OUT
LVDS_IG_PANEL_PWR
8
17
OUT
LVDS_IG_BKL_PWM
8
OUT
LVDS_IG_DDC_CLK
8
OUT
LVDS_IG_DDC_DATA
8
OUT
TP_LVDS_IG_CTRL_CLK
6
TP_LVDS_IG_CTRL_DATA
6
PCH_LVDS_IBG
TP_PCH_LVDS_VBG
1
1%
MF
201
2
6
LVDS_IG_A_CLK_N
74 80
OUT
LVDS_IG_A_CLK_P
74 80
OUT
LVDS_IG_A_DATA_N<0>
6
74 80
OUT
LVDS_IG_A_DATA_N<1>
6
74 80
OUT
LVDS_IG_A_DATA_N<2>
6
74 80
OUT
LVDS_IG_A_DATA_N<3>
8
80
OUT
LVDS_IG_A_DATA_P<0>
6
74 80
OUT
LVDS_IG_A_DATA_P<1>
6
74 80
OUT
LVDS_IG_A_DATA_P<2>
6
74 80
OUT
LVDS_IG_A_DATA_P<3>
8
80
OUT
LVDS_IG_B_CLK_N
8
80
OUT
LVDS_IG_B_CLK_P
8
80
OUT
LVDS_IG_B_DATA_N<0>
8
80
OUT
LVDS_IG_B_DATA_N<1>
8
80
OUT
LVDS_IG_B_DATA_N<2>
8
80
OUT
LVDS_IG_B_DATA_N<3>
8
80
OUT
LVDS_IG_B_DATA_P<0>
8
80
OUT
LVDS_IG_B_DATA_P<1>
8
80
OUT
LVDS_IG_B_DATA_P<2>
8
80
OUT
LVDS_IG_B_DATA_P<3>
8
80
OUT
TP_CRT_IG_BLUE
6
TP_CRT_IG_GREEN
6
TP_CRT_IG_RED
6
TP_CRT_IG_DDC_CLK
6
TP_CRT_IG_DDC_DATA
6
TP_CRT_IG_HSYNC
6
TP_CRT_IG_VSYNC
6
PCH_DAC_IREF
PLACE_NEAR=U1800.T43:2.54mm
1
R1951
1K
5%
1/20W
MF
201
2
OMIT_TABLE
MOBILE
FCBGA
SDVO_TVCLKINN
SDVO_TVCLKINP
SDVO_STALLN
SDVO_STALLP
SDVO_INTN
SDVO_INTP
SDVO_CTRLCLK
SDVO_CTRLDATA
(IPD-PLTRST#)
DDPB_AUXN
DDPB_AUXP
DDPB_HPD
U1800
PANTHERPOINT
(4 OF 10)
LVDS
DDPC_CTRLCLK
DDPC_CTRLDATA
(IPD-PLTRST#)
DDPC_AUXN
DDPC_AUXP
DDPC_HPD
DIGITAL DISPLAY INTERFACE
DDPD_CTRLCLK
DDPD_CTRLDATA
(IPD-PLTRST#)
DDPD_AUXN
DDPD_AUXP
DDPD_HPD
CRT
(IPD)
(IPD)
(IPD)
(IPD)
(IPD)
(IPD)
DDPB_0N
DDPB_0P
DDPB_1N
DDPB_1P
DDPB_2N
DDPB_2P
DDPB_3N
DDPB_3P
DDPC_0N
DDPC_0P
DDPC_1N
DDPC_1P
DDPC_2N
DDPC_2P
DDPC_3N
DDPC_3P
DDPD_0N
DDPD_0P
DDPD_1N
DDPD_1P
DDPD_2N
DDPD_2P
DDPD_3N
DDPD_3P
AP43
AP45
AM42
AM40
AP39
AP40
P38
M39
AT49
AT47
AT40
AV42
AV40
AV45
AV46
AU48
AU47
AV47
AV49
P46
P42
AP47
AP49
AT38
AY47
AY49
AY43
AY45
BA47
BA48
BB47
BB49
M43
M36
AT45
AT43
BH41
BB43
BB45
BF44
BE44
BF42
BE42
BJ42
BG42
TP_SDVO_TVCLKINN
TP_SDVO_TVCLKINP
TP_SDVO_STALLN
TP_SDVO_STALLP
TP_SDVO_INTN
TP_SDVO_INTP
DPA_IG_DDC_CLK
DPA_IG_DDC_DATA
DPA_IG_AUX_CH_N
DPA_IG_AUX_CH_P
DPA_IG_HPD
TP_DP_IG_B_MLN<0>
TP_DP_IG_B_MLP<0>
TP_DP_IG_B_MLN<1>
TP_DP_IG_B_MLP<1>
TP_DP_IG_B_MLN<2>
TP_DP_IG_B_MLP<2>
TP_DP_IG_B_MLN<3>
TP_DP_IG_B_MLP<3>
DPB_IG_DDC_CLK
DPB_IG_DDC_DATA
DPB_IG_AUX_CH_N
DPB_IG_AUX_CH_P
DPB_IG_HPD
TP_DP_IG_C_MLN<0>
TP_DP_IG_C_MLP<0>
TP_DP_IG_C_MLN<1>
TP_DP_IG_C_MLP<1>
TP_DP_IG_C_MLN<2>
TP_DP_IG_C_MLP<2>
TP_DP_IG_C_MLN<3>
TP_DP_IG_C_MLP<3>
TP_DP_IG_D_CTRL_CLK
TP_DP_IG_D_CTRL_DATA
TP_DP_IG_D_AUXN
TP_DP_IG_D_AUXP
TP_DP_IG_D_HPD
TP_DP_IG_D_MLN<0>
TP_DP_IG_D_MLP<0>
TP_DP_IG_D_MLN<1>
TP_DP_IG_D_MLP<1>
TP_DP_IG_D_MLN<2>
TP_DP_IG_D_MLP<2>
TP_DP_IG_D_MLN<3>
TP_DP_IG_D_MLP<3>
6
6
6
6
6
6
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
D
C
B
=PP3V3_SUS_PCH_GPIO
=PP3V3_S0_PCH_GPIO
=PP3V3_S5_PCH
R1985
R1991
A
R1982
R1925
R1924
R1921
R1922
R1923
R1981
R1984
8.2K
10K
100K
100K
100K
100K
100K
100K
1K
1K
7
16 17 18 19
7
16 18 19 30
7
21
1/20W
5%
21
1/20W
5%
21
1/20W
5%
21
1/20W
5%
12
1/20W
5%
12
1/20W
5% MF
12
1/20W
5%
12
1/20W
5%
12
1/20W
5%
12
1/20W
5%
MF
MF
MF
MF
MF
MF
MF
MF
MF
PM_PWRBTN_L
201
PM_CLKRUN_L
201
GPIO29
201
PCIE_WAKE_L
201
MAKE_BASE=TRUE
PM_SLP_S3_L
201
PM_SLP_S4_L
201
PM_SLP_S5_L
201
PM_SLP_SUS_L
201
LVDS_IG_BKL_ON
201
LVDS_IG_PANEL_PWR
201
17 23 45
6
17 45 47
17
6
17 24 32
=TBT_WAKE_L
6 8
17 26 45 73
6
17 26 32 45 73
17 45 73
17 73
8
17
8
17
75
IN
6 3
SYNC_MASTER=J31_MLB
PAGE TITLE
PCH DMI/FDI/PM/Graphics
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
SYNC_DATE=06/13/2011
DRAWING NUMBER
051-9058
REVISION
6.0.0
BRANCH
PAGE
19 OF 109
SHEET
17 OF 86
124578
SIZE
A
D
8 7 6 5 4 3
12
BG26
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
D
TP_PCH_TP23
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
USB3_EXTA_RX_N
42 80
IN
USB3_EXTB_RX_N
43 80
IN
USB3_EXTC_RX_N
8
IN
USB3_EXTD_RX_N
8
C
=PP3V3_S0_PCH_GPIO
7
16 17 18 19 30
R2010
R2011
R2012
R2013
B
R2054
=PP3V3_SUS_PCH_GPIO
=PP3V3_S3_PCH_GPIO
=PP3V3_S0_PCH_GPIO
R2016
R2017
R2018
R2030
R2014
R2031
A
R2033
R2069
R2060
R2061
R2062
R2068
R2067
10K
10K
10K
10K
10K
10K
10K
10K
10K
10K
10K
10K
10K
NO STUFF
NO STUFF
7
16 17 19
7
24
7
16 17 18 19 30
21
1/20W
5%
21
1/20W
5% MF
21
1/20W
5%
21
1/20W
5%
21
1/20W
5%
21
1/20W
5%
Redundant to pull-up on audio page
21
1/20W
5%
21
5%
21
5%
21
21
5%
21
5%
12
5%
XDP_DB3_PCH_GPIO14_SDCONN_STATE_CHANGE
1/20W
1/20W
1/20W
1/20W
1/20W
1/20W
JTAG_GMUX_TMS
201
MF
BLC_I2C_MUX_SEL
201
USE_HDD_OOB_L
201
MF
BLC_GPIO
201
MF
AUD_IP_PERIPHERAL_DET
201
MF
TBT_PWR_REQ_L
201
MF
AUD_I2C_INT_L
201
MF
MF
201
XDP_DA0_PCH_GPIO59_USB_EXTA_OC_L
MF
201
XDP_DA1_PCH_GPIO40_USB_EXTB_OC_L
MF5%
201
XDP_DA2_PCH_GPIO41_USB_EXTC_OC_L
201
MF
XDP_DA3_PCH_GPIO42_USB_EXTD_OC_L
MF
201
AP_PWR_EN
201
MF
10K
10K
10K
10K
10K
NO STUFF
21
21
21
21
12
18
18
18
18
18 62
18 75
18 62
23 32 73
1/20W
5%
1/20W
5%
1/20W
5%
1/20W
5%
1/20W
5%
18 23
18 23
18 23
18 23
18 23
IN
42 80
IN
43 80
IN
8
IN
8
IN
42 80
OUT
43 80
OUT
8
OUT
8
OUT
42 80
OUT
43 80
OUT
8
OUT
8
OUT
201
MF
201
MF
201
MF
201
MF
18
OUT
18
OUT
18
OUT
201
MF
18
IN
18 62
IN
18 75
IN
18 62
IN
6
24 26
OUT
24 81
OUT
24
OUT
6
24
OUT
USB3_EXTA_RX_P
USB3_EXTB_RX_P
USB3_EXTC_RX_P
USB3_EXTD_RX_P
USB3_EXTA_TX_N
USB3_EXTB_TX_N
USB3_EXTC_TX_N
USB3_EXTD_TX_N
USB3_EXTA_TX_P
USB3_EXTB_TX_P
USB3_EXTC_TX_P
USB3_EXTD_TX_P
PCI_INTA_L
PCI_INTB_L
PCI_INTC_L
PCI_INTD_L
JTAG_GMUX_TMS
BLC_I2C_MUX_SEL
USE_HDD_OOB_L
TP_PCH_STRP_BBS1
TP_PCH_STRP_ESI_L
PCH_STRP_TOPBLK_SWP_L
BLC_GPIO
AUD_IP_PERIPHERAL_DET
TBT_PWR_REQ_L
AUD_I2C_INT_L
TP_PCI_PME_L
PLT_RESET_L
LPC_CLK33M_SMC_R
LPC_CLK33M_LPCPLUS_R
TP_PCI_CLK33M_OUT2
TP_PCI_CLK33M_OUT3
PCH_CLK33M_PCIOUT
TP1
BJ26
TP2
BH25
TP3
BJ16
TP4
BG16
TP5
AH38
TP6
AH37
TP7
AK43
TP8
AK45
TP9
C18
TP10
N30
TP11
H3
TP12
AH12
TP13
AM4
TP14
AM5
TP15
Y13
TP16
K24
TP17
L24
TP18
AB46
TP19
AB45
TP20
B21
TP21
M20
TP22
AY16
TP23
BG46
TP24
BE28
USB3RN1
BC30
USB3RN2
BE32
USB3RN3
BJ32
USB3RN4
BC28
USB3RP1
BE30
USB3RP2
BF32
USB3RP3
BG32
USB3RP4
AV26
USB3TN1
BB26
USB3TN2
AU28
USB3TN3
AY30
USB3TN4
AU26
USB3TP1
AY26
USB3TP2
AV28
USB3TP3
AW30
USB3TP4
K40
PIRQA*
K38
PIRQB*
H38
PIRQC*
G38
PIRQD*
C46
REQ1*/GPIO50
C44
REQ2*/GPIO52
E40
REQ3*/GPIO54
D47
GNT1*/GPIO51
E42
GNT2*/GPIO53
F46
GNT3*/GPIO55
(IPU-PCIERST#)
G42
PIRQE*/GPIO2
G40
PIRQF*/GPIO3
C42
PIRQG*/GPIO4
D44
PIRQH*/GPIO5
K10
PME*
C6
PLTRST*
H49
CLKOUT_PCI0
H43
CLKOUT_PCI1
J48
CLKOUT_PCI2
K42
CLKOUT_PCI3
H40
CLKOUT_PCI4
(IPU)
(IPD)
U1800
PANTHERPOINT
MOBILE
FCBGA
(5 OF 10)
USB
PCI
USBRBIAS*
OC0*/GPIO59
OC1*/GPIO40
OC2*/GPIO41
OC3*/GPIO42
OC4*/GPIO43
OC5*/GPIO9
OC6*/GPIO10
OC7*/GPIO14
6 3
RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
RSVD6
RSVD7
RSVD8
RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
RSVD15
RSVD16
RSVD17
RSVD18
RSVD19
RSVD20
RSVD21
RSVD22
RSVD23
RSVD24
RSVD25
RSVD26
RSVD27
RSVD28
RSVD29
USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P
USBP10N
USBP10P
USBP11N
USBP11P
USBP12N
USBP12P
USBP13N
USBP13P
(IPD)
USBRBIAS
AY7
NC
AV7
NC
AU3
NC
BG4
NC
AT10
NC
BC8
NC
AU2
NC
AT4
NC
AT3
NC
AT1
NC
AY3
NC
AT5
NC
AV3
NC
AV1
NC
BB1
NC
BA3
NC
BB5
NC
BB3
NC
BB7
NC
BE8
NC
BD4
NC
BF6
NC
AV5
NC
AV10
NC
AT8
NC
AY5
NC
BA2
NC
AT12
NC
BF3
NC
C24
A24
C25
B25
C26
A26
K28
H28
E28
D28
C28
A28
C29
B29
N28
M28
L30
K30
G30
E30
C30
A30
L32
K32
G32
E32
C32
A32
C33
B33
A14
K20
B17
C16
L16
A16
D14
C14
USB_EXTA_N
USB_EXTA_P
USB_EXTB_XHCI_N
USB_EXTB_XHCI_P
USB_EXTC_N
USB_EXTC_P
USB_EXTD_XHCI_N
USB_EXTD_XHCI_P
TP_USB_4N
TP_USB_4P
TP_USB_SDN
TP_USB_SDP
TP_USB_WLANN
TP_USB_WLANP
USB_HUB_UP_N
USB_HUB_UP_P
USB_CAMERA_N
USB_CAMERA_P
USB_EXTB_EHCI_N
USB_EXTB_EHCI_P
USB_EXTD_EHCI_N
USB_EXTD_EHCI_P
TP_USB_BT_HSN
TP_USB_BT_HSP
TP_USB_12N
TP_USB_12P
TP_USB_13N
TP_USB_13P
PCH_USB_RBIAS
80
XDP_DA0_PCH_GPIO59_USB_EXTA_OC_L
XDP_DA1_PCH_GPIO40_USB_EXTB_OC_L
XDP_DA2_PCH_GPIO41_USB_EXTC_OC_L
XDP_DA3_PCH_GPIO42_USB_EXTD_OC_L
XDP_DB0_PCH_GPIO43_USB_EXTB_OC_EHCI_L
XDP_DB1_PCH_GPIO9_USB_EXTD_OC_EHCI_L
XDP_DB2_PCH_GPIO10_AP_PWR_EN
XDP_DB3_PCH_GPIO14_SDCONN_STATE_CHANGE
D
42 80
BI
42 80
BI
25 80
BI
25 80
BI
8
80
BI
8
80
BI
8
80
BI
8
80
BI
Ext A (XHCI/EHCI)
Ext B (XHCI)
Ext C (XHCI/EHCI)
Ext D (XHCI) (Mobiles: Trackpad?)
C
Unused
RSVD: SD
RSVD: WiFi
25 80
BI
25 80
BI
32 80
BI
32 80
BI
25 80
BI
25 80
BI
8
BI
8
BI
USB Hub (All LS/FS Devices)
Camera
Ext B (EHCI)
Ext D (EHCI)
RSVD: BT (HS)
Unused
B
Unused
PLACE_NEAR=U1800.B33:2.54mm
1
R2070
2
22.6
1%
1/20W
MF
201
SYNC_MASTER=J31_MLB
PAGE TITLE
PCH PCI/USB/TP/RSVD
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
SYNC_DATE=06/13/2011
DRAWING NUMBER
051-9058
REVISION
6.0.0
BRANCH
PAGE
20 OF 109
SHEET
18 OF 86
SIZE
A
D
18 23
IN
18 23
IN
18 23
IN
18 23
IN
23
IN
23
IN
23
OUT
18 23
IN
124578
OMIT_TABLE
8 7 6 5 4 3
BOM GROUP
RAMCFG_SLOT
BOM OPTIONS
RAMCFG3:H,RAMCFG2:H,RAMCFG1:H,RAMCFG0:H
12
TABLE_BOMGROUP_HEAD
TABLE_BOMGROUP_ITEM
Systems with no chip-down memory should pull all 4 RAMCFG GPIOs high.
Systems with chip-down memory should add pull-downs on another page and set straps per software.
=PP3V3_S0_PCH_GPIO
7
16 17 18 19 30
RAMCFG3:H
R2172
D
XDP_FC1_PCH_GPIO0
19 23
FW_PME_L
8
19 39
IN
DPMUX_UC_IRQ
19
IN
SMC_RUNTIME_SCI_L
19 45
IN
TP_PCH_GPIO8
WOL_EN
19 73
OUT
XDP_FC0_PCH_GPIO15_MEM_VDD_SEL_1V5_L
23
IN
XDP_DD2_PCH_GPIO16_AUD_IPHS_SWITCH_EN_PCH
23
OUT
LPCPLUS_GPIO
6
19 47
BI
ODD_PWR_EN_L
19 41
OUT
PCH_GPIO24
19
(PU necessary?)
SMC_SCI_L
19 46
XDP_DC0_PCH_GPIO28_ISOLATE_CPU_MEM_L
23
35
OUT
TBT_SW_RESET_L
R2180
0
C
OUT
21
5%
MF
TBT_SW_RESET_R_L
19
1/20W
201
XDP_DC1_PCH_GPIO35_MXM_GOOD
23
OUT
XDP_DD0_PCH_GPIO36_DP_GPU_TBT_SEL
19 23
OUT
XDP_DD1_PCH_GPIO37_JTAG_ISP_TCK
23
OUT
JTAG_ISP_TDO
8
19
IN
JTAG_ISP_TDI
8
OUT
FW_PWR_EN_PCH
19 24
OUT
XDP_DD3_PCH_GPIO49_ENET_LOW_PWR_PCH
23
OUT
SPIROM_USE_MLB
6
19 47 56
BI
T7
BMBUSY*/GPIO0
A42
TACH1/GPIO1
H36
TACH2/GPIO6
E38
TACH3/GPIO7
C10
GPIO8
(IPU-RSMRST#)
C4
LAN_PHY_PWR_CTRL/GPIO12
G2
GPIO15
(IPD)
SATA4GP/GPIO16
TACH0/GPIO17
SCLOCK/GPIO22
GPIO24
GPIO27
(IPU-DeepS4/S5)
GPIO28
(IPU-RSMRST#)
STP_PCI*/GPIO34
GPIO35
SATA2GP/GPIO36
(IPD-PLTRST#)
SATA3GP/GPIO37
(IPD-PLTRST#)
SLOAD/GPIO38
SDATAOUT0/GPIO39
SDATAOUT1/GPIO48
SATA5GP/GPIO49/TEMP_ALERT*
GPIO57
VSS_NCTF_0
VSS_NCTF_1
VSS_NCTF_2
VSS_NCTF_3
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_7
VSS_NCTF_8
VSS_NCTF_9
VSS_NCTF_10
VSS_NCTF_11
VSS_NCTF_12
VSS_NCTF_13
BD49
BE49
BF49
U2
D40
T5
E8
E16
P8
K1
K4
V8
M5
N2
M3
V13
V3
D6
A4
A44
A45
A46
A5
A6
B3
B47
BD1
BE1
BF1
OMIT_TABLE
U1800
PANTHERPOINT
MOBILE
FCBGA
(6 OF 10)
NCTF
TACH4/GPIO68
TACH5/GPIO69
TACH6/GPIO70
TACH7/GPIO71
(IPD-PLTRST#?)
CPU/MISC
GPIO
A20GATE
PECI
(IPD)
RCIN*
PROCPWRGD
THRMTRIP*
INIT3_3V*
(IPU)
DF_TVS
TS_VSS1
TS_VSS2
TS_VSS3
TS_VSS4
NC_1
VSS_NCTF_14
VSS_NCTF_15
VSS_NCTF_16
VSS_NCTF_17
VSS_NCTF_18
VSS_NCTF_19
VSS_NCTF_20
VSS_NCTF_21
VSS_NCTF_22
VSS_NCTF_23
VSS_NCTF_24
VSS_NCTF_25
VSS_NCTF_26
VSS_NCTF_27
VSS_NCTF_28
VSS_NCTF_29
VSS_NCTF_30
VSS_NCTF_31
C40
B41
C41
A40
P4
AU16
P5
AY11
AY10
T14
AY1
AH8
AK11
AH10
AK10
P37
BG2
BG48
BH3
BH47
BJ4
BJ44
BJ45
BJ46
BJ5
BJ6
C2
C48
D1
D49
E1
E49
F1
F49
NC
MLB_RAMCFG3
MLB_RAMCFG2
MLB_RAMCFG1
MLB_RAMCFG0
PCH_A20GATE
PCH_PECI
PCH_RCIN_L
PCH_PROCPWRGD
PM_THRMTRIP_L_R
46
PCH_INIT3V3_L
PCH_DF_TVS
NO STUFF
R2130
1/20W
1/20W
19
19
1
1K
This has internal pull up and should not pulled low.
5%
THIS SIGNAL IS INTENDED FOR FIRMWARE HUB AND WE ARE NOT USING IT.
MF
201
2
10K
5%
MF
201
R2170
R2140
R2156
1
2
RAMCFG2:H
1
R2173
10K
5%
1/20W
MF
201
2
43
0
390
NO STUFF
21
CPU_PECI
5%
MF
21
CPU_PWRGD
5%
MF
21
PM_THRMTRIP_L
5%
MF
RAMCFG1:H
R2174
1/20W
201
1/20W
201
1/20W
201
1/20W
10K
RAMCFG0:H
1
1
R2175
10K
5%
5%
1/20W
MF
MF
201
201
2
2
10 46 78
BI
10 23 78
OUT
10 46 78
ININ
R2178
1K
2 1
1/20W
201
=PP1V8_S0_PCH_VCC_DFTERM
1
R2179
2.2K
5%
1/20W
MF
201
2
CPU_PROC_SEL_L
5%
DF_TVS:DMI & FDI Term Voltage
MF
Set to Vss when Low
Set to Vcc when High
10
7
20 22
D
C
SIZE
B
A
D
B
=PP3V3_S5_PCH_GPIO
=PP3V3_SUS_PCH_GPIO
=PP3V3_S0_PCH_GPIO
=PP3V3_T29_PCH_GPIO
R2186
R2199
R2160
R2185
R2196
R2190
R2197
R2184
R2150
R2155
A
R2194
R2192
R2193
R2191
R2111
R2195
R2112
R2198
R2113
R2116
10K
10K
10K
10K
10K
100K
10K
10K
10K
10K
10K
10K
100K
10K
20K
100K
10K
10K
10K
10K
NO STUFF
7
7
16 17 18
7
16 17 18 19 30
7
16
21
1/20W
5%
21
1/20W
5%
21
1/20W
5%
21
1/20W
5%
21
1/20W
5%
21
1/20W
5%
Must stuff R2197 when R2180 NO STUFFed.
21
1/20W
5%
21
1/20W
5%
21
1/20W
5%
21
1/20W
5%
21
1/20W
5%
21
1/20W
5%
21
1/20W
5%
21
1/20W
5%
12
1/20W
5%
12
1/20W
5%
12
1/20W
5%
12
1/20W
5%
12
1/20W
5%
12
1/20W
5%
JTAG_ISP_TDO
201
MF
JTAG_TBT_TDI
201
MF
XDP_FC1_PCH_GPIO0
201
MF
FW_PME_L
201
MF
SMC_RUNTIME_SCI_L
201
MF
LPCPLUS_GPIO
201
MF
TBT_SW_RESET_R_L
201
MF
FW_PWR_EN_PCH
201
MF
PCH_A20GATE
201
MF
PCH_RCIN_L
201
MF
WOL_EN
201
MF
PCH_GPIO24
201
MF
SPIROM_USE_MLB
201
MF
SMC_SCI_L
201
MF
DPMUX_UC_IRQ
201
MF
AUD_IPHS_SWITCH_EN_PCH
201
MF
ODD_PWR_EN_L
201
MF
XDP_DD0_PCH_GPIO36_DP_GPU_TBT_SEL
201
MF
JTAG_ISP_TCK
201
MF
ENET_LOW_PWR_PCH
201
MF
8
19
8
33
19 23
8
19 39
19 45
6
19 47
19
19 24
19
19
19 73
19
6
19 47 56
19 46
19
23 24
19 41
19 23
8
23
23 24
6 3
SYNC_MASTER=J31_MLB
PAGE TITLE
PCH GPIO/MISC/NCTF
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
SYNC_DATE=06/13/2011
DRAWING NUMBER
051-9058
REVISION
6.0.0
BRANCH
PAGE
21 OF 109
SHEET
19 OF 86
124578
8 7 6 5 4 3
12
D
OMIT_TABLE
V5REF
N26
=PP1V05_S0_PCH_VCCIO_USB
P26
P28
T27
T29
T23
=PP3V3_SUS_PCH_VCCSUS_USB
T24
V23
V24
P24
T26
=PP1V05_S0_PCH_VCCIO_PLLUSB
M26
=PP5V_SUS_PCH_V5REFSUS
AN23
AN24
P34
N20
N22
P20
P22
AA16
W16
T34
AJ2
AF13
AH13
AH14
AF14
AK1
AF11
AC16
AC17
AD17
T21
V21
T19
P32
NC-ed per DG
NC
=PP3V3_SUS_PCH_VCCSUS
=PP5V_S0_PCH_V5REF
=PP3V3_SUS_PCH_VCCSUS_GPIO
=PP3V3_S0_PCH_VCC3_3_GPIO
=PP3V3_S0_PCH_VCC3_3_SATA
=PP1V05_S0_PCH_VCCIO_SATA
VCCAPLLSATA pin left as NC per DG
NC
=PP1V8R1V5_S0_PCH_VCCVRM
=PP1V05_S0_PCH_VCCIO_SATA
=PP1V05_S0_PCH_VCCASW
=PP3V3R1V5_S0_PCH_VCCSUSHDA
10 mA Max, 1mA Idle
7
22
7
22
7
22
7
22
7
22
7
22
7
22
7
16 20 22
7
20
7
16 20 22
7
20 22
7
22 24
VCCAFDIPLL pin left as NC per DG
AD49
VCCACLK pin left as NC per DG
=PP3V3_S5_PCH_VCCDSW
7
22
NC
TP_PPVOUT_PCH_DCPSUSBYP
PP3V3_S0_PCH_VCC3_3_CLK_F
22
VCCAPLLDMI2 pin left as NC per DG
=PP1V05_S0_PCH_VCCIO_CLK
7
20 22
AL24 left as NC per DG
=PP1V05_S0_PCH_VCCASW
7
20 22
NC
NC
C
PLACE_NEAR=U1800.N16:2.54mm
B
PCH output, for decoupling only
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V
1
C2210
0.1UF
20%
10V
2
CERM
402
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V
1
C2222
0.1UF
PLACE_NEAR=U1800.V16:2.54mm
20%
10V
2
CERM
402
PPVOUT_G3_PCH_DCPRTC
=PP1V8R1V5_S0_PCH_VCCVRM
7
20
PP1V05_S0_PCH_VCCADPLLA_F
22
PP1V05_S0_PCH_VCCADPLLB_F
22
=PP1V05_S0_PCH_VCCIO_CLK
7
20 22
=PP1V05_S0_PCH_VCCDIFFCLK
7
16 22
55mA Max, 5mA Idle
=PP1V05_S0_PCH_VCCSSC
7
22
PPVOUT_S0_PCH_DCPSST
=PP1V05_S0_PCH_V_PROC_IO
7
22
=PPVRTC_G3_PCH
7
16 17
C2231
PLACE_NEAR=U1800.A22:2.54mm
NC-ed per DG
1
1UF
10%
6.3V
2
CERM
402
NC
NC
1
C2232
0.1UF
20%
10V
2
CERM
402
PLACE_NEAR=U1800.A22:2.54mm
VCCACLK
T16
VCCDSW3_3
V12
DCPSUSBYP
T38
VCC3_3_5_CLK
BH23
VCCAPLLDMI2
AL29
VCCIO_14_PLLCLK
AL24
DCPSUS_3_CLK
AA19
VCCASW_1_CLK
AA21
VCCASW_2_CLK
AA24
VCCASW_3_CLK
AA26
VCCASW_4_CLK
AA27
VCCASW_5_CLK
AA29
VCCASW_6_CLK
AA31
VCCASW_7_CLK
AC26
VCCASW_8_CLK
AC27
VCCASW_9_CLK
AC29
VCCASW_10_CLK
AC31
VCCASW_11_CLK
AD29
VCCASW_12_CLK
AD31
VCCASW_13_CLK
W21
VCCASW_14_CLK
W23
VCCASW_15_CLK
W24
VCCASW_16_CLK
W26
VCCASW_17_CLK
W29
VCCASW_18_CLK
W31
VCCASW_19_CLK
W33
VCCASW_20_CLK
N16
DCPRTC
Y49
VCCVRM_4_CLK
BD47
VCCADPLLA
BF47
VCCADPLLB
AF17
VCCIO_7_CLK
AF33
VCCDIFFCLKN
AF34
VCCDIFFCLKN
AG34
VCCDIFFCLKN
AG33
VCCSSC
V16
DCPSST
T17
DCPSUS_1_CLK
V19
DCPSUS_2_CLK
BJ8
V_PROC_IO
A22
VCCRTC
1
C2233
0.1UF
20%
10V
2
CERM
402
PLACE_NEAR=U1800.A22:2.54mm
U1800
PANTHERPOINT
MOBILE
FCBGA
(8 OF 10)
CLK/MISC
CPURTC
VCCIO_29_USB
VCCIO_30_USB
VCCIO_31_USB
VCCIO_32_USB
VCCIO_33_USB
VCCSUS3_3_7_USB
VCCSUS3_3_8_USB
VCCSUS3_3_9_USB
VCCSUS3_3_10_USB
VCCSUS3_3_6_USB
VCCIO_34_PLLUSB
V5REF_SUS
USB
DCPSUS_4_USB
VCCSUS3_3_1_USB
VCCSUS3_3_2_GPIO
VCCSUS3_3_3_GPIO
VCCSUS3_3_4_GPIO
VCCSUS3_3_5_GPIO
VCC3_3_1_GPIO
VCC3_3_8_GPIO
LPC
VCC3_3_4_GPIO
PCI/GPIO/
VCC3_3_2_SATA
VCCIO_5_PLLSATA
VCCIO_12_SATA3
VCCIO_13_SATA3
VCCIO_6_PLLSATA3
VCCAPLLSATA
SATAMISC
VCCVRM_1_SATA
VCCIO_2_SATA
VCCIO_3_SATA
VCCIO_4_SATA
VCCASW_22_MISC
VCCASW_23_MISC
VCCASW_21_MISC
VCCSUSHDA
HDA
=PP1V05_S0_PCH_VCC_CORE
7
22
1.44 A Max, 474mA Idle
=PP1V05_S0_PCH_VCCIO_PLLPCIE
7
TP_1V05_S0_PCH_VCCAPLLEXP
=PP1V05_S0_PCH_VCCIO
7
22
=PP3V3_S0_PCH_VCC3_3_PCI
7
22
=PP1V8R1V5_S0_PCH_VCCVRM
7
20
=PP1V05_S0_PCH_VCCIO_PLLFDI
7
=PP1V05_S0_PCH_VCCDMI_FDI
7
AA23
VCCCORE
AC23
VCCCORE
AD21
VCCCORE
AD23
VCCCORE
AF21
VCCCORE
AF23
VCCCORE
AG21
VCCCORE
AG23
VCCCORE
AG24
VCCCORE
AG26
VCCCORE
AG27
VCCCORE
AG29
VCCCORE
AJ23
VCCCORE
AJ26
VCCCORE
AJ27
VCCCORE
AJ29
VCCCORE
AJ31
VCCCORE
AN19
VCCIO_28_PLLPCIE
BJ22
VCCAPLLEXP
AN16
VCCIO_15_FDI
AN17
VCCIO_16_FDI
AN21
VCCIO_17_PCIE
AN26
VCCIO_18_PCIE
AN27
VCCIO_19_PCIE
AP21
VCCIO_20_PCIE
AP23
VCCIO_21_PCIE
AP24
VCCIO_22_PCIE
AP26
VCCIO_23_PCIE
AT24
VCCIO_24_PCIE
AN33
VCCIO_25_DP
AN34
VCCIO_26_DP
BH29
VCC3_3_3_PCIE
AP16
VCCVRM_2_FDI
BG6
NC
VCCAFDIPLL
AP17
VCCIO_27_PLLFDI
AU20
VCCDMI_2_FDI
OMIT_TABLE
U1800
PANTHERPOINT
MOBILE
FCBGA
(7 OF 10)
VCC CORE
LVDS
HVCMOS
VCCIO
DMI CRT
FDI
DFT/SPI
VCCADAC
VSSADAC
VCCALVDS
VSSALVDS
VCCTX_LVDS
VCCTX_LVDS
VCCTX_LVDS
VCCTX_LVDS
VCC3_3_6_HVCMOS
VCC3_3_7_HVCMOS
VCCVRM_3_DMI
VCCDMI_1_DMI
VCCCLKDMI
VCCDFTERM
VCCDFTERM
VCCDFTERM
VCCDFTERM
VCCSPI
U48
PP3V3_S0_PCH_VCCA_DAC_F
U47
AK36
=PP3V3_S0_PCH_VCCA_LVDS
AK37
PP1V8_S0_PCH_VCCTX_LVDS_F
AM37
AM38
AP36
AP37
=PP3V3_S0_PCH_VCC3_3_HVCMOS
V33
V34
AT16
=PP1V8R1V5_S0_PCH_VCCVRM
AT20
=PP1V05_S0_PCH_VCC_DMI
AB36
PP1V05_S0_PCH_VCCCLKDMI_F
=PP1V8_S0_PCH_VCC_DFTERM
AG16
AG17
AJ16
AJ17
V1
=PP3V3_SUS_PCH_VCC_SPI
22
7
22
7
22
7
20
7
22
22
7
19 22
7
22
D
C
B
A
SYNC_MASTER=J31_MLB
PAGE TITLE
PCH POWER
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
6 3
SYNC_DATE=06/13/2011
DRAWING NUMBER
051-9058
REVISION
6.0.0
BRANCH
PAGE
22 OF 109
SHEET
20 OF 86
124578
SIZE
A
D
8 7 6 5 4 3
OMIT_TABLE
H5
AA17
AA2
AA3
AA33
AA34
AB11
AB14
AB39
AB4
D
C
B
AB43
AC19
AC21
AC24
AC33
AC34
AC48
AD10
AD11
AD12
AD13
AD19
AD24
AD26
AD27
AD33
AD34
AD36
AD37
AD38
AD39
AD40
AD42
AD43
AD45
AD46
AF10
AF12
AD14
AD16
AF16
AF19
AF24
AF26
AF27
AF29
AF31
AF38
AF42
AF46
AG19
AG31
AG48
AH11
AH36
AH39
AH40
AH42
AH46
AJ19
AJ21
AJ24
AJ33
AJ34
AK12
AB5
AB7
AC2
AD4
AD8
AE2
AE3
AF4
AF5
AF7
AF8
AG2
AH3
AH7
AK3
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
U1800
PANTHERPOINT
MOBILE
FCBGA
(9 OF 10)
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AK38
AK4
AK42
AK46
AK8
AL16
AL17
AL19
AL2
AL21
AL23
AL26
AL27
AL31
AL33
AL34
AL48
AM11
AM14
AM36
AM39
AM43
AM45
AM46
AM7
AN2
AN29
AN3
AN31
AP12
AP19
AP28
AP30
AP32
AP38
AP4
AP42
AP46
AP8
AR2
AR48
AT11
AT13
AT18
AT22
AT26
AT28
AT30
AT32
AT34
AT39
AT42
AT46
AT7
AU24
AU30
AV11
AV16
AV20
AV24
AV30
AV38
AV4
AV43
AV8
AW14
AW18
AW2
AW22
AW26
AW28
AW32
AW34
AW36
AW40
AW48
AY12
AY22
AY28
A
AY42
AY46
BB12
BB16
BB20
BB22
BB24
BB28
BB30
BB38
BB46
BC14
BC18
BC22
BC26
BC32
BC34
BC36
BC40
BC42
BC48
BD46
BE22
BE26
BE40
BF10
BF12
BF16
BF20
BF22
BF24
BF26
BF28
BF30
BF38
BF40
BG17
BG21
BG33
BG44
BH11
BH15
BH17
BH19
BH27
BH31
BH33
BH35
BH39
BH43
AY4
AY8
B11
B15
B19
B23
B27
B31
B35
B39
B7
F45
BB4
BC2
BD5
BD3
BF8
BG8
H10
BH7
D3
D12
D16
D18
D22
D24
D26
D30
D32
D34
D38
D42
D8
E18
E26
G18
G20
G26
G28
G36
G48
H12
H18
H22
H24
H26
H30
H32
H34
F3
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
OMIT_TABLE
U1800
PANTHERPOINT
MOBILE
FCBGA
(10 OF 10)
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
H46
K18
K26
K39
K46
K7
L18
L2
L20
L26
L28
L36
L48
M12
P16
M18
M22
M24
M30
M32
M34
M38
M4
M42
M46
M8
N18
P30
N47
P11
P18
T33
P40
P43
P47
P7
R2
R48
T12
T31
T37
T4
W34
T46
T47
T8
V11
V17
V26
V27
V29
V31
V36
V39
V43
V7
W17
W19
W2
W27
W48
Y12
Y38
Y4
Y42
Y46
Y8
BG29
N24
AJ3
AD47
B43
BE10
BG41
G14
H16
T36
BG22
BG24
C22
AP13
M14
AP3
AP1
BE16
BC16
BG28
BJ28
SYNC_MASTER=J31_MLB
PAGE TITLE
PCH GROUNDS
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
6 3
12
SYNC_DATE=06/13/2011
DRAWING NUMBER
051-9058
REVISION
6.0.0
BRANCH
PAGE
23 OF 109
SHEET
21 OF 86
124578
SIZE
D
C
B
A
D
8 7 6 5 4 3
12
L2406
=PP1V05_S0_PCH
7
16
10UH-0.12A-0.36OHM
0603
21
PP1V05_S0_PCH_VCCCLKDMI_R
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM
VOLTAGE=1.05V
PLACE_NEAR=U1800.AB36:2.54mm
R2415
0
5%
1/16W
MF-LF
402
PP1V05_S0_PCH_VCCCLKDMI_F
21
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM
VOLTAGE=1.05V
MAKE_BASE=TRUE
1
C2411
10UF
20%
6.3V
2
CERM-X5R
0402-1
20
PLACE_NEAR=U1800.P24:2.54mm
D
L2407
=PP1V8_S0_PCH_VCCTX_LVDS
7
=PP3V3_S0_PCH_VCCADAC
7
C
=PP3V3_S0_PCH
7
16
=PP5V_S0_PCH
7
24
1 mA
PLACE_NEAR=U1800.P34:2.54mm
0.1UH
21
PP1V8_S0_PCH_VCCTX_LVDS_F
0805
R2450
1/16W
MF-LF
402
C2450
PLACE_NEAR=U1800.U48:2.54mm
PLACE_NEAR=U1800.U48:2.54mm
PLACE_NEAR=U1800.U48:2.54mm
R2405
C2439
20
C2400
22UF
20%
6.3V
CERM
805
PLACE_NEAR=U1800.AM37:2.54mm
PLACE_NEAR=U1800.AM37:2.54mm
PLACE_NEAR=U1800.AM37:2.54mm
0
21
5%
1
10UF
20%
6.3V
2
X5R
603
2
100
NC
5%
1/16W
MF-LF
402
1
1
1UF
10%
10V
2
X5R
402
C2406
0.01UF
X7R-CERM
0402
10%
16V
1
2
C2408
1
2
PP3V3_S0_PCH_VCCA_DAC_F
1
C2451
0.1UF
X7R-CERM
5
NC
C2455
0.01UF
10%
16V
2
X7R-CERM
0402
PCH V5REF Filter & Follower
(PCH Reference for 5V Tolerance on PCI)
1
D2400
BAT54DW-X-G
SOT-363
6
PP5V_S0_PCH_V5REF
MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.25MM
VOLTAGE=5V
MAKE_BASE=TRUE
0402
=PP5V_S0_PCH_V5REF
0.01UF
10%
16V
X7R-CERM
0402
1
10%
16V
2
NEED PWR CONSTRAINT
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM
VOLTAGE=1.8V
1
2
MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V
<1 MA
20
20
=PP3V3_S0_PCH_VCC3_3_CLK
7
PCH VCCSUS3_3 BYPASS
(PCH SUSPEND USB 3.3V PWR)
=PP3V3_SUS_PCH_VCCSUS_USB
7
20
1
C2484
0.1UF
10%
16V
2
X7R-CERM
0402
=PP1V05_S0_PCH_V_PROC_IO
7
20
PLACE_NEAR=U1800.BJ8:2.54mm
PLACE_NEAR=U1800.BJ8:2.54mm
PLACE_NEAR=U1800.BJ8:2.54mm
PCH VCCIO BYPASS
=PP1V05_S0_PCH_VCC_DMI
7
20
PCH VCC3_3 BYPASS
(PCH PCI 3.3V PWR)
PLACE_NEAR=U1800.AT20:2.54mm
R2451
1
21
5%
1/16W
MF-LF
402
1
C2413
0.1UF
10%
16V
2
X7R-CERM
0402
PLACE_NEAR=U1800.V24:2.54mm
1
1
C2416
4.7UF
20%
6.3V
X5R
402
1
C2419
1UF
10%
6.3V
2
CERM
402
C2417
0.1UF
10%
16V
2
2
X7R-CERM
0402
10UH-0.12A-0.36OHM
PP3V3_S0_PCH_VCC3_3_CLK_R
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V
1
C2430
0.1UF
10%
16V
2
X7R-CERM
0402
PLACE_NEAR=U1800.T16:2.54mm
L2451
21
20
0603
C2453
10UF
6.3V
CERM-X5R
0402-1
PLACE_NEAR=U1800.T38:2.54mm
PLACE_NEAR=U1800.T38:2.54mm
20
PP3V3_S0_PCH_VCC3_3_CLK_F
20%
=PP1V8_S0_PCH_VCC_DFTERM
7
19 20
PLACE_NEAR=U1800.AJ16:2.54mm
PCH VCCSUSHDA BYPASS
(PCH HD Audio 3.3V/1.5V PWR)
=PP3V3R1V5_S0_PCH_VCCSUSHDA
7
20 24
PLACE_NEAR=U1800.P32:2.54mm
=PP3V3_SUS_PCH_VCC_SPI
7
20
PLACE_NEAR=U1800.V1:2.54mm
=PP3V3_S5_PCH_VCCDSW
7
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
C2454
VOLTAGE=3.3V
1
2
1UF
10%
10V
X5R
402
1
2
C2499
0.1UF
20%
10V
CERM
402
1
2
1
C2441
0.1UF
20%
10V
2
CERM
402
1
C2442
1UF
10%
6.3V
2
CERM
402
1
2
C2440
0.1UF
20%
10V
CERM
402
=PP1V05_S0_PCH_VCCIO_SATA
7
16 20
PLACE_NEAR=U1800.AH13:2.54mm
PLACE_NEAR=U1800.AC17:2.54mm
7
20
PLACE_NEAR=U1800.AG33:2.54mm
7
16 20
PLACE_NEAR=U1800.AF34:2.54mm
=PP1V05_S0_PCH_VCCIO
7
20
1
C2444
1UF
10%
6.3V
2
CERM
402
1
C2452
1UF
10%
6.3V
2
CERM
402
=PP1V05_S0_PCH_VCCSSC
1
2
=PP1V05_S0_PCH_VCCDIFFCLK
=PP1V05_S0_PCH_VCC_CORE
7
20
1
C2481
1UF
10%
6.3V
2
CERM
402
PLACE_NEAR=U1800.AD21:2.54mm
PLACE_NEAR=U1800.AG24:2.54mm
PLACE_NEAR=U1800.AJ27:2.54mm
PLACE_NEAR=U1800.AG26:2.54mm
1
C2429
1UF
10%
6.3V
2
CERM
402
1
2
1
C2414
1UF
10%
6.3V
2
CERM
402
C2475
1UF
10%
6.3V
CERM
402
1
C2434
1UF
2
C2482
1UF
10%
6.3V
CERM
402
PCH VCCIO BYPASS
(PCH USB 1.05V PWR)
=PP1V05_S0_PCH_VCCIO_USB
7
20
PLACE_NEAR=U1800.P28:2.54mm
=PP3V3_SUS_PCH_VCCSUS_GPIO
7
20
PLACE_NEAR=U1800.P22:2.54mm
=PP1V05_S0_PCH_VCCIO_CLK
7
20
10%
6.3V
CERM
402
PLACE_NEAR=U1800.AF17:2.54mm
PCH VCCCORE BYPASS
(PCH 1.05V CORE PWR)
1
C2460
2
1
C2407
1UF
10%
6.3V
2
CERM
402
C2483
1UF
10%
6.3V
CERM
402
1
C2463
1UF
10%
6.3V
2
CERM
402
10UF
20%
6.3V
X5R
603
C2401
10UF
1
2
6.3V
20%
X5R
603
1
C2446
1UF
10%
6.3V
2
CERM
402
D
1
C2476
1UF
10%
6.3V
2
CERM
402
1
C2469
1UF
10%
6.3V
2
CERM
402
C
1
2
=PP3V3_SUS_PCH
B
PLACE_NEAR=U1800.M26:2.54mm
=PP3V3_S0_PCH_VCC3_3_PCI
7
20
PLACE_NEAR=U1800.BH29:2.54mm
A
=PP3V3_S0_PCH_VCC3_3_HVCMOS
7
20
PLACE_NEAR=U1800.V33:2.54mm
7
=PP5V_SUS_PCH
7
1 mA S0-S5
C2438
1
C2421
0.1UF
10%
16V
2
X7R-CERM
0402
R2404
1/16W
MF-LF
402
0.1UF
20%
10V
CERM
402
1
C2424
0.1UF
10%
16V
2
X7R-CERM
0402
PCH V5REF_SUS Filter & Follower
(PCH Reference for 5V Tolerance on USB)
2
10
5%
1
1
2
4
2
D2400
NC
NC
BAT54DW-X-G
SOT-363
3
PP5V_SUS_PCH_V5REFSUS
MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.25MM
VOLTAGE=5V
MAKE_BASE=TRUE
=PP5V_SUS_PCH_V5REFSUS
20
NEED PWR CONSTRAINT
=PP3V3_S0_PCH_VCC3_3_SATA
7
PLACE_NEAR=U1800.AJ2:2.54mm
=PP3V3_S0_PCH_VCC3_3_GPIO
7
20
PLACE_NEAR=U1800.T34:2.54mm
<1 MA S0-S5
20
1
C2486
0.1UF
10%
25V
2
X5R
402
1
C2423
0.1UF
10%
16V
2
X7R-CERM
0402
1
C2485
0.1UF
10%
25V
2
PLACE_NEAR=U1800.AA16:2.54mm
X5R
402
=PP1V05_S0_PCH_VCCADPLL
7
R2460
0
5%
1/16W
MF-LF
402
R2465
0
5%
1/16W
MF-LF
402
PCH VCCADPLLA Filter
1
C2402
0.1UF
20%
10V
2
CERM
402
1
C2465
0.1UF
20%
10V
2
CERM
402
(PCH DPLLA PWR)
PP1V05_S0_PCH_VCCADPLLA_F
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
1
C2461
1UF
10%
6.3V
2
CERM
402
PCH VCCADPLLB Filter
(PCH DPLLB PWR)
PP1V05_S0_PCH_VCCADPLLB_F
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
1
C2466
1UF
10%
6.3V
2
CERM
402
PLACE_NEAR=U1800.BD47:2.54MM
PLACE_NEAR=U1800.BF47:2.54MM
68 mA
69 mA
20
=PP1V05_S0_PCH_VCCASW
7
20
1
C2426
1UF
10%
6.3V
2
CERM
402
20
PLACE_NEAR=U1800.AC27:2.54mm
PLACE_NEAR=U1800.AC27:2.54mm
PLACE_NEAR=U1800.AC27:2.54mm
PLACE_NEAR=U1800.AC27:2.54mm
PLACE_NEAR=U1800.AC27:2.54mm
21
21
6 3
PLACE_NEAR=U1800.AN27:2.54mm
PLACE_NEAR=U1800.AN27:2.54mm
PLACE_NEAR=U1800.AN27:2.54mm
PLACE_NEAR=U1800.AN27:2.54mm
PLACE_NEAR=U1800.AN27:2.54mm
C2456
1UF
10%
6.3V
CERM
402
1
C2496
1UF
10%
6.3V
2
CERM
402
C2428
22UF
20%
6.3V
CERM
805
1
C2420
2
1
2
PAGE TITLE
PCH DECOUPLING
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
22UF
6.3V
CERM
20%
805
1
2
SYNC_DATE=02/15/2011SYNC_MASTER=K90I_MLB
DRAWING NUMBER
051-9058
REVISION
6.0.0
BRANCH
PAGE
24 OF 109
SHEET
22 OF 86
124578
SIZE
B
A
D
8 7 6 5 4 3
12
=PPVCCIO_S0_XDP
7
23
=PP3V3_S0_XDP
7
XDP_CPU_PREQ_L
10 78
BI
XDP_CPU_PRDY_L
10 78
D
(R2560-R2563)
XDP_CPU:BPM
XDP_CPU:BPM
XDP_CPU:BPM
XDP_CPU:BPM
10
IN
10
IN
10
IN
10
IN
9
78
IN
9
78
IN
9
78
IN
9
78
IN
10 19 78
IN
17 23 45
OUT
9
23 78
OUT
17 24 45
OUT
XDP_BPM_L<4>
XDP_BPM_L<5>
XDP_BPM_L<6>
XDP_BPM_L<7>
CPU_CFG<12>
CPU_CFG<13>
CPU_CFG<14>
CPU_CFG<15>
CPU_PWRGD
PM_PWRBTN_L
CPU_CFG<0>
PLACE_NEAR=U1000.C60:2.54mm
PLACE_NEAR=U4900.P17:2.54mm
PLACE_NEAR=U1000.B57:2.54mm
PM_PCH_SYS_PWROK
R2560
R2561
R2562
R2563
R2564
R2565
R2566
R2567
R2500
R2502
R2501
R2504
0
0
0
0
(R2564-R2567)
XDP_CPU:CFG
XDP_CPU:CFG
XDP_CPU:CFG
XDP_CPU:CFG
0
0
0
0
1K
0
1K
330
21
5% 201MF
21
5% 201MF
21
5% 201MF
21
5% 201MF
21
5% 201MF
21
5% 201MF
21
5%
21
5% MF
XDP
21
5%
XDP
21
5% 201
XDP
21
5%
XDP
21
5% 201MF
1/20W
1/20W
1/20W
1/20W
1/20W
1/20W
1/20W
1/20W
1/20W
1/20W
1/20W
1/20W
201MF
201
201MF
MF
201MF
C
XDP SIGNALS
R2584
R2585
R2520
R2521
R2522
R2523
R2524
R2525
R2526
R2527
R2528
R2529
R2530
R2531
R2532
R2533
R2534
R2535
R2536
R2537
XDP_DA0_USB_EXTA_OC_L
23
OUT
XDP_DA1_USB_EXTB_OC_L
23
OUT
XDP_DA2_USB_EXTC_OC_L
23
OUT
XDP_DA3_USB_EXTD_OC_L
23
OUT
XDP_DB0_USB_EXTB_OC_EHCI_L
23
OUT
XDP_DB1_USB_EXTD_OC_EHCI_L
23
OUT
XDP_DB2_AP_PWR_EN
23
IN
XDP_DB3_SDCONN_STATE_CHANGE
23
OUT
XDP_FC0
23
OUT
XDP_FC1
23
OUT
XDP_DC0_ISOLATE_CPU_MEM_L
23
IN
XDP_DC1_MXM_GOOD
23
IN
XDP_DC2_DP_AUXCH_ISOL
23
IN
XDP_DC3_SATARDRVR_EN
23
IN
XDP_DD0_DP_GPU_TBT_SEL
23
IN
XDP_DD1_JTAG_ISP_TCK
23
IN
XDP_DD2_AUD_IPHS_SWITCH_EN
23
IN
XDP_DD3_ENET_LOW_PWR
23
IN
B
PCH/XDP Signal Isolation Notes:
- Following Intel’s Debug Prot Design Guid for HR and CR v1.3
doc id 404081.
Initially, stuffing both 33 and 0 ohms and validate whether
it is functional in that state, else add BOM options.
- For isolated GPIOs:
- ’Output’ non-XDP signals require pulls.
- ’Output’ PCH/XDP signals require pulls.
R252x, R253x, R257x and R259x should be placed where signal path
needs to split between route from PCH to J2550
and path to non-XDP signal destination.
ALL_SYS_PWRGD
24 45 73
17 23 45
OUT
IN
PM_PWRBTN_L
PLACE_NEAR=J2550.39:2.54mm
PLACE_NEAR=U4900.P17:2.54mm
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
1K
0
(R2520-R2537)
XDP
XDP
XDP
XDP
XDP
XDP
XDP
XDP
XDP
XDP
XDP
XDP
XDP
XDP
XDP
XDP
XDP
XDP
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
XDP
21
1/20W
5% 201MF
XDP
21
1/20W
5% 201MF
PCH SIGNALS
1/20W
5% 201MF
5% MF
1/20W
1/20W
5% 201MF
1/20W
5% 201MF
5% 201MF
1/20W
1/20W
5% 201MF
1/20W
5%
1/20W
5% 201MF
1/20W
5% 201MF
1/20W
5% 201MF
1/20W
5% 201MF
1/20W
5% 201MF
1/20W
5% 201MF
1/20W
5% 201MF
1/20W
5% 201MF
1/20W
5%
1/20W
5%
5% 201MF
1/20W
XDP_DB0_PCH_GPIO43_USB_EXTB_OC_EHCI_L
XDP_DB3_PCH_GPIO14_SDCONN_STATE_CHANGE
XDP_DD2_PCH_GPIO16_AUD_IPHS_SWITCH_EN_PCH
A
1/20W
XDP_DA0_PCH_GPIO59_USB_EXTA_OC_L
XDP_DA1_PCH_GPIO40_USB_EXTB_OC_L
201
XDP_DA2_PCH_GPIO41_USB_EXTC_OC_L
XDP_DA3_PCH_GPIO42_USB_EXTD_OC_L
XDP_DB1_PCH_GPIO9_USB_EXTD_OC_EHCI_L
201MF
XDP_FC0_PCH_GPIO15_MEM_VDD_SEL_1V5_L
XDP_DC0_PCH_GPIO28_ISOLATE_CPU_MEM_L
XDP_DC2_PCH_GPIO21_DP_AUXCH_ISOL
XDP_DC3_PCH_GPIO19_SATARDRVR_EN
XDP_DD0_PCH_GPIO36_DP_GPU_TBT_SEL
XDP_DD1_PCH_GPIO37_JTAG_ISP_TCK
201MF
201MF
XDP_DD3_PCH_GPIO49_ENET_LOW_PWR_PCH
23 48
23 48
16 23
IN
XDP_BPM_L<0>
10 78
IN
XDP_BPM_L<1>
10 78
IN
XDP_BPM_L<2>
10 78
IN
XDP_BPM_L<3>
10 78
IN
CPU_CFG<10>
9
78
IN
CPU_CFG<11>
9
78
IN
XDP_OBSDATA_B<0>
XDP_OBSDATA_B<1>
XDP_OBSDATA_B<2>
XDP_OBSDATA_B<3>
XDP_CPU_PWRGD
XDP_CPU_PWRBTN_L
XDP_CPU_CFG<0>
XDP_VR_READY
=SMBUS_XDP_SDA
23 48
BI
=SMBUS_XDP_SCL
23 48
IN
XDP_CPU_TCK
10 23 78
OUT
R2581
21
1/20W
5%
201
MF
1K
XDP_DB2_PCH_GPIO10_AP_PWR_EN
XDP_FC1_PCH_GPIO0
XDP_DC1_PCH_GPIO35_MXM_GOOD
TP_XDP_PCH_OBSFN_A<0>
6
TP_XDP_PCH_OBSFN_A<1>
6
XDP_DA0_USB_EXTA_OC_L
23
XDP_DA1_USB_EXTB_OC_L
23
XDP_DA2_USB_EXTC_OC_L
23
XDP_DA3_USB_EXTD_OC_L
23
TP_XDP_PCH_OBSFN_B<0>
6
TP_XDP_PCH_OBSFN_B<1>
6
XDP_DB0_USB_EXTB_OC_EHCI_L
23
XDP_DB1_USB_EXTD_OC_EHCI_L
23
XDP_DB2_AP_PWR_EN
23
XDP_DB3_SDCONN_STATE_CHANGE
23
XDP_PCH_S5_PWRGD
6
XDP_PCH_PWRBTN_L
6
TP_XDPPCH_HOOK2
6
TP_XDPPCH_HOOK3
6
=SMBUS_XDP_SDA
BI
=SMBUS_XDP_SCL
IN
XDP_PCH_TCK
OUT
R2580
201
NO STUFF
1K
R2540
1/16W
MF-LF
21
5%
MF
402
1K
5%
1
2
OBSDATA_A0
OBSDATA_A1
OBSDATA_A2
OBSDATA_A3
OBSDATA_B0
OBSDATA_B1
OBSDATA_B2
OBSDATA_B3
PWRGD/HOOK0
VCC_OBS_AB
18 23
IN
18 23
IN
18
IN
18
IN
18
IN
18
IN
18 23
OUT
18 23
IN
19 23
IN
19
IN
19 23
OUT
19
OUT
16 23
OUT
16 23
OUT
19
OUT
19 23
OUT
19 23
OUT
19 23
OUT
OBSDATA_A0
OBSDATA_A1
OBSDATA_A2
OBSDATA_A3
OBSDATA_B0
OBSDATA_B1
OBSDATA_B2
OBSDATA_B3
PWRGD/HOOK0
VCC_OBS_AB
OBSFN_A0
OBSFN_A1
OBSFN_B0
OBSFN_B1
HOOK1
HOOK2
HOOK3
TCK1
TCK0
C2500
0.1UF
X7R-CERM
NOTE: This is not the standard XDP pinout.
Use with 921-0133 Adapter Flex to
support chipset debug.
OBSFN_A0
OBSFN_A1
OBSFN_B0
OBSFN_B1
HOOK1
HOOK2
HOOK3
TCK1
TCK0
C2580
0.1UF
X7R-CERM
CPU Micro2-XDP
CRITICAL
XDP_CONN
J2500
DF40RC-60DP-0.4V
M-ST-SM
62
8 7
10
12 11
14 13
16 15
18 17
20219
22 21
24 23
26 25
28 27
30329
32 31
34 33
36 35
38 37
40439
42 41
44 43
46 45
48 47
50549
SDA
SCL
XDP
0402
10%
16V
1
2
52 51
54 53
56 55
NC
58 57
60659
64 63
998-2516
PCH Micro2-XDP
CRITICAL
XDP_CONN
J2550
DF40RC-60DP-0.4V
M-ST-SM
62
8 7
10
12 11
14 13
16 15
18 17
20219
22 21
24 23
26 25
28 27
30329
32 31
34 33
36 35
38 37
40439
42 41
44 43
46 45
48 47
50549
SDA
SCL
XDP
0402
10%
16V
1
2
52 51
54 53
56 55
NC
58 57
60659
64 63
998-2516
NOTE: This is not the standard XDP pinout.
Use with 921-0133 Adapter Flex to
support chipset debug.
61
1
9
OBSFN_C0
OBSFN_C1
OBSDATA_C0
OBSDATA_C1
OBSDATA_C2
OBSDATA_C3
OBSFN_D0
OBSFN_D1
OBSDATA_D0
OBSDATA_D1
OBSDATA_D2
OBSDATA_D3
ITPCLK/HOOK4
ITPCLK#/HOOK5
VCC_OBS_CD
RESET#/HOOK6
DBR#/HOOK7
NOTE: XDP_DBRESET_L pulled-up to 3.3V on PCH Support Page
TDO
TRSTn
TDI
TMS
XDP_PRESENT#
XDP
1
C2501
0.1UF
10%
16V
2
X7R-CERM
0402
=PP3V3_S5_XDP
61
1
9
OBSFN_C0
OBSFN_C1
OBSDATA_C0
OBSDATA_C1
OBSDATA_C2
OBSDATA_C3
OBSFN_D0
OBSFN_D1
OBSDATA_D0
OBSDATA_D1
OBSDATA_D2
OBSDATA_D3
ITPCLK/HOOK4
ITPCLK#/HOOK5
VCC_OBS_CD
RESET#/HOOK6
DBR#/HOOK7
NOTE: XDP_DBRESET_L pulled-up to 3.3V on PCH Support Page
TDO
TRSTn
TDI
TMS
XDP_PRESENT#
XDP
1
C2581
0.1UF
10%
16V
2
X7R-CERM
0402
CPU_CFG<16>
CPU_CFG<17>
CPU_CFG<0>
CPU_CFG<1>
CPU_CFG<2>
CPU_CFG<3>
CPU_CFG<8>
CPU_CFG<9>
CPU_CFG<4>
CPU_CFG<5>
CPU_CFG<6>
CPU_CFG<7>
XDP_CPU_CLK100M_P
78
XDP_CPU_CLK100M_N
78
XDP_CPURST_L
78
XDP_DBRESET_L
XDP_CPU_TDO
XDP_CPU_TRST_L
XDP_CPU_TDI
XDP_CPU_TMS
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
IN
OUT
OUT
OUT
9
9
9
23 78
9
78
9
78
9
78
9
78
9
78
9
78
9
78
9
78
9
78
10 23 24 78
10 23 78
10 23 78
10 23 78
10 23 78
PCH SIGNALS
XDP_DA0_PCH_GPIO59_USB_EXTA_OC_L
18 23
OUT
XDP_DA1_PCH_GPIO40_USB_EXTB_OC_L
18 23
OUT
XDP_DB2_PCH_GPIO10_AP_PWR_EN
18 23
IN
XDP_DB3_PCH_GPIO14_SDCONN_STATE_CHANGE
18 23
OUT
XDP_DC3_PCH_GPIO19_SATARDRVR_EN
16 23
IN
XDP_DC0_PCH_GPIO28_ISOLATE_CPU_MEM_L
19 23
OUT
XDP_DC2_PCH_GPIO21_DP_AUXCH_ISOL
16 23
IN
XDP_FC0_PCH_GPIO15_MEM_VDD_SEL_1V5_L
19 23
IN
7
XDP_DD1_PCH_GPIO37_JTAG_ISP_TCK
XDP_DD2_PCH_GPIO16_AUD_IPHS_SWITCH_EN_PCH
19 23
OUT
XDP_DD3_PCH_GPIO49_ENET_LOW_PWR_PCH
19 23
OUT
XDP_FC0
XDP_FC1
XDP_DC0_ISOLATE_CPU_MEM_L
XDP_DC1_MXM_GOOD
XDP_DC2_DP_AUXCH_ISOL
XDP_DC3_SATARDRVR_EN
TP_XDP_PCH_OBSFN_D<0>
TP_XDP_PCH_OBSFN_D<1>
XDP_DD0_DP_GPU_TBT_SEL
XDP_DD1_JTAG_ISP_TCK
XDP_DD2_AUD_IPHS_SWITCH_EN
XDP_DD3_ENET_LOW_PWR
TP_XDP_PCH_HOOK4
TP_XDP_PCH_HOOK5
XDPPCH_PLTRST_L
XDP_DBRESET_L
XDP_PCH_TDO
TP_XDP_PCH_TRST_L
XDP_PCH_TDI
XDP_PCH_TMS
R2515
R2516
R2505
23
23
23
23
23
23
6
6
23
23
23
23
6
6
24
IN
10 23 24 78
OUT
16 23
IN
16 23
OUT
16 23
OUT
XDP_CPU_TDO
10 23 78
XDP_CPU_TDI
10 23 78
XDP_CPU_TMS
10 23 78
XDP_CPU_TCK
10 23 78
XDP_CPU_TRST_L
10 23 78
XDP
0
0
1K
R2590
R2591
R2596
R2597
R2573
R2570
R2572
R2574
PLACE_NEAR=R1841.1:2.54mm
21
ITPXDP_CLK100M_P
1/20W
5% 201MF
XDP
PLACE_NEAR=R1840.1:2.54mm
21
ITPXDP_CLK100M_N
1/20W
5% 201MF
XDP
PLACE_NEAR=U1000.G3:2.54mm
21
CPU_RESET_L
5% 201MF
1/20W
0
0
0
0
0
0
0
0
R2575
R2576
R2577
0
0
0
XDP_PCH_TDO
16 23
XDP_PCH_TDI
16 23
XDP_PCH_TMS
16 23
XDP_PCH_TCK
16 23
1K series R on PCH Support Page
R2510
R2511
R2512
R2513
R2514
21
21
5% 201MF
21
5% 201MF
21
5% 201MF
21
5% 201MF
21
5% 201MF
21
21
5% 201MF
21
5% 201MF
21
5% 201MF
21
5% 201MF
R2550
R2551
R2552
R2556
SYNC_MASTER=J31_MLB
PAGE TITLE
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
51
51
51
51
51
16 78
IN
16 78
IN
10 24
IN
Non-XDP Signals
MF 2015%
1/20W
1/20W
1/20W
1/20W
1/20W
1/20W
MF 2015%
1/20W
1/20W
1/20W
AUD_IPHS_SWITCH_EN_PCH
1/20W
1/20W
51
51
51
51
CPU & PCH XDP
Apple Inc.
R
6 3
=PPVCCIO_S0_XDP
7
23
XDP
PLACE_NEAR=J2500.52:2.54mm
12
1/20W
5% 201MF
XDP
PLACE_NEAR=U1000.K61:2.54mm
12
1/20W
5% 201MF
XDP
PLACE_NEAR=U1000.H59:2.54mm
12
1/20W
5% 201MF
XDP
PLACE_NEAR=U1000.J58:2.54mm
12
1/20W
5% 201MF
XDP
PLACE_NEAR=U1000.H63:2.54mm
12
1/20W
5% 201MF
USB_EXTA_OC_L
USB_EXTB_OC_L
SDCONN_STATE_CHANGE
AP_PWR_EN
SATARDRVR_EN
ISOLATE_CPU_MEM_L
DP_AUXCH_ISOL
MEM_VDD_SEL_1V5_L
JTAG_ISP_TCK
ENET_LOW_PWR_PCH
=PP1V05_SUS_PCH_JTAG
7
XDP
PLACE_NEAR=J2550.52:2.54mm
12
1/20W
5% 201MF
XDP
PLACE_NEAR=U1800.K5:2.54mm
12
1/20W
5% 201MF
XDP
PLACE_NEAR=U1800.H7:2.54mm
12
1/20W
5% 201MF
XDP
PLACE_NEAR=U1800.J3:2.54mm
12
1/20W
5% 201MF
SYNC_DATE=06/13/2011
IN
IN
OUT
IN
OUT
OUT
OUT
OUT
OUTOUT
OUT
OUT
DRAWING NUMBER
051-9058
REVISION
6.0.0
BRANCH
PAGE
25 OF 109
SHEET
23 OF 86
124578
42
42
18 32 73
24
16 41
26
16 75
67
8
19 19 23
19 24
19 24
SIZE
D
C
B
A
D
8 7 6 5 4 3
12
D
GreenClk 25MHz Power
Ethernet XTAL Power
SB XTAL Power
T29 XTAL Power
C
B
A
System RTC Power Source & 32kHz / 25MHz Clock Generator
=PPVBAT_G3_SYSCLK
7
Coin-Cell: VBAT (300-ohm & 10uF RC)
No Coin-Cell: 3.42V G3Hot (no RC)
=PP3V3_S5_SYSCLK
7
Coin-Cell & G3Hot: 3.42V G3Hot
Coin-Cell & No G3Hot: 3.3V S5
=PP3V3_ENET_SYSCLK
7
=PPVDDIO_ENET_CLK
7
=PPVDDIO_S0_SBCLK
7
=PPVDDIO_T29_CLK
7
1
C2624
0.1UF
X5R-CERM
C2605
12PF
2 1
5%
50V
C0G-CERM
0402
C2606
12PF
21
5%
50V 4
C0G-CERM
0402
SYSCLK_CLK25M_X2
CRITICAL
Y2605
NC
SM-3.2X2.5MM
42
NC
31
25.000MHZ-12PF-20PPM
NOTE: 30 PPM crystal required
0201
10%
16V
2
C2622
0.1UF
X5R-CERM
0201
R2605
0
5%
1/20W
MF
201
No Coin-Cell: 3.3V S5
1
C2620
0.1UF
10%
16V
21
10%
16V
2
X5R-CERM
0201
SYSCLK_CLK25M_X2_R
NO STUFF
1
R2606
1M
5%
1/20W
MF
201
2
SYSCLK_CLK25M_X1
No bypass necessary
5172
1
1
C2602
1UF
10%
10V
2
2
X5R
402-1
11
6
14
3
4
VDD_25M
U2600
SLG3NB148A
CRITICAL
VDDIO_25M_A
VDDIO_25M_B
VDDIO_25M_C
X2
X1
+V3.3A
TQFN
VDD_RTC_OUT
THRM
GND
PAD
16107
13
VBAT and +V3.3A are
internally ORed to
+3.42V
create VDD_RTC_OUT.
+V3.3A should be first
available ~3.3V power
to reduce VBAT draw.
12
32KHZ_A
9
25MHZ_A
8
25MHZ_B
15
25MHZ_C
1
SYSCLK_CLK32K_RTC
SYSCLK_CLK25M_SB
SYSCLK_CLK25M_ENET
SYSCLK_CLK25M_T29
=PPVRTC_G3_OUT
For SB RTC Power
1
C2610
1UF
10%
6.3V
2
CERM
402
GPIO Glitch Prevention
=PP3V3_S3_PCH_GPIO
7
18 24
ENET_MEDIA_SENSE ISOLATION CIRCUIT
ENET_MEDIA_SENSE
36
IN
=PP3V3_S3_PCH_GPIO
7
18 24
R2611
100K
5%
1/20W
MF
201
ENET_MEDIA_SENSE_EN_L
R2612
0
5%
1/16W
MF-LF
402
ENET_MEDIA_SENSE_EN
NO STUFF
R2663
0
21
5%
1/16W
MF-LF
402
7
24
1
C2660
0.1UF
20%
10V
2
CERM
402
R2662
3.0K
SYS_PWROK_R
R2660
0
5%
1/16W
MF-LF
402
21
5%
1/16W
MF-LF
402
21
ENET_LOW_PWR_PCH
19 23
IN
PM_PCH_PWROK
17 24
IN
FW_PWR_EN_PCH
19
IN
TBT_PWR_EN_PCH
16
IN
PM_PCH_PWROK
17 24
IN
AUD_IPHS_SWITCH_EN_PCH
19 23
IN
=PP3V3_S5_PCHPWRGD
7
24
=PP3V3_S0_SB_PM
7
24
23 45 73
IN
68
IN
=PP3V3_S3_PCH_GPIO
7
18 24
PCH S0 PWRGD
ALL_SYS_PWRGD
CPUIMVP_PGOOD
CRITICAL
1
2
5
6
CRITICAL
1
2
5
6
R2650
1/16W
MF-LF
VCC
U2601
SOT833
08
A1
B1
A2
B2
GND
VCC
U2652
SOT833
08
A1
B1
A2
B2
GND
1
1K
5%
402
2
1
8
Y1
Y2
4
74LVC2G08GT
8
Y1
Y2
4
74LVC2G08GT
35 45 46
C2650
2
7
ENET_LOW_PWR
3
FW_PWR_EN
1
C2652
2
7
TBT_PWR_EN
3
AUD_IPHS_SWITCH_EN
5
MC74VHC1G08
1
U2650
2
3
SMC_DELAYED_PWRGD
0.1UF
20%
10V
CERM
402
0.1UF
20%
10V
CERM
402
1
C2600
0.1UF
20%
10V
2
CERM
402
SC70-HF
4
PM_S0_PGOOD
30 36
OUT
39
OUT
=PP3V3R1V5_S0_PCH_VCCSUSHDA
35
OUT
62
OUT
=PP3V3_S5_PCHPWRGD
5
MC74VHC1G08
1
2
U2660
3
SC70-HF
4
6 3
Ethernet WAKE# Isolation
=PP3V3_ENET_PHY
1
Q2630
SSM3K15AMFVAPE
VESM
PCIE_WAKE_L
6
17 32 36
OUT
D
3
1
GS
2
R2630
10K
5%
1/16W
MF-LF
402
2
ENET_WAKE_L
MAKE_BASE=TRUE
7
36 71
=ENET_WAKE_L
18 26
IN
PCH Reset Button
=PP3V3_S0_SB_PM
7
24
1
R2695
10K
5%
1/16W
MF-LF
402
2
21
PM_SYSRST_L
OMIT
1
R2697
0
5%
1/16W
MF-LF
402
2
SILK_PART=SYS RESET
=PP3V3_S0_RSTBUF
7
16
OUT
=PP3V3_S3_SDBUF
1
C2670
0.1UF
20%
10V
2
CERM
402
SDCONN_STATE_CHANGE_SMC
SOT665
4
Y
CRITICAL
5
U2670
A
B
3
2
1
R2610
12K
402
CRITICAL
SSM6N37FEAPE
Q2610
SOT563
1
2
5
SSM6N37FEAPE
Q2610
1
SOT563
2
2
PM_PCH_SYS_PWROK
PLACE_NEAR=U1800.L22:5.54mm
NO STUFF
1
R2661
0
5%
1/16W
MF-LF
402
2
XDP_DBRESET_L
10 23
IN
78
OUT
OUT
OUT
OUT
7
5%
21
ENET_MEDIA_SENSE_RDIV
1/16WMF-LF
3
D
SG
4
6
D
SG
1
PM_PCH_PWROK
MAKE_BASE=TRUE
PM_PCH_APWROK
23
XDP
R2696
0
5%
1/16W
MF-LF
16 81
16 81
36 81
33 81
402
SDCONN_STATE_CHANGE ISOLATION
SDCONN_STATE_CHANGE
TC7SZ08FEAPE
17 23 45
OUT
17 24
OUT
17
OUT
Platform Reset Connections
PLT_RESET_L
MAKE_BASE=TRUE
IN
17 45
BI
2
1
C2680
0.1UF
20%
10V
2
CERM
402
18 81
IN
18
IN
18
IN
PCH uses HDA_SDO as a power-up strap. If low, ME functions normally.
7
If high, ME is disabled. This allows for full re-flashing of SPI ROM.
SMC controls strap enable to allow in-field control of strap setting.
Q2620 & 5V pull-up allows circuit to work regardless of HDA voltage.
30 46
=PP3V3R1V5_S0_PCH_VCCSUSHDA
7
20 22 24
SPI_DESCRIPTOR_OVERRIDE_L
45
IN
Unbuffered
R2681
33
21
5%
1/16W
MF-LF
402
R2671
0
21
5%
1/16W
MF-LF
402
Buffered
5
U2680
74LVC1G07
SC70
NC
3
1
NC
LPC_CLK33M_SMC_R
LPC_CLK33M_LPCPLUS_R
PCH_CLK33M_PCIOUT
PLT_RST_BUF_L
MAKE_BASE=TRUE
1
R2680
100K
5%
1/16W
MF-LF
402
2
PLACE_NEAR=U1800.H49:5.1mm
PLACE_NEAR=U1800.H43:5.1mm
PLACE_NEAR=U1800.H40:2.54MM:5.1mm
R2627
22
5%
1/16W
MF-LF
402
R2629
22
5%
1/16W
MF-LF
402
21
R2626
21
PCH ME Disable Strap
Q2620
SSM6N37FEAPE
SOT563
D
3
Q2620
SSM6N37FEAPE
SOT563
5
SPI_DESCRIPTOR_OVERRIDE_LS5V
S G
SPI_DESCRIPTOR_OVERRIDE
4
6
D
2
SG
1
SYNC_MASTER=K90I_MLB SYNC_DATE=02/15/2011
PAGE TITLE
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
LPC_RESET_L
LPCPLUS_RESET_L
MAKE_BASE=TRUE
R2683
33
21
SMC_LRESET_L
5%
1/16W
MF-LF
402
=ENET_RESET_L
R2688
0
21
AP_RESET_L
5%
1/16W
MF-LF
402
XDP
R2689
1/16W
MF-LF
R2693
1/16W
MF-LF
PCA9557D_RESET_L
1K
21
XDPPCH_PLTRST_L
5%
402
=T29_RESET_L
Series R is R3803
0
21
BKLT_PLT_RST_L
5%
402
=FW_RESET_L
Series R is R4283
CPU_RESET_L
VTT voltage divider on CPU page
LPC_CLK33M_SMC
22
21
LPC_CLK33M_LPCPLUS
5%
1/16W
MF-LF
402
PCH_CLK33M_PCIIN
=PP5V_S0_PCH
7
22
Chipset Support
Apple Inc.
R
1
R2620
100K
5%
1/20W
MF
201
2
1
R2621
1K
5%
1/20W
MF
201
2
HDA_SDOUT_R
IPD = 9-50k
DRAWING NUMBER
051-9058
REVISION
BRANCH
PAGE
SHEET
124578
81
OUT
6
47
OUT
45
OUT
30
OUT
32
OUT
31
OUT
23
OUT
35
OUT
77
OUT
39
OUT
10 23
OUT
45 81
OUT
6
47 81
OUT
16 80
OUT
16 81
OUT
6.0.0
26 OF 109
24 OF 86
SIZE
D
C
B
A
D
8 7 6 5 4 3
12
BOM GROUP
HUB_ALLREM
HUB_1NONREM
USB MUX FOR LS/FS INTERNAL DEVICES
R2701
1
R2706
10K
5%
1/16W
MF-LF
402
2
1
2
C2706
X7R-CERM
100
5%
1/16W
MF-LF
402
C2702
0.1UF
10%
16V
X7R-CERM
0402
0.1UF
BYPASS=U2700.5::2MM
1
2
BYPASS=U2700.23::2MM
1
2
USB_HUB_TEST
USB_HUB_RESET_L
25
USB_HUB_XTAL1
USB_HUB_XTAL2_R
C2708
10%
16V
0402
21
USB_HUB_NONREM0
USB_HUB_NONREM1
USB_HUB_CFG_SEL0
USB_HUB_CFG_SEL1
1
R2707
10K
5%
1/16W
MF-LF
402
2
C2703
0.1UF
10%
16V
X7R-CERM
0402
0.1UF
X7R-CERM
1
10%
16V
2
0402
5
VDD33
SYM VER 1
U2700
USB2513B
11
TEST
26
RESET*
33
XTALIN/CLKIN
32
XTALOUT
28
SUSP_IND/LOCAL_PWR/NON_REM0
22
SDA/SMBDATA/NON_REM1
24
SCL/SMBCLK/CFG_SEL0
25
HS_IND/CFG_SEL1
QFN
OMIT
THRM_PAD
PPUSB_HUB2_VDD1V8
MIN_LINE_WIDTH=0.4MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=1.8V
PPUSB_HUB2_VDD1V8PLL
MIN_LINE_WIDTH=0.4MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=1.8V
3629231510
34
14
CRFILT
PLLFILT
USBDM_DN1/PRT_DIS_M1
USBDP_DN1/PRT_DIS_P1
USBDM_DN2/PRT_DIS_M2
USBDP_DN2/PRT_DIS_P2
USBDM_DN3/PRT_DIS_M3
USBDP_DN3/PRT_DIS_P3
PRTPWR1/BC_EN1*
PRTPWR2/BC_EN2*
PRTPWR3/BC_EN3*
37
IPU
IPU
IPU
IPU
OCS1*
OCS2*
OSC3*
RBIAS
VBUS_DET
USBDM_UP
USBDP_UP
1
C2711
0.1UF
10%
16V
2
X7R-CERM
0402
1
USBHUB_DN1_N
2
USBHUB_DN1_P
3
USBHUB_DN2_N
4
USBHUB_DN2_P
6
USBHUB_DN3_N
7
USBHUB_DN3_P
8
USBHUB_DN4_N
NC
9
USBHUB_DN4_P
NC
12
TP_USB_HUB_PRTPWR1
16
NC_USB_HUB_PRTPWR2
18
NC_USB_HUB_PRTPWR3
20
NC_USB_HUB_PRTPWR4
NC
13
TP_USB_HUB_OCS1
17
NC_USB_HUB_OCS2
19
NC_USB_HUB_OCS3
21
NC_USB_HUB_OCS4
NC
35
USB_HUB_RBIAS
27
USB_HUB_VBUS_DET
30
USB_HUB_UP_N
31
USB_HUB_UP_P
PCH PORT 7 (EHCI1)
1
C2712
2
1UF
10%
16V
X5R
402
8
BI
8
BI
8
BI
8
BI
8
BI
8
BI
25
BI
25
BI
18 80
BI
18 80
BI
=PP3V3_S3_USB_HUB
7
D
C
25
1/16W
MF-LF
1/16W
MF-LF
10K
10K
HUB_NONREM0_1
1
1
R2703
10K
5%
5%
1/16W
MF-LF
402
402
2
2
HUB_NONREM0_0
1
1
R2705
10K
5%
5%
1/16W
MF-LF
402
402
2
2
HUB_NONREM1_1
R2702
HUB_NONREM1_0
R2704
J5 USES 197S0181 FOR Y2700 DUE TO HEIGHT LIMITATION
J3X USE 197S0284 FOR Y2700 TO SAVE COST
BYPASS=U27000.5::5MM
BYPASS=U2700.23::5MM
USB_HUB_XTAL2
CRITICAL
1
C2709
18PF
5%
50V
2
C0G-CERM
0402
=PP3V3_S3_USB_RESET
7
1
C2700
4.7UF
20%
6.3V
2
X5R
603
BYPASS=U2700.15::2MM
1
C2704
4.7UF
20%
6.3V
2
X5R
603
Y2700
24.000M-60PPM-16PF
1
R2710
0
5%
1/16W
MF-LF
402
2
5X3.2X1.4-SM
CRITICAL
R2700
1M
5%
1/16W
MF-LF
402
21
21
1
C2701
0.1UF
10%
16V
2
X7R-CERM
0402
BYPASS=U2700.10::2MM
1
C2705
0.1UF
10%
16V
2
X7R-CERM
0402
BYPASS=U2700.36::2MM
BYPASS=U2650.29::2MM
CRITICAL
1
C2710
18PF
5%
50V
2
C0G-CERM
0402
HUB_2NONREM
HUB_3NONREM
NON_REM 1 : NON_REM 0 STRAP PIN CFG
0 : 0 ALL PORTS ARE REMOVABLE
0 : 1 PORT 1 IS NON REMOVABLE
1 : 0 PORT 1&2 ARE NON REMOVABLE
CANNOT INDICATE ALL 4 PORTS ARE NON REMOVABLE ON USB2514B VIA STARPPING, PROGRAM NON_REMOVABLE DEVICE REGISTER 09H
1
2
C2713
0.1UF
10%
16V
X7R-CERM
0402
1
2
C2714
1UF
10%
16V
X5R
402
BLUETOOTH FOR J5 & J3X
TP/KB FOR J5, IR FOR J3X
25
SMC DEBUG PORT FOR J5, TP/KB FOR J3X
25
NC FOR J5, SMC DEBUG PORT FOR J3X
=PP3V3_S3_USB_HUB
1
R2708
10K
5%
1/16W
MF-LF
402
2
CRITICAL
1
R2709
12K
1%
1/16W
MF
402
2
1 : 1 PORT 1&2&3 ARE NON REMOVABLE
PART#
338S0824
338S0923
338S0983
J5 ENGINEERING: USE USB2513B PRODUCTION: USE USB2512B
J3X ENGINEERING: USE USB2514B PRODUCTION: USE USB2513B
USBHUB_DN3_N
8
25
USBHUB_DN3_P
8
25
USBHUB_DN4_N
25
USBHUB_DN4_P
25
7
25
HUB_NONREM1_0,HUB_NONREM0_0
HUB_NONREM1_0,HUB_NONREM0_1
HUB_NONREM1_1,HUB_NONREM0_0
HUB_NONREM1_1,HUB_NONREM0_1
DESCRIPTION
QTY
USB HUB 2514B
1
1
USB HUB 2513B
1
USB HUB 2512B
BOM OPTIONS
BOM TABLE
NOSTUFF
R2716
10K
5%
1/16W
MF-LF
402
NOSTUFF
1
R2717
10K
5%
1/16W
MF-LF
402
2
1
2
REFERENCE DESIGNATOR(S)
U2700
U2700
U2700
=PP3V3_S3_USB_HUB
NOSTUFF
R2718
10K
5%
1/16W
MF-LF
402
NOSTUFF
1
R2719
10K
5%
1/16W
MF-LF
402
2
1
2
CRITICAL BOM OPTION
CRITICAL
CRITICAL
CRITICAL
USBHUB2514B
USBHUB2513B
USBHUB2512B
7
25
TABLE_BOMGROUP_HEAD
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
D
TABLE_5_HEAD
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
C
SIZE
B
A
D
B
PLACE_NEAR=U2700.26:2.5MM
A
C2715
0.1UF
X7R-CERM
10%
16V
0402
1
R2712
10K
5%
1/16W
MF-LF
402
2
USB_HUB_RESET_L
1
2
25
PCH PORT 9 (EHCI2)
PCH PORT 1 (XHCI)
USB XHCI/EHCI2 PORT MUX FOR EXT B
=PP3V3_S3_USBMUX
7
1
18
80
18 80
18
80
18 80
BI
BI
BI
BI
USB_EXTB_EHCI_P
USB_EXTB_EHCI_N
USB_EXTB_XHCI_P
USB_EXTB_XHCI_N
C2760
0.1UF
CERM
20%
10V
2
402
5
4
7
6
8
M+
M-
U2760
PI3USB102ZLE
D+
D-
9
VCC
TQFN
CRITICAL
GND
3
1
Y+
2
Y-
PULL-UP TO 3.3V SUS ON PCH PAGE, SEL PIN IS LEAKAGE-SAFE
10
SELOE*
USB_EXTB_MUX_P
USB_EXTB_MUX_N
USB_EXTB_SEL_XHCI
SEL=0 CHOOSE USB EHCI2 PORT
SEL=1 CHOOSE USB XHCI PORT
43 80
BI
43 80
BI
16
IN
TO CONNECTOR
PCH GPIO60
6 3
SYNC_MASTER=LINDA_J30
PAGE TITLE
USB HUB & MUX
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
SYNC_DATE=09/19/2011
DRAWING NUMBER
051-9058
REVISION
6.0.0
BRANCH
PAGE
27 OF 109
SHEET
25 OF 86
124578
8 7 6 5 4 3
The circuit below handles CPU and VTT power during S0->S3->S0 transitions, as well
as isolating the CPU’s SM_DRAMRST# output from the SO-DIMMs when necessary.
ISOLATE_CPU_MEM_L GPIO state during S3<->S0 transitions determines behavior of signals.
D
WHEN HIGH: CPU 1.5V remains powered in S3, VTT follows S0 rails, MEM_RESET_L not isolated.
WHEN LOW: CPU 1.5V follows S0 rails, VTT ensures clean CKE transition, MEM_RESET_L isolated.
P1V5CPU_EN = (ISOLATE_CPU_MEM_L + PM_SLP_S3_L) * PM_SLP_S4_L
MEMVTT_EN = (ISOLATE_CPU_MEM_L + PLT_RST_L) * PM_SLP_S3_L
MEM_RESET_L = !ISOLATE_CPU_MEM_L + CPU_MEM_RESET_L
PM_SLP_S4_L
6
17 32 45 73
IN
=PP3V3_S3_MEMRESET
7
C
ISOLATE_CPU_MEM_L
23
IN IN
=PP5V_S3_MEMRESET
7
26
CPUMEM_S0
1
R2815
100K
5%
1/16W
MF-LF
402
2
CPUMEM_S0
Q2815
SSM6N37FEAPE
SOT563
B
NOSTUFF
1
C2817
0.047UF
10%
6.3V
2
X5R
201
=MEM_RESET_L
10
IN
6
MEMRESET_ISOL_LS5V_L
31
2
D
S G
CPU_MEM_RESET_L
MAKE_BASE=TRUE
1
CPUMEM_S0
CPUMEM_S0
Q2800
SSM6N37FEAPE
SOT563
CPUMEM_S0
CPUMEM_S0
Q2800
SSM6N37FEAPE
SOT563
CPUMEM_S0
SSM6N37FEAPE
5
S G
4
R2801
100K
1/16W
MF-LF
5
R2802
100K
1/16W
MF-LF
2
Q2815
5%
402
D
SG
5%
402
D
SG
SOT563
1
2
P1V5CPU_EN_L
3
4
1
2
MEMVTT_EN_L
6
1
D
3
SSM6N37FEAPE
SSM6N37FEAPE
CPUMEM_S0
1
R2816
1K
5%
1/16W
MF-LF
402
2
CPUMEM_S0
Q2805
SOT563
CPUMEM_S0
Q2810
SOT563
2
3
4
2
3
4
D
S G
D
S G
1
C2816
2
CPUMEM_S3
R2817
0
21
5%
1/16W
MF-LF
402
Step ISOLATE_CPU_MEM_L PLT_RESET_L PM_SLP_S3_L PM_SLP_S4_L CPU_MEM_RESET_L MEM_RESET_L MEMVTT_EN P1V5CPU_EN
S0
0 1 1 1 1 1 CPU_MEM_RESET_L 1 1
1 0 1 1 1 1 1 1 1
to
2 0 0 1 1 1 1 0 1
A
3 0 0 0 1 X 1 0 0
S3
4 0 0 1 1 X 1 0 1
5 0 1 1 1 0 (*) 1 1 1
to
6 0 1 1 1 1 1 1 1
7 1 1 1 1 1 CPU_MEM_RESET_L 1 1
S0
(*) CPU_MEM_RESET_L asserts due to loss of PM_MEM_PWRGD, must wait for software to clear before deasserting ISOLATE_CPU_MEM_L GPIO.
NOTE: In the event of a S3->S5 transition ISOLATE_CPU_MEM_L will still be asserted on next S5->S0
transition. Rails will power-up as if from S3, but MEM_RESET_L will not properly assert. Software
must deassert ISOLATE_CPU_MEM_L and then generate a valid reset cycle on CPU_MEM_RESET_L.
6 3
CPUMEM_S0
1
R2805
10K
5%
1/16W
MF-LF
402
2
P1V5CPU_EN
6
D
SG
1
CPUMEM_S0
Q2805
SSM6N37FEAPE
SOT563
5
PM_SLP_S3_L
CPUMEM_S0
1
R2810
10K
5%
1/16W
MF-LF
402
2
MEMVTT_EN
6
D
SG
1
CPUMEM_S0
Q2810
SSM6N37FEAPE
SOT563
5
PLT_RESET_L
=PP1V5_S3_MEMRESET
CPUMEM_S0
0.1UF
10%
16V
X7R-CERM
0402
OUT
OUT
IN
7
MEM_RESET_L
72
6 8
8
18 24
17 45 73
12
D
1V5 S0 "PGOOD" for CPU
=PP3V3_S5_CPU_VCCDDR
7
PM_MEM_PWRGD pull-up to CPU VTT rail is on CPU page
=PP1V5_S3_CPU_VCCDDR
7
10 12 15
R2820
27.4K
1/16W
MF-LF
R2821
33.2K
1/16W
MF-LF
1%
402
1%
402
1
2
P1V5_S0_DIV
1
2
NO STUFF
C2820
0.001UF
1
R2822
10K
5%
1/16W
MF-LF
402
2
PM_MEM_PWRGD_L
3
CRITICAL
Q2820
5
DMB53D0UV
SOT-563
1
20%
50V
2
CERM
402
4
CRITICAL
G
2
PM_MEM_PWRGD
6
D
Q2820
DMB53D0UV
SOT-563
S
1
10 17 78
OUT
C
MEMVTT Clamp
Ensures CKE signals are held low in S3
=PPVTT_S0_VTTCLAMP
7
=PP5V_S3_MEMRESET
7
26
27 29
OUT
=DDRVTT_EN
8
67
IN
CPUMEM_S0
CPUMEM_S0
Q2850
SSM6N37FEAPE
SOT563
R2851
100K
1/16W
MF-LF
5
1
5%
402
2
3
D
SG
4
SSM6N37FEAPE
VTTCLAMP_EN
NO STUFF
CPUMEM_S0
Q2850
C2851
0.001UF
20%
50V
CERM
402
SOT563
2
1
2
6
D
SG
1
CPUMEM_S0
VTTCLAMP_L
1
R2850
10
75mA max load @ 0.75V
5%
60mW max power
1/10W
MF-LF
603
2
SYNC_MASTER=K90I_MLB SYNC_DATE=02/15/2011
PAGE TITLE
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
CPU Memory S3 Support
Apple Inc.
R
DRAWING NUMBER
REVISION
BRANCH
PAGE
SHEET
051-9058
28 OF 109
6.0.0
26 OF 86
SIZE
B
A
D
124578
8 7 6 5 4 3
12
Power aliases required by this page:
- =PP1V5_S0_MEM_A
- =PP1V5_S3_MEM_A
- =PP0V75_S0_MEM_VTT_A
- =PPSPD_S0_MEM_A (2.5 - 3.3V)
Signal aliases required by this page:
- =I2C_SODIMMA_SCL
- =I2C_SODIMMA_SDA
BOM options provided by this page:
D
(NONE)
C
B
A
Page Notes
=PPSPD_S0_MEM_A
7
1
2
C2940
2.2UF
20%
6.3V
CERM
402-LF
11 79
11 79
11 79
11 79
11 79
11 79
11 79
11 79
11 79
11 79
11 79
11 79
11 79
11 79
11 79
11 79
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
1
R2940
10K
5%
1/16W
MF-LF
402
2
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
BI
BI
BI
BI
BI
BI
BI
BI
IN
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
IN
BI
BI
MEM_A_CKE<0>
MEM_A_BA<2>
MEM_A_A<12>
MEM_A_A<9>
MEM_A_A<8>
MEM_A_A<5>
MEM_A_A<3>
MEM_A_A<1>
MEM_A_CLK_P<0>
MEM_A_CLK_N<0>
MEM_A_A<10>
MEM_A_BA<0>
MEM_A_WE_L
MEM_A_CAS_L
MEM_A_A<13>
MEM_A_CS_L<1>
=MEM_A_DQ<32>
=MEM_A_DQ<33>
=MEM_A_DQS_N<4>
=MEM_A_DQS_P<4>
=MEM_A_DQ<34>
=MEM_A_DQ<35>
=MEM_A_DQ<40>
=MEM_A_DQ<41>
=MEM_A_DM<5>
=MEM_A_DQ<42>
=MEM_A_DQ<43>
=MEM_A_DQ<48>
=MEM_A_DQ<49>
=MEM_A_DQS_N<6>
=MEM_A_DQS_P<6>
=MEM_A_DQ<50>
=MEM_A_DQ<51>
=MEM_A_DQ<56>
=MEM_A_DQ<57>
=MEM_A_DM<7>
=MEM_A_DQ<58>
=MEM_A_DQ<59>
MEM_A_SA<0>
MEM_A_SA<1>
1
R2941
10K
5%
1/16W
MF-LF
402
2
=PP1V5_S3_MEM_A
7
1
C2900
10UF
20%
6.3V
2
X5R
603
OMIT_TABLE
KEY
CKE0
VDD
77
NC
NC
NC
79
83 84
85
89
91 92
95 96
97 98
99
101
103
107
109
113
115
119
121
125
129
131
135
137
139
141
143
145
147
149
151
153
157
159
163
165
169
171
173
175
177
179
181
183
185
187
191
193
197
199
J2900
BA2
F-RT-THB
VDD
A12/BC*
A9
VDD
A8
A5
VDD
A3
A1
VDD
CK0
CK0*
VDD
A10/AP
BA0
VDD
WE*
CAS*
VDD
A13
S1*
VDD
TEST
VSS
DQ32
DQ33
VSS
DQS4*
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
DQS6*
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SA0
VDDSPD
SA1
VTT
SPD ADDR=0xA0(WR)/0xA1(RD)
DDR3-SODIMM-DUAL-K6
(SYMBOL 2 OF 2)
VREFCA
EVENT*
6 3
CKE1
VDD
A15
A14
VDD
A11
VDD
VDD
CK1
CK1*
VDD
BA1
RAS*
VDD
S0*
ODT0
VDD
ODT1
VDD
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5*
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7*
DQS7
VSS
DQ62
DQ63
VSS
SDA
SCL
VTT
VDD
A7
A6
A4
A2
A0
NC
1
C2901
10UF
20%
6.3V
2
X5R
603
DDR3 DECOUPLING AND GND RETURN CAPS (SPACE EVENLY AT CONNECTOR)
1
C2910
0.1UF
20%
10V
2
CERM
402
7473
7675
78
80
8281
86
8887
90
9493
100
102
104
106105
108
110
112111
114
116
118117
120
122
124123
126
128127
130
132
134133
136
138
140
142
144
146
148
150
152
154
156155
158
160
162161
164
166
168167
170
172
174
176
178
180
182
184
186
188
190189
192
194
196195
198
200
202201
204203
NC
MEM_A_CKE<1>
MEM_A_A<15>
MEM_A_A<14>
MEM_A_A<11>
MEM_A_A<7>
MEM_A_A<6>
MEM_A_A<4>
MEM_A_A<2>
MEM_A_A<0>
MEM_A_CLK_P<1>
MEM_A_CLK_N<1>
MEM_A_BA<1>
MEM_A_RAS_L
MEM_A_CS_L<0>
MEM_A_ODT<0>
MEM_A_ODT<1>
=MEM_A_DQ<36>
=MEM_A_DQ<37>
=MEM_A_DM<4>
=MEM_A_DQ<38>
=MEM_A_DQ<39>
=MEM_A_DQ<44>
=MEM_A_DQ<45>
=MEM_A_DQS_N<5>
=MEM_A_DQS_P<5>
=MEM_A_DQ<46>
=MEM_A_DQ<47>
=MEM_A_DQ<52>
=MEM_A_DQ<53>
=MEM_A_DM<6>
=MEM_A_DQ<54>
=MEM_A_DQ<55>
=MEM_A_DQ<60>
=MEM_A_DQ<61>
=MEM_A_DQS_N<7>
=MEM_A_DQS_P<7>
=MEM_A_DQ<62>
=MEM_A_DQ<63>
MEM_EVENT_L
=I2C_SODIMMA_SDA
=I2C_SODIMMA_SCL
1
C2911
0.1UF
20%
10V
2
CERM
402
PP0V75_S3_MEM_VREFDQ_A
31
11 79
IN
11 79
IN
11 79
IN
11 79
IN
11 79
IN
11 79
IN
11 79
IN
11 79
IN
11 79
IN
11 79
IN
11 79
IN
11 79
IN
11 79
IN
11 79
IN
11 79
IN
11 79
IN
28
BI
28
BI
28
IN
28
BI
28
BI
28
BI
28
BI
28
BI
28
BI
28
BI
28
BI
28
BI
28
BI
28
IN
28
BI
28
BI
28
BI
28
BI
28
BI
28
BI
28
BI
28
BI
29 45 46
OUT
BI
48
IN
48
1
C2950
1UF
10%
10V
2
X5R
402
1
2
C2912
0.1UF
20%
10V
CERM
402
1
C2951
1UF
10%
10V
2
X5R
402
1
2
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
1
C2935
2.2UF
20%
6.3V
2
CERM
402-LF
=PP0V75_S0_MEM_VTT_A
C2913
0.1UF
20%
10V
CERM
402
1
C2930
2.2UF
20%
6.3V
2
CERM
402-LF
BI
IN
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
IN
BI
BI
=MEM_A_DQ<0>
=MEM_A_DQ<1>
=MEM_A_DM<0>
=MEM_A_DQ<2>
=MEM_A_DQ<3>
=MEM_A_DQ<8>
=MEM_A_DQ<9>
=MEM_A_DQS_N<1>
=MEM_A_DQS_P<1>
=MEM_A_DQ<10>
=MEM_A_DQ<11>
=MEM_A_DQ<16>
=MEM_A_DQ<17>
=MEM_A_DQS_N<2>
=MEM_A_DQS_P<2>
=MEM_A_DQ<18>
=MEM_A_DQ<19>
=MEM_A_DQ<24>
=MEM_A_DQ<25>
=MEM_A_DM<3>
=MEM_A_DQ<26>
=MEM_A_DQ<27>
1
2
1
C2952
1UF
10%
10V
2
X5R
402
1
C2914
0.1UF
20%
10V
2
CERM
402
1
2
PP0V75_S3_MEM_VREFCA_A
C2936
0.1UF
20%
10V
CERM
402
C2931
0.1UF
20%
10V
CERM
402
1
2
C2953
1UF
10%
10V
X5R
402
1
C2915
2
0.1UF
20%
10V
CERM
402
7
1
2
C2916
0.1UF
20%
10V
CERM
402
1
2
C2917
0.1UF
20%
10V
CERM
402
1
C2918
0.1UF
2
1
C2919
20%
10V
CERM
402
0.1UF
20%
10V
2
CERM
402
1
C2920
2
0.1UF
20%
10V
CERM
402
1
2
C2921
0.1UF
20%
10V
CERM
402
1
C2922
2
0.1UF
20%
10V
CERM
402
1
C2923
2
0.1UF
20%
10V
CERM
402
D
OMIT_TABLE
DQS0*
DQS0
VSS
VSS
DQ12
DQ13
VSS
VSS
DQ14
DQ15
VSS
DQ20
DQ21
VSS
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3*
DQS3
VSS
DQ30
DQ31
VSS
DQ4
DQ5
DQ6
DQ7
DM1
DM2
VSS
VSS
21
4
6
8
10
12
1413
16
18
2019
22
24
2625
28
30
3231
34
36
3837
40
42
4443
46
48
50
52
54
56
58
60
62
64
6665
68
70
7271
=MEM_A_DQ<4>
=MEM_A_DQ<5>
=MEM_A_DQS_N<0>
=MEM_A_DQS_P<0>
=MEM_A_DQ<6>
=MEM_A_DQ<7>
=MEM_A_DQ<12>
=MEM_A_DQ<13>
=MEM_A_DM<1>
MEM_RESET_L
=MEM_A_DQ<14>
=MEM_A_DQ<15>
=MEM_A_DQ<20>
=MEM_A_DQ<21>
=MEM_A_DM<2>
=MEM_A_DQ<22>
=MEM_A_DQ<23>
=MEM_A_DQ<28>
=MEM_A_DQ<29>
=MEM_A_DQS_N<3>
=MEM_A_DQS_P<3>
=MEM_A_DQ<30>
=MEM_A_DQ<31>
28
BI
28
BIBI
28
BI
28
BI
28
BI
28
BI
28
BI
28
BI
28
IN
26 29
IN
28
BI
28
BI
28
BI
28
BI
28
IN
28
BI
28
BI
28
BI
28
BI
28
BI
28
BI
28
BI
28
BI
C
VREFDQ
3
VSS
5
DQ0
CRITICAL
7
DQ1
9
VSS
11
15
17
21
23
27
29
33
35
39
41
45
47
49
51
53
55
57
59
61
63
67
69
DM0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1*
DQS1
VSS
DQ10
DQ11
VSS
DQ16
DQ17
VSS
DQS2*
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
VSS
DQ26
DQ27
VSS
J2900
F-RT-THB
(SYMBOL 1 OF 2)
RESET*
DDR3-SODIMM-DUAL-K6
KEY
B
31
"Factory" (top) slot
SIZE
A
D
PAGE TITLE
DDR3 SO-DIMM Connector A
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
SYNC_DATE=02/15/2011SYNC_MASTER=K90I_MLB
DRAWING NUMBER
051-9058
REVISION
6.0.0
BRANCH
PAGE
29 OF 109
SHEET
27 OF 86
124578
8 7 6 5 4 3
12
CPU CHANNEL A DQS 0 -> DIMM A DQS 0
MEM_A_DQS_N<0>
11 79
MEM_A_DQS_P<0>
11 79
MEM_A_DQ<7>
11 79
MEM_A_DQ<6>
11 79
MEM_A_DQ<5>
11 79
MEM_A_DQ<4>
11 79
MEM_A_DQ<3>
11 79
MEM_A_DQ<2>
11 79
MEM_A_DQ<1>
11 79
MEM_A_DQ<0>
D
C
B
A
11 79
CPU CHANNEL A DQS 1 -> DIMM A DQS 1
MEM_A_DQS_N<1>
11 79
MEM_A_DQS_P<1>
11 79
MEM_A_DQ<15>
11 79
MEM_A_DQ<14>
11 79
MEM_A_DQ<13>
11 79
MEM_A_DQ<12>
11 79
MEM_A_DQ<11>
11 79
MEM_A_DQ<10>
11 79
MEM_A_DQ<9>
11 79
MEM_A_DQ<8>
11 79
CPU CHANNEL A DQS 2 -> DIMM A DQS 2
MEM_A_DQS_N<2>
11 79
MEM_A_DQS_P<2>
11 79
MEM_A_DQ<23>
11 79
MEM_A_DQ<22>
11 79
MEM_A_DQ<21>
11 79
MEM_A_DQ<20>
11 79
MEM_A_DQ<19>
11 79
MEM_A_DQ<18>
11 79
MEM_A_DQ<17>
11 79
MEM_A_DQ<16>
11 79
CPU CHANNEL A DQS 3 -> DIMM A DQS 3
MEM_A_DQS_N<3>
11 79
MEM_A_DQS_P<3>
11 79
MEM_A_DQ<31>
11 79
MEM_A_DQ<30>
11 79
MEM_A_DQ<29>
11 79
MEM_A_DQ<28>
11 79
MEM_A_DQ<27>
11 79
MEM_A_DQ<26>
11 79
MEM_A_DQ<25>
11 79
MEM_A_DQ<24>
11 79
CPU CHANNEL A DQS 4 -> DIMM A DQS 4
MEM_A_DQS_N<4>
11 79
MEM_A_DQS_P<4>
11 79
MEM_A_DQ<39>
11 79
MEM_A_DQ<38>
11 79
MEM_A_DQ<37>
11 79
MEM_A_DQ<36>
11 79
MEM_A_DQ<35>
11 79
MEM_A_DQ<34>
11 79
MEM_A_DQ<33>
11 79
MEM_A_DQ<32>
11 79
CPU CHANNEL A DQS 5 -> DIMM A DQS 5
MEM_A_DQS_N<5>
11 79
MEM_A_DQS_P<5>
11 79
MEM_A_DQ<47>
MEM_A_DQ<46>
11 79
MEM_A_DQ<45>
11 79
MEM_A_DQ<44>
11 79
MEM_A_DQ<43>
11 79
MEM_A_DQ<42>
11 79
MEM_A_DQ<41>
11 79
MEM_A_DQ<40>
11 79
CPU CHANNEL A DQS 6 -> DIMM A DQS 6
MEM_A_DQS_N<6>
11 79
MEM_A_DQS_P<6>
11 79
MEM_A_DQ<55>
11 79
MEM_A_DQ<54>
11 79
MEM_A_DQ<53>
11 79
MEM_A_DQ<52>
11 79
MEM_A_DQ<51>
11 79
MEM_A_DQ<50>
11 79
MEM_A_DQ<49>
11 79
MEM_A_DQ<48>
11 79
MEM_A_DQS_N<7>
11 79
MEM_A_DQS_P<7>
11 79
MEM_A_DQ<63>
11 79
MEM_A_DQ<62>
11 79
MEM_A_DQ<61>
11 79
MEM_A_DQ<60>
11 79
MEM_A_DQ<59>
11 79
MEM_A_DQ<58>
11 79
MEM_A_DQ<57>
11 79
MEM_A_DQ<56>
11 79
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
=MEM_A_DQS_N<0>
=MEM_A_DQS_P<0>
=MEM_A_DM<0>
=MEM_A_DQ<3>
=MEM_A_DQ<6>
=MEM_A_DQ<1>
=MEM_A_DQ<5>
=MEM_A_DQ<2>
=MEM_A_DQ<7>
=MEM_A_DQ<0>
=MEM_A_DQ<4>
=MEM_A_DQS_N<1>
=MEM_A_DQS_P<1>
=MEM_A_DM<1>
=MEM_A_DQ<11>
=MEM_A_DQ<10>
=MEM_A_DQ<12>
=MEM_A_DQ<9>
=MEM_A_DQ<15>
=MEM_A_DQ<14>
=MEM_A_DQ<13>
=MEM_A_DQ<8>
=MEM_A_DQS_N<2>
=MEM_A_DQS_P<2>
=MEM_A_DM<2>
=MEM_A_DQ<23>
=MEM_A_DQ<22>
=MEM_A_DQ<21>
=MEM_A_DQ<20>
=MEM_A_DQ<18>
=MEM_A_DQ<19>
=MEM_A_DQ<16>
=MEM_A_DQ<17>
=MEM_A_DQS_N<3>
=MEM_A_DQS_P<3>
=MEM_A_DM<3>
=MEM_A_DQ<26>
=MEM_A_DQ<24>
=MEM_A_DQ<28>
=MEM_A_DQ<25>
=MEM_A_DQ<31>
=MEM_A_DQ<27>
=MEM_A_DQ<30>
=MEM_A_DQ<29>
=MEM_A_DQS_N<4>
=MEM_A_DQS_P<4>
=MEM_A_DM<4>
=MEM_A_DQ<38>
=MEM_A_DQ<39>
=MEM_A_DQ<37>
=MEM_A_DQ<33>
=MEM_A_DQ<34>
=MEM_A_DQ<35>
=MEM_A_DQ<32>
=MEM_A_DQ<36>
=MEM_A_DQS_N<5>
=MEM_A_DQS_P<5>
=MEM_A_DM<5>
=MEM_A_DQ<46>
=MEM_A_DQ<43>
=MEM_A_DQ<45>
=MEM_A_DQ<41>
=MEM_A_DQ<47>
=MEM_A_DQ<42>
=MEM_A_DQ<40>
=MEM_A_DQ<44>
=MEM_A_DQS_N<6>
=MEM_A_DQS_P<6>
=MEM_A_DM<6>
=MEM_A_DQ<51>
=MEM_A_DQ<54>
=MEM_A_DQ<49>
=MEM_A_DQ<53>
=MEM_A_DQ<50>
=MEM_A_DQ<55>
=MEM_A_DQ<48>
=MEM_A_DQ<52>
=MEM_A_DQS_N<7>
=MEM_A_DQS_P<7>
=MEM_A_DM<7>
=MEM_A_DQ<58>
=MEM_A_DQ<59>
=MEM_A_DQ<60>
=MEM_A_DQ<57>
=MEM_A_DQ<63>
=MEM_A_DQ<62>
=MEM_A_DQ<61>
=MEM_A_DQ<56>
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
NOTE: Ivybridge does not use DM signals per doc 460452 CR SFF DG Section 2.6.14
CPU CHANNEL B DQS 0 -> DIMM B DQS 0
MEM_B_DQS_N<0>
11 79
MEM_B_DQS_P<0>
11 79
MEM_B_DQ<7>
11 79
MEM_B_DQ<6>
11 79
MEM_B_DQ<5>
11 79
MEM_B_DQ<4>
11 79
MEM_B_DQ<3>
11 79
MEM_B_DQ<2>
11 79
MEM_B_DQ<1>
11 79
MEM_B_DQ<0>
11 79
CPU CHANNEL B DQS 1 -> DIMM B DQS 1
MEM_B_DQS_N<1>
11 79
MEM_B_DQS_P<1>
11 79
MEM_B_DQ<15>
11 79
MEM_B_DQ<14>
11 79
MEM_B_DQ<13>
11 79
MEM_B_DQ<12>
11 79
MEM_B_DQ<11>
11 79
MEM_B_DQ<10>
11 79
MEM_B_DQ<9>
11 79
MEM_B_DQ<8>
11 79
CPU CHANNEL B DQS 2 -> DIMM B DQS 2
MEM_B_DQS_N<2>
11 79
MEM_B_DQS_P<2>
11 79
MEM_B_DQ<23>
11 79
MEM_B_DQ<22>
11 79
MEM_B_DQ<21>
11 79
MEM_B_DQ<20>
11 79
MEM_B_DQ<19>
11 79
MEM_B_DQ<18>
11 79
MEM_B_DQ<17>
11 79
MEM_B_DQ<16>
11 79
CPU CHANNEL B DQS 3 -> DIMM B DQS 3
MEM_B_DQS_N<3>
11 79
MEM_B_DQS_P<3>
11 79
MEM_B_DQ<31>
11 79
MEM_B_DQ<30>
11 79
MEM_B_DQ<29>
11 79
MEM_B_DQ<28>
11 79
MEM_B_DQ<27>
11 79
MEM_B_DQ<26>
11 79
MEM_B_DQ<25>
11 79
MEM_B_DQ<24>
11 79
CPU CHANNEL B DQS 4 -> DIMM B DQS 4
MEM_B_DQS_N<4>
11 79
MEM_B_DQS_P<4>
11 79
MEM_B_DQ<39>
11 79
MEM_B_DQ<38>
11 79
MEM_B_DQ<37>
11 79
MEM_B_DQ<36>
11 79
MEM_B_DQ<35>
11 79
MEM_B_DQ<34>
11 79
MEM_B_DQ<33>
11 79
MEM_B_DQ<32>
11 79
CPU CHANNEL B DQS 5 -> DIMM B DQS 5
MEM_B_DQS_N<5>
11 79
MEM_B_DQS_P<5>
11 79
MEM_B_DQ<47>
11 79 11 79
MEM_B_DQ<46>
11 79
MEM_B_DQ<45>
11 79
MEM_B_DQ<44>
11 79
MEM_B_DQ<43>
11 79
MEM_B_DQ<42>
11 79
MEM_B_DQ<41>
11 79
MEM_B_DQ<40>
11 79
CPU CHANNEL B DQS 6 -> DIMM B DQS 6
MEM_B_DQS_N<6>
11 79
MEM_B_DQS_P<6>
11 79
MEM_B_DQ<55>
11 79
MEM_B_DQ<54>
11 79
MEM_B_DQ<53>
11 79
MEM_B_DQ<52>
11 79
MEM_B_DQ<51>
11 79
MEM_B_DQ<50>
11 79
MEM_B_DQ<49>
11 79
MEM_B_DQ<48>
11 79
CPU CHANNEL B DQS 7 -> DIMM B DQS 7CPU CHANNEL A DQS 7 -> DIMM A DQS 7
MEM_B_DQS_N<7>
11 79
MEM_B_DQS_P<7>
11 79
MEM_B_DQ<63>
11 79
MEM_B_DQ<62>
11 79
MEM_B_DQ<61>
11 79
MEM_B_DQ<60>
11 79
MEM_B_DQ<59>
11 79
MEM_B_DQ<58>
11 79
MEM_B_DQ<57>
11 79
MEM_B_DQ<56>
11 79
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUEMAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
6 3
=MEM_B_DQS_N<0>
=MEM_B_DQS_P<0>
=MEM_B_DM<0>
=MEM_B_DQ<3>
=MEM_B_DQ<2>
=MEM_B_DQ<0>
=MEM_B_DQ<4>
=MEM_B_DQ<7>
=MEM_B_DQ<6>
=MEM_B_DQ<5>
=MEM_B_DQ<1>
=MEM_B_DQS_N<1>
=MEM_B_DQS_P<1>
=MEM_B_DM<1>
=MEM_B_DQ<15>
=MEM_B_DQ<14>
=MEM_B_DQ<13>
=MEM_B_DQ<8>
=MEM_B_DQ<11>
=MEM_B_DQ<10>
=MEM_B_DQ<12>
=MEM_B_DQ<9>
=MEM_B_DQS_N<2>
=MEM_B_DQS_P<2>
=MEM_B_DM<2>
=MEM_B_DQ<23>
=MEM_B_DQ<18>
=MEM_B_DQ<16>
=MEM_B_DQ<17>
=MEM_B_DQ<22>
=MEM_B_DQ<19>
=MEM_B_DQ<21>
=MEM_B_DQ<20>
=MEM_B_DQS_N<3>
=MEM_B_DQS_P<3>
=MEM_B_DM<3>
=MEM_B_DQ<26>
=MEM_B_DQ<30>
=MEM_B_DQ<28>
=MEM_B_DQ<29>
=MEM_B_DQ<27>
=MEM_B_DQ<31>
=MEM_B_DQ<25>
=MEM_B_DQ<24>
=MEM_B_DQS_N<4>
=MEM_B_DQS_P<4>
=MEM_B_DM<4>
=MEM_B_DQ<38>
=MEM_B_DQ<39>
=MEM_B_DQ<33>
=MEM_B_DQ<37>
=MEM_B_DQ<34>
=MEM_B_DQ<35>
=MEM_B_DQ<32>
=MEM_B_DQ<36>
=MEM_B_DQS_N<5>
=MEM_B_DQS_P<5>
=MEM_B_DM<5>
=MEM_B_DQ<43>
=MEM_B_DQ<46>
=MEM_B_DQ<40>
=MEM_B_DQ<45>
=MEM_B_DQ<47>
=MEM_B_DQ<42>
=MEM_B_DQ<41>
=MEM_B_DQ<44>
=MEM_B_DQS_N<6>
=MEM_B_DQS_P<6>
=MEM_B_DM<6>
=MEM_B_DQ<54>
=MEM_B_DQ<55>
=MEM_B_DQ<53>
=MEM_B_DQ<49>
=MEM_B_DQ<51>
=MEM_B_DQ<50>
=MEM_B_DQ<48>
=MEM_B_DQ<52>
=MEM_B_DQS_N<7>
=MEM_B_DQS_P<7>
=MEM_B_DM<7>
=MEM_B_DQ<56>
=MEM_B_DQ<59>
=MEM_B_DQ<61>
=MEM_B_DQ<60>
=MEM_B_DQ<63>
=MEM_B_DQ<58>
=MEM_B_DQ<57>
=MEM_B_DQ<62>
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
SYNC_MASTER=K90I_MLB SYNC_DATE=02/15/2011
PAGE TITLE
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
DDR3 Byte/Bit Swaps
Apple Inc.
R
DRAWING NUMBER
051-9058
REVISION
6.0.0
BRANCH
PAGE
30 OF 109
SHEET
28 OF 86
SIZE
D
C
B
A
D
124578
8 7 6 5 4 3
12
D
C
B
A
Page Notes
Power aliases required by this page:
- =PP1V5_S0_MEM_B
- =PP1V5_S3_MEM_B
- =PP0V75_S0_MEM_VTT_B
- =PPSPD_S0_MEM_B (2.5 - 3.3V)
Signal aliases required by this page:
- =I2C_SODIMMB_SCL
- =I2C_SODIMMB_SDA
BOM options provided by this page:
(NONE)
=PPSPD_S0_MEM_B
7
1
2
C3140
2.2UF
20%
6.3V
CERM
402-LF
1
2
R3140
10K
5%
1/16W
MF-LF
402
=PP1V5_S3_MEM_B
7
1
C3100
10UF
20%
6.3V
2
X5R
603
1
2
C3101
10UF
20%
6.3V
X5R
603
OMIT_TABLE
MEM_B_CKE<0>
11 79
IN
77
NC
MEM_B_BA<2>
11 79
IN
MEM_B_A<12>
11 79
IN
MEM_B_A<9>
11 79
IN
MEM_B_A<8>
11 79
IN
MEM_B_A<5>
11 79
IN
MEM_B_A<3>
11 79
IN
MEM_B_A<1>
11 79
IN
MEM_B_CLK_P<0>
11 79
IN
MEM_B_CLK_N<0>
11 79
IN
MEM_B_A<10>
11 79
IN
MEM_B_BA<0>
11 79
IN
MEM_B_WE_L
11 79
IN
MEM_B_CAS_L
11 79
IN
MEM_B_A<13>
11 79
IN
MEM_B_CS_L<1>
11 79
IN
=MEM_B_DQ<32>
28
BI
=MEM_B_DQ<33>
28
BI
=MEM_B_DQS_N<4>
28
BI
=MEM_B_DQS_P<4>
28
BI
=MEM_B_DQ<34>
28
BI
=MEM_B_DQ<35>
28
BI
=MEM_B_DQ<40>
28
BI
=MEM_B_DQ<41>
28
BI
=MEM_B_DM<5>
28
IN
=MEM_B_DQ<42>
28
BI
=MEM_B_DQ<43>
28
BI
=MEM_B_DQ<48>
28
BI
=MEM_B_DQ<49>
28
BI
=MEM_B_DQS_N<6>
28
BI
=MEM_B_DQS_P<6>
28
BI
=MEM_B_DQ<50>
28
BI
=MEM_B_DQ<51>
28
BI
=MEM_B_DQ<56>
28
BI
=MEM_B_DQ<57>
28
BI
=MEM_B_DM<7>
28
IN
=MEM_B_DQ<58>
28
BI
=MEM_B_DQ<59>
28
BI
MEM_B_SA<0>
MEM_B_SA<1>
1
R3141
10K
5%
1/16W
MF-LF
402
2
79
83 84
85
89
91 92
95 96
97 98
99
101
103
107
109
113
115
119
121
125
NC
129
131
135
137
139
141
143
145
147
149
151
153
157
159
163
165
169
171
173
175
177
179
181
183
185
187
191
193
197
199
SPD ADDR=0xA4(WR)/0xA5(RD)
KEY
CKE0
VDD
NC
BA2
J3100
VDD
F-RT-BGA6
A12/BC*
A9
VDD
A8
A5
VDD
A3
A1
VDD
CK0
CK0*
VDD
A10/AP
BA0
VDD
WE*
CAS*
VDD
A13
S1*
VDD
TEST
VSS
DQ32
DQ33
VSS
DQS4*
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
DQS6*
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SA0
VDDSPD
SA1
VTT
MTG PIN
MTG PIN
MTG PIN MTG PIN
MTG PIN
DDR3-SODIMM
MTG PINS
(2 OF 2)
VREFCA
EVENT*
MTG PIN
MTG PIN
MTG PIN
CKE1
VDD
A15
A14
VDD
A11
VDD
VDD
CK1
CK1*
VDD
BA1
RAS*
VDD
S0*
ODT0
VDD
ODT1
VDD
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5*
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7*
DQS7
VSS
DQ62
DQ63
VSS
SDA
SCL
VTT
VDD
7473
7675
78
80
8281
86
A7
8887
90
A6
A4
9493
A2
A0
100
102
104
106105
108
110
112111
114
116
118117
120
122
NC
NC
124123
126
128127
130
132
134133
136
138
140
142
144
146
148
150
152
154
156155
158
160
162161
164
166
168167
170
172
174
176
178
180
182
184
186
188
190189
192
194
196195
198
200
202201
204203
206205
208207
210209
212211
6 3
DDR3 DECOUPLING AND GND RETURN CAPS (SPACE EVENLY AT CONNECTOR)
MEM_B_CKE<1>
MEM_B_A<15>
MEM_B_A<14>
MEM_B_A<11>
MEM_B_A<7>
MEM_B_A<6>
MEM_B_A<4>
MEM_B_A<2>
MEM_B_A<0>
MEM_B_CLK_P<1>
MEM_B_CLK_N<1>
MEM_B_BA<1>
MEM_B_RAS_L
MEM_B_CS_L<0>
MEM_B_ODT<0>
MEM_B_ODT<1>
=MEM_B_DQ<36>
=MEM_B_DQ<37>
=MEM_B_DM<4>
=MEM_B_DQ<38>
=MEM_B_DQ<39>
=MEM_B_DQ<44>
=MEM_B_DQ<45>
=MEM_B_DQS_N<5>
=MEM_B_DQS_P<5>
=MEM_B_DQ<46>
=MEM_B_DQ<47>
=MEM_B_DQ<52>
=MEM_B_DQ<53>
=MEM_B_DM<6>
=MEM_B_DQ<54>
=MEM_B_DQ<55>
=MEM_B_DQ<60>
=MEM_B_DQ<61>
=MEM_B_DQS_N<7>
=MEM_B_DQS_P<7>
=MEM_B_DQ<62>
=MEM_B_DQ<63>
MEM_EVENT_L
=I2C_SODIMMB_SDA
=I2C_SODIMMB_SCL
1
2
C3110
0.1UF
20%
10V
CERM
402
1
C3111
0.1UF
20%
10V
2
CERM
402
PP0V75_S3_MEM_VREFDQ_B
31
11 79
IN
11 79
IN
11 79
IN
11 79
IN
11 79
IN
11 79
IN
11 79
IN
11 79
IN
11 79
IN
11 79
IN
11 79
IN
11 79
IN
11 79
IN
11 79
IN
11 79
IN
11 79
IN
28
BI
28
BI
28
IN
28
BI
28
BI
28
BI
28
BI
28
BI
28
BI
28
BI
28
BI
28
BI
28
BI
28
IN
28
BI
28
BI
28
BI
28
BI
28
BI
28
BI
28
BI
28
BI
27 45 46
OUT
BI
48
IN
1
C3112
0.1UF
20%
10V
2
CERM
402
48
1
C3150
1UF
10%
10V
2
X5R
402
1
2
1
C3151
1UF
2
C3135
10%
10V
X5R
402
2.2UF
20%
6.3V
CERM
402-LF
1
C3113
0.1UF
20%
10V
2
CERM
402
1
C3130
2.2UF
20%
6.3V
2
CERM
402-LF
=MEM_B_DQ<0>
28
BI
=MEM_B_DQ<1>
28
BI
=MEM_B_DM<0>
28
IN
=MEM_B_DQ<2>
28
BI
=MEM_B_DQ<3>
28
BI
=MEM_B_DQ<8>
28
BI
=MEM_B_DQ<9>
28
BI
=MEM_B_DQS_N<1>
28
BI
=MEM_B_DQS_P<1>
28
BI
=MEM_B_DQ<10>
28
BI
=MEM_B_DQ<11>
28
BI
=MEM_B_DQ<16>
28
BI
=MEM_B_DQ<17>
28
BI
=MEM_B_DQS_N<2>
28
BI
=MEM_B_DQS_P<2>
28
BI
=MEM_B_DQ<18>
28
BI
=MEM_B_DQ<19>
28
BI
=MEM_B_DQ<24>
28
BI
=MEM_B_DQ<25>
28
BI
=MEM_B_DM<3>
28
IN
=MEM_B_DQ<26>
28
BI
=MEM_B_DQ<27>
28
BI
1
2
=PP0V75_S0_MEM_VTT_B
1
2
C3136
0.1UF
20%
10V
CERM
402
C3152
1UF
10%
10V
X5R
402
1
2
C3114
0.1UF
20%
10V
CERM
402
1
C3131
0.1UF
20%
10V
2
CERM
402
PP0V75_S3_MEM_VREFCA_B
1
C3153
1UF
10%
10V
2
X5R
402
1
C3115
0.1UF
20%
10V
2
CERM
402
1
C3116
2
0.1UF
20%
10V
CERM
402
1
C3117
0.1UF
20%
2
CERM
402
1
C3118
0.1UF
10V
20%
10V
2
CERM
402
OMIT_TABLE
DQS0*
DQS0
VSS
VSS
DQ12
DQ13
VSS
VSS
DQ14
DQ15
VSS
DQ20
DQ21
VSS
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3*
DQS3
VSS
DQ30
DQ31
VSS
DQ4
DQ5
DQ6
DQ7
DM1
DM2
VSS
VSS
21
4
6
8
10
12
1413
16
18
2019
22
24
2625
28
30
3231
34
36
3837
40
42
4443
46
48
50
52
54
56
58
60
62
64
6665
68
70
7271
VREFDQ
3
VSS
5
DQ0
CRITICAL
7
DQ1
9
VSS
11
15
17
21
23
27
29
33
35
39
41
45
47
49
51
53
55
57
59
61
63
67
69
7
DM0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1*
DQS1
VSS
DQ10
DQ11
VSS
DQ16
DQ17
VSS
DQS2*
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
VSS
DQ26
DQ27
VSS
J3100
F-RT-BGA6
DDR3-SODIMM
KEY
31
(1 OF 2)
RESET*
1
C3119
0.1UF
20%
10V
2
CERM
402
=MEM_B_DQ<4>
=MEM_B_DQ<5>
=MEM_B_DQS_N<0>
=MEM_B_DQS_P<0>
=MEM_B_DQ<6>
=MEM_B_DQ<7>
=MEM_B_DQ<12>
=MEM_B_DQ<13>
=MEM_B_DM<1>
MEM_RESET_L
=MEM_B_DQ<14>
=MEM_B_DQ<15>
=MEM_B_DQ<20>
=MEM_B_DQ<21>
=MEM_B_DM<2>
=MEM_B_DQ<22>
=MEM_B_DQ<23>
=MEM_B_DQ<28>
=MEM_B_DQ<29>
=MEM_B_DQS_N<3>
=MEM_B_DQS_P<3>
=MEM_B_DQ<30>
=MEM_B_DQ<31>
1
2
C3120
0.1UF
20%
10V
CERM
402
1
2
C3121
0.1UF
20%
10V
CERM
402
1
C3122
2
0.1UF
20%
10V
CERM
402
1
C3123
2
0.1UF
20%
10V
CERM
402
D
28
BI
28
BI
28
BI
28
BI
28
BI
28
BI
28
BI
28
BI
28
IN
26 27
IN
28
BI
28
BI
28
BI
28
BI
28
IN
28
BI
28
BI
28
BI
28
BI
28
BI
28
BI
28
BI
28
BI
C
B
"Expansion" (bottom) slot
SIZE
A
D
SYNC_MASTER=K90I_MLB SYNC_DATE=02/15/2011
PAGE TITLE
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
DDR3 SO-DIMM Connector B
Apple Inc.
R
DRAWING NUMBER
051-9058
REVISION
BRANCH
PAGE
31 OF 109
SHEET
6.0.0
29 OF 86
124578
8 7 6 5 4 3
12
SD Card Connector
516-0225
CRITICAL
J3300
SD-CARD-K19-K24
CRITICAL
L3300
SDCONN_CLK
36 82
IN
SDCONN_CMD
36 82
OUT
SDCONN_DATA<0>
36 82
D
BI
SDCONN_DATA<1>
36 82
BI
SDCONN_DATA<2>
36 82
BI
SDCONN_DATA<3>
36 82
BI
SDCONN_DATA<4>
36 82
BI
SDCONN_DATA<5>
36 82
BI
SDCONN_DATA<6>
36 82
BI
SDCONN_DATA<7>
36 82
BI
SDCONN_CARDDETECT_L
30
OUT
36
OUT
30
R3379
R3361
R3371
R3372
R3373
R3374
R3375
R3376
R3377
R3378
33
33
33
33
33
33
33
33
21
5% 1/16W MF-LF
21
5% 1/16W33MF-LF
21
5% 1/16W33MF-LF
21
5% 1/16W MF-LF
21
5% 1/16W MF-LF
21
5% 1/16W MF-LF
21
5% 1/16W MF-LF
21
5% 1/16W MF-LF
21
5% MF-LF
1/16W
21
5% 1/16W MF-LF
Place near attr for series resistors:
PLACE_NEAR=U3900.21:5MM
PLACE_NEAR=U3900.26:5MM
PLACE_NEAR=U3900.25:5MM
PLACE_NEAR=U3900.24:5MM
PLACE_NEAR=U3900.23:5MM
PLACE_NEAR=U3900.22:5MM
PLACE_NEAR=U3900.52:5MM
PLACE_NEAR=U3900.53:5MM
PLACE_NEAR=U3900.54:5MM
PLACE_NEAR=U3900.55:5MM
402
402
402
402
402
402
402
402
402
402
SDCONN_CLK_R
SDCONN_CMD_R
SDCONN_R_DATA<0>
SDCONN_R_DATA<1>
SDCONN_R_DATA<2>
SDCONN_R_DATA<3>
SDCONN_R_DATA<4>
SDCONN_R_DATA<5>
SDCONN_R_DATA<6>
SDCONN_R_DATA<7>
SDCONN_WP
=PP3V3_S0_SW_SD_PWR
1
C3372
10PF
5%
50V
2
COG-CERM
0201
NOSTUFF
1
C3373
10PF
5%
50V
2
COG-CERM
0201
NOSTUFF
1
C3374
10PF
5%
50V
2
COG-CERM
0201
NOSTUFF
1
C3375
10PF
5%
50V
2
COG-CERM
0201
NOSTUFF
NOSTUFF
1
C3376
10PF
5%
50V
2
COG-CERM
0201
1
C3377
10PF
5%
50V
2
COG-CERM
0201
NOSTUFF
1
C3378
10PF
5%
50V
2
COG-CERM
0201
NOSTUFF
1
C3379
10PF
5%
50V
2
COG-CERM
0201
NOSTUFF
1
C3380
10PF
5%
50V
2
COG-CERM
0201
NOSTUFF
1
C3381
10PF
5%
50V
2
COG-CERM
0201
NOSTUFF
47NH-1.3OHM
NOSTUFF
1
C3371
22PF
5%
50V
2
CERM
0402
0402
21
SDCONN_CLK_R_L
NOSTUFF
1
C3370
15PF
5%
50V
2
CERM
402
F-RT-TH
3
VSS
6
VSS
5
CLK
2
CMD
7
DAT0
8
DAT1
9
DAT2
1
CD/DAT3
10
DAT4
11
DAT5
12
DAT6
13
DAT7
14
CARD_DETECT_SW
15
CARD_DETECT_GND
16
WRITE_PROTECT_SW
4
VDD
17
SHLD_PIN
18
SHLD_PIN
19
SHLD_PIN
20
SHLD_PIN
SD Not Inserted, CARD_DETECT is OPEN.
CAESAR-IV Card Detect is programmable,
but a Silicon bug makes the active
high case unusable.
D
C
C
SD Detect & Reset Logic
SDCONN_DETECT Debounce, Inversion, Detect-Changed PCH GPIO Latch Circuit
Converts SDCONN from active-low level signal to active-high pulses.
=PP3V3_S4_SD_HPD
7
1
C3310
R3311 and R3310 mutually exclusive
to control effect of =ENET_RESET_L
on DET_CHANGED# logic.
ENET_LOW_PWR
24 36
IN
=ENET_RESET_L
24
-> From PCH GPI0
-> From SD Conn
(Low active)
IN
SDCONN_CARDDETECT_L
30
IN
B
R3311
0
5%
1/16W
MF-LF
402
21
SLG_ENET_RESET_IN_L
1
R3310
10K
5%
1/16W
MF-LF
402
2
NOSTUFF
1UF
10%
10V
2
X5R
402-1
SD_DET_LVL_L
1
R3316
10K
5%
1/16W
MF-LF
402
2
2
3
7
1
LOW_PWR
RST_IN*
DET_IN
(IPU)
DET_LVL
VDD
U3311
SLG4AP026V
TDFN
RST
LOGIC
DLY
XOR
GND
5
CRITICAL
10
XOR
RST_OUT*
DET_CH_EN*
DET_CHNGD*
DET_OUT
THRM
PAD
11
4
SLG_ENET_RESET_OUT_L
6
SD_DET_CH_EN_L
(OD)
9
SDCONN_STATE_CHANGE_SMC
(OD)
8
SDCONN_DETECT_L
R3314
1/16W
MF-LF
402
1
R3317
10K
5%
1/16W
MF-LF
402
2
0
5%
1
R3315
10K
5%
1/16W
MF-LF
402
2
21
ENET_RESET_L
1
R3312
0
5%
1/16W
MF-LF
402
2
NOSTUFF
Must STUFF R3312 and NOSTUFF R3314
when R3311 is NOT STUFFED.
R3314 and R3312 mutually exclusive
to bypass reset logic
36 82
OUT
-> To Isolation Circuit (then to PCH GPIOi) & SMC
24 46
OUT
-> To ENET Chip
36
OUT
DLY block is 20ms nominal
When ENET_LOW_PWR deasserts, RST_OUT#
deasserts for >80ms, then asserts for
10ms regardless ofmove RST_IN# state.
Otherwise RST_OUT# follows RST_IN#
B
SD Card 3.3V Overcurrent Protection
TPS2065-1 (1.0A limit) has active load discharge so R4810 is NOSTUFF.
CRITICAL
1
5%
402
2
=PP3V3_S0_SW_SD_PWR
PP3V3_S0_SW_SD_PWR
MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V
=PP3V3_S0_PCH_GPIO
SDCONN_OC_L
U3300
TPS2065-1
2
=PP3V3_S0_SDCARD
7
ENET_CR_PWREN
A
36
CRITICAL
1
C3300
10UF
20%
6.3V
2
X5R
603
1
C3301
0.1UF
10%
16V
2
X7R-CERM
0402
IN0
3
IN1
4
EN
GND
1
DGN
THRM
OUT0
OUT1
OUT2
OC*
PAD
353S3004
9
6
7
8
5
CRITICAL
1
C3302
10UF
20%
6.3V
2
X5R
603
1
C3303
0.1UF
10%
16V
2
X7R-CERM
0402
SDCONN_OC_L_R
NOSTUFF
1
R3300
47K
5%
1/16W
MF-LF
402
2
R3302
0
5%
1/16W
MF-LF
402
R3301
10K
1/16W
MF-LF
21
6 3
30
7
16 17 18 19
SYNC_MASTER=YONAS_J30
PAGE TITLE
SD Card Connector
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
SYNC_DATE=11/03/2011
DRAWING NUMBER
051-9058
REVISION
6.0.0
BRANCH
PAGE
33 OF 109
SHEET
30 OF 86
124578
SIZE
A
D
8 7 6 5 4 3
12
NOTE: Must not enable more than two SO-DIMM margining
=PP3V3_S3_VREFMRGN
7
OMIT
R3418
SHORT
21
PP3V3_S3_VREFMRGN_DAC
MIN_LINE_WIDTH=0.3 mm
NONE
MIN_NECK_WIDTH=0.2 mm
NONE
VOLTAGE=3.3V
NONE
402
D
48
IN
48
BI
DDRVREF_DAC
C3400
=I2C_VREFDACS_SCL
=I2C_VREFDACS_SDA
2.2UF
6.3V
CERM
402-LF
20%
Addr=0x98(WR)/0x99(RD)
OMIT
R3419
SHORT
21
PP3V3_S3_VREFMRGN_CTRL
MIN_LINE_WIDTH=0.3 mm
NONE
MIN_NECK_WIDTH=0.2 mm
NONE
VOLTAGE=3.3V
Page Notes
Power aliases required by this page:
- =PP3V3_S3_VREFMRGN
- =PPVTT_S3_DDR_BUF
- =PPDDR_S3_MEMVREF
Signal aliases required by this page:
- =I2C_VREFDACS_SCL
- =I2C_VREFDACS_SDA
C
B
- =I2C_PCA9557D_SCL
- =I2C_PCA9557D_SDA
BOM options provided by this page:
DDRVREF_DAC - Stuffs Apple margining circuit.
VREFDQ:LDO - LDO outputs sent to DQ inputs.
VREFDQ:LDO_DAC - Margined LDO outputs sent to DQ inputs.
VREFDQ:M1_M3 - CPU margined DDR voltage divider sent to DQ inputs.
VREFDQ:M1_DAC - DAC margined DDR voltage divider sent to DQ inputs.
VREFCA:LDO - LDO outputs sent to CA inputs.
VREFCA:LDO_DAC - DAC margined LDO outputs sent to CA inputs.
=PPDDR_S3_MEMVREF
7
31
MEMRESET_ISOL_LS5V_L
26 31
PPCPU_MEM_VREFDQ_A
9
NONE
402
CRITICAL
VREFDQ:M1_M3
Q3420
SSM6N15AFE
2
SOT563
S G
1
1
2
D
6
DDRVREF_DAC
C3402
Addr=0x30(WR)/0x31(RD)
=I2C_PCA9557D_SCL
48
IN
=I2C_PCA9557D_SDA
48
BI
PCA9557D_RESET_L
24
IN
RST* on ’platform reset’ so that system
watchdog will disable margining.
NOTE: Margining will be disabled across all
soft-resets and sleep/wake cycles.
PLACE_NEAR=Q3420.6:2mm
VREFDQ:M1_M3
C3420
0.1UF
10%
16V
X7R-CERM
0402
VREFDQ:M1_M3
1
2
PLACE_NEAR=R3421.2:1mm
=PPDDR_S3_MEMVREF
7
MEMRESET_ISOL_LS5V_L
26 31
PPCPU_MEM_VREFDQ_B
9
31
CRITICAL
VREFDQ:M1_M3
Q3420
SSM6N15AFE
5
SOT563
S G
4
PLACE_NEAR=Q3420.3:2mm
1
C3440
0.1UF
10%
16V
2
X7R-CERM
0402
D
3
VREFDQ:M1_M3
PLACE_NEAR=Q3420.3:1mm
1
R3441
1K
1%
1/16W
MF-LF
402
2
PLACE_NEAR=R3441.2:1mm
DDRVREF_DAC
1
1
C3401
2
0.1UF
CERM
0.1UF
20%
10V
2
CERM
402
6
SCL
7
SDA
9
A0
10
A1
1
20%
10V
2
402
3
A0
4
A1
5
A2
1
SCL
2
SDA
THRM
PAD
17
8
VDD
MSOP
DAC5574
GND
3
16
VCC
U3401
PCA9557
QFN
GND
8
CRITICAL
DDRVREF_DAC
U3400
VOUTA
VOUTB
VOUTC
VOUTD
CRITICAL
DDRVREF_DAC
(OD)
P0
P1
P2
P3
P4
P5
P6
P7
RESET*
1
2
4
5
NOTE: MEMVREG and FRAMEBUF share
a DAC output, cannot enable
both at the same time!
6
NC
7
9
10
11
12
13
14
NC
15
PLACE_NEAR=Q3420.6:1mm
R3421
1K
1%
1/16W
MF-LF
402
PP0V75_S3_MEM_VREFDQ_A
VREFDQ:M1_M3
1
R3422
1K
1%
1/16W
MF-LF
402
2
NOTE: CPU DAC output step sizes:
DDR3 (1.5V) 7.70mV per step
DDR3L (1.35V) 6.99mV per step
27 31
VREFDQ:M1_M3
PP0V75_S3_MEM_VREFDQ_B
VREFDQ:M1_M3
1
R3442
1K
1%
1/16W
MF-LF
402
2
29 31
VREFMRGN_SODIMMA_DQ
VREFMRGN_SODIMMB_DQ
VREFMRGN_SODIMMS_CA
VREFMRGN_MEMVREG_FBVREF
VREFMRGN_DQ_SODIMMA_EN
VREFMRGN_DQ_SODIMMB_EN
VREFMRGN_CA_SODIMMA_EN
VREFMRGN_CA_SODIMMB_EN
VREFMRGN_MEMVREG_EN
VREFMRGN_FRAMEBUF_EN
DDRVREF_DAC
R3416
1/16W
MF-LF
1
0
5%
402
2
VREFMRGN_MEMVREG_FBVREF_R
DDRVREF_DAC
1
R3413
100K
5%
1/16W
MF-LF
402
2
DDRVREF_DAC
1
R3415
100K
5%
1/16W
MF-LF
402
2
DDRVREF_DAC
1
R3401
100K
5%
1/16W
MF-LF
402
2
DDRVREF_DAC
1
R3402
100K
5%
1/16W
MF-LF
402
2
DDRVREF_DAC
1
R3407
100K
5%
1/16W
MF-LF
402
2
DDRVREF_DAC
1
R3408
100K
5%
1/16W
MF-LF
402
2
A2
A3
DDRVREF_DAC
DDRVREF_DAC
C3403
0.1UF
20%
10V
CERM
402
C3404
0.1UF
20%
10V
CERM
402
DDRVREF_DAC
C3405
0.1UF
CERM
1
2
1
2
20%
10V
402
CRITICAL
VREFMRGN_FRAMEBUF_BUF
DDRVREF_DAC
B1
U3404
MAX4253
V+
UCSP
A1
A4
V-
B4
VREFMRGN_FRAMEBUF_BUF_R
1
2
A2
A3
C2
C3
A2
A3
C2
C3
C2
C3
DDRVREF_DAC
1
R3417
0
5%
1/16W
MF-LF
402
2
B1
V+
V-
B4
B1
V+
V-
B4
B1
V+
V-
B4
B1
V+
V-
B4
B1
V+
V-
B4
buffers at once or VRef source may be overloaded.
VREFDQ:LDO_DAC
R3403
200
PLACE_NEAR=J2900.1:2.54mm
21
1%
1/16W
MF-LF
402
VREFDQ:LDO_DAC
R3404
133
21
1%
PLACE_NEAR=R3403.2:1mm
1/16W
MF-LF
402
VREFDQ:LDO_DAC
R3405
200
PLACE_NEAR=J3100.1:2.54mm
21
1%
1/16W
MF-LF
402
VREFDQ:LDO_DAC
R3406
133
21
1%
PLACE_NEAR=R3405.2:1mm
1/16W
MF-LF
402
VREFCA:LDO_DAC
R3409
200
PLACE_NEAR=J2900.126:2.54mm
21
1%
1/16W
MF-LF
402
VREFCA:LDO_DAC
R3410
133
21
1%
PLACE_NEAR=R3409.2:1mm
1/16W
MF-LF
402
VREFCA:LDO_DAC
R3411
200
PLACE_NEAR=J3100.126:2.54mm
21
1%
1/16W
MF-LF
402
VREFCA:LDO_DAC
R3412
133
21
1%
PLACE_NEAR=R3411.2:1mm
1/16W
MF-LF
402
21
DDRREG_FB
Required zero ohm resistors when no VREF margining circuit stuffed
DESCRIPTION
DESCRIPTION
CRITICAL
DDRVREF_DAC
U3402
MAX4253
UCSP
A1
A4
CRITICAL
DDRVREF_DAC
U3402
MAX4253
UCSP
C1
C4
CRITICAL
DDRVREF_DAC
U3403
MAX4253
UCSP
A1
A4
CRITICAL
DDRVREF_DAC
U3403
MAX4253
UCSP
C1
C4
CRITICAL
DDRVREF_DAC
U3404
MAX4253
UCSP
C1
VREFMRGN_MEMVREG_BUF
C4
PLACE_NEAR=R7320.2:1mm
PART NUMBER
PART NUMBER
=PPVTT_S3_DDR_BUF
7
67
10mA max load
VREFMRGN_DQ_SODIMMA_BUF
VREFMRGN_DQ_SODIMMB_BUF
VREFMRGN_CA_SODIMMA_BUF
VREFMRGN_CA_SODIMMB_BUF
QTY
116S0004
116S0004
2
2
QTY
114S0218
114S0171
4
2
DDRVREF_DAC
R3414
33.2K
1%
1/16W
MF-LF
402
RES,MTL FILM,0,5%,0402,SM,LF
RES,MTL FILM,0,5%,0402,SM,LF
RES,MTL FILM,1K,1%,0402,SM,LF
RES,MTL FILM,332,1%,0402,SM,LF
PP0V75_S3_MEM_VREFDQ_A
MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0.75V
PP0V75_S3_MEM_VREFDQ_B
MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0.75V
PP0V75_S3_MEM_VREFCA_A
MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0.75V
PP0V75_S3_MEM_VREFCA_B
MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0.75V
67
OUT
REFERENCE DES
R3403,R3405
R3409,R3411
REFERENCE DES
R3421,R3422,R3441,R3442
R3404,R3406
CRITICAL
CRITICAL
27 31
29 31
27
29
D
C
B
BOM OPTION
VREFDQ:LDO
VREFCA:LDO
BOM OPTION
VREFDQ:M1_DAC
VREFDQ:M1_DAC
A
DAC Channel:
PCA9557D Pin:
Nominal value
Margined target:
DAC range:
VRef current:
DAC step size:
MEM A VREF DQ
A
1
MEM B VREF DQ
MEM A VREF CA
B
2
0.75V (DAC: 0x3A)
0.300V - 1.200V (+/- 450mV)
0.000V - 1.501V (0x00 - 0x74)
+3.4mA - -3.4mA (- = sourced)
7.69mV / step @ output
MEM B VREF CA
C
3
C
4
MEM VREG
D
5
1.5V (DAC: 0x3A)
1.000V - 2.000V (+/- 500mV)
0.000V - 3.000V (0x00 - 0x74)
+61uA - -61uA (- = sourced)
8.59mV / step @ output
GPU Frame Buffer (1.8V, 70% VRef)
1.267V (DAC: 0x8B)
1.056V - 1.442V (+/- 180mV)
0.000V - 3.300V (0x00 - 0xFF)
+6.0mA - -5.0mA (- = sourced)
1.51mV / step @ output
6 3
SIZE
A
D
SYNC_MASTER=J31_MLB
PAGE TITLE
D
6
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
DDR3/FRAMEBUF VREF MARGINING
Apple Inc.
R
SYNC_DATE=06/13/2011
DRAWING NUMBER
051-9058
REVISION
6.0.0
BRANCH
PAGE
34 OF 109
SHEET
31 OF 86
124578
8 7 6 5 4 3
PLACE_NEAR=J3501.15:2.54mm
C3531
0.1UF
10% 16V
C3530
PLACE_NEAR=J3501.17:2.54mm
21
0.1UF
10% 16V21
0201X5R-CERM
PCIE_AP_R2D_C_P
0201X5R-CERM
PCIE_AP_R2D_C_N
16 81
IN
16 81
IN
12
D
C
B
819Q-3506-K281
A
518S0815
CRITICAL
J3502
F-RT-SM1
D
R3510
0
R3511
0
21
21
727 MA PEAK
606 MA NOMINAL MAX
6
46
AP_TEMP_SMB_SDA_R
6
AP_TEMP_SMB_SCL_R
6
WIFI_EVENT_L_R
6
R3500
R3501
R3502
21
21
21
1/16W5%MF-LF0402
1/16W5%MF-LF0402
1/16W5%MF-LF0402
=AP_TEMP_SMB_SDA
=AP_TEMP_SMB_SCL
WIFI_EVENT_L
PCIE_AP_R2D_P
6
81
PCIE_AP_R2D_N
6
81
1/20W
5% 201MF
1/20W
48
BI
48
IN
45 46
OUT
5% 201MF
516S0582
CRITICAL
J3501
500913-0302
F-ST-SM
32
31
2
1
4
3
6
5
8
7
10
9
12
11
14
13
16
15
18
17
20
19
22
21
24
23
26
25
28
27
30
29
34
33
MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.5 mm
PP3V3_S3RS4_BT_F
6
32
PCIE_WAKE_L
8
PP5V_S3_ALSCAMERA_F
6
5
4
3
2
1
7
6
=I2C_ALS_SCL
=I2C_ALS_SDA
USB_CAMERA_CONN_P
6
80
USB_CAMERA_CONN_N
6
80
PCIE_AP_D2R_PI_P
6
81
PCIE_AP_D2R_PI_N
6
81
6
17 24
OUT
IN
1
2
MIN_LINE_WIDTH=0.5 mm
48
MIN_NECK_WIDTH=0.2 mm
48
BI
PCIE_CLK100M_AP_CONN_P
6
85
PCIE_CLK100M_AP_CONN_N
6
85
C3532
0.01UF
10%
16V
X7R-CERM
0402
L3505
2 1
FERR-120-OHM-1.5A
0402-LF
PLACE_NEAR=J3501.27:2.54mm
L3506
2 1
FERR-120-OHM-1.5A
0402-LF
PLACE_NEAR=J3501.27:2.54mm
CRITICAL
L3507
90-OHM
4 3
PLACE_NEAR=J3502.2:2.54MM
BTPWR:S4
BTPWR:S3
DLP0NS
SYM_VER-1
=PP3V3_S4_BT
=PP3V3_S3_BT
ALS
CAMERA
USB_CAMERA_P
21
USB_CAMERA_N
CRITICAL
L3501
330-OHM-80MA
DLP11S
SYM_VER-1
4 3
PLACE_NEAR=J3501.11:2.54mm
BLUETOOTH
USB_BT_CONN_P
6
80
USB_BT_CONN_N
6
80
7
7
275 mA peak
206 mA nominal max
AIRPORT
PCIE_CLK100M_AP_P
21
PCIE_CLK100M_AP_N
NOSTUFF
6
17 26 45 73
IN
18 80
BI
18 80
BI
NOSTUFF
1
R3517
15K
1%
1/20W
MF
201
2
NOSTUFF
1
R3515
15K
1%
1/20W
MF
201
2
1
R3516
15K
1%
1/20W
MF
201
2
BTPWR:S4
PM_SLP_S4_L
R3519
5%
1/20W
MF
201
AP_RESET_CONN_L
6
AP_CLKREQ_Q_L
6
PLACE_NEAR=J3502.6:2.54MM
L3508
FERR-120-OHM-1.5A
2 1
0402-LF
1
C3552
0.1uF
20%
10V
2
CERM
402
0
21
PLACE_NEAR=J3501.29:2.54mm
16 81
IN
16 81
IN
BTPWR:S3
1
R3518
0
5%
1/20W
MF
201
2
BTMUX_SEL
NOSTUFF
1
C3511
0.01UF
10%
16V
2
X7R-CERM
0402
=PP5V_S3_ALSCAMERA
PCIE_AP_D2R_P
PCIE_AP_D2R_N
PP3V3_WLAN
MIN_LINE_WIDTH=1 mm
MIN_NECK_WIDTH=0.2 mm
C3522
1
2
10
FERR-120-OHM-3A
1
0.1uF
20%
10V
2
CERM
402
9
VCC
Y+
Y-
U3510
PI3USB102ZLE
TQFN
CRITICAL
SEL OE*
GND
3
155S0367
L3504
0603
C3521
0.1uF
20%
10V
CERM
402
5
M+
4
M-
7
D+
6
D-
8
SEL OUTPUT
L USB_BT_WAKE
H USB_BT
7
16 81
OUT
16 81
OUT
MIN_NECK_WIDTH=0.4 mm
MIN_LINE_WIDTH=1 mm
PP3V3_WLAN_F
32
21
PLACE_NEAR=Q3550.6:2.54mm
1
1
C3520
10UF
20%
10V
2
2
X5R
805
PP3V3_S3RS4_BT_F
1
C3510
0.1UF
10%
6.3V
2
X5R
201
USB_BT_WAKEP
USB_BT_WAKEN
USB_BT_P
USB_BT_N
BI
BI
6
BTPWR:S4
8
80
8
80
1
R3553
100K
1%
1/16W
MF-LF
402
2
32
1
R3512
15K
1%
1/20W
MF
201
2
NOSTUFF
1
R3514
15K
1%
1/20W
MF
201
2
NOSTUFF
1
R3513
15K
1%
1/20W
MF
201
2
PP3V3_WLAN_F
1
R3554
232K
1%
1/16W
MF-LF
402
2
P3V3WLAN_VMON
1
R3555
100K
1%
1/16W
MF-LF
402
2
DMP2018LFK
DFN2563-6
4
C3550
0.1UF
21
10%
16V
X5R
402-1
BTPWR:S4
CRITICAL
Q3510
VESM
1
32
CRITICAL
U3540
SLG4AP016V
2
SENSE
0.7V
4
RESET*
7
IN
THRM
PAD
CRITICAL
Q3550
D
G S
TDFN
+
-
9
6 3
3V S3 WLAN FET
MOSFET
CHANNEL
RDS(ON)
LOADING
2
S
1
G
3
0.033UF
P3V3WLAN_SS
=BT_WAKE_L
SSM3K15AMFVAPE
3
D
2
C3551
10%
16V
X5R
402
TPCP8102
P-TYPE
20-30 MOHM @2.5V
0.727 A (EDP)
1
2
R3550
OUT
Supervisor & CLKFREG # ISolation
Delay = 60 ms +/- 20%
=PP3V3_S3_WLAN
1
VDD
DLY
3
MR*
6
EN
8
OUT
(OD)
GND
5
PAGE TITLE
1
C3540
0.1uF
20%
10V
2
CERM
402
7
32
X19/ALS/CAMERA CONNECTOR
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
33K
21
5%
1/16W
MF-LF
402
46
AP_RESET_L
AP_PWR_EN
AP_CLKREQ_L
1
R3551
10K
5%
1/16W
MF-LF
402
2
=PP3V3_S3_WLAN
PM_WLAN_EN_L
24
IN
18 23 73
IN
16
OUT
DRAWING NUMBER
051-9058
REVISION
BRANCH
PAGE
SHEET
124578
73
IN
SYNC_DATE=02/15/2011SYNC_MASTER=K90I_MLB
6.0.0
35 OF 109
32 OF 86
7
32
C
B
A
SIZE
D
8 7 6 5 4 3
12
CRITICAL
RECEIVE
OMIT_TABLE
(SYM 1 OF 2)
CLK REQUEST
TEST PORT
PORT0PORT1
U3600
T29
FCBGA
PCIE GEN2
MISC
SINK PORT 0SINK PORT 1
SOURCE PORT 0
DPSRC0_HOT_PLUG_DET
DISPLAY
PORTS
PET_0_P
PET_0_N
PET_1_P
PET_1_N
PET_2_P
TRANSMIT
PET_2_N
PET_3_P
PET_3_N
WAKE*
PERST*
RSENSE
RBIAS
PCIE_RST_0*
PCIE_RST_1*
PCIE_RST_2*
PCIE_RST_3*
POWER ON RESET
JTAG
REFCLK_100_IN_P
REFCLK_100_IN_N
XTAL_25_IN
XTAL_25_OUT
CLOCKS
TMU_CLK_OUT
TMU_CLK_IN
DPSRC0_ML_LANE_3P
DPSRC0_ML_LANE_3N
DPSRC0_ML_LANE_2P
DPSRC0_ML_LANE_2N
DPSRC0_ML_LANE_1P
DPSRC0_ML_LANE_1N
DPSRC0_ML_LANE_0P
DPSRC0_ML_LANE_0N
DPSRC0_AUX_CHP
DPSRC0_AUX_CHN
DP_ATEST
DP_RES_0
DP_RES_1
PRT2_T29T_P
PRT2_T29T_N
PRT2_T29R_P
PRT2_T29R_N
PORT2
T29_2_LSEO
T29_2_LSOE
PRT3_T29T_P
PRT3_T29T_N
PRT3_T29R_P
PRT3_T29R_N
PORT3
T29_3_LSEO
T29_3_LSOE
1K
402
1
2
1
1%
2
1/16W
MF-LF
10K
402
5%
C3640
C3641
C3642
C3643
C3644
C3645
C3646
C3647
R3651
IN
6
6
6
6
IN
IN
IN
OUT
IN
IN
1
2
6
6
6
6
6
6
6
6
6
6
1
R3632
100K
5%
1/16W
MF-LF
402
2
OUT
OUT
IN
IN
OUT
IN
OUT
OUT
IN
IN
OUT
IN
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
35
8
19
16
8
8
16 81
16 81
8
83
8
83
8
83
8
83
8
8
8
83
8
83
8
83
8
83
8
8
10K
C3685
100PF
V21
PCIE_T29_D2R_C_P<0>
81
T21
PCIE_T29_D2R_C_N<0>
81
P21
PCIE_T29_D2R_C_P<1>
81
M21
PCIE_T29_D2R_C_N<1>
81
K21
PCIE_T29_D2R_C_P<2>
81
H21
PCIE_T29_D2R_C_N<2>
81
F21
PCIE_T29_D2R_C_P<3>
81
D21
PCIE_T29_D2R_C_N<3>
81
F1
T29_PCIE_WAKE_L
E6
T29_RESET_L
E14
T29_RSENSE
R3655
1/16W
MF-LF
E16
T29_RBIAS
Not used in host mode.
K1
TP_T29_PCIE_RESET0_L
J2
TP_T29_PCIE_RESET1_L
K3
TP_T29_PCIE_RESET2_L
J4
TP_T29_PCIE_RESET3_L
T3
TDI
TMS
TCK
TDO
JTAG_TBT_TDI
R4
JTAG_TBT_TMS
R2
JTAG_TBT_TCK
T1
JTAG_TBT_TDO
PCIE_CLK100M_T29_P
H17
G16
PCIE_CLK100M_T29_N
P17
SYSCLK_CLK25M_T29_R
81
R16
TP_T29_XTAL25OUT
U2
T29_TMU_CLK_OUT
E2
T29_TMU_CLK_IN
NO STUFF
R3699
AA18
TP_DP_T29SRC_ML_CP<3>
Y17
TP_DP_T29SRC_ML_CN<3>
AA16
TP_DP_T29SRC_ML_CP<2>
Y15
TP_DP_T29SRC_ML_CN<2>
AA14
TP_DP_T29SRC_ML_CP<1>
Y13
TP_DP_T29SRC_ML_CN<1>
AA12
TP_DP_T29SRC_ML_CP<0>
Y11
TP_DP_T29SRC_ML_CN<0>
W16
TP_DP_T29SRC_AUXCH_CP
U16
TP_DP_T29SRC_AUXCH_CN
V3
DP_T29SRC_HPD
Y19
T29_DP_ATEST
Y21
AA20
T29_DP_RES
R3685
14.0K
1%
1/16W
MF-LF
402
A14
T29_R2D_C_P<2>
A12
T29_R2D_C_N<2>
C12
T29_D2R_P<2>
C10
T29_D2R_N<2>
G4
T29_LSEO<2>
H3
T29_LSOE<2>
A18
T29_R2D_C_P<3>
A16
T29_R2D_C_N<3>
C16
T29_D2R_P<3>
C14
T29_D2R_N<3>
G2
H1
T29_LSOE<3>
NOTE: All unused LSOE/EO pairs should be aliased
together. Other signals okay to float (TP/NC).
21
PCIE_T29_D2R_P<0>
X5R-CERM
0201
16V10%
21
PCIE_T29_D2R_N<0>
X5R-CERM
0201
16V10%
21
PCIE_T29_D2R_P<1>
X5R-CERM
0201
16V10%
21
PCIE_T29_D2R_N<1>
X5R-CERM
0201
16V10%
21
PCIE_T29_D2R_P<2>
0201
X5R-CERM
16V10%
21
PCIE_T29_D2R_N<2>
0201
X5R-CERM
16V10%
21
PCIE_T29_D2R_P<3>
0201
X5R-CERM
16V10%
21
PCIE_T29_D2R_N<3>
0201
X5R-CERM
16V10%
=PP3V3_T29_RTR
21
1/20W
5% 201
=PP3V3_T29_RTR
1
R3698
10K
5%
1/16W
MF-LF
402
2
1
R3696
1K
5%
1/16W
MF-LF
402
2
100pF SRF > 40MHz
BYPASS=U3600.Y19::2mm
BYPASS=U3600.Y19::5.08mm
1
1
C3686
CERM
0402
5%
50V
0.01UF
10%
16V
2
2
X7R-CERM
0402
8
81
OUT
8
81
OUT
8
81
OUT
8
81
OUT
8
81
OUT
8
81
OUT
8
81
OUT
8
81
OUT
7
33 34 35
MF
7
33 34 35
R3695
806
21
SYSCLK_CLK25M_T29
1%
1/16W
MF-LF
402
PAGE TITLE
T29 Host (1 of 2)
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
D
C
24 81
IN
B
SIZE
A
D
SYNC_DATE=02/15/2011SYNC_MASTER=K90I_MLB
DRAWING NUMBER
051-9058
REVISION
BRANCH
PAGE
36 OF 109
SHEET
6.0.0
33 OF 86
124578
5%
1/16W
MF-LF
402
R3629
1/16W
MF-LF
8
OUT
R3630
100K
1/16W
MF-LF
8
OUT
R3631
100K
1/16W
MF-LF
1
R3621
10K
5%
1/16W
MF-LF
402
2
1
0
5%
402
2
1
5%
402
2
1
5%
402
2
21
X5R-CERM
16V10%
21
X5R-CERM
16V10%
21
X5R-CERM
16V10%
21
X5R-CERM
16V10%
21
X5R-CERM
16V10%
21
X5R-CERM
16V10%
21
X5R-CERM
16V10%
21
X5R-CERM
16V10%
PCIE_T29_R2D_P<0>
81
0201
PCIE_T29_R2D_N<0>
81
0201
PCIE_T29_R2D_P<1>
81
0201
PCIE_T29_R2D_N<1>
81
0201
PCIE_T29_R2D_P<2>
81
0201
PCIE_T29_R2D_N<2>
81
0201
PCIE_T29_R2D_P<3>
81
0201
PCIE_T29_R2D_N<3>
81
0201
TP_TBT_MONDC0
6
TP_TBT_MONDC1
6
DEBUG: For monitoring current/voltage
TP_TBT_MONOBSP
6
TP_TBT_MONOBSN
6
DEBUG: For monitoring clock
=T29_CLKREQ_L
35
OUT
T29_GPIO<1>
T29_GPIO<2>
T29_RSVD
T29_SPI_MOSI
83
T29_SPI_MISO
83
T29_SPI_CS_L
83
T29_SPI_CLK
83
TP_T29_THERM_DP
51
Use B1 GND ball for THERM_DN
T29_TEST_EN
TP_T29_TEST_POINT_0
TP_T29_TEST_POINT_1
TP_T29_TEST_POINT_2
T29_TEST_POINT_3
DP_T29SNK0_ML_P<3>
33 83
DP_T29SNK0_ML_N<3>
33 83
DP_T29SNK0_ML_P<2>
33 83
DP_T29SNK0_ML_N<2>
33 83
DP_T29SNK0_ML_P<1>
33 83
DP_T29SNK0_ML_N<1>
33 83
DP_T29SNK0_ML_P<0>
33 83
DP_T29SNK0_ML_N<0>
33 83
DP_T29SNK0_AUXCH_P
33 83
DP_T29SNK0_AUXCH_N
33 83
DP_T29SNK0_HPD
DP_T29SNK1_ML_P<3>
33 83
DP_T29SNK1_ML_N<3>
33 83
DP_T29SNK1_ML_P<2>
33 83
DP_T29SNK1_ML_N<2>
33 83
DP_T29SNK1_ML_P<1>
33 83
DP_T29SNK1_ML_N<1>
33 83
DP_T29SNK1_ML_P<0>
33 83
DP_T29SNK1_ML_N<0>
33 83
DP_T29SNK1_AUXCH_P
33 83
DP_T29SNK1_AUXCH_N
33 83
DP_T29SNK1_HPD
T29_R2D_C_P<0>
75 83
OUT
T29_R2D_C_N<0>
75 83
OUT
T29_D2R_P<0>
75 83
IN
T29_D2R_N<0>
75 83
IN
T29_LSEO<0>
75
OUT
T29_LSOE<0>
75
IN
T29_R2D_C_P<1>
75 83
OUT
T29_R2D_C_N<1>
75 83
OUT
T29_D2R_P<1>
75 83
IN
T29_D2R_N<1>
75 83
IN
T29_LSEO<1> T29_LSEO<3>
75
OUT
T29_LSOE<1>
75
IN
I2C_T29_SDA
48 83
BI
I2C_T29_SCL
48 83
OUT
V19
PER_0_P
T19
PER_0_N
P19
PER_1_P
M19
PER_1_N
K19
PER_2_P
H19
PER_2_N
F19
PER_3_P
D19
PER_3_N
B21
MONDC0
A20
MONDC1
K17
MONOBSP
M17
MONOBSN
P3
PCIE_CLKREQ_0*
N4
PCIE_CLKREQ_1*
M3
PCIE_CLKREQ_2*
L4
PCIE_CLKREQ_3*
P1
EE_DI
M1
EE_DO
N2
EE_CS*
L2
EE_CLK
A2
THERM_DP
E4
TEST_EN
P5
TEST_POINT_0
N6
TEST_POINT_1
M5
TEST_POINT_2
L6
TEST_POINT_3
AA4
DPSNK0_ML_LANE_3P
Y3
DPSNK0_ML_LANE_3N
AA6
DPSNK0_ML_LANE_2P
Y5
DPSNK0_ML_LANE_2N
AA8
DPSNK0_ML_LANE_1P
Y7
DPSNK0_ML_LANE_1N
AA10
DPSNK0_ML_LANE_0P
Y9
DPSNK0_ML_LANE_0N
V1
DPSNK0_AUX_CHP
W2
DPSNK0_AUX_CHN
V5
DPSNK0_HOT_PLUG_DET
V9
DPSNK1_ML_LANE_3P
U8
DPSNK1_ML_LANE_3N
V11
DPSNK1_ML_LANE_2P
U10
DPSNK1_ML_LANE_2N
V13
DPSNK1_ML_LANE_1P
U12
DPSNK1_ML_LANE_1N
V15
DPSNK1_ML_LANE_0P
U14
DPSNK1_ML_LANE_0N
V7
DPSNK1_AUX_CHP
U6
DPSNK1_AUX_CHN
U4
DPSNK1_HOT_PLUG_DET
A6
PRT0_T29T_P
A4
PRT0_T29T_N
C4
PRT0_T29R_P
C2
PRT0_T29R_N
J6
T29_0_LSEO
K5
T29_0_LSOE
A10
PRT1_T29T_P
A8
PRT1_T29T_N
C8
PRT1_T29R_P
C6
PRT1_T29R_N
G6
T29_1_LSEO
H5
T29_1_LSOE
F3
T29_SDA
F5
T29_SCL
EEPROM
10K
402
C3600
0.1UF
C3601
0.1UF
C3602
0.1UF
C3603
0.1UF
C3604
0.1UF
C3605
0.1UF
C3606
0.1UF
C3607
0.1UF
1
1
R3622
10K
5%
5%
1/16W
MF-LF
402
2
2
1
R3625
0
2
PCIE_T29_R2D_C_P<0>
8
81
IN
PCIE_T29_R2D_C_N<0>
8
81
IN
PCIE_T29_R2D_C_P<1>
8
81
IN
PCIE_T29_R2D_C_N<1>
8
81
IN
PCIE_T29_R2D_C_P<2>
8
81
IN
D
1
1
402
1
R3691
5%
2
2
R3690
3.3K
1/16W
MF-LF
(T29_SPI_MOSI)
C
(T29_SPI_CLK)
(T29_SPI_CS_L)
C3690
3.3K
5%
1/16W
MF-LF
402
T29ROM_WP_L
T29ROM_HOLD_L
1UF
10%
6.3V
CERM
402
2
5
D Q
M95320-RMC6XG
6
C
1
S_L
3
W_L
7
HOLD_L
VCC
U3690
MLP
VSS
489
CRITICAL
OMIT_TABLE
2
THM
PAD
PCIE_T29_R2D_C_N<2>
8
81
IN
PCIE_T29_R2D_C_P<3>
8
81
IN
PCIE_T29_R2D_C_N<3>
8
81
IN
R3692
3.3K
1/16W
MF-LF
(T29_SPI_MISO)
402
=PP3V3_T29_RTR
7
33 34 35
1
R3623
5%
2
1
R3693
3.3K
5%
1/16W
MF-LF
402
2
1/16W
MF-LF
SNK0 AC Coupling
DP_T29SNK0_ML_C_P<0>
8
83
IN
DP_T29SNK0_ML_C_N<0>
8
83
IN
DP_T29SNK0_ML_C_P<1>
8
83
IN
DP_T29SNK0_ML_C_N<1>
8
83
IN
B
DP_T29SNK0_ML_C_P<2>
8
83
IN
DP_T29SNK0_ML_C_N<2>
8
83
IN
DP_T29SNK0_ML_C_P<3>
8
83
IN
DP_T29SNK0_ML_C_N<3>
8
83
IN
DP_T29SNK0_AUXCH_C_P
8
83
BI
DP_T29SNK0_AUXCH_C_N
8
83
BI
C3620
0.1UF
C3621
0.1UF
C3622
0.1UF
C3623
0.1UF
C3624
0.1UF
C3625
0.1UF
C3626
0.1UF
C3627
0.1UF
C3628
0.1UF
C3629
0.1UF
21
DP_T29SNK0_ML_P<0>
16V10%
0201
X5R-CERM
21
DP_T29SNK0_ML_N<0>
16V10%
0201
X5R-CERM
21
DP_T29SNK0_ML_P<1>
16V10%
0201
X5R-CERM
21
DP_T29SNK0_ML_N<1>
16V10%
0201
X5R-CERM
21
DP_T29SNK0_ML_P<2>
16V10%
0201
X5R-CERM
21
DP_T29SNK0_ML_N<2>
16V10%
0201
X5R-CERM
21
DP_T29SNK0_ML_P<3>
16V10%
0201
X5R-CERM
21
DP_T29SNK0_ML_N<3>
16V10%
0201
X5R-CERM
21
DP_T29SNK0_AUXCH_P
16V10%
0201
X5R-CERM
21
DP_T29SNK0_AUXCH_N
16V10%
0201
X5R-CERM
33 83
33 83
33 83
33 83
33 83
33 83
33 83
33 83
33 83
33 83
SNK1 AC Coupling
DP_T29SNK1_ML_C_P<0>
8
83
IN
DP_T29SNK1_ML_C_N<0>
8
83
IN
DP_T29SNK1_ML_C_P<1>
8
83
IN
DP_T29SNK1_ML_C_N<1>
8
83
IN
DP_T29SNK1_ML_C_P<2>
8
83
A
IN
DP_T29SNK1_ML_C_N<2>
8
83
IN
DP_T29SNK1_ML_C_P<3>
8
83
IN
DP_T29SNK1_ML_C_N<3>
8
83
IN
DP_T29SNK1_AUXCH_C_P
8
83
BI
DP_T29SNK1_AUXCH_C_N
8
83
BI
C3630
0.1UF
C3631
0.1UF
C3632
0.1UF
C3633
0.1UF
C3634
0.1UF
C3635
0.1UF
C3636
0.1UF
C3637
0.1UF
C3638
0.1UF
C3639
0.1UF
21
DP_T29SNK1_ML_P<0>
16V10%
0201
X5R-CERM
21
DP_T29SNK1_ML_N<0>
16V10%
0201
X5R-CERM
21
DP_T29SNK1_ML_P<1>
16V10%
0201
X5R-CERM
21
DP_T29SNK1_ML_N<1>
16V10%
0201
X5R-CERM
21
DP_T29SNK1_ML_P<2>
16V10%
0201
X5R-CERM
21
DP_T29SNK1_ML_N<2>
16V10%
X5R-CERM
0201
21
DP_T29SNK1_ML_P<3>
16V10%
0201
X5R-CERM
21
DP_T29SNK1_ML_N<3>
16V10%
0201
X5R-CERM
21
DP_T29SNK1_AUXCH_P
16V10%
0201
X5R-CERM
21
DP_T29SNK1_AUXCH_N
16V10%
X5R-CERM
0201
33 83
33 83
33 83
33 83
33 83
33 83
33 83
33 83
33 83
33 83
6 3
8 7 6 5 4 3
12
D
=PP1V05_T29_RTR
7
2100 mA (Single Port)
2250 mA (Dual Port)
EDP: 3000 mA
C
L3730
FERR-120-OHM-1.5A
0402
1
C3700
10UF
20%
6.3V
2
X5R
603
1
C3701
10UF
20%
6.3V
2
X5R
603
21
PP1V05_T29_VDD_DPPLL
MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.05V
1
C3705
1UF
10%
6.3V
2
CERM
402
1
C3710
1UF
10%
6.3V
2
CERM
402
1
C3706
1UF
10%
6.3V
2
CERM
402
1
C3711
1UF
10%
6.3V
2
CERM
402
1
C3707
1UF
10%
6.3V
2
CERM
402
1
C3712
1UF
10%
6.3V
2
CERM
402
1
C3720
1UF
10%
6.3V
2
CERM
402
1
C3708
1UF
10%
6.3V
2
CERM
402
1
C3713
1UF
10%
6.3V
2
CERM
402
1
C3721
1UF
10%
6.3V
2
CERM
402
1
C3709
1UF
10%
6.3V
2
CERM
402
1
C3714
1UF
10%
6.3V
2
CERM
402
1
C3722
1UF
10%
6.3V
2
CERM
402
1
C3730
2.2UF
20%
6.3V
2
CERM
402-LF
B
H9
VCC1P0
H11
VCC1P0
H13
VCC1P0
K9
VCC1P0
K11
VCC1P0
K13
VCC1P0
M9
VCC1P0
M11
VCC1P0
M13
VCC1P0
H15
VCC1P0_PE
K15
VCC1P0_PE
M15
VCC1P0_PE
E8
VCC1P0_PE
E10
VCC1P0_PE
E12
VCC1P0_PE
G14
VCC1P0_PE
R8
VDD1P0_DP_RX1
R10
VDD1P0_DP_TXRX
R12
VDD1P0_DP_TXRX
R14
VDD1P0_DP_PLL
G8
VSS
J8
VSS
J10
VSS
J12
VSS
J14
VSS
L8
VSS
L10
VSS
L12
VSS
L14
VSS
N8
VSS
N10
VSS
N12
VSS
N14
VSS
B1
VSSPE
B3
VSSPE
B5
VSSPE
B7
VSSPE
B9
VSSPE
B11
VSSPE
B13
VSSPE
B15
VSSPE
B17
VSSPE
B19
VSSPE
C18
VSSPE
C20
VSSPE
D1
VSSPE
D3
VSSPE
D5
VSSPE
D7
VSSPE
D9
VSSPE
D11
VSSPE
D13
VSSPE
D15
VSSPE
D17
VSSPE
E18
VSSPE
E20
VSSPE
F7
VSSPE
CRITICAL
OMIT_TABLE
U3600
T29
FCBGA
(SYM 2 OF 2)
VCC3P3_DP_TXRXBIAS
GND VCC
VCC3P3
VCC3P3
VCC3P3
VCC3P3_T29
VCC3P3_T29
VCC3P3_DP_RX1
VCC3P3_DP_RX1
VCC3P3_DP_TXRX
VCC3P3_DP_TXRX
VDD3P3DP_PLL
VSSDP
VSSDP
VSSDP
VSSDP
VSSDP
VSSDP
VSSDP
VSSDP
VSSDP
VSSDP
VSSDP
VSSDP
VSSDP
VSSDP
VSSDP
VSSDP_PLL
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
H7
M7
K7
G10
G12
P7
R6
P9
P11
P13
P15
T5
T7
T9
T11
T15
T17
V17
W4
W6
W8
W10
W12
W14
Y1
AA2
T13
F9
F11
F13
F15
F17
G18
G20
J16
J18
J20
L16
L18
L20
N16
N18
N20
R18
R20
U18
U20
W18
W20
C3744
1UF
10%
6.3V
CERM
402
C3753
1UF
10%
6.3V
CERM
402
C3760
1UF
10%
6.3V
CERM
402
C3770
2.2UF
20%
6.3V
CERM
402-LF
1
C3743
2
1
C3752
2
1
2
PP3V3_T29_DPBIAS
MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V
1
2
1UF
6.3V
CERM
1UF
6.3V
CERM
10%
402
10%
402
1
2
1
2
C3745
1UF
10%
6.3V
CERM
402
C3751
1UF
10%
6.3V
CERM
402
1
2
1
2
1
C3746
10UF
20%
6.3V
2
X5R
603
C3750
1UF
6.3V
CERM
10%
402
1
C3747
10UF
20%
6.3V
2
X5R
603
1
2
L3770
FERR-120-OHM-1.5A
0402
=PP3V3_T29_RTR
135 mA (Single-Port)
152 mA (Dual-Port)
EDP: 200 mA
21
7
33 35
D
C
B
A
Current numbers from Vendor slide (<REDACTED> power measure 1.ppt), emailed 6/21/2010, TDP @ 90C.
6 3
SYNC_MASTER=K90I_MLB SYNC_DATE=02/15/2011
PAGE TITLE
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
T29 Host (2 of 2)
Apple Inc.
R
DRAWING NUMBER
051-9058
REVISION
BRANCH
PAGE
37 OF 109
SHEET
6.0.0
34 OF 86
124578
SIZE
A
D
8 7 6 5 4 3
12
Page Notes
Power aliases required by this page:
- =PPVIN_SW_T29BST (8-13V Boost Input)
- =PP18V_T29_REG (18V Boost Output)
- =PP3V3_T29_P3V3T29FET (3.3V FET Input)
- =PP3V3_T29_FET (3.3V FET Output)
- =PP3V3_S0_T29PWRCTL
- =PP1V05_T29_P1V05T29FET (1.05V FET Input)
- =PP1V05_T29_FET (1.05V FET Output)
Signal aliases required by this page:
- =T29_CLKREQ_L
D
- =T29_RESET_L
BOM options provided by this page:
T29BST:Y - Stuffs 18V boost circuitry.
C
Platform (PCIe) Reset
=T29_RESET_L
24
IN
Open-Drain GPIO
TBT_SW_RESET_L
19
IN
TBT_PWR_EN
24
IN
TBT_CLKREQ_L
16
OUT
Pull-up provided by SB page.
Supervisor & CLKREQ# Isolation
=PP3V3_S0_T29PWRCTL
7
C3800
0.1UF
2
R3803
10K
5%
1/16W
MF-LF
402
1
10%
25V
X5R
402
1
2
SLG4AP016V
3
MR*
6
EN
8
OUT
(OD)
1
VDD
U3800
TDFN
DLY
GND
5
CRITICAL
SENSE
+
-
0.7V
RESET*
IN
THRM
PAD
9
=PPVIN_SW_T29BST
7 8
8-13V Input
Changes required
for 2S.
=PP3V3_T29_RTR
1
R3807
100K
5%
1/16W
MF-LF
402
2
2
4
7
PP1V05_T29
T29_RESET_L
DLY = 60 ms +/- 20%
=T29_CLKREQ_L
T29_CLKREQ_ISOL_L
MAKE_BASE=TRUE
T29BST:Y
R3880
470K
1/16W
MF-LF
T29BST:Y
R3881
330K
1/16W
MF-LF
75 76
IN
7
33 34
7
T29BST:Y
1
1
C3880
5%
2
402
2
T29BST_PWREN_DIV_L
1
5%
402
2
T29BST_PWREN_L
SSM3K15AMFVAPE
T29BST:Y
TBT_A_HV_EN
33
OUT
33
IN
0.1UF
10%
25V
X5R
402
Q3805
VESM
SI8409DB:
CRITICAL
T29BST:Y
Q3880
SI8409DB
SGD
4
1
T29BST:Y
3
D
C3892
4.7UF
1
G S
2
T29BST:Y
1
R3892
73.2K
1%
1/16W
MF-LF
402
2
<R2>
UVLO(falling) = 1.22 * (R1 + R2) / R2
UVLO(rising) = UVLO(falling) + (2uA * R1)
UVLO = 4.55V (falling), 4.95 (rising)
Vds(max): -30V
Vgs(max): +/-12V
Vgs(th): -1.4V
Rds(on): 46mOhm @ 4.5V Vgs
Id(max): 3.7A @ 70C
BGA
32
PPVIN_SW_T29BST
7
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
Voltage not specified here,
add property on another page.
1
1
C3887
47PF
10%
10V
X5R
805
5%
50V
2
2
CERM
402
T29BST_VC_RC
T29BST:Y
1
C3893
0.0033UF
10%
50V
2
X7R-CERM
0402
T29BST:Y
R3893
10K
1/16W
MF-LF
T29BST:Y
R3894
T29BST:Y
1
1%
402
2
41.2K
1/16W
MF-LF
402
R3891
200K
1/16W
MF-LF
<R1>
1
1%
2
1
T29 15V Boost Regulator
T29BST:Y
C3890
10UF
10%
25V
X5R
1
1%
402
6
805
2
T29BST_EN_UVLO
T29BST_INTVCC
T29BST_VC
T29BST_RT
T29BST_SS
T29BST:Y
1
C3894
0.33UF
10%
6.3V
2
CERM-X5R
402
GND_T29BST_SGND
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=0V
T29BST:Y
D
Q3888
SSM6N37FEAPE
SOT563
Max Vgs: 10V
2
S G
T29BST_SHDN_DIV
T29BST:Y
1
R3887
330K
5%
1/20W
MF
201
2
T29BST:Y
1
C3891
2
10UF
10%
25V
X5R
805
1
2
VIN
25
EN/UVLO
28
INTVCC
30
VC
33
RT
32
SS
34
SYNC
SGND
4
SGND shorted to
GND inside package,
no XW necessary.
T29BST:Y
1
R3888
330K
5%
1/20W
MF
201
2
T29BST:Y
3
D
Q3888
SSM6N37FEAPE
SOT563
5
S G
4
SMC_DELAYED_PWRGD
CRITICAL
T29BST:Y
L3895
10UH-4A-68-MOHM
PCMB063T-100MS
9
CRITICAL
T29BST:Y
U3890
LT3957
QFN
372423
12
8
SW
GND
27
21
T29BST_BOOST
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
SWITCH_NODE=TRUE
DIDT=TRUE
382120
6
SNS1
3
SNS2
T29BST_VSNS_RC
1
2
10
NC
35
36
31
FBX
1716151413
NC
T29BST_SNS1
T29BST_SNS2
T29BST:Y
R3890
1
C3888
22PF
5%
50V
2
CERM
0402
T29BST_FBX
NO STUFF
1
C3889
100PF
5%
50V
2
CERM
0402
T29BST:Y
R3889
49.9K
2 1
1%
1/16W
MF-LF
402
1/16W
MF-LF
T29BST:Y
R3895
T29BST:Y
R3896
Vout = 1.6V * (1 + Ra / Rb)
24 45 46
IN
1
0
5%
402
2
T29BST_VSNS
1
137K
1%
1/16W
MF-LF
402
2
<Ra>
1
15.8K
1%
1/16W
MF-LF
402
2
<Rb>
CRITICAL
T29BST:Y
A
D3895
POWERDI-123
DFLS230L
K
PLACE_NEAR=C3897.1:2 mm
XW3895
SM
21
T29BST:Y
1
C3895
4.7UF
10%
50V
2
X7R-CERM
1206
T29BST:Y
C3896
4.7UF
10%
50V
X7R-CERM
1206
1
2
T29BST:Y
1
2
T29BST:Y
C3898
C3897
4.7UF
10%
50V
X7R-CERM
1206
4.7UF
X7R-CERM
1206
=PP15V_T29_REG
Vout = 18.3V
Max Current = 0.8A
Freq = 300KHz
T29BST:Y
1
1
C3899
10%
50V
0.001UF
10%
50V
2
2
X7R-CERM
0402
D
7 8
C
SIZE
B
A
D
B
=PP3V3_S0_P3V3T29FET
7 7
C3810
1UF
10%
6.3V
CERM
402
R3816
1/16W
MF-LF
TBT_PWR_EN_RC
=PP1V05_S0_P1V05T29FET
7 7
A
C3815
1UF
10%
6.3V
CERM
402
NO STUFF
C3816
1UF
10%
6.3V
CERM
402
3.3V T29 Switch
U3810
TPS22924
CSP
GND
A1
VOUT
B1
C1
A2
VIN
B2
1
2
5%
402
CRITICAL
C2
ON
1
0
2
1.05V T29 Switch
U3815
TPS22920
CSP
GND
A1
B1
VOUT
C1
D1
A2
B2
VIN
C2
1
2
CRITICAL
D2
ON
1
2
=PP3V3_T29_FET
Max Current = 2A (85C)
=PP1V05_T29_FET
Max Current = 4A (85C)
Part
Type
R(on)
@ 2.5V
Part
Type
R(on)
@ 1.05V
U3810
TPS22924C
Load Switch
18.3 mOhm Typ
24 mOhm Max
U3815
TPS22920
Load Switch
8 mOhm Typ
11.5 mOhm Max
6 3
SYNC_MASTER=K90I_MLB SYNC_DATE=02/15/2011
PAGE TITLE
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
T29 Power Support
Apple Inc.
R
DRAWING NUMBER
051-9058
REVISION
BRANCH
PAGE
38 OF 109
SHEET
6.0.0
35 OF 86
124578
8 7 6 5 4 3
BCM57765 ENET SR pins are internal 1.2V switching regulator. See note for SR_DISABLE below.
If disabled: Okay to float VDD, VDDP & LX pin. VFB must always connect to =PP1V2_S3_ENET_PHY.
If enabled: VDD/VDDP connect to =PP3V3_S3_ENET_PHY (add bypassing), LX connects to inductor.
Special Star routing needed on these pins. Decoupling on Pg 37.
=PP3V3_ENET_PHY
7
24 36 71
281mA (1000base-T max power, Caesar IV)
CRITICAL
L3900
FERR-600-OHM-0.5A
D
CRITICAL
FERR-600-OHM-0.5A
CRITICAL
FERR-600-OHM-0.5A
=PP3V3_S0_ENETPHY
C
PCIE_ENET_D2R_N
16 81
OUT
PCIE_ENET_D2R_P
16 81
OUT
PCIE_ENET_R2D_C_P
16 81
IN
PCIE_ENET_R2D_C_N
16 81
IN
=ENET_WAKE_L
24
OUT
(See note)
WAKE#
Must isolate from PCIe WAKE# if PHY
is powered-down in S3/S5. Standard
N-channel FET isolation suggested.
B
If PHY is always powered then alias
=ENET_WAKE_L to PCIE_WAKE_L.
7
C3950
0.1UF
10%
16V
X7R-CERM
0402
C3955
0.1UF
10%
16V
X7R-CERM
0402
R3943
0
5%
1/16W
MF-LF
402
21
C3951
0.1UF
21
10%
16V
X7R-CERM
0402
21
C3956
0.1UF
21
10%
16V
X7R-CERM
0402
21
SM
L3905
SM
L3910
SM
21
PP3V3_S3_ENET_PHY_XTALVDDH
MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V
21
PP3V3_S3_ENET_PHY_BIASVDDH
MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V
21
PP3V3_S3_ENET_PHY_AVDDH
MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V
1
R3940
4.7K
5%
1/16W
MF-LF
402
2
1
R3942
1K
Current
5%
1/16W
Limiting
MF-LF
Resistor
402
2
81
81
81
81
16 81
IN
16 81
IN
30 82
IN
16
OUT
24 30
IN
BCM57765_SCLK
36
BCM57765_MISO
36
BCM57765_MOSI
36
BCM57765_CS_L
36
TP_BCM57765_SPD100LED_L
TP_BCM57765_TRAFFICLED_L
24 81
SYSCLK_CLK25M_ENET
IN
R3910
4.7K
1/16W
MF-LF
402
1
R3941
4.7K
5%
1/16W
MF-LF
402
2
ENET_VMAIN_PRSNT
PCIE_ENET_D2R_C_N
PCIE_ENET_D2R_C_P
PCIE_ENET_R2D_P
PCIE_ENET_R2D_N
PCIE_CLK100M_ENET_P
PCIE_CLK100M_ENET_N
ENET_RESET_L
ENET_CLKREQ_L
ENET_WAKE_R_L
ENET_LOW_PWR
BCM57765_SMB_CLK
BCM57765_SMB_DATA
C3900
0.1UF
X7R-CERM
0402
1
5%
2
10%
16V
C3915
X5R-CERM
4.7UF
BCM57765_RDAC
1
R3965
1.24K
1%
1/16W
MF-LF
402
2
=PP3V3_ENET_PHY
7
24 36 71
PHY Non-Volatile Memory
ROM contains MAC address, PCIe config
info as well as code for Bonjour proxy.
Required for proper PHY operation.
(Required ROM size TBD)
1
2
6.3V
1
2
1
2
10%
603
C3905
0.1UF
10%
16V
X7R-CERM
0402
C3910
0.1UF
10%
16V
X7R-CERM
0402
1
2
36
VDD for Card Reader I/O
=PP3V3R1V8_ENET_LR_OUT
1
C3911
0.1UF
10%
16V
2
X7R-CERM
0402
1
C3916
0.1UF
2
10%
16V
X7R-CERM
0402
NC
42
AVDDH
58
VMAIN_PRSNT
27
PCIE_TXD_N
28
PCIE_TXD_P
33
PCIE_RXD_P
34
PCIE_RXD_N
31
PCIE_REFCLK_P
30
PCIE_REFCLK_N
11
PERST*
12
CLKREQ*
3
WAKE*
4
LOW_PWR
6
SMB_CLK
10
SMB_DATA
66
SCLK_SPD1000LED*
64
SI/EEDATA
65
SO_LINKLED*
63
CS*/EECLK
2
SPD100LED*/SERIAL_DO
67
TRAFFICLED*/SERIAL_DI
18
XTALI
19
XTALO
38
RDAC
7
17
37
48
62
56
20
151416
VDDO
SR_VDD
BIASVDDH
XTALVDDH
(IPD)
(IPD)
(OD)
(OD)
SD_DETECT can only be used active low due to errata.
(IPD)
(IPD)
SR_VDDP
U3900
BCM57765B0
QFN-8X8
NOTE: "IPx" == Programmable pull-up/down
(IPU)
(OD)
(OD)
THRM_PAD
69
SR_LX
13
ENET_SR_LX
ENET_SR_VFB
29
514539
AVDDL
71
Internal 1.2V Switching Regulator pins.
71
C3921
0.1UF
X7R-CERM
0402
C3926
0.1UF
X7R-CERM
0402
C3931
0.1UF
X7R-CERM
0402
61
35
32
36
VDDC
SR_VFB
GPHY_PLLVDDL
PCIE_PLLVDDL
GPIO_0/CR_ACT_LED*
GPIO_1/LR_OUT
(IPD)
GPIO_2/MEDIA_SENSE
SD_DETECT
(IPx)
(IPU)
(IPU)
CR_LED*/CR_BUS_PWR
(IPU)
SR_DISABLE
TRD0_P
TRD0_N
TRD1_P
TRD1_N
TRD2_P
TRD2_N
TRD3_P
TRD3_N
CR_CMD
CR_CLK
CR_DATA0
CR_DATA1
CR_DATA2
CR_DATA3
CR_DATA4
CR_DATA5
CR_DATA6
CR_DATA7
MS_INS*
CR_WP*
40
41
44
43
46
47
50
49
5
8
9
1
o
26
21
25
24
23
22
52
53
54
55
59
60
57
68
BCM57765 supports both active-levels for WP.
10%
16V
10%
16V
10%
16V
1
2
1
2
1
2
1
C3936
0.1UF
10%
16V
2
X7R-CERM
0402
ENET_MDI_P<0>
ENET_MDI_N<0>
ENET_MDI_P<1>
ENET_MDI_N<1>
ENET_MDI_P<2>
ENET_MDI_N<2>
ENET_MDI_P<3>
ENET_MDI_N<3>
NC
TP_CE_L_MS_INS_L
ENET_CR_PWREN
BDM57765_SR_DISABLE
PP1V2_ENET_PHY_AVDDL
MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.2V
1
C3920
4.7UF
10%
6.3V
2
X5R-CERM
603
PP1V2_ENET_PHY_PCIEPLL
MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.2V
1
C3925
4.7UF
10%
6.3V
2
X5R-CERM
603
PP1V2_ENET_PHY_GPHYPLL
MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.2V
1
C3930
4.7UF
10%
6.3V
2
X5R-CERM
603
CRITICAL
1
C3935
10UF
10%
6.3V
2
X5R
805
BI
BI
BI
BI
BI
BI
BI
BI
OUT
R3980
37 82
37 82
37 82
37 82
37 82
37 82
37 82
37 82
30
CRITICAL
L3920
FERR-600-OHM-0.5A
SM
CRITICAL
L3925
FERR-600-OHM-0.5A
SM
CRITICAL
L3930
FERR-600-OHM-0.5A
SM
LR_OUT/GPIO1 is used as a 3.3V/1.8V internal LDO out for
the card reader on-chip I/O.
Connect only to U3900 pin 20.
1
C3970
4.7UF
10%
6.3V
2
X5R-CERM
603
No MS (Memory Stick) Insert feature needed.
Control signal to light LED or control SD bus power.
1K
SR_DISABLE must be pulled down to use
internal SR. IPD has a race condition.
=PP1V2_ENET_PHY
???mA (1000base-T, Caesar V)
21
21
21
1
C3971
0.1UF
10%
16V
2
X7R-CERM
0402
21
1/16W
5%
MF-LF
71
=PP3V3R1V8_ENET_LR_OUT
PP3V3R1V8_ENET_LR_OUT_REG
MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.8V
1
C3972
0.1UF
10%
16V
2
X7R-CERM
0402
ENET_MEDIA_SENSE
SDCONN_DETECT_L
SDCONN_CMD
SDCONN_CLK
SDCONN_DATA<0>
SDCONN_DATA<1>
SDCONN_DATA<2>
SDCONN_DATA<3>
SDCONN_DATA<4>
SDCONN_DATA<5>
SDCONN_DATA<6>
SDCONN_DATA<7>
SDCONN_WP
402
OUT
IN
IN
OUT
BI
BI
BI
BI
BI
BI
BI
BI
IN
36
24
30
30 82
30 82
30 82
30 82
30 82
30 82
30 82
30 82
30 82
30 82
30
12
D
C
B
6
VCC
U3990
AT45DB011D
BCM57765_SCLK
A
36
BCM57765_CS_L
36
4
5
3
SCK
CS*
WP*
RESET*
SOIC-8S1
OMIT
GND
7
SI
SO
1
C3990
0.1UF
10%
16V
2
X7R-CERM
0402
12
8
NOSTUFF
1
R3990
4.7K
5%
1/16W
MF-LF
402
2
BCM57765_MOSI
BCM57765_MISO
1
R3997
4.7K
5%
1/16W
MF-LF
402
2
NOTE: Pull-down on SO plus internal pull-ups on
other 3 SPI pins configures ENET for the
Atmel AT45DB011D (1Mbit) ROM. If a different
ROM is used then the straps must change.
NOTE: ENETM requires SI pull-down instead of SO.
36
36
6 3
SYNC_MASTER=J31_MLB
PAGE TITLE
ETHERNET PHY (CAESAR IV)
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
SYNC_DATE=06/15/2011
DRAWING NUMBER
051-9058
REVISION
6.0.0
BRANCH
PAGE
39 OF 109
SHEET
36 OF 86
124578
SIZE
A
D
8 7 6 5 4 3
Page Notes
Power aliases required by this page:
(NONE)
Signal aliases required by this page:
(NONE)
BOM options provided by this page:
(NONE)
12
D
Place one of 0.1uf cap close to each centertap pin of transformer
D
ENETCONN_CTAP
1/16W
MF-LF
402
1
C4006
0.1UF
10%
16V
2
X5R-CERM
0201
CRITICAL
J4000
RJ45-M97-3
F-RT-TH
9
10
1
2
3
4
5
6
7
8
11
12
514-0636
1
1
R4002
75
75
5%
5%
1/16W
MF-LF
402
2
2
1
R4003
75
5%
1/16W
MF-LF
402
2
ENET_BOB_SMITH_CAP
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm
CRITICAL
C4008
1000PF
10%
2KV
CERM
1206
21
C
B
1
C4000
0.1UF
10%
16V
2
X5R-CERM
0201
OMIT_TABLE
CRITICAL
T4000
ENET_MDI_P<0>
36 82
BI
ENET_MDI_N<0>
36 82
BI
C
ENET_MDI_P<1>
36 82
BI
ENET_MDI_N<1>
36 82
BI
ENET_MDI_P<3>
36 82
BI
ENET_MDI_N<3>
36 82
BI
ENET_MDI_N<2>
36 82
BI
ENET_MDI_P<2>
36 82
BI
Transformers should be
mirrored on opposite
sides of the board
1
2
3
4
5
1
2
3
4
5
SM
TX
TLA-6T213HF
RX
OMIT_TABLE
CRITICAL
T4001
SM
TX
TLA-6T213HF
RX
1
C4002
0.1UF
10%
16V
2
X5R-CERM
0201
12
11
10
9
8
76
12
11
10
9
8
76
B
1
2
ENETCONN_P<0>
85
ENETCONN_N<0>
85
ENET_CTAP0
ENET_CTAP1
ENETCONN_P<1>
85
ENETCONN_N<1>
85
ENETCONN_P<3>
85
ENETCONN_N<3>
85
ENET_CTAP2
ENET_CTAP3
ENETCONN_N<2>
85
ENETCONN_P<2>
85
1
R4000
75
5%
1/16W
MF-LF
402
2
C4004
0.1UF
10%
16V
X5R-CERM
0201
R4001
PART NUMBER
157S0084
QTY
XFMR,ISO,HALF-PORT,1000T,12P,SMD,HF
2
DESCRIPTION
A
6 3
REFERENCE DES
T4000,T4001
CRITICAL
CRITICAL
BOM OPTION
SYNC_MASTER=K90I_MLB SYNC_DATE=02/15/2011
PAGE TITLE
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
Ethernet Connector
Apple Inc.
R
DRAWING NUMBER
051-9058
REVISION
6.0.0
BRANCH
PAGE
40 OF 109
SHEET
37 OF 86
124578
SIZE
A
D
8 7 6 5 4 3
12
21
21
39
=PP3V3_FW_FWPHY
PLACEMENT_NOTE=Place C4170 close to U1400
PLACEMENT_NOTE=Place C4171 close to U1400
C4170
0.1UF
C4171
0.1UF
C4175
0.1UF
C4176
0.1UF
PLACEMENT_NOTE=Place C4175 close to U4100
PLACEMENT_NOTE=Place C4176 close to U4100
FW643_LDO
R4165
1
R4164
10K
5%
1/16W
MF-LF
402
2
7 mA I/O
1
C4120
1UF
10%
6.3V
2
CERM
402
D
L4110
=PP1V0_FW_FWPHY
7
39
135 mA
120-OHM-0.3A-EMI
0402-LF
110 mA Digital Core
1
C4100
2
1UF
10%
6.3V
CERM
402
1
2
21
C4101
1UF
10%
6.3V
CERM
402
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.0V
1
C4102
1UF
10%
6.3V
2
CERM
402
1
C4103
1UF
2
10%
6.3V
CERM
402
1
C4104
1UF
10%
6.3V
2
CERM
402
25 mA PCIe SerDes
1
C4110
1UF
10%
6.3V
2
CERM
402
1
C4105
1UF
10%
6.3V
2
CERM
402
1
C4111
1UF
2
1
C4106
1UF
2
10%
6.3V
CERM
402
10%
6.3V
CERM
402
C4121
1UF
6.3V
CERM
C4130
1UF
6.3V
CERM
1
C4122
10%
2
402
114 mA FireWire PHY
1
C4131
10%
2
402
17 mA PCIe SerDes
C4135
1
1UF
10%
6.3V
2
CERM
402
1
1UF
10%
6.3V
2
CERM
402
1
1UF
10%
6.3V
2
CERM
402
0 mA VReg PWR
C4141
0.1UF
C4123
C4132
C4136
20%
10V
CERM
402
1UF
10%
6.3V
CERM
402
1UF
10%
6.3V
CERM
402
1UF
10%
6.3V
CERM
402
1
2
1
2
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V
1
2
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V
1
2
1
2
1
C4124
1UF
10%
6.3V
2
CERM
402
PP3V3_FW_FWPHY_VDDA
PP3V3_FW_FWPHY_VP25PP1V0_FW_FWPHY_AVDD
C4140
1UF
10%
6.3V
CERM
402
L4130
120-OHM-0.3A-EMI
0402-LF
L4135
120-OHM-0.3A-EMI
0402-LF
C
L9
L6
L5
N11N3M12
MISCELLANEOUS
F8
F7
F10
C1
1394 PHY
G4
G12F1C12
VDD33
G8G7G6
OMIT
CRITICAL
U4100
FW643E
BGA
VSS
H4
G10
L11
H7D7H6
A1
B12
B13
ATBUSB
NC
A13
ATBUSH
NC
A11
ATBUSN
NC
=FW_PHY_DS0
40
IN
=FW_PHY_DS1
40
IN
=FW_PHY_DS2
40
IN
FW_P0_TPA_N
40 82
BI
FW_P0_TPA_P
40 82
BI
FW_P1_TPA_N
40 82
BI
FW_P1_TPA_P
40 82
BI
FW_P2_TPA_N
40
BI
FW_P2_TPA_P
40
BI
FW_P0_TPB_N
40 82
BI
FW_P0_TPB_P
40 82
BI
FW_P1_TPB_N
40 82
BI
FW_P1_TPB_P
40 82
BI
FW_P2_TPB_N
40
=PPVP_FW_PHY_CPS
40
1
R4160
B
C4150
22PF
5%
50V
CERM
0402
C4151
22PF
5%
50V
CERM
0402
21
21
NC
NC
FW_CLK24P576M_XO
CRITICAL
Y4150
24.576MHZ
SM-3.2X2.5MM
42
31
R4150
412
1%
1/16W
MF-LF
402
200K
1%
1/16W
MF-LF
402
2
21
1
1
R4161
2.94K
1/16W
MF-LF
R4162
470K
1/16W
MF-LF
R4170
191
1%
1%
1/16W
MF-LF
402
402
2
2
1
1
C4162
0.33UF
5%
10%
6.3V
2
402
CERM-X5R
402
2
BI
40
BI
40
BI
39 40
BI
40
BI
6
6
6
6
6
FW_P2_TPB_P
FW_P0_TPBIAS
FW_P1_TPBIAS
FW_P2_TPBIAS
FW643_R0
FW643_TPCPS
TP_FW643_NAND_TREE
FW643_REXT
FW_CLK24P576M_XO_R
FW_CLK24P576M_XI
TP_FW643_SE
TP_FW643_SM
TP_FW643_MODE_A
TP_FW643_CE
TP_FW643_FW620_L
TP_FW643_JASI_EN
TP_FW643_AVREG
TP_FW643_VBUF
FW643_PU_RST_L
TP_FW643_OCR10_CTL
F12
DS0
(IPD) NT-2
E12
DS1
(IPD) NT-3
E13
DS2
(IPD) NT-4
B8
TPA0N
A8
TPA0P
B5
TPA1N
A5
TPA1P
B3
TPA2N
A3
TPA2P
B9
TPB0N
A9
TPB0P
B6
TPB1N
A6
TPB1P
B4
TPB2N
A4
TPB2P
B7
TPBIAS0
C3
TPBIAS1
A2
TPBIAS2
B11
R0
B10
TPCPS
K1
NAND_TREE
L8
REXT
F13
XO
G13
XI
NT-9
M13
SE
(IPD)
N13
SM
(IPD)
J2
MODE_A
L13
D12
D1
A10
H13
K13
J12
J13
NC
(IPD) NT-1
CE
(IPD)
FW620*
(IPU)
JASI_EN
(IPD) NT-11
AVREG
VBUF
FW_RESET*
OCR_CTL_V10
OCR_CTL_V12
D4
B2
H12H2E10
C13
VDD10
NT-OUT
NOTE: NT-xx notes show
NAND tree order.
(IPU) NT-8
(Reserved)
D10
F6F4E9E5E4
L1
K2
E2
B1
M2
L3
J1
D8D6D5
A12
VDDH
L10
VP25
VP
PCI EXPRESS PHY
TEST CONTROLLER
FIXME!!! - TYPO IN SYMBOL REGCTL
POWER MANAGEMENT
NT-12 (IPD)
NT-13
SCIF
SERIAL EEPROM
CONTROLLER
CHIP RESET
J9J5J4
H8
J10
H10
VREG_PWR
NT-10 (IPD)
NT-16 (IPD)
NT-14 (IPD)
NT-15 (IPD)
K8D9K7K5K4
K12
PCIE_RXD0N
PCIE_RXD0P
PCIE_TXD0N
PCIE_TXD0P
NT-21 (IPU)
NT-20 (IPU)
NT-18 (IPU)
NT-19 (IPU)
(OD)
VAUX_DETECT
VAUX_DISABLE
(OD)
NT-17
NT-5
VREG_VSS
K6L7K9
K10
REFCLKN
REFCLKP
(IPU)
TRST*
WAKE*
REGCLT
CLKREQN
SCIFCLK
SCIFDAIN
SCIFDOUT
SCIFMC
NT-7
NT-6
PERST*
L12
TCK
TDI
TDO
TMS
SCL
SDA
N8
N7
N5
N6
N9
N10
M4
N2
M1
M3
N1
C2
D13
E1
D2
L2
G2
G1
H1
F2
N12
M11
N4
PCIE_FW_R2D_N
81
PCIE_FW_R2D_P
81
PCIE_FW_D2R_C_N
81
PCIE_FW_D2R_C_P
81
PCIE_CLK100M_FW_N
PCIE_CLK100M_FW_P
TP_FW643_TCK
TP_FW643_TDI
TP_FW643_TDO
TP_FW643_TMS
FW643_TRST_L
=FW_PME_L
FW643_REGCTL
FW643_VAUX_DETECT
TP_FW643_VAUX_ENABLE
=FW_CLKREQ_L
TP_FW643_SCIFCLK
TP_FW643_SCIFDAIN
TP_FW643_SCIFDOUT
TP_FW643_SCIFMC
FW643_SCL
TP_FW643_SDA
FW_RESET_L
1
R4163
10K
5%
1/16W
MF-LF
402
2
16 81
IN
16 81
IN
6
6
6
8
OUT
39
OUT
6
39
IN
7
38 39 40
138 mA
21
PCIE_FW_R2D_C_N
0402
X7R-CERM
16V10%
21
PCIE_FW_R2D_C_P
0402
X7R-CERM
16V10%
21
PCIE_FW_D2R_N
0402
X7R-CERM
16V10%
21
PCIE_FW_D2R_P
0402
X7R-CERM
16V10%
=PP3V3_FW_FWPHY
1
1
R4166
10K
10K
5%
1/16W
MF-LF
5%
1/16W
MF-LF
402
402
2
2
NOTE: FW_PME_L and FW_CLKREQ_L are
isolated for systems that use
1394B physical plug detect.
WITH PLUG DETECT:
- Gate CLKREQ# based on PHY power
- TP (or NC) PME#
WITHOUT PLUG DETECT:
- Alias both signals to drop = prefix
D
C
16 81
IN
16 81
IN
16 81
OUT
16 81
OUT
7
38 39 40
B
A
PAGE TITLE
FireWire LLC/PHY (FW643E)
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
6 3
SYNC_DATE=02/15/2011SYNC_MASTER=K90I_MLB
DRAWING NUMBER
051-9058
REVISION
6.0.0
BRANCH
PAGE
41 OF 109
SHEET
38 OF 86
124578
SIZE
A
D
8 7 6 5 4 3
12
Page Notes
Power aliases required by this page:
- =PPBUS_S5_FWPWRSW (FW VP FET Input)
- =PPBUS_FW_FET (FW VP FET Output)
- =PP3V3_FW_P3V3FWFET (3.3V FET Input)
- =PP3V3_FW_FET (3.3V FET Output)
- =PP3V3_FW_FWPHY (PHY 3.3V Power)
- =PP3V3_S0_FWLATEVG
- =PP3V3_S0_FWPWRCTL
- =PP1V05_S0_FWPWRCTL (5KPD Bias Rail)
- =PP1V05_FW_P1V0FWFET (1.0V FET Input)
- =PP1V0_FW_FET_R (1.0V FET Output)
D
- =PP1V0_FW_FWPHY (PHY 1.0V)
Signal aliases required by this page:
- =FW_CLKREQ_L
- =FW_PME_L
BOM options provided by this page:
(NONE)
C
=PPBUS_S5_FWPWRSW
7
1
R4262
10K
5%
1/16W
MF-LF
402
2
1
R4263
10
5%
1/16W
MF-LF
402
2
=PP3V3_S0_FWLATEVG
7
40
Q4262 provides for fast-off of Q4260 in S0 (Late-VG detection)
4
(SYM-VER2)
SOT-363
S
FWPORT_FASTOFF_L_DIV
5
G
BSS8402DW
Q4262
D
3
FWPORT_FASTOFF_L
6
D
Q4262
BSS8402DW
SOT-363
S
(SYM-VER1)
1
SSM3K15AMFVAPE
Q4261
VESM
1
G S
40
IN
FWPORT_PWR_EN
G
2
1
R4260
300K
5%
1/16W
MF-LF
402
2
FWPORT_PWREN_L_DIV
1
R4261
470K
5%
1/16W
MF-LF
402
2
FWPORT_PWREN_L
3
D
2
FireWire Port Power Switch
CRITICAL
Q4260
FDC638P_G
SM
6
5
2
1
NO STUFF
C4261
0.1UF
C4260
10%
25V
X5R
402
0.1UF
1
2
4
1
10%
25V
2
X5R
402
3
PPBUS_FW_FWPWRSW_F
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
=PP3V3_S0_FWPWRCTL
7
=FW_RESET_L
24
IN
FW_PWR_EN
24 39
IN
FW_CLKREQ_L
16
OUT
Pull-up provided by another page.
CRITICAL
F4260
1.1A-24V
MINISMDC110H24
21
PPBUS_FW_FWPWRSW_D
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=12.6VVOLTAGE=12.6V
CRITICAL
D4260
SM
CRS08-1.5A-30V
Supervisor & CLKREQ# Isolation
2
R4283
10K
5%
1/16W
MF-LF
402
1
FW_RESET_R_L
C4290
0.1UF
1
10%
25V
2
X5R
402
3
MR*
6
EN
8
OUT
(OD)
1
VDD
U4290
SLG4AP016V
TDFN
+
-
DLY
THRM
GND
PAD
5
CRITICAL
SENSE
0.7V
RESET*
IN
9
KA
1
R4290
100K
5%
1/16W
MF-LF
402
2
2
4
FW_RESET_L
DLY = 60 ms +/- 20%
7
=PPBUS_FW_FET
=PP1V0_FW_FWPHY
=FW_CLKREQ_L
FW_CLKREQ_PHY_L
MAKE_BASE=TRUE
7
D
7
38
38
OUT
38
IN
C
=PP1V05_S0_FWPWRCTL
7
FW_PWR_EN
24 39
IN
2
B
A
TEXT NOTE FOR 3.3V RAIL CURRENT CHANGED TO EDP NUMBER.
R4275
1/16W
MF-LF
G
1K
5%
402
1
All FireWire devices require 5K pull-down on TPB pair.
Host can detect as load on TPBIAS signal.
Current source only active when FW_PWR_EN is low.
2
FW_PWR_EN_L
6
CRITICAL
D
Q4275
DMB53D0UV
SOT-563
S
1
FireWire Port 5K Pull-Down Detect
1
R4270
330K
5%
1/16W
MF-LF
402
2
3
CRITICAL
Q4270
BC847CDXV6TXG
SOT563
5
FWDET_MIRROR
4
FW_P1_TPBIAS_R
R4272
PLACE_NEAR=C4360.1:2 mm
FW_P1_TPBIAS
38 40
IN
When PHY is powered, FW_5KPD_DET_L acts as legacy PME# signal.
=FW_PME_L
8
38
IN
1
R4271
56K
5%
1/16W
MF-LF
402
2
FW_5KPD_DET_RC
6
CRITICAL
Q4270
2
BC847CDXV6TXG
SOT563
1
FWDET_EMIT
1/16W
MF-LF
1
1K
5%
402
2
R4273
1/16W
MF-LF
12K
FireWire PHY WAKE# Support
=PP3V3_FW_FWPHY
7
38 40
R4277
10K
5%
1/16W
MF-LF
402
FW643_WAKE_L
8
MAKE_BASE=TRUE
6 3
3.3V FW Switch
U4201
A2
B2
C2
TPS22924
VIN
CRITICAL
ON
CSP
VOUT
GND
C1
C4270
0.1UF
X7R-CERM
=PP3V3_FW_P3V3FWFET
FW_5KPD_DET_L
MAKE_BASE=TRUE
3
CRITICAL
Q4275
5
DMB53D0UV
1
10%
16V
2
0402
4
SOT-563
7
1
C4201
1UF
10%
6.3V
2
CERM
402
1.0V FW Switch
1
5%
402
2
=PP1V05_FW_P1V0FWFET
7
C4202
1UF
1
10%
6.3V
2
CERM
402
A2
B2
C2
U4202
TPS22924
VIN
CRITICAL
ON
CSP
VOUT
GND
C1
A1
B1
MIN_LINE_WIDTH=0.4 mm
A1
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.05V
B1
1
R4202
2
=PP3V3_FW_FET
EDP = 0.14A (85C)
PP1V05_FW_FET
LSI FireWire PHY requires 1.0V.
0.549
1%
1/16W
MF
402
To avoid an extra power supply,
1.05V is used with a series R
to reduce voltage.
=PP1V0_FW_FET_R
7
U4201 & U4202
7
TPS22924C
Load Switch
18 mOhm Typ
50 mOhm Max
Part
Type
R(on)
Max Output: 2A
B
Dual-purpose output:
1) 5K Pull-down Detect when FW_PWR_EN is low.
1
2
2
1
R4276
100K
5%
1/16W
MF-LF
402
2
FW_WAKE
NO STUFF
C4276
0.1UF
X7R-CERM
1
10%
16V
2
0402
6
D
G
CRITICAL
Q4276
DMB53D0UV
S
SOT-563
1
2) FW643 WAKE# (PME#) when PHY is powered.
FW_PME_L
Pull-up provided on another page.
3
CRITICAL
Q4276
5
DMB53D0UV
SOT-563
4
8
19
OUT
PAGE TITLE
FireWire Port & PHY Power
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
SYNC_DATE=06/23/2011SYNC_MASTER=K90I_MLB
DRAWING NUMBER
051-9058
REVISION
6.0.0
BRANCH
PAGE
42 OF 109
SHEET
39 OF 86
SIZE
A
D
124578
8 7 6 5 4 3
12
Page Notes
Power aliases required by this page:
- =PPVP_FW_PORT1
- =PPVP_FW_PHY_CPS_FET (From Port)
- =PPVP_FW_PHY_CPS (To PHY)
- =PP3V3_FW_FWPHY
- =PP3V3_S0_FWLATEVG
Signal aliases required by this page:
- =FW_PHY_DS0
- =FW_PHY_DS1
- =FW_PHY_DS2
D
NOTE: This page is expected to contain
the necessary aliases to map the
FireWire TPA/TPB pairs to their
appropriate connectors and/or to
properly terminate unused signals.
BOM options provided by this page:
(NONE)
1394b implementation based on Apple
FireWire Design Guide (FWDG 0.6, 5/14/03)
C
FW643 TPCPS Leakage Protection
FW643 has internal leakage path from TPCPS pin to VDD33.
FET blocks current to TPCPS until VDD33 is powered.
BSS8402DW
SOT-363
(SYM-VER2)
=PPVP_FW_PHY_CPS_FET
7
From Port
=PP3V3_FW_FWPHY
7
38 39 40
R4311
470K
1/16W
MF-LF
1
5%
402
2
2
4
G
Q4300
SGD
5
CPS_EN_L_DIV
CPS_EN_L
6
D
S
1
3
Q4300
BSS8402DW
SOT-363
(SYM-VER1)
R4312
330K
1/16W
MF-LF
5%
402
MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=12.6V
MAKE_BASE=TRUE
PPVP_FW_CPS
=PPVP_FW_PHY_CPS
1
2
To FW643
Unused FireWire Ports
Disabled per LSI instructions
(All unused port signals TP/NC)
FW_P0_TPBIAS
38
IN
FW_P0_TPA_P
38 82
BI
FW_P0_TPA_N
38 82
BI
FW_P0_TPB_P
38 82
BI
FW_P0_TPB_N
38 82
38
BI
FW_P2_TPBIAS
38
IN
FW_P2_TPA_P
38
BI
FW_P2_TPA_N NC_FW2_TPAN
38
BI
FW_P2_TPB_P
38
BI
FW_P2_TPB_N
38
BI
NC_FW0_TPBIAS
MAKE_BASE=TRUE
NC_FW0_TPAP
MAKE_BASE=TRUE
NC_FW0_TPAN
MAKE_BASE=TRUE
NC_FW0_TPBP
MAKE_BASE=TRUE
NC_FW0_TPBN
MAKE_BASE=TRUE
NC_FW2_TPBIAS
MAKE_BASE=TRUE
NC_FW2_TPAP
MAKE_BASE=TRUE
MAKE_BASE=TRUE
NC_FW2_TPBP
MAKE_BASE=TRUE
NC_FW2_TPBN
MAKE_BASE=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
6
6
6
6
6
6
6
6
Configures PHY for:
- Port "1" Bilingual (1394B)
=PP3V3_FW_FWPHY
7
38 39 40
FireWire PHY Config Straps
1
1/16W
MF-LF
10K
1
R4380
10K
1%
1%
1/16W
MF-LF
402
402
2
2
FWPHY_DS0
MAKE_BASE=TRUE
FWPHY_DS1
MAKE_BASE=TRUE
FWPHY_DS2
MAKE_BASE=TRUE
1
R4381
10K
1%
1/16W
MF-LF
402
2
R4382
=FW_PHY_DS0
=FW_PHY_DS1
=FW_PHY_DS2
38
OUT
38
OUT
38
OUT
D
C
CRITICAL
FERR-250-OHM
1
C4314
0.01UF
10%
50V
2
X7R
402
L4310
SM
C4319
0.1uF
1
R4319
1M
5%
1/16W
MF-LF
402
2
Note: Trace PPVP_FW_PORT1 must handle up to 5A
21
PPVP_FW_PORT1_F
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=33V
(FW_PORT1_TPB_N)
(FW_PORT1_BREF)
(FW_PORT1_TPB_P)
(GND)
(FW_PORT1_TPA_N)
FW_PORT1_AREF
(FW_PORT1_TPA_P)
PLACE_NEAR=J4310.5:2 mm
1
10%
50V
2
X7R
603-1
AREF needs to be isolated from all
local grounds per 1394b spec
When a bilingual device is connected to a
beta-only device, there is no DC path
between them (to avoid ground offset issue)
BREF should be hard-connected to logic
ground for speed signaling and connection
NC
PORT 1
BILINGUAL
CRITICAL
J4310
1394B-M97
F-RT-TH
TPB-
1
9
2
8
7
6
TPA-
3
5
TPA+
4
10
11
12
13
514S0605
CHASSIS
GND
TPB(R)
VPTPB+
SC/NC
VG
TPA(R)
TPB-
TPB<R>
TPB+
VP
NC
VG
TPA-
TPA<R>
TPA+
OUTPUT
B
INPUT
D1+
D1-
D2+
D2-
Cable Power
=PPVP_FW_PORT1
7
8
7
6
5
Termination
Place close to FireWire PHY
FW_P1_TPBIAS
38 39
IN
1
C4360
0.33UF
10%
6.3V
2
CERM-X5R
402
SIGNAL_MODEL=EMPTY
SIGNAL_MODEL=EMPTY
1
R4360
56.2
1%
1/16W
MF-LF
402
FW_P1_TPA_P
38 82
BI
FW_P1_TPA_N
38 82
BI
B
38 82
38 82
BI
BI
FW_P1_TPB_P
FW_P1_TPB_N
2
SIGNAL_MODEL=EMPTY
1
R4362
56.2
1%
1/16W
MF-LF
402
2
FW_PORT1_TPB_C
1
C4364
220PF
5%
25V
2
C0G-CERM
0402
SIGNAL_MODEL=EMPTY
R4361
56.2
1/16W
MF-LF
R4363
56.2
1/16W
MF-LF
R4364
4.99K
1/16W
MF-LF
1
1%
402
2
FW_PORT1_TPA_P
MAKE_BASE=TRUE
FW_PORT1_TPA_N
MAKE_BASE=TRUE
FW_PORT1_TPB_P
MAKE_BASE=TRUE
FW_PORT1_TPB_N
MAKE_BASE=TRUE
1
1%
402
2
1
1%
402
2
"Snapback" & "Late VG" Protection
=PP3V3_S0_FWLATEVG
7
39
TP_FWLATEVG_VCLMP
FWPORT_PWR_EN
39
OUT
(FW_PORT1_TPA_P)
(FW_PORT1_TPA_N)
PLACE_NEAR=U4350.1:2 mm
C4350
0.1UF
X7R-CERM
R4350
100K
5%
1/16W
MF-LF
402
(FW_PORT1_TPB_P)
(FW_PORT1_TPB_N)
1
10%
16V
2
0402
3
VCLMP
4
FWPWR_EN
1
2
12
VCC
U4350
TPD4S1394
LLP
CRITICAL
GND
(PINS 5/6 AND 7/8 ARE
SWAPPED FOR BETTER ROUTING)
A
CANNOT SYNC THIS PAGE FROM T27, TPA AND TPB FOR U4350 IS SWAPPED
6 3
SYNC_MASTER=K90I_MLB SYNC_DATE=02/15/2011
PAGE TITLE
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
FireWire Connector
Apple Inc.
R
DRAWING NUMBER
051-9058
REVISION
6.0.0
BRANCH
PAGE
43 OF 109
SHEET
40 OF 86
124578
SIZE
A
D
D
C
2 1
B
=PP5V_S3_IR
1
R4532
0
2
A
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=5V
1
2
C4537
100UF
20%
10V
X5R-CERM
1206
NOSTUFF
PLACE_NEAR=J4501.7:10MM
PLACE_NEAR=J4501.7:10MM
5%
1/16W
MF-LF
402
PP5V_S3_IR_R
6
C4532
0.1UF
10%
16V
X7R-CERM
0402
8 7 6 5 4 3
C4538
100UF
20%
10V
X5R-CERM
1206
2 1
NOSTUFF
7
44
ODD Power Control
7
Note: 3.3V must be S0 if 5V is S3 or S5 to
ensure the drive is unpowered in S3/S5.
=PP3V3_S0_ODD
7
19
IN
41
SSM6N37FEAPE
ODD_PWR_EN_L
R4597
Q4596
SOT563
5
100K
1/16W
MF-LF
402
1
5%
2
D
SG
SSM6N37FEAPE
ODD_PWR_EN
3
4
SATA HDD Connector (Gen3)
L4500
PP5V_S0_HDD_FLT
6
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.4MM
VOLTAGE=5V
SSD_OOBR2D_L
SSD_OOBD2R_L
SYS_LED_ANODE_R
6
IR_RX_OUT
J4501
54722-0224
F-ST-SM
2
1
43
65
87
9
10
1211
1413
1615
1817
20
19
2221
516S0687
CRITICAL
GND_VOID
GND_VOID
GND_VOID
GND_VOID
FERR-70-OHM-4A
CRITICAL
PLACE_NEAR=J4501.9:6MM
2
C4501
0.1UF
20%
10V
1
CERM
402
PLACE_NEAR=L4500.1:2MM
C4531
0.001UF
X7R-CERM
80
80
80
80
21
0603
R4537
453
L4539
R4531
4.7
1
10%
50V
2
0402
SATA_HDD_D2R_C_P
6
SATA_HDD_D2R_C_N
6
SATA_HDD_R2D_N
6
SATA_HDD_R2D_P
6
=PP5V_S0_HDD
2
C4502
0.1UF
20%
10V
1
CERM
402
PLACE_NEAR=L4500.2:2MM
21
1/16W1%MF-LF
21
5%
D2R Passive DeEmphasis
VALUE: 4.5 DB
R2D Passive DeEmphasis
VALUE: 3.0 DB
=PP5V_S3_ODD
R4596
100K
1/16W
MF-LF
Q4596
SOT563
2
SMC_SSD_OOBR2D_L
402
21
SSD_OOBD2R_FTL_L
FERR-220-OHM
R4536
C4536
C4535
R4535
R4534
C4534
C4533
R4533
0402
SYS_LED_ANODE
MF-LF1/16W
402
68.1
0201
5.0PF
0201
5.0PF
68.1
41.2
15PF
15PF
41.2
1
5%
402
2
ODD_PWR_EN_LS5V_L
6
D
SG
1
7
GND_VOID=TRUE
21
1/20W
MF1%
GND_VOID=TRUE
21
+/-0.1PF
C0G
GND_VOID=TRUE
21
+/-0.1PF
GND_VOID=TRUE
21
1%
1/20W
MF
GND_VOID=TRUE
21
1/20W
MF1%
GND_VOID=TRUE
21
NP0-CERM
5%
25V
0201
GND_VOID=TRUE
21
NP0-CERM
5%
25V
0201
GND_VOID=TRUE
21
MF
1/20W
1%
Q4590
DMP2018LFK
DFN2563-6
2
1
C4595
0.068UF
10%
10V
2
X5R-CERM
0402
R4595
100K
21
7
ODD_PWR_SS
7
41
C4516
0.01UF
C4515
0.01UF
C4511
0.01UF
C4510
0.01UF
5%
1/16W
MF-LF
402
=PP3V3_S0_HDD
1
R4538
100K
5%
1/16W
MF-LF
402
2
46
IN
41
OUT
46
IN
6
44
OUT
201
SATA_HDD_D2R_RC_P
80 85
25V
SATA_HDD_D2R_RC_N
80
25VC0G
201
201
SATA_HDD_R2D_RC_N
80 85
SATA_HDD_R2D_RC_P
80
SATARDRVR_EN
16 23
IN
201
SATARDRVR_I2C_ADDR0
41
IN
SATARDRVR_I2C_ADDR1
41
IN
1
45
=PP1V5_S0_RDRVR
21
10%
21
10%
21
10%
21
10%
6
CRITICAL
PP5V_SW_ODD
6
MIN_LINE_WIDTH=0.6MM
D
S
G
3
C4596
0.01UF
10%
16V
X7R-CERM
0402
=PP3V3_S0_ODD
7
41
SMC_ODD_DETECT
OUT
Note: Indicates disc presence.
SATA Redriver
Internally PD ~150K
Write:0xB6 Read:0xB7
ADDR1
L
L
H
H
R4510
4.7K
1/16W
MF-LF
402
NOSTUFF
GND_VOID=TRUE
0402
X7R-CERM
16V
GND_VOID=TRUE
0402
X7R-CERM
16V
GND_VOID=TRUE
0402
X7R-CERM
16V
GND_VOID=TRUE
0402
X7R-CERM
16V
MIN_NECK_WIDTH=0.4MM
VOLTAGE=5V
4
21
1
R4590
33K
5%
1/16W
MF-LF
402
2
41
ADD0
L
H
L
H
1
5%
2
SATA_HDD_D2R_RDRIN_P
SATA_HDD_D2R_RDRIN_N
85
SATA_HDD_R2D_RDROUT_N
SATA_HDD_R2D_RDROUT_P
85 85
SATARDRVR_I2C_EN_L
SATARDRVR_TEST
1
R4511
0
5%
1/16W
MF-LF
402
2
=PP1V5_S0_RDRVR
7
41
SSD_OOBD2R_FTL_L
IN
Address (R/W)
0x96/0x97
0x98/0x99
0xB6/0xB7
0xB8/0xB9
SATA ODD Connector
J4500
54722-0164
F-ST-SM
2
1
43
65
8 7
9
10
12 11
14 13
16 15
CRITICAL
516S0616
SATA OOB Comparator
Notes:
OOBD2R was OOB_TEMP, from SSD, to SMC
OOBR2D was TEMP_CTL, from SMC, to SSD
=PP3V3_S0_SMC
7
1
R4581
100K
5%
1/16W
MF-LF
402
2
R4582
3.3K
5%
1/16W
MF-LF
402
=PP1V5_S0_RDRVR
7
41
16
6
VDD
U4510
PS8521A
1
A_INP
2
A_INN
4
B_OUTN
5
B_OUTP
7
EN
8
B_PRE0/I2C_ADDR0
9
APRE0/I2C_ADDR1
10
I2C_EN*
18
TEST
GND_VOID
GND_VOID
GND_VOID
GND_VOID
GND
3
TQFN
13
GND_VOID
GND_VOID
GND_VOID
GND_VOID
A_PRE1/SCL_CTL
B_PRE1/SDA_CTL
THRM
PAD
21
338S0907
CRITICAL
6 3
SATA_ODD_R2D_P
6
80
SATA_ODD_R2D_N
6
80
SATA_ODD_D2R_C_N
6
85
SATA_ODD_D2R_C_P
6
85
1
R4583
49.9K
1%
1/16W
MF-LF
402
2
SSD_OOB1V0REF
21
SSD_OOBD2R_R_L
1
R4584
100K
5%
1/16W
MF-LF
402
2
1
C4514
0.1UF
20%
10V
2
CERM
402
PLACE_NEAR=U4510.6:2MM
15
A_OUTP
14
A_OUTN
12
B_INN
11
B_INP
20
REXT
19
17
C4521
C4520
C4526
C4525
3
1
1
C4584
0.1UF
20%
10V
2
CERM
402
1
C4519
0.01UF
20%
16V
2
X7R-CERM
0402
PLACE_NEAR=U4510.16:2MM
SATA_HDD_D2R_RDROUT_P
85
SATA_HDD_D2R_RDROUT_N
85
SATA_HDD_R2D_RDRIN_N
85
SATA_HDD_R2D_RDRIN_P
SATARDRVR_REXT
=SATARDRVR_I2C_SCL
=SATARDRVR_I2C_SDA
0.01UF
0.01UF
0.01UF
0.01UF
5
VCC+
GND
2
41
GND_VOID=TRUE
21
16V
10%
GND_VOID=TRUE
21
16V
10%
GND_VOID=TRUE
21
16V
10%
GND_VOID=TRUE
21
16V
10%
U4580
LMV331
SC70-5
4
SMC_SSD_OOBD2R_R_L
=PP1V5_S0_RDRVR
7
R4513
4.7K
1/16W
MF-LF
402
C4518 & C4517 Placement Note:
It is critical that these two should be near
to U1800 pin AM1 and AM3.
C4518
0.01UF
C4517
0.01UF
C4513
0.01UF
C4512
0.01UF
48
IN
48
BI
1
R4512
3.74K
1%
1/16W
MF-LF
402
2
SATA_ODD_R2D_C_P
0402
X7R-CERM
SATA_ODD_R2D_C_N
0402
X7R-CERM
SATA_ODD_D2R_N
0402
X7R-CERM
SATA_ODD_D2R_P
0402
X7R-CERM
1
C4580
0.1UF
20%
10V
2
CERM
402
PLACE_NEAR=U4580.8:2MM
NO STUFF
1
R4515
4.7K
5%
2
SYNC_MASTER=YONAS_J30
PAGE TITLE
5%
1/16W
MF-LF
402
PLACE_NEAR=U1800.AM1:5MM
GND_VOID=TRUE
21
X7R-CERM
16V
10%
21
X7R-CERM
16V
10%
PLACE_NEAR=U1800.AM3:5MM
GND_VOID=TRUE
PLACE_NEAR=U4510.12:5MM
GND_VOID=TRUE
21
X7R-CERM
16V
10%
21
X7R-CERM
16V
10%
PLACE_NEAR=U4510.11:5MM
GND_VOID=TRUE
1
R4585
1K
5%
1/16W
MF-LF
402
2
R4586
5%
1/16W
MF-LF
402
1
2
SATARDRVR_I2C_ADDR0
SATARDRVR_I2C_ADDR1
SATA_HDD_D2R_P
0402
SATA_HDD_D2R_N
0402
SATA_HDD_R2D_C_N
0402
SATA_HDD_R2D_C_P
0402
0
21
SMC_SSD_OOBD2R_L
SATA/IR/SIL Connectors
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
OUT
OUT
IN
IN
12
16 80
16 80
16 80
16 80
DRAWING NUMBER
REVISION
BRANCH
PAGE
SHEET
124578
051-9058
OUT
41
41
16 80
OUT
16 80
OUT
16 80
IN
16 80
IN
SYNC_DATE=11/08/2011
6.0.0
45 OF 109
41 OF 86
D
C
46
B
A
SIZE
D
8 7 6 5 4 3
12
D
=PP5V_S3_USB
7
USB_EXTA_OC_L
23
OUT
USB_EXTB_OC_L
23
OUT
=USB_PWR_EN
73
1
1
C4690
10UF
6.3V
20%
X5R
603
C4691
0.1UF
20%
10V
2
2
CERM
402
Current limit per port (R4600): 2.18A min / 2.63A max
C
USB Port Power Switch
CRITICAL
U4600
TPS2561DR
SON
CRITICAL
1
C4696
220UF-35MOHM
20%
6.3V
2
POLY-TANT
CASE-B2-SM1
2
3
10
6
4
5
IN_0
IN_1
FAULT1*
FAULT2*
EN1
EN2
GND
1
THRM
PAD
11
OUT1
OUT2
ILIM
9
8
7
USB_ILIM
1
R4600
23.2K
1%
1/16W
MF-LF
402
2
www.qdzbwx.com
C4695
10UF
6.3V
USB Port A (Front Port)
CRITICAL
L4605
PP5V_S3_USB_A_ILIM
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.375 mm
VOLTAGE=5V
1
C4617
20%
2
X5R
603
10UF
6.3V
20%
X5R
603
PP5V_S3_USB_B_ILIM
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.375 mm
VOLTAGE=5V
1
2
43
USB_EXTA_MUXED_N
80
USB_EXTA_MUXED_P
80
C4605
0.01UF
20%
16V
X7R-CERM
0402
GND_VOID=TRUE
CRITICAL
L4610
80OHM-25%-100MA
FERR-120-OHM-3A
1
2
4 3
0504
0603
CRITICAL
L4600
90-OHM-100MA
DLP11S
SYM_VER-1
21
21
PP5V_S3_USB_A_F
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.375 mm
VOLTAGE=5V
6
VBUS
1
GND
RCLAMP0582N
NC
IO
D4600
SLP1210N6
CRITICAL
32 54
NC
IO
USB_EXTA_MUXED_F_N
80
USB_EXTA_MUXED_F_P
80
USB3_EXTA_RX_F_N
80
USB3_EXTA_RX_F_P
80
USB3_EXTA_TX_F_N
80
USB3_EXTA_TX_F_P
80
CRITICAL
J4600
USB-3.0-J30
F-RT-TH
1
VBUS
2
D-
3
D+
4
GND
5
STDA_SSRX-
6
STDA_SSRX+
7
GND_DRAIN
8
STDA_SSTX-
9
STDA_SSTX+
10
11
12
13
14
SHIELD
15
16
17
18
D
C
L2
4
1
GND_VOID=TRUE
CRITICAL
L4620
80OHM-25%-100MA
4
1
ESD3V3U4ULC-IP4292CZ10
0.1UF
10%
X5R
OUT
OUT
6.3V
USB3_EXTA_RX_N
USB3_EXTA_RX_P
USB3_EXTA_TX_C_N
80
21
USB3_EXTA_TX_C_P
80
201
21
6.3V
201
GND_VOID=TRUE
18 80
18 80
C4621
Mojo SMC Debug Mux
=PP3V42_G3H_SMCUSBMUX
7
MOJO:YES
1
C4650
0.1UF
20%
10V
2
CERM
45 46
IN
45 46
OUT
SMC_DEBUGPRT_RX_L
SMC_DEBUGPRT_TX_L
USB_EXTA_P
18 80
BI
USB_EXTA_N
18 80
BI
402
B
5
4
7
6
8
M+
M-
U4650
PI3USB102ZLE
D+
CRITICAL
D-
9
VCC
Y+
Y-
TQFN
MOJO:YES
SELOE*
GND
3
SIGNAL_MODEL=MOJO_MUX
1
2
10
MOJO:NO
R4651
1/16W
MF-LF
MOJO:YES
1
R4650
10K
5%
1/16W
MF-LF
402
2
SMC_DEBUGPRT_EN_L
SEL=0 Choose SMC
SEL=1 Choose USB
0
21
5%
402
MOJO:NO
R4652
0
5%
1/16W
MF-LF
402
21
45
IN
USB3_EXTA_TX_N
18 80
IN
USB3_EXTA_TX_P
18 80
IN
GND_VOID=TRUE
C4620
0.1UF
10%
X5R
3
2
L1
0504
L2
3
2
L1
PGTSLP91-XSON-COMBO
CRITICAL
D4610
B
5
4
2
1
NC
GND
3
987
6
A
6 3
SYNC_MASTER=J31_MLB
PAGE TITLE
External A USB3 Connector
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
SYNC_DATE=07/08/2011
DRAWING NUMBER
051-9058
REVISION
6.0.0
BRANCH
PAGE
46 OF 109
SHEET
42 OF 86
124578
SIZE
A
D
8 7 6 5 4 3
12
D
PP5V_S3_USB_B_ILIM
42
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.375 mm
VOLTAGE=5V
25 80
BI
25 80
BI
USB_EXTB_MUX_N
USB_EXTB_MUX_P
C
OUT
OUT
USB3_EXTB_RX_N
USB3_EXTB_RX_P
18 80
18 80
USB Port B (Back Port)
CRITICAL
L4705
C4705
0.01UF
20%
16V
X7R-CERM
0402
GND_VOID=TRUE
CRITICAL
80OHM-25%-100MA
4
1
1
2
L4710
0504
L2
L1
FERR-120-OHM-3A
4 3
3
2
0603
CRITICAL
L4700
90-OHM-100MA
DLP11S
SYM_VER-1
21
21
PP5V_S3_USB_B_F
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.375 mm
VOLTAGE=5V
NC
6
VBUS
1
GND
D4700
RCLAMP0582N
SLP1210N6
CRITICAL
32 54
NC
IO
CRITICAL
J4700
USB-3.0-J30
F-RT-TH
1
VBUS
USB_EXTB_F_N
80
USB_EXTB_F_P
80
USB3_EXTB_RX_F_N
80
USB3_EXTB_RX_F_P
IO
80
USB3_EXTB_TX_F_N
80
USB3_EXTB_TX_F_P
80
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
DD+
GND
STDA_SSRXSTDA_SSRX+
GND_DRAIN
STDA_SSTXSTDA_SSTX+
SHIELD
D
C
GND_VOID=TRUE
CRITICAL
B
GND_VOID=TRUE
C4720
0.1UF
18 80
IN
18 80
IN
USB3_EXTB_TX_N
USB3_EXTB_TX_P
10%
X5R
21
6.3V
201
GND_VOID=TRUE
C4721
0.1UF
10%
X5R
6.3V
USB3_EXTB_TX_C_N
80
21
USB3_EXTB_TX_C_P
80
201
L4720
80OHM-25%-100MA
4
1
0504
L2
3
2
L1
5
4
2
CRITICAL
1
B
D4710
PGTSLP91-XSON-COMBO
ESD3V3U4ULC-IP4292CZ10
NOTE: Swapped pin4 and 5, pin6 and 7 for layout.
A
6 3
NC
GND
3
987
6
SIZE
A
D
SYNC_MASTER=J31_MLB
PAGE TITLE
External B USB3 Connector
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
SYNC_DATE=07/08/2011
DRAWING NUMBER
051-9058
REVISION
6.0.0
BRANCH
PAGE
47 OF 109
SHEET
43 OF 86
124578
8 7 6 5 4 3
IR SUPPORT
12
D
8
80
BI
8
80
BI
C
=PP5V_S3_IR
7
41
DIFFERENTIAL_PAIR=USB2_TPAD
DIFFERENTIAL_PAIR=USB2_TPAD
1
C4801
0.1UF
2
USB_IR_P
USB_IR_N
IR_VREF_FILTER
1
C4803
1UF
10%
10V
2
X5R
402-1
10%
16V
X7R-CERM
0402
12
P1.0/D+
13
P1.1/D-
15
P1.2/VREG
16
P1.3/SSEL
17
P1.4/SCLK
18
P1.5/SMOSI
19
P1.6/SMISO
8
9
10
20
NC
21
22
23
24
14
VCC
U4800
CY7C63803-LQXC
QFN
CRITICAL
OMIT
P/N 338S0633
THRML
25
P0.0
P0.1
INT0/P0.2
INT1/P0.3
INT2/P0.4
TIO0/P0.5
TIO1/P0.6
VSSPAD
11
7
6
5
4
3
2
1
IR_RX_OUT_RC
1
C4804
0.001UF
10%
50V
2
X7R-CERM
0402
R4800
100
5%
1/16W
MF-LF
402
21
IR_RX_OUT
6
41
IN
D
C
SIZE
B
A
D
B
A
PAGE TITLE
Front Flex Support
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
6 3
SYNC_DATE=02/15/2011SYNC_MASTER=K90I_MLB
DRAWING NUMBER
051-9058
REVISION
6.0.0
BRANCH
PAGE
48 OF 109
SHEET
44 OF 86
124578
8 7 6 5 4 3
12
1UF
10%
10V
X5R
402
D
C
B
D
U4900
LM4FSXAH5BB
BGA
(1 OF 2)
OMIT
T3CCP1/PJ5/C2T3CCP0/PJ4/C2+
AIN00
AIN01
AIN02
AIN03
AIN04
AIN05
AIN06
AIN07
AIN08
AIN09
AIN10
AIN11
AIN12
AIN13
AIN14
AIN15
AIN16
AIN17
AIN18
AIN19
AIN20
AIN21
AIN22
AIN23
PC5/C1+
SSI0CLK/PA2
SSI0FSS/PA3
SSI0RX/PA4
SSI0TX/PA5
U1RX/B0
U1TX/PB1
T0CCP0/PB6
T0CCP1/PB7
SSI1RX/PF0
SSI1TX/PF1
SSI1CLK/PF2
SSI1FSS/PF3
WT0CCP0/PG4
WT0CCP1/PG5
WT2CCP0/PH0
WT2CCP1/PH1
WT3CCP0/PH4
WT3CCP1/PH5
WT4CCP0/PH6
WT4CCP1/PH7
T1CCP0/PJ0
T1CCP1/PJ1
T2CCP0/PJ2
T2CCP1/PJ3
WT5CCP1/PM3
C0C0+
C1-
PF4
PF5
E2
SMC_ADC0
E1
SMC_ADC1
F2
SMC_ADC2
F1
SMC_ADC3
B3
SMC_ADC4
A3
SMC_ADC5
B4
SMC_ADC6
A4
SMC_ADC7
B5
SMC_ADC8
A5
SMC_ADC9
B6
SMC_ADC10
A6
SMC_ADC11
C1
SMC_ADC12
C2
SMC_ADC13
B1
SMC_ADC14
B2
SMC_ADC15
G2
SMC_ADC16
G1
SMC_ADC17
H1
SMC_ADC18
H2
SMC_ADC19
B7
SMC_ADC20
A7
SMC_ADC21
B8
SMC_ADC22
A8
SMC_ADC23
K2
CPU_PROCHOT_L
K1
SMC_VCCIO_CPU_DIV2
L2
SMC_S5_PWRGD_VIN
L1
SPI_DESCRIPTOR_OVERRIDE_L
C5
CPU_CATERR_L
D5
CPU_THRMTRIP_3V3
M2
SMC_PM_G2_EN
M3
PM_DSW_PWRGD
L4
SMC_DELAYED_PWRGD
N1
SMC_PROCHOT
F11
SMC_DEBUGPRT_RX_L
E11
SMC_DEBUGPRT_TX_L
F4
SMC_SYS_LED
F3
SMC_GFX_THROTTLE_L
M9
SPI_SMC_MISO
N9
SPI_SMC_MOSI
L10
SPI_SMC_CLK
K10
SPI_SMC_CS_L
L9
S5_PWRGD
K9
PM_PCH_SYS_PWROK
K7
SMC_DEBUGPRT_EN_L
L7
SMC_GFX_OVERTEMP
K3
ALL_SYS_PWRGD
K4
SMC_THRMTRIP
J3
PM_PWRBTN_L
H4
PM_SYSRST_L
H3
MEM_EVENT_L
G4
SMC_ADAPTER_EN
C9
SMC_OOB1_RX_L
B9
SMC_OOB1_TX_L
A9
SMC_IR_RX_OUT_RC
C8
BDV_BKL_PWM
H10
SMC_BATLOW_L
NC FOR STACK BRD
NC FOR STACK BRD
NC FOR STACK BRD
NC FOR STACK BRD
NC FOR STACK BRD
NC FOR STACK BRD
NC FOR STACK BRD
NC FOR STACK BRD
NC FOR STACK BRD
1.2V FOR ENG PKG
NC FOR STACK BRD
NC FOR STACK BRD
NC FOR STACK BRD
NC FOR STACK BRD
(OD)
NC FOR ENG PKG
NC FOR ENG PKG
NC FOR ENG PKG
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
IN
IN
OUT
OUT
OUT
OUT
IN
OUT
OUT
IN
OUT
OUT
OUT
IN
IN
OUT
IN
IN
OUT
OUT
OUT
BI
OUT
IN
OUT
IN
OUT
OUT
46
46
46
46
46
46
46
46
46
46
46
46
46
46
46
46
46
46
46
46
46
46
46
46
10 46 68 78
46
24
10 78
46
6
73
17
24 35 46
46
42 46
42 46
46
46 81
46 81
46 81
46 81
73
17 23 24
42
46
23 24 73
46
17 23
17 24
27 29 46
17 46 73
46
46
46
46
46 73
=PP3V3_S5_SMC
1
C4902
1UF
20%
10V
2
CERM
603
1
C4903
0.1UF
20%
10V
2
CERM
402
1
C4907
0.1UF
20%
10V
2
CERM
402
7
46
L4901
1
C4904
0.1UF
20%
10V
2
CERM
402
1
C4908
0.1UF
20%
10V
2
CERM
402
1
C4905
0.1UF
20%
10V
2
CERM
402
1
C4909
0.1UF
20%
10V
2
CERM
402
1
C4906
0.1UF
20%
10V
2
CERM
402
1
R4902
1M
5%
1/20W
MF
201
2
SMC_RESET_L
46 47 64
IN
WIFI_EVENT_L
32 46
BI
SMC_WAKE_L
NC_SMC_HIB_L
SMC_CLK32K
46
IN
NC_SMC_XOSC1
SMC_EXTAL
46
SMC_XTAL
46 46
PP1V2_S5_SMC_VDDC
46
MIN_LINE_WIDTH=0.25MM
MIN_NECK_WIDTH=0.1MM
VOLTAGE=1.2V
1
C4910
1UF
10%
25V
2
X5R
402
NOSTUFF
1
C4911
2
1UF
10%
25V
X5R
402
30-OHM-1.7A
(OD)
1
C4912
1UF
10%
25V
2
X5R
402
0402
M10
G13
F10
J10
B11
N13
M12
N10
G12
K12
K13
D7
E6
E8
E9
J7
J9
J1
J6
RST*
PK4/RTCCLK
WAKE*
HIB*
XOSC0
XOSC1
OSC0
OSC1
VBAT
D6
21
PP3V3_S5_SMC_VDDA
MIN_LINE_WIDTH=0.25MM
MIN_NECK_WIDTH=0.1MM
VOLTAGE=3.3V
U4900
LM4FSXAH5BB
BGA
(2 OF 2)
OMIT
VDD
VDDC
1
C4913
0.1UF
20%
10V
2
CERM
402
SWCLK/TCK
SWDIO/TMS
SWO/TDO
VDDA
VREFA+
VREFA-
GNDA
GND
1
C4914
0.1UF
20%
10V
2
CERM
402
TDI
1
C4901
0.1UF
20%
10V
2
CERM
402
C10G10
SMC_TCK
A10
SMC_TMS
A11
SMC_TDO
B10
SMC_TDI
A2
NC
NC
6
46 47
6
46 47
6
46 47
6
46 47
D3
D2
PP3V3_S5_AVREF_SMC
D1
50
49
C3
GND_SMC_AVSS
46
E3
A1
C7
D9
E5
F9
H5
H9
J5
J8
J11
K11
1
C4915
0.1UF
20%
10V
2
CERM
402
1
C4916
0.1UF
20%
10V
2
CERM
402
46
XW4900
1
C4920
0.01UF
10%
10V
2
X5R-CERM
0201
1
C4917
0.1UF
20%
10V
2
CERM
402
2 1
PLACE_NEAR=U4900.A1:4MM
SM
1
C4921
2
NC
NC
B13
LPC0AD0
A13
LPC0AD1
C12
LPC0AD2
D11
LPC0AD3
H12
LPC0CLK
D12
LPC0FRAME*
C13
LPC0RESET*
H13
LPC0SERIRQ
G11
LPC0CLKRUN*
F13
LPC0PD*
F12
LPC0SCI*
B12
PK5
E10
I2C0SCL
D13
I2C0SDA
M4
I2C1SCL
N2
I2C1SDA
N8
I2C2SCL
M8
I2C2SDA
L8
I2C3SCL
K8
I2C3SDA
N7
I2C4SCL
M7
I2C4SDA
N4
I2C5SCL
N3
I2C5SDA
H11
PM6/FAN0PWM0
L13
PM7/FAN0TACH0
C11
PK6/FAN0PWM1
A12
PK7/FAN0TACH1
G3
PN2/FAN0PWM2
D10
PN3/FAN0TACH2
L11
PN4/FAN0PWM3
N12
PN5/FAN0TACH3
N11
PN6/FAN0PWM4
M11
PN7/FAN0TACH4
J4
PH2/FAN0PWM5
J2
PH3/FAN0TACH5
C4
PECI0RX
C6
PECI0TX
M13
PP0/IRQ116
L12
PP1/IRQ117
M5
PP2/IRQ118
J12
PP3/IRQ119
J13
PP4/IRQ120
L5
PP5/IRQ121
D8
PP6/IRQ122
K6
PP7/IRQ123
D4
PQ0/IRQ124
E4
PQ1/IRQ125
F5
PQ2/IRQ126
N5
PQ3/IRQ127
N6
PQ4/IRQ128
K5
PQ5/IRQ129
M6
PQ6/IRQ130
L6
PQ7/IRQ131
L3
U0RX
M1
U0TX
E13
USB0DM
E12
USB0DP
LPC_AD<0>
6
16 47 81
BI
LPC_AD<1>
6
16 47 81
BI
LPC_AD<2>
6
16 47 81
BI
LPC_AD<3>
6
16 47 81
BI
LPC_CLK33M_SMC
24 81
IN
LPC_FRAME_L
6
16 47 81
IN
SMC_LRESET_L
24
IN
LPC_SERIRQ
6
16 47
BI
PM_CLKRUN_L
6
17 47
OUT
LPC_PWRDWN_L
6
17 47
IN
SMC_RUNTIME_SCI_L
19
OUT
SMC_WAKE_SCI_L
46
OUT
SMBUS_SMC_0_S0_SCL
48 84
BI
SMBUS_SMC_0_S0_SDA
48 84
BI
SMBUS_SMC_1_S0_SCL
48 84
BI
SMBUS_SMC_1_S0_SDA
48 84
BI
SMBUS_SMC_2_S3_SCL
6
48 84
BI
SMBUS_SMC_2_S3_SDA
6
48 84
BI
SMBUS_SMC_3_SCL
48 84
BI
SMBUS_SMC_3_SDA
48 84
C
B
BI
SMBUS_SMC_4_ASF_SCL
46
BI
SMBUS_SMC_4_ASF_SDA
46
BI
SMBUS_SMC_5_G3_SCL
6
48 84
BI
SMBUS_SMC_5_G3_SDA
6
48 84
BI
SMC_FAN_0_CTL
52
OUT
SMC_FAN_0_TACH
52
IN
SMC_FAN_1_CTL
46
OUT
SMC_FAN_1_TACH
46
IN
SMC_MPM5_LED_PWR
46
OUT
SMC_MPM5_LED_CHG
46
OUT
SMC_SYS_KBDLED
54
OUT
SMC_T25_EN_L
46
OUT
SYS_TDM_ONEWIRE
46
BI
SYS_ONEWIRE
63
IN
HISIDE_ISENSE_OC
46
IN
SMC_ODD_DETECT
6
41
IN
CPU_PECI_R
46 46
IN BI
SMC_PECI_L
46
OUT
SMC_BIL_BUTTON_L
6
46 63
IN
SMC_DP_HPD_L
46
IN
SMC_PME_S4_WAKE_L
46
IN
SMC_PME_S4_DARK_L
46
IN
SMC_S4_WAKESRC_EN
46 73
OUT
SMC_LID
46 53 63
IN
ENET_ASF_GPIO
46
OUT
SMS_INT_L
55
IN
SMC_BC_ACOK
46 63
IN
G3_POWERON_L
46
IN
PM_SLP_S3_L
6 8
17 26 73
IN
PM_SLP_S4_L
6
17 26 32 73
IN
PM_SLP_S5_L
17 73
IN
SMC_ONOFF_L
46 53
IN
SMC_RX_L
6
46 47
IN
SMC_TX_L
6
46 47
OUT
USB_SMC_N
8
80
BI
USB_SMC_P
8
80
BI
(OD)
(OD)
(OD)
(OD)
(OD)
(OD)
(OD)
(OD)
(OD)
(OD)
NC FOR ENG PKG
NC FOR ENG PKG
(OD)
(OD)
NC FOR STACK BRD
NC FOR STACK BRD
(OD)
NC FOR ENG PKG
(OD)
NOTE:
SMS Interrupt can be active high or low, rename net accordingly.
If SMS interrupt is not used, pull up to SMC rail.
A
NOTE:
Unused pins have "SMC_Pxx" names. Unused
pins designed as outputs can be left floating,
those designated as inputs require pull-ups.
6 3
SYNC_MASTER=YONAS_J30
PAGE TITLE
SMC
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
SYNC_DATE=12/21/2011
DRAWING NUMBER
051-9058
REVISION
6.0.0
BRANCH
PAGE
49 OF 109
SHEET
45 OF 86
124578
SIZE
A
D
8 7 6 5 4 3
12
SMC Reset "Button", Supervisor & AVREF Supply
=PP3V3_S5_SMC
7
45 46
=PPVIN_S5_SMCVREF
7
Desktops: 5V
Mobiles: 3.42V
1
C5020
0.47UF
10%
6.3V
2
CERM-X5R
C5001
0.01UF
X7R-CERM
0402
10%
16V
402
1
2
SMC_TPAD_RST_L
53
D
IN
SMC_ONOFF_L
45 46 53
IN
SMC_MANUAL_RST_L
OMIT
1
R5001
0
5%
1/10W
MF-LF
603
2
SILK_PART=SMC_RST
1
V+
U5010
VREF-3.3V-VDET-3.0V
6
MR1*
(IPU)
MR2*
DELAY
GND
(IPU)
2
SN0903048
CRITICAL
7
4
PLACEMENT_NOTE=Place R5001 on BOTTOM side
MR1* and MR2* must both be low to cause manual reset.
Used on mobiles to support SMC reset via keyboard.
NOTE: Internal pull-ups are to VIN, not V+.
Debug Power "Buttons"
SMC_ONOFF_L
603
1
0
5%
2
OMIT
1
R5015
0
5%
1/10W
MF-LF
603
2
SILK_PART=PWR_BTN
PLACE_SIDE=TOP
OMIT
R5016
1/10W
MF-LF
C
SILK_PART=PWR_BTN
PLACE_SIDE=BOTTOM
45 46 53
OUT
SMC Crystal Circuit
SMC USB Clock require these crystal
values:5,6,8,10,12,16,18,20,24,25 MHz
R5010
2.49K
SMC_XTAL
45
SMC_EXTAL
45
1%
1/20W
MF
201
21
SMC_XTAL_R
12.000MHZ-30PPM-10PF
1
C5010
12PF
5%
50V
2
C0G-CERM
0402
Y5010
3.2X2.5MM-SM
42
NC NC
CRITICAL
31
B
S4 HPD SMC Wake Source
=PP3V3_S4_SMC
1
R5020
100K
5%
1/20W
MF
201
2
CRITICAL
Q5020
A
75
IN
53 45
IN
32
IN
SSM3K15AMFVAPE
DP_A_EXT_HPD
=PSOC_WAKE_L
=BT_WAKE_L
VESM
1
G S
SMC_DP_HPD_L
3
D
=PP3V3_S4_SMC
2
1
R5082
100K
5%
1/20W
MF
201
2
SMC_PME_S4_WAKE_L
MAKE_BASE=TRUE
DFN
3
VIN
RESET*
REFOUT
THRM
PAD
9
5
8
C5025
10uF
20%
6.3V
X5R
603
1
C5011
12PF
5%
50V
2
C0G-CERM
0402
7
46
45
OUT
7
46
OUT
7
1
R5000
100K
5%
1/16W
MF-LF
402
2
SMC_RESET_L
PP3V3_S5_AVREF_SMC
MIN_LINE_WIDTH=0.4MM
MIN_NECK_WIDTH=0.1MM
VOLTAGE=3.3V
1
1
C5026
0.01UF
10%
16V
2
2
X7R-CERM
0402
GND_SMC_AVSS
MIN_LINE_WIDTH=0.4MM
MIN_NECK_WIDTH=0.1MM
VOLTAGE=0V
Note:
ADC10 and ADC11 are shared
with comparators on Stack Board.
Note:
Pull-up for SMC_PME_S4_DARK_L
are in page33 (R3315).
45 49 50
45 47 64
OUT
45
17
IN
System (Sleep) LED Circuit
=PP5V_S3_SYSLED
1
523
201
1%
MF
2
1
R5030
20
1%
1/16W
MF-LF
402
2
SYS_LED_ILIM
R5031
1/20W
SYS_LED_L_VDIV
1
R5032
1.47K
1%
1/20W
MF
201
2
SYS_LED_L
SMC_SYS_LED
45
IN
6 3
SMC_ADC0
45
SMC_ADC1
45
SMC_ADC2
45
SMC_ADC3
45
SMC_ADC4
45
SMC_ADC5
45
SMC_ADC6
45
SMC_ADC7
45
SMC_ADC8
45 50
SMC_ADC9
45
SMC_ADC10
45
SMC_ADC11
45
SMC_ADC12
45
SMC_ADC13
45
SMC_ADC14
45
SMC_ADC15
45
SMC_ADC16
45
SMC_ADC17
45
SMC_ADC18
45
SMC_ADC19
45
SMC_ADC20
45
SMC_ADC21
45
SMC_ADC22
45
SMC_ADC23
45 46
SMC_GFX_OVERTEMP
45
SMC_GFX_THROTTLE_L
45
SMC_FAN_1_CTL
45
SMC_FAN_1_TACH
45
ENET_ASF_GPIO
45
SMC_MPM5_LED_PWR
45
SMC_MPM5_LED_CHG
45
SYS_TDM_ONEWIRE
45
SMC_OOB1_RX_L
45
SMC_OOB1_TX_L
45
=CHGR_ACOK
50 64
HISIDE_ISENSE_OC
45
SMBUS_SMC_4_ASF_SCL
45
SMBUS_SMC_4_ASF_SDA
45
BDV_BKL_PWM
45
SMC_PME_S4_DARK_L
45
SMC_SCI_L
19
SMC_T25_EN_L
45
SMC_IR_RX_OUT_RC
45
PM_CLK32K_SUSCLK_R
PLACE_NEAR=U1800.N14:5MM
5
BD
Q1
GS
1 2463
E
Q2
C
CRITICAL
Q5030
DMB54D0UV
SOT-563
SYS_LED_ANODE
SMC_CPU_VSENSE
MAKE_BASE=TRUE
SMC_CPU_ISENSE
MAKE_BASE=TRUE
NC_SMC_ADC2
MAKE_BASE=TRUE
SMC_DCIN_VSENSE
MAKE_BASE=TRUE
SMC_DCIN_ISENSE
MAKE_BASE=TRUE
SMC_PBUS_VSENSE
MAKE_BASE=TRUE
SMC_HDD_ISENSE
MAKE_BASE=TRUE
SMC_BMON_ISENSE
MAKE_BASE=TRUE
SMC_CPU_HI_ISENSE
MAKE_BASE=TRUE
SMC_OTHER_HI_ISENSE
MAKE_BASE=TRUE
SMC_MEM_ISENSE
MAKE_BASE=TRUE
SMC_CPUVCCIO_ISENSE
MAKE_BASE=TRUE
SMC_AXG_VSENSE
MAKE_BASE=TRUE
NC_SMC_ADC13
MAKE_BASE=TRUE
NC_SMC_ADC14
MAKE_BASE=TRUE
NC_SMC_ADC15
MAKE_BASE=TRUE
NC_SMC_ADC16
MAKE_BASE=TRUE
NC_SCM_ADC17
MAKE_BASE=TRUE
SMC_AXG_ISENSE
MAKE_BASE=TRUE
NC_SMC_ADC19
MAKE_BASE=TRUE
NC_SMC_ADC20
MAKE_BASE=TRUE
NC_SMC_ADC21
MAKE_BASE=TRUE
NC_SMC_ADC22
MAKE_BASE=TRUE
SMC_ADC23
MAKE_BASE=TRUE
NC_SMC_GFX_OVERTEMP
MAKE_BASE=TRUE
NC_SMC_GFX_THROTTLE_L
MAKE_BASE=TRUE
NC_SMC_FAN_1_CTL
MAKE_BASE=TRUE
NC_SMC_FAN_1_TACH
MAKE_BASE=TRUE
NC_ENET_ASF_GPIO
MAKE_BASE=TRUE
NC_SMC_MPM5_LED_PWR
MAKE_BASE=TRUE
NC_SMC_MPM5_LED_CHG
MAKE_BASE=TRUE
NC_SYS_TDM_ONEWIRE
MAKE_BASE=TRUE
SMC_SSD_OOBD2R_L
MAKE_BASE=TRUE
SMC_SSD_OOBR2D_L
MAKE_BASE=TRUE
SMC_BC_ACOK
MAKE_BASE=TRUE
NC_HISIDE_ISENSE_OC
MAKE_BASE=TRUE
NC_SMBUS_SMC_4_ASF_SCL
MAKE_BASE=TRUE
NC_SMBUS_SMC_4_ASF_SDA
MAKE_BASE=TRUE
NC_BDV_BKL_PWM
MAKE_BASE=TRUE
SDCONN_STATE_CHANGE_SMC
MAKE_BASE=TRUE
SMC_WAKE_SCI_L
MAKE_BASE=TRUE
NC_SMC_T25_EN_L
MAKE_BASE=TRUE
NC_SMC_IR_RX_OUT_RC
MAKE_BASE=TRUE
R5012
22
21
SMC_CLK32K
5%
1/20W
OUT
201MF
7
45 73 17
IN
41
49
49
50
50
50
49
50
50
49
49
49
49
45 46
41
41
45 46 63
CPU_PROCHOT_L
10 45 68 78
BI
PM_THRMTRIP_L_R
19
OUT
CPU_THRMTRIP_3V3
45 46
OUT
SCM12 Eng Pkg Support
24 30
45
45
OUT
BATLOW# Isolation
=PP3V3_S5_SMCBATLOW
R5040
SMC_BATLOW_L
Q5058
MMBT3904LP-7
DFN1006-3
CRITICAL
PP1V2_S5_SMC_VDDC
45
SMC_ADC23
45 46
=PPVCCIO_S0_SMC
7
46
SMC_VCCIO_CPU_DIV2
45
1
100K
1/20W
201
5%
MF
SSM3K15AMFVAPE
2
6
D
S G
1
3
D
S G
4
3
2
CRITICAL
Q5040
VESM
D
3
R5041
1/16W
MF-LF
Q5059
SSM6N15AFE
SOT563
CRITICAL
2
SMC_PROCHOT
Q5059
SSM6N15AFE
SOT563
CRITICAL
5
SMC_THRMTRIP
1
PM_THRMTRIP_B_L
SMC_PACKAGE:ENG
1
GS
2
0
21
5%
NOSTUFF
402
IN
IN
R5058
3.3K
5%
1/16W
MF-LF
402
1
R5099
0
5%
1/16W
MF-LF
402
2
1
R5097
100K
1%
1/16W
MF-LF
402
2
1
R5096
100K
1%
1/16W
MF-LF
402
2
=PP3V3_SUS_SMC
PM_BATLOW_L
Internal 20K pull-up on
PM_BATLOW_L in PCH.
SMC12 PECI Support
45
45
45 46
21
SMC_PECI_L
IN
From SMC.
PM_THRMTRIP_L
R5052
5%
1/16W
MF-LF
402
OUT
To SMC.
IN
0
21
CPU_PECI_R
10 19 78
SMC12 SPI Support
Series resistors are no stuffed until the
topology of 2 SPI Masters are verified.
45 81
45 81
45 81
45 81
Notes:
OOBD2R was OOB_TEMP, from SSD, to SMC
OOBR2D was TEMP_CTL, from SMC, to SSD
7
OUT
SPI_SMC_MISO
IN
SPI_SMC_MOSI
IN
SPI_SMC_CLK
IN
SPI_SMC_CS_L
IN
SMC_ONOFF_L
45 46 53
G3_POWERON_L
45
SMC_LID
45 53 63
SMC_TX_L
6
45 47
SMC_RX_L
6
45 47
SMC_DEBUGPRT_TX_L
42 45
SMC_DEBUGPRT_RX_L
42 45
SMC_TMS
6
45 47
SMC_TDO
6
45 47
SMC_TDI
6
45 47
SMC_TCK
6
45 47
SMC_BIL_BUTTON_L
6
45 63
SMC_BC_ACOK
45 46 63
SMC_S5_PWRGD_VIN
45
MEM_EVENT_L
27 29 45
CPU_THRMTRIP_3V3
45 46
SMC_ROMBOOT
47
SMC_THRMTRIP
45 46
SMC_ADAPTER_EN
17 45 73
SMC_DELAYED_PWRGD
24 35 45
SMC_S4_WAKESRC_EN
45 73
WIFI_EVENT_L
32 45
NO STUFF
NO STUFF
R5022
R5024
1
2
SYNC_MASTER=YONAS_J30
PAGE TITLE
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
CRITICAL
Q5050
SSM3K15AMFVAPE
SMC_PECI_L_R
1
2
R5021
0
21
5%
402
0
21
5%
402
R5070
R5072
R5071
R5073
R5074
R5075
R5076
R5077
R5078
R5079
R5080
R5081
R5087
R5092
R5014
R5017
R5023
100K
100K
100K
470K
100K
100K
1/16W
MF-LF
1/16W
MF-LF
R5088
1K
5%
1/20W
MF
201
R5086
R5085
R5091
R5090
100K
100K
R5089
SMC Support
Apple Inc.
R
VESM
1
R5053
1.6K
5%
1/16W
MF-LF
402
NOSTUFF
R5054
43
5%
1/16W
MF-LF
402
0
5%
1/16W
MF-LF
402
0
5%
1/16W
MF-LF
402
10K
10K
10K
10K
10K
10K
10K
10K
10K
10K
10K
10K
10K
G S
21
21
=PPVCCIO_S0_SMC
3
D
2
1
R5051
330
5%
1/16W
MF-LF
402
2
21
CPU_PECI
From/To CPU/PCH.
NO STUFF
SPI_MLB_MISO
PLACE_NEAR=U6100.2:1MM
SPI_MLB_MOSI
PLACE_NEAR=U6100.5:1MM
NO STUFF
SPI_MLB_CLK
PLACE_NEAR=U6100.6:1MM
SPI_MLB_CS_L
PLACE_NEAR=U6100.1:1MM
=PP3V3_S5_SMC
7
45 46
21
5%
21
5% 201MF
21
5%
21
5%
21
5%
21
5%
21
5% 201MF
21
5%
21
5%
21
5%
21
5%
21
5%
21
5% 201
21
5% 201MF
21
5% MF 201
21
5%
21
5%
21
5%
21
5%
21
5%
PP3V3_WLAN
6
32
21
5%
BI
1/20W
MF 201
1/20W
1/20W
1/20W
1/20W
1/20W
1/20W
1/20W
1/20W
1/20W
1/20W
1/20W
1/20W
1/20W
1/20W
1/20W
1/20W
1/20W
1/20W
1/20W
1/20W
201MF
201MF
201MF
MF 201
MF 201
201MF
201MF
201MF
201MF
MF
MF 201
201MF
MF
201
MF 201
201MF
201MF
SYNC_DATE=01/02/2012
DRAWING NUMBER
051-9058
REVISION
6.0.0
BRANCH
PAGE
50 OF 109
SHEET
46 OF 86
124578
7
46
D
10 19 78 45
47 56 81
OUT
OUT
OUT
OUT
C
47 56 81
47 56 81
47 56 81
B
A
SIZE
D
8 7 6 5 4 3
12
D
=PP3V3_S5_LPCPLUS
7
=PP5V_S0_LPCPLUS
7
LPC_AD<0>
6
16 45 81
BI
LPC_AD<1>
6
16 45 81
BI
SPI_ALT_MOSI
6
47
IN
SPI_ALT_MISO
6
47
OUT
LPC_FRAME_L
6
16 45 81
IN
PM_CLKRUN_L
6
17 45
OUT
SMC_TMS
6
45 46
OUT
LPCPLUS_RESET_L
6
24
IN
SMC_TDO
6
45 46
OUT
TP_SMC_TRST_L
TP_SMC_MD1
SMC_TX_L
6
45 46
IN
C
LPC+SPI Connector
CRITICAL
LPCPLUS_CONN:YES
J5100
55909-0374
M-ST-SM
31
32
2
1
4
3
6
5
8
7
10
9
12
11
14
13
16
15
18
17
20
19
22
21
24
23
26
25
28
27
30
29
33
34
LPC_CLK33M_LPCPLUS
LPC_AD<2>
LPC_AD<3>
SPIROM_USE_MLB
SPI_ALT_CLK
SPI_ALT_CS_L
LPC_SERIRQ
LPC_PWRDWN_L
SMC_TDI
SMC_TCK
SMC_RESET_L
SMC_ROMBOOT
SMC_RX_L
LPCPLUS_GPIO
6
24 81
IN
6
16 45 81
BI
6
16 45 81
BI
6
19 56
OUT
6
47
IN
6
47
IN
6
16 45
BI
6
17 45
IN
6
45 46
OUT
6
45 46
OUT
45 46 64
OUT
46
OUT
6
45 46
OUT
6
19
OUT
D
C
516S0573
SPI Bus Series Termination
SPI_ALT_MISO
SPI_ALT_MOSI
SPI_ALT_CLK
47
21
5%
PLACE_NEAR=R5125.2:5mm
1/16W
MF-LF
402
SPI_ALT_CS_L
PLACE_NEAR=J5100.14:5mm
PLACE_NEAR=J5100.12:5mm
PLACE_NEAR=J5100.9:5mm
PLACE_NEAR=J5100.11:5mm
SPI_MLB_CS_L
SPI_MLB_CLK
SPI_MLB_MOSI
SPI_MLB_MISO
47
21
5%
PLACE_NEAR=R5127.2:5mm
1/16W
MF-LF
402
LPCPLUS_R:YES
1
R5126
47
5%
1/16W
MF-LF
402
2
R5121
47
5%
1/16W
MF-LF
402
21
LPCPLUS_R:YES
1
R5125
47
5%
1/16W
MF-LF
402
2
R5120
PLACE_NEAR=R5126.2:5mm
R5123
15
5%
1/16W
MF-LF
402
21
LPCPLUS_R:YES
1
R5127
47
5%
1/16W
MF-LF
402
2
R5122
PLACE_NEAR=U6100.2:5mm
LPCPLUS_R:YES
1
R5128
0
5%
1/16W
MF-LF
402
2
SPI_CS0_R_L
16 81
IN
B
16 81
PLACE_NEAR=U1800.AY1:5mm
16 81
16 81
IN
IN
OUT
PLACE_NEAR=U1800.BA2:5mm
SPI_CLK_R
SPI_MOSI_R
SPI_MISO
PLACE_NEAR=U1800.AV3:5mm
R5112
15
21
5%
1/16W
MF-LF
402
R5111
15
1/16W
MF-LF
402
R5110
15
21
SPI_CS0_L
81
5%
1/16W
MF-LF
402
21
5%
SPI_CLK
81
SPI_MOSI
81
6
47
6
47
6
47
6
47
46 56 81
OUT
46 56 81
OUT
46 56 81
OUT
46 56 81
IN
B
A
6 3
SYNC_MASTER=J31_MLB
PAGE TITLE
LPC+SPI Debug Connector
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
SYNC_DATE=06/15/2011
DRAWING NUMBER
051-9058
REVISION
6.0.0
BRANCH
PAGE
51 OF 109
SHEET
47 OF 86
124578
SIZE
A
D
8 7 6 5 4 3
12
PCH SMBus "0" Connections
=PP3V3_S0_SMBUS_PCH
7
48
1
1
Cougar-Point
U1800
(MASTER)
SMBUS_PCH_CLK
16 81
D
MAKE_BASE=TRUE
SMBUS_PCH_DATA
16 81
MAKE_BASE=TRUE
R5200
1/16W
MF-LF
VRef DACs
(Write: 0x98 Read: 0x99)
U3400
=I2C_VREFDACS_SCL
31
=I2C_VREFDACS_SDA
31
Margin Control
(Write: 0x30 Read: 0x31)
U3401
=I2C_PCA9557D_SCL
31
=I2C_PCA9557D_SDA
31
R5201
1K
1K
5%
5%
1/16W
MF-LF
402
402
2
2
SO-DIMM "A"
(Write: 0xA0 Read: 0xA1)
J2900
=I2C_SODIMMA_SCL
=I2C_SODIMMA_SDA
SO-DIMM "B"
(Write: 0xA4 Read: 0xA5)
J3100
=I2C_SODIMMB_SCL
=I2C_SODIMMB_SDA
LED BACKLIGHT
U9701
(WRITE: 0x58 READ: 0x59)
=I2C_BKL_1_SCL
=I2C_BKL_1_SDA
SMC
U4900
(MASTER)
27
27
29
29
77
77
SMBUS_SMC_0_S0_SCL
45 84
MAKE_BASE=TRUE
SMBUS_SMC_0_S0_SDA
45 84
MAKE_BASE=TRUE
SMC "0" SMBus Connections
=PP3V3_S0_SMBUS_SMC_0_S0
7
R5250
4.7K
1/16W
MF-LF
1
1
R5251
4.7K
5%
5%
1/16W
MF-LF
402
402
2
2
45 84
45 84
SMC
U4900
(MASTER)
SMBUS_SMC_5_G3_SCL
6
MAKE_BASE=TRUE
SMBUS_SMC_5_G3_SDA
6
MAKE_BASE=TRUE
Battery
Battery Manager - (Write: 0x16 Read: 0x17)
Battery LED Driver - (Write: 0x36 Read: 0x37)
Battery Temp - (Write: 0x90 Read: 0x91)
X19
(Write: 0x90 Read: 0x91)
=AP_TEMP_SMB_SCL
=AP_TEMP_SMB_SDA
32
32
SMC
Mikey
C
XDP Connectors
J2500 & J2550
(MASTER)
=SMBUS_XDP_SCL
23
=SMBUS_XDP_SDA
23
(Write: 0x72 Read: 0x73)
=I2C_MIKEY_SCL
=I2C_MIKEY_SDA
(Write: 0xB6 Read: 0xB7)
=SATARDRVR_I2C_SCL
=SATARDRVR_I2C_SDA
U6880
SATA_Redriver
U4510
58 62
58 62
SMC
U4900
41
41
(MASTER)
SMBUS_SMC_2_S3_SCL
6
45 84
MAKE_BASE=TRUE
SMBUS_SMC_2_S3_SDA
6
45 84
MAKE_BASE=TRUE
SMC "2" SMBus Connections
NOTE: SMC RMT bus remains powered and may be active in S3 state
=PP3V3_S3_SMBUS_SMC_A_S3
7
R5270
1/16W
MF-LF
1
1
R5271
1K
1K
5%
5%
1/16W
MF-LF
402
402
2
2
Trackpad
(Write: 0x90 Read: 0x91)
=I2C_TPAD_SCL
=I2C_TPAD_SDA
J5800
54
54
U4900
(MASTER)
SMBUS_SMC_3_SCL
45 84
SMBUS_SMC_3_SDA
45 84
SMC "5" SMBus Connections
=PP3V42_G3H_SMBUS_SMC_BSA
7
1
R5280
2.0K
5%
1/16W
MF-LF
402
2
SMC "3" SMBus Connections
=PP3V3_S3_SMBUS_SMC_MGMT
7
NO STUFF
1
R5290
4.7K
5%
1/16W
MF-LF
402
2
T29 I2C Connections
1
R5281
2.0K
5%
1/16W
MF-LF
402
2
NO STUFF
1
R5291
4.7K
5%
1/16W
MF-LF
402
2
Battery Charger
ISL6258 - U7000
(Write: 0x12 Read: 0x13)
=SMBUS_CHGR_SCL
=SMBUS_CHGR_SDA
Battery
J6955
(See Table)
=SMBUS_BATT_SCL
=SMBUS_BATT_SDA
64
64
63
63
D
C
B
Cougar-Point
SML_PCH_0_CLK
16 81
MAKE_BASE=TRUE
SML_PCH_0_DATA
16 81
MAKE_BASE=TRUE
Cougar-Point
A
(Write: 0x88 Read: 0x89)
SML_PCH_1_CLK
16 81
SML_PCH_1_DATA
16 81
SMLink 1 is slave port to
access PCH & CPU via PECI.
U1800
(MASTER)
U1800
PCH "SMLink 0" Connections
=PP3V3_S0_SMBUS_PCH
7
48
1
8.2K
1/16W
MF-LF
1
R5211
8.2K
5%
5%
1/16W
MF-LF
402
402
2
2
R5210
PCH "SMLink 1" Connections
ALS
(Write: 0x72 Read: 0x73)
=I2C_ALS_SCL
=I2C_ALS_SDA
J3502
32
32
Digital SMS
LIS331DLH: U5920
(Write: 0x30 Read: 0x31)
=I2C_SMC_SMS_SCL
=I2C_SMC_SMS_SDA
55
55
R5236
U4900
(MASTER)
SMBUS_SMC_1_S0_SCL
45 84
MAKE_BASE=TRUE
SMBUS_SMC_1_S0_SDA
45 84
MAKE_BASE=TRUE
SMC "1" SMBus Connections
=PP3V3_S0_SMBUS_SMC_B_S0
7
R5260
4.7K
1/16W
MF-LF
1
1
R5261
4.7K
5%
5%
1/16W
MF-LF
402
402
2
2
CPU TempSMC
EMC1414: U5511
(Write: 0x98 Read: 0x99)
=I2C_CPUTHMSNS_SCL
=I2C_CPUTHMSNS_SDA
51
51
R5237
6 3
7
T29 IC
U3600
(MASTER)
I2C_T29_SDA
33 83
MAKE_BASE=TRUE
I2C_T29_SCL
33 83
MAKE_BASE=TRUE
For Compliance Testing
SDRVI2C:SB
0
SDRVI2C:SB
0
21
5%
MF
21
5%
MF
=PP3V3_S0_T29I2C
201
201
I2C_DPSDRVA_SCL
MAKE_BASE=TRUE
I2C_DPSDRVA_SDA
MAKE_BASE=TRUE
1/20W
1/20W
Microcontroller abstracts
R5230
4.7K
1/16W
MF-LF
SDRVI2C:MCU
R5234
1/20W
SYNC_MASTER=K90I_MLB
PAGE TITLE
201
1
5%
402
2
1
0
5%
MF
2
actual CDR(s) in plug.
1
R5231
4.7K
5%
1/16W
MF-LF
402
2
SDRVI2C:MCU
1
R5235
0
5%
1/20W
MF
201
2
SMBus Connections
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
T29 Plug uC
(Write: 0x26 Read: 0x27)
U9330
=I2C_T29AMCU_SDA
=I2C_T29AMCU_SCL
DP Re-driver
U9310
(Write: 0x94 Read: 0x95)
=I2C_DPSDRVA_SCL
=I2C_DPSDRVA_SDA
SYNC_DATE=02/15/2011
DRAWING NUMBER
051-9058
REVISION
6.0.0
BRANCH
PAGE
52 OF 109
SHEET
48 OF 86
124578
75
B
75
75
75
A
SIZE
D
8 7 6 5 4 3
CPU VCCIO 1.05V Load Side Current Sense (IC1C)
Gain: 100x, EDP: 20.1 A
Rsense: 0.001 (R7640)
V across Rsense: 20.1 mV
Gain needed: 164.2x
=PP3V3_S0_ISNS
7
3
D
CPUVCCIOS0_CS_N
IN
PLACE_NEAR=R7640.3:5MM
CPUVCCIOS0_CS_P
70 85
IN
PLACE_NEAR=R7640.4:5MM
DDR 1.5V S3 (Memory) Current Sense (IM0C)
Gain: 364.9x, EDP: 9 A
Rsense: 0.001 (R5370)
V across Rsense: 9 mV
Gain needed: 366.6x
=PP1V5_S3_DDR_ISNS_R
7
IN
1
R5370
0.001
1%
1W
MF-1
0612
0.001
MF-1
0612
432
85
1
1%
1W
432
85
C
=PP1V5_S3_DDR_ISNS
7
OUT
=PP5V_S0_HDD_ISNS_R
7
IN
HDD Current Sense (IHDC)
Gain: 1000x, EDP: 2.5 A (12.5 W)
Rsense: 0.001 (R5380)
V across Rsense: 2.5 mV
Gain needed: 1320x
R5380
=PP5V_S0_HDD_ISNS
7
OUT
5
4
LOADISNS:YES
CRITICAL
ISNS_1V5_S3_DDR_P
ISNS_1V5_S3_DDR_N
ISNS_5V_S0_HDD_P
ISNS_5V_S0_HDD_N
V+
U5360
INA214
SC70
IN-
IN+ REF
GND
2
R5371
2.74K
R5372
2.74K
R5381
R5382
B
OUT
1/16W
MF-LF
402
1/16W
MF-LF
402
1K
1/20W
201
1K
1/20W
201
6
1
21
85
1%
21
85
1%
21
85
1%
MF
21
85
1%
MF
1
C5360
0.1uF
20%
10V
2
CERM
402
LOADISNS:YES
CPUVCCIO_IOUT
LOADISNS:YES
PLACE_NEAR=U4900.A6:5MM
=PP3V3_S3_ISNS
7
ISNS_1V5_S3_DDR_R_P
ISNS_1V5_S3_DDR_R_N
1
R5373
1M
1%
1/16W
MF-LF
402
2
=PP5V_S0_ISNS
7
ISNS_5V_S0_HDD_R_P
ISNS_5V_S0_HDD_R_N
1
R5383
1M
1%
1/16W
MF-LF
402
2
R5369
4.53K
1%
1/16W
MF-LF
402
1
+IN
3
-IN
R5374
1/16W
MF-LF
1
+IN
3
-IN
R5384
1/16W
MF-LF
21
SMC_CPUVCCIO_ISENSE
1
C5369
0.22UF
20%
6.3V
2
X5R
402
GND_SMC_AVSS
CRITICAL
U5370
OPA330
5
SC70-5
V+
4
ISNS_1V5_S3_DDR_IOUT
V-
2
1M
21
1%
402
CRITICAL
U5380
OPA330
5
SC70-5
V+
4
ISNS_5V_S0_HDD_IOUT
V-
2
1M
21
1%
402
LOADISNS:YES
PLACE_NEAR=U4900.A6:5MM
PLACE_NEAR=U5370.5:3MM
1
C5370
0.1UF
20%
10V
2
CERM
402
R5379
4.53K
1/16W
PLACE_NEAR=U4900.B6:5MM
PLACE_NEAR=U4900.B4:5MM
MF-LF
PLACE_NEAR=U5380.5:3MM
1
C5380
0.1UF
20%
10V
2
CERM
402
R5389
4.53K
1/16W
MF-LF
OUT
1%
402
1%
402
46 70 85
45 46 49 50
21
21
SMC_MEM_ISENSE
1
C5379
0.22UF
20%
6.3V
2
X5R
402
PLACE_NEAR=U4900.B6:5MM
GND_SMC_AVSS
SMC_HDD_ISENSE
1
C5389
0.22UF
20%
6.3V
2
X5R
402
PLACE_NEAR=U4900.B4:5MM
GND_SMC_AVSS
OUT
OUT
46
45 46 49 50
46
45 46 49 50
CPUIMVP_ISNS1_P
68 69 85
IN
PLACE_NEAR=R7510.4:5MM
LOADISNS:YES
CPUIMVP_ISNS2_P
68 69 85
IN
PLACE_NEAR=R7520.3:5MM
LOADISNS:YES
CPUIMVP_ISNS1_N
69 85
IN
PLACE_NEAR=R7510.3:5MM
LOADISNS:YES
CPUIMVP_ISNS2_N
69 85
IN
PLACE_NEAR=R7520.4:5MM
LOADISNS:YES
CPUIMVP_ISNS1G_P
69 85
IN
PLACE_NEAR=R7550.3:5MM
LOADISNS:YES
CPUIMVP_ISNS2G_P
69 85
IN
PLACE_NEAR=R7560.3:5MM
LOADISNS:YES
CPUIMVP_ISNS1G_N
69 85
IN
PLACE_NEAR=R7550.4:5MM
LOADISNS:YES
CPUIMVP_ISNS2G_N
69 85
IN
PLACE_NEAR=R7560.4:5MM
LOADISNS:YES
CPU Core Voltage Sense (VC0C)
=PPCPUVCORE_S0_VSENSE
7
PLACE_NEAR=R7510.2:5 MM
XW5320
SM
21
CPUVSENSE_IN
PLACE_NEAR=U4900.E2:5MM
R5329
4.53K
21
1%
1/16W
MF-LF
402
SMC_CPU_VSENSE
PLACE_NEAR=U4900.E2:5MM
1
C5329
0.22UF
20%
6.3V
2
X5R
402
GND_SMC_AVSS
OUT
46
45 46 49 50
CPU Core Load Side Current Sense (IC0C)
Gain: 161.5x, EDP: 53 A
Rsense: 2x of 0.00075 (R7510, R7520), Rsum: 0.000375
V across Rsense: 19.8 mV
Gain needed: 166.1x
R5345
4.42K
21
0.1%
1/16W
MF
0402
R5346
4.42K
21
CPUIMVP_ISNS_P
85
0.1%
1/16W
MF
0402
R5347
4.42K
21
CPUIMVP_ISNS_N
85
0.1%
1/16W
MF
0402
R5348
4.42K
21
0.1%
1/16W
MF
0402
AXG Core Load Side Current Sense (IN0C)
Gain: 190.6x, EDP: 46 A
Rsense: 2x of 0.00075 (R7550, R7560), Rsum: 0.000375
V across Rsense: 17.25 mV
Gain needed: 191.3x
R5355
4.42K
21
0.1%
1/16W
MF
0402
R5356
4.42K
21
CPUIMVP_ISNSG_P
85
0.1%
1/16W
MF
0402
R5357
4.42K
21
CPUIMVP_ISNSG_N
85
0.1%
1/16W
MF
0402
R5358
4.42K
21
0.1%
1/16W
MF
0402
PART NUMBER
116S0114
LOADISNS:YES
R5342
2.21K
0.1%
1/16W
MF
0402
R5343
2.21K
0.1%
1/16W
MF
LOADISNS:YES
0402
LOADISNS:YES
R5352
1.54K
1%
1/16W
MF-LF
402
R5353
1.54K
1%
1/16W
MF-LF
LOADISNS:YES
402
QTY
RES,MTL FLIM,100K,1/16W,0402,SMD,LF
3
21
CPUIMVP_ISUM_R_P
85
21
CPUIMVP_ISUM_R_N
85
1
2
21
CPUIMVP_ISUMG_R_P
85
21
CPUIMVP_ISUMG_R_N
85
1
2
DESCRIPTION
=PP3V3_S0_IMVPISNS
7
49
R5344
715K
0.1%
1/16W
MF
402
LOADISNS:YES
SIGNAL_MODEL=EMPTY
=PP3V3_S0_IMVPISNS
7
49
R5354
715K
0.1%
1/16W
MF
402
LOADISNS:YES
SIGNAL_MODEL=EMPTY
LOADISNS:YES
CRITICAL
8
3
V+
2
V-
THRM
4
9
R5341
715K
21
0.1%
1/16W
MF
402
8
5
V+
6
V-
THRM
4
9
R5351
715K
21
0.1%
1/16W
MF
402
REFERENCE DES
C5349,C5359,C5369
U5340
OPA2333
DFN
1
CPUIMVP_ISUM_IOUT
LOADISNS:YES
PLACE_NEAR=U4900.E1:5MM
LOADISNS:YES
SIGNAL_MODEL=EMPTY
LOADISNS:YES
CRITICAL
U5340
OPA2333
DFN
7
CPUIMVP_ISUMG_IOUT
LOADISNS:YES
PLACE_NEAR=U4900.H1:5MM
LOADISNS:YES
SIGNAL_MODEL=EMPTY
1
2
CRITICAL
LOADISNS:YES
PLACE_NEAR=U5340.8:3MM
C5340
0.1UF
20%
10V
CERM
402
R5349
4.53K
21
1%
1/16W
MF-LF
402
R5359
4.53K
21
1%
1/16W
MF-LF
402
BOM OPTION
LOADISNS:NO
SMC_CPU_ISENSE
1
C5349
0.22UF
20%
6.3V
2
X5R
402
LOADISNS:YES
PLACE_NEAR=U4900.E1:5MM
GND_SMC_AVSS
SMC_AXG_ISENSE
1
C5359
0.22UF
20%
6.3V
2
X5R
402
LOADISNS:YES
PLACE_NEAR=U4900.H1:5MM
GND_SMC_AVSS
12
OUT
OUT
D
46
45 46 49 50
C
46
B
45 46 49 50
A
AXG Core Voltage Sense (VN0C)
=PPAXGVCORE_S0_VSENSE
7
PLACE_NEAR=R7550.2:5 MM
XW5330
SM
21
AXGVSENSE_IN
PLACE_NEAR=U4900.C1:5MM
R5339
4.53K
1%
1/16W
MF-LF
402
21
SMC_AXG_VSENSE
PLACE_NEAR=U4900.C1:5MM
1
C5339
0.22UF
20%
6.3V
2
X5R
402
GND_SMC_AVSS
46
OUT
45 46 49 50
6 3
SYNC_MASTER=LINDA_J30
PAGE TITLE
Power Sensors: Load Side
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
SYNC_DATE=09/28/2011
DRAWING NUMBER
051-9058
REVISION
6.0.0
BRANCH
PAGE
53 OF 109
SHEET
49 OF 86
124578
SIZE
A
D
8 7 6 5 4 3
12
CPU High Side Current Sense (IC0R)
Gain: 50x, EDP: 17.4 A
Rsense: 0.003 (R5400)
V across Rsense: 52.2 mV
D
Gain needed: 63.2x
=PPVIN_S5_HS_COMPUTING_ISNS
7
OUT
R5400
0.003
CRITICAL
=PPVIN_S5_HS_COMPUTING_ISNS_R
7
IN
OTHER High Side Current Sense (IO0R)
Gain: 100x, EDP: 8.8 A
Rsense: 0.003 (R5410)
V across Rsense: 26.4 mV
Gain needed: 125x
=PPVIN_S5_HS_OTHER_ISNS
7
C
OUT
R5410
0.003
CRITICAL
=PPVIN_S5_HS_OTHER_ISNS_R
7
IN
PLACE_NEAR=U5400.5:10MM
1
85
2%
0.5W
85
MF
0612
432
PLACE_NEAR=U5400.4:10MM
PLACE_NEAR=U5410.5:10MM
1
85
2%
0.5W
85
MF
0612
432
PLACE_NEAR=U5410.4:10MM
ISNS_HS_COMPUTING_N
ISNS_HS_COMPUTING_P
ISNS_HS_OTHER_N
ISNS_HS_OTHER_P
=PP3V3_S0_HS_COMPUTING_ISNS
7
3
V+
U5400
INA213
5
SC70
IN-
4
GND
CRITICAL
=PP3V3_S0_HS_OTHER_ISNS
7
5
4
CRITICAL
2
3
V+
U5410
INA214
SC70
IN-
IN+ REF
GND
2
OUT
OUT
6
1
REFIN+
6
1
1
C5401
0.1UF
20%
10V
2
CERM
402
HS_COMPUTING_IOUT
PLACE_NEAR=U4900.B5:5MM
1
C5411
0.1UF
20%
10V
2
CERM
402
HS_OTHER_IOUT
PLACE_NEAR=U4900.A5:5MM
R5409
4.53K
1%
1/16W
MF-LF
402
R5419
4.53K
1%
1/16W
MF-LF
402
21
SMC_CPU_HI_ISENSE
1
C5409
0.22UF
20%
6.3V
2
X5R
402
PLACE_NEAR=U4900.B5:5MM
GND_SMC_AVSS
21
SMC_OTHER_HI_ISENSE
1
C5419
0.22UF
20%
6.3V
2
X5R
402
PLACE_NEAR=U4900.A5:5MM
GND_SMC_AVSS
OUT
OUT
46
45 46 49 50
46
45 46 49 50
PBUS Voltage Sense & Enable (VP0R)
CRITICAL
Q5480
NTUD3169CZ
SOT-963
=PBUSVSENS_EN
73
IN
=PPBUS_S0_VSENSE
7
Enables PBUS VSense
divider when in S0.
R5481
100K
1/16W
MF-LF
402
1
1%
2
PBUSVSENS_EN_L_DIV
2
1
5
4
N-CHANNEL
G
G
P-CHANNEL
6
D
S
D
S
PBUSVSENS_EN_L
3
PBUS_S0_VSENSE
R5482
100K
1/16W
MF-LF
1
1%
402
2
PLACE_NEAR=U4900.A3:5MM
R5488
R5489
PLACE_NEAR=U4900.A3:5MM
27.4K
1/16W
MF-LF
5.49K
1/16W
MF-LF
1
1%
Rthevenin = 4573 Ohms
402
2
1
1%
402
2
SMC_PBUS_VSENSE
PLACE_NEAR=U4900.A3:5MM
1
C5489
0.22UF
20%
6.3V
2
X5R
402
GND_SMC_AVSS
OUT
D
46
45 46 49 50
C
DC In Voltage Sense & Enable (VD0R)
Charger (BMON Production) Current Sense (IPBR)
Charger Gain: 36x
Rsense: 0.010 (R7050)
Max Current Measured: 9.2 A
=CHGR_ACOK
46 64
73
IN
IN
PM_SUS_EN
PLACE_NEAR=U4900.A4:5MM
R5429
45.3K
CHGR_BMON
64
IN
B
DC-In (AMON) Current Sense (ID0R)
Charger Gain: 20x
Rsense: 0.020 (R7020)
Max Current Measured: 8.3 A
PLACE_NEAR=U4900.B3:5MM
CHGR_AMON
64
IN
A
1%
1/16W
MF-LF
402
R5439
4.53K
1%
1/16W
MF-LF
402
21
SMC_BMON_ISENSE
1
C5429
0.022UF
20%
16V
2
CERM
402
PLACE_NEAR=U4900.A4:5MM
GND_SMC_AVSS
21
SMC_DCIN_ISENSE
1
C5439
0.22UF
20%
6.3V
2
X5R
402
PLACE_NEAR=U4900.B3:5MM
GND_SMC_AVSS
OUT
OUT
46
45 46 49 50
46
45 46 49 50
NO STUFF
Enables DC-In VSense
divider when AC present.
R5493
0
21
1/20W
5% 201MF
R5494
0
21
1/20W
5% 201MF
=PPDCIN_S5_VSENSE
7
DCIN_VSENSE_EN
1
R5491
100K
1%
1/16W
MF-LF
402
2
6 3
CRITICAL
Q5490
NTUD3169CZ
SOT-963
N-CHANNEL
D
G
2
1
5
4
G
P-CHANNEL
S
D
S
PDCINVSENS_EN_L_DIV
6
DCINVSENS_EN_L
3
DCIN_S5_VSENSE
R5492
100K
1/16W
MF-LF
1
1%
402
2
PLACE_NEAR=U4900.F1:5MM
R5498
R5499
PLACE_NEAR=U4900.F1:5MM
1
27.4K
1%
1/16W
MF-LF
Rthevenin = 4573 Ohms
402
2
SMC_DCIN_VSENSE
PLACE_NEAR=U4900.F1:5MM
1
1
5.49K
1/16W
MF-LF
402
C5499
0.22UF
1%
20%
6.3V
2
X5R
402
2
GND_SMC_AVSS
SYNC_MASTER=YONAS_J30
PAGE TITLE
Power Sensors: High Side
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
OUT
Apple Inc.
46
45 46 49 50
SYNC_DATE=11/03/2011
DRAWING NUMBER
051-9058
REVISION
6.0.0
BRANCH
PAGE
54 OF 109
SHEET
50 OF 86
124578
SIZE
B
A
D
8 7 6 5 4 3
12
D
D
Thermal Sensor:
CPU Proximity, Fin Stack, Memory Proximity, 5V/3.3V Proximity
I2C Write, 0x98, I2C Read: 0x99
R5510
47
7
Thermal Diode: Fin Stack
Placement Note:
Place Q5520 on BOTTOM side.
Close to Fin Stack.
C
THMSNS_D2_P
CRITICAL
PLACE_SIDE=TOP
85
THMSNS_D2_N
85
NOSTUFF
PLACE_NEAR=Q5510.2:5MM
1
C5510
22PF
5%
50V
2
CERM
0402
PLACE_NEAR=Q5510.3:5MM
Q5510
BC846BMXXH
SOT732-3
2
1
3
Thermal Diode: 5V/3.3V Proximity
Placement Note:
Place Q5510 on the TOP side,
Next to 5V and 3.3V power supplies.
PLACE_NEAR=Q5520.3:5MM
1
C5520
22PF
5%
BC846BMXXH
50V
2
NOSTUFF
NOSTUFF
CERM
0402
PLACE_NEAR=Q5520.2:5MM
PLACE_NEAR=Q5515.3:5MM
1
C5515
22PF
5%
BC846BMXXH
50V
2
CERM
0402
PLACE_NEAR=Q5515.2:5MM
Thermal Diode: Memory Proximity
Placement Note:
Place Q5515 on the EITHER side, on the
right of DIMM connectors.
=PP3V3_S0_CPUTHMSNS
85
3
Q5520
SOT732-3
2
CRITICAL
85
3
Q5515
SOT732-3
2
CRITICAL
THMSNS_D1_P
1
THMSNS_D1_N
1
PLACE_NEAR=U5511.2:5MM
SIGNAL_MODEL=EMPTY
PLACE_NEAR=U5511.3:5MM
PLACE_NEAR=U5511.4:5MM
SIGNAL_MODEL=EMPTY
PLACE_NEAR=U5511.5:5MM
21
5%
1/16W
MF-LF
402
C5511
0.0022uF
C5512
0.0022uF
PP3V3_S0_CPUTHMSNS_R
MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V
1
10%
50V
2
CERM
402
1
10%
50V
2
CERM
402
1
VDD
U5511
EMC1414
DP1
DN1
DP2
DN2
GND
6
DFN
THERM*/ADDR
ALERT*
SMDATA
SMCLK
THRM_PAD
11
2
3 8
4
5
Thermal Sensor: CPU Proximity
Placement Note:
Place U5511 on bottom side under CPU
1
C5513
0.1uF
20%
10V
R5511
2
CERM
402
7
CPUTHMSNS_THM_L
CPUTHMSNS_ALERT_L
9
=I2C_CPUTHMSNS_SDA
10
=I2C_CPUTHMSNS_SCL
PLACE_SIDE=BOTTOM
10K
1/16W
MF-LF
402
1
1
R5512
10K
5%
5%
1/16W
MF-LF
402
2
2
C
48
BI
48
BI
Thermal Sensor: T29 Die
SIZE
B
A
D
B
33
BI
TP_T29_THERM_DP
21
XW5520
SM
T29_THERMD_P
85
MAKE_BASE=TRUE
T29_THERMD_N
85
PLACE_NEAR=U3600.B1:2MM
1
R5520
10K
5%
1/16W
MF-LF
402
2
NOSTUFF
PLACE_SIDE=BOTTOM
Note: Use GND pin B1 on U3600 for N leg.
A
SYNC_MASTER=YONAS_J30
PAGE TITLE
Thermal Sensors
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
6 3
SYNC_DATE=08/01/2011
DRAWING NUMBER
051-9058
REVISION
6.0.0
BRANCH
PAGE
55 OF 109
SHEET
51 OF 86
124578
8 7 6 5 4 3
12
D
=PP5V_S0_FAN_RT
7
=PP3V3_S0_FAN_RT
7
CRITICAL
J5601
78171-0004
M-RT-SM
5
NC
1
2
3
4
6
NC
518S0521
5V DC
TACH
MOTOR CONTROL
GND
47K
1/16W
MF-LF
1
5%
2
402
C
R5660
R5665
47K
1
GS
2
5%
1/16W
MF-LF
402
Q5660
21
FAN_RT_TACH
6
VESM
D
3
FAN_RT_PWM
6
SMC_FAN_0_TACH
45
SMC_FAN_0_CTL
45
R5661
100K
1/16W
MF-LF
402
1
5%
2
SSM3K15AMFVAPE
D
C
SIZE
B
A
D
B
A
PAGE TITLE
Fan
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
6 3
SYNC_DATE=02/15/2011SYNC_MASTER=K90I_MLB
DRAWING NUMBER
051-9058
REVISION
6.0.0
BRANCH
PAGE
56 OF 109
SHEET
52 OF 86
124578
8 7 6 5 4 3
12
VDD
10
POWERV_SNSR_SNS
0.255E-6 W
16.32E-6 W
0.72E-3 W
294E-6 W
75.2E-6 W
THRM
PAD
11
36E-3 W
96E-6 W
OUT_1
OUT_2
OUT_3
OUT_ALL#
45 46
1
C5750
0.1UF
10%
16V
2
X7R-CERM
0402
9
WS_LEFT_SHIFT_KEY
8
WS_LEFT_OPTION_KEY
7
WS_CONTROL_KEY
Pull-up in U5010.
6
SMC_TPAD_RST_L
53
53
SMC_ONOFF_L
OUT
PLACEMENT_NOTE=NEAR J5713
Keyboard Connector
=PP3V3_S4_TPAD
7
53 54
=PP3V42_G3H_TPAD
7
53
WS_KBD1
6
53
WS_KBD2
6
53
WS_KBD3
6
53
WS_KBD4
6
53
WS_KBD5
6
53
WS_KBD6
6
53
WS_KBD7
6
53
WS_KBD8
6
53
WS_KBD9
6
53
WS_KBD10
6
53
WS_KBD11
6
WS_KBD15_C
WS_KBD16N
C5710
0.1UF
CERM
53
53
53
46
OUT
20%
10V
402
1
2
R5714
470
1%
1/16W
MF-LF
402
R5715
10K
1%
1/16W
MF-LF
402
R5710
1K
5%
1/16W
MF-LF
402
53
WS_KBD12
6
53
21
21
21
WS_KBD13
6
53
WS_KBD14
6
53
WS_KBD15_CAP
6
WS_KBD16_NUM
6
WS_KBD17
6
53
WS_KBD18
6
53
WS_KBD19
6
53
WS_KBD20
6
53
WS_KBD21
6
53
WS_KBD22
6
53
WS_KBD23
6
53
WS_KBD_ONOFF_L
6
WS_LEFT_SHIFT_KBD
6
53
WS_LEFT_OPTION_KBD
6
53
WS_CONTROL_KBD
6
53
32
NC
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
31
NC
F-RT-SM
FF14-30A-R11B-B-3H
J5713
CRITICAL
518S0637
D
C
B
PSOC USB CONTROLLER
- USB INTERFACES TO MLB
- SPI HOST TO Z2
- TRACKPAD PICK BUTTONS
PLACE_SIDE=BOTTOM
=PP3V3_S4_TPAD
7
53 54
D
=PSOC_WAKE_L
46
OUT
PICKB_L
6
54
BUTTON_DISABLE
53
Z2_HOST_INTN
6
54
WS_LEFT_SHIFT_KEY
53
WS_LEFT_OPTION_KEY
53
WS_CONTROL_KEY
53
Z2_KEY_ACT_L
6
54
TPAD_VBUS_EN
73
IN
Z2_DEBUG3
6
54
Z2_RESET
6
54
PSOC_MISO
6
54
PSOC_F_CS_L
6
54
PSOC_MOSI
6
C
54
PSOC_SCLK
6
54
Z2_MISO
6
54
Z2_CS_L
6
54
Z2_MOSI
6
54
Z2_SCLK
6
54
TP_PSOC_SCL
TP_PSOC_SDA
TP_PSOC_P1_3
6
TP_ISSP_SCLK_P1_1
ISSP SCLK/I2C SCL
USB_TPAD_P
8
80
USB_TPAD_N
8
80
R5704
1.5
12
PP3V3_S3_PSOC
MIN_LINE_WIDTH=0.50MM
5%
MIN_NECK_WIDTH=0.20MM
1/16W
VOLTAGE=3.3V
MF-LF
402
NC
R5701
24
5%
1/16W
MF-LF
402
R5702
24
5%
1/16W
MF-LF
402
1
R5703
220K
5%
1/16W
MF-LF
402
2
1 42
P2_5
P2_3
2 41
P2_1
3 40
P4_7
4 39
P4_5
5 38
P4_3
6 37
P4_1
7 36
P3_7
8 35
P3_5
9 34
P3_3
10 33
P3_1
11 32
P5_7
12 31
P5_5
13 30
P5_3
14 29
P5_1
P1_7
15281627172618
21
USB_TPAD_R_P
85
21
USB_TPAD_R_N
85
- KEYBOARD SCANNER
51485247534654
554456
P2_7
P0_3
P0_5
P0_7
P0_1
CRITICAL
OMIT
U5701
CY8C24794
(SYM-VER2)
337S2983
P1_1
P1_3
P1_5
VSS
D+
20
BYPASS=U5701.22:19:5 mm
1
C5704
100PF
5%
50V
2
CERM
0402
50194922
VSS
MLF
D-
21
45
VDD
P0_4
P0_2
P0_0
P0_6
P7_7
P7_0
P1_0
P1_2
VDD
23
24
25
1
C5702
100PF
5%
50V
2
CERM
0402
BYPASS=U5701.49:50:5 mm
BYPASS=U5701.22:19:8 mm
1
C5705
0.1UF
10%
16V
2
X7R-CERM
0402
43
P2_4
P2_6
P2_2
P2_0
P4_6
P4_4
P4_2
P4_0
P3_6
P3_4
P3_2
P3_0
P5_6
P5_4
P5_2
P5_0
THRML
57
PAD
P1_4
P1_6
TP_ISSP_SDATA_P1_0
ISSP SDATA/I2C SDA
1
C5703
0.1UF
10%
16V
2
X7R-CERM
0402
BYPASS=U5701.49:50:8 mm
BYPASS=U5701.22:19:11 mm
1
C5706
4.7UF
20%
6.3V
2
X5R
603
WS_KBD23
WS_KBD22
WS_KBD21
WS_KBD20
WS_KBD19
WS_KBD18
WS_KBD17
WS_KBD16N
WS_KBD15_C
WS_KBD14
WS_KBD13
WS_KBD12
WS_KBD11
WS_KBD10
WS_KBD9
WS_KBD8
WS_KBD7
WS_KBD1
WS_KBD2
WS_KBD3
WS_KBD4
WS_KBD5
WS_KBD6
Z2_CLKIN
TP_P7_7
6
6
6
6
6
6
6
53
53
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
(PP3V3_S3_PSOC)
1
C5701
4.7UF
20%
6.3V
2
X5R
603
BYPASS=U5701.49:50:11 mm
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
54
IC
TMP102
3V3 LDO
PSOC
18V BOOSTER
PIN NAME
V+
VDD
VOUT
VDD
VIN
Left shift, option & control keys combined with power button cause SMC RESET# assertion.
Keys ANDed with MSP power to isolate when MSP is not powered. No IPD on OE input pin PP3V3_S4 (symbol error).
CURRENT
10UA
80UA
60MA (MAX)
60MA (MAX)
8MA (TYP)
14MA (MAX)
4MA (MAX)
2.55 KOHM
10 OHM
0.2 OHM
1.5 OHM
4.7 OHM
0.0255 V
0.204 V
0.6 V
0.012 V
0.012 V
0.021 V
0.0188 V
SMC Manual Reset & Isolation
=PP3V42_G3H_TPAD
7
53
B
CRITICAL
TPAD Buttons Disable
BUTTON_DISABLE
53
SSM3K15AMFVAPE
CRITICAL
SMC_LID
45 46 63
IN
Q5701
VESM
1
G S
PLACE THESE COMPONENTS CLOSE TO J5800
THIS ASSUMES THERE’S A PP3V42_G3H PULL UP ON MLB
3
D
THE TPAD BUTTONS WILL BE DISABLE
WHEN THE LID IS CLOSED
2
LID OPEN => SMC_LID_LC ~ 3.42V
LID CLOSE => SMC_LID_LC < 0.50V
=PP3V3_S4_TPAD
7
53 54
WS_LEFT_SHIFT_KBD
6
53
WS_LEFT_OPTION_KBD
6
53
WS_CONTROL_KBD
6
53
4
OE
(IPD)
1
IN_1
(IPD)
2
IN_2
(IPD)
3
IN_3
(IPD)
U5750
SLG4AP021
TQFN
GND
5
A
6 3
SYNC_MASTER=J31_MLB
PAGE TITLE
WELLSPRING 1
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
SYNC_DATE=07/01/2011
DRAWING NUMBER
051-9058
REVISION
6.0.0
BRANCH
PAGE
57 OF 109
SHEET
53 OF 86
124578
SIZE
A
D
8 7 6 5 4 3
12
BOOSTER +18.5VDC FOR SENSORS
BOOSTER DESIGN CONSIDERATION:
- POWER CONSUMPTION
- DROOP LINE REGULATION
D
TPAD:Z2
=PP5V_S5_TPAD
7
R5805
- RIPPLE TO MEET ERS
- 100-300 KHZ CLEAN SPECTRUM
- STARTUP TIME LESS THAN 2MS
- R5812,R5813,C5818 MODIFIED
0
12
5%
1/16W
MF-LF
402
TPAD:Z2
1
C5816
0.1UF
X7R-CERM
10%
16V
0402
1
2
2
PP5V_S4_P18V5S5
MIN_LINE_WIDTH=0.50MM
MIN_NECK_WIDTH=0.20MM
VOLTAGE=5V
PP5V_S5_P18V5S5_VIN
MIN_LINE_WIDTH=0.50MM
MIN_NECK_WIDTH=0.20MM
VOLTAGE=5V
TPAD:Z2
C5817
2.2UF
10%
16V
X5R
603
1
U5805
L
TPS61045
3 5
DO
NC
THRML
PAD
CRITICAL
9
TPAD:Z2
CRITICAL
L5801
3.3UH-870MA
VLF3010AT-SM-HF
2
VIN
QFN-1
CTRL
TPAD:Z2
PGND
GND
6
7
FB
SW
21
4
8
P18V5S4_SW
MIN_LINE_WIDTH=0.50MM
MIN_NECK_WIDTH=0.20MM
SWITCH_NODE=TRUE
P18V5S4_FB
Z2_BOOST_EN
TPAD:Z2
1
R5811
100K
1%
1/16W
MF-LF
402
2
6
54
TPAD:Z2
CRITICAL
D5802
SOD-323
B0520WSXG
TPAD:Z2
C5818
39PF
KA
5%
50V
CERM
0402
1
2
PP18V5_S4_R
MIN_LINE_WIDTH=0.50MM
MIN_NECK_WIDTH=0.20MM
VOLTAGE=18.5V
TPAD:Z2
1
R5812
1M
1%
1/16W
MF-LF
402
2
TPAD:Z2
1
R5813
71.5K
1%
1/16W
MF-LF
402
2
TPAD:Z2
C5819
603-1
1UF
TPAD:Z2
R5806
0
21
5%
1/16W
MF-LF
402
1
C5815
1000PF
5%
25V
2
NP0-C0G
402
TPAD:Z2
1
10%
25V
2
X5R
PP18V5_Z2
MIN_LINE_WIDTH=0.50MM
MIN_NECK_WIDTH=0.20MM
VOLTAGE=18.5V
6
54
PP5V_S5_CUMULUS
6
VOLTAGE=5V
MIN_NECK_WIDTH=0.20MM
MIN_LINE_WIDTH=0.50MM
=PP3V3_S4_TPAD
7
53
6
53
6
53
6
53
6
53
6
53
6
54
6
53
6
53
IPD Flex Connector
CRITICAL
J5800
55560-0228
M-ST-SM
2
Z2_CS_L
Z2_DEBUG3
Z2_MOSI
Z2_MISO
Z2_SCLK
Z2_BOOST_EN
Z2_HOST_INTN
Z2_CLKIN
4 3
6 5
8 7
10
12 11
14 13
16 15
18 17
20
22 21
1
9
19
Z2_KEY_ACT_L
Z2_RESET
PSOC_F_CS_L
PICKB_L
PSOC_MISO
PSOC_MOSI
PSOC_SCLK
=I2C_TPAD_SDA
=I2C_TPAD_SCL
PP18V5_Z2
6
54
6
53
6
53
6
53
6
53
6
53
6
53
6
53
48
48
C
516S0689
PLACE_NEAR=J5800.18:3MM
TPAD:CUMULUS
1
C5800
0.1UF
20%
10V
2
CERM
402
TPAD:CUMULUS
L5800
FERR-120-OHM-1.5A
PLACE_NEAR=J5800.18:3MM
0402-LF
21
PIN 21 IS NC ON CUMULUS FLEX
PIN 18 IS NC ON Z2 FLEX
D
C
Keyboard Backlight Driver & Detection
=PP5V_S0_KBDLED
7
B
45
To detect Keyboard backlight, SMC will
tristate and read SMC_SYS_KBDLED:
If LOW, keyboard backlight present
If HIGH, keyboard backlight not present
R5853 always stuffed, R5854 only
grounded when KB BL flex connected.
7
SMC_SYS_KBDLED
BI
=PP3V3_S0_KBDLED
R5853
470K
1/16W
MF-LF
402
5%
1
2
1
R5854
4.7K
5%
1/16W
MF-LF
402
2
C5850
NO STUFF
R5852
1/16W
MF-LF
10K
402
402-1
1UF
5%
1
10%
10V
2
X5R
U5850
STLA02
3
LX
CRITICAL
EN/PWM
1
2
GND
2
CRITICAL
L5850
10UH-0.58A-0.35OHM
1098AS-SM
1
VIN
DFN6
VOUT
FB
THRM_PAD
7
21
KBDLED_SW
MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.25 MM
SWITCH_NODE=TRUE
KBDLED_ANODE
6
MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.2 MM
1
R5855
4
56
10
1%
1/16W
MF-LF
402
2
KBDLED_CAP
MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.25 MM
1
C5855
2
0.47UF
10%
50V
CERM-X5R
0603
1
2
C5856
0.47UF
10%
50V
CERM-X5R
0603
6
(SMC_KBDLED_PRESENT_L)
A
6 3
Keyboard Backlight Connector
CRITICAL
J5815
FF18-4A-R11AD-B-3H
F-RT-SM
SMC_KDBLED_PRESENT_L
1
2
3
4
518S0691
J5815 pin 1 is grounded
on keyboard backlight flex
PAGE TITLE
WELLSPRING 2
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
SYNC_DATE=09/28/2011SYNC_MASTER=JACK_J30
DRAWING NUMBER
051-9058
REVISION
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BRANCH
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SHEET
54 OF 86
124578
SIZE
B
A
D
8 7 6 5 4 3
12
D
=PP3V3_S3_SMS
7
C5926
C
BYPASS=U5920.14:13:8 mm
10UF
45
OUT
BYPASS=U5920.14:13:8 mm
1
1
C5922
0.1UF
20%
6.3V
X5R
603
SMS_INT_L
TP_SMS_INT2
10%
16V
2
2
X7R-CERM
0402
PLACEMENT_NOTE=See schematic for orientation.
Desired orientation when placed on top-side:
R5924
1/16W
MF-LF
10K
1
5%
402
2
2
NC
NC
3
NC
10
RESERVED
15
11
INT1CSSDA/SDI/SDO
9
INT2
+Y
+Z (up)
14
VDD
U5920
LIS331DLH
5
+X
CRITICAL
1
VDD_IO
LGA
SDO
SCL/SPC
GND
161312
338S0687
Front of system
PLACE_SIDE=TOP
8
SMS_I2C_SEL
7
SMS_ADDR_SELECT
6
I2C_SMC_SMS_SDA_R
4
I2C_SMC_SMS_SCL_R
R5920
1/16W
MF-LF
R5921
1/16W
MF-LF
1
10K
5%
402
2
R5923
0
21
=I2C_SMC_SMS_SDA
5%
1/16W
MF-LF
402
R5922
10K
1
5%
402
2
0
21
=I2C_SMC_SMS_SCL
5%
1/16W
MF-LF
402
SMS_ADDR_SELECT=0 Addr: 0x30(Wr)/0x31(Rd)
SMS_ADDR_SELECT=1 Addr: 0x32(Wr)/0x33(Rd)
NOTE: SDA and SCL have internal pull-ups to VDD_IO.
48
BI
48
IN
D
C
B
A
6 3
Circle indicates pin 1 location when placed
in correct orientation
PAGE TITLE
Digital Accelerometer
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
SYNC_DATE=02/15/2011SYNC_MASTER=K90I_MLB
DRAWING NUMBER
051-9058
REVISION
6.0.0
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PAGE
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SHEET
55 OF 86
124578
SIZE
B
A
D
8 7 6 5 4 3
12
D
C
=PP3V3_SUS_ROM
7
1
R6101
3.3K
5%
1/16W
MF-LF
402
2
46 47 81 46 47 81
46 47 81
6
19 47
NOTE: If HOLD* is asserted
ROM will ignore SPI cycles.
SPI_MLB_CLK
IN IN
SPI_MLB_CS_L
IN
SPI_WP_L
SPIROM_USE_MLB
IN
C6100
0.1UF
CERM
1
20%
10V
2
402
6
SCK
1
3
7
U6100
SST25VF064C
CE*
WP*
HOLD*
8
VDD
64MBIT
SOIC
OMIT
VSS
4
CRITICAL
5
2
SPI_MLB_MOSI
SPI_MLB_MISO
46 47 81
OUT
SI
SO
D
C
SIZE
B
A
D
B
A
6 3
SYNC_MASTER=K90I_MLB SYNC_DATE=02/15/2011
PAGE TITLE
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
SPI ROM
Apple Inc.
DRAWING NUMBER
051-9058
REVISION
6.0.0
BRANCH
PAGE
61 OF 109
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56 OF 86
124578
8 7 6 5 4 3
AUDIO CODEC
L6201
7
IN
=PP1V8R1V5_S0_AUDIO
FERR-220-OHM
0402
D
GND_AUDIO_HP_AMP
57 58 59
PP4V5_AUDIO_ANALOG
6
57 62
IN
AUD_GPIO_0
57
OUT
TP_AUD_GPIO_1
TP_AUD_GPIO_2
GPIO3 = SPKR AMP SHDN CONTROL
60
62
7
57 61 62
AUD_GPIO_3
OUT
AUD_SENSE_A
IN
=PP3V3_S0_AUDIO
IN
U6201 CONSUMES ?MA MAX. FROM 1.5V RAIL
21
1
1
C6226
2
2
0.1UF
10%
16V
X7R-CERM
0402
1
C6211
2
0.1UF
10%
16V
X7R-CERM
0402
C6221
10UF
20%
10V
X5R-CERM
0402-1
CRITICAL
1
R6210
2.67K
1%
1/20W
MF
201
2
C6210
4.7UF
20%
4V
X5R-1
402
PP1V8R1V5_S0_AUDIO_DIG
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.5V
CRITICAL
1
1
C6220
10UF
20%
2
C6222
2.2UF
20%
6.3V
CERM
402-LF
10V
2
X5R-CERM
0402-1
1
2
C6219
TANT-POLY
2012-LLP
CS4206_FP
CS4206_FN
CS4206_FLYP
CS4206_FLYC
1
C6223
2
CS4206_FLYN
10UF
2.2UF
402-LF
20%
16V
20%
6.3V
CERM
1
2
VBIAS_DAC
C
HDA_BIT_CLK
16 81
IN
HDA_SYNC
16 81
IN
HDA_SDIN0
16 81
OUT
HDA_SDOUT
16 81
IN
HDA_RST_L
16 81
IN
TP_AUD_SPDIF_IN
AUD_SPDIF_OUT
61
OUT
B
GND_AUDIO_CODEC
57 62
4.5V POWER SUPPLY FOR CODEC
R6211
22
5%
1/16W
MF-LF
402
21
AUD_SDI_R
81
R6212
39
5%
1/16W
MF-LF
402
AUD_SPDIF_OUT_CHIP
21
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=0V
APPLE P/N 353S3199 as of July 2011
9
VA_REF
VD
29
VBIAS_DAC
44
VHP_FILT+
41
VHP_FILT-
2
GPIO0/DMIC_SDA1
12
GPIO1/DMIC_SDA2
/SPDIF_OUT2
14
GPIO2
15
GPIO3
13
SENSE_A
45
FLYP
43
FLYC
42
FLYN
3
VL_HD
1
VL_IF
6
BITCLK
10
SYNC
8
SDI
5
SDO
11
RESET*
47
SPDIF_IN
48
SPDIF_OUT
THRM_PAD
DGND
7
GND_AUDIO_HP_AMP
57 58 59
24
VA_HP
U6201
CS4206B
QFN
CRITICAL
AGND
49
46
25
VA
HPOUT_L
HPOUT_R
HPREF
LINEOUT_L1+
LINEOUT_L1LINEOUT_R1+
LINEOUT_R1-
LINEOUT_L2+
LINEOUT_L2LINEOUT_R2+
LINEOUT_R2-
MICBIAS
VCOM
LINEIN_L+
LINEIN_CLINEIN_R+
MICIN_L+
MICIN_LMICIN_R+
MICIN_R-
VREF+_ADC
DMIC_SCL
26
C6218
0.1UF
X7R-CERM
C6216
1UF
10%
1
1
C6217
10%
16V
0402
38
40
39
35
34
36
37
31
30
32
33
10UF
20%
16V
2
2
TANT-POLY
2012-LLP
MIN_LINE_WIDTH=0.30MM
MIN_LINE_WIDTH=0.30MM
MIN_LINE_WIDTH=0.30MM MIN_NECK_WIDTH=0.20MM
10V
X5R
402-1
16
CS4206_VCOM
28
21
22
23
18
17
19
20
27
4
C6224
0603-SM
1UF
TANT
1
20%
16V
2
CS4206_VREF_ADC
AUD_DMIC_SCL
1
C6225
10UF
20%
16V
2
TANT-POLY
2012-LLP
1
C6215
0.1UF
2
X7R-CERM
MIN_NECK_WIDTH=0.10MM
MIN_NECK_WIDTH=0.10MM
10%
16V
0402
R6214
1/16W
MF-LF
=PP5V_S3_AUDIO
=PP3V3R1V5_S0_AUDIO
1
C6214
0.1UF
2
X7R-CERM
0402
1
1
C6213
10UF
10%
16V
20%
10V
2
2
X5R-CERM
0402-1
PP4V5_AUDIO_ANALOG
CRITICAL
GND_AUDIO_HP_AMP
GND_AUDIO_CODEC
AUD_HP_PORT_L
AUD_HP_PORT_R
HPAMP_REF
TP_AUD_LO1_P_L
TP_AUD_LO1_N_L
AUD_LO1_P_R
AUD_LO1_N_R
AUD_LO2_P_L
AUD_LO2_N_L
AUD_LO2_P_R
AUD_LO2_N_R
AUD_CODEC_MICBIAS
AUD_MIC_INP_L
AUD_MIC_INN_L
AUD_MIC_INP_R
AUD_MIC_INN_R
22
21
5%
402
NOSTUFF
1
R6213
100K
5%
1/20W
MF
201
2
AUD_DMIC_CLK
7
57
7
6
57 62
IN
57 58 59
57 62
59 61
OUT
59 61
OUT
58
IN
60 85
OUT
FR SPKR AMP. SIG. SOURCE
60 85
OUT
60 85
OUT
LFT. SPKR AMP. SIG. SOURCE
60 85
OUT
60 85
OUT
RT. SPKR AMP. SIG. SOURCE
60 85
OUT
62
OUT
NC
NC
NC
62
IN
EXT MIC CODEC INPUT
62
IN
62
IN
BI MIC CODEC INPUT
62
IN
57
OUT
Digial Mic - Only for mock ups
as of July 2011
AUD_DMIC_CLK
57
AUD_GPIO_0
57
TP_AUD_DMIC_CLK
MAKE_BASE=TRUE
TP_AUD_DMIC_SDATA
MAKE_BASE=TRUE
12
D
C
B
APPLE P/N 353S2281 as of July 2011
L6200
57
57 61 62
7
IN
7
IN
=PP5V_S3_AUDIO
=PP3V3_S0_AUDIO
FERR-220-OHM
0402
R6200
2.21K
1%
1/16W
MF-LF
402
A
21
MIN_LINE_WIDTH=0.15MM
MIN_NECK_WIDTH=0.10MM
VOLTAGE=5V
21
4V5_REG_IN
4V5_REG_EN
1
C6200
1UF
10%
10V
2
X5R
402
XW6200
SM
NOSTUFF
R6201
0
5%
1/16W
MF-LF
402
XW6201
SM
1
R6203
100K
5%
1/16W
MF-LF
402
2
21
21
21
1
C6201
1UF
2
U6200
TPS71745
6
IN
CRITICAL
4
EN
10%
10V
X5R
402
GND
SON
2
OUT
NR/FB
NC
1
3
4V5_NR
5
NC
C6202
0.1UF
10%
16V
X7R-CERM
0402
MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=0V
1
2
MIN_LINE_WIDTH=0.15MM
MIN_NECK_WIDTH=0.10MM
VOLTAGE=4.5V
PP4V5_AUDIO_ANALOG
1
C6203
1UF
10%
10V
2
X5R
402
GND_AUDIO_CODEC
GND_AUDIO_HP_AMP
BI
6
57 62
57 58 59
57 62
www.qdzbwx.com
6 3
NOTES ON J30 audio
Codec HPamp used for Lineout/HPout. No external HPamp.
3 Spk amplifiers - 2 tweeters and a sub woofer
No line input capability
SPDIF out
China headset support
SYNC_MASTER=KAVITHA_J30
PAGE TITLE
AUDIO: CODEC/REGULATOR
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
SYNC_DATE=07/25/2011
DRAWING NUMBER
051-9058
REVISION
6.0.0
BRANCH
PAGE
62 OF 109
SHEET
57 OF 86
124578
SIZE
A
D
8 7 6 5 4 3
12
D
D
EXTERNAL (HEADSET) MIC INPUT CIRCUITRY APN:353S3066 as of July 2011
L6400
=PP3V42_G3H_AUDIO
7
FERR-220-OHM
0402
21
C
AUD_HS_MIC1
61
IN
FROM HEADSET
AUD_HS_MIC2
61
IN
AUD_HS_RET2
61
IN
AUD_HS_RET1
61
IN
GND_AUDIO_HP_AMP
57 59
B
PP_AUDIO_CHS
MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.25 MM
VOLTAGE=3.42V
C6416
33PF
C0G-CERM
0402
5%
50V
1
C6403
10UF
20%
6.3V
2
CERM-X5R
0402-1
1
2
1
C6400
0.1UF
10%
16V
2
X7R-CERM
0402
1
C6405
10UF
20%
6.3V
2
CERM-X5R
0402-1
TS3A8237A0YZPR
B1 D2
C1
MIN_NECK_WIDTH=0.20MMMIN_LINE_WIDTH=0.40MM
MIN_NECK_WIDTH=0.20MMMIN_LINE_WIDTH=0.40MM
MIC1
MIC2
DGND
A2
A1
VDD
U6400
WCSP
RAMPO/CLAMPI
GND
C3B3B2
RAMPI
CLAMPO
GND2
MIC
REF
SCL
SDA
CPO
GND1
C2
C4
D4
CHS_CLAMP0
D3
D1
A3
A4
B4
CPP
1
C6406
0.001UF
10%
50V
2
X7R-CERM
0402
R6403
2.21K
1%
1/16W
MF-LF
402
XW6400
CHS_CLAMPI
21
R6404
1/16W
MF-LF
R6405
SM
21
0
5%
402
1/16W
MF-LF
0
5%
402
R6402
2.21K
1%
1/16W
MF-LF
402
NOSTUFF
21
21
21
NOSTUFF
1
C6402
10UF
20%
6.3V
2
CERM-X5R
0402-1
R6401
1.02K
1
C6401
10UF
20%
6.3V
2
CERM-X5R
0402-1
CHS_CAP_REF
1/16W
MF-LF
402
21
1%
EXT_MIC_BIAS
EXT_MIC_P
62
IN
C
62
OUT
TO MIKEY & FILTER
CHS_SCL
CHS_SDA
EXT_MIC_N
R6406
0
5%
1/16W
MF-LF
402
R6407
0
5%
1/16W
MF-LF
402
21
21
=I2C_MIKEY_SCL
=I2C_MIKEY_SDA
OUT
IN
BI
62
48 62
48 62
HPAMP_REF
OUT
B
57
I2C ADDRESSES: CHS uses SMBus 0 connections
CHS U6400 READ 0111 0111 0x77
CHS U6400 WRITE 0111 0110 0x76
A
SYNC_MASTER=DIRK_J30
PAGE TITLE
AUDIO: DETECT/MIC BIAS
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
6 3
SYNC_DATE=02/16/2012
DRAWING NUMBER
051-9058
REVISION
6.0.0
BRANCH
PAGE
64 OF 109
SHEET
58 OF 86
124578
SIZE
A
D
8 7 6 5 4 3
12
D
D
ZOBEL NETWORK & 1ST ORDER DAC FILTER PLACEHOLDER
AUD_HP_PORT_L
57 61
IN
AUD_HP_ZOBEL_L
C
GND_AUDIO_HP_AMP
57 58
IN
AUD_HP_ZOBEL_R
AUD_HP_PORT_R
57 61
IN
CRITICAL
CRITICAL
C6500
R6510
C6510
0.1UF
X7R-CERM
0.1UF
X7R-CERM
R6500
39
5%
1/16W
MF-LF
402
10%
16V
0402
1
10%
16V
2
0402
1
39
5%
1/16W
MF-LF
402
2
1
2
1
2
C
SIZE
B
A
D
B
A
6 3
SYNC_MASTER=KAVITHA_J30
PAGE TITLE
AUDIO: HEADPHONE FILTER
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
SYNC_DATE=07/25/2011
DRAWING NUMBER
051-9058
REVISION
6.0.0
BRANCH
PAGE
65 OF 109
SHEET
59 OF 86
124578
8 7 6 5 4 3
12
SATELLITE & SUB TWEETER AMPLIFIER
APN:353S2888 as of July 2011
SATELLITE
D
SUB
GAIN
ALIAS OF PP5VLT_S3, MIN_LINE_WIDTH=0.60MM, MIN_NECK_WIDTH=0.20MM
=PP5V_S3_AUDIO_AMP
7
60
L6611
57 85
AUD_LO2_P_R
IN
FERR-1000-OHM
FERR-1000-OHM
57 85
AUD_LO2_N_R
IN
C
ALIAS OF PP5VLT_S3, MIN_LINE_WIDTH=0.60MM, MIN_NECK_WIDTH=0.20MM
57
IN
SPKRAMP_SHDN
60
60
AUD_GPIO_3
=PP5V_S3_AUDIO_AMP
7
FERR-1000-OHM
57 85
AUD_LO1_P_R
IN
FERR-1000-OHM
57 85
AUD_LO1_N_R
IN
SPKRAMP_SHDN
60
0402
L6610
0402
L6621
0402
L6620
0402
21
85
21
85
85
85
SPKRAMP_INR_P
SPKRAMP_INR_N
21
SPKRAMP_INSUB_P
21
SPKRAMP_INSUB_N
CRITICAL
C6611
0.0047UF
10%
25V
CERM
402
CRITICAL
C6620
0.033UF
10%
16V
X5R
402
21
21
CRITICAL
C6610
0.0047UF
10%
25V
CERM
402
CRITICAL
C6621
0.033UF
10%
16V
X5R
402
21
R6610
5%
1/16W
MF-LF
402
21
0
21
FC=1.2kHz typical
FC= 172 HZ typical
3DB with Rin=28k typical
1
C6607
0.1UF
10%
16V
2
X7R-CERM
0402
SSM2315_R_P
85
SSM2315_R_N
85
1
R6611
100K
5%
1/16W
MF-LF
402
2
SSM2315_SUB_P
85
SSM2315_SUB_N
85
C6608
0.1UF
X7R-CERM
0402
A3
B3
C2
B2
NC
1
10%
16V
2
A3
B3
C2
B2
NC
A1
PVDD
U6610
MAX98300
WLP
IN+
IN-
CRITICAL
NC
PGND
A2
A1
PVDD
U6620
MAX98300
WLP
IN+
IN-
CRITICAL
NC
PGND
A2
OUT+
OUT-
GAINSHDN*
OUT+
OUT-
GAINSHDN*
B1
C1
C3
SPKAMP1_GAIN
B1
C1
C3
SPKAMP2_GAIN
1
R6612
100K
5%
1/16W
MF-LF
402
2
1
R6622
100K
5%
1/16W
MF-LF
402
2
CRITICAL
1
C6601
47UF
20%
6.3V
2
TANT1
2012-LLP
CRITICAL
1
C6603
100UF
20%
6.3V
2
TANT
CASE-AL1
Gain Pin
Connect to VDD
Connect to VDD through 100k
Not connected
Connect to GND through 100k
Connect to GND
MIN_LINE_WIDTH=0.30 mm
MIN_NECK_WIDTH=0.20 MM
SPKRAMP_R_P_OUT
MIN_LINE_WIDTH=0.30 mm
MIN_NECK_WIDTH=0.20 MM
SPKRAMP_R_N_OUT
MIN_LINE_WIDTH=0.30 mm
MIN_NECK_WIDTH=0.20 MM
SPKRAMP_SUB_N_OUT
MIN_LINE_WIDTH=0.30 mm
MIN_NECK_WIDTH=0.20 MM
SPKRAMP_SUB_P_OUT
Gain dB
12
9
6
3
0
D
6
61 85
BI
6
61 85
OUT
C
6
61 85
OUT
6
61 85
OUT
SIZE
B
A
D
B
ALIAS OF PP5VLT_S3, MIN_LINE_WIDTH=0.60MM, MIN_NECK_WIDTH=0.20MM
=PP5V_S3_AUDIO_AMP
7
60
1
SSM2315_L_P
85
SSM2315_L_N
85
C6609
0.1UF
X7R-CERM
0402
10%
16V
2
A3
B3
C2
B2
NC
A1
PVDD
U6630
MAX98300
WLP
IN+
IN-
CRITICAL
NC
PGND
OUT+
OUT-
GAINSHDN*
B1
C1
C3
SPKAMP3_GAIN
A2
57 85
IN
57 85
IN
SPKRAMP_SHDN
60
AUD_LO2_P_L
AUD_LO2_N_L
L6631
FERR-1000-OHM
85
0402
L6630
FERR-1000-OHM
85
0402
21
SPKRAMP_INL_P
21
SPKRAMP_INL_N
CRITICAL
C6631
0.0047UF
10%
25V
CERM
402
21
CRITICAL
C6630
0.0047UF
10%
25V
CERM
402
21
A
6 3
1
R6632
100K
5%
1/16W
MF-LF
402
2
CRITICAL
1
C6605
47UF
20%
6.3V
2
TANT1
2012-LLP
MIN_LINE_WIDTH=0.30 mm
MIN_NECK_WIDTH=0.20 MM
SPKRAMP_L_P_OUT
MIN_LINE_WIDTH=0.30 mm
MIN_NECK_WIDTH=0.20 MM
SPKRAMP_L_N_OUT
6
61 85
OUT
6
61 85
OUT
SYNC_MASTER=KAVITHA_J30
PAGE TITLE
AUDI0: SPEAKER AMP
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
SYNC_DATE=07/25/2011
DRAWING NUMBER
051-9058
REVISION
6.0.0
BRANCH
PAGE
66 OF 109
SHEET
60 OF 86
124578
8 7 6 5 4 3
12
AUDIO JACK:LO/HP CONNECTOR, SPDIF TX
AUD_HS_MIC1_UNFILT
21
=PP3V3_S0_AUDIO
7
57 62
Place XW on/near Jack pin
D
APN:514-0671
J6700
SPDIF-TXRX-K24
F-RT-TH
CRITICAL
DETECT
SWITCH
LEFT
RIGHT
MIC
GND
6
5
2
1
3
4
AUD_CONNJ1_USMIC
MIN_LINE_WIDTH=0.4MM
MIN_NECK_WIDTH=0.2MM
AUD_CONNJ1_USGND
AUD_CONNJ1_USGND_DET
AUD_CONNJ1_TIPDET
AUD_CONNJ1_TIP
AUD_CONNJ1_RING
SM
XW6700
Place XW on/near Jack pin
XW6701
AUD_HS_MIC2_UNFILT
21
SM
L6701
FERR-1000-OHM
0402
CRITICAL
L6703
FERR-120-OHM-2.0A
0402
L6702
FERR-1000-OHM
0402
CRITICAL
L6706
FERR-120-OHM-2.0A
0402
21
21
21
21
AUD_HS_MIC1
AUD_HS_RET2
AUD_HS_MIC2
AUD_HS_RET1
58
OUT
58
OUT
58
OUT
58
OUT
D
AUDIO
PINS
7
8
9
10
11
12
13
CHASSIS GND STITCHES
XW6710
XW6711
R6760
1/16W
MF-LF
1
C6700
1UF
10%
6.3V
2
CERM
402
CRITICAL
DZ6705
6.8V-100PF
CRITICAL
DZ6701
6.8V-100PF
402
SM
21
SM
21
0
21
5%
402
2
1
1
DZ6704
6.8V-100PF
402
CRITICAL
2
402
2
1
CRITICAL
2
DZ6703
6.8V-100PF
402
1
DZ6700
ESDALC5-1BM2
CRITICAL
SOD882
1
2 1
C6701
100PF
2
5%
50V
CERM
0402
CRITICAL
L6704
FERR-120-OHM-2.0A
0402
CRITICAL
L6705
FERR-120-OHM-2.0A
0402
R6700
10K
21
5%
1/16W
MF-LF
402
R6701
4.7
21
5%
1/16W
MF-LF
402
21
21
A - VIN
B - VCC
OPERATING VOLTAGE 3.3
C - GND
POF
SHELL
SHIELD
C
GND_CHASSIS_AUDIO_JACK
VOLTAGE=0V
MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.1MM
B
AUD_SPDIF_OUT
AUD_HP_PORT_L
AUD_HP_PORT_R
AUD_J1_SLEEVEDET_R
AUD_J1_TIPDET_R
57
IN
ANALOG MIC CONNECTOR
57 59
BI
57 59
BI
62
OUT
62
OUT
APN:518S0520
BI_MIC_LO
6
62
BI_MIC_SHIELD
6
62
BI_MIC_HI
6
62
SPEAKER CONNECTOR
APN:518S0519
SPKRAMP_L_P_OUT
6
60 85
IN
SPKRAMP_L_N_OUT
6
60 85
IN
SPKRAMP_SUB_P_OUT
6
60 85
IN
SPKRAMP_SUB_N_OUT
6
60 85
IN
SPKRAMP_R_P_OUT
6
60 85
IN
CRITICAL
J6701
78171-0003
M-RT-SM
4
1
2
3
5
78171-0002
CRITICAL
78171-0004
CRITICAL
J6702
M-RT-SM
3
1
2
4
J6703
M-RT-SM
5
1
2
3
4
6
C
B
APN:518S0521
SPKRAMP_R_N_OUT
6
60 85
C6760 - C6763 ARE FOR FILTERING POTENTIAL FSB NOISE COUPLED ON SPKR LINES
A
6 3
IN
SYNC_MASTER=DIRK_J30
PAGE TITLE
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
AUDIO: JACK
SYNC_DATE=11/10/2011
DRAWING NUMBER
051-9058
REVISION
6.0.0
BRANCH
PAGE
67 OF 109
SHEET
61 OF 86
124578
SIZE
A
D
8 7 6 5 4 3
12
CODEC OUTPUT SIGNAL PATHS
FUNCTION
HP/LINE OUT
SATELLITES
SUB
SPDIF OUT
VOLUME
0X02 (2)
0X04 (4)
0X03 (3)
N/A
CONVERTER
0X02 (2)
0X04 (4)
0X03 (03)
0X08 (8)
PIN COMPLEX
0X09 (9,A)
0X0B (11)
0X0A (10)
0X10 (16)
CODEC INPUT SIGNAL PATHS
PIN COMPLEX
0X0D (13,B,RIGHT)
0X0D (13,V22,B,LEFT)
SYSTEM INTERRUPT
N/A
PANTHER_POINT GPIO5/PIRQH
PANTHER_POINT GPIO3/PIRQH
PORT A DETECT (HEADPHONES)
AUD_J1_SLEEVEDET_R_INV
62
D
3
1
R6812
220K
5%
1/16W
MF-LF
402
D
6
2
AUD_J1_SLEEVEDET_R_BUF
APN:376S1081
VOLTAGE=5V
APN:376S0634
4
S
SOT-563-HF
NTZD3152P
Q6804
D
3
AUD_J1_DET_RC2_INV
1
R6808
220K
5%
1/16W
MF-LF
402
2
GND_AUDIO_CODEC
57 62
21
10V
402
R6807
100K
1/20W
CONVERTER
0X06 (6)
0X06 (6)
SYSTEM GPIO
PANTHER_POINT GPIO16
N/A
N/A
DMC2400UV
P-CH
G
5
S
4
2
G
S
1
21
5%
1
MF
201
2
Q6803
SOT563
62
N-CH
PP4V5_AUDIO_ANALOG_FLT
62
MIN_LINE_WIDTH=0.1MM
MIN_NECK_WIDTH=0.1MM
5
G
C6803
0.1UF
10V
20%
CERM
402
AUD_SENSE_A
0
5%
1/16W
MF-LF
402
FUNCTION
BUILT-IN MIC
HEADSET MIC
FUNCTION
AUD_IPHS_SWITCH_EN
AUD_I2C_INT_L
AUD_IP_PERIPHERAL_DET
1
R6801
220K
5%
1/16W
MF-LF
402
2
TIPDET_UNFILT
21
SOUTHBRIDGE RESOURCES
21
R6804
150K
5%
1/16W
MF-LF
402
1
C6802
0.01UF
10%
16V
2
X7R-CERM
0402
AUD_J1_SLEEVEDET_R_INV
62
CRITICAL
L6801
FERR-1000-OHM
0402
C6804
0.1UF
10V
402
R6802
AUD_J1_DET_RC
100K
21
5%
1/20W
MF
201
62
21
1
20%
2
CERM
AUD_J1_DET_RC2
1
C6801
0.1UF
20%
2
CERM
D
57
OUT
PP4V5_AUDIO_ANALOG_FLT
62
C
AUD_J1_SLEEVEDET_R
61
IN
GND_AUDIO_CODEC
57 62
GND_AUDIO_CODEC
57 62
PP4V5_AUDIO_ANALOG
6
57
IN
B
61
IN
GND_AUDIO_CODEC
57 62
AUD_J1_TIPDET_R
NOSTUFF
R6830
A
CRITICAL
R6803
220K
5%
1/16W
MF-LF
402
2
G
MUTE CONTROL
N/A
GPIO_3
GPIO_3
N/A
VREF
MIC_BIAS (80%)
MIKEY
SSM6N37FEAPE
Q6801
SOT563
5
1
S
D
6
1
2
PORT B DETECT(SPDIF DELEGATE)
1
R6806
39.2K
1%
1/16W
MF-LF
402
2
AUD_PORTA_DET_L
3
D
SG
4
62
AUD_J1_SLEEVEDET_R_BUF
AUD_J1_DET_NMOS_DRN
SOT-563-HF
NTZD3152P
Q6804
SSM3K15AMFVAPE
R6809
AUD_J1_DET_NMOS_GATE
220K
5%
1/16W
MF-LF
402
DET ASSIGNMENT
0X09 (A)
N/A
N/A
0X0D (B)
DET ASSIGNMENT
N/A
MIKEY
CRITICAL
SSM6N37FEAPE
Q6801
Q6800
VESM
SOT563
2
1
NC
G S
1
R6805
20.0K
1%
1/16W
MF-LF
402
2
AUD_PORTB_DET_L
6
D
SG
1
APN:376S1017
3
D
2
7
57 61
I2C addresses: Mikey uses SMBus 0
MIKEY U6880 READ 0111 0011 0x73
MIKEY U6880 WRITE 0111 0010 0x72
=I2C_MIKEY_SCL
48 58
IN
=I2C_MIKEY_SDA
48 58
BI
AUD_CODEC_MICBIAS
57
IN
GND_AUDIO_CODEC
57 62
AUD_MIC_INP_R
57
OUT
AUD_MIC_INN_R
57
OUT
GND_AUDIO_CODEC
57 62
=PP3V3_S0_AUDIO
GND_AUDIO_CODEC
57 62
XW6851
MIKEY
L6880
FERR-1000-OHM
0402
PULLUPS for I2C ON PCH PAGE
AUD_I2C_INT_L
18
OUT
AUD_IPHS_SWITCH_EN
24
IN
AUD_MIC_INP_L
57
OUT
AUD_MIC_INN_L
57
OUT
CRITICAL
C6851
0.1UF
SM
21
21
R6850
100
1%
1/20W
MF
201
CRITICAL
C6850
0.1UF
21
10%
25V
X5R
402
21
10%
25V
X5R
R6853
402
2.4K
1%
1/20W
MF
201
R6810
10K
21
AUD_IP_PERIPHERAL_DET
5%
1/16W
MF-LF
402
EXTRACTION NOTIFICATION
18
OUT
6 3
PORT B LEFT(HEADSET MIC)
HP=80HZ, LP=8.82KHZ
MIN_LINE_WIDTH=0.10MM
MIN_NECK_WIDTH=0.10MM
VOLTAGE=3.3V
PP3V3_S0_AUDIO_F
CRITICAL
1
5%
402
2
MIKEY
CRITICAL
C6886
0.1UF
10%
25V
X5R
402
MIKEY
C6880
R6880
100K
1/16W
MF-LF
CRITICAL
21
1UF
10%
10V
X5R
402
402
5%
1
2
MIKEY
C6883
0.1UF
21
10%
25V
X5R
402
R6885
100K
1/16W
MF-LF
TIPDET_UNFILT
62
PORT B RIGHT(BUILT-IN MIC)
21
MIC_BIAS_FILT
CRITICAL
1
C6852
2.2UF
20%
6.3V
2
TANT
402-1
BI_MIC_HI_F
1
R6852
100K
5%
1/16W
MF-LF
402
2
21
BI_MIC_LO_F
CRITICAL
0.001UF
50V
HP=80HZ
1
2
C6853
X7R-CERM0402
C3
B3
D3
A3
A1
B2
R6851
2.4K
1/20W
10%
1
2
1%
MF
201
U6880
CD3282A1
WCSP
SCL
SDA
INT*
ENABLE
HDET
CS
HS_MIC_HI_RC
MIKEY
R6883
100K
5%
1/16W
MF-LF
402
21
1
2
CRITICAL
A2
MIKEY
AVDD
MICBIAS
DETECT
BYPASS
DGND
C2
D2
WCSP MIKEY 1A
APN:353S2640
C1
B1
HS_SW_DET
D1
HS_RX_BP
MIKEY
1
C6881
AGND
0.01UF
16V
10%
MIKEY
2
0402
1
2
C6884
X7R-CERM
MIKEY
0.0082UF
10%
X7R-CERM0402
CRITICAL
MIKEY
25V
R6884
2.2K
1/16W
MF-LF
FERR-1000-OHM
FERR-1000-OHM
5%
402
L6850
0402
L6851
0402
R6881
21
1K
1%
1/16W
MF-LF
402
1
2
21
BI_MIC_HI
21
BI_MIC_LO
BI_MIC_SHIELD
PAGE TITLE
AUDIO:Jack Translators
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
MIKEY
CRITICAL
1
C6882
2.2UF
20%
6.3V
2
TANT
402-1
GND_AUDIO_CODEC
EXT_MIC_BIAS
EXT_MIC_P
MIKEY
1
C6885
27PF
50V
5%
2
CERM 0402-1
CRITICAL
EXT_MIC_N
Apple Inc.
D
57 62
58
OUT
58
IN
C
58
IN
6
61
IN
SIZE
B
A
D
6
61
IN
6
61
IN
SYNC_DATE=02/20/2012SYNC_MASTER=DIRK_J30
DRAWING NUMBER
051-9058
REVISION
6.0.0
BRANCH
PAGE
68 OF 109
SHEET
62 OF 86
124578
8 7 6 5 4 3
12
MagSafe DC Power Jack
CRITICAL
J6900
78048-0573
M-RT-SM
1
2
3
4
D
5
ADAPTER_SENSE
6
PP18V5_DCIN_FUSE
6
MIN_LINE_WIDTH=1mm
MIN_NECK_WIDTH=0.20mm
VOLTAGE=18.5V
1
C6905
0.01UF
20%
50V
2
CERM
0603
518S0656
CRITICAL
F6905
6AMP-24V
1206-1
21
=PP3V42_G3H_ONEWIREPROT
1
C6908
0.1UF
20%
10V
2
CERM
402
PLACE_NEAR=U6901.5:1mm
45
BI
R6929
2.0K
402
MF-LF
1/16W
5%
SYS_ONEWIRE
CRITICAL
U6901
TC7SZ08FEAPE
SOT665
4
5
2
A
Y
1
B
3
SMC_BC_ACOK
21
4
1
VCC
CRITICAL
U6900
MAX9940
SC70-5
GND
2
SMC_BC_ACOK_VCC
5
EXTINT
NC
3
=PP18V5_DCIN_CONN
7
45 46
7
63
D
NC
1-Wire OverVoltage Protection
BIL CONNECTOR
=PP3V42_G3H_BATT
7
CRITICAL
J6955
CPB6312-0101F
C
=SMBUS_BATT_SDA
48 63
BI
=SMBUS_BATT_SCL
48 63
BI
46
SMC_BIL_BUTTON_L
6
45
TO SMC
47PF
CERM
50V
402
1
5%
2
C6954
0.001UF
X7R-CERM
0402
10%
50V
C6952
1
2
C6953
47PF
50V
CERM
402
1
5%
2
F-ST-SM
14 13
2
1
43
65
8 7
9
10
12 11
NC NC
16 15
516S0523
SMC_LID_R
6
C6951
0.1UF
20%
10V
CERM
402
R6961
100
21
5%
MF-LF
402
1/16W
1
1
C6955
0.001UF
10%
50V
2
2
X7R-CERM
0402
SMC_LID
45 46 53
C
CRITICAL
48 63
48 63
1
2
D6990
BAT30CWFILM
SOT-323
1
2
C6990
4.7UF
X5R-CERM
PPVIN_G3H_P3V42G3H
3
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.3 mm
VOLTAGE=18.5V
1
10%
35V
2
0805
CRITICAL
R6905
5.0
=PPBUS_G3H
7
64
B
518-0375
CRITICAL
J6950
BAT-K90-K91-K92
M-RT-TH
1
P1
2
P2
3
P3
4
P4
5
P5
6
P6
7
SHLD_PIN
SHLD_PIN
SHLD_PIN
SHLD_PIN
P7
8
P8
9
P9
10
11
12
13
A
=SMBUS_BATT_SCL
SYS_DETECT_L
6
=SMBUS_BATT_SDA
6
64
C6950
0.1UF
=PP18V5_DCIN_CONN
7
63
BATTERY CONNECTOR
PPVBAT_G3H_CONN
10%
25V
X5R
402
1
2
C6960
1UF
603-1
10%
25V
X5R
RCLAMP2402B
1
2
CRITICAL
PBUS_G3H_R
21
MIN_LINE_WIDTH=0.6 mm
5%
MIN_NECK_WIDTH=0.25 mm
1/3W
VOLTAGE=18.5V
MF-LF
0805
R6990
47
21
5%
1/3W
MF
0805
D6950
1
SC-75
P18V5_DCIN_CONN_R
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.3 mm
VOLTAGE=18.5V
2
R6950
10K
5%
1/16W
MF-LF
3
402
6 3
3.425V "G3Hot" Supply
Supply needs to guarantee 3.31V delivered to SMC VRef generator
1
R6995
1.00M
1%
1/8W
MF-LF
805
2
P3V42G3H_TON
P3V42G3H_FB
1
C6991
1UF
10%
25V
2
X5R
603-1
NC
3
TON
4
EN
8
VCC
2
FB
1
REF
353S2776
CRITICAL
7
VIN
U6990
PM6640
DFN
THRM
GND
PAD
5
P3V42G3H_REF3
10
REF3
9
BYP
6
SW
11
C6994
0.1UF
10%
16V
X5R
402-1
1
C6996
0.1UF
10%
16V
2
X5R
402-1
P3V42G3H_SW
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
SWITCH_NODE=TRUE
1
2
DIDT=TRUE
CRITICAL
33UH-20%-0.44A-0.455OHM
L6995
D52LC-SM
21
=PP3V42_G3H_REG
Vout = 3.465
350mA max output
f = 470 kHz
1
C6999
22UF
20%
6.3V
2
X5R-CERM-1
603
7
PAGE TITLE
DC-In & Battery Connectors
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
SYNC_DATE=07/29/2011SYNC_MASTER=JACK_J30
DRAWING NUMBER
051-9058
REVISION
6.0.0
BRANCH
PAGE
69 OF 109
SHEET
63 OF 86
124578
SIZE
B
A
D
8 7 6 5 4 3
R7091
0
Inrush Limiter
FROM ADAPTER
=PPDCIN_S5_CHGR
7
D
ACIN pin threshold is 3.2V, +/- 50mV
Divider sets ACIN threshold at 13.55V
Input impedance of ~40K meets
sparkitecture requirements
=PP3V42_G3H_CHGR
7
C
BATT_3S
R7012
1/16W
MF-LF
1
R7010
30.1K
1%
1/16W
MF-LF
402
2
402
1
1K
1%
2
47
SMC_RESET_L
45
IN
46
Float CELL for 1S
1
R7011
9.31K
1%
1/16W
MF-LF
402
2
BATT_2S
R7013
1K
1%
1/16W
MF-LF
402
B
1
R7015
100K
1%
1/16W
MF-LF
402
2
1
2
CHGR_VCOMP_R
1
R7042
0
5%
1/16W
MF-LF
402
2
R7016
CHGR_VNEG_R
1
C7016
470PF
10%
50V
2
CERM
0402
CHGR_ICOMP_RC
1
C7042
0.068UF
10%
10V
2
X5R-CERM
0402
C7002
1UF
1
C7015
330PF
5%
50V
2
COG
402
3.01K
1%
1/16W
MF-LF
402
1
10%
10V
2
X5R
402
GND_CHGR_AGND
R7000
0
5%
1/16W
MF-LF
402
1
2
21
NO STUFF
1
C7086
1UF
10%
25V
2
X5R
603-1
30mA max load
PP5V1_CHGR_VDD
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=5.1V
64
=SMBUS_CHGR_SCL
48
IN
=SMBUS_CHGR_SDA
48
BI
CHGR_VFRQ
73
IN
CHGR_CELL
CHGR_ACIN
CHGR_ICOMP
CHGR_VCOMP
CHGR_VNEG
CHGR_CSO_P
84
CHGR_CSO_N
84
1
C7050
1UF
10%
16V
2
X5R
402
1
C7085
0.1UF
10%
25V
2
X5R
402
CRITICAL
D7005
BAT30CWFILM
SOT-323
1
2
NO STUFF
1
R7002
100K
5%
1/16W
MF-LF
402
2
CHGR_RST_L
C7011
0.01UF
10%
16V
X7R-CERM
0402
1
R7085
470K
1%
1/16W
MF-LF
402
2
1
R7086
332K
1%
1/16W
MF-LF
402
2
3
PPCHGR_DCIN_D
64
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=18.5V
1
1
C7000
1UF
10%
10V
2
2
X5R
402-1
CHGR_AGATE_DIV
MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.3 mm
12
VHST
13
SMB_RST_N
11
SCL
10
SDA
4
VFRQ
6
CELL
3
ACIN
5
ICOMP
7
VCOMP
8
VNEG
18
CSOP
17
CSON
CRITICAL
Q7085
AON6405L
DFN5X6
OMIT
S
3 21
(CHGR_AGATE)
R7005
20
5%
1/16W
MF-LF
402
R7001
4.7
21
PP5V1_CHGR_VDDP
64
5%
1/16W
MF-LF
402
VDD
CRITICAL
(AGND)
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=5.1V
20
19
VDDP
DCIN
SGATE
U7000
AGATE
TQFN
CSIP
CSIN
BOOT
UGATE
ISL6259
PHASE
LGATE
BGATE
AMON
20V/V
BMON
36V/V
ACOK
(OD)
THRM_PAD
PGND
353S2929
29
22
XW7000
SM
21
PLACE_NEAR=U7000.29:1mm
PLACE_NEAR=U7000.22:1mm
C7005
0.22UF
D
PPDCIN_G3H_INRUSH_FET
5
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.3 MM
VOLTAGE=18.5V
G
4
21
(CHGR_DCIN)
C7001
1UF
2
PPCHGR_DCIN
64
26
CHGR_SGATE
1
CHGR_AGATE
28
CHGR_CSI_P
84
27
CHGR_CSI_N
84
25
CHGR_BOOT
24
CHGR_UGATE
23
CHGR_PHASE
21
CHGR_LGATE
16
CHGR_BGATE
9
CHGR_AMON
15
CHGR_BMON
14
=CHGR_ACOK
(GND)
(CHGR_CSO_P)
(CHGR_CSO_N)
1
20%
25V
2
X5R
603
GND_CHGR_AGND
64
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0V
10%
10V
X5R
402
1
C7087
4.7UF
10%
25V
2
X5R-CERM
0603
1
2
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
SWITCH_NODE=TRUE
DIDT=TRUE
Reverse-Current Protection
CRITICAL
Q7080
AON6405L
DFN5X6
OMIT
D
5
G
4
1
C7020
0.047UF
10%
10V
2
X5R-CERM
0402
C7022
0.1UF
R7025
1/16W
MF-LF
402
MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.6 mm
GATE_NODE=TRUE
DIDT=TRUE
50
OUT
50
OUT
46 50
OUT
1
C7026
0.001UF
10%
50V
2
X7R-CERM
0402
S
3 21
CHGR_SGATE_DIV
MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.3 mm
(CHGR_SGATE)
R7021
R7022
1
1
C7021
10%
25V
X5R
402
1
0
5%
2
0.1UF
10%
25V
2
2
X5R
402
CHGR_BOOT_R
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
1
C7025
0.22UF
10%
10V
2
CERM
402
PLACE_NEAR=U7000.25:2mm
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
GATE_NODE=TRUE
DIDT=TRUE
5
G
4
PPDCIN_G3H_INRUSH
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.4 mm
VOLTAGE=18.5V
1
R7080
100K
5%
1/16W
MF-LF
402
2
1
R7081
62K
5%
1/16W
MF-LF
402
2
10
21
5%
1/16W
MF-LF
402
10
21
5%
1/16W
MF-LF
402
4
OMIT
D
CRITICAL
Q7035
RJK03E1DNS
HWSON-8
S
321
R7051
R7052
85
85
G
2.2
0
CHGR_CSI_R_P
CHGR_CSI_R_N
5
OMIT
D
CRITICAL
Q7030
RJK03E1DNS
HWSON-8
S
321
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
SWITCH_NODE=TRUE
DIDT=TRUE
PART#
107S0129
CHGR_PHASE_RC
DIDT=TRUE
NO STUFF
1
C7039
470PF
10%
50V
2
CERM
0402
21
CHGR_CSO_R_P
85
1/16W MF-LF
5%
21
CHGR_CSO_R_N
85
1/16W MF-LF
5%
(PPVBAT_G3H_CHGR_R)(PPVBAT_G3H_CHGR_R)
(CHGR_BGATE)
PPCHGR_DCIN_D
64
CRITICAL
1
R7020
0.02
0.5%
1W
MF
RL1632W
432
PPDCIN_G3H_CHGR
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.4 mm
VOLTAGE=18.5V
Max Current = 8A
NO STUFF
R7039
402
402
DESCRIPTION
QTY
1
RES,5MOHM,1%,1W,0612,4-TERM
NO STUFF
R7093
0
21
5%
1/16W
MF-LF
402
NO STUFF
C7090
4.7UF
10%
35V
X5R-CERM
0805
(L7030 limit)
f = 400 kHz
CRITICAL
L7030
4.7UH-9.5A
IHLP4040DZ-SM
1
180
5%
1/10W
MF-LF
603
PPVBAT_G3H_CHGR_REG
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.4 mm
2
VOLTAGE=12.6V
CRITICAL
BATT_3S
R7050
0.01
0.5%
1W
MF
0612-3
PPCHGR_DCIN_D_R
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=18.5V
1
2
CRITICAL
1
C7030
22UF
20%
25V
2
POLY-TANT
CASE-D2-SM
21
21
43
REFERENCE DESIGNATOR(S)
5.5V "G3Hot" Supply
P5V5G3H_BOOST
DIDT=TRUE
6
VIN
U7090
LT3470A
SHDN*
CRITICAL
7
NC
1
2
PPVBAT_G3H_CHGR_R
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.4 mm
VOLTAGE=12.6V
R7050
NO STUFF
3
BOOST
DFN
SW
BIAS
FB
THRM
GND
PAD
9
5
CRITICAL
C7031
22UF
20%
25V
POLY-TANT
CASE-D2-SM
C7055
603-1
CRITICAL BOM OPTION
CRITICAL
1UF
10%
25V
X5R
48
2
1
P5V5G3H_SW
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
SWITCH_NODE=TRUE
DIDT=TRUE
P5V5G3H_FB
Vout = 1.25V * (1 + Ra / Rb)
1
C7035
1UF
10%
25V
2
X5R
603-1
PLACE_NEAR=Q7030.5:1mm
CRITICAL
1
C7040
22UF
20%
25V
2
POLY-TANT
CASE-D2-SM
1
C7056
0.1UF
10%
16V
2
X5R
402-1
BATT_2S
NO STUFF
C7094
0.22UF
10%
10V
CERM
402
1
C7036
1UF
10%
25V
2
X5R
603-1
1
C7057
0.01UF
2
X7R-CERM
1
2
NO STUFF
CRITICAL
L7095
33UH-20%-0.39A-0.435OHM
DP418C-SM
NO STUFF
1
C7095
22PF
5%
50V
2
NP0-C0G-CERM
0201
R7095
NO STUFF
R7096
1
C7037
0.001UF
10%
50V
2
X7R-CERM
0402
PLACE_NEAR=C7036.1:3mm
CRITICAL
F7040
1
C7045
0.001UF
10%
50V
2
X7R-CERM
0402
0402
TABLE_5_HEAD
TABLE_5_ITEM
10%
16V
8AMP-24V
1
2
1206
21
CRITICAL
AON6403L
S
3
2
1
Q7055
<Ra>
681K
1/20W
<Rb>
200K
1/20W
201
DFN5X6
SYM-VER-2
OMIT
G
4
21
1%
MF
201
1%
MF
NO STUFF
1
2
1
2
D
1
2
5%
1/16W
MF-LF
402
R7092
0
5%
1/16W
MF-LF
402
PP5V5_CHGR_VDDP
NO STUFF
CRITICAL
C7098
10UF
20%
10V
X5R
603
TO SYSTEM
=PPBUS_G3H
TO/FROM BATTERY
5
PPVBAT_G3H_CONN
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.4 mm
VOLTAGE=12.6V
12
NO STUFF
21
PP5V1_CHGR_VDDP
NO STUFF
21
PPCHGR_DCIN
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=5.5V
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=5.5V
Vout = 5.506V
200MA MAX OUTPUT
(Switcher limit)
NO STUFF
CRITICAL
1
C7099
10UF
20%
10V
2
X5R
603
64
64
D
C
7
63
B
6
63
A
PART NUMBER
376S0927
376S0966
K6 NOTES : L7030 CHANGED BACK TO K24 IND DUE TO LAYOUT
QTY
2
2
DESCRIPTION
FDMC3020DC
RJK03E1DNS
REFERENCE DES
Q7030,Q7035
Q7030,Q7035
CRITICAL
CRITICAL
CRITICAL
BOM OPTION
CHARGER_POWER_FET:FAIR
CHARGER_POWER_FET:REN
PART NUMBER
376S0761 SI7137DP CRITICAL
376S0845 SI7149DP CRITICAL
376S0845 SI7149DP CRITICAL
QTY
1
1
1
DESCRIPTION
REFERENCE DES
Q7055
Q7080
Q7085
CRITICAL
6 3
BOM OPTION
PAGE TITLE
PBus Supply & Battery Charger
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
SYNC_DATE=09/27/2011SYNC_MASTER=JACK_J30
DRAWING NUMBER
051-9058
REVISION
6.0.0
BRANCH
PAGE
70 OF 109
SHEET
64 OF 86
124578
SIZE
A
D
8 7 6 5 4 3
System Agent Power Supply
12
D
=PPVIN_S0_VCCSAS0
7
=PP5V_S0_VCCSAS0
7
1
R7101
2.2
5%
1/16W
MF-LF
402
PP5V_S0_VCCSAS0_VCC
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=5V
73
C
CPU_VCCSASENSE
12
IN
VCCSAS0_RTN
XW7101
PLACE_NEAR=C1761.2:1mm
2
SM
1
B
R7151
1.62K
1%
1/16W
MF-LF
402
R7153
1.62K
1%
1/16W
MF-LF
402
1
C7106
10PF
5%
50V
2
C0G-CERM
0402
21
1
R7147
41.2K
1%
1/16W
MF-LF
402
1
2
2
1
R7148
52.3K
1%
1/16W
MF-LF
402
2
R7150
82.5K
21
1%
1/16W
MF-LF
402
VCCSAS0_SET_R
1
R7149
499K
1%
1/16W
MF-LF
402
2
21
C7103
0.022UF
10%
16V
X5R-X7R-CERM
0402
1
R7154
4.64K
1%
1/16W
MF-LF
402
2
1
R7152
4.64K
1%
1/16W
MF-LF
402
2
1
C7105
10PF
5%
50V
2
C0G-CERM
0402
IN
73
OUT
1
C7102
2.2UF
10%
16V
2
X5R
603
R7103
12
12
=PVCCSA_EN
CPU_VCCSASENSE_DIV
VCCSAS0_SREF
VCCSAS0_VO
VCCSAS0_OCSET
PVCCSA_PGOOD
VCCSAS0_RTN_DIV
VCCSAS0_FSEL
VCCSAS0_SET0
1
VCCSAS0_SET1
0
5%
1/16W
MF-LF
402
2
CPU_VCCSA_VID<1>
IN
CPU_VCCSA_VID<0>
IN
VCCSAS0_AGND
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0V
14
13
INTEL TABLE:
2
19
VCC
U7100
ISL95870A
EN
CRITICAL
FB
OMIT_TABLE
SREF
VO
OCSET
PGOOD
RTN
FSEL
SET0
SET1
VID0
(ENDIAN SWAP)
VID1
XW7100
SM
PLACE_NEAR=U7100.3:1mm
GND
UTQFN
3
15 18
10
7
12
11
4
8
9
6
5
CRITICAL
1
C7101
10UF
20%
10V
2
X5R
603
20
PVCC
BOOT
UGATE
PHASE
LGATE
PGND
2
21
VCCSAS0_BOOT_RC
MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
DIDT=TRUE
VCCSAS0_VBST
MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
DIDT=TRUE
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
17
16
1
GATE_NODE=TRUE
DIDT=TRUE
VCCSAS0_LL
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
SWITCH_NODE=TRUE
DIDT=TRUE
VCCSAS0_DRVL
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
GATE_NODE=TRUE
DIDT=TRUE
(VCCSAS0_OCSET)
(VCCSAS0_VO)
R7130
5%
1/10W
MF-LF
603
VCCSAS0_DRVH
PART NUMBER
353S3074
CRITICAL
C7130
0.22UF
10%
10V
CERM
402
1
6
39UF-0.027OHM
376S0944
2
543
1
1
0
2
2
QTY
IC,ISL95870A,PWM,2BIT-VID,RMOT-SNSE,20P
1
C7120
20%
16V
POLY
B1A-SM
CRITICAL
Q7100
RJK0222DNS
HWSON
7
R7141
1/16W
MF-LF
DESCRIPTION
1
C7121
2
PLACE_NEAR=Q7100.2:1mm
CRITICAL
L7100
1.0UH-7.7A
FDV0630H-SM
152S0913
1
1K
1%
C7140
402
2
1000PF
NP0-C0G
1UF
603-1
2 1
5%
25V
402
10%
25V
X5R
1
2
21
VCCSAS0_CS_P
85
VCCSAS0_CS_N
85
1
R7142
1K
1%
1/16W
MF-LF
402
2
1
C7122
1000PF
5%
25V
2
NP0-C0G
402
PLACE_NEAR=C7121.1:3mm
PPVCCSA_S0_REG_R
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.05V
REFERENCE DES
U7100
CRITICAL
R7140
0.001
1%
1W
MF-1
0612
21
43
OCP = R7141 x 8.5uA / R7140
OCP = 8.5A
CRITICAL
BOM OPTION
CRITICAL
=PPVCCSA_S0_REG
6A Max Output
f = 300 kHz
7
D
C
B
VID1 VID0 Voltage
0 0 0.9V
1 0 0.8V
0 1 0.725V
1 1 0.675V
A
.
6 3
SYNC_MASTER=JACK_J30 SYNC_DATE=09/28/2011
PAGE TITLE
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
System Agent Supply
Apple Inc.
R
DRAWING NUMBER
051-9058
REVISION
6.0.0
BRANCH
PAGE
71 OF 109
SHEET
65 OF 86
124578
SIZE
A
D
8 7 6 5 4 3
12
5V_S3/3.3V_S5 POWER SUPPLY
D
D
C
=PPVIN_S5_5VS3
7
66
MAX CURRENT = 12.947A
PWM FREQ. = 300 KHZ
B
=PP5V_S3_REG
7
1
C7293
0.001UF
20%
50V
2
CERM
402
1
C7282
0.001UF
20%
50V
2
CERM
402
PLACE_NEAR=C7281.1:3MM
1
C7290
10UF
20%
10V
2
X5R
603
1
2
1
2
CRITICAL
C7291
220UF
20%
6.3V
ELEC
D1A-SM
CRITICAL
C7280
82UF
20%
16V
ELEC
B6S-SM
PLACE_NEAR=L7260.1:1 MM
7
66
PLACE_NEAR=C7291.1:1 MM
1
C7281
1UF
10%
25V
2
X5R
603-1
PLACE_NEAR=Q7260.5:1MM
OMIT
CRITICAL
Q7260
RJK03E1DNS
HWSON-8
CRITICAL
L7260
4.7UH-13A-15MOHM
PCMB104E4R7-SM
RJK03E0DNS
VOUT = (2 * RA / RB) + 2
XW7203
SM
2 1
=PPVIN_S5_5VS3
XW7202
SM
2 1
5
D
G
S
3 21
21
OMIT
CRITICAL
Q7261
HWSON-8
3 21
4
5
D
G
S
5V_S3_VFB_XW7203
C7260
0.1UF
10%
16V
X7R-CERM
0402
2 1
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
DIDT=TRUE
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
DIDT=TRUE
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
DIDT=TRUE
4
P5VS3_VBST_R
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
DIDT=TRUE
<RA> <RB>
R7267
21K
1%
1/16W
MF-LF
402
21
R7268
13.7K
1%
1/16W
MF-LF
402
=P5V3V3_REG_EN
73
1
2
P5VP3V3_VREF
1
C7271
0.22UF
10%
10V
2
CERM
402
R7260
0
5%
MIN_LINE_WIDTH=0.6 MM
1/16W
MIN_NECK_WIDTH=0.2 MM
MF-LF
DIDT=TRUE
402
21
P5VS3_VBST
P5VS3_DRVH
P5VS3_LL
P5VS3_DRVL
P5VS3_VO1
P5VS3_VFB
P5VS3_ENTRIP
1
R7271
115K
1%
1/16W
MF-LF
402
2
C7272
1UF
10%
25V
X5R
603-1
14
SKIPSEL
4
TONSEL
VBST1
DRVH1
LL1
DRVL1
VO1
VFB1
ENTRIP1
21
16
VIN
CRITICAL
U7200
GND
15
<RD>
R7269
10K
1%
1/16W
MF-LF
402
P5VP3V3_REG3
3
VREF
VREG3
VREG5
VBST2
DRVH2
QFN
LL2
DRVL2
VO2
TPS51125
VFB2
ENTRIP2
VCLK
PGOOD
EN0
THRM_PAD
25
VOUT = (2 * RC / RD) + 2
<RC>
R7270
6.49K
1%
1/16W
MF-LF
21
R7273
100K
5%
1/16W
MF-LF
402
8
17
PP5V_S5_LDO
922
P3V3S5_VBST
1021
P3V3S5_DRVH
1120
P3V3S5_LL
1219
P3V3S5_DRVL
724
P3V3S5_VO2
52
P3V3S5_VFB
61
P3V3S5_ENTRIP
18
NC
23
13
5V3V3_REG_EN
1
2
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
DIDT=TRUE
402
=PP5V_S5_LDO
1
C7270
1UF
20%
10V
2
CERM
603
R7220
0
5%
1/16W
MF-LF
402
21
1
C7273
10UF
20%
6.3V
2
X5R
603
21
3V3S5_VFB_R7270
7
C7220
0.1UF
X7R-CERM
P3V3S5_VBST_R
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
DIDT=TRUE
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
DIDT=TRUE
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
DIDT=TRUE
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
DIDT=TRUE
1
R7272
78.7K
1%
1/16W
MF-LF
402
2
XW7204
PLACE_NEAR=L7220.2:1 MM
1
10%
16V
2
0402
SM
2 1
1
6
XW7205
SM
2 1
C
1
C7241
1UF
10%
25V
2
X5R
603-1
2
543
PLACE_NEAR=Q7220.2:1MM
CRITICAL
Q7220
RJK0216DPA
WPAK2
7
CRITICAL
1
C7240
82UF
20%
16V
2
ELEC
B6S-SM
CRITICAL
L7220
2.2UH-14A
IHLP2525CZ-SM1
21
CRITICAL
1
C7251
150UF
20%
6.3V
2
POLY
B1A-SM
1
C7242
0.001UF
20%
50V
2
CERM
402
PLACE_NEAR=C7241.1:3MM
1
C7250
10UF
20%
6.3V
2
X5R
603
=PPVIN_S5_3V3S5
=PP3V3_S5_REG
1
C7253
0.001UF
20%
50V
2
CERM
402
7
B
7
GND_5V3V3S5_SGND
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=0V
Q7221
6
D
SSM6N37FEAPE
SOT563
2
SG
=P5VS3_EN_L
73
IN
A
PART NUMBER
376S0927
376S0928
376S0966
376S0895
QTY
1
1
1
1
DESCRIPTION
FDMC3020DC
FDMC2514SDC
RJK03E1DNS
RJK03E0DNS
REFERENCE DES
Q7260
Q7261
Q7260
Q7261
CRITICAL
1
BOM OPTION
5V_S3_POWER_FET:FAIR
5V_S3_POWER_FET:FAIR
5V_S3_POWER_FET:REN
5V_S3_POWER_FET:REN
73
IN
=P3V3S5_EN_L
Q7221
3
D
SSM6N37FEAPE
SOT563
5
SG
4
SEPERATED MASTER PGOOD FOR BOTH 5V AND 3V3.
21
XW7201
SM
PLACE_NEAR=U7200.25:1 MM
P5V3V3_PGOOD
73
PAGE TITLE
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
6 3
MAX CURRENT = 7.45A
PWM FREQ. = 375 KHZ
5V/3.3V SUPPLY
SYNC_DATE=08/22/2011SYNC_MASTER=JACK_J30
DRAWING NUMBER
051-9058
REVISION
6.0.0
BRANCH
PAGE
72 OF 109
SHEET
66 OF 86
124578
SIZE
A
D
8 7 6 5 4 3
12
D
C
B
NO STUFF
NO STUFF
7
31
IN
8
26
IN
73
IN
DDRREG_1V8_VREF
C7315
X7R-CERM
1
R7319
150K
1%
1/16W
MF-LF
402
2
DDRREG_P1V35_L
Q7319
3
D
SSM3K15AMFVAPE
VESM
1
GS
2
MEM_VDD_SEL_1V5_L
=PP5V_S3_DDRREG
DDRREG_FB
=DDRVTT_EN
=DDRREG_EN
1
0.1UF
10%
16V
2
0402
PLACE_NEAR=U7300.6:1mm
GND_DDRREG_SGND
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.17 mm
VOLTAGE=0V
1
R7315
20.0K
1%
1/16W
MF-LF
402
2
PLACE_NEAR=U7300.8:5mm
1
R7316
100K
1%
1/16W
MF-LF
402
2
PLACE_NEAR=U7300.8:5mm
=PPVIN_S0_DDRREG_LDO
7
C7300
10UF
PLACE_NEAR=U7300.12:1mm
1
C7316
0.01UF
10%
16V
2
X7R-CERM
0402
PLACE_NEAR=U7300.8:1mm
23
IN
1
20%
10V
2
X5R
603
PLACE_NEAR=U7300.19:3mm
VDDQ/VTTREF Enable
1
R7317
200K
1%
1/16W
MF-LF
402
2
VTT Enable
DDRREG_MODE
DDRREG_TRIP
1
R7318
66.5K
1%
1/16W
MF-LF
402
2
PLACE_NEAR=U7300.18:3mm
C7301
10UF
20%
10V
X5R
603
PLACE_NEAR=U7300.2:1mm
17
16
6
8
19
18
V5IN
S3
S5
VREF
REFIN
MODE
TRIP
1
2
TPS51916
CRITICAL
PGND
10
2
VLDOIN
U7300
QFN
VTT
GND
7
4
VDDQSNS
THRM
PADGND
VBST
DRVH
SW
DRVL
PGOOD
VTT
VTTSNS
VTTREF
21
XW7300
=PPVIN_S3_DDRREG
7
MIN_NECK_WIDTH=0.17 mm
MIN_LINE_WIDTH=0.6 mm
DDRREG_VBST
1512
DDRREG_DRVH
14
DDRREG_LL
13
SWITCH_NODE=TRUE
DIDT=TRUE
DDRREG_DRVL
11
DDRREG_PGOOD
20
DDRREG_VDDQSNS
9
=PPVTT_S0_DDR_LDO
7
3
1
DDRREG_VTTSNS
=PPVTT_S3_DDR_BUF
5
10mA max load
2
C7350
0.22UF
SM
PLACE_NEAR=U7300.21:1mm
CERM
1
GATE_NODE=TRUE
DIDT=TRUE
GATE_NODE=TRUE
DIDT=TRUE
OUT
C7360, C7361 close to memory
1
10%
10V
2
402
CRITICAL
1
C7330
39UF-0.027OHM
20%
16V
2
POLY
B1A-SM
R7325
5%
1/16W
0
8
SM
CRITICAL
C7360
10UF
20%
6.3V
X5R
603
21
MF-LF
21
402
XW7360
PLACE_NEAR=C7361.1:3mm
PLACE_NEAR=C3101.1:1mm
1
2
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.17 mm
DDRREG_VBST_RC
MIN_NECK_WIDTH=0.17 mm
MIN_LINE_WIDTH=0.6 mm
CRITICAL
1
1
C7361
10UF
20%
6.3V
2
2
X5R
603
PLACE_NEAR=C3101.1:3mm
CRITICAL
C7331
39UF-0.027OHM
20%
16V
POLY
B1A-SM
PLACE_NEAR=Q7330.5:1mm
(DDRREG_LL)
(DDRREG_DRVL)
(DDRREG_VDDQSNS)
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.17 mm
1
C7332
1UF
10%
25V
2
X5R
603-1
PLACE_NEAR=C7332.1:3mm
(DDRREG_DRVH)
C7325
0.1UF
21
10%
25V
X5R
402
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.17 mm
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.17 mm
4
1
C7333
0.001UF
10%
50V
2
X7R-CERM
0402
4
G
G
5
5
D
S
D
S
321
CRITICAL
Q7335
RJK0226DNS
HVSON-333
OMIT
321
CRITICAL
1
C7334
33UF
20%
16V
2
POLY-TANT
CASED2E-SM
NO STUFF
CRITICAL
Q7330
RJK0225DNS
HVSON-3333
OMIT
0.88UH-20%-19A-2.3MOHM
CRITICAL
L7330
MPCG1040LR88-SM
21
PART NUMBER
CRITICAL
1
C7340
330UF
20%
2.0V
2
POLY-TANT
CASE-B2-SM1
CRITICAL
C7341
330UF
POLY-TANT
CASE-B2-SM1
ALTERNATE FOR
PART NUMBER
128S0218128S0299
128S0218128S0093
20%
2.0V
D
BOM OPTION
REF DES
ALL
ALL
COMMENTS:
TABLE_ALT_HEAD
TABLE_ALT_ITEM
TABLE_ALT_ITEM
C
=PPDDR_S3_REG
Vout = 1.5V
14.1A max output
1
C7346
0.001UF
10%
50V
2
X7R-CERM
1
1
C7345
10UF
20%
6.3V
2
2
X5R
603
0402
2
XW7301
SM
1
PLACE_NEAR=C7340.1:1mm
(Q7335 limit)
f = 400 kHz
B
PART NUMBER
376S0874
QTY
1
1
DESCRIPTION
FDMC0225
FDMC0202S
A
REFERENCE DES
Q7330376S0979
Q7335
CRITICAL
BOM OPTION
DDR_POWER_FET:FAIR
DDR_POWER_FET:FAIR
6 3
SYNC_MASTER=JACK_J30 SYNC_DATE=07/28/2011
PAGE TITLE
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
1.5V DDR3 Supply
Apple Inc.
R
DRAWING NUMBER
051-9058
REVISION
6.0.0
BRANCH
PAGE
73 OF 109
SHEET
67 OF 86
124578
SIZE
A
D
8 7 6 5 4 3
12
=PP5V_S0_CPUIMVP
R7401
10
PP5V_S0_CPUIMVP_VCC
68
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
D
C
B
VOLTAGE=5V
10 45 46 78
OUT
1
R7468
5.76K
1%
1/16W
MF-LF
402
2
1
CRITICAL
R7469
100KOHM
0402
2
PLACE_NEAR=Q7510.1:1mm
PLACE_NEAR=Q7550.1:1mm
CPU_PROCHOT_L
1
R7466
5.76K
1%
1/16W
MF-LF
402
2
1
CRITICAL
R7467
100KOHM
0402
2
=PPVCCIO_S0_CPUIMVP
7
1
C7450
43PF
5%
50V
2
C0G-CERM
0402
OMIT
1
R7464
NOSTUFF
NONE
NONE
NONE
402
2
1
R7465
200K
1%
1/16W
MF-LF
402
2
73
IN
12 78
IN
12 78
IN
12 78
IN
R7479
PLACE_NEAR=U7400.18:2mm
CPUIMVP_VR_ON
CPU_VIDSOUT
CPU_VIDSCLK
CPU_VIDALERT_L
1
R7462
196K
1%
1/16W
MF-LF
402
2
1
R7463
137K
1%
1/16W
MF-LF
402
2
CPUIMVP_ISUMG_AVE_P
69
IN
54.9
1/16W
MF-LF
402
1
1
R7480
130
1%
1%
1/16W
MF-LF
402
2
2
PLACE_NEAR=U7400.16:2mm
1
R7460
215K
1%
1/16W
MF-LF
402
2
1
R7461
137K
1%
1/16W
MF-LF
402
2
GND_CPUIMVP_SGND
CPUIMVP_AXG_PWM2
69
OUT
CPUIMVP_PGOOD
24
OUT
CPUIMVP_AXG_PGOOD
73
OUT
CPUIMVP_NTC
CPUIMVP_NTCG
CPUIMVP_SLEW
CPUIMVP_IMAXA
CPUIMVP_IMAXB
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0V
C7401
2.2UF
20%
10V
X5R-CERM
402
C7441
1000PF
X7R-CERM
10%
16V
0201
1
2
46
VCC
U7400
MAX15119GTM
13
DRVPWMB
37
DRVPWMA
NC
45
4
24
12
47
21
23
22
39
40
38
35
36
8
1
2
1
2
CRITICAL
CSPA3
VRHOT*
POKA
POKB
EN
VDIO
CLK
ALERT*
THERMA
THERMB
SR
IMAXA
IMAXB
CSPBAVE
AGND
GNDSA
2
5
20
C7440
1000PF
10%
16V
X7R-CERM
0201
CPU_VCCSENSE_R
NO STUFF
1
C7442
1000PF
10%
16V
2
X7R-CERM
0201
PLACE HOLDER PLACE HOLDER
21
5%
1/16W
MF-LF
402
19
29
VDDB
VDDA
QFN
TONB
TONA
BSTA1
27
DHA1
LXA1
DLA1
CSPA1
CSPAAVE
CSNA
FBA
CSPA2
BSTA2
DHA2
LXA2
DLA2
BSTB
DHB
LXB
DLB
CSPB2
CSPB1
CSNB
FBB
PAD
THRM
GNDSB
PGNDA
7
PGNDB
49
17
30
XW7400
2 1
CPU_AXG_SENSE_R
NO STUFF
1
C7443
1000PF
10%
16V
2
X7R-CERM
0201
1
CPUIMVP_TONB
48
CPUIMVP_TONA
25
CPUIMVP_BOOT1
CPUIMVP_UGATE1
26
CPUIMVP_PHASE1
28
CPUIMVP_LGATE1
42
CPUIMVP_ISUM1_P
41
CPUIMVP_ISUM
43
CPUIMVP_ISUM_N
3
CPUIMVP_FBA
44
CPUIMVP_ISUM2_P
34
CPUIMVP_BOOT2
32
CPUIMVP_UGATE2
33
CPUIMVP_PHASE2
31
CPUIMVP_LGATE2
14
CPUIMVP_BOOT1G
16
CPUIMVP_UGATE1G
15
CPUIMVP_PHASE1G
18
CPUIMVP_LGATE1G
11
9
10
6
CPUIMVP_FBB
SM
R7441
10
5%
1/20W
MF
201
1
C7402
2.2UF
20%
10V
2
X5R-CERM
402
PLACE_NEAR=U7400.19:2mm
PLACE_NEAR=U7400.29:2mm
Note: value needs scrubbing
NO STUFF
1
C7418
100PF
5%
25V
2
NP0-CERM
0201
R7440
10
21
CPU_AXG_SENSE_N
5%
1/20W
MF
201
21
CPU_VCCSENSE_N
R7403
182K
1%
1/16W
MF-LF
402
NO STUFF
1
C7419
100PF
5%
25V
2
NP0-CERM
0201
1
C7403
2.2UF
20%
10V
2
X5R-CERM
402
21
OUT
OUT
OUT
OUT
68
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
68
69
69
69
69
69
69
69
69
69
69
69
69
R7402
150K
1%
1/16W
MF-LF
402
NO STUFF
1
C7414
100PF
5%
25V
2
NP0-CERM
0201
21
12 78
IN
12 78
IN
7
69
NO STUFF
1
C7415
100PF
5%
25V
2
NP0-CERM
0201
=PPVIN_S0_CPUIMVP
69
IN
OUT
NO STUFF
1
C7416
100PF
5%
25V
2
NP0-CERM
0201
NO STUFF
1
C7423
100PF
5%
25V
2
NP0-CERM
0201
CPUIMVP_FBA
68
CPUIMVP_FBB
68
7
69
R7406
200
21
CPUIMVP_ISNS1_P
5%
1/20W
MF
201
R7407
200
21
CPUIMVP_ISNS2_P
5%
NO STUFF
C7408
150PF
21
69
OUT
69
10%
25V
X7R-CERM
0201
C7409
1000PF
X7R-CERM
CPUIMVP_ISUM_R
21
10%
16V
0201
R7410
1
5%
1/20W
MF
201
21
1/20W
MF
201
PP5V_S0_CPUIMVP_VCC
AXG_PHASE1
1
R7430
0
5%
1/16W
MF-LF
402
2
CPUIMVP_ISUMG2_P
CPUIMVP_ISUMG1_P
CPUIMVP_ISUMG_N
49 69 85
IN
49 69 85
IN
68
69
IN
69
IN
69 85
IN
D
C
NO STUFF
C7452
100PF
21
5%
25V
NP0-CERM
0201
R7412
7.68K
1%
1/20W
MF
201
R7422
8.25K
1%
1/20W
MF
201
C7462
100PF
21
5%
25V
NP0-CERM
0201
NO STUFF
1
C7412
2
21
CPUIMVP_FBA_R
21
CPUIMVP_FBB_R
1000PF
10%
16V
X7R-CERM
0201
1
C7422
1000PF
10%
16V
2
X7R-CERM
0201
R7413
10
5%
1/20W
MF
201
R7423
10
5%
1/20W
MF
201
21
21
CPU_VCCSENSE_P
CPU_AXG_SENSE_P
12 78
IN
12 78
IN
B
A
6 3
SYNC_MASTER=JACK_J30 SYNC_DATE=08/03/2011
PAGE TITLE
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
CPU IMVP7 & AXG VCore Regulator
Apple Inc.
R
DRAWING NUMBER
051-9058
REVISION
BRANCH
PAGE
SHEET
6.0.0
74 OF 109
68 OF 86
124578
SIZE
A
D
8 7 6 5 4 3
=PPVIN_S0_CPUIMVP
7
68 69
PHASE 1
CPUIMVP_BOOT1
68
IN
MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.2 MM
CPUIMVP_UGATE1
68
IN
D
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM
68
68
DIDT=TRUE
GATE_NODE=TRUE
CPUIMVP_PHASE1
IN
MIN_LINE_WIDTH=1.5 MM
MIN_NECK_WIDTH=0.2 MM
CPUIMVP_LGATE1
IN
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM
R7515
=PPVIN_S0_CPUIMVP
7
68 69
PHASE 2
CPUIMVP_BOOT2
68
IN
MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.2 MM
C
CPUIMVP_UGATE2
68
IN
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM
68
IN
68
IN
GATE_NODE=TRUE
DIDT=TRUE
CPUIMVP_PHASE2
MIN_LINE_WIDTH=1.5 MM
MIN_NECK_WIDTH=0.2 MM
CPUIMVP_LGATE2
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM
=PPVIN_S0_CPUAXG
7
CPUIMVP_UGATE1G_R
MIN_NECK_WIDTH=0.25 MM
MIN_LINE_WIDTH=0.5 MM
AXG PHASE 1
B
CPUIMVP_BOOT1G
68
IN
MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.2 MM
CPUIMVP_UGATE1G
68
IN
MIN_NECK_WIDTH=0.2 MM
MIN_LINE_WIDTH=0.5 MM
68
68
IN
IN
DIDT=TRUE
GATE_NODE=TRUE
CPUIMVP_PHASE1G
MIN_LINE_WIDTH=1.5 MM
MIN_NECK_WIDTH=0.2 MM
CPUIMVP_LGATE1G
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM
CPUIMVP_BOOT1_RC
MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.2 MM
R7511
3.3
5%
1/16W
MF-LF
402
DIDT=TRUE
1
21
CPUIMVP_UGATE1_R
MIN_LINE_WIDTH=0.5 MM
5%
MIN_NECK_WIDTH=0.2 MM
1/16W
MF-LF
402
DIDT=TRUE
SWITCH_NODE=TRUE
DIDT=TRUE
GATE_NODE=TRUE
R7521
R7525
1
21
5%
1/16W
MF-LF
402
DIDT=TRUE
SWITCH_NODE=TRUE
DIDT=TRUE
GATE_NODE=TRUE
CPUIMVP_BOOT1G_RC
MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.25 MM
1
R7551
2.2
5%
1/16W
MF-LF
402
2
DIDT=TRUE
R7555
DIDT=TRUE
SWITCH_NODE=TRUE
DIDT=TRUE
GATE_NODE=TRUE
DIDT=TRUE
1
1
C7511
0.22UF
10%
1
2
DIDT=TRUE
1
2
10V
2
CERM
402
DIDT=TRUE
GATE_NODE=TRUE
2
CPUIMVP_BOOT2_RC
MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.25 MM
2.2
5%
1/16W
MF-LF
402
DIDT=TRUE
CPUIMVP_UGATE2_R
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.25 MM
DIDT=TRUE
GATE_NODE=TRUE
DIDT=TRUE
C7551
0.22UF
10%
10V
CERM
402
1
21
5%
1/16W
MF-LF
402
1
C7521
0.22UF
10%
10V
2
CERM
402
DIDT=TRUE
GATE_NODE=TRUE
3
4
5
376S1005
CRITICAL
Q7510
CSD58872Q5D
SON5X6
TG
3
TGR
4
BG
5
Q7520
CSD58872Q5D
TG
3
TGR
4
BG
5
376S1005
376S1005
CRITICAL
Q7550
CSD58872Q5D
SON5X6
TG
TGR
BG
VIN
VSW
PGND
9
CRITICAL
SON5X6
PGND
9
VIN
VSW
PGND
9
CRITICAL
1
C7513
82UF
20%
16V
2
ELEC
B6S-SM
1
6
7
8
CRITICAL
1
C7523
82UF
20%
16V
2
ELEC
B6S-SM
VIN
1
VSW
6
7
8
CRITICAL
1
C7553
2
1
6
CPUIMVP_VSWG
MIN_LINE_WIDTH=0.5 MM
7
MIN_NECK_WIDTH=0.25 MM
SWITCH_NODE=TRUE
8
DIDT=TRUE
CRITICAL
1
C7514
82UF
20%
16V
2
ELEC
B6S-SM
PPVCORE_S0_CPU_PH1_L
DIDT=TRUE
SWITCH_NODE=TRUE
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.25 MM
VOLTAGE=1.25V
CRITICAL
1
C7524
82UF
20%
16V
2
ELEC
B6S-SM
PPVCORE_S0_CPU_PH2_L
DIDT=TRUE
SWITCH_NODE=TRUE
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.25 MM
VOLTAGE=1.25V
Removed snubber with EMC’s comment
CRITICAL
1
82UF
20%
16V
ELEC
B6S-SM
C7554
82UF
20%
16V
2
ELEC
B6S-SM
CRITICAL
0.36UH-20%-35A-0.00081OHM
L7550
FCUL1040-SM
152S1271
CRITICAL
1
C7515
10UF
10%
16V
2
X5R-CERM
0805
0.36UH-20%-35A-0.00081OHM
CRITICAL
1
C7525
10UF
10%
16V
2
X5R-CERM
0805
0.36UH-20%-35A-0.00081OHM
CRITICAL
1
C7555
2
PPVCORE_S0_AXG_R
21
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.25 MM
VOLTAGE=1.05V
CPUIMVP_ISNS1G_P
CRITICAL
1
C7516
10UF
10%
16V
2
X5R-CERM
0805
PLACE_NEAR=Q7510.1:1mm
CRITICAL
L7510
FCUL1040-SM
152S1271
CRITICAL
1
C7526
10UF
10%
16V
2
X5R-CERM
0805
PLACE_NEAR=Q7520.1:1mm
CRITICAL
L7520
FCUL1040-SM
152S1271
10UF
10%
16V
X5R-CERM
0805
R7553
1
2
46.4
1/20W
AXG PHASE 2
=PP5V_S0_CPUIMVP
7
68
AXG_PHASE2
1
AXG_PHASE2
1
R7540
10K
5%
1/16W
MF-LF
402
A
2
CPUIMVP_AXG_PWM2
68
IN
CPUIMVP_SKIP
2
6
PWN
SKIP*
5
VDD
U7542
MAX17491
TQFN
CRITICAL
THRM
GND
3
AXG_PHASE2
BST
PAD
9
1
8
DH
7
LX
4
DL
C7541
1UF
10%
25V
2
X5R
402
CPUIMVP_BOOT2G
MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.2 MM
CPUIMVP_UGATE2G
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM
CPUIMVP_PHASE2G
MIN_LINE_WIDTH=1.5 MM
MIN_NECK_WIDTH=0.2 MM
CPUIMVP_LGATE2G
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM
DIDT=TRUE
AXG_PHASE2
DIDT=TRUE
GATE_NODE=TRUE
DIDT=TRUE
SWITCH_NODE=TRUE
DIDT=TRUE
GATE_NODE=TRUE
R7542
AXG_PHASE2
R7567
1
5%
1/16W
MF-LF
402
1/16W
MF-LF
21
CPUIMVP_BOOT2G_RC
MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.25 MM
DIDT=TRUE
1
0
5%
402 2
2
AXG_PHASE2
1
C7542
0.22UF
10%
10V
CERM
402
CPUIMVP_UGATE2G_R
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM
DIDT=TRUE
GATE_NODE=TRUE
THESE TWO CAPS ARE FOR EMC
1
C7517
1UF
10%
25V
2
X5R
402
PLACE_NEAR=C7517.1:3mm
PPVCORE_S0_CPU_PH1
21
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.25 MM
VOLTAGE=1.25V
THESE TWO CAPS ARE FOR EMC
1
C7527
1UF
10%
25V
2
X5R
402
PLACE_NEAR=C7527.1:3mm
PPVCORE_S0_CPU_PH2
21
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.25 MM
VOLTAGE=1.25V
THESE TWO CAPS ARE FOR EMC
CRITICAL
C7556
10UF
10%
16V
X5R-CERM
0805
1
C7557
2
PLACE_NEAR=Q7550.1:1mm
1%
1W
MF
0612
CRITICAL
21
43
R7550
0.00075
CPUIMVP_ISNS1G_N
1
1
R7554
2
10
1%
1/20W
MF
201
2
CPUIMVP_ISUMG_N
201
1%
MF
CPUIMVP_ISUMG1_P
1
C7528
0.001UF
10%
50V
2
X7R-CERM
0402
1
C7518
0.001UF
10%
50V
2
X7R-CERM
0402
1
2
1
C7529
0.001UF
10%
50V
2
X7R-CERM
0402
R7523
1
C7558
1UF
10%
25V
X5R
402
PLACE_NEAR=C7557.1:3mm
=PPVCORE_S0_AXG_REG
0.001UF
10%
50V
2
X7R-CERM
0402
1
C7574
2200PF
10%
10V
2
X7R-CERM
0201
PLACE_NEAR=U7400.10:1mm
C7519
0.001UF
10%
50V
X7R-CERM
0402
CRITICAL
R7520
0.00075
1
46.4
1%
1/20W
MF
201
2
1
2
49 85 49 69 85
OUTOUT
68 69 85
IN
68
IN
CRITICAL
1
C7530
33UF
20%
16V
2
POLY-TANT
CASED2E-SM
NOSTUFF
1%
1W
MF
0612
C7559
0.001UF
10%
50V
X7R-CERM
0402
CRITICAL
1
C7540
33UF
20%
16V
2
POLY-TANT
CASED2E-SM
NOSTUFF
CRITICAL
R7510
0.00075
1%
1W
MF
0612
1
R7513
46.4
1%
1/20W
MF
201
2
=PPVCORE_S0_CPU_REG
21
43
CPUIMVP_ISNS2_N
CPUIMVP_ISNS2_P
1
R7524
10
1%
1/20W
MF
201
2
7
69
PLACE_NEAR=U7400.43:1mm
1
C7572
2200PF
10%
10V
2
X7R-CERM
0201
CRITICAL
1
C7560
33UF
20%
16V
2
POLY-TANT
CASED2E-SM
NOSTUFF
AXG_PHASE2
CRITICAL
Q7560
CSD58872Q5D
SON5X6
TG
3
TGR
4
BG
5
Note: value needs scrubbing
Note: value needs scrubbing
CPUIMVP_ISUMG_N
68 69 85
OUT
21
43
1
R7514
10
1%
1/20W
MF
201
2
CPUIMVP_ISUM_N
CPUIMVP_ISUM2_P
VIN
VSW
PGND
9
376S1005
=PPVCORE_S0_CPU_REG
CPUIMVP_ISNS1_N
CPUIMVP_ISNS1_P
CPUIMVP_ISUM_N
PLACE_NEAR=U7400.43:1mm
1
C7571
2200PF
10%
10V
2
X7R-CERM
0201
CPUIMVP_ISUM1_P
7
69
49 85
OUT
49 68 85
OUT
CRITICAL
1
C7561
33UF
20%
16V
2
POLY-TANT
CASED2E-SM
NOSTUFF
Reserve for acoustic noise
CPUIMVP_VSWG2
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.25 MM
1
6
7
8
SWITCH_NODE=TRUE
R7563
7
69
49 85
OUT
49 68 85
OUT
IN
IN
68 69
IN
68
IN
CRITICAL
1
C7562
33UF
20%
16V
2
POLY-TANT
CASED2E-SM
NOSTUFF
AXG_PHASE2
CRITICAL
0.36UH-20%-35A-0.00081OHM
1
100
1%
1/20W
MF
201
2
C7568
1000PF
X7R-CERM
L7560
FCUL1040-SM
CPUIMVP_ISNS2G_P
49 85 49 85
OUT OUT
AXG_PHASE2
1
R7566
0
5%
1/20W
MF
201
CPUIMVP_ISUMG_AVE_R_P
2
1
10%
16V
2
0201
Note: value needs scrubbing
68 69
68
CRITICAL
1
C7563
10UF
10%
16V
2
X5R-CERM
0805
PPVCORE_S0_AXG2_L
21
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.25 MM
152S1271
VOLTAGE=1.05V
CPUIMVP_ISNS1G_P
1
R7564
200
Note: value needs scrubbing
1%
1/20W
MF
201
2
1
C7569
2
CPUIMVP_ISUMG_AVE_P
NOSTUFF
330PF
10%
16V
X7R
201
AXG_PHASE2
R7561
OUT
THESE TWO CAPS ARE FOR EMC
1
C7565
1UF
10%
25V
2
X5R
402
PLACE_NEAR=C7565.1:3mm
AXG_PHASE2
CRITICAL
R7560
0.00075
1%
1W
MF
0612
21
43
1
46.4
1/20W
201
49 69 85
1%
MF
1
2
2
1
2
1
C7566
0.001UF
10%
50V
2
X7R-CERM
0402
=PPVCORE_S0_AXG_REG
CPUIMVP_ISNS2G_N
AXG_PHASE2
R7562
10
1%
1/20W
MF
201
CPUIMVP_ISUMG_N
PLACE_NEAR=U7400.10:1mm
C7573
2200PF
10%
10V
X7R-CERM
0201
CPUIMVP_ISUMG2_P
68
OUT
CRITICAL
1
C7564
10UF
10%
16V
2
X5R-CERM
0805
PLACE_NEAR=Q7560.1:1mm
PAGE TITLE
CPU IMVP7 & AXG VCore Output
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
AXG_PHASE2
6 3
1
C7567
0.001UF
10%
50V
2
X7R-CERM
0402
12
7
SYNC_DATE=07/28/2011SYNC_MASTER=JACK_J30
DRAWING NUMBER
051-9058
REVISION
6.0.0
BRANCH
PAGE
75 OF 109
SHEET
69 OF 86
124578
D
C
B
69
68 69 85
OUT
68
OUT
A
SIZE
D
8 7 6 5 4 3
12
D
CPU_VCCIOSENSE_P
12 78
CPU_VCCIOSENSE_N
C
12 78
1
402
402
1
R7644
3.01K
1%
1%
1/16W
MF-LF
402
2
2
<Ra>
1
1
R7645
2.74K
1%
1%
1/16W
MF-LF
402
2
2
<Rb>
1
C7604
47PF
50V
CERM
402
5%
1
C7605
47PF
5%
50V
2
2
CERM
402
C7602
1
C7603
0.047UF
10%
16V
2
X7R-CERM
0402
73
73
2.2UF
R7604
3.01K
1/16W
MF-LF
R7605
2.74K
1/16W
MF-LF
B
PP5V_S0_CPUVCCIOS0_VCC
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=5V
IN
OUT
1
1
10%
16V
2
X5R
603
2
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0V
CPU VCCIO (1.05V S0) Regulator
=PPVIN_S0_CPUVCCIOS0
7
=PP5V_S0_CPUVCCIOS0
7
=CPUVCCIOS0_EN
CPUVCCIOS0_FB
CPUVCCIOS0_SREF
CPUVCCIOS0_VO
CPUVCCIOS0_OCSET
CPUVCCIOS0_PGOOD
CPUVCCIOS0_RTN
CPUVCCIOS0_FSEL
R7603
0
5%
1/16W
MF-LF
402
CPUVCCIOS0_AGND
1
R7601
2.2
5%
1/16W
MF-LF
402
2
U7600
ISL95870
3 12
EN
CRITICAL
6
FB
4
SREF
8
VO
7
OCSET
9
PGOOD
2
RTN
5
FSEL
XW7600
SM
PLACE_NEAR=U7600.1:1mm
VCC
GND
1
13
UTQFN
21
PVCC
PGND
1
2
14
BOOT
UGATE
PHASE
LGATE
16
CPUVCCIOS0_VBST_RC
MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
DIDT=TRUE
1
C7601
10UF
20%
10V
X5R
603
R7630
2
CPUVCCIOS0_VBST
MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
DIDT=TRUE
11
10
CPUVCCIOS0_LL
MIN_LINE_WIDTH=1.5 mm
MIN_NECK_WIDTH=0.2 mm
15
SWITCH_NODE=TRUE
DIDT=TRUE
0
5%
1/16W
MF-LF
402
CPUVCCIOS0_DRVH
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
GATE_NODE=TRUE
DIDT=TRUE
CPUVCCIOS0_DRVL
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
GATE_NODE=TRUE
DIDT=TRUE
(CPUVCCIOS0_OCSET)
(CPUVCCIOS0_VO)
1
2
C7630
1UF
10%
25V
X5R
402
CRITICAL
1
C7620
39UF-0.027OHM
20%
16V
2
POLY
B1A-SM
2
1
6
OCP = R7641 x 8.5uA / R7640
OCP = 26.265A
Vout = 0.5V * (1 + Ra / Rb)
PHASE
543
CRITICAL
Q7630
FDMS3602S
POWER56
7
CRITICAL
1
C7621
39UF-0.027OHM
20%
16V
2
POLY
B1A-SM
CRITICAL
L7630
0.68UH-18A-3.3MOHM
PCMB103T
R7631
2.2
2 1
5%
1/10W
MF-LF
603
NOSTUFF
R7641
3.09K
1/16W
MF-LF
1%
402
DIDT=TRUE
1
C7640
2
1000PF
2 1
NP0-C0G
25V
402
21
5%
1
C7622
1000PF
5%
25V
2
NP0-C0G
402
PLACE_NEAR=C7624.1:3mm
PPCPUVCCIO_S0_REG_R
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.05V
CPUVCCSAS0_SNUB
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
NOSTUFF
1
C7631
0.001UF
10%
50V
2
X7R-CERM
0402
CPUVCCIOS0_CS_P
49 85
CPUVCCIOS0_CS_N
49 85
1
R7642
3.09K
1%
1/16W
MF-LF
402
2
1
C7624
1UF
10%
25V
2
X5R
603-1
PLACE_NEAR=Q7630.2:1mm
CRITICAL
R7640
0.001
MF-1
0612
1%
1W
21
43
C7623
1000PF
NP0-C0G
=PPCPUVCCIO_S0_REG
Vout = 1.05V
20.1A Max Output
1
f = 300 kHz
5%
25V
2
402
7
D
C
B
A
SYNC_MASTER=JACK_J30
PAGE TITLE
CPUVCCIO (1.05V) Power Supply
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
6 3
SYNC_DATE=09/28/2011
DRAWING NUMBER
051-9058
REVISION
6.0.0
BRANCH
PAGE
76 OF 109
SHEET
70 OF 86
124578
SIZE
A
D
8 7 6 5 4 3
12
CAESAR IV 1.2V INT.VR CMPTS
CRITICAL
L7700
=PP3V3_ENET_PHY
7
D
24 36
1
C7717
4.7UF
20%
6.3V
2
CERM
603
PLACE_NEAR=U3900.14:1mm
PLACE_NEAR=U3900.14:3mm
1
C7718
0.1UF
10%
16V
2
X7R-CERM
0402
4.7UH-0.91A
PLE031B-SM
PLACE_NEAR=U3900.16:1mm
XW7700
PLACE_NEAR=C7725.1:1mm
1
C7725
10UF
20%
6.3V
2
X5R
603-2
21
SM
21
1
C7726
0.1UF
10%
16V
2
X7R-CERM
0402
PLACE_NEAR=L7700.1:1mm
PLACE_NEAR=L7700.1:3mm
ENET_SR_LX
MIN_LINE_WIDTH=0.4MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=1.2V
SWITCH_NODE=TRUE
DIDT=TRUE
ENET_SR_VFB
MIN_LINE_WIDTH=0.25MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=1.2V
=PP1V2_ENET_PHY
PP1V2_S3_ENET_INTREG
MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.25MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=1.2V
36
36
36
6
Cougar Point requires JTAG pull-ups to be powered at 1.05V in SUS.
Pull-ups (3) must be 51 ohms to support XDP (not required in production).
70mA is required to support pull-ups. Alternative is strong voltage
dividers (200/100) to 3.3V S5, which burns 100mW in all S-states.
=PP3V3_SUS_P1V05SUSLDO
7
1.05V SUS LDO
CRITICAL
XDP_PCH
U7740
TPS720105
SON
4
XDP_PCH
C7740
1UF
6.3V
CERM
10%
402
BIAS
6
IN
3
EN
1
2
GND
5
THRM
PAD
7
OUT
1
2
NC
NC
=PP1V05_SUS_LDO
7
Vout = 1.05V
Max Current = 0.35A
XDP_PCH
1
C7741
2.2UF
10%
6.3V
2
X5R
402
D
C
=PP3V3_S0_P1V8S0
7
1
C7764
0.022UF
10%
P1V8_S0_COMP_RC
16V
2
X5R-X7R-CERM
0402
1
2
1
C7760
22UF
20%
6.3V
2
CERM-X5R
805
PLACE_NEAR=C7768.1:3mm
P1V8S0_SS
C7765
1500PF
10%
25V
X7R
402
73
1.8V S0 Switcher
1
2
=P1V8S0_EN
IN
R7765
3.24K
1/16W
MF-LF
402
C7761
0.1UF
10%
16V
X5R
402-1
1%
1
C7768
1UF
10%
10V
2
X5R
21
P1V8S0_COMP
402
PLACE_NEAR=U7760.A3:1mm
B2
B3
C2
C1
B1
SKIP
EN
SS/REFIN
FB
COMP
U7760
MAX15053EWL
WLP
CRITICAL
GND
A1
IN
LX
PGOOD
P1V8SO_FB
A3
A2
C3
P1V8S0_SW
MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
SWITCH_NODE=TRUE
DIDT=TRUE
P1V8S0_PGOOD
1.0UH-20%-11A-0.013OHM
73
OUT
P1V8_S0_RC
1
C7767
100PF
5%
50V
2
NOSTUFF
CERM
0402
Vout = 1.8V
MAX CURRENT = 2A
F = 1MHZ
CRITICAL
L7760
21
1
R7760
20.0K
1%
1/16W
MF-LF
402
2
1
R7761
10K
1%
1/16W
MF-LF
402
2
1
R7767
10K
1%
1/16W
MF-LF
402
2
PIC0503H-SM
NOSTUFF
1
C7766
100PF
5%
50V
2
CERM
0402
1
C7762
22UF
20%
6.3V
2
X5R-CERM-1
603
=PP1V8_S0_REG
1
C7772
22UF
20%
6.3V
2
X5R-CERM-1
603
1
C7763
0.1UF
10%
16V
2
X5R
402-1
7
B
1.5V S0 Switcher
=PP1V5_S0_REG
=PP3V3_S0_P1V5S0
7
1
C7770
10uF
20%
6.3V
2
X5R
603
=P1V5S0_EN
73
IN
A
U7770
TPS62201
4
FB
3
EN
1
VI
SOT23-5
GND
2
CRITICAL
10UH-0.55A-330MOHM
5
P1V5S0_SW
SW
MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
SWITCH_NODE=TRUE
DIDT=TRUE
CRITICAL
L7770
PCAA031B-SM
Vout = 1.5V
1
MAX CURRENT = 0.3A
F = 1MHZ
1
C7773
10uF
20%
2
6.3V
2
X5R
603
6 3
7
=PP3V3_S0_P1V05S0LDO
7
=PP1V8_S0_P1V05S0LDO
7
=1V05_S0_LDO_EN
73
C7782
1UF
10%
6.3V
CERM
402
PLACE_NEAR=U7780.4:1mm
1.05V S0 LDO
CRITICAL
U7780
TPS720105
SON
4
BIAS
6
IN
3
EN
1UF
10%
6.3V
CERM
402
1
2
1
C7780
2
PLACE_NEAR=U7780.6:1mm
THRM
PADGND
7
5
OUT
=PP1V05_S0_LDO
Vout = 1.05V
1
Max Current = 0.35A
2
NC
NC
1
C7781
2.2UF
10%
6.3V
2
X5R
402
7
PAGE TITLE
Misc Power Supplies
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
SYNC_DATE=07/28/2011SYNC_MASTER=JACK_J30
DRAWING NUMBER
051-9058
REVISION
BRANCH
PAGE
77 OF 109
SHEET
6.0.0
71 OF 86
124578
SIZE
C
B
A
D
8 7 6 5 4 3
NO STUFF
R7803
0
21
5%
1/10W
MF-LF
603
3.3V S4 FET
=PP3V3_S4_P3V3S4FET
D
73
IN
7
Q7803
SSM3K15AMFVAPE
VESM
=P3V3S4_EN
1
G S
1
3
D
2
R7802
220K
5%
1/16W
MF-LF
402
2
P3V3S4_EN_L
R7800
5.1K
C7809
0.033UF
5%
1/16W
MF-LF
402
1
10%
16V
2
X5R
402
21
P3V3S4_GATE
3.3V S3 FET
=PP3V3_S3_P3V3S3FET
7
1
6
SOT563
D
2
SG
1
C
=P3V3S3_EN
73
IN
Q7812
SSM6N37FEAPE
R7812
100K
5%
1/16W
MF-LF
402
2
P3V3S3_EN_L
C7811
0.033UF
R7810
47K
5%
1/16W
MF-LF
402
1
10%
16V
2
X5R
402
21
P3V3S3_SS
74
Q7810
SIA427DJ
74
S
CRITICAL
Q7800
SIA427DJ
SC70-6L
S
G
3
C7800
0.01UF
X7R-CERM
CRITICAL
SC70-6L
G
3
C7810
0.01UF
10%
16V
X7R-CERM
0402
=PP3V3_S0_P3V3S0FET
7
3
SOT563
5
SOT563
D
SG
4
6
D
2
SG
1
D
1
=PP3V3_S4_FET
7
Q7812
SSM6N37FEAPE
3.3V S4 FET
=P3V3S0_EN
73
MOSFET
21
10%
16V
0402
D
1
CHANNEL
RDS(ON)
LOADING
=PP3V3_S3_FET
SiA427
P-TYPE 8V/5V
26 mOhm @1.8V
1.35 A (EDP)
7
IN
=PP3V3_S5_P3V3SUSFET
7
Q7822
SSM6N37FEAPE
=P5V_3V3_SUS_EN
72 73
IN
1
2
1
2
3.3V S3 FET
MOSFET
21
CHANNEL
RDS(ON)
LOADING
SiA427
P-TYPE 8V/5V
31 mOhm @1.8V
1.608 A (EDP)
=P5V_3V3_SUS_EN
72 73
IN
=PP5V_S5_P5VSUSFET
7
Q7822
SSM6N37FEAPE
SOT563
5
3
D
SG
4
1
2
3.3V S0 FET
1
R7832
10K
5%
1/16W
MF-LF
402
P3V3S0_EN_L
C7831
0.033UF
R7830
91K
5%
1/16W
MF-LF
402
10%
16V
2
X5R
402
21
P3V3S0_SS
3.3V_SUS FET
12K
5%
1/16W
MF-LF
402
10%
16V
X5R
402
21
1
2
P3V3SUS_SS
R7822
100K
5%
1/16W
MF-LF
402
P3V3SUS_EN_L
C7821
0.033UF
R7820
5V_SUS FET
3.3K
5%
1/16W
MF-LF
402
10%
16V
X5R
402
21
1
2
P5VSUS_SS
R7842
220K
5%
1/16W
MF-LF
402
P5VSUS_EN_L
C7841
0.033UF
R7840
CRITICAL
Q7830
SIA427DJ
74
S
3
CRITICAL
Q7820
SIA427DJ
74
S
3
CRITICAL
Q7840
SIA413DJ
SC70-6L
74
S
3
SC70-6L
G
C7830
0.01UF
10%
16V
X7R-CERM
0402
SC70-6L
G
C7820
0.01UF
10%
16V
X7R-CERM
0402
G
C7840
0.01UF
10%
16V
X7R-CERM
0402
D
=PP3V3_S0_FET
1
7
3.3V S0 FET
MOSFET
CHANNEL
21
D
1
RDS(ON)
LOADING
=PP3V3_SUS_FET
SiA427
P-TYPE 8V/5V
26 mOhm @1.8V
3.2 A (EDP)
7
3.3V SUS FET
MOSFET
21
D
1
CHANNEL
RDS(ON)
LOADING
=PP5V_SUS_FET
SiA427
P-TYPE 8V/5V
26 mOhm @1.8V
100? mA (EDP)
7
5V SUS FET
MOSFET
21
CHANNEL
RDS(ON)
LOADING
SiA427
P-TYPE 8V/5V
16 mOhm @4.5V
100? mA (EDP)
12
D
C
1.5V S3/S0 FET
=PP1V5_S3_P1V5S3RS0_FET
=PP5V_S5_P1V5DDRFET
7
C7801
0.1UF
20%
10V
CERM
402
B
26
P1V5CPU_EN
IN
NO STUFF
C7802
4.7UF
6.3V
X5R-CERM
1
10%
2
603
7
1
2
2
3
VCC
U7801
SLG5AP020
TDFN
ON
CRITICAL
SHDN*
GND
4
1
5
THRM
PAD
9
D
7
G
6
S
8
PG
P1V5S0FET_GATE
R7801
0
5%
1/16W
MF-LF
402
21
P1V5S0FET_GATE_R
4
G
APN 376S0928
5
CRITICAL
D
Q7801
SI7108DN
PWRPK-1212-8-HF
S
321
=PP1V5_S3RS0_FET
7
1.5V S3/S0 FET
P1V5S3RS0_RAMP_DONE
8
OUT
MOSFET
CHANNEL
RDS(ON)
LOADING
SI7108DN
N-TYPE
6 mOhm @4.5V
5 A (EDP)
=PP5V_S3_P5VS0FET
7
SSM3K15AMFVAPE
=P5VS0_EN
73
IN
Q7802
VESM
1
G S
D
5.0V S0 FET
1
R7862
220K
5%
1/16W
MF-LF
402
2
P5V0S0_EN_L
3
2
C7861
0.033UF
R7860
10K
5%
1/16W
MF-LF
402
1
10%
16V
2
X5R
402
21
P5V0S0_SS
A
6 3
CRITICAL
Q7860
DMP2018LFK
DFN2563-6
2
S
1
G
3
C7860
=PP5V_S0_FET
D
4
MOSFET TPCP8102
CHANNEL
0.01UF
21
10%
16V
X7R-CERM
0402
SYNC_MASTER=K90I_MLB SYNC_DATE=02/15/2011
PAGE TITLE
RDS(ON)
LOADING
7
5.0V S0 FET
P-TYPE
18 MOHM @4.5V
1.678 A (EDP)
Power FETs
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
DRAWING NUMBER
051-9058
REVISION
6.0.0
BRANCH
PAGE
78 OF 109
SHEET
72 OF 86
124578
SIZE
B
A
D
D
C
B
A
6 45
IN
=PP3V3_S0_VMON
7 73
7
S0PGOOD_ISL
R7960
S0PGOOD_ISL
R7961
8 7 6 5 4 3
S5 Rail Enables & PGOOD
=PP3V42_G3H_PWRCTL
7 73
C7940
0.1uF
SMC_PM_G2_EN
MAKE_BASE=TRUE
=PP3V3_S5_PWRCTL
7 73
Threshold: ??
DLY > 10 ms
S5PGOOD_DLY
1
C7941
220PF
5%
25V
2
C0G-CERM
0402
ALL_SYS_PWRGD CPUIMVP_VR_ON
23 24 45 73
1
R7951
15.0K
1%
1/16W
MF-LF
402
2
1
R7952
7.15K
1/16W
MF-LF
402
2
Thresholds:
VDD: 2.734V-3.010V
V2MON: 2.815V-3.099V
V3MON: 0.572V-0.630V
V4MON: 0.572V-0.630V
=PP5V_S0_VMON
6.04K
1/16W
MF-LF
15.0K
1/16W
MF-LF
7 73
1
S0PGOOD_ISL
R7970
1%
402
2
P5V_DIV_VMON
1
S0PGOOD_ISL
R7971
1%
402
2
=PP1V5_S0_VMON
1%
=PP1V5_S0_VMON
7 73
PP1V5_S0
7 73
10K
1%
1/16W
MF-LF
402
10K
1%
1/16W
MF-LF
402
VMON_3V3_DIV
=PP1V05_S0_VMON
=PP1V05_S0_VMON
7 73
1
S0PGOOD_ISL
R7972
6.04K
2
P1V5_DIV_VMON
1
S0PGOOD_ISL
R7973
15.0K
1/16W
2
20%
10V
CERM
402
=PP3V3_S5_VMON
7
S0 Rail PGOOD Circuitry
(ISL Version in development)
1%
1/16W
MF-LF
402
1%
MF-LF
402
Internal pull-ups 100K +/- 20%
1
2
2
IN_A
(IPD)
6
IN_B
1.3V
7
DLY_1C
R7974
5%
1/16W
MF-LF
402
1
CRITICAL
343S0497
VDD
U7941
SLG4AP012
TDFN
+
2:1
-
DLY
GND
THRM
5
PAD
CPUVCORE ENABLE
0
21
PLACE_NEAR=U7400.7:5mm
OUT_A*
(OD,IPU)
OUT_A
(OD,IPU)
OUT_B
(OD,IPU)
9
4
P3V3S5_EN_L_R
MAKE_BASE=TRUE
3
P5V3V3_REG_EN
MAKE_BASE=TRUE
8
S5_PWRGD (old name RSMRST_PWRGD)-->SMC
SMC-->PM_DSW_PWRGD
S0 Rail PGOOD (BJT Version)
1
R7956
150K
1%
1/16W
MF-LF
402
2
R7953
1/16W
MF-LF
R7954
1/16W
MF-LF
R7955
1K
5%
1/16W
MF-LF
402
=PP3V3_S0_VMON
7 73
S0PGOOD_ISL
C7960
0.1uF
1
2
P1V05_DIV_VMON
1
2
1K
21
VMON_Q2_BASE
5%
402
1K
402
5%
21
VMON_Q3_BASE
21
VMON_Q4_BASE
Worst-Case Thresholds:
Q2: 0.XXXV
Q3: 0.640V
3.3V w/Divider: 2.345V
Q4: 0.660V
1
20%
10V
2
CERM
402
ISL88042IRTEZ
3
V2MON
5
V3MON
6
V4MON
S0PGD_C
6
5
Q2
8
NC
7
Q3
CRITICAL
2
NC
1
Q4
P1V5S0_PGOOD from U7710
7
2
VDD
U7960
TDFN
(IPU)
1
MR*
CRITICAL
S0PGOOD_ISL
GND
THRM_PAD
4
RST*
9
353S2310
8
3
68
IN
71
IN
66
IN
70
IN
65
IN
NC
ALL_SYS_PWRGD_R
R7941
ALL_SYS_PWRGD
4
Q7950
Q1
ASMCC0179
DFN2015H4-8
353S2809
S0PGD_BJT_GND_R
CPUIMVP_AXG_PGOOD
P1V8S0_PGOOD
P5V3V3_PGOOD
CPUVCCIOS0_PGOOD
PVCCSA_PGOOD
100
21
5%
1
1/16W
MF-LF
402
=P5V3V3_REG_EN
R7957
C7942
0.033UF
10%
16V
2
X5R
402
NO STUFF
OUT
S5_PWRGD
MAKE_BASE=TRUE
OUT
SMC_BATLOW_L:100K pull up on SMC page
1
100
5%
1/16W
MF-LF
402
2
=PP3V3_S0_PWRCTL
7
R7965
100
5%
1/16W
MF-LF
402
R7963
100
5%
1/16W
MF-LF
402
S0PGOOD_ISL
R7962
330
21
5%
1/16W
MF-LF
402
68
R7967
NO STUFF
R7968
100
21
5%
1/16W
MF-LF
402
21
R7964
100
1/16W
MF-LF
402
21
ALL_SYS_PWRGD
OUT
23 24 45 73
1/16W
MF-LF
R7966
100
5%
1/16W
MF-LF
402
5%
10K
21
P3V3S5_EN_L
MAKE_BASE=TRUE
=P3V3S5_EN_L
66
=PP3V3_S5_PWRCTL
7 73
45
45 46
17
5%
402
PLACE_NEAR=U7970.6:3mm
45 46
IN
3.3V/5.0V Sus ENABLE
=PP3V3_S5_PWRCTL
7 73
PLACE_NEAR=U7940.1:2.3mm
SMC_BATLOW_L
IN
PM_SLP_SUS_L
IN
=PP3V3_SUS_PWRCTL
7 73
1
2
21
OUT
66
OUT
1
C7970
0.1UF
10%
10V
2
X5R-CERM
0201
SMC_S4_WAKESRC_EN
1
C7943
0.1uF
20%
10V
2
CERM
402
NO STUFF
R7917
No stuff C7931, 12ms
Min delay time
U7930 Sense input
threhold is 3.07V
S4_PGOOD_CT
23 24 45 73
3.3V S4 ENABLE
PM_SLP_S5_L
17 45
IN
5
VCC
U7940
74AUP1G3208
SOT891
1
A
3
B
6
C
GND
2
0
21
5%
1/16W
MF-LF
402
=PP3V3_S5_PWRCTL
7 73
CRITICAL
5 1
SENSE
TPS3808G33DBVRG4
4
CT
1
C7931
0.001UF
20%
50V
2
CERM
402
NO STUFF
State
Run (S0)
Sleep (S3)
Deep Sleep (S4)
Deep Sleep (S5)
Battery Off (G3Hot)
U7970
6
74LVC1G32
2
SOT891
1
NC
3
5
NC
NO STUFF
R7919
0
21
5%
1/16W
MF-LF
402
PLACE_NEAR=U1800.G18:5mm
4
PM_SUS_EN
50
Y
MAKE_BASE=TRUE
3.3V SUS Detect
PLACE_NEAR=U7930.6:2.3mm
U7930
SOT23-6
VDD
GND
6
2
C7930
0.1uF
RESET*
MR*
(90K IPU)
CERM
20%
10V
402
3
SMC_PM_G2_ENABLE
1
1
1
1
0
P3V3_S4_EN
4
MAKE_BASE=TRUE
=P5V_3V3_SUS_EN
=PP3V3_SUS_PWRCTL
1
2
NC
1
R7933
100K
5%
1/16W
MF-LF
402
2
PM_RSMRST_L
PM_RSMRST_L goes to U1800.C21
19
6 8 17 26 45 73
17 45 46
1
1
1
0
0
6 8 17 26 45 73
IN
SSM3K15AMFVAPE
72
OUT
17
OUT
WOL_EN
IN
PM_SLP_S3_L
IN
SMC_ADAPTER_EN
IN
PM_SLP_S4_L
1 1
1
0
0
=P3V3S4_EN
=TBTAPWRSW_EN
S0 ENABLE
R7978
PM_SLP_S3_L
=PP3V42_G3H_PWRCTL
7
73
CHGR VFRQ Generation
2N7002DW-X-G
1/16W
MF-LF
Q7931
VESM
1
G S
Q7925
SOT-363
Q7920
2N7002DW-X-G
SOT-363
100
5%
402
21
D
5
G
2
G
PM_SLP_S3_LPM_SLP_S5_L
21
R7931
CHGR_VFRQ
3
2
6 3
0
00
0
0
72
OUT
76
OUT
(PM_SLP_S3_R_L)
2
1/16W
1
MF-LF
402
PLACE_NEAR=U7100.15:6mm
10K
5%
1/16W
MF-LF
402
OUT
PVCCSA_EN
64
PLACE_NEAR=U7100.15:6mm
1
2
VFRQ Low: Fix Frequency
VFRQ High: Variable Frequency
ENET Enable Generation
"ENET" = "S0" || ("S3" && "AC" && "WOL_EN")
=PP3V3_S3_P3V3ENETFET
7
PM_ENET_EN_L
3
D
S
4
SSM3K15AMFVAPE
AC_EN_L
6
NO STUFF
R7929
1/16W
MF-LF
402
1
0
5%
2
D
S
1
6 17 26 32 45
R7987
33K
5%
MAKE_BASE=TRUE
C7987
0.47UF
10%
6.3V
CERM-X5R
402
Q7921
VESM
(AC_EN_L)
(PM_SLP_S3_L)
PM_SLP_S4_L
IN
MAKE_BASE=TRUE
2
R7981
20K
5%
1/16W
MF-LF
1
402
PLACE_NEAR=U7600.3:6mm
CPUVCCIOS0_EN
MAKE_BASE=TRUE
PLACE_NEAR=U7600.3:6mm
1
C7981
0.47UF
10%
6.3V
2
CERM-X5R
402
R7921
3
D
1
G S
2
Q7920
2N7002DW-X-G
SOT-363
3.3V,5V S3 ENABLE
=PP3V42_G3H_PWRCTL
7 73
2
R7911
5.1K
5%
1/16W
MF-LF
1
402
PLACE_NEAR=U7300.16:6mm
1
C7910
0.47UF
10%
6.3V
2
CERM-X5R
PLACE_NEAR=U7300.16:6mm
10K
1/16W
MF-LF
402
5
402
PM_SLP_S3_R_L
MAKE_BASE=TRUE
2
R7988
39K
5%
1/16W
MF-LF
1
402
PLACE_NEAR=U7770.3:6mm
P1V5S0_EN
MAKE_BASE=TRUE
PLACE_NEAR=U7770.3:6mm
1
C7988
0.47UF
10%
6.3V
2
CERM-X5R
402
1
5%
2
NOTE: S3 term is guaranteed by S3 pull-up on open-drain AP_PWR_EN signal.
G
R7922
100K
5%
1/16W
MF-LF
402
WLAN Enable Generation
"WLAN" = ("S3" && "AP_PWR_EN" && ("AC" || "S0"))
6
D
G
S
1
PAGE TITLE
3
D
S
4
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
R7913
68K
21
5%
1/16W
MF-LF
402
R7914
1/16W
MF-LF
PLACE_NEAR=U5701.3:6mm
2
R7912
9.1K
5%
1/16W
MF-LF
402
1
PLACE_NEAR=Q7812.2:6mm
1
C7912
0.47UF
10%
6.3V
2
CERM-X5R
402
PLACE_NEAR=Q7812.2:6mm
2
R7986
5.1K
5%
1/16W
1
MF-LF
402
PLACE_NEAR=U7760.B3:6mm
P1V8S0_EN
MAKE_BASE=TRUE
PLACE_NEAR=U7760.B3:6mm
1
C7986
0.47UF
10%
6.3V
2
CERM-X5R
402
3.3K
5%
402
P5VS3_EN_L
MAKE_BASE=TRUE
21
D
1
G S
P3V3S3_EN
MAKE_BASE=TRUE
DDRREG_EN
MAKE_BASE=TRUE
3
2
=P5VS3_EN_L
NO STUFF
1
C7913
0.068UF
10%
10V
2
X5R-CERM
0402
TPAD_VBUS_EN
Q7911
SSM3K15AMFVAPE
VESM
=P3V3S3_EN
=DDRREG_EN
=USB_PWR_EN
=P5VS0_EN
=P3V3S0_EN
=PBUSVSENS_EN
=P1V8S0_EN
=P1V5S0_EN
=1V05_S0_LDO_EN
=CPUVCCIOS0_EN
=PVCCSA_EN
3.3V ENET FET
CRITICAL
Q7922
NTR4101P
SOT-23-HF
DS
2
1
C7921
0.033UF
10%
16V
2
X5R
402
21
P3V3ENET_SS
PM_WLAN_EN_L
Q7925
2N7002DW-X-G
SOT-363
2
AP_PWR_EN
Power Control 1/ENABLE
Apple Inc.
R
G
1
C7922
0.01UF
2 1
10%
16V
X7R-CERM
0402
3
=PP3V3_ENET_FET
SYNC_DATE=02/15/2011SYNC_MASTER=K90I_MLB
DRAWING NUMBER
051-9058
REVISION
BRANCH
PAGE
SHEET
66
OUT
53
OUT
72
OUT
67
OUT
42
OUT
72
OUT
72
OUT
50
OUT
71
OUT
71
OUT
71
OUT
70
OUT
65
OUT
32
OUT
18 23 32
IN
6.0.0
79 OF 109
73 OF 86
SIZE
124578
12
D
C
B
7
A
D
8 7 6 5 4 3
12
D
D
LCD CONNECTOR
LCD_IG_PWR_EN
8
10%
50V
X7R-CERM
0402
MIN_NECK_WIDTH=0.20 MM
CRITICAL
L9080
90-OHM-100MA
DLP11S
SYM_VER-1
1
2
77
77
77
77
77
77
C9010
0.001UF
21
LED_RETURN_1
6
LED_RETURN_2
6
LED_RETURN_3
6
LED_RETURN_4
6
LED_RETURN_5
6
LED_RETURN_6
6
CRITICAL
U9000
FPF1009
MFET-2X2-8IN
1
ON
=PP3V3_S5_LCD
7
1
C9009
C
2
0.1UF
10%
16V
X7R-CERM
0402
2
3
VIN_1
VIN_2
GND
6
VOUT_1
VOUT_2
THRM
PAD
7
4
5
1
C9011
0.1UF
10%
16V
2
X7R-CERM
0402
1
C9012
2
10UF
20%
6.3V
X5R
603
PP3V3_LCDVDD_SW
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.30 MM
MIN_NECK_WIDTH=0.20 MM
LVDS_DDC_CLK
6 8
LVDS_DDC_DATA
6 8
=PP3V3_S0_LCD
7
1
R9008
10K
5%
1/16W
MF-LF
402
2
L9004
FERR-120-OHM-1.5A
0402-LF
1
R9009
10K
5%
1/16W
MF-LF
402
2
21
L9008
120-OHM-0.3A-EMI
0402-LF
(LVDS DDC POWER)
CRITICAL
21
MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.20 MM
LVDS_IG_A_CLK_N
17 80
LVDS_IG_A_CLK_P
17 80
C9015
0.001UF
PP3V3_S0_LCD_F
6
VOLTAGE=3.3V
4 3
10%
50V
X7R-CERM
0402
6
85
6
85
1
2
PP3V3_LCDVDD_SW_F
6
VOLTAGE=3.3V
6
17 80
6
17 80
6
17 80
6
17 80
6
17 80
6
17 80
LVDS_CONN_A_CLK_F_N
LVDS_CONN_A_CLK_F_P
PPVOUT_SW_LCDBKLT
6
77
C9020
0.001UF
10%
50V
X7R-CERM
0402
MIN_LINE_WIDTH=0.30 MM
LVDS_IG_A_DATA_N<0>
LVDS_IG_A_DATA_P<0>
LVDS_IG_A_DATA_N<1>
LVDS_IG_A_DATA_P<1>
LVDS_IG_A_DATA_N<2>
LVDS_IG_A_DATA_P<2>
1
2
B
LVDS CONNECTOR:518S0787
CRITICAL
J9000
20525-130E-01
F-RT-SM
31
1
2
3
4
5
NC
6
7
8
9
10
11
12
13
14
15
16
17
LVDS I/F
18
19
NC
NC
NC
20
21
22
23
24
25
26
27
28
29
30
33
34
35
36
37
38
39
40
41
32
LED BKLT I/F
C
B
A
6 3
SYNC_MASTER=K90I_MLB
PAGE TITLE
LVDS CONNECTOR
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
SYNC_DATE=02/15/2011
DRAWING NUMBER
051-9058
REVISION
6.0.0
BRANCH
PAGE
90 OF 109
SHEET
74 OF 86
124578
SIZE
A
D
8 7 6 5 4 3
1%
1/16W
MF-LF
402
21
X5R-CERM
21
X5R-CERM
21
X5R-CERM
21
X5R-CERM
21
X5R-CERM
21
X5R-CERM
21
X5R-CERM
21
X5R-CERM
21
X5R-CERM
21
X5R-CERM
16V10%
0201
16V10%
0201
16V10%
0201
16V10%
0201
16V10%
0201
16V10%
0201
16V10%
0201
16V10%
0201
16V10%
0201
16V10%
0201
DP_EXTA_ML_P<0>
DP_EXTA_ML_N<0>
DP_EXTA_ML_P<1>
DP_EXTA_ML_N<1>
DP_EXTA_ML_P<2>
DP_EXTA_ML_N<2>
DP_EXTA_ML_P<3>
DP_EXTA_ML_N<3>
R9309
DP_EXTA_AUXCH_P
DP_EXTA_AUXCH_N
R9308
DP A Super-Driver
1
1
C9310
2.2UF
20%
6.3V
CERM
402-LF
DP_EXTA_ML_P<0>
75 81
DP_EXTA_ML_N<0>
75 81
DP_EXTA_ML_P<1>
75 81
DP_EXTA_ML_N<1>
75 81
DP_EXTA_ML_P<2>
75 81
DP_EXTA_ML_N<2>
75 81
DP_EXTA_ML_P<3>
75 81
DP_EXTA_ML_N<3>
75 81
DP_EXTA_DDC_CLK
8
IN
DP_EXTA_DDC_DATA
8
BI
DP_EXTA_AUXCH_P
75 81
DP_EXTA_AUXCH_N
75 81
DP_EXTA_HPD
8
OUT
DPSDRVA_I2C_CTL_EN
DPSDRVA_I2C_ADDR0
DPSDRVA_I2C_ADDR1
=I2C_DPSDRVA_SCL
48
IN
=I2C_DPSDRVA_SDA
48
BI
DPSDRVA_REXT
DP_AUXCH_ISOL
16 23
IN
DP_A_PWRDWN_R
PS8301 has internal
~150K pull-down on PD
pin. Okay to drive this
pin even when VCC=0V per
Parade (pin is 5V-tolerant).
C9311
0.1UF
10%
16V
2
2
X5R-CERM
0201
DP_A_CA_DET
75
T29_LSEO<0>
33
IN
=I2C_T29AMCU_SCL
48
IN
=I2C_T29AMCU_SDA
48
BI
T29DPA_HPD
76
IN
T29_A_BIAS_R
76
OUT
T29_LSOE<0>
33
OUT
T29_LSOE<1>
33
OUT
TBT_PWR_REQ_L
18
OUT
DP_EXTA_ML_C_P<0>
8
81
IN
DP_EXTA_ML_C_N<0>
8
81
IN
DP_EXTA_ML_C_P<1>
8
81
IN
DP_EXTA_ML_C_N<1>
8
81
IN
DP_EXTA_ML_C_P<2>
8
81
D
IN
DP_EXTA_ML_C_N<2>
8
81
IN
DP_EXTA_ML_C_P<3>
8
81
IN
DP_EXTA_ML_C_N<3>
8
81
IN
DP_EXTA_AUXCH_C_P
8
81
BI
DP_EXTA_AUXCH_C_N
8
81
BI
If GPU uses common pins for AUX_CH
and DDC, alias nets together at GPU.
=PP3V3_S0_DPSDRVA
7
75
C9300
0.1UF
C9301
0.1UF
C9302
0.1UF
C9303
0.1UF
C9304
0.1UF
C9305
0.1UF
C9306
0.1UF
C9307
0.1UF
C9308
0.1UF
C9309
0.1UF
PS8301 I2C Addresses:
C
A1 A0 Addr (W/R)
0 0 0x96/0x97
0 1 0xB6/0xB7
1 0 0x94/0x95
1 1 0xB4/0xB5
Note: Other Parade
devices use 96/B6,
so only 94/B4 are
used for this part.
NO STUFF
1
R9312
1K
5%
1/16W
MF-LF
402
2
R9311
1/16W
MF-LF
1
1
R9310
1K
1K
5%
5%
1/16W
MF-LF
402
402
2
2
B
SDRV_PD
R9318
1/20W
DP_A_PWRDWN
75
=TBT_WAKE_L:
A
Desktops use PCIe WAKE#
Mobiles use S4 WAKE#
17
=TBT_WAKE_L
OUT
OMIT
R9330
1/16W
MF-LF
T29_A_UC_ADDR
R9330 provides pads for programming/debug of MCU, please make accessible.
If project has space for 10-pin programming header it should be used.
75
1
R9319
4.22K
0
5%
MF
201
2
1 2
1
SWCLK
0
5%
402
2
SWDIO
12
T29_A_BIAS_R2DP0
8
IN
GND_VOID=TRUE
75 81
75 81
75 81
75 81
75 81
75 81
75 81
75 81
21
21
1
C9312
0.1UF
10%
16V
2
X5R-CERM
0201
5%
MF 201
75 81
75 81
5%
MF
1
IN_D0P
2
IN_D0N
4
IN_D1P
5
IN_D1N
7
IN_D2P
8
IN_D2N
9
IN_D3P
10
IN_D3N
14
IN_SCL
13
IN_SDA
16
IN_AUXP
15
IN_AUXN
3
IN_HPD
26
I2C_CTL_EN
36
I2C_ADDR0
35
I2C_ADDR1
38
SCL_CTL
37
SDA_CTL
12
REXT
39
AUXDDC_OFF
34
PD
1M
1M
=PP3V3_S0_DPSDRVA
1/20W
R9308/R9309 maintain bias on C9308/C9309
to prevent spikes when U9310 AUXDDC_OFF
1/20W
201
transitions from high to low.
40
21
VDD
U9310
PS8301TQFN40GTR-A2
QFN
CRITICAL
OUT_AUXP_SCL
OUT_AUXN_SDA
(IPD)
(IPU)
(IPD)
(IPD)
(IPD)
(IPD)
GND
6
33
THMPAD
41
OUT_D0P
OUT_D0N
OUT_D1P
OUT_D1N
OUT_D2P
OUT_D2N
OUT_D3P
OUT_D3N
AC_AUXP
AC_AUXN
OUT_HPD
CA_DET
CEXT
T29 signals are
P/N-swapped after AC
caps to improve layout.
7
75
30
DP_SDRVA_ML_C_P<0>
83
29
DP_SDRVA_ML_C_N<0>
83
28
DP_SDRVA_ML_C_P<1>
83
27
DP_SDRVA_ML_C_N<1>
83
25
DP_SDRVA_ML_C_P<2>
83
24
DP_SDRVA_ML_C_N<2>
83
23
DP_SDRVA_ML_C_P<3>
83
22
DP_SDRVA_ML_C_N<3>
83
20
DP_SDRVA_AUXCH_C_P
83
19
DP_SDRVA_AUXCH_C_N
83
18
(DP_SDRVA_AUXCH_P)
17
(DP_SDRVA_AUXCH_N)
31
(DP_SDRVA_HPD)
32
DP_A_CA_DET
11
DPSDRVA_CEXT
PLACE_NEAR=U9310.11:2 mm
C9319
33 83
OUT
33 83
OUT
33 83
IN
33 83
IN
33 83
OUT
33 83
OUT
33 83
IN
33 83
IN
2.2UF
6.3V
CERM
402-LF
20%
T29_D2R_N<0>
T29_D2R_P<0>
T29_R2D_C_N<0>
T29_R2D_C_P<0>
T29_D2R_N<1>
T29_D2R_P<1>
T29_R2D_C_N<1>
T29_R2D_C_P<1>
R9354
R9355
R9350
R9351
75
IN
1
2
30
30
30
30
21
21
21
21
MF5%201
5%
MF
5%
MF
5%
MF
R9352
C9363
0.1UF
C9362
0.1UF
C9367
0.1UF
C9366
0.1UF
AUXCH Snoop Port,
used by PS8301
during training.
C9369
0.1UF
C9368
0.1UF
1/20W
1/20W
1/20W
1/20W
DP_SDRVA_ML_R_N<0>
83
201
DP_SDRVA_ML_R_P<2>
83
201
DP_SDRVA_ML_R_N<2>
83 83
201
1
270
5%
1/20W
MF
201
2
21
16V10%
X5R-CERM
0201
21
16V10%
X5R-CERM
0201
21
16V10%
X5R-CERM
0201
21
16V10%
X5R-CERM
0201
21
16V10%
0201
X5R-CERM
21
16V10%
X5R-CERM
0201
DP_SDRVA_ML_R_P<0>
83
GND_VOID=TRUE
(C9370/C9371)
1
R9353
270
5%
1/20W
MF
201
2
1
R9392
51
5%
1/20W
MF
201
2
75
Port A MCU
PP3V3_SW_TBTAPWR
75 76
CRITICAL
1
RESET#/PIO0_0
2
PIO0_1/CLKOUT
7
PIO0_2/SSEL/CT16B0_CAP0
8
PIO0_4/SCL
9
PIO0_5/SDA
10
PIO0_6/SCK
11
PIO0_7/CTS#
12
PIO0_8/MISO/CT16B0_MAT0
13
PIO0_9/MOSI/CT16B0_MAT1
14
SWCLK/PIO0_10/SCK/CT16B0_MAT2
15
R/PIO0_11/AD0
(OD)
(OD)
Must be 3.3V DP A port power
5
22
VDD
U9330
LPC1112A
HVQFN25
(OD)
VSS
3
OMIT_TABLE
(IPU)
SWDIO/PIO1_3/AD4
PIO1_4/AD5/WAKEUP
PIO1_8/CT16B1_CAP0
(OD)
THRM
PAD
21
25
R/PIO1_0/AD1
R/PIO1_1/AD2
R/PIO1_2/AD3
PIO1_6/RXD
PIO1_7/TXD
XTALIN
1
C9330
0.1UF
20%
10V
2
CERM
402
16
17
18
19
20
23
24
6
4
1
2
1
C9331
0.1UF
20%
10V
2
CERM
402
T29DPA_CONFIG1_RC
T29DPA_CONFIG2_RC
TBT_A_HV_EN_R
T29_A_UC_ADDR
DP_A_EXT_HPD
T29_A_LSX_P2R
T29_A_LSX_R2P
T29_LSEO<1>
R9335
1K
5%
1/16W
MF-LF
402
1
R9336
10K
5%
1/16W
MF-LF
402
2
76
IN
76
IN
75
46 75
33
IN
I2C Addr:
0x26/0x27 (Wr/Rd)
R9338
R9334
10K
1/16W
MF-LF
402
T29_A_BIAS_R2DN0
8
IN
C9370
0.47UF
C9371
0.47UF
GND_VOID=TRUE
C9372
0.47UF
C9373
0.47UF
GND_VOID=TRUE
T29_A_BIAS_R2DP1
8
IN
T29_A_BIAS_R2DN1
8
IN
GND_VOID=TRUE
GND_VOID=TRUE
(C9380/C9381)
C9380
0.47UF
C9381
0.47UF
GND_VOID=TRUE
C9382
0.47UF
C9383
0.47UF
GND_VOID=TRUE
C9364
0.22UF
C9365
0.22UF
C9360
0.22UF
C9361
0.22UF
=PP3V3_S0_DPSDRVA
7
DP_A_PWRDWN
75
IC supports input
high while Vcc = 0V.
1
R9393
51
5%
1/20W
MF
201
2
R9396
1
10K
5%
1/16W
MF-LF
402
2
21
5%
TBT_A_HV_EN
P2R = Plug to Receptacle
R2P = Receptacle to Plug
1
R9339
1M
5%
1/16W
MF-LF
402
2
21
20%
CERM-X5R-1
21
20%
CERM-X5R-1
21
20%
CERM-X5R-1
21
20%
CERM-X5R-1
21
20%
CERM-X5R-1
21
20%
CERM-X5R-1
21
20%
CERM-X5R-1
21
20%
CERM-X5R-1
21
20%
X5R
21
20%
X5R
21
20%
X5R
21
20%
X5R
C9359
0.1UF
X7R-CERM
0402
1K
5%
1/20W
MF
201
4V
201
4V
201
4V
201
4V
201
4V
201
4V
201
4V
201
4V
201
6.3V
0201
6.3V
0201
6.3V
0201
6.3V
0201
10%
16V
1 2
GND_VOID=TRUE
R9372
1.5K
T29_R2D_P<0>
83
T29_R2D_N<0>
83
GND_VOID=TRUE
1.5K
R9373
T29 Path
Biasing
GND_VOID=TRUE
R9382
1.5K
T29_R2D_P<1>
83
T29_R2D_N<1>
83
GND_VOID=TRUE
1.5K
R9383
DP_SDRVA_ML_P<0>
83
DP_SDRVA_ML_N<0>
83
DP_SDRVA_ML_P<2>
83
DP_SDRVA_ML_N<2>
1
2
CRITICAL
5
U9359
74LVC1G04DBDCK
2
4
DP_A_BIAS
SC70
3
DP_SDRVA_ML_N<3>
83
DP_SDRVA_ML_P<3>
83
DP_SDRVA_ML_N<1>
83
DP_SDRVA_ML_P<1>
83
DP_SDRVA_AUXCH_P
83
DP_SDRVA_AUXCH_N
83
DP_SDRVA_HPD
CKPLUS_WAIVE=NdifPr_badTerm
T29_A_RSVD_N
T29_A_RSVD_P
(T29_A_LSX_P2R)
(T29_A_LSX_R2P)
T29_D2R1_BIASP
T29_D2R1_BIASN
R9397
1K
5%
1/20W
MF
201
1 2
CBTL04DP081 (353S3151) and
PI3vEDP212 (353S3055) are
footprint-compatible parts with
similar pinouts. NXP uses pin
10 for ML and HPD, Pericom uses
pin 10 for ML and pin 11 for HPD.
35 76
OUT
DP_A_PWRDWN
75
T29_A_BIAS
8
76
6 3
T29 A High-Speed Signals
T29_D2R_C_P<0>
T29_D2R_C_N<0>
(D9364.2)
T29: TX_0
T29DPA_ML_C_P<0>
T29DPA_ML_C_N<0>
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
R9374
R9375
GND_VOID=TRUE
(D9372/D9373)
(D9365.2)
1.5K
1.5K
T29_D2R_C_P<1>
T29_D2R_C_N<1>
(D9360.2)
T29: TX_1
T29DPA_ML_C_P<2>
T29DPA_ML_C_N<2>
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
R9384
GND_VOID=TRUE
R9385
201
201
(D9382/D9383)
(D9361.2)
1.5K
1.5K
Both R’s must connect
to C in star topology.
DP_A_BIAS0
8
VOLTAGE=3.3V
DP_A_BIAS2
8
VOLTAGE=3.3V
R9363
21
21
21
21
5%
1/20W
MF
201
1/20W
5%
MF
201
1/20W
5%
MF
201
1/20W
5%
MF 201
D9364
BAR90-02LRH
D9372
BAR90-02LRH
D9373
BAR90-02LRH
D9365
BAR90-02LRH
D9372/D9373:
D9364/D9365:
D9360
BAR90-02LRH
D9382
BAR90-02LRH
D9383
BAR90-02LRH
D9361
BAR90-02LRH
R9361
R9360
R9365
R9364
KA
TSLP-2-7
KA
TSLP-2-7
KA
TSLP-2-7
KA
TSLP-2-7
CRITICAL
CRITICAL
CRITICAL
CRITICAL
(All 4 D’s)
SIGNAL_MODEL=T29PIN
SIGNAL_MODEL=T29PIN
SIGNAL_MODEL=EMPTY
SIGNAL_MODEL=EMPTY
KA
TSLP-2-7
KA
TSLP-2-7
KA
TSLP-2-7
KA
TSLP-2-7
CRITICAL
CRITICAL
CRITICAL
CRITICAL
(All 4 D’s)
SIGNAL_MODEL=T29PIN
SIGNAL_MODEL=T29PIN
(D9382/D9383)
SIGNAL_MODEL=EMPTY
SIGNAL_MODEL=EMPTY
(D9360/D9361)
DP Path Biasing
1.5K
1.5K
1.5K
1.5K
21
5%
MF 201
21
5%MF1/20W
21
5%MF1/20W
21
5%
MF 201
GND_VOID=TRUE
GND_VOID=TRUE
1/20W
1/20W
DP/T29 A Low-Speed MUX
PP3V3_SW_TBTAPWR
Must be 3.3V DP A port power
OMIT_TABLE
NC
Note: U9390 ML/HPD defaults to T29 mode so that DP/T29
Display can detect host T29 support using I2C
pull-ups on ML<3>. U9390 AUX defaults to DP mode
because 100-ohm pull-downs would defeat DP Sink’s
detection of DP Source.
75 76
292016129
31
DIN1_0+
30
DIN1_0-
27
DIN1_1+
26
DIN1_1-
19
AUX1+
18
AUX1-
17
HPD_1
25
DIN2_0+
24
DIN2_0-
23
DIN2_1+
22
DIN2_1-
15
AUX2+
14
AUX2-
13
HPD_2
10
GPU_SEL
32
AUX_SEL
11
NC
THMPAD
33
PAGE TITLE
3
VDD
U9390
CBTL04DP081
HVQFN
DOUT_0+
DOUT_0-
CRITICAL
DOUT_1+
DOUT_1-
AUX+
AUX-
HPD_IN
LO=Port A
HI=Port B
GND
SIGNAL_MODEL=T29DP_MUX
28
21
DisplayPort/T29 A MUXing
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
1
R9399
100K
5%
1/20W
MF
201
2
1
2
4
5
6
7
8
T29DPA_ML_N<3>
T29DPA_ML_P<3>
T29: Unused
T29DPA_ML_N<1>
T29DPA_ML_P<1>
T29: LSX_A_R2P/P2R (P/N)
DP_A_EXT_AUXCH_P
DP_A_EXT_AUXCH_N
T29: RX_1 Bias Sink
DP_A_EXT_HPD
1
R9398
100K
5%
1/20W
MF
201
2
Apple Inc.
51
5%
1/20W
MF
201
1
C9390
0.1UF
20%
10V
2
CERM
402
SYNC_DATE=02/15/2011SYNC_MASTER=K90I_MLB
21
5%MF1/20W
21
5%MF1/20W
21
5%
MF
21
5%
MF
1
R9362
51
5%
1
1/20W
MF
201
2
C9358
2
0.1UF
X7R-CERM
1
2
DRAWING NUMBER
051-9058
REVISION
6.0.0
BRANCH
PAGE
93 OF 109
SHEET
75 OF 86
124578
IN
IN
OUT
OUT
201
201
IN
IN
OUT
OUT
1/20W
201
1/20W
201
21
10%
16V
0402
C9391
0.1UF
20%
10V
CERM
402
OUT
BI
BI
OUT
BI
BI
IN
76 83
76 83
76 83
76 83
76 83
76 83
76 83
76 83
76 83
76 83
76 83
76 83
76 83
76 83
46 75
SIZE
D
C
B
A
D
8 7 6 5 4 3
12
3.3V/HV Power MUX
V3P3 must be S4 to support
wake from Thunderbolt devices.
=PP3V3_S4_TBTAPWRSW
7
CRITICAL
C9487
D
100UF
POLY-TANT
CASE-B2-SM
CRITICAL
1
C9480
22UF
X5R-CERM-1
4.7UF
X5R-CERM
0603
73
35 75
8
20%
6.3V
603
1
10%
25V
2
=TBTAPWRSW_EN
IN
TBT_A_HV_EN
IN
=TBT_S0_EN
IN
20%
6.3V
2
=PPHV_SW_TBTAPWRSW
7
20V Max
C9415
1
2
C9410
0.1UF
603-1
1
C9481
0.1UF
20%
10V
2
CERM
402
10%
50V
X7R
19
20
1
2
16 15
17
C
For 12V systems:
DESCRIPTION
RES,MTL FILM,1/16W,17.8K,1,0402,SMD,LF
RES,MTL FILM,1/16W,17.8K,1,0402,SMD,LF
21
8
75
OUT
1
1
R9499
2.2K
5%
5%
1/20W
MF
MF
201
201
2
2
GND_VOID=TRUE
1
51
5%
1/20W
MF
201
2
GND_VOID=TRUE
QTY
2
2
C9490
0.1UF
10%
16V
X7R-CERM
0402
T29_A_BIAS
VOLTAGE=3.3V
R9498
2.2K
1/20W
PART NUMBER
114S0338
114S0338
Nominal Min Max
IHVS0/S3 1120mA 1090mA 1170mA (12W minimum)
T29_A_BIAS_R
75
IN
R9491
B
T29_A_BIAS_D2RN1
8
IN
T29_A_BIAS_D2RP1
8
IN
75 83
75 83
T29_D2R_C_P<1>
OUT
T29_D2R_C_N<1>
OUT
Nominal Min Max
IV3P3 1100mA 1030mA 1200mA
IHVS0 890mA 830mA 930mA (assumes 15V, 12W minimum)
IHVS3 890mA 830mA 930mA (assumes 3S, 9-12.6V, 7.5-11.7W)
18
V3P3OUT
V3P3
6
VHV
7
CRITICAL
U9410
CD3210A0RGP
RSVD
5
EN
HV_EN
S0
GND
1
TBTHV:P15V
QFN
ISET_V3P3
432
R9413
22.6K
ISET_S0
ISET_S3
13
1%
1/20W
MF
201
OUT
RSVD
THRM
PAD
21
1
2
12
14
C9485
0.1UF
20%
10V
CERM
402
8
TBTAPWRSW_ISET_V3P3
1011
TBTAPWRSW_ISET_S0
9
TBTAPWRSW_ISET_S3
TBTAPWRSW_ISET_S3_R
TBTAPWRSW_ISET_S0_R
TBTHV:P15V
1
R9414
22.6K
1%
1/20W
MF
201
2
<RHVS0><RHVS3>
REFERENCE DES
R9410,R9413
R9411,R9414
T29_D2R_C_P<0>
75 83
OUT
T29_D2R_C_N<0>
75 83
OUT
GND_VOID=TRUE
R9494
SIGNAL_MODEL=EMPTY
T29DPA_ML_P<3>
75 83
BI
T29DPA_ML_N<3>
75 83
BI
T29: Unused
D9498
BAR90-02LRH
D9499
BAR90-02LRH
SIGNAL_MODEL=T29PIN
SIGNAL_MODEL=T29PIN
(Both L’s)
DP_A_EXT_AUXCH_P
75 83
BI
DP_A_EXT_AUXCH_N
75 83
BI
KA
TSLP-2-7
KA
TSLP-2-7
CRITICAL
CRITICAL
GND_VOID=TRUE
GND_VOID=TRUE
1
1
2
2
12V: See
below
ILIM = 40000 / RISET
CRITICAL
1
1K
5%
1/20W
MF
201
2
C9486
10UF
20%
6.3V
X5R
603
TBTHV:P15V
R9410
22.6K
1%
1/20W
MF
201
Single-fault protection
requires two R’s per HV
ISET_Sx with CD3210.
Single R on ISET_V3P3 OK.
GND_VOID=TRUE
1
R9495
1K
5%
1/20W
MF
201
2
SIGNAL_MODEL=EMPTY
1
C9498
30PF
5%
50V
2
CERM
402
PP3V3_SW_TBTAPWR
MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=3.3V
PPHV_SW_TBTAPWR
MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=15V
1
C9411
0.1UF
10%
50V
2
X7R
603-1
TBTHV:P15V
1
1
R9411
22.6K
1%
1/20W
MF
201
2
2
75
1
R9412
36.5K
1%
1/20W
MF
201
2
<RV3P3>
BOM OPTION
TBTHV:P12V
TBTHV:P12V
1
C9400
0.01UF
10%
50V
2
X7R
402
CRITICAL
650NH-5%-0.430MA-0.52OHM
650NH-5%-0.430MA-0.52OHM
L9498
2 1
0603
SIGNAL_MODEL=EMPTY
T29DPA_D2R1_AUXCH_P
83
T29DPA_D2R1_AUXCH_N
83 83
CRITICAL
L9499
2 1
0603
SIGNAL_MODEL=EMPTY
1
C9499
30PF
5%
50V
2
CERM
402
GND_VOID=TRUE
GND_VOID=TRUE
C9402
0.01UF
X5R-CERM
0201
10%
10V
L9400
FERR-120-OHM-3A
0603
T29 Dir
MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=18V
1
1
C9401
0.01UF
10%
50V
2
2
X7R
402
21
PP3V3RHV_SW_DPAPWR
MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=18V
DPACONN_20_RC
DP Dir
R9401
12
5%
1/20W
MF
201
Thunderbolt Connector A
For J9400 T29 SMT pads
(3, 5, 17 & 19):
GND_VOID=TRUE
GND_VOID=TRUEGND_VOID=TRUEGND_VOID=TRUE
CRITICAL
J9400
DSPLYPRT-M97-1
F-RT-THSM
BOT ROW TOP ROW
TH PINS SM PINS
2
HOT_PLUG_DETECT
4
CONFIG1
6
CONFIG2
8 7
GND
10
ML_LANE3P
12
ML_LANE3N
14 13
GND
16
AUX_CHP
18
AUX_CHN
20
DP_PWR
SHIELD PINS
21
ML_LANE0P
ML_LANE0N
ML_LANE1P
ML_LANE1N
ML_LANE2P
ML_LANE2N
22 21
GND
GND
GND
RETURN
GND_DPACONN_1_C
MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=0V
DP Dir
1
3
5
9
11
15
17
19
GND_DPACONN_7_C
MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=0V
C9405
0.01UF
21
10%
25V
T29 Dir
X5R-CERM
0201
T29DPA_ML_P<0>
83
T29DPA_ML_N<0>
83
T29: TX_0
C9406
0.01UF
21
10%
25V
X5R-CERM
0201
T29: LSX_R2P/P2R (P/N)
T29DPA_ML_P<2>
83
T29DPA_ML_N<2>
T29: TX_1
GND_VOID=TRUE
GND_VOID=TRUE
(Both C’s)
C9470
0.47UF
C9471
0.47UF
GND_VOID=TRUE
1
R9470
470K
5%
1/20W
MF
201
2
C9472
0.47UF
C9473
0.47UF
GND_VOID=TRUE
1
R9472
470K
5%
1/20W
MF
201
2
470k R’s for ESD protection
on AC-coupled signals.
21
20%
CERM-X5R-1
21
20%
CERM-X5R-1
GND_VOID=TRUE
1
R9471
470K
5%
1/20W
MF
201
2
GND_VOID=TRUE
GND_VOID=TRUE
(Both C’s)
21
20%
CERM-X5R-1
21
20%
CERM-X5R-1
GND_VOID=TRUE
1
R9473
470K
5%
1/20W
MF
201
2
4V
201
4V
201
4V
201
4V
201
T29DPA_ML_C_P<0>
T29DPA_ML_C_N<0>
T29DPA_ML_P<1>
T29DPA_ML_N<1>
T29DPA_ML_C_P<2>
T29DPA_ML_C_N<2>
D
C
75 83
IN
75 83
IN
75 83
IN
75 83
BI
75 83
IN
75 83
IN
B
T29DPA_HPD
75
A
OUT
T29DPA_CONFIG1_RC
75
OUT
T29DPA_CONFIG2_RC
75
OUT
R9452
1/16W
MF-LF
402
SIZE
A
D
DP Source must pull
down HPD input with
greater than or equal
330PF
10%
50V
X7R-CERM
0402
to 100K (DPv1.1a).
Sink HPD range:
High: 2.0 - 5.0V
Low: 0 - 0.8V
1
1
R9451
1M
1M
5%
5%
1/16W
MF-LF
402
2
2
C9494
330PF
10%
50V
X7R-CERM
0402
1
1
C9495
2
2
1
R9441
100K
5%
1/16W
MF-LF
402
2
PAGE TITLE
Thunderbolt Connector A
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
6 3
SYNC_DATE=02/15/2011SYNC_MASTER=K90I_MLB
DRAWING NUMBER
051-9058
REVISION
BRANCH
PAGE
94 OF 109
SHEET
124578
6.0.0
76 OF 86
8 7 6 5 4 3
12
PPBUS S0 LCDBkLT FET
MOSFET
CHANNEL
CRITICAL
Q9706
FDC638APZ_SBMS001
F9700
D
=PPBUS_S0_LCDBKLT
7
3AMP-32V-467
8
IN
603-HF
BOTTOM
LCD_BKLT_EN
21
PPBUS_S0_LCDBKLT_FUSED
MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=12.6V
1
R9788
301K
1%
1/16W
MF-LF
402
2
LCDBKLT_EN_DIV
1
R9789
147K
1%
1/16W
MF-LF
402
2
LCDBKLT_EN_L
Q9707
SSM6N15AFE
SOT563
5
C9782
0.1UF
X7R-CERM
3
D
SG
4
LCDBKLT_DISABLE
Q9707
SSM6N15AFE
SOT563
0402
1
10%
16V
2
SSOT6-HF
4
3
6
D
RDS(ON)
LOADING
PPBUS_SW_LCDBKLT_PWR
MIN_LINE_WIDTH=0.4 mm
6521
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=12.6V
=PP3V3_S0_BKL_VDDIO
7
C
2
SG
24
BKLT_PLT_RST_L
IN
1
FDC638APZ
P-TYPE
43 mOhm @4.5V
0.715 A (EDP)
8
THERE IS A SENSE RESISTOR BETWEEN
PPBUS_SW_LCDBKLT_PWR
AND PPBUS_SW_BKL
ON THE SENSOR PAGE
=PP5V_S0_BKL
7
=PPBUS_SW_BKL
8
PLACE_NEAR=L9701.1:4mm
77
CRITICAL
C9712
10UF
10%
25V
X5R
805
PLACE_NEAR=U9701.C4:4mm
1
2
1
C9713
0.1UF
10%
25V
2
X5R
402
PLACE_NEAR=L9701.1:3mm
PLACE_NEAR=U9701.D1:5mm
1
C9711
0.1UF
10%
16V
2
X7R-CERM
0402
C9710
603-1
1UF
*C9797 AND C9799 SHOULD BE PLACED IN T-BONE FOR ACOUSTICS
*PPBUS_SW_LCDBKLT_PWR_SW SHOULD BE KEPT AS SHORT AS POSSIBLE.
*LCD_BKLT_PWM SHOULD BE AWAY FROM BOOST CIRCUIT
PLACE_NEAR=L9701.2:3mm
CRITICAL
L9701
33UH-1.8A-110MOHM
PLACE_NEAR=U9701.D1:3mm
1
1
C9714
10%
25V
X5R
0.01UF
10%
16V
2
2
X7R-CERM
0402
1217AS-2SM
21
PPBUS_SW_LCDBKLT_PWR_SW
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=40V
SWITCH_NODE=TRUE
DIDT=TRUE
PPVOUT_SW_LCDBKLT_FB
VOLTAGE=40V
MIN_LINE_WIDTH=0.1 MM
MIN_NECK_WIDTH=0.1 MM
CRITICAL
D9701
SOD-123
RB160M-60G
XW9720
SM
PLACE_NEAR=C9797.1:5mm
KA
21
PLACE_NEAR=U9701.A5:3mm
1
C9796
220PF
10%
50V
2
X7R-CERM
0402
CRITICAL
1
C9797
10UF
10%
50V
2
X5R
1210-1
PLACE_NEAR=D9701.2:3mm
CRITICAL
1
C9799
10UF
10%
50V
2
X5R
1210-1
PLACE_NEAR=D9701.2:5mm
PPVOUT_SW_LCDBKLT
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.375 MM
VOLTAGE=50V
D
6
74
C
R9755
10K
21
5%
1/16W
MF-LF
402
R9741
10K
21
5%
R9753
0
1
C9704
33PF
5%
50V
2
C0G-CERM
0402
1/16W
MF-LF
21
5%
402
R9731
301K
1%
1/16W
MF-LF
402
=I2C_BKL_1_SCL
48
Addr: 0x58(Wr)/0x59(Rd)
IN
=I2C_BKL_1_SDA
48
BI
PPBUS_SW_LCDBKLT_PWR
8
77
B
LCD_BKLT_PWM
8
IN
R9757
0
5%
1/16W
MF-LF
402
R9704
33
5%
1/16W
MF-LF
402
21
21
1/16W
MF-LF
402
21
2
R9715
100K
1%
1/16W
MF-LF
402
1
see spec for others
TP_BKL_FAULT
PLACE_SIDE=BOTTOM
Fpwm=9.62kHz
R9716
90.9K
1/16W
MF-LF
BKL_VSYNC_R
BKL_FLTR
BKL_ISET
BKL_FSET
BKL_SCL
BKL_SDA
BKL_PWM
BKL_EN
I_LED=22.7mA
1
1
R9714
16.2K
1%
1%
1/16W
MF-LF
402
402
2
2
GND_BKL_SGND
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=0V
I_LED=369/Riset
(EEPROM should set EN_I_RES=1)
D2
C2
B3
B4
D3
D4
A4
A3
C3
C4
VDDIO
VSYNC
FILTER
ISET
FSET
SCLK
SDA
PWM
EN
FAULT
D1
C1
VIN
VLDO
U9701
25-BUMP-MICRO
SW_0
SW_1
B1
B2
A5
FB
LP8550
E5
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
CRITICAL
GND_SW
GND_SW
GND_S
GND_L
A2
A1B5E4
PLACEMENT_NOTE=Keep away from noise nodes(E4, A1, A2, B1, B2 pins)
XW9710
SM
BKL_ISEN1
D5
BKL_ISEN2
C5
BKL_ISEN3
E3
BKL_ISEN4
E2
BKL_ISEN5
E1
BKL_ISEN6
21
PLACE_NEAR=U9701.E5:10mm
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm
PLACE_NEAR=U9701.D5:10mm
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm
PLACE_NEAR=U9701.C5:10mm
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm
PLACE_NEAR=U9701.E3:10mm
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm
PLACE_NEAR=U9701.E2:10mm
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm
PLACE_NEAR=U9701.E1:10mm
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm
BOTTOM
BOTTOM
BOTTOM
BOTTOM
BOTTOM
BOTTOM
BKLT:PROD
R9717
0
5%
1/16W
MF-LF
402
BKLT:PROD
R9718
0
5%
1/16W
MF-LF
402
BKLT:PROD
R9719
0
5%
1/16W
MF-LF
402
BKLT:PROD
R9720
0
5%
1/16W
MF-LF
402
BKLT:PROD
R9721
0
5%
1/16W
MF-LF
402
BKLT:PROD
R9722
0
5%
1/16W
MF-LF
402
21
LED_RETURN_1
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm
21
LED_RETURN_2
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm
21
LED_RETURN_3
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm
21
LED_RETURN_4
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm
21
LED_RETURN_5
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm
21
LED_RETURN_6
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm
6
74
OUT
6
74
OUT
B
6
74
OUT
6
74
OUT
6
74
OUT
6
74
OUT
A
PART NUMBER
103S0198
103S0198
QTY
3
RES,THIN FLIM,1/16W,10.2 OHM,0.1,0402,SM
3
RES,THIN FLIM,1/16W,10.2 OHM,0.1,0402,SM
DESCRIPTION
6 3
REFERENCE DES
R9717,R9718,R9719
R9720,R9721,R9722
CRITICAL
BOM OPTION
BKLT:ENG
BKLT:ENG
10.2 ohm resistors for current
measurement on LED strings.
PAGE TITLE
LCD Backlight Driver
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
SYNC_DATE=07/08/2011SYNC_MASTER=J31_MLB
DRAWING NUMBER
051-9058
REVISION
6.0.0
BRANCH
PAGE
97 OF 109
SHEET
77 OF 86
124578
SIZE
A
D
8 7 6 5 4 3
12
CPU Signal Constraints
LAYER
CPU_50S
CPU_55S
CPU_27P4S
ALLOW ROUTE
ON LAYER?
*
*
=55_OHM_SE =55_OHM_SE
=27P4_OHM_SE
*
NOTE: 7 mil gap is for VCCSense pair, which Intel says to route with 7 mil spacing without specifying a target impedance.
LAYER
D
SPACING_RULE_SET
CPU_AGTL
CPU_8MIL
CPU_COMP
CPU_ITP
CPU_VCCSENSE
Most CPU signals with impedance requirements are 50-ohm single-ended.
Some signals require 27.4-ohm single-ended impedance.
LINE-TO-LINE SPACING
*
* ?
*
SOURCE: Huron River SFF DG (DG-438297_v1.0), Section 4.18 and Huron River Platform Power Delivery DG v1.0 Section 2.7
=STANDARD
8 MIL
20 MIL
=2:1_SPACING
25 MIL
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
=50_OHM_SE =50_OHM_SE=50_OHM_SE =50_OHM_SE
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
=27P4_OHM_SE
SPACING_RULE_SET
CPU_AGTL
=27P4_OHM_SE
WEIGHT
?*
?
?
?*
=55_OHM_SE=55_OHM_SE
=27P4_OHM_SE
LAYER
TOP,BOTTOM
LINE-TO-LINE SPACING
=2x_DIELECTRIC
PCI-Express
PCIE_85D
SPACING_RULE_SET
LAYER
LAYER
*
*
ALLOW ROUTE
ON LAYER?
=85_OHM_DIFF
=90_OHM_DIFF
LINE-TO-LINE SPACING
CLK_PCIE
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
* ?
C
PCIE_PCH_RX2RX =3x_DIELECTRIC
PCIE_PCH_RX2TX
PCIE_PCH_2OTHER
NET_SPACING_TYPE1 NET_SPACING_TYPE2
PCIE_PCH_TX
PCIE_PCH_TX
PCIE_PCH_RX
PCIE_PCH_RX
PCIE_PCH_TX
PCIE_PCH_RX
SOURCE: 471984_Cheif_River_MS_PDG_1.0 and the spacing rule is adjusted per SI team feedback.
* ?
* ?
* ?
*_PCH_TX
*_PCH_RX
*_PCH_RX
*_PCH_TX
*
20 MIL
=3X_DIELECTRICPCIE_PCH_TX2TX
=4X_DIELECTRICPCIE_PCH_TX2RX
=4x_DIELECTRIC
=3x_DIELECTRIC
AREA_TYPE
*
*
*
*
**
*
MINIMUM LINE WIDTH
=85_OHM_DIFF
=90_OHM_DIFF
WEIGHT
WEIGHT
SPACING_RULE_SET
PCIE_PCH_TX2TX
PCIE_PCH_TX2RX
PCIE_PCH_RX2RX
PCIE_PCH_RX2TX
PCIE_PCH_2OTHER
PCIE_PCH_2OTHER
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
?*
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
?*
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
MINIMUM NECK WIDTH
=90_OHM_DIFFCLK_PCIE_90D
SPACING_RULE_SET
PCIE_PCH_TX2TX
PCIE_PCH_TX2RX
PCIE_PCH_RX2RX
PCIE_PCH_RX2TX
PCIE_PCH_2OTHER
MAXIMUM NECK LENGTH
=85_OHM_DIFF=85_OHM_DIFF
=90_OHM_DIFF
LAYER
TOP,BOTTOM
TOP,BOTTOM
TOP,BOTTOM
TOP,BOTTOM
TOP,BOTTOM
LINE-TO-LINE SPACING
=4X_DIELECTRIC
=5X_DIELECTRIC
=4x_DIELECTRIC
=4x_DIELECTRIC
=4x_DIELECTRIC
DIFFPAIR PRIMARY GAP
=STANDARD
=STANDARD =STANDARD
7 MIL
WEIGHT
DIFFPAIR PRIMARY GAP
=85_OHM_DIFF
=90_OHM_DIFF
WEIGHT
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
?
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
?
TABLE_SPACING_RULE_ITEM
?
TABLE_SPACING_RULE_ITEM
?
TABLE_SPACING_RULE_ITEM
?
TABLE_SPACING_RULE_ITEM
?
=STANDARD
7 MIL
=85_OHM_DIFF
=90_OHM_DIFF
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
CPU Net Properties
ELECTRICAL_CONSTRAINT_SET
DMI_S2N
DMI_S2N
DMI_N2S
DMI_N2S
FDI_DATA
CPU_PECI
PM_SYNC
PM_MEM_PWRGD
CPU_SM_RCOMP
CPU_SM_RCOMP
CPU_SM_RCOMP
CPU_CATERR_L
CPU_PROCHOT_L
CPU_PWRGD
PM_THRMTRIP_L
DMI_CLK100M
DMI_CLK100M
ITPCPU_CLK100M
ITPCPU_CLK100M
ITPCPU_CLK100M
I125
ITPCPU_CLK100M
I126
ITPCPU_CLK100M
I127
ITPCPU_CLK100M
I128
I121
XDP_TRST_L
XDP_BPM_L
XDP_BPM_R_L
(FSB_CPURST_L)
NET_TYPE
PHYSICAL
PCIE_85D
PCIE_85D
PCIE_85D
PCIE_85D
PCIE_85DFDI_DATA
PCIE_85D
CPU_50S
CPU_50S
CPU_50S
CPU_50S
CPU_50S
CPU_50S
CPU_50S CPU_ITP
CPU_50S
CPU_50S
CPU_27P4S
CPU_27P4S
CPU_27P4S
CPU_50S
CPU_50S
CPU_50S
CPU_50S
CPU_50S
CLK_PCIE_90D
CLK_PCIE_90D
CLK_PCIE_90D
CLK_PCIE_90D
CLK_PCIE_90D
CLK_PCIE_90D
CLK_PCIE_90D
CLK_PCIE_90D
CPU_27P4S
CPU_27P4S
CPU_50S CPU_ITPXDP_TDO
CPU_50S CPU_ITPXDP_TMS
CPU_50SXDP_TCK CPU_ITP
CPU_50S CPU_ITP
CPU_50S
CPU_50S
PCIE_PCH_TX
PCIE_PCH_TX
PCIE_PCH_RX
PCIE_PCH_RX
PCIE_PCH_RX
PCIE_PCH_RX
CPU_AGTL
CPU_AGTL
CPU_AGTL
CPU_COMP
CPU_AGTL
CPU_AGTL
CPU_ITPCPU_50S
CPU_ITPCPU_50S
CPU_AGTL
CPU_AGTL
CPU_COMP
CPU_COMP
CPU_COMP
CPU_ITPCPU_50S
CPU_AGTL
CPU_AGTL
CPU_AGTL
CPU_AGTL
CPU_8MIL
CLK_PCIE
CLK_PCIE
CLK_PCIE
CLK_PCIE
CLK_PCIE
CLK_PCIE
CLK_PCIE
CLK_PCIE
CPU_COMP
CPU_COMP
CPU_ITPCPU_50SXDP_TDI
CPU_ITP
CPU_ITPCPU_50S
CPU_ITP
SPACING
DMI_S2N_P<3:0>
DMI_S2N_N<3:0>
DMI_N2S_P<3:0>
DMI_N2S_N<3:0>
FDI_DATA_P<7:0>
FDI_DATA_N<7:0>
FDI_FSYNC<1..0>
FDI_LSYNC<1..0>
FDI_INT
CPU_PECI
PM_SYNC
PM_MEM_PWRGD
XDP_DBRESET_L
XDP_CPU_PRDY_L
XDP_CPU_PREQ_L
PM_EXT_TS_L<0>
PM_EXT_TS_L<1>
CPU_SM_RCOMP<0>
CPU_SM_RCOMP<1>
CPU_SM_RCOMP<2>
CPU_CFG<11..0>
CPU_CATERR_L
CPU_VCCIO_SEL
CPU_PROCHOT_L
CPU_PWRGD
PM_THRMTRIP_L
DMI_CLK100M_CPU_P
DMI_CLK100M_CPU_N
ITPCPU_CLK100M_P
ITPCPU_CLK100M_N
ITPXDP_CLK100M_P
ITPXDP_CLK100M_N
XDP_CPU_CLK100M_P
XDP_CPU_CLK100M_N
EDP_COMP
CPU_PEG_COMP
XDP_CPU_TDI
XDP_CPU_TDO
XDP_CPU_TMS
XDP_CPU_TCK
XDP_CPU_TRST_L
XDP_BPM_L<3..0>
CPU_CFG<15..12>
XDP_CPURST_L
9
17
9
17
9
17
9
17
9
17
9
17
9
17
9
17
9
17
10 19 46
10 17
10 17 26
10 23 24
10 23
10 23
10
10
10
9
23
10 45
8
12
10 45 46 68
10 19 23
10 19 46
10 16
10 16
10 16
10 16
16 23
16 23
23
23
9
9
10 23
10 23
10 23
10 23
10 23
10 23
9
23
23
D
C
CPU_VCCSENSE_P
CPU_VCCSENSE_N
CPU_VCCIOSENSE_P
CPU_VCCIOSENSE_N
CPU_AXG_SENSE_P
CPU_AXG_SENSE_N
CPU_VDDQ_SENSE_P
CPU_VDDQ_SENSE_N
CPU_AXG_VALSENSE_P
CPU_AXG_VALSENSE_N
CPU_VCC_VALSENSE_P
CPU_VCC_VALSENSE_N
CPU_VIDALERT_L
CPU_VIDSCLK
CPU_VIDSOUT
12 68
12 68
12 70
12 70
12 68
12 68
12
12
9
9
9
9
12 68
12 68
12 68
I115
I116
I117
I118
I119
I120
I122
I123
I124
CPU_VCCAXG_SENSE
CPU_VCCAXG_SENSE
CPU_VCCSENSE
CPU_VCCSENSE
CPU_VCCAXG_SENSE
CPU_VCCAXG_SENSE
CPU_VALSENSE
CPU_VALSENSE
CPU_VALSENSE
CPU_VALSENSE
CPU_VALSENSE
CPU_VALSENSE
CPU_SVIDALERT_L
CPU_SVIDSCLK
CPU_SVIDSOUT
B
CPU_27P4S
CPU_27P4S
CPU_27P4S
CPU_27P4S
CPU_27P4S
CPU_27P4S
CPU_27P4S
CPU_27P4S
CPU_27P4S
CPU_27P4S
CPU_27P4S
CPU_27P4S
CPU_50S
CPU_50S
CPU_50S
CPU_VCCSENSE
CPU_VCCSENSE
CPU_VCCSENSE
CPU_VCCSENSE
CPU_VCCSENSE
CPU_VCCSENSE
CPU_VCCSENSE
CPU_VCCSENSE
CPU_VCCSENSE
CPU_VCCSENSE
CPU_VCCSENSE
CPU_VCCSENSE
CPU_COMP
CPU_COMP
CPU_COMP
A
6 3
CPU_VCCSA_VID<0>
CPU_VCCSA_VID<1>
SYNC_MASTER=K90I_MLB SYNC_DATE=02/15/2011
PAGE TITLE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
CPU Constraints
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
DRAWING NUMBER
051-9058
REVISION
6.0.0
BRANCH
PAGE
100 OF 109
SHEET
78 OF 86
124578
SIZE
B
A
D
8 7 6 5 4 3
12
Memory Bus Constraints
LAYER
MEM_37S
MEM_40S
MEM_72D
MEM_50S
MEM_85D
MEM_50S
D
MEM_85D
MEM_50S
MEM_85D
TOP,BOTTOM
TOP,BOTTOM
ISL10
ISL10
ISL3,ISL4,ISL9
ISL3,ISL4,ISL9
ALLOW ROUTE
ON LAYER?
*
*
*
=72_OHM_DIFF
Y
Y
N
N
Y
Y
MINIMUM LINE WIDTH
=72_OHM_DIFF
=85_OHM_DIFF
MINIMUM NECK WIDTH
=72_OHM_DIFF
=50_OHM_SE=50_OHM_SE
=85_OHM_DIFF
=50_OHM_SE
=85_OHM_DIFF=85_OHM_DIFF
=50_OHM_SE
=85_OHM_DIFF=85_OHM_DIFF
MAXIMUM NECK LENGTH
=37_OHM_SE=37_OHM_SE=37_OHM_SE =37_OHM_SE
=40_OHM_SE=40_OHM_SE =40_OHM_SE =40_OHM_SE
=72_OHM_DIFF
=50_OHM_SE
=85_OHM_DIFF
=50_OHM_SE=50_OHM_SE
=85_OHM_DIFF
=50_OHM_SE=50_OHM_SE
=85_OHM_DIFF
DIFFPAIR PRIMARY GAP
=STANDARD
=STANDARD
=STANDARD =STANDARD
=85_OHM_DIFF =85_OHM_DIFF
C
SPACING_RULE_SET
LAYER
MEM_CLK2MEM
MEM_CTRL2CTRL
MEM_CTRL2MEM
MEM_CMD2CMD
MEM_CMD2MEM
MEM_DATA2DATA
MEM_DATA2MEM =3:1_SPACING
MEM_DQS2MEM
MEM_2OTHER
LINE-TO-LINE SPACING
=4:1_SPACING
* ?
=3:1_SPACING
=2.5:1_SPACING
* ?
* ?
*
=1.5:1_SPACING
=3:1_SPACING
=1.5:1_SPACING
* ?
=3:1_SPACING
*
25 MILS
Memory Bus Spacing Group Assignments
NET_SPACING_TYPE1 NET_SPACING_TYPE2
MEM_CLK
MEM_CLK
B
MEM_CLK
MEM_CLK
MEM_CLK
MEM_CLK
MEM_CTRL
MEM_CMD
MEM_DATA
MEM_DQS
NET_SPACING_TYPE1 NET_SPACING_TYPE2
MEM_CTRL
MEM_CTRL
MEM_CTRL
MEM_CLK
MEM_CTRL
MEM_CMD
MEM_DATAMEM_CTRL
MEM_CTRL
MEM_DQS
NET_SPACING_TYPE1 NET_SPACING_TYPE2
MEM_CLKMEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_CTRL
MEM_CMD
MEM_DATA
MEM_DQSMEM_DQS
DDR3:
A
Sandybridge SFF 2C when routed on Type-3 (Through hole) should follow rPGA guidelines
per Huron River SFF DG rev1.0 (#438297).
DQS intra-pair matching should be within 0.127mm, no inter-pair matching requirement.
DQ to DQS matching per byte lane should be within 0.127mm.
DQS to clock matching should be within [CLK-63.5mm] and [CLK+38.1mm].
CLK intra-pair matching should be within 0.127mm, inter-pair matching should be within 0.0508mm.
CONTROL signals should be matched within [CLK-2.54mm] to [CLK+0.0mm] of CLK pairs.
A/BA/CMD signals should be matched within [CLK-12.7mm] to [CLK+12.7mm] of CLK pairs A/BA/CMD signals to each other should match within 5.08mm.
DQ/DQS/A/BA/cmd signal spacing is 4x dielectric, CLK is 5x dielectric.
Maximum length of any signal from die pad to SODIMM pad is 119.83mm, from procesor ball to SODIMM pad is 88.9mm.
SOURCE: Huron River Platform DG, Rev 1.01 (#436735), Section 2.5
AREA_TYPE
*
*
*
*
*
AREA_TYPE
*
*
*
*
*
AREA_TYPE
*
*
*
*
*
TABLE_SPACING_RULE_HEAD
WEIGHT
TABLE_SPACING_RULE_ITEM
?*
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
?*
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
?
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
?*
TABLE_SPACING_RULE_ITEM
?
MEM_CLK2MEM
MEM_CLK2MEM
MEM_CLK2MEM
MEM_CLK2MEM
MEM_CLK2MEM
MEM_CTRL2MEM
MEM_CTRL2CTRL
MEM_CTRL2MEM
MEM_CTRL2MEM
MEM_CTRL2MEM
MEM_DQS2MEM
MEM_DQS2MEM
MEM_DQS2MEM
MEM_DQS2MEM
MEM_DQS2MEM
TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
SPACING_RULE_SET
SPACING_RULE_SET
SPACING_RULE_SET
NET_SPACING_TYPE1 NET_SPACING_TYPE2
MEM_CLKMEM_CMD
MEM_CMD
MEM_CMD
MEM_CMD
MEM_CTRL
MEM_CMD
MEM_DATA
MEM_DQSMEM_CMD
NET_SPACING_TYPE1 NET_SPACING_TYPE2
MEM_DATA
MEM_DATA
MEM_DATA
MEM_DATA
MEM_DATA
MEM_CLK
MEM_CTRL
MEM_CMD
MEM_DATA
MEM_DQS
NET_SPACING_TYPE1 NET_SPACING_TYPE2
MEM_CLK
MEM_CTRL
* *
MEM_CMD
MEM_DATA
* *
MEM_DQS
Need to support MEM_*-style wildcards!
AREA_TYPE
*
*
*
*
*
AREA_TYPE
*
*
*
*
*
AREA_TYPE
**
**
**
6 3
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
=STANDARD
=STANDARD
=72_OHM_DIFF=72_OHM_DIFF
=STANDARD=STANDARD
=85_OHM_DIFF=85_OHM_DIFF
=STANDARD=STANDARD
=85_OHM_DIFF=85_OHM_DIFF
MEM_CMD2MEM
MEM_CMD2MEM
MEM_CMD2CMD
MEM_CMD2MEM
MEM_CMD2MEM
MEM_DATA2MEM
MEM_DATA2MEM
MEM_DATA2MEM
MEM_DATA2DATA
MEM_DATA2MEM
MEM_2OTHER
MEM_2OTHER
MEM_2OTHER
MEM_2OTHER
MEM_2OTHER
TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
SPACING_RULE_SET
SPACING_RULE_SET
SPACING_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
Memory Net Properties
ELECTRICAL_CONSTRAINT_SET
MEM_A_CLK
MEM_A_CLK
MEM_A_CNTL
MEM_A_CNTL
MEM_A_CNTL
MEM_A_CMD
MEM_A_CMD
MEM_A_CMD
MEM_A_CMD
MEM_A_CMD
MEM_A_DQ_BYTE0
MEM_A_DQ_BYTE1
MEM_A_DQ_BYTE3
MEM_A_DQ_BYTE4
MEM_A_DQ_BYTE5
MEM_A_DQ_BYTE6
MEM_A_DQS0
MEM_A_DQS0
MEM_A_DQS1
MEM_A_DQS1
MEM_A_DQS2
MEM_A_DQS2
MEM_A_DQS3
MEM_A_DQS3
MEM_A_DQS4
MEM_A_DQS4
MEM_A_DQS5
MEM_A_DQS5
MEM_A_DQS6
MEM_A_DQS6
MEM_A_DQS7
MEM_A_DQS7
MEM_B_CLK
MEM_B_CLK
MEM_B_CNTL
MEM_B_CNTL
MEM_B_CNTL
MEM_B_CMD
MEM_B_CMD
MEM_B_CMD
MEM_B_CMD
MEM_B_CMD
MEM_B_DQS0
MEM_B_DQS0
MEM_B_DQS1
MEM_B_DQS1
MEM_B_DQS2
MEM_B_DQS2
MEM_B_DQS3
MEM_B_DQS3
MEM_B_DQS4
MEM_B_DQS4
MEM_B_DQS5
MEM_B_DQS5
MEM_B_DQS6
MEM_B_DQS6
MEM_B_DQS7
MEM_B_DQS7
PHYSICAL
MEM_72D
MEM_37S
MEM_37S
MEM_37S
MEM_40S MEM_CMD
MEM_40S
MEM_50S
MEM_50S
MEM_50SMEM_A_DQ_BYTE2
MEM_50S
MEM_50S
MEM_50S
MEM_50S
MEM_50SMEM_A_DQ_BYTE7
MEM_85D
MEM_85D
MEM_85D
MEM_85D
MEM_85D
MEM_85D
MEM_85D
MEM_85D
MEM_85D
MEM_85D
MEM_85D
MEM_85D
MEM_85D
MEM_85D
MEM_85D
MEM_85D
MEM_72D
MEM_37S
MEM_37S
MEM_37S
MEM_40S
MEM_40S MEM_CMD
MEM_50SMEM_B_DQ_BYTE0
MEM_50SMEM_B_DQ_BYTE1
MEM_50SMEM_B_DQ_BYTE2
MEM_50SMEM_B_DQ_BYTE3
MEM_50SMEM_B_DQ_BYTE4
MEM_50SMEM_B_DQ_BYTE5
MEM_50SMEM_B_DQ_BYTE6
MEM_50SMEM_B_DQ_BYTE7
MEM_85D
MEM_85D
MEM_85D
MEM_85D
MEM_85D
MEM_85D
MEM_85D
MEM_85D
MEM_85D
MEM_85D
MEM_85D
MEM_85D
MEM_85D
MEM_85D
NET_TYPE
SPACING
MEM_CLKMEM_72D
MEM_CLK
MEM_CTRL
MEM_CTRL
MEM_CTRL
MEM_CMDMEM_40S
MEM_CMDMEM_40S
MEM_CMD
MEM_CMDMEM_40S
MEM_DATA
MEM_DATA
MEM_DATA
MEM_DATA
MEM_DATA
MEM_DATA
MEM_DATA
MEM_DATA
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_CLKMEM_72D
MEM_CLK
MEM_CTRL
MEM_CTRL
MEM_CTRL
MEM_CMD
MEM_CMDMEM_40S
MEM_CMDMEM_40S
MEM_CMDMEM_40S
MEM_DATA
MEM_DATA
MEM_DATA
MEM_DATA
MEM_DATA
MEM_DATA
MEM_DATA
MEM_DATA
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQSMEM_85D
MEM_DQS
MEM_DQS
MEM_DQSMEM_85D
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_A_CLK_P<5..0>
MEM_A_CLK_N<5..0>
MEM_A_CKE<3..0>
MEM_A_CS_L<3..0>
MEM_A_ODT<3..0>
MEM_A_A<15..0>
MEM_A_BA<2..0>
MEM_A_RAS_L
MEM_A_CAS_L
MEM_A_WE_L
MEM_A_DQ<7..0>
MEM_A_DQ<15..8>
MEM_A_DQ<23..16>
MEM_A_DQ<31..24>
MEM_A_DQ<39..32>
MEM_A_DQ<47..40>
MEM_A_DQ<55..48>
MEM_A_DQ<63..56>
MEM_A_DQS_P<0>
MEM_A_DQS_N<0>
MEM_A_DQS_P<1>
MEM_A_DQS_N<1>
MEM_A_DQS_P<2>
MEM_A_DQS_N<2>
MEM_A_DQS_P<3>
MEM_A_DQS_N<3>
MEM_A_DQS_P<4>
MEM_A_DQS_N<4>
MEM_A_DQS_P<5>
MEM_A_DQS_N<5>
MEM_A_DQS_P<6>
MEM_A_DQS_N<6>
MEM_A_DQS_P<7>
MEM_A_DQS_N<7>
MEM_B_CLK_P<5..0>
MEM_B_CLK_N<5..0>
MEM_B_CKE<3..0>
MEM_B_CS_L<3..0>
MEM_B_ODT<3..0>
MEM_B_A<15..0>
MEM_B_BA<2..0>
MEM_B_RAS_L
MEM_B_CAS_L
MEM_B_WE_L
MEM_B_DQ<7..0>
MEM_B_DQ<15..8>
MEM_B_DQ<23..16>
MEM_B_DQ<31..24>
MEM_B_DQ<39..32>
MEM_B_DQ<47..40>
MEM_B_DQ<55..48>
MEM_B_DQ<63..56>
MEM_B_DQS_P<0>
MEM_B_DQS_N<0>
MEM_B_DQS_P<1>
MEM_B_DQS_N<1>
MEM_B_DQS_P<2>
MEM_B_DQS_N<2>
MEM_B_DQS_P<3>
MEM_B_DQS_N<3>
MEM_B_DQS_P<4>
MEM_B_DQS_N<4>
MEM_B_DQS_P<5>
MEM_B_DQS_N<5>
MEM_B_DQS_P<6>
MEM_B_DQS_N<6>
MEM_B_DQS_P<7>
MEM_B_DQS_N<7>
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PAGE TITLE
Memory Constraints
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
SYNC_DATE=02/15/2011SYNC_MASTER=K90I_MLB
DRAWING NUMBER
051-9058
REVISION
6.0.0
BRANCH
PAGE
101 OF 109
SHEET
79 OF 86
124578
SIZE
D
C
B
A
D
8 7 6 5 4 3
Digital Video Signal Constraints
LAYER
DP_85D
LVDS_90D
SPACING_RULE_SET
LAYER
DP_PCH
DP_PCH_TX
LVDS_PCH_TX
D
SATA Interface Constraints
LAYER
SATA_90D
SPACING_RULE_SET
LAYER
SATA_PCH_TX
SATA_PCH_RX
SATA_ICOMP
SPACING_RULE_SET
LAYER
SATA3_PCH_TX2TX
SATA3_PCH_TX2RX
SATA3_PCH_RX2RX
SATA3_PCH_RX2TX
SATA3_PCH_2OTHER
C
NET_SPACING_TYPE1 NET_SPACING_TYPE2
SATA3_PCH_TX
SATA3_PCH_TX
SATA3_PCH_RX
SATA3_PCH_RX
SATA3_PCH_TX
SATA3_PCH_RX SATA3_PCH_2OTHER
SOURCE: 471984_Cheif_River_MS_PDG_1.0 and the spacing rule is adjusted per SI team feedback.
USB 2.0 Interface Constraints
LAYER
PCH_USB_RBIAS
USB_85D
LAYER
B
SPACING_RULE_SET
USB
SOURCE: Calpella Platform Design Guide for Ibex Peak M (DG-398905-398905_v1.5), Section 3.8
USB 3.0 Interface Constraints
LAYER
USB_85D
SPACING_RULE_SET
USB3_PCH_RX2RX =4x_DIELECTRIC
USB3_PCH_2OTHER
NET_SPACING_TYPE1 NET_SPACING_TYPE2
USB3_PCH_TX
A
USB3_PCH_TX
USB3_PCH_RX
USB3_PCH_RX
USB3_PCH_TX
USB3_PCH_RX
SOURCE: 471984_Cheif_River_MS_PDG_1.0 and the spacing rule is adjusted per SI team feedback.
LAYER
ALLOW ROUTE
ON LAYER?
*
=85_OHM_DIFF
=90_OHM_DIFF
*
MINIMUM LINE WIDTH
LINE-TO-LINE SPACING
=3x_DIELECTRIC
*
* ?
*
=3x_DIELECTRIC
=3x_DIELECTRIC
ALLOW ROUTE
ON LAYER?
=90_OHM_DIFF
MINIMUM LINE WIDTH
LINE-TO-LINE SPACING
=3x_DIELECTRIC
*
* ?
=3x_DIELECTRIC
8 MIL
LINE-TO-LINE SPACING
* ?
* ?
* ?
=4X_DIELECTRIC
=5X_DIELECTRIC
=4x_DIELECTRIC
=5x_DIELECTRIC
=4x_DIELECTRIC
AREA_TYPE
*_PCH_TX
*_PCH_RX
*_PCH_RX
*_PCH_TX
*
*
*
*
*
*
SPACING_RULE_SET
SATA3_PCH_TX2TX
SATA3_PCH_TX2RX
SATA3_PCH_RX2RX
SATA3_PCH_RX2TX
SATA3_PCH_2OTHER
* *
ALLOW ROUTE
ON LAYER?
=STANDARD
*
=85_OHM_DIFF
*
MINIMUM LINE WIDTH
8 MIL
=85_OHM_DIFF
LINE-TO-LINE SPACING
* ?
*
=2x_DIELECTRIC
ALLOW ROUTE
ON LAYER?
=85_OHM_DIFF
MINIMUM LINE WIDTH
=85_OHM_DIFF
LINE-TO-LINE SPACING
=4X_DIELECTRICUSB3_PCH_TX2TX
* ?
=5X_DIELECTRICUSB3_PCH_TX2RX
*
=5x_DIELECTRICUSB3_PCH_RX2TX
=4x_DIELECTRIC
AREA_TYPE
*_PCH_TX
*_PCH_RX
*_PCH_RX
*_PCH_TX
* *
* *
*
*
*
*
SPACING_RULE_SET
USB3_PCH_TX2TX
USB3_PCH_TX2RX
USB3_PCH_RX2RX
USB3_PCH_RX2TX
USB3_PCH_2OTHER
USB3_PCH_2OTHER
WEIGHT
WEIGHT
WEIGHT
WEIGHT
WEIGHT
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
?*
TABLE_SPACING_RULE_ITEM
?
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
?*
TABLE_SPACING_RULE_ITEM
?
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
?*
TABLE_SPACING_RULE_ITEM
?*
TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
?*
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
?
TABLE_SPACING_RULE_ITEM
?*
TABLE_SPACING_RULE_ITEM
?*
TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
MINIMUM NECK WIDTH
SPACING_RULE_SET
DP_PCH
DP_PCH_TX
LVDS_PCH_TX
MINIMUM NECK WIDTH
=90_OHM_DIFF=90_OHM_DIFF
SPACING_RULE_SET
SATA_PCH_TX
SATA_PCH_RX
SPACING_RULE_SET
SATA3_PCH_TX2TX
SATA3_PCH_TX2RX
SATA3_PCH_RX2RX
SATA3_PCH_RX2TX
SATA3_PCH_2OTHER?TOP,BOTTOM
MINIMUM NECK WIDTH
8 MIL
=85_OHM_DIFF =85_OHM_DIFF
SPACING_RULE_SET
USB
MINIMUM NECK WIDTH
SPACING_RULE_SET
USB3_PCH_TX2RX =6X_DIELECTRIC
USB3_PCH_2OTHER
MAXIMUM NECK LENGTH
=85_OHM_DIFF=85_OHM_DIFF=85_OHM_DIFF
=90_OHM_DIFF=90_OHM_DIFF=90_OHM_DIFF
LAYER
TOP,BOTTOM
TOP,BOTTOM
TOP,BOTTOM
MAXIMUM NECK LENGTH
=90_OHM_DIFF
LAYER
TOP,BOTTOM
TOP,BOTTOM
LAYER
TOP,BOTTOM
TOP,BOTTOM
TOP,BOTTOM
TOP,BOTTOM
MAXIMUM NECK LENGTH
=STANDARD
LAYER
TOP,BOTTOM
MAXIMUM NECK LENGTH
=85_OHM_DIFF=85_OHM_DIFF
LAYER
TOP,BOTTOM
TOP,BOTTOM
TOP,BOTTOM
TOP,BOTTOM
TOP,BOTTOM
DIFFPAIR PRIMARY GAP
=90_OHM_DIFF
LINE-TO-LINE SPACING
=4x_DIELECTRIC
=4x_DIELECTRIC
=4x_DIELECTRIC
DIFFPAIR PRIMARY GAP
=90_OHM_DIFF
LINE-TO-LINE SPACING
=4x_DIELECTRIC
=4x_DIELECTRIC
LINE-TO-LINE SPACING
=5X_DIELECTRIC
=6X_DIELECTRIC
=5x_DIELECTRIC
=6x_DIELECTRIC
=5x_DIELECTRIC
DIFFPAIR PRIMARY GAP
=STANDARD
=85_OHM_DIFF
LINE-TO-LINE SPACING
=4x_DIELECTRIC
DIFFPAIR PRIMARY GAP
LINE-TO-LINE SPACING
=5X_DIELECTRICUSB3_PCH_TX2TX
=5x_DIELECTRICUSB3_PCH_RX2RX
=6x_DIELECTRICUSB3_PCH_RX2TX
=5x_DIELECTRIC
PCH Net Properties
ELECTRICAL_CONSTRAINT_SET
LVDS_IG_A_CLK
LVDS_IG_A_CLK
LVDS_IG_A_DATA
LVDS_IG_A_DATA
I213
I214
I215
I216
SATA_HDD_R2D
SATA_HDD_R2D
SATA_HDD_R2D_CONN
SATA_HDD_R2D_CONN
SATA_HDD_D2R
SATA_HDD_D2R SATA3_PCH_RX
SATA_HDD_D2R_CONN
SATA_HDD_D2R_CONN
SATA_ODD_R2D
SATA_ODD_R2D
SATA_ODD_R2D
SATA_ODD_R2D
SATA_ODD_D2R
SATA_ODD_D2R
SATA_HDD_R2D_CONN
SATA_HDD_R2D_CONN
SATA_HDD_D2R_CONN
SATA_HDD_D2R_CONN
PCH_SATA_ICOMP
USB_HUB1_UP
USB_EXTA
USB_EXTA
USB_EXTB
I219
I220
I221
I222
I223
I224
I225
I226
I247
I248
I250
I249
USB3_EXT_RX
I228
I227
USB3_EXT_TX
I229
I230
USB3_EXT_RX
I231
I232
USB3_EXT_TX
I234
I233
I235
I236
I238
I237
I240
I239
I241
I242
I244
I243
I246
I245
USB_EXTA
I251
I252
USB_EXTC
USB_CAMERA
USB_CAMERA
USB_BT
USB_BT
USB_BT
I253
USB_BT
I254
USB_TPAD
USB_IR
PCH_USB_RBIAS PCH_USB_RBIAS
PCH_DIFFCLK_UNUSED_
PCH_DIFFCLK_UNUSED_
PCH_DIFFCLK_UNUSED_
PCH_DIFFCLK_UNUSED_
PCH_DIFFCLK_UNUSED_
PCH_DIFFCLK_UNUSED_
LPC_CLK33M
PHYSICAL
LVDS_90D
LVDS_90D
LVDS_90D
LVDS_90D
LVDS_90D
LVDS_90D
LVDS_90D
LVDS_90D
LVDS_90D
LVDS_90D
SATA_90D
SATA_90D
SATA_90D
SATA_90D
SATA_90D
SATA_90D
SATA_90D
SATA_90D
SATA_90D
SATA_90D
SATA_90D
SATA_90D
SATA_90D
SATA_90D
SATA_90D
SATA_90D
SATA_90D
SATA_90D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
CLK_PCIE_90D
CLK_PCIE_90D
CLK_PCIE_90D
CLK_PCIE_90D
CLK_PCIE_90D
CLK_PCIE_90D
CPU_50S
CPU_50S
NET_TYPE
SPACING
LVDS_PCH_TX
LVDS_PCH_TX
LVDS_PCH_TX
LVDS_PCH_TX
LVDS_PCH_TX
LVDS_PCH_TX
LVDS_PCH_TX
LVDS_PCH_TX
LVDS_PCH_TX
LVDS_PCH_TX
SATA3_PCH_TX
SATA3_PCH_TX
SATA3_PCH_TX
SATA3_PCH_TX
SATA3_PCH_RX
SATA3_PCH_RX
SATA3_PCH_RX
SATA_PCH_TX
SATA_PCH_TX
SATA_PCH_TX
SATA_PCH_TX
SATA_PCH_RX
SATA_PCH_RX
SATA3_PCH_TX
SATA3_PCH_TX
SATA3_PCH_RX
SATA3_PCH_RX
SATA_ICOMP
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB3_PCH_RX
USB3_PCH_RX
USB3_PCH_TX
USB3_PCH_TX
USB3_PCH_RX
USB3_PCH_RX
USB3_PCH_TX
USB3_PCH_TX
USB3_PCH_RX
USB3_PCH_RX
USB3_PCH_TX
USB3_PCH_TX
USB3_PCH_RX
USB3_PCH_RX
USB3_PCH_TX
USB3_PCH_TX
USB3_PCH_TX
USB3_PCH_TX
USB3_PCH_TX
USB3_PCH_TX
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
CLK_PCIE
CLK_PCIE
CLK_PCIE
CLK_PCIE
CLK_PCIE
CLK_PCIE
CLK_PCIE
CLK_PCIE
LVDS_IG_A_CLK_P
LVDS_IG_A_CLK_N
LVDS_IG_A_DATA_P<2..0>
LVDS_IG_A_DATA_N<2..0>
LVDS_IG_A_DATA_P<3>
LVDS_IG_A_DATA_N<3>
LVDS_IG_B_DATA_P<3..0>
LVDS_IG_B_DATA_N<3..0>
LVDS_IG_B_CLK_P
LVDS_IG_B_CLK_N
SATA_HDD_R2D_C_P
SATA_HDD_R2D_C_N
SATA_HDD_R2D_P
SATA_HDD_R2D_N
SATA_HDD_D2R_P
SATA_HDD_D2R_N
SATA_HDD_D2R_C_P
SATA_HDD_D2R_C_N
SATA_ODD_R2D_C_P
SATA_ODD_R2D_C_N
SATA_ODD_R2D_P
SATA_ODD_R2D_N
SATA_ODD_D2R_P
SATA_ODD_D2R_N
SATA_HDD_R2D_RC_P
SATA_HDD_R2D_RC_N
SATA_HDD_D2R_RC_P
SATA_HDD_D2R_RC_N
PCH_SATAICOMP
USB_HUB_UP_P
USB_HUB_UP_N
USB_EXTA_P
USB_EXTA_N
USB_EXTB_MUX_P
USB_EXTB_MUX_N
USB_EXTA_MUXED_F_P
USB_EXTA_MUXED_F_N
USB_EXTB_F_P
USB_EXTB_F_N
USB_EXTA_MUXED_P
USB_EXTA_MUXED_N
USB_EXTD_XHCI_P
USB_EXTD_XHCI_N
USB_EXTB_EHCI_P
USB_EXTB_EHCI_N
USB_EXTB_XHCI_P
USB_EXTB_XHCI_N
USB3_EXTA_RX_P
USB3_EXTA_RX_N
USB3_EXTA_TX_P
USB3_EXTA_TX_N
USB3_EXTB_RX_P
USB3_EXTB_RX_N
USB3_EXTB_TX_P
USB3_EXTB_TX_N
USB3_EXTA_RX_F_P
USB3_EXTA_RX_F_N
USB3_EXTA_TX_F_P
USB3_EXTA_TX_F_N
USB3_EXTB_RX_F_P
USB3_EXTB_RX_F_N
USB3_EXTB_TX_F_P
USB3_EXTB_TX_F_N
USB3_EXTA_TX_C_P
USB3_EXTA_TX_C_N
USB3_EXTB_TX_C_P
USB3_EXTB_TX_C_N
USB_SMC_P
USB_SMC_N
USB_EXTC_P
USB_EXTC_N
USB_CAMERA_P
USB_CAMERA_N
USB_CAMERA_CONN_P
USB_CAMERA_CONN_N
USB_BT_P
USB_BT_N
USB_BT_CONN_P
USB_BT_CONN_N
USB_TPAD_P
USB_TPAD_N
USB_IR_P
USB_IR_N
PCH_USB_RBIAS
PCIE_CLK100M_PCH_P
PCIE_CLK100M_PCH_N
PCH_CLK96M_DOT_P
PCH_CLK96M_DOT_N
PCH_CLK100M_SATA_P
PCH_CLK100M_SATA_N
PCH_CLK14P3M_REFCLK
PCH_CLK33M_PCIIN
WEIGHT
WEIGHT
WEIGHT
WEIGHT
WEIGHT
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
?
TABLE_SPACING_RULE_ITEM
?
TABLE_SPACING_RULE_ITEM
?
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
?
TABLE_SPACING_RULE_ITEM
?
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
?
TABLE_SPACING_RULE_ITEM
?
TABLE_SPACING_RULE_ITEM
?
TABLE_SPACING_RULE_ITEM
?
TABLE_SPACING_RULE_ITEM
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
?
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
?
TABLE_SPACING_RULE_ITEM
?
TABLE_SPACING_RULE_ITEM
?
TABLE_SPACING_RULE_ITEM
?
TABLE_SPACING_RULE_ITEM
?
=85_OHM_DIFF=85_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=STANDARD
=85_OHM_DIFF
=85_OHM_DIFF=85_OHM_DIFF
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
6 3
17 74
17 74
6
17 74
6
17 74
8
17
8
17
8
17
8
17
8
17
8
17
16 41
16 41
6
41
6
41
16 41
16 41
6
41
6
41
16 41
16 41
6
41
6
41
16 41
16 41
41
41
41
41
16
18 25
18 25
18 42
18 42
25 43
25 43
42
42
43
43
42
42
8
18
8
18
18 25
18 25
18 25
18 25
18 42
18 42
18 42
18 42
18 43
18 43
18 43
18 43
42
42
42
42
43
43
43
43
42
42
43
43
8
45
8
45
8
18
8
18
18 32
18 32
6
32
6
32
8
32
8
32
6
32
6
32
8
53
8
53
8
44
8
44
18
16
16
16
16
16
16
16
16 24
12
SYNC_MASTER=K90I_MLB SYNC_DATE=02/15/2011
PAGE TITLE
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
PCH Constraints 1
Apple Inc.
R
DRAWING NUMBER
051-9058
REVISION
6.0.0
BRANCH
PAGE
102 OF 109
SHEET
80 OF 86
124578
SIZE
D
C
B
A
D
8 7 6 5 4 3
LPC Bus Constraints
LAYER
LPC_50S
CLK_LPC_50S
SPACING_RULE_SET
LAYER
LPC
CLK_LPC
SOURCE: Calpella Platform Design Guide for Ibex Peak M (DG-398905-398905_v1.5), Section 3.15
D
SMBus Interface Constraints
LAYER
SMB_50S
SPACING_RULE_SET
LAYER
SMB
HD Audio Interface Constraints
LAYER
HDA_50S
SPACING_RULE_SET
LAYER
HDA
SOURCE: Calpella Platform Design Guide for Ibex Peak M (DG-398905-398905_v1.5), Section 3.15
SIO Signal Constraints
LAYER
CLK_SLOW_55S
C
SPACING_RULE_SET
CLK_SLOW
SPI Interface Constraints
SPI_50S
SPACING_RULE_SET
SPI
PCI-Express Signal Constraints
B
SPACING_RULE_SET
PCIE_T29_TX2TX
PCIE_T29_TX2RX
PCIE_T29_RX2RX
PCIE_T29_RX2TX =4x_DIELECTRIC
PCIE_T29_2OTHER
NET_SPACING_TYPE1 NET_SPACING_TYPE2
PCIE_T29_TX
PCIE_T29_TX
PCIE_T29_RX
PCIE_T29_RX
PCIE_T29_TX
PCIE_T29_RX
SOURCE: 471984_Cheif_River_MS_PDG_1.0 and the spacing rule is adjusted per SI team feedback.
A
System Clock Signal Constraints
CLK_SLOW_55S
CLK_25M_55S
SPACING_RULE_SET
CLK_SLOW
LAYER
LAYER
LAYER
LAYER
LAYER
LAYER
ALLOW ROUTE
ON LAYER?
=50_OHM_SE =50_OHM_SE =50_OHM_SE=50_OHM_SE
*
=50_OHM_SE =50_OHM_SE=50_OHM_SE=50_OHM_SE
*
LINE-TO-LINE SPACING
*
* ?
ALLOW ROUTE
ON LAYER?
*
=50_OHM_SE =50_OHM_SE=50_OHM_SE
LINE-TO-LINE SPACING
* ?
ALLOW ROUTE
ON LAYER?
*
=50_OHM_SE =50_OHM_SE =50_OHM_SE
LINE-TO-LINE SPACING
*
ALLOW ROUTE
ON LAYER?
*
LINE-TO-LINE SPACING
*
ALLOW ROUTE
ON LAYER?
*
=50_OHM_SE =50_OHM_SE =50_OHM_SE =50_OHM_SE
LINE-TO-LINE SPACING
*
LINE-TO-LINE SPACING
* ?
* ?
*
* ?
*_TX
*_RX
*_RX
*_TX
* *
* *
ALLOW ROUTE
ON LAYER?
*
*
LINE-TO-LINE SPACING
* ?
6 MIL
8 MIL
=2x_DIELECTRIC
=2x_DIELECTRIC
8 MIL
8 MIL
=3X_DIELECTRIC
=4X_DIELECTRIC
=3x_DIELECTRIC
=3x_DIELECTRIC
AREA_TYPE
*
*
*
*
=2x_DIELECTRIC
=5x_DIELECTRICCLK_25M
MINIMUM LINE WIDTH
MINIMUM LINE WIDTH
WEIGHT
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
?
TABLE_SPACING_RULE_ITEM
MINIMUM NECK WIDTH
MINIMUM NECK WIDTH
=50_OHM_SE
TABLE_SPACING_RULE_HEAD
WEIGHT
TABLE_SPACING_RULE_ITEM
MINIMUM LINE WIDTH
MINIMUM LINE WIDTH
WEIGHT
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
?
MINIMUM NECK WIDTH
MINIMUM NECK WIDTH
=55_OHM_SE=55_OHM_SE =55_OHM_SE
TABLE_SPACING_RULE_HEAD
WEIGHT
TABLE_SPACING_RULE_ITEM
?
MINIMUM LINE WIDTH
SPACING_RULE_SET
PCIE_T29_TX2TX
PCIE_T29_TX2RX
PCIE_T29_RX2RX
PCIE_T29_RX2TX
PCIE_T29_2OTHER
PCIE_T29_2OTHER
MINIMUM LINE WIDTH
WEIGHT
WEIGHT
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
?
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
?*
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
?
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
MINIMUM NECK WIDTH
SPACING_RULE_SET
PCIE_T29_TX2TX =4X_DIELECTRIC
PCIE_T29_TX2RX =5X_DIELECTRIC
PCIE_T29_RX2RX =4x_DIELECTRIC
PCIE_T29_RX2TX =4x_DIELECTRIC
PCIE_T29_2OTHER
MINIMUM NECK WIDTH
=55_OHM_SE =55_OHM_SE=55_OHM_SE =55_OHM_SE
=55_OHM_SE=55_OHM_SE =55_OHM_SE
TABLE_SPACING_RULE_HEAD
WEIGHT
TABLE_SPACING_RULE_ITEM
?*
TABLE_SPACING_RULE_ITEM
=55_OHM_SE
NOTE: 25MHz system clocks very sensitive to noise.
MAXIMUM NECK LENGTH
MAXIMUM NECK LENGTH
MAXIMUM NECK LENGTH
=50_OHM_SE
MAXIMUM NECK LENGTH
=55_OHM_SE
MAXIMUM NECK LENGTH
LAYER
TOP,BOTTOM
TOP,BOTTOM
TOP,BOTTOM
TOP,BOTTOM
TOP,BOTTOM
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR PRIMARY GAP
DIFFPAIR PRIMARY GAP
=STANDARD
DIFFPAIR PRIMARY GAP
=STANDARD
DIFFPAIR PRIMARY GAP
=STANDARD =STANDARD
LINE-TO-LINE SPACING
=4x_DIELECTRIC
DIFFPAIR PRIMARY GAP
=STANDARD =STANDARD
PCH Net Properties
ELECTRICAL_CONSTRAINT_SET
LPC_AD
LPC_FRAME_L
LPC_RESET_L
LPC_CLK33M
LPC_CLK33M
LPC_CLK33M
SMBUS_PCH_CLK
SMBUS_PCH_DATA
SMBUS_PCH_0_CLK
SMBUS_PCH_0_DATA
SMBUS_SMC_B_S0_SCL
SMBUS_SMC_B_S0_SDA
HDA_BIT_CLK
HDA_SYNC
HDA_RST_L
HDA_SDIN0
HDA_SDOUT
PM_SUS_CLK
SPI_MOSI
SPI_MISO
SPI_CS0 SPI_50S
I288
I289
I290
I291
I292
I293
I294
I295
PCIE_ENET_R2D
PCIE_ENET_D2R
PCIE_FW_R2D PCIE_PCH_TX
PCIE_AP_D2R
PCIE_CLK100M_ENET
MCP_PE1_REFCLK
MCP_PE2_REFCLK
I235
I236
I237
I238
I239
I240
I241
I242
I243
I244
I245
I246
I247
I248
I249
I250
PHYSICAL
LPC_50S
LPC_50S
LPC_50S
CLK_LPC_50S
CLK_LPC_50S
CLK_LPC_50S
SMB_50S
SMB_50S
SMB_50S
SMB_50S
SMB_50S
SMB_50S
HDA_50S
HDA_50S
HDA_50S
HDA_50S
HDA_50S
HDA_50S
HDA_50S
HDA_50S
HDA_50S
HDA_50S
CLK_SLOW_55S
SPI_50SSPI_CLK
SPI_50S
SPI_50S
SPI_50S
SPI_50S
SPI_50S
SPI_50S
SPI_50S
SPI_50S
SPI_50S
SPI_50S
SPI_50S
SPI_50S
SPI_50S
PCIE_85D
PCIE_85D
PCIE_85D
PCIE_85D
PCIE_85D
PCIE_85D
PCIE_85D
PCIE_85D
PCIE_85D
PCIE_85D
PCIE_85D
PCIE_85D
PCIE_85D
PCIE_85D
PCIE_85D
PCIE_85D
PCIE_85D
PCIE_85D
PCIE_85D
PCIE_85D
PCIE_85D
PCIE_85D
PCIE_85D
PCIE_85D
PCIE_85D
PCIE_85D
CLK_PCIE_90D
CLK_PCIE_90D
CLK_PCIE_90D
CLK_PCIE_90D
CLK_PCIE_90D
CLK_PCIE_90D
CLK_PCIE_90D
CLK_PCIE_90D
CLK_PCIE_90D
CLK_PCIE_90D
CPU_27P4S
CPU_27P4S
CPU_27P4S
CPU_27P4S
CPU_27P4S
CPU_27P4S
CPU_27P4S
CPU_27P4S
CPU_27P4S
CPU_27P4S
CPU_27P4S
CPU_27P4S
CPU_27P4S
CPU_27P4S
CPU_27P4S
CPU_27P4S
NET_TYPE
SPACING
LPC
LPC
LPC
CLK_LPC
CLK_LPC
CLK_LPC
SMB
SMB
SMB
SMB
SMB
SMB
HDA
HDA
HDA
HDA
HDA
HDA
HDA
HDA
HDA
HDA
CLK_SLOW
SPI
SPI
SPI
SPI
SPI
SPI
SPI
SPI
SPI
SPI
SPI
SPI
SPI
SPI
SPI
PCIE_PCH_TX
PCIE_PCH_TX
PCIE_PCH_TX
PCIE_PCH_TX
PCIE_PCH_RX
PCIE_PCH_RX
PCIE_PCH_RX
PCIE_PCH_RX
PCIE_PCH_TX
PCIE_PCH_TX
PCIE_PCH_TXPCIE_AP_R2D
PCIE_PCH_TX
PCIE_PCH_RXPCIE_AP_D2R
PCIE_PCH_RX
PCIE_PCH_TX
PCIE_PCH_TX
PCIE_PCH_TX
PCIE_PCH_RXPCIE_FW_D2R
PCIE_PCH_RX
PCIE_PCH_RX
PCIE_PCH_RX
PCIE_PCH_RX
PCIE_PCH_RX
PCIE_PCH_RXPCIE_AP_R2D
PCIE_PCH_RX
CLK_PCIE
CLK_PCIE
CLK_PCIE
CLK_PCIE
CLK_PCIE
CLK_PCIE
CLK_PCIE
CLK_PCIE
CLK_PCIE
CLK_PCIE
CPU_COMP
CPU_COMP
CPU_COMP
CPU_COMP
CPU_COMP
CPU_COMP
CPU_COMP
CPU_COMP
CPU_COMP
CPU_COMP
CPU_COMP
CPU_COMP
CPU_COMP
CPU_COMP
CPU_COMP
CPU_COMP
LPC_AD<3..0>
LPC_FRAME_L
LPC_RESET_L
LPC_CLK33M_SMC_R
LPC_CLK33M_SMC
LPC_CLK33M_LPCPLUS
SMBUS_PCH_CLK
SMBUS_PCH_DATA
SML_PCH_0_CLK
SML_PCH_0_DATA
SML_PCH_1_CLK
SML_PCH_1_DATA
HDA_BIT_CLK
HDA_BIT_CLK_R
HDA_SYNC
HDA_SYNC_R
HDA_RST_R_L
HDA_RST_L
HDA_SDIN0
AUD_SDI_R
HDA_SDOUT
HDA_SDOUT_R
PM_CLK32K_SUSCLK
SPI_CLK_R
SPI_CLK
SPI_MOSI_R
SPI_MOSI
SPI_MISO
SPI_CS0_R_L
SPI_CS0_L
SPI_MLB_CLK
SPI_MLB_CS_L
SPI_MLB_MOSI
SPI_MLB_MISO
SPI_SMC_MISO
SPI_SMC_MOSI
SPI_SMC_CLK
SPI_SMC_CS_L
PCIE_ENET_R2D_P
PCIE_ENET_R2D_N
PCIE_ENET_R2D_C_P
PCIE_ENET_R2D_C_N
PCIE_ENET_D2R_P
PCIE_ENET_D2R_N
PCIE_ENET_D2R_C_P
PCIE_ENET_D2R_C_N
PCIE_AP_R2D_P
PCIE_AP_R2D_N
PCIE_AP_R2D_C_P
PCIE_AP_R2D_C_N
PCIE_AP_D2R_P
PCIE_AP_D2R_N
PCIE_FW_R2D_P
PCIE_FW_R2D_N
PCIE_FW_R2D_C_P
PCIE_FW_R2D_C_N
PCIE_FW_D2R_P
PCIE_FW_D2R_N
PCIE_FW_D2R_C_P
PCIE_FW_D2R_C_N
PCIE_AP_D2R_PI_P
PCIE_AP_D2R_PI_N
PCIE_AP_R2D_PI_P
PCIE_AP_R2D_PI_N
PEG_CLK100M_P
PEG_CLK100M_N
PCIE_CLK100M_ENET_P
PCIE_CLK100M_ENET_N
PCIE_CLK100M_AP_P
PCIE_CLK100M_AP_N
PCIE_CLK100M_FW_P
PCIE_CLK100M_FW_N
PCIE_CLK100M_EXCARD_P
PCIE_CLK100M_EXCARD_N
PCH_VSS_NCTF<1>
PCH_VSS_NCTF<2>
PCH_VSS_NCTF<5>
TP_PCH_VSS_NCTF<7>
PCH_VSS_NCTF<9>
PCH_VSS_NCTF<9>
PCH_VSS_NCTF<11>
PCH_VSS_NCTF<12>
PCH_VSS_NCTF<15>
PCH_VSS_NCTF<17>
PCH_VSS_NCTF<19>
PCH_VSS_NCTF<21>
PCH_VSS_NCTF<22>
PCH_VSS_NCTF<25>
PCH_VSS_NCTF<27>
PCH_VSS_NCTF<29>
6
16 45 47
6
16 45 47
24
18 24
24 45
6
24 47
16 48
16 48
16 48
16 48
16 48
16 48
16 57
16
16 57
16
16
16 57
16 57
57
16 57
16 24
16 47
47
16 47
47
16 47
16 47
47
46 47 56
46 47 56
46 47 56
46 47 56
45 46
45 46
45 46
45 46
36
36
16 36
16 36
16 36
16 36
36
36
6
32
6
32
16 32
16 32
16 32
16 32
38
38
16 38
16 38
16 38
16 38
38
38
6
32
6
32
8
16
8
16
16 36
16 36
16 32
16 32
16 38
16 38
8
16
8
16
6
6
6
6
81
6
81
6
6
6
6
6
6
6
6
6
WEIGHT
=STANDARD=STANDARD
=STANDARD=STANDARD
=STANDARD=STANDARD
=STANDARD
=STANDARD
=STANDARD=STANDARD
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
?
TABLE_SPACING_RULE_ITEM
?
TABLE_SPACING_RULE_ITEM
?
TABLE_SPACING_RULE_ITEM
?
TABLE_SPACING_RULE_ITEM
?
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
6 3
Chipset Net Properties
ELECTRICAL_CONSTRAINT_SET
DP_EXTA_ML
I252
DP_EXTA_ML
I251
I253
I255
DP_EXTA_AUXCH
I254
DP_EXTA_AUXCH
I256
I257
I258
PCIE_T29_R2D
I271
PCIE_T29_R2D
I273
PCIE_T29_R2D
I272
PCIE_T29_R2D
I274
PCIE_T29_D2R
I276
PCIE_T29_D2R
I275
PCIE_T29_D2R
I277
PCIE_T29_D2R
I278
I279
I280
PHYSICAL
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
PCIE_85D
PCIE_85D
PCIE_85D
PCIE_85D
PCIE_85D
PCIE_85D
PCIE_85D
PCIE_85D
CLK_PCIE_90D
CLK_PCIE_90D
Clock Net Properties
ELECTRICAL_CONSTRAINT_SET
SYSCLK_CLK32K_RTC
I281
SYSCLK_CLK25M_SB
I282
I283
I284
I285
SYSCLK_CLK25M_T29
I286
I287
PHYSICAL
CLK_SLOW_55S
CLK_25M_55S
CLK_25M_55S
CLK_25M_55S
CLK_25M_55S
CLK_25M_55S
CLK_25M_55S
SYNC_MASTER=K90I_MLB
PAGE TITLE
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
NET_TYPE
SPACING
DP_PCH_TX
DP_PCH_TX
DP_PCH_TX
DP_PCH_TX
DP_PCH
DP_PCH
DP_PCH
DP_PCHDP_85D
PCIE_T29_RX
PCIE_T29_RX
PCIE_T29_RX
PCIE_T29_RX
PCIE_T29_TX
PCIE_T29_TX
PCIE_T29_TX
PCIE_T29_TX
CLK_PCIEPCIE_CLK100M_T29
CLK_PCIEPCIE_CLK100M_T29
NET_TYPE
SPACING
CLK_SLOW
CLK_25M
CLK_25M
CLK_25M
CLK_25M
CLK_25M
CLK_25M
PCH Constraints 2
Apple Inc.
R
12
DP_EXTA_ML_C_P<3..0>
DP_EXTA_ML_C_N<3..0>
DP_EXTA_ML_P<3..0>
DP_EXTA_ML_N<3..0>
DP_EXTA_AUXCH_C_P
DP_EXTA_AUXCH_C_N
DP_EXTA_AUXCH_P
DP_EXTA_AUXCH_N
PCIE_T29_R2D_C_P<3..0>
PCIE_T29_R2D_C_N<3..0>
PCIE_T29_R2D_P<3..0>
PCIE_T29_R2D_N<3..0>
PCIE_T29_D2R_P<3..0>
PCIE_T29_D2R_N<3..0>
PCIE_T29_D2R_C_P<3..0>
PCIE_T29_D2R_C_N<3..0>
PCIE_CLK100M_T29_P
PCIE_CLK100M_T29_N
SYSCLK_CLK32K_RTC
SYSCLK_CLK25M_SB
SYSCLK_CLK25M_SB_R
SYSCLK_CLK25M_ENET
SYSCLK_CLK25M_ENET_R
SYSCLK_CLK25M_T29
SYSCLK_CLK25M_T29_R
DRAWING NUMBER
REVISION
BRANCH
PAGE
SHEET
SYNC_DATE=02/15/2011
051-9058
6.0.0
103 OF 109
81 OF 86
124578
8
8
75
75
8
8
75
75
8
8
33
33
8
8
33
33
16 33
16 33
16 24
16 24
16
24 36
24 33
33
75
75
75
75
D
33
33
33
33
C
B
A
SIZE
D
8 7 6 5 4 3
12
CAESAR IV (Ethernet) Constraints
LAYER
ENET_50S
SPACING_RULE_SET
ENET_3X
LAYER
SOURCE: Broadcom 5764-DS04-RDS Page 38
D
SPACING_RULE_SET
ENET_CR_DATA
LAYER
ALLOW ROUTE
ON LAYER?
*
=50_OHM_SE
LINE-TO-LINE SPACING
* ?
LINE-TO-LINE SPACING
MINIMUM LINE WIDTH
=3:1_SPACING
8MIL
CAESAR IV (Ethernet PHY) Constraints
ENET_100D
SPACING_RULE_SET
ENET_MDI
LAYER
LAYER
*
ALLOW ROUTE
ON LAYER?
=100_OHM_DIFF
LINE-TO-LINE SPACING
SOURCE: Broadcom 5764-DS04-RDS Page 38
C
FireWire Interface Constraints
LAYER
FW_110D
SPACING_RULE_SET
FW_TP
LAYER
*
*
ALLOW ROUTE
ON LAYER?
=110_OHM_DIFF
LINE-TO-LINE SPACING
MINIMUM LINE WIDTH
=100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF
0.6 MM
MINIMUM LINE WIDTH
=110_OHM_DIFF =110_OHM_DIFF
=3:1_SPACING
WEIGHT
WEIGHT
WEIGHT
WEIGHT
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
?*
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
?*
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
?
MINIMUM NECK WIDTH
=50_OHM_SE=50_OHM_SE
MINIMUM NECK WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
=50_OHM_SE
MAXIMUM NECK LENGTH
MAXIMUM NECK LENGTH
=110_OHM_DIFF
DIFFPAIR PRIMARY GAP
DIFFPAIR PRIMARY GAP
DIFFPAIR PRIMARY GAP
=110_OHM_DIFF =110_OHM_DIFF
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
=STANDARD=STANDARD
TABLE_PHYSICAL_RULE_HEAD
=100_OHM_DIFF=100_OHM_DIFF
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
Ethernet Net Properties
ELECTRICAL_CONSTRAINT_SET
ENET_MDI
CR_DATA
I166
CR_DATA
I167
CR_CLK
I168
CR_DATA
I169
CR_DATA
I170
CR_CLK
I171
CR_CLK
I172
PHYSICAL
ENET_50S
ENET_50S
ENET_50S
ENET_100D
ENET_100D
ENET_50S
ENET_50S
ENET_50S
ENET_50S
ENET_50S
ENET_50S
ENET_50S
FireWire Net Properties
ELECTRICAL_CONSTRAINT_SET
FW_P0_TPA
I158
FW_P0_TPA
I159
FW_P0_TPB
I160
FW_P0_TPB
I161
FW_P1_TPA
I162
FW_P1_TPA
I163
FW_P1_TPB
I164
FW_P1_TPB
I165
FW_110D
FW_110D
FW_110D
FW_110D
FW_110D
FW_110D
FW_110D
FW_110D
PHYSICAL
NET_TYPE
NET_TYPE
SPACING
ENET_3X
ENET_3X
ENET_3X
ENET_MDI
ENET_MDI
ENET_CR_DATA
ENET_CR_DATA
ENET_CR_DATA
ENET_CR_DATA
ENET_CR_DATA
ENET_CR_DATA
ENET_CR_DATA
SPACING
FW_TP
FW_TP
FW_TP
FW_TP
FW_TP
FW_TP
FW_TP
FW_TP
BCM5764_CLK25M_XTALI
BCM5764_CLK25M_XTALO
ENET_RESET_L
ENET_MDI_P<3..0>
ENET_MDI_N<3..0>
ENET_CR_DATA<7..0>
ENET_CR_CMD
ENET_CR_CLK
SDCONN_DATA<7..0>
SDCONN_CMD
SDCONN_CLK
SDCONN_CLK_L
FW_P0_TPA_P
FW_P0_TPA_N
FW_P0_TPB_P
FW_P0_TPB_N
FW_P1_TPA_P
FW_P1_TPA_N
FW_P1_TPB_P
FW_P1_TPB_N
30 36
36 37
36 37
30 36
30 36
30 36
38 40
38 40
38 40
38 40
38 40
38 40
38 40
38 40
D
C
Port 2 Not Used
SIZE
B
A
D
B
A
6 3
SYNC_MASTER=K90I_MLB SYNC_DATE=02/15/2011
PAGE TITLE
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
Ethernet/FW Constraints
Apple Inc.
R
DRAWING NUMBER
051-9058
REVISION
BRANCH
PAGE
104 OF 109
SHEET
6.0.0
82 OF 86
124578
8 7 6 5 4 3
DisplayPort Signal Constraints
NOTE: DisplayPort Physical/Spacing Constraints provided by Chipset or GPU page.
T29 I2C Signal Constraints
LAYER
ALLOW ROUTE
ON LAYER?
T29_I2C_55S
SPACING_RULE_SET
LAYER
T29_I2C
D
T29 SPI Signal Constraints
LAYER
T29_SPI_55S
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
=2x_DIELECTRIC
*
ALLOW ROUTE
ON LAYER?
=55_OHM_SE =55_OHM_SE=55_OHM_SE
LINE-TO-LINE SPACING
*
=2x_DIELECTRICT29_SPI
MINIMUM LINE WIDTH
=55_OHM_SE =55_OHM_SE=55_OHM_SE=55_OHM_SE
WEIGHT
?
MINIMUM LINE WIDTH
WEIGHT
?
MINIMUM NECK WIDTH
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
MINIMUM NECK WIDTH
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
T29/DP Connector Signal Constraints
T29DP_80D
T29DP_100D
SPACING_RULE_SET
T29DP
LAYER
LAYER
*
*
*
ALLOW ROUTE
ON LAYER?
=80_OHM_DIFF
=100_OHM_DIFF
LINE-TO-LINE SPACING
=5x_DIELECTRIC
SOURCE: Bill Cornelius’s T29 Routing Notes
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
=100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF
TABLE_SPACING_RULE_HEAD
WEIGHT
?
TABLE_SPACING_RULE_ITEM
SPACING_RULE_SET
T29DP
C
B
T29 IC Net Properties
ELECTRICAL_CONSTRAINT_SET
I62
I61
DP_T29SNK0_ML
I63
DP_T29SNK0_ML
I64
I65
I66
DP_T29SNK0_AUXCH
I67
DP_T29SNK0_AUXCH
I68
I69
I70
DP_T29SNK1_ML
I71
DP_T29SNK1_ML
I72
I74
I73
DP_T29SNK1_AUXCH
I75
DP_T29SNK1_AUXCH
I76
I77
I78
I79
I80
I81
A
I82
T29_SPI_CLK
I83
T29_SPI_MOSI
I84
T29_SPI_MISO
I85
T29_SPI_CS_L
I86
I87
I88
I89
I90
NET_TYPE
PHYSICAL
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D DP_PCH
DP_85D DP_PCH
DP_85D DP_PCH
DP_85D DP_PCH
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D DP_PCH
DP_85D DP_PCH
DP_85D DP_PCH
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
T29_I2C_55S
T29_I2C_55S
T29_SPI_55S
T29_SPI_55S
T29_SPI_55S
T29_SPI_55S
T29DP_80D
T29DP_80D
T29DP_100D
T29DP_100D
SPACING
DP_PCH_TX
DP_PCH_TX
DP_PCH_TX
DP_PCH_TX
DP_PCH_TX
DP_PCH_TX
DP_PCH_TX
DP_PCH_TX
DP_PCH
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
T29_I2C
T29_I2C
T29_SPI
T29_SPI
T29_SPI
T29_SPI
T29DP
T29DP
T29DP
T29DP
DP_T29SNK0_ML_C_P<3..0>
DP_T29SNK0_ML_C_N<3..0>
DP_T29SNK0_ML_P<3..0>
DP_T29SNK0_ML_N<3..0>
DP_T29SNK0_AUXCH_C_P
DP_T29SNK0_AUXCH_C_N
DP_T29SNK0_AUXCH_P
DP_T29SNK0_AUXCH_N
DP_T29SNK1_ML_C_P<3..0>
DP_T29SNK1_ML_C_N<3..0>
DP_T29SNK1_ML_P<3..0>
DP_T29SNK1_ML_N<3..0>
DP_T29SNK1_AUXCH_C_P
DP_T29SNK1_AUXCH_C_N
DP_T29SNK1_AUXCH_P
DP_T29SNK1_AUXCH_N
DP_T29SRC_ML_C_P<3..0>
DP_T29SRC_ML_C_N<3..0>
DP_T29SRC_AUXCH_C_P
DP_T29SRC_AUXCH_C_N
I2C_T29_SCL
I2C_T29_SDA
T29_SPI_CLK
T29_SPI_MOSI
T29_SPI_MISO
T29_SPI_CS_L
T29_R2D_C_P<3..0>
T29_R2D_C_N<3..0>
T29_D2R_P<3..0>
T29_D2R_N<3..0>
MAXIMUM NECK LENGTH
MAXIMUM NECK LENGTH
=55_OHM_SE
MAXIMUM NECK LENGTH
=80_OHM_DIFF=80_OHM_DIFF=80_OHM_DIFF
LAYER
TOP,BOTTOM
8
33
8
33
33
33
8
33
8
33
33
33
8
33
8
33
33
33
8
33
8
33
33
33
33 48
33 48
33
33
33
33
8
33 75
8
33 75
8
33 75
8
33 75
=STANDARD
=STANDARD
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
DIFFPAIR PRIMARY GAP
=STANDARD*
DIFFPAIR PRIMARY GAP
=STANDARD*
DIFFPAIR PRIMARY GAP
=100_OHM_DIFF =100_OHM_DIFF
LINE-TO-LINE SPACING
WEIGHT
=7x_DIELECTRIC
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
=80_OHM_DIFF=80_OHM_DIFF
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
?
Only used on hosts supporting T29 video-in
6 3
T29/DP Net Properties
ELECTRICAL_CONSTRAINT_SET
T29_R2D0
I1
T29_R2D0
I2
T29_R2D1
I3
T29_R2D1
I4
I5
I7
T29_D2R0
I6
T29_D2R0
I8
T29_D2R1
I9
T29_D2R1
I10
I11
I12
I13
I15
I14
I17
DP_SDRVA_ML_EVEN
I16
DP_SDRVA_ML_EVEN
I18
DP_SDRVA_ML_ODD
I19
DP_SDRVA_ML_ODD
I20
DP_SDRVA_AUXCH
I21
DP_SDRVA_AUXCH
I22
I23
I24
I25
I26
I27
I28
I30
I29
T29_R2D2
I31
T29_R2D2
I32
T29_R2D3
I34
T29_R2D3
I33
I35
I36
T29_D2R2
I37
T29_D2R2
I39
T29_D2R3
I38
T29_D2R3
I40
I41
I42
I43
I44
I46
I45
DP_SDRVB_ML_EVEN
I47
DP_SDRVB_ML_EVEN
I48
DP_SDRVB_ML_ODD
I49
DP_SDRVB_ML_ODD
I50
DP_SDRVB_AUXCH
I51
DP_SDRVB_AUXCH
I52
I53
I54
I55
I56
I57
I58
I59
I60
PHYSICAL
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_100D
T29DP_100D
T29DP_100D
T29DP_100D
T29DP_100D
T29DP_100D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_100D
T29DP_100D
T29DP_100D
T29DP_100D
T29DP_100D
T29DP_100D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
NET_TYPE
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
SPACING
T29_R2D_P<0>
T29_R2D_N<0>
T29_R2D_P<1>
T29_R2D_N<1>
T29_R2D_C_F_P<1..0>
T29_R2D_C_F_N<1..0>
T29_D2R_C_P<0>
T29_D2R_C_N<0>
T29_D2R_C_P<1>
T29_D2R_C_N<1>
T29DPA_D2R1_AUXCH_P
T29DPA_D2R1_AUXCH_N
DP_SDRVA_ML_C_P<3..0>
DP_SDRVA_ML_C_N<3..0>
DP_SDRVA_ML_R_P<3..0>
DP_SDRVA_ML_R_N<3..0>
DP_SDRVA_ML_P<2..0:2>
DP_SDRVA_ML_N<2..0:2>
DP_SDRVA_ML_P<3..1:2>
DP_SDRVA_ML_N<3..1:2>
DP_SDRVA_AUXCH_P
DP_SDRVA_AUXCH_N
DP_SDRVA_AUXCH_C_P
DP_SDRVA_AUXCH_C_N
T29DPA_ML_P<3..0>
T29DPA_ML_N<3..0>
T29DPA_ML_C_P<3..0>
T29DPA_ML_C_N<3..0>
DP_A_EXT_AUXCH_P
DP_A_EXT_AUXCH_N
T29_R2D_P<2>
T29_R2D_N<2>
T29_R2D_P<3>
T29_R2D_N<3>
T29_R2D_C_F_P<3..2>
T29_R2D_C_F_N<3..2>
T29_D2R_C_P<2>
T29_D2R_C_N<2>
T29_D2R_C_P<3>
T29_D2R_C_N<3>
T29DPB_D2R3_AUXCH_P
T29DPB_D2R3_AUXCH_N
DP_SDRVB_ML_C_P<3..0>
DP_SDRVB_ML_C_N<3..0>
DP_SDRVB_ML_R_P<3..0>
DP_SDRVB_ML_R_N<3..0>
DP_SDRVB_ML_P<2..0:2>
DP_SDRVB_ML_N<2..0:2>
DP_SDRVB_ML_P<3..1:2>
DP_SDRVB_ML_N<3..1:2>
DP_SDRVB_AUXCH_P
DP_SDRVB_AUXCH_N
DP_SDRVB_AUXCH_C_P
DP_SDRVB_AUXCH_C_N
T29DPB_ML_P<3..0>
T29DPB_ML_N<3..0>
T29DPB_ML_C_P<3..0>
T29DPB_ML_C_N<3..0>
DP_B_EXT_AUXCH_P
DP_B_EXT_AUXCH_N
75
75
75
75
75 76
75 76
75 76
75 76
76
76
75
75
75
75
75 83
75 83
75
75
75
75
75
75
75 76
75 76
75 76
75 76
75 76
75 76
Only used on dual-port hosts.
83
83
SYNC_MASTER=K90I_MLB
PAGE TITLE
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
T29 Constraints
Apple Inc.
R
12
SYNC_DATE=02/15/2011
DRAWING NUMBER
051-9058
REVISION
6.0.0
BRANCH
PAGE
105 OF 109
SHEET
83 OF 86
124578
SIZE
D
C
B
A
D
8 7 6 5 4 3
12
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
1TO1_DIFFPAIR
LAYER
ALLOW ROUTE
ON LAYER?
*
MINIMUM LINE WIDTH
=STANDARD=STANDARD
MINIMUM NECK WIDTH
=STANDARD =STANDARD
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
0.1 MM 0.1 MM
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
D
C
SMC SMBus Net Properties
ELECTRICAL_CONSTRAINT_SET
SMBUS_SMC_A_S3_SCL
SMBUS_SMC_A_S3_SDA
SMBUS_SMC_B_S0_SCL
SMBUS_SMC_B_S0_SDA
SMBUS_SMC_0_S0_SCL
SMBUS_SMC_0_S0_SDA
SMBUS_SMC_BSA_SCL
SMBUS_SMC_BSA_SDA
SMBUS_SMC_MGMT_SCL
SMBUS_SMC_MGMT_SDA
SMB_50S
SMB_50S
SMB_50S
SMB_50S
SMB_50S
SMB_50S
SMB_50S
SMB_50S
SMB_50S
SMB_50S
SMBus Charger Net Properties
ELECTRICAL_CONSTRAINT_SET
CHGR_CSI
CHGR_CSO
1TO1_DIFFPAIR
1TO1_DIFFPAIR
1TO1_DIFFPAIR
1TO1_DIFFPAIR
PHYSICAL
PHYSICAL
NET_TYPE
NET_TYPE
SMB
SMB
SMB
SMB
SMB
SMB
SMB
SMB
SMB
SMB
SPACING
SPACING
SMBUS_SMC_2_S3_SCL
SMBUS_SMC_2_S3_SDA
SMBUS_SMC_1_S0_SCL
SMBUS_SMC_1_S0_SDA
SMBUS_SMC_0_S0_SCL
SMBUS_SMC_0_S0_SDA
SMBUS_SMC_5_G3_SCL
SMBUS_SMC_5_G3_SDA
SMBUS_SMC_3_SCL
SMBUS_SMC_3_SDA
CHGR_CSI_P
CHGR_CSI_N
CHGR_CSO_P
CHGR_CSO_N
6
45 48
6
45 48
45 48
45 48
45 48
45 48
6
45 48
6
45 48
45 48
45 48
64
64
64
64
D
C
SIZE
B
A
D
B
A
6 3
SYNC_MASTER=K90I_MLB SYNC_DATE=02/15/2011
PAGE TITLE
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
SMC Constraints
Apple Inc.
R
DRAWING NUMBER
051-9058
REVISION
6.0.0
BRANCH
PAGE
106 OF 109
SHEET
84 OF 86
124578
8 7 6 5 4 3
12
SENSE_1TO1_55S
THERM_1TO1_55S
DIFFPAIR
SPACING_RULE_SET
D
SENSE
THERM
AUDIO
SPACING_RULE_SET
ENETCONN
SPACING_RULE_SET
GND
SPACING_RULE_SET
GND_P2MM
PWR_P2MM
NET_SPACING_TYPE1 NET_SPACING_TYPE2
MEM_CLK
MEM_CMD
C
B
MEM_CTRL
MEM_DATA
MEM_DQS
MEM_40S
OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE
MEM_72D 0.09 MM 400 MIL
OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE
MEM_37S 400 MIL0.09 MM
OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE
OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE
PCIE_85D 0.076 MM
OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE
USB_85D 500 MIL
OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE
CPU_27P4S TOP
OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE
CLK_PCIE_90D
OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE
LAYER
LAYER
LAYER
LAYER
LAYER
LAYER
TOP
TOP
*
*
*
*
*
*
*
*
*
*
GND
GND
GND
GND
GND
*
*
*
*
*
ALLOW ROUTE
ON LAYER?
=1:1_DIFFPAIR
=1:1_DIFFPAIR
MINIMUM LINE WIDTH
LINE-TO-LINE SPACING
=2:1_SPACING
=2:1_SPACING
=2:1_SPACING
LINE-TO-LINE SPACING
25 MILS
LINE-TO-LINE SPACING
=STANDARD
LINE-TO-LINE SPACING
0.20 MM
0.20 MM
AREA_TYPE
*
*
*
*
*
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
=55_OHM_SE
=55_OHM_SE =55_OHM_SE
TABLE_SPACING_RULE_HEAD
WEIGHT
TABLE_SPACING_RULE_ITEM
?
TABLE_SPACING_RULE_ITEM
?
TABLE_SPACING_RULE_ITEM
?
TABLE_SPACING_RULE_HEAD
WEIGHT
TABLE_SPACING_RULE_ITEM
?
TABLE_SPACING_RULE_HEAD
WEIGHT
TABLE_SPACING_RULE_ITEM
?
TABLE_SPACING_RULE_HEAD
WEIGHT
TABLE_SPACING_RULE_ITEM
1000
TABLE_SPACING_RULE_ITEM
1000
SPACING_RULE_SET
GND_P2MM
GND_P2MM
GND_P2MM
GND_P2MM
GND_P2MM
=55_OHM_SE
TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
MINIMUM NECK WIDTH
0.09 MM 400 MIL
0.09 MM
0.1 MM
0.09 MM
0.09 MM
MAXIMUM NECK LENGTH
=55_OHM_SE
=55_OHM_SE
=1:1_DIFFPAIR=1:1_DIFFPAIR
DIFFPAIR PRIMARY GAP
NET_SPACING_TYPE1 NET_SPACING_TYPE2
CPU_COMP
CPU_VCCSENSE
GND
GND
NET_SPACING_TYPE1 NET_SPACING_TYPE2
ENET_MDI
GND
NET_SPACING_TYPE1 NET_SPACING_TYPE2
GND
GND
GND
GND
CLK_PCIE
PCIE*
SATA*
USB*
CLK_PCIESB_POWER PWR_P2MM
SATA*
SATA*
NET_SPACING_TYPE1 NET_SPACING_TYPE2
GND
MAXIMUM NECK LENGTH
LVDS*
DIFFPAIR PRIMARY GAP
400 MILMEM_85D
10 mm
400 MIL
400 MIL
=1:1_DIFFPAIR
=1:1_DIFFPAIR
=1:1_DIFFPAIR
AREA_TYPE
AREA_TYPE
AREA_TYPE
AREA_TYPE
*
*
*
*
*
*
*
*
*
*
*
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
=1:1_DIFFPAIR
=1:1_DIFFPAIR
=1:1_DIFFPAIR
GND_P2MM
GND_P2MM
GND_P2MM
GND_P2MM
GND_P2MM
GND_P2MM
GND_P2MM
PWR_P2MMSB_POWER
PWR_P2MMSB_POWER
GND_P2MM
TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
SPACING_RULE_SET
SPACING_RULE_SET
SPACING_RULE_SET
SPACING_RULE_SET
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
J30 Specific Net Properties J30 Specific Net Properties
ELECTRICAL_CONSTRAINT_SET
I295
I298
I297
I296
SENSE_DIFFPAIR THERM_1TO1_55S
I287
I288
SENSE_DIFFPAIR THERM_1TO1_55S
SENSE_DIFFPAIR THERM_1TO1_55S
SENSE_DIFFPAIR SENSE_1TO1_55S
SENSE_DIFFPAIR SENSE_1TO1_55S
SENSE_DIFFPAIR
SENSE_DIFFPAIR SENSE_1TO1_55S
SENSE_DIFFPAIR SENSE_1TO1_55S
I317
I318
SENSE_DIFFPAIR SENSE_1TO1_55S
SENSE_DIFFPAIR
I322
I321
SENSE_DIFFPAIR
I249
I250
SENSE_DIFFPAIR
I252
I251
SENSE_DIFFPAIR SENSE_1TO1_55S
I253
I254
SENSE_DIFFPAIR SENSE_1TO1_55S
I256
I255
I281
I282
SENSE_DIFFPAIR
I283
I284
SENSE_DIFFPAIR
I292
I291
SENSE_DIFFPAIR
I319
I320
I293
I294
PHYSICAL
ENET_100D
ENET_100D
SATA_90D
SATA_90D
SATA_90D
SATA_90D
SATA_90D
SATA_90D
SATA_90D
SATA_90D
SATA_90D
SATA_90D
THERM_1TO1_55S
THERM_1TO1_55SSENSE_DIFFPAIR
THERM_1TO1_55S
THERM_1TO1_55S
THERM_1TO1_55S
SENSE_1TO1_55S
SENSE_1TO1_55SSENSE_DIFFPAIR
SENSE_1TO1_55S
SENSE_1TO1_55S
SENSE_1TO1_55S
SENSE_1TO1_55S
SENSE_1TO1_55S
SENSE_1TO1_55SSENSE_DIFFPAIR
SENSE_1TO1_55S
SENSE_1TO1_55S
SENSE_1TO1_55SSENSE_DIFFPAIR
SENSE_1TO1_55S
SENSE_1TO1_55S
SENSE_1TO1_55S
SENSE_1TO1_55S
SENSE_1TO1_55S
SENSE_1TO1_55S
SENSE_1TO1_55SSENSE_DIFFPAIR
SENSE_1TO1_55S
SENSE_1TO1_55S
SENSE_1TO1_55S
SENSE_1TO1_55S
SENSE_1TO1_55S
SENSE_1TO1_55SSENSE_DIFFPAIR
SENSE_1TO1_55S
SENSE_1TO1_55S
SENSE_1TO1_55S
SENSE_1TO1_55S
SENSE_1TO1_55S
SENSE_1TO1_55S
SENSE_1TO1_55S
LVDS_90D
LVDS_90D
NET_TYPE
SPACING SPACING
ENETCONN
ENETCONN
SATA_PCH_RX
SATA_PCH_RX
SATA3_PCH_RX
SATA3_PCH_RX
SATA3_PCH_TX
SATA3_PCH_TX
SATA3_PCH_TX
SATA3_PCH_TX
SATA3_PCH_TX
SATA3_PCH_TX
THERM
THERM
THERM
THERM
THERM
THERM
THERM
THERM
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
LVDS_PCH_TX
LVDS_PCH_TX
ENETCONN_P<3..0>
ENETCONN_N<3..0>
SATA_ODD_D2R_C_P
SATA_ODD_D2R_C_N
SATA_HDD_D2R_RDROUT_P
SATA_HDD_D2R_RDROUT_N
SATA_HDD_R2D_RDRIN_P
SATA_HDD_R2D_RDRIN_N
SATA_HDD_D2R_RDRIN_P
SATA_HDD_D2R_RDRIN_N
SATA_HDD_R2D_RDROUT_P
SATA_HDD_R2D_RDROUT_N
THMSNS_D1_P
THMSNS_D1_N
THMSNS_D2_P
THMSNS_D2_N
T29_THERMD_P
T29_THERMD_N
T29THMSNS_D2_P
T29THMSNS_D2_N
ISNS_HS_COMPUTING_N
ISNS_HS_COMPUTING_P
ISNS_HS_OTHER_N
ISNS_HS_OTHER_P
CPUVCCIOS0_CS_N
CPUVCCIOS0_CS_P
CPUIMVP_ISNS1_P
CPUIMVP_ISNS1_N
CPUIMVP_ISNS2_P
CPUIMVP_ISNS2_N
CPUIMVP_ISNS1G_P
CPUIMVP_ISNS1G_N
CPUIMVP_ISNS2G_P
CPUIMVP_ISNS2G_N
CPUIMVP_ISUM_R_P
CPUIMVP_ISUM_R_N
CPUIMVP_ISUMG_R_P
CPUIMVP_ISUMG_R_N
CPUIMVP_ISNSG_P
CPUIMVP_ISNSG_N
CPUIMVP_ISNS_P
CPUIMVP_ISNS_N
VCCSAS0_CS_P
VCCSAS0_CS_N
CPUIMVP_ISUMG_P
CPUIMVP_ISUMG_N
CPU_THERMD_P
CPU_THERMD_N
ISNS_5V_S0_HDD_N
ISNS_5V_S0_HDD_P
ISNS_5V_S0_HDD_R_N
ISNS_5V_S0_HDD_R_P
ISNS_LCDBKLT_N
ISNS_LCDBKLT_P
ISNS_1V5_S3_DDR_P
ISNS_1V5_S3_DDR_N
ISNS_1V5_S3_DDR_R_P
ISNS_1V5_S3_DDR_R_N
LVDS_CONN_A_CLK_F_N
LVDS_CONN_A_CLK_F_P
37
37
6
41
6
41
41
41
41
41
41
41
41
41
51
51
51
51
51
51
50
50
50
50
49 70
49 70
49 68 69
49 69
49 68 69
49 69
49 69
49 69
49 69
49 69
49
49
49
49
49
49
49
49
65
65
68 69
8 9
8 9
49
49
49
49
49
49
49
49
6
74
6
74
ELECTRICAL_CONSTRAINT_SET
PCIE_CLK100M_AP
SPK_OUT
SPK_OUT
SPK_OUT
SPK_OUT
SPK_OUT
SPK_OUT
AUD_DIFF
I299
AUD_DIFF
I300
AUD_DIFF
I302
AUD_DIFF
I301
AUD_DIFF
I304
AUD_DIFF
I303
AUD_DIFF
I305
AUD_DIFF
I307
AUD_DIFF
I306
AUD_DIFF
I310
AUD_DIFF
I308
AUD_DIFF
I309
AUD_DIFF
I311
AUD_DIFF
I312
AUD_DIFF
I313
AUD_DIFF
I314
AUD_DIFF
I315
AUD_DIFF
I316
PHYSICAL
CLK_PCIE_90D
CLK_PCIE_90D
1TO1_DIFFPAIR
1TO1_DIFFPAIR
1TO1_DIFFPAIR
1TO1_DIFFPAIR
DIFFPAIR
DIFFPAIR
DIFFPAIR
DIFFPAIR
DIFFPAIR
DIFFPAIR
1TO1_DIFFPAIR
1TO1_DIFFPAIR
1TO1_DIFFPAIR
1TO1_DIFFPAIR
1TO1_DIFFPAIR
1TO1_DIFFPAIR
1TO1_DIFFPAIR
1TO1_DIFFPAIR
1TO1_DIFFPAIR
1TO1_DIFFPAIR
1TO1_DIFFPAIR
1TO1_DIFFPAIR
1TO1_DIFFPAIR
1TO1_DIFFPAIR
1TO1_DIFFPAIR
1TO1_DIFFPAIR
1TO1_DIFFPAIR
1TO1_DIFFPAIR
USB_85D
USB_85D
NET_TYPE
CLK_PCIE
CLK_PCIE
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
USB
USB
SB_POWER
SB_POWER
SB_POWER
GND
PCIE_CLK100M_AP_CONN_P
PCIE_CLK100M_AP_CONN_N
CHGR_CSI_R_P
CHGR_CSI_R_N
CHGR_CSO_R_P
CHGR_CSO_R_N
SPKRAMP_L_P_OUT
SPKRAMP_L_N_OUT
SPKRAMP_SUB_P_OUT
SPKRAMP_SUB_N_OUT
SPKRAMP_R_P_OUT
SPKRAMP_R_N_OUT
SSM2315_SUB_N
SSM2315_SUB_P
SSM2315_L_N
SSM2315_L_P
SSM2315_R_N
SSM2315_R_P
AUD_LO2_N_R
AUD_LO2_P_R
AUD_LO1_N_R
AUD_LO1_P_R
AUD_LO2_N_L
AUD_LO2_P_L
SPKRAMP_INL_P
SPKRAMP_INL_N
SPKRAMP_INR_P
SPKRAMP_INR_N
SPKRAMP_INSUB_P
SPKRAMP_INSUB_N
USB_TPAD_R_P
USB_TPAD_R_N
PP3V3_S5
PP3V3_S0
PP1V5_S3RS0
GND
6
32
6
32
64
64
64
64
6
60 61
6
60 61
6
60 61
6
60 61
6
60 61
6
60 61
60
60
60
60
60
60
57 60
57 60
57 60
57 60
57 60
57 60
60
60
60
60
60
60
53
53
6 7
6 7
6 7
D
C
B
Memory Constraint Relaxations
A
Allow 0.127 mm necks for >0.127 mm lines for ARD fanout.
BOTTOM
ALLOW ROUTE
ON LAYER?
TOP
LAYER
MEM_72D 6.35 MM
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
0.127 MM
0.1 MM
MAXIMUM NECK LENGTH
6.35 MMMEM_85D
DIFFPAIR PRIMARY GAP
6 3
SIZE
A
D
PAGE TITLE
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
Project Specific Constraints
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
SYNC_DATE=02/15/2011SYNC_MASTER=K90I_MLB
DRAWING NUMBER
051-9058
REVISION
6.0.0
BRANCH
PAGE
108 OF 109
SHEET
85 OF 86
124578
8 7 6 5 4 3
K90i Board-Specific Spacing & Physical Constraints
BOARD LAYERS
TOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,ISL8,ISL9,ISL10,ISL11,BOTTOM
ISL10
ISL10
LAYER
TOP,BOTTOM
LAYER
TOP,BOTTOM
LAYER
ISL10
TOP,BOTTOM
ALLOW ROUTE
ON LAYER?
ALLOW ROUTE
ON LAYER?
ALLOW ROUTE
ON LAYER?
ALLOW ROUTE
ON LAYER?
ALLOW ROUTE
ON LAYER?
ALLOW ROUTE
ON LAYER?
ALLOW ROUTE
ON LAYER?
LAYER
DEFAULT
STANDARD
LAYER
D
50_OHM_SE
50_OHM_SE
TOP,BOTTOM
LAYER
40_OHM_SE
40_OHM_SE =STANDARD
40_OHM_SE
40_OHM_SE
TOP,BOTTOM
ISL3,ISL4,ISL9
LAYER
37_OHM_SE
37_OHM_SE
37_OHM_SE
37_OHM_SE
27P4_OHM_SE
27P4_OHM_SE
C
55_OHM_SE
55_OHM_SE
72_OHM_DIFF
72_OHM_DIFF
72_OHM_DIFF
72_OHM_DIFF
TOP,BOTTOM
ISL3,ISL4,ISL9
ISL3,ISL4,ISL9
MINIMUM LINE WIDTH
Y*
Y*
MINIMUM LINE WIDTH
Y
Y*
MINIMUM LINE WIDTH
Y
N
Y
N*
MINIMUM LINE WIDTH
Y
N
Y
N*
MINIMUM LINE WIDTH
Y
Y*
MINIMUM LINE WIDTH
Y
Y*
MINIMUM LINE WIDTH
N*
Y
N
Y
=DEFAULT
0.110 MM
0.080 MM
0.126 MM
0.126 MM
0.190 MM
0.145 MM
0.145 MM
0.310 MM
0.235 MM
0.140MM
MINIMUM NECK WIDTH
=50_OHM_SE=50_OHM_SE
=DEFAULT
MINIMUM NECK WIDTH
0.090 MM
0.080 MM
MINIMUM NECK WIDTH
0.165 MM0.165 MM
0.126 MM
0.126 MM
=STANDARD
MINIMUM NECK WIDTH
0.1 MM
0.1 MM
0.1 MM
MINIMUM NECK WIDTH
0.2 MM
0.2 MM
MINIMUM NECK WIDTH
0.090 MM0.090 MM
0.070 MM0.070 MM
MINIMUM NECK WIDTH
0.140 MM0.140 MM
0.140 MM
0.175 MM0.175 MM
BOARD AREAS
NO_TYPE,BGA
MAXIMUM NECK LENGTH
10 MM
10 MM
MAXIMUM NECK LENGTH
=STANDARD
MAXIMUM NECK LENGTH
=STANDARD
=STANDARD=STANDARD
MAXIMUM NECK LENGTH
=STANDARD
=STANDARD
=STANDARD=STANDARD=STANDARD
MAXIMUM NECK LENGTH
=STANDARD
MAXIMUM NECK LENGTH
=STANDARD
MAXIMUM NECK LENGTH
=STANDARD=STANDARD=STANDARD
DIFFPAIR PRIMARY GAP
0 MM
DIFFPAIR PRIMARY GAP
DIFFPAIR PRIMARY GAP
=STANDARD
=STANDARD
DIFFPAIR PRIMARY GAP
=STANDARD
DIFFPAIR PRIMARY GAP
=STANDARD =STANDARD
DIFFPAIR PRIMARY GAP
DIFFPAIR PRIMARY GAP
=STANDARD =STANDARD
0.190 MM
BOARD UNITS
(MIL or MM)
MM
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
0 MM
=DEFAULT=DEFAULT
=STANDARD=STANDARD
=STANDARD
=STANDARD
=STANDARD=STANDARD
=STANDARD=STANDARD
=STANDARD
=STANDARD=STANDARD
=STANDARD=STANDARD
0.190 MM0.190 MM
0.190 MM
0.200 MM0.200 MM
ALLEGRO
VERSION
16.2
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_BOARD_INFO
SPACING_RULE_SET
DEFAULT
STANDARD
BGA_P1MM
BGA_P2MM
SPACING_RULE_SET
1.5:1_SPACING
2:1_SPACING
2.5:1_SPACING
3:1_SPACING
4:1_SPACING
1:1_DIFFPAIR
LAYER
LAYER
LAYER
*
*
*
*
*
*
*
*
*
*
LINE-TO-LINE SPACING
0.1 MM
=DEFAULT
=DEFAULT
=DEFAULT
LINE-TO-LINE SPACING
0.15 MM
0.2 MM
0.25 MM
0.3 MM
0.4 MM
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
Y
TABLE_SPACING_RULE_HEAD
WEIGHT
WEIGHT
NET_SPACING_TYPE1 NET_SPACING_TYPE2
TABLE_SPACING_RULE_ITEM
?
TABLE_SPACING_RULE_ITEM
?
TABLE_SPACING_RULE_ITEM
?
TABLE_SPACING_RULE_ITEM
?
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
?
TABLE_SPACING_RULE_ITEM
?
TABLE_SPACING_RULE_ITEM
?
TABLE_SPACING_RULE_ITEM
?
TABLE_SPACING_RULE_ITEM
?
MEM_CLK
CLK_PCIE
CLK_SLOW
SPACING_RULE_SET
2X_DIELECTRIC
3X_DIELECTRIC
4X_DIELECTRIC
5X_DIELECTRIC
6X_DIELECTRIC
7X_DIELECTRIC
www.qdzbwx.com
MINIMUM NECK WIDTH
=STANDARD
=STANDARD
*
AREA_TYPE
*
*
*
*
LAYER
*
* ?
* ?
*
* ?
BGA
BGA
BGA
BGA
LINE-TO-LINE SPACING
0.140 MM
0.210 MM
0.280 MM
0.350 MM
0.420 MM
0.490 MM
MAXIMUM NECK LENGTH
=STANDARD
DIFFPAIR PRIMARY GAP
BGA_P1MM
BGA_P2MM
BGA_P2MM
BGA_P2MM
WEIGHT
TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
?
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
?
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
?*
SPACING_RULE_SET
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
0.1 MM 0.1 MM
12
D
C
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
LAYER
85_OHM_DIFF
85_OHM_DIFF
85_OHM_DIFF
85_OHM_DIFF
*
ISL3,ISL4
ISL9,ISL10
TOP,BOTTOM
LAYER
90_OHM_DIFF
B
90_OHM_DIFF
90_OHM_DIFF
90_OHM_DIFF
ISL3,ISL4
ISL9,ISL10
TOP,BOTTOM
LAYER
100_OHM_DIFF
100_OHM_DIFF
100_OHM_DIFF
100_OHM_DIFF
ISL3,ISL4
ISL9,ISL10
TOP,BOTTOM
LAYER
110_OHM_DIFF
110_OHM_DIFF
110_OHM_DIFF
110_OHM_DIFF
NOTE: These are Intel recommended impedances for PEG, unused on K90i.
* N
ISL3,ISL4
ISL9,ISL10
TOP,BOTTOM
LAYER
A
48_OHM_SE
48_OHM_SE
TOP,BOTTOM
*
LAYER
80_OHM_DIFF
80_OHM_DIFF
80_OHM_DIFF
80_OHM_DIFF
*
ISL3,ISL4
ISL9,ISL10
TOP,BOTTOM
ALLOW ROUTE
ON LAYER?
N
Y
Y
Y
ALLOW ROUTE
ON LAYER?
N*
Y
Y
Y
ALLOW ROUTE
ON LAYER?
N*
Y
Y
Y
ALLOW ROUTE
ON LAYER?
Y
Y
Y
ALLOW ROUTE
ON LAYER?
Y
Y
ALLOW ROUTE
ON LAYER?
N
Y
Y
Y
MINIMUM LINE WIDTH
0.101 MM
0.101 MM
0.125 MM
MINIMUM LINE WIDTH
0.091 MM
0.091 MM
0.111 MM
MINIMUM LINE WIDTH
=STANDARD
0.076 MM
0.076 MM
0.085 MM
MINIMUM LINE WIDTH
=STANDARD
0.068 MM
MINIMUM LINE WIDTH
0.165 MM
MINIMUM LINE WIDTH
=STANDARD
0.115 MM
0.115 MM
0.140 MM
MINIMUM NECK WIDTH
0.1 MM
0.1 MM
0.1 MM
MINIMUM NECK WIDTH
0.091 MM
0.091 MM
0.111 MM
MINIMUM NECK WIDTH
=STANDARD
0.076 MM
0.076 MM
0.085 MM
MINIMUM NECK WIDTH
=STANDARD
0.068 MM
0.068 MM0.068 MM
0.081 MM0.081 MM
MINIMUM NECK WIDTH
0.165 MM
0.090 MM0.090 MM
MINIMUM NECK WIDTH
=STANDARD
0.115 MM
0.115 MM
0.140 MM
MAXIMUM NECK LENGTH
=STANDARD=STANDARD=STANDARD
MAXIMUM NECK LENGTH
=STANDARD=STANDARD=STANDARD
MAXIMUM NECK LENGTH
=STANDARD
MAXIMUM NECK LENGTH
=STANDARD
MAXIMUM NECK LENGTH
=STANDARD
MAXIMUM NECK LENGTH
=STANDARD
DIFFPAIR PRIMARY GAP
0.170 MM 0.170 MM
0.170 MM 0.170 MM
0.190 MM 0.190 MM
DIFFPAIR PRIMARY GAP
0.180 MM 0.180 MM
0.180 MM 0.180 MM
0.200 MM 0.200 MM
DIFFPAIR PRIMARY GAP
=STANDARD
DIFFPAIR PRIMARY GAP
=STANDARD
0.250 MM
DIFFPAIR PRIMARY GAP
=STANDARD
DIFFPAIR PRIMARY GAP
=STANDARD
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
=STANDARD=STANDARD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
=STANDARD=STANDARD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
=STANDARD
TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM
0.250 MM0.250 MM
TABLE_PHYSICAL_RULE_ITEM
0.250 MM0.250 MM
TABLE_PHYSICAL_RULE_ITEM
0.200 MM0.200 MM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
=STANDARD
TABLE_PHYSICAL_RULE_ITEM
0.250 MM0.250 MM
TABLE_PHYSICAL_RULE_ITEM
0.250 MM0.250 MM
TABLE_PHYSICAL_RULE_ITEM
0.250 MM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
=STANDARD
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
=STANDARD
TABLE_PHYSICAL_RULE_ITEM
0.180 MM0.180 MM
TABLE_PHYSICAL_RULE_ITEM
0.180 MM0.180 MM
TABLE_PHYSICAL_RULE_ITEM
0.190 MM0.190 MM
85_DIFF_BGA
85_DIFF_BGA
85_DIFF_BGA
NOTE: 85_DIFF_BGA is 85-ohms differential impedance on outer layers and 80-ohms on inner layers.
90_DIFF_BGA
90_DIFF_BGA
90_DIFF_BGA
NOTE: 90_DIFF_BGA is 90-ohms differential impedance on outer layers and 85-ohms on inner layers.
100_DIFF_BGA
100_DIFF_BGA
100_DIFF_BGA
NOTE: 100_DIFF_BGA is 100-ohms differential impedance on outer layers and 95-ohms on inner layers.
NOTE: 110_DIFF is 110-ohms differential impedance on outer layers and 105-ohms on inner layers.
LAYER
ISL3,ISL4
ISL9,ISL10
LAYER
ISL3,ISL4
ISL9,ISL10
LAYER
ISL3,ISL4
ISL9,ISL10
ALLOW ROUTE
ON LAYER?
*
*
*
=85_OHM_DIFF
ALLOW ROUTE
ON LAYER?
=90_OHM_DIFF
ALLOW ROUTE
ON LAYER?
=100_OHM_DIFF
Y
Y
Y
Y
Y
Y
MINIMUM LINE WIDTH
=85_OHM_DIFF
0.075 MM
0.075 MM
MINIMUM LINE WIDTH
=90_OHM_DIFF
MINIMUM LINE WIDTH
=100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF
0.075 MM
0.075 MM
MINIMUM NECK WIDTH
=85_OHM_DIFF =85_OHM_DIFF
0.075 MM
0.075 MM
MINIMUM NECK WIDTH
0.075 MM0.075 MM
0.075 MM0.075 MM
MINIMUM NECK WIDTH
0.075 MM
0.075 MM
MAXIMUM NECK LENGTH
MAXIMUM NECK LENGTH
MAXIMUM NECK LENGTH
=90_OHM_DIFF=90_OHM_DIFF
6 3
DIFFPAIR PRIMARY GAP
=85_OHM_DIFF =85_OHM_DIFF
0.125 MM 0.125 MM
0.125 MM 0.125 MM
DIFFPAIR PRIMARY GAP
DIFFPAIR PRIMARY GAP
=100_OHM_DIFF =100_OHM_DIFF
0.125 MM 0.125 MM
0.125 MM
=90_OHM_DIFF=90_OHM_DIFF
0.125 MM0.125 MM
0.125 MM0.125 MM
0.125 MM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
SYNC_MASTER=K90I_MLB SYNC_DATE=02/15/2011
PAGE TITLE
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
PCB Rule Definitions
Apple Inc.
R
DRAWING NUMBER
051-9058
REVISION
6.0.0
BRANCH
PAGE
109 OF 109
SHEET
86 OF 86
SIZE
B
A
D
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
124578
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