Apple J30 User Manual
8
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.
2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.
7
6 5 4 3
2 1
REV ECN
DESCRIPTION OF REVISION
CK
APPD
DATE
6
0001395489
ENGINEERING RELEASED
2012-03-13
SCHEM,MLB,J30
03/12/12
D
C
B
Sync
Date
02/15/2011
02/15/2011
03/26/2009
02/15/2011
02/15/2011
02/15/2011
02/15/2011
02/15/2011
02/15/2011
02/15/2011
02/15/2011
02/15/2011
02/15/2011
09/27/2011
02/15/2011
06/13/2011
06/13/2011
06/13/2011
06/13/2011
06/13/2011
06/13/2011
02/15/2011
06/13/2011
02/15/2011
09/19/2011
02/15/2011
02/15/2011
02/15/2011
02/15/2011
11/03/2011
06/13/2011
02/15/2011
02/15/2011
02/15/2011
02/15/2011
06/15/2011
02/15/2011
02/15/2011
06/23/2011
02/15/2011
11/08/2011
07/08/2011
07/08/2011
02/15/2011
12/21/2011
Page
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
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TABLE_TABLEOFCONTENTS_ITEM
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TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
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TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
(.csa)
50
SMC Support
51
LPC+SPI Debug Connector
52
SMBus Connections
53
Power Sensors: Load Side
54
Power Sensors: High Side
55
Thermal Sensors
56
Fan
57
WELLSPRING 1
58
WELLSPRING 2
59
Digital Accelerometer
61
SPI ROM
62
AUDIO: CODEC/REGULATOR
64
AUDIO: DETECT/MIC BIAS
65
AUDIO: HEADPHONE FILTER
66
AUDI0: SPEAKER AMP
67
AUDIO: JACK
68
AUDIO:Jack Translators
69
DC-In & Battery Connectors
70
PBus Supply & Battery Charger
71
System Agent Supply
72
5V/3.3V SUPPLY
73
1.5V DDR3 Supply
74
CPU IMVP7 & AXG VCore Regulator
75
CPU IMVP7 & AXG VCore Output
76
CPUVCCIO (1.05V) Power Supply
77
Misc Power Supplies
78
Power FETs
79
Power Control 1/ENABLE
90
LVDS CONNECTOR
93
DisplayPort/T29 A MUXing
94
Thunderbolt Connector A
97
LCD Backlight Driver
100
CPU Constraints
101
Memory Constraints
102
PCH Constraints 1
103
PCH Constraints 2
104
Ethernet/FW Constraints
105
T29 Constraints
106
SMC Constraints
108
Project Specific Constraints
109
PCB Rule Definitions
Contents
Sync
YONAS_J30
J31_MLB
K90I_MLB
LINDA_J30
YONAS_J30
YONAS_J30
K90I_MLB
J31_MLB
JACK_J30
K90I_MLB
K90I_MLB
KAVITHA_J30
DIRK_J30
KAVITHA_J30
KAVITHA_J30
DIRK_J30
DIRK_J30
JACK_J30
JACK_J30
JACK_J30
JACK_J30
JACK_J30
JACK_J30
JACK_J30
JACK_J30
JACK_J30
K90I_MLB
K90I_MLB
K90I_MLB
K90I_MLB
K90I_MLB
J31_MLB
K90I_MLB
K90I_MLB
K90I_MLB
K90I_MLB
K90I_MLB
K90I_MLB
K90I_MLB
K90I_MLB
K90I_MLB
Date
01/02/2012
06/15/2011
02/15/2011
09/28/2011
11/03/2011
08/01/2011
02/15/2011
07/01/2011
09/28/2011
02/15/2011
02/15/2011
07/25/2011
02/16/2012
07/25/2011
07/25/2011
11/10/2011
02/20/2012
07/29/2011
09/27/2011
09/28/2011
08/22/2011
07/28/2011
08/03/2011
07/28/2011
09/28/2011
07/28/2011
02/15/2011
02/15/2011
02/15/2011
02/15/2011
02/15/2011
07/08/2011
02/15/2011
02/15/2011
02/15/2011
02/15/2011
02/15/2011
02/15/2011
02/15/2011
02/15/2011
02/15/2011
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
(.csa)
1
1
2
3
4
5
6
7
8
9
Table of Contents
2
System Block Diagram
3
Revision History
4
Revision History
5
BOM Configuration
7
FUNC TEST
8
Power Aliases
9
Signal Aliases
10
CPU DMI/PEG/FDI/RSVD
11
CPU CLOCK/MISC/JTAG
12
CPU DDR3 INTERFACES
13
CPU POWER
14
CPU GROUNDS
16
CPU DECOUPLING-I
17
CPU DECOUPLING-II
18
PCH SATA/PCIe/CLK/LPC/SPI
19
PCH DMI/FDI/PM/Graphics
20
PCH PCI/USB/TP/RSVD
21
PCH GPIO/MISC/NCTF
22
PCH POWER
23
PCH GROUNDS
24
PCH DECOUPLING
25
CPU & PCH XDP
26
Chipset Support
27
USB HUB & MUX
28
CPU Memory S3 Support
29
DDR3 SO-DIMM Connector A
30
DDR3 Byte/Bit Swaps
31
DDR3 SO-DIMM Connector B
33
SD Card Connector
34
DDR3/FRAMEBUF VREF MARGINING
35
X19/ALS/CAMERA CONNECTOR
36
T29 Host (1 of 2)
37
T29 Host (2 of 2)
38
T29 Power Support
39
ETHERNET PHY (CAESAR IV)
40
Ethernet Connector
41
FireWire LLC/PHY (FW643E)
42
FireWire Port & PHY Power
43
FireWire Connector
45
SATA/IR/SIL Connectors
46
External A USB3 Connector
47
External B USB3 Connector
48
Front Flex Support
49
SMC
Contents
K90I_MLB
MASTER
K20A_MLB
K90I_MLB
K90I_MLB
K90I_MLB
K90I_MLB
K90I_MLB
MASTER
MASTER
MASTER
MASTER
MASTER
JACK_J30
MASTER
J31_MLB
J31_MLB
J31_MLB
J31_MLB
J31_MLB
J31_MLB
K90I_MLB
J31_MLB
K90I_MLB
LINDA_J30
K90I_MLB
K90I_MLB
K90I_MLB
K90I_MLB
YONAS_J30
J31_MLB
K90I_MLB
K90I_MLB
K90I_MLB
K90I_MLB
J31_MLB
K90I_MLB
K90I_MLB
K90I_MLB
K90I_MLB
YONAS_J30
J31_MLB
J31_MLB
K90I_MLB
YONAS_J30
D
C
B
Page
TABLE_TABLEOFCONTENTS_HEAD TABLE_TABLEOFCONTENTS_HEAD
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
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TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
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TABLE_TABLEOFCONTENTS_ITEM
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TABLE_TABLEOFCONTENTS_ITEM
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A
Schematic / PCB #’s
PART NUMBER
051-9058
820-3115
DRAWING
TITLE=MLB
ABBREV=DRAWING
LAST_MODIFIED=Tue Mar 13 14:00:17 2012
QTY
1
1
DESCRIPTION
SCHEM,MLB,J30
PCBF,MLB,J30
REFERENCE DES
SCH
PCB
CRITICAL
CRITICAL
CRITICAL
BOM OPTION
SIZE
A
D
DRAWING TITLE
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
3
SCHEM,MLB,J30
Apple Inc.
R
DRAWING NUMBER
051-9058
REVISION
6.0.0
BRANCH
PAGE
1 OF 109
SHEET
1 OF 86
1245678
8 7 6 5 4 3
12
U1000
INTEL CPU
2.X GHz
IVY BRIDGE 2C-35W
PG 9-13
DDR3-1333/1600MHZ
D
GPIO
PG 19
U2600
SYSTEM
CLOCK
PG 24
J4501
SATA
CONN
HDD
PG 41
J4500
SATA
CONN
ODD
PG 41
U9390
MUX
PG 75
0
1
DP/TMDS
4 LANEs
U3600
CIO
PCIe x4
C
J9400
Display Port
/ T29
CONN
PG 76
1.05V/6GHZ.
1.05V/1.5GHZ.
T29 Host
PG 33,34
DP
J9000
LVDS
CONN
B
PG 74
BUFFER
PG 16
0
SATA
PG 16
1
eDP OUT
HDMI OUT
RGB OUT
DP OUT
DVI OUT
TMDS OUT
PG 17
LVDS OUT
PG 17
PG 18
PCI-E
PG 16
JTAG
PG 16
CLK
PCI
PEG
PG 16
FDI
PG 17
DMI
PG 17
INTEL
PANTHER POINT-MPCH
U1800
PG 16-21
PCI-E
(UP TO 8 LINES)
PG 16
2 3 1
PG 16
MISC
PG 19
SPI
PG 16
LPC
PG 16
PWR
CTRL
PG 17
USB
SMBUS
PG 16
HDA
PG 16
J2500
2 DIMMs
RTC
J3502
13
12
1011
8 9
6 70
543
21
(UP TO 14 DEVICES)
4
2 3
PG 18 PG 18
1
USB 3
XDP CONN
PG 23
J3100
PG 29
J2900
PG 27
DIMM
CAMERA
PG 32
DIMM’s
U6100
SPI
Boot ROM
PG 56
J3501
X19
Bluetooth
1 2 3
U2700
USB
HUB
PG 25
U4900
U5701
TP/KB
PSOC
From PCH
I2C
SMS ADC Ser
SMC
PG 45
J5800, J5713
J6900, J6950
DC/BATT
U5511
TEMP SENSOR
U5920
Sudden Motion Sensor
U5400,U5410,U5340,U5360,U5370,Q5480,Q5490
POWER SENSE
J5601
FAN CONN AND CONTROL
Fan
Prt
SPI
PG 63
PG 51
PG 55
PG 49, 50
PG 52
J5100
LPC+SPI Conn
Port80,serial
POWER SUPPLY
PG 63-73
PG 47
D
C
TRACKPAD/
PG 53PG 32
KEYBOARD
PG 54, 53
U4800
IR
Controller
PG 44 PG 41
U2760
USB
EHCI
MUX
XHCI
PG 25
J2550
J4501
IR
J4700
EXTERNAL B
USB 3
PG 43
J4600
EXTERNAL A
USB 3
PG 42
B
PCH XDP
CONN
PG 23
U6201
EXTMIC LINEIN HPOUT SPDIF MICIN LINEOUT
U4100
A
J3501
X19
AirPort
PG 32
FW643E
PG 38
J4310
FW800
CONN
PG 40
U3900
E-NET
BCM57765
PG 36
J4000
E-NET
CONN
PG 37
J3300
SD Card
CONN
PG 30
U6400
MIC BIAS
PG58
6 3
AUDIO
Codec
PG 57
J6700 J6701
AUDIO
CONNs
PG 61
U6610, U6620, U6630
SPEAKER
AMPs
PG 60
J6702
J6703
SYNC_MASTER=MASTER
PAGE TITLE
System Block Diagram
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
SYNC_DATE=02/15/2011
DRAWING NUMBER
051-9058
REVISION
6.0.0
BRANCH
PAGE
2 OF 109
SHEET
2 OF 86
124578
SIZE
A
D
8 7 6 5 4 3
12
R6905
Q5300
V
PP5V_S3_REG
PP3V3_S5_REG
D6990
R5400
A
22
PP3V3_S5
8
PP3V3_ENET
Q7922
PM_SLP_S3_L&&WOL_EN||SMC_ADAPTER_EN//WOL_EN
R7803
Q7800
P3V3S4_EN
Q7810
P3V3S3_EN
Q7820
P5V_3V3_SUS_EN
Q7830
PM_SLP_S3_L_R
2
15
PP5V_S0_CPUVCCIOS0
CPUVCCIOS0_EN
21
24
CPUIMVP_VR_ON
DDRREG_EN
DDRVTT_EN
PP5V_S0_FET
PVCCSA_EN
CPU_VCCSA_VID<1>
CPU_VCCSA_VID<0>
14
BCM57765
EN
U3900
CAESAR IV
(PAGE 36)
PP3V3_S4_FET
PP3V3_S3
PP3V3_SUS_FET
TPS720105
U7740
(PAGE 71)
14
VCC
EN
VR_ON
Q7860
P5VS0_EN
Q4590
ODD_PWR_EN_L
12
14
10-3
PP1V05_SUS_LDO
ENABLE
3.425V G3HOT
PM6640
U6990
(PAGE 63)
1.05V
ISL95870
U7600
(PAGE 70)
VIN
CPU VCORE
MAX15119GTM
U7400
(PAGE 68)
1.5V
S5
S3
0.75V
TPS51916
U7300
(PAGE 67)
VCC
EN
ISL95870A
VID0
VID1
(PAGE 65)
PP5V_S0_FET
PP5V_SW_ODD
PP1V2_ENET_PHY
VOUT
PGOOD
VOUT
VOUT
PGOOD
PGOODG
VLDOIN
VIN
VOUT1
VOUT2
PGOOD
VOUT
U7100
PGOOD
15
P1V8_S0_EN
17
P1V5S0_EN
9
19
PP3V3_FW_P3V3FWFET
PP3V42_G3H_REG
R7640
A
CPUVCCIOS0_PGOOD
CPUIMVP_PGOOD
CPUIMVP_AXG_PGOOD
PPDDR_S3_REG
PPVTT_S0_DDR_LDO
DDRREG_PGOOD
PP1V5S0FET_GATE
PPVCCSA_S0_REG
PVCCSA_PGOOD
PP5V_S0_VMON
PP1V5_S3RS0_VMON
PP1V05_S0_VMON
PP3V3_S0
16
MAX15053EWL
EN
U7760
(PAGE 71)
TPS62201
EN
U7770
(PAGE8 71)
TPS22924
EN
U4201
(PAGE 39)
PPCPUVCCIO_S0_REG
SMC_CPU_FSB_ISENSE
22-1
R5320
SMC_CPU_VSENSE
V
PPVCORE_S0_CPU_REG
R5330
SMC_GFX_VSENSE
V
PPVCORE_S0_AXG_REG
25-1
26-1
Q7801
PP1V5_S3RS0_FET
23
23-1
PP3V3_S0_VMON
VMON_Q2
ISL88042IRTEZ
VMON_Q3
VMON_Q4
(PAGE 73)
PP1V8_S0_REG
PP1V5_S0_REG
PP3V3_FW_FE5T
3
16
U7960
P1V05_S0_LDO_EN
SMC PWRGD
SN0903048
(PAGE 44)
22
18
EN
20
U5010
25
26
CPUIMVP_AXG_PGOOD
P1V8S0_PGOOD
P5V3V3_PGOOD
CPUVCCIOS0_PGOOD
PVCCSA_PGOOD
ALL_SYS_PWRGD
TPS720105
U7780
(PAGE 71)
PP1V05_S0_LDO
SMC_RESET_L
TPS22924
U4202
(PAGE 39)
EN
FW_PWR_EN
RSMRST_PWRGD
SMC_ONOFF_L
4
PP1V0_FW_FWPHY
COUGAR-POINT
(PCH)
SYS_RERST#
27
U2850
25
9
5
PM_SLP_S5_L
PM_SLP_S4_L
PM_SLP_S3_L
19
SYNC_MASTER=K20A_MLB
PAGE TITLE
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
U1800
PM_PCH_PWRGD
(PAGE 16~21)
SM_DRAMPWROK
CPU
U1000
UNCOREPWRGOOD
(PAGE 9~13)
SMC
PWRGD(P12)
RSMRST_IN(P13)
PWR_BUTTON(P90)
SLP_S5_L(P95)
SLP_S4_L(P94)
SLP_S3_L(P93)
U4900
(PAGE 43)
RSMRST_OUT(P15)
99ms DLY
IMVP_VR_ON(P16)
Revision History
Apple Inc.
R
PWRBTN#
RSMRST#
PLTRST#
PROCPWRGD
DRAMPWROK
RESET*
SYSRST(PA2)
P17(BTN_OUT)
RES*
PM_PWRBTN_L
PM_SYSRST_L
PM_RSMRST_L
PM_DSW_PWRGD
PLT_RERST_L
CPU_PWRGD
PM_MEM_PWRGD
30
PM_DSW_PWRGD
PM_RSMRST_L
CPUIMVP_VR_ON
PM_SYSRST_L
PM_PWRBTN_L
SMC_RESET_L
29
28
10
12
DRAWING NUMBER
REVISION
BRANCH
PAGE
SHEET
124578
26
6-1
4
SYNC_DATE=03/26/2009
051-9058
6.0.0
3 OF 109
3 OF 86
SIZE
D
C
B
A
D
J30 POWER SYSTEM ARCHITECTURE
PPDCIN_G3H
V
1
R7020
A
SMC_RESET_L
VIN
BATTERY CHARGER
Q7055
CHGR_BGATE
U7000
ISL6259HRTZ
PBUS SUPPLY/
(PAGE 63)
D
J6900
AC
ADAPTER
DCIN(16.5V)
F6905
6A FUSE
IN
J6950
PPVBATT_G3H_CONN
3S2P
(9 TO 12.6V)
Q5310
SMC_DCIN_ISENSE
R6990
VOUT
PPVBAT_G3H_CHGR_R
PPVBAT_G3H
R7050
SMC_BATT_ISENSE
PPDCIN_S5_P3V42G3H
F7040
1
A
PPBUS_G3H
C
SMC
U4900
P60
(PAGE 44)
SLP_S5#(E4)
COUGAR-POINT
(PCH)
B
A
U1800
(PAGE 16~21)
RC
DELAY
RC
DELAY
RC
DELAY
RC
DELAY
SLP_S4#(H4)
SLP_S3#(F4)
1V05_S0_LDO_EN
CPUVCCIOS0_EN
PVCCSA_EN
P1V5S0_EN
P1V8S0_EN
SMC_PM_G2_EN
SLP_SUS
PM_SLP_S3_L_R
21
21
22
19
17
6
R7916
PM_SLP_S5_L
R7917
RC
DELAY
RC
DELAY
R7978
P5VS0_EN
P3V3S0_EN
PBUSVSENS_EN
RC
DELAY
P3V3S4_EN
P5V_3V3_SUS_EN
P5VS3_EN
DDRREG_EN
P3V3S3_EN
PM_SLP_S4_L
PM_SLP_S3_L
PG73
P3V3S5_EN
PG73
PG 17
PG73
PG73
PG73
PG 17
PG 17
14-1
14-1
14-1
7
11
11
10-1
PG73
13-1
15
13-2
13
14
F9700
LCD_BKLT_EN
BKLT_PLT_RST_L
&&
PPBUS_SW_LCDBKLT_PWR
Q4260
FWP5ORT_PWR_EN
T29_A_HV_EN
www.qdzbwx.com
R5410
A
13
Q9706
VIN
LP8550
U9701
EN
(PAGE 76)
Q3880
PPBUS_S5_HS_OTHER_ISNS
P5VS3_EN_L
P3V3S5_EN_L
7
PP5V_S5_LDO
PPVOUT_SW_LCDBKLT
VOUT
F4260
LT3957
U3890
(PAGE 35)
PPBUS_FW_FET
VIN
VOUT
EN1
EN2
VREG5
P5V_3V3_SUS_EN
PP15V_T29_REG
VIN
5V
(L/H)
3.3V
(R/H)
TPS51125
U7200
(PAGE 66)
PGOOD
P5V3V3_PGOOD
Q7840
VOUT1
VOUT2
14-1
PP5V_SUS_FET
10-2
6 3
PROTO:
8 7 6 5 4 3
12
D
C
D
C
SIZE
B
A
D
B
A
6 3
SYNC_MASTER=K90I_MLB SYNC_DATE=02/15/2011
PAGE TITLE
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
Revision History
Apple Inc.
R
DRAWING NUMBER
051-9058
REVISION
6.0.0
BRANCH
PAGE
4 OF 109
SHEET
4 OF 86
124578
8 7 6 5 4 3
12
BOM Variants
BOM NUMBER
607-8895
085-3092
607-8721
607-8722
607-8723
D
607-9309
607-9310
607-9311
639-3752
639-3756
639-3753
639-3755
639-3751
639-3754
C
J30 BOM GROUPS
BOM GROUP
J30_COMMON
J30_COMMON1
J30_COMMON2
J30_PROGPARTS
J30_DEVEL:ENG BKLT:ENG,XDP_CONN,XDP_CPU:BPM,XDP_PCH,LPCPLUS_CONN:YES,LOADISNS:YES,DDRVREF_DAC,S0PGOOD_ISL
J30_DEVEL:PVT
J30_DEBUG:ENG
J30_DEBUG:PVT
J30_DEBUG:PROD
Module Parts
PART NUMBER
337S4113
B
337S4264
337S4265
337S4269
343S0534
338S0753
338S1072 CRITICAL
353S3055 CRITICAL
946-3827
516S0806
516-0246 CRITICAL
516S0805 CRITICAL SODIMM:MOLEX
516-0245 SODIMM:MOLEXCRITICAL
516S0805
516-0246
BOM NAME
CMN PTS,PCBA,MLB,J30
J30 MLB DEVELOPMENT BOM
POWER FETS PAIR,FAIRCHILD,DDR,J30
POWER FETS PAIR,FAIRCHILD,5V_S3,J30
POWER FETS PAIR,FAIRCHILD,PBUS_CHARGER,J30
POWER FETS PAIR,RENESAS,DDR,J30
POWER FETS PAIR,RENESAS,5V_S3,J30
POWER FETS PAIR,RENESAS,PBUS_CHARGER,J30
PCBA,MLB,MOL,2.9G,J30
PCBA,MLB,HYB,2.9G,J30
PCBA,MLB,FOX,2.5G,J30
PCBA,MLB,HYB,2.5G,J30
PCBA,MLB,MOL,2.5G,J30
PCBA,MLB,FOX,2.9G,J30
ALTERNATE,COMMON,J30_COMMON1,J30_COMMON2,J30_DEBUG:ENG,J30_PROGPARTS,T29BST:Y,TBTHV:P15V
BATT_3S,CPUMEM_S0,USBHUB2513B,HUB_3NONREM,T29:YES,SDRV_PD,SDRVI2C:MCU,AXG_PHASE1,BTPWR:S4,UV_GLUE_J30
BOOTROM_PROG,SMC_PROG,TPAD_PROG,ENET_PROG,T29ROM:PROG,T29MCU:PROG
DEVEL_BOM,BKLT:PROD,MOJO:YES,XDP,LPCPLUS_R:YES,VREFDQ:M1_M3,VREFCA:LDO,USBHUB2514B
BKLT:PROD,MOJO:YES,XDP,LPCPLUS_R:YES,LOADISNS:NO,VREFDQ:M1_M3,VREFCA:LDO,USBHUB2513B
QTY
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
DESCRIPTION
IC,IVB,2C,35W,1023BGA
IVB,S R0N0,PRQ,L1,2.5,35W,2+2,1.1,3M,BGA
IVB,S R0MU,PRQ,L1,2.9,35W,2+2,1.25,4M,BGA
PANTHERPOINT,C1,SLJ8C,PRQ,BD82HM77
IC,BCM57765B0,ENET&SD,8X8
IC,FW643E,1394B PHY/OHCI LINK/PCI-E,12
IC,T29,PRQ,S LJJY,FCBGA,15x15MM,C1
IC,PI3VEDP212,X2 DISPLAYPORT 2:1 MUX,QFN
J30 MLB DYMAX ADHESIVE 29993-SC 0.48G
CONN,204P,SODIMM,SOCKET,DDR3,RAM,BGA,FOXCONN
CONN,204P,SODIMM,DDR3,P=0.6MM,FOXCONN
CONN,204P,SODIMM,SOCKET,DDR3,RAM,BGA,MOLEX
CONN,204P,SODIMM,DDR3,P=0.6MM,MOLEX
CONN,204P,SODIMM,SOCKET,DDR3,RAM,BGA,MOLEX
CONN,204P,SODIMM,DDR3,P=0.6MM,FOXCONN
BOM OPTIONS
J30_COMMON,FET_PAIR
J30_DEVEL:ENG
DDR_POWER_FET:FAIR
5V_S3_POWER_FET:FAIR
CHARGER_POWER_FET:FAIR
DDR_POWER_FET:REN
5V_S3_POWER_FET:REN
CHARGER_POWER_FET:REN
J30_CMNPTS,CPU_2_9GHZ,SODIMM:MOLEX,EEEE_F1YK
J30_CMNPTS,CPU_2_9GHZ,SODIMM:HYBRID,EEEE_F1YH
J30_CMNPTS,CPU_2_5GHZ,SODIMM:FOXCONN,EEEE_F1YL
J30_CMNPTS,CPU_2_5GHZ,SODIMM:HYBRID,EEEE_F1YJ
J30_CMNPTS,CPU_2_5GHZ,SODIMM:MOLEX,EEEE_F1YM
J30_CMNPTS,CPU_2_9GHZ,SODIMM:FOXCONN,EEEE_F1YG
BOM OPTIONS
MIKEY,TPAD:Z2,RAMCFG_SLOT
LPCPLUS_CONN:YES,XDP_CONN
DEVEL_BOM,MOJO:YES,XDP,LPCPLUS_R:YES,VREFDQ:M1_M3,VREFCA:LDO_DAC
REFERENCE DES
U1000
U1000
U1000
U1800
U3900
U4100
U3600
U9390
UV_GLUE_J30
J3100
J2900
J3100
J2900
J3100
J2900
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
BOM OPTION
CPU_IVB_2C
CPU_2_5GHZ
CPU_2_9GHZ
UV_GLUE_J30
SODIMM:FOXCONN
SODIMM:FOXCONN
SODIMM:HYBRID
SODIMM:HYBRID
T29:YES
TABLE_BOMGROUP_HEAD
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_HEAD
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
Bar Code Labels / EEEE #’s
PART NUMBER
826-4393
826-4393
826-4393
826-4393
826-4393
QTY
1
1
1
1
1
1
DESCRIPTION
LBL,P/N LABEL,PCB,28MM X 6 MM
LBL,P/N LABEL,PCB,28MM X 6 MM
LBL,P/N LABEL,PCB,28MM X 6 MM
LBL,P/N LABEL,PCB,28MM X 6 MM
LBL,P/N LABEL,PCB,28MM X 6 MM
LBL,P/N LABEL,PCB,28MM X 6 MM
REFERENCE DES
[EEEE:F1YG]
[EEEE:F1YH]
[EEEE:F1YJ]
[EEEE:F1YK]
[EEEE:F1YL]
[EEEE:F1YM]
Programmable Parts
PART NUMBER
335S0862
341S3096
335S0550
341S3430
337S3997 CRITICAL
341S3365 CRITICAL
338S1098
341S3300 CRITICAL
335S0807
335S0812
341S3558
341S2384
341S3522
QTY
1
1
1
1
1
1
1
1
1
1
1
1
1
DESCRIPTION
IC,FLASH,SERIAL,SPI,!MBIT,2V7,REV F
IC ENET,1!MBITFLAH,CIV REV01,K9x
IC,EEPROM,SERIAL,SPI,4Kx8,1.8V,MLP8,LF
IC,T29 EEPROM,LR,J30/J31
IC,MCU,32B,LPC1112A,16KB/2KB,HVQFN25
IC,PROGRMD,T29,PORT MCU,K90IA,K91A,K92A
IC,SMC12-A3,40MHZ/50DMIPS MCU,9x9,157BGA
IC,SMC,EXTERNAL,FSB,A3,J30
IC,SPI SRL 50MHZ FLASH,64MBT,8SOP,FUSE=1
64 MBIT SPI SRL DUAL I/O FLSH,SOIC8
IC,EFI,V00C7,J30/J31
IR,ENCORE II, CY7C63803-LQXC
IC,PSOC,TP/KB,J30/J31
Alternate Parts
PART NUMBER
138S0603
128S0303 128S0353 138S0648
138S0676 138S0691
152S0778
376S0855
376S0977 376S0859
376S0972
376S0777
376S0953
377S0107
371S0709
607-9310
607-9311
ALTERNATE FOR
PART NUMBER
138S0602
157S0084
152S0693
376S1032
376S1017
376S0845376S0937
376S0761
376S0958376S0957
376S0958
377S0126
371S0652
514-0671514-0788
607-8722
607-8723
BOM OPTION
REF DES
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
COMMENTS:
Murata alt to Samsung
Delta alt to TDK Magnetics157S0058
Panasonic alt to Sanyo
Murata alt to Samsung
Cyntec alt to Vishay
Diodes alt to Toshiba
Diodes alt to Toshiba
Rohm alt to Toshiba
Fairchild alt to Renesas
AON alt to Siliconix
Fairchild alt to Fairchild
Fairchild alt to Renesas
ONsemi alt to Semtech
NXP alt to Infineon
Acon(w liteon) alt to Acon
Renesas alternate to fairchild
Renesas alternate to fairchild
REFERENCE DES
U3990
U3990
U3690
U3690
U9330
U9330
U4900
U4900
U6100
U6100
U6100
U4800
U5701
TABLE_ALT_HEAD
PART NUMBER
TABLE_ALT_ITEM
152S1499
TABLE_ALT_ITEM
152S1493
TABLE_ALT_ITEM TABLE_ALT_ITEM
138S0652
TABLE_ALT_ITEM
TABLE_ALT_ITEM
152S1512
TABLE_ALT_ITEM
152S1019
TABLE_ALT_ITEM
376S1023 376S0960
TABLE_ALT_ITEM
353S3312
TABLE_ALT_ITEM
353S3238
TABLE_ALT_ITEM
353S3519
TABLE_ALT_ITEM
TABLE_ALT_ITEM
138S0681
TABLE_ALT_ITEM
138S0671
TABLE_ALT_ITEM
TABLE_ALT_ITEM
377S0124
TABLE_ALT_ITEM
341S3492
TABLE_ALT_ITEM
376S1053
376S1076
CRITICAL
CRITICAL826-4393
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
ALTERNATE FOR
PART NUMBER
152S0864
152S1300
138S0660138S0684
152S1295
152S1271
353S3055
353S1428
353S2179
155S0367155S0578
138S0638
138S0673
376S0796376S0903
377S0057
341S3096
376S0604
376S0634
BOM OPTION
EEEE_F1YG
EEEE_F1YH
EEEE_F1YJ
EEEE_F1YK
EEEE_F1YL
EEEE_F1YM
BOM OPTION
ENET_BLANK
ENET_PROG
T29ROM:BLANK
T29ROM:PROG
T29MCU:BLANK
T29MCU:PROG
SMC_BLANK
BOOTROM_BLANK
BOOTROM_BLANK
BOOTROM_PROG
TPAD_PROG
BOM OPTION
SMC_PROG
REF DES
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
COMMENTS:
Coilcraft alt to Murata
Coilcraft alt to Murata
Samsung/Murata alt to Taiyo
Murata alt to Taiyo
Cyntec alt to NEC
Cyntec alt to TOKO
Siliconix alt to Renesas
NXP alt to Pericom
Intersil alt to TI
Intersil alt to TI
Taiyo alt to Murata
Taiyo alt to Samsung
Taiyo alt to Murata
Fairchidl alt to Vishay
Amotech alt to Tdk
Numonix alt to Atmel (ENET ROM)
Diodes alt to fairchild
Diodes alt to onsemi
D
C
TABLE_ALT_HEAD
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
B
Sub BOM
A
PART NUMBER
607-8895
607-8721
607-8722
607-8723 CSET3 CRITICAL
QTY
1
1
1
1
1
DESCRIPTION
J30 MLB DEVELOPMENT
CMN PTS,PCBA,MLB,J30
POWER_FETS PAIR,FAIRCHILD,DDR,J30
POWER_FETS PAIR,FAIRCHILD,5V_S3,J30
POWER_FETS PAIR,FAIRCHILD,PBUS_CHARGER,J30
6 3
REFERENCE DES
DEVEL
CMNPTS
CSET2 CRITICAL
CRITICAL
CRITICAL085-3092
CRITICAL
CRITICAL
BOM OPTION
DEVEL_BOM
J30_CMNPTS
FET_PAIRCSET1
FET_PAIR
FET_PAIR
PAGE TITLE
BOM Configuration
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
SYNC_DATE=02/15/2011SYNC_MASTER=K90I_MLB
DRAWING NUMBER
051-9058
REVISION
6.0.0
BRANCH
PAGE
5 OF 109
SHEET
5 OF 86
124578
SIZE
A
D
8 7 6 5 4 3
12
NC_EDP_TXP<0..3>
Functional Test Points
NC NO_TESTs
Fan Connectors
I12
I15
I16
D
I554
I553
I555
TRUE
TRUE
TRUE
MIC FUNC_TEST
TRUE
TRUE
TRUE
PP5V_S0
FAN_RT_PWM
FAN_RT_TACH
(NEED TO ADD 1 GND TP)
BI_MIC_LO
BI_MIC_HI
BI_MIC_SHIELD
(NEED TO ADD 1 GND TP)
6 7
52
52
61 62
61 62
61 62
SPEAKER FUNC_TEST
I227
I226
I228
I230
I229
I231
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
SPKRAMP_L_N_OUT
SPKRAMP_L_P_OUT
SPKRAMP_R_N_OUT
SPKRAMP_R_P_OUT
SPKRAMP_SUB_N_OUT
SPKRAMP_SUB_P_OUT
60 61 85
60 61 85
60 61 85
60 61 85
60 61 85
60 61 85
LVDS FUNC_TEST
I259
I258
I260
I407
C
I262
I261
I256
I257
I255
I252
I253
I254
I250
I251
I313
I246
I247
I248
I249
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
PP3V3_LCDVDD_SW_F
PP3V3_S0_LCD_F
PPVOUT_SW_LCDBKLT
LVDS_DDC_CLK
LVDS_DDC_DATA
LVDS_IG_A_DATA_N<0>
LVDS_IG_A_DATA_P<0>
LVDS_IG_A_DATA_N<1>
LVDS_IG_A_DATA_P<1>
LVDS_IG_A_DATA_N<2>
LVDS_IG_A_DATA_P<2>
LVDS_CONN_A_CLK_F_N
LVDS_CONN_A_CLK_F_P
LED_RETURN_1
LED_RETURN_2
LED_RETURN_3
LED_RETURN_4
LED_RETURN_5
LED_RETURN_6
(NEED TO ADD 5 GND TP)
(NEED 2 TP)
(NEED 2 TP)
6
74
6
74
74 77
8
74
8
74
17 74 80
17 74 80
17 74 80
17 74 80
17 74 80
17 74 80
74 85
74 85
74 77
74 77
74 77
74 77
74 77
74 77
SATA ODD CONN
I264
I268
I269
I267
B
I265
I266
I628
I627
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
PP5V_SW_ODD
SMC_ODD_DETECT
SATA_ODD_D2R_C_P
SATA_ODD_D2R_C_N
SATA_ODD_R2D_P
SATA_ODD_R2D_N
SMC_SSD_TEMP_CTL_R
HDD_OOB_TEMP
(NEED TO ADD 3 GND TP)
(NEED 2 TP)
41 45
41 85
41 85
41 80
41 80
6
41
SATA HDD/IR/SIL
I319
I314
I315
I318
I317
I307
I309
I625
I311
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
PP5V_S0_HDD_FLT
SATA_HDD_R2D_P
SATA_HDD_R2D_N
SATA_HDD_D2R_C_P
SATA_HDD_D2R_C_N
SYS_LED_ANODE_R
IR_RX_OUT
SMC_SSD_THROTTLE_R
PP5V_S3_IR_R
(NEED TO ADD 3 GND TP)
(NEED 2 TP)
41 80
41 80
41 80
41 80
41
41 44
41
6
41
BATT POWER CONN
I322
I321
I320
A
I305
TRUE
TRUE
TRUE
TRUE
SMBUS_SMC_5_G3_SCL
SMBUS_SMC_5_G3_SDA
SYS_DETECT_L
PPVBAT_G3H_CONN
(NEED TO ADD 5 GND TP)
(NEED 5 TP)
6
45 48 84
6
45 48 84
63
63 64
BIL CONN
I326
I323
I324
I325
I308
TRUE
TRUE
TRUE
TRUE
TRUE
PP3V42_G3H
SMBUS_SMC_5_G3_SCL
SMBUS_SMC_5_G3_SDA
SMC_BIL_BUTTON_L
SMC_LID_R
(NEED TO ADD 2 GND TP)
6 7
6
45 48 84
6
45 48 84
45 46 63
63
I303
I301
I302
I300
I299
I298
I293
I288
I292
I295
I290
I271
I289
I595
I594
I593
I375
I374
I372
I370
I371
I369
I368
I361
I366
I365
I363
I364
I362
I360
I359
I357
I358
I377
I564
I626
I354
I355
I344
I345
I346
I347
I349
I348
I350
I352
I351
I353
I327
I328
I329
I343
I342
I341
I339
I340
I338
I336
I337
I333
I335
I334
I332
I330
I331
I356
I394
I408
I409
I410
I297
I294
X19 CONN
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
PP3V3_WLAN
PCIE_AP_D2R_PI_P
PCIE_AP_D2R_PI_N
PCIE_AP_R2D_P
PCIE_AP_R2D_N
PCIE_CLK100M_AP_CONN_P
PCIE_CLK100M_AP_CONN_N
PP3V3_S3RS4_BT_F
PCIE_WAKE_L
USB_BT_CONN_P
USB_BT_CONN_N
AP_CLKREQ_Q_L
AP_RESET_CONN_L
AP_TEMP_SMB_SDA_R
AP_TEMP_SMB_SCL_R
WIFI_EVENT_L_R
(NEED TO ADD 5 GND TP)
IPD_FLEX_CONN
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
PP3V3_S4
PP18V5_Z2
Z2_CS_L
Z2_DEBUG3
Z2_MOSI
Z2_MISO
Z2_SCLK
Z2_BOOST_EN
Z2_HOST_INTN
Z2_CLKIN
Z2_KEY_ACT_L
Z2_RESET
PSOC_MISO
PSOC_MOSI
PSOC_SCLK
SMBUS_SMC_2_S3_SCL
SMBUS_SMC_2_S3_SDA
PSOC_F_CS_L
PICKB_L
PP5V_S5_CUMULUS
(NEED TO ADD 2 GND TP)
KEYBOARD CONN
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
PP3V3_S4
PP3V42_G3H
WS_KBD1
WS_KBD2
WS_KBD3
WS_KBD4
WS_KBD5
WS_KBD6
WS_KBD7
WS_KBD8
WS_KBD9
WS_KBD10
WS_KBD11
WS_KBD12
WS_KBD13
WS_KBD14
WS_KBD15_CAP
WS_KBD16_NUM
WS_KBD17
WS_KBD18
WS_KBD19
WS_KBD20
WS_KBD21
WS_KBD22
WS_KBD23
WS_KBD_ONOFF_L
WS_LEFT_SHIFT_KBD
WS_LEFT_OPTION_KBD
WS_CONTROL_KBD
KBD BACKLIGHT CONN
TRUE
TRUE
KBDLED_ANODE
SMC_KDBLED_PRESENT_L
CAMERA/ALS CONN
TRUE
TRUE
TRUE
TRUE
TRUE
PP5V_S3_ALSCAMERA_F
SMBUS_SMC_2_S3_SCL
SMBUS_SMC_2_S3_SDA
USB_CAMERA_CONN_P
USB_CAMERA_CONN_N
(NEED 3 TP)
(NEED TO ADD 2 GND TP)
(NEED TO ADD 1 GND TP)
(NEED TO ADD 2 GND TP)
6
32 46
32 81
32 81
32 81
32 81
32 85
32 85
32
17 24 32
32 80
32 80
32
32
32
32
32
6 7
6
54
53 54
53 54
53 54
53 54
53 54
54
53 54
53 54
53 54
53 54
53 54
53 54
53 54
6
45 48 84
6
45 48 84
53 54
53 54
54
6 7
6 7
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
54
54
32
6
45 48 84
6
45 48 84
32 80
32 80
I287
I285
I414
I280
I281
I282
I283
I376
I278
I270
I416
I273
I274
I275
I417
I392
I391
I390
I388
I418
I386
I383
I419
I382
I565
I380
I598
I597
I596
I599
I600
I601
I602
I603
I604
I605
I606
I607
I608
I610
I611
I612
I614
I613
I617
I616
I618
I620
I619
I622
DEBUG VOLTAGE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
DC POWER CONN
I312
I304
TRUE
TRUE
PPVCORE_S0_CPU
PPVCORE_S0_AXG
PP1V2_S3_ENET_INTREG
PP1V05_S0
PP1V5_S3RS0
PP1V8_S0
PP3V3_S0
PP5V_S0
PP3V3_S3
PP5V_S3
PPVCCSA_S0_CPU
PP3V3_S5
PP3V42_G3H
PPBUS_G3H
PP3V3_ENET
PP3V3_WLAN
PP5V_SW_ODD
PP5V_S0_HDD_FLT
PP18V5_Z2
PP3V3_S0_LCD_F
PP3V3_LCDVDD_SW_F
PP4V5_AUDIO_ANALOG
PP1V5_S3
SMC_PM_G2_EN
PM_SLP_S4_L
PM_SLP_S3_L
(NEED TO ADD 6 GND TP)
(NEED 3 TP)
PP18V5_DCIN_FUSE
ADAPTER_SENSE
(NEED TO ADD 4 GND TP)
7
7
71
7
7
85
7
7
85
6 7
7
7
7
16
7
85
16
6 7
16
7
7
6
32 46
6
41
6
41
6
54
6
74
6
74
57 62
7
45 73
17 26 32 45 73
8
17 26 45 73
63
63
18
18
LPC+SPI DEBUG_CONN
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
LPC_AD<0>
LPC_AD<1>
LPC_AD<2>
LPC_AD<3>
LPC_CLK33M_LPCPLUS
LPC_FRAME_L
LPC_PWRDWN_L
LPC_SERIRQ
LPCPLUS_GPIO
LPCPLUS_RESET_L
PM_CLKRUN_L
PP3V42_G3H
PP5V_S0
SMC_RX_L
SMC_TCK
SMC_TDI
SMC_TDO
SMC_TMS
SMC_TX_L
SPI_ALT_CLK
SPI_ALT_CS_L
SPI_ALT_MISO
SPI_ALT_MOSI
SPIROM_USE_MLB
(NEED TO ADD 2 GND TP)
16 45 47 81
16 45 47 81
16 45 47 81
16 45 47 81
24 47 81
16 45 47 81
17 45 47
16 45 47
19 47
24 47
17 45 47
6 7
6 7
45 46 47
45 46 47
45 46 47
45 46 47
45 46 47
45 46 47
47
47
47
47
19 47 56
TP_SDVO_TVCLKINN
17
TP_SDVO_TVCLKINP
17
TP_SDVO_STALLN
17
TP_SDVO_STALLP
17
TP_SDVO_INTN
17
TP_SDVO_INTP
17
NO_TEST
TP_CRT_IG_BLUE
17
TP_CRT_IG_GREEN
17
TP_CRT_IG_RED
17
TP_CRT_IG_DDC_CLK
17
TP_CRT_IG_DDC_DATA
17
TP_CRT_IG_HSYNC
17
TP_CRT_IG_VSYNC
17
TP_LVDS_IG_CTRL_CLK
17
TP_LVDS_IG_CTRL_DATA
17
TP_PCH_LVDS_VBG
17
TP_HDA_SDIN2
TP_HDA_SDIN3
TP_PCI_PME_L
TP_PCI_CLK33M_OUT3
TP_CLINK_CLK
16
TP_CLINK_DATA
16
TP_CLINK_RESET_L
16
TP_PCIE_CLK100M_PEBN
16
TP_PCIE_CLK100M_PEBP
16
TP_FW643_SDA
38
TP_FW643_SM
38
TP_FW643_TCK
38
TP_FW643_TMS
38
TP_FW643_FW620_L
38
TP_FW643_VBUF
38
TP_FW643_OCR10_CTL
38
TP_FW643_AVREG
38
TP_FW643_TDI
38
TP_XDP_PCH_OBSFN_A<0..1>
23
TP_XDP_PCH_OBSFN_B<0..1>
23
TP_XDPPCH_HOOK2
23
TP_XDPPCH_HOOK3
23
TP_XDP_PCH_OBSFN_D<0..1>
23
TP_XDP_PCH_HOOK4
23
TP_XDP_PCH_HOOK5
23
TP_PCH_GPIO64_CLKOUTFLEX0
16
TP_PCH_GPIO65_CLKOUTFLEX1
16
TP_PCH_GPIO66_CLKOUTFLEX2
16
TP_PCH_GPIO67_CLKOUTFLEX3
16
I500
I499
I498
I497
I495
I496
I494
I493
I492
I491
I581
I580
I582
I583
I584
I585
I586
I588
I587
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
NO_TEST
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
NC NO_TESTs
NC_FW2_TPBP
NC_FW2_TPBN
NC_FW2_TPBIAS
NC_FW2_TPAP
NC_FW2_TPAN
NC_FW0_TPBP
NC_FW0_TPBN
NC_FW0_TPAP
XDP_PCH_AP_PWR_EN
XDP_PCH_USB_HUB_SOFT_RST_L
XDP_PCH_SDCONN_STATE_RST_L
XDP_PCH_ENET_PWR_EN
XDP_PCH_SDCONN_DET_L
XDP_PCH_S5_PWRGD
XDP_PCH_PWRBTN_L
XDP_PCH_ISOLATE_CPU_MEM_L
XDP_FW_CLKREQ_L
XDP_AP_CLKREQ_L
XDP_PCH_AUD_IPHS_SWITCH_EN
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
NC_LVDS_IG_CTRL_CLK
TRUE
MAKE_BASE=TRUE
NC_LVDS_IG_CTRL_DATA
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
NC_CRT_IG_BLUE
NC_CRT_IG_GREEN
NC_CRT_IG_RED
NC_CRT_IG_DDC_CLK
NC_CRT_IG_DDC_DATA
NC_CRT_IG_HSYNC
NC_CRT_IG_VSYNC
NC_PCH_LVDS_VBG
NC_HDA_SDIN1TP_HDA_SDIN1
NC_HDA_SDIN2
NC_HDA_SDIN3
NC_PCI_PME_L
NC_PCI_CLK33M_OUT3
NC_CLINK_CLK
NC_CLINK_DATA
NC_CLINK_RESET_L
NC_PCIE_CLK100M_PEBN
NC_PCIE_CLK100M_PEBP
NC_FW643_SDA
NC_FW643_SM
NC_FW643_TCK
NC_FW643_TMS
NC_FW643_FW620_L
NC_FW643_VBUF
NC_FW643_OCR10_CTL
NC_FW643_AVREG
NC_FW643_TDI
NC_TP_XDP_PCH_OBSFN_A<0..1>
NC_TP_XDP_PCH_OBSFN_B<0..1>
NC_TP_XDPPCH_HOOK2
NC_TP_XDPPCH_HOOK3
NC_TP_XDP_PCH_OBSFN_D<0..1>
NC_TP_XDP_PCH_HOOK4
NC_TP_XDP_PCH_HOOK5
NC_PCH_GPIO64_CLKOUTFLEX0
NC_PCH_GPIO65_CLKOUTFLEX1
NC_PCH_GPIO66_CLKOUTFLEX2
NC_PCH_GPIO67_CLKOUTFLEX3
40
40
40
40
40
40
40
40
23
23
NC_SDVO_TVCLKINN
NC_SDVO_TVCLKINP
NC_SDVO_STALLN
NC_SDVO_STALLP
NC_SDVO_INTN
NC_SDVO_INTP
MAKE_BASE=TRUE
NC_EDP_TXN<0..3>
MAKE_BASE=TRUE
NC_EDP_AUXP
MAKE_BASE=TRUE
NC_EDP_AUXN
MAKE_BASE=TRUE
NC_CPU_THERMDA
MAKE_BASE=TRUE
NC_CPU_THERMDC
MAKE_BASE=TRUE
NC_CPU_RSVD<30..45>
MAKE_BASE=TRUE
NC_CPU_RSVD<8..27>
MAKE_BASE=TRUE
NC_PEG_R2D_CP<0..7>
MAKE_BASE=TRUE
NC_PEG_R2D_CN<0..7>
MAKE_BASE=TRUE
NC_PEG_D2RP<0..7>
MAKE_BASE=TRUE
NC_PEG_D2RN<0..7>
MAKE_BASE=TRUE
NC_PEG_R2D_CP<8..11>
MAKE_BASE=TRUE
NC_PEG_R2D_CN<8..11>
MAKE_BASE=TRUE
NC_PEG_D2RP<8..11>
MAKE_BASE=TRUE
NC_PEG_D2RN<8..11>
MAKE_BASE=TRUE
TP_PCIE_CLK100M_PE4N
16
TP_PCIE_CLK100M_PE4P
16
TP_PCIE_CLK100M_PE5N
16
TP_PCIE_CLK100M_PE5P
16
TP_PCIE_CLK100M_PE6N
TP_PCIE_CLK100M_PE6P
TP_PCIE_CLK100M_PE7N
TP_PCIE_CLK100M_PE7P
TP_PSOC_P1_3
53
TP_SATA_C_D2RN
16
TP_SATA_C_D2RP
16
TP_SATA_C_R2D_CN
16
TP_SATA_C_R2D_CP
16
TP_SATA_D_D2RN
16
TP_SATA_D_D2RP
16
TP_SATA_D_R2D_CN
16
TP_SATA_D_R2D_CP
16
TP_SATA_E_D2RN
16
TP_SATA_E_D2RP
16
TP_SATA_E_R2D_CN
16
TP_SATA_E_R2D_CP
16
TP_SATA_F_D2RN
16
TP_SATA_F_D2RP
16
TP_SATA_F_R2D_CN
16
TP_SATA_F_R2D_CP
16
TP_TBT_MONDC0
33
TP_TBT_MONDC1
33
TP_TBT_MONOBSP
33
TP_TBT_MONOBSN
33
TP_DP_T29SRC_ML_CP<0..3>
33
TP_DP_T29SRC_ML_CN<0..3>
33
TP_DP_T29SRC_AUXCH_CP
33
TP_DP_T29SRC_AUXCH_CN
33
TP_T29_PCIE_RESET0_L
6
33
TP_T29_PCIE_RESET1_L
6
33
TP_T29_PCIE_RESET2_L
6
33
TP_T29_PCIE_RESET3_L
6
33
PCH_VSS_NCTF<1>
TRUE
I522
I521
I520
I519
I518
I517
PCH_VSS_NCTF<2>
TRUE
PCH_VSS_NCTF<5>
TRUE
PCH_VSS_NCTF<9>
TRUE
PCH_VSS_NCTF<11>
TRUE
PCH_VSS_NCTF<12>
TRUE
TP_LVDS_IG_B_CLKN
8
TP_LVDS_IG_B_CLKP
8
TP_LVDS_IG_BKL_PWM
SMC_BS_ALRT_L
SYNC_MASTER=K90I_MLB
PAGE TITLE
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
Apple Inc.
R
6 3
TP_EDP_TX_P<0..3>
TP_EDP_TX_N<0..3>
TP_EDP_AUX_P
TP_EDP_AUX_N
TP_CPU_THERMDA
TP_CPU_THERMDC
TP_CPU_RSVD<30..45>
TP_CPU_RSVD<8..27>
=PEG_R2D_C_P<0..7>
=PEG_R2D_C_N<0..7>
=PEG_D2R_P<0..7>
=PEG_D2R_N<0..7>
=PEG_R2D_C_P<8..11>
=PEG_R2D_C_N<8..11>
=PEG_D2R_P<8..11>
=PEG_D2R_N<8..11>
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
I547
81
I546
81
I545
81
I544
I543
81
I542
81
I541
81
I540
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
FUNC TEST
NC_PCIE_CLK100M_PE4N
NC_PCIE_CLK100M_PE4P
NC_PCIE_CLK100M_PE5N
NC_PCIE_CLK100M_PE5P
NC_PCIE_CLK100M_PE6N
NC_PCIE_CLK100M_PE6P
NC_PCIE_CLK100M_PE7N
NC_PCIE_CLK100M_PE7P
NC_PSOC_P1_3
NC_SATA_C_D2RN
NC_SATA_C_D2RP
NC_SATA_C_R2D_CN
NC_SATA_C_R2D_CP
NC_SATA_D_D2RN
NC_SATA_D_D2RP
NC_SATA_D_R2D_CN
NC_SATA_D_R2D_CP
NC_SATA_E_D2RN
NC_SATA_E_D2RP
NC_SATA_E_R2D_CN
NC_SATA_E_R2D_CP
NC_SATA_F_D2RN
NC_SATA_F_D2RP
NC_SATA_F_R2D_CN
NC_SATA_F_R2D_CP
NC_TBT_MONDC0
NC_TBT_MONDC1
NC_TBT_MONOBSP
NC_TBT_MONOBSN
NC_DP_T29SRC_ML_CP<0..3>
NC_DP_T29SRC_ML_CN<0..3>
NC_DP_T29SRC_AUXCH_CP
NC_DP_T29SRC_AUXCH_CN
TP_T29_PCIE_RESET0_L
TP_T29_PCIE_RESET1_L
TP_T29_PCIE_RESET2_L
TP_T29_PCIE_RESET3_L
PCH_VSS_NCTF<15>
TRUE
PCH_VSS_NCTF<17>
TRUE
PCH_VSS_NCTF<19>
TRUE
PCH_VSS_NCTF<19>
TRUE
PCH_VSS_NCTF<21>
TRUE
PCH_VSS_NCTF<25>
TRUE
PCH_VSS_NCTF<27>
TRUE
PCH_VSS_NCTF<29>
TRUE
NC_LVDS_IG_B_CLKN
NC_LVDS_IG_B_CLKP
NC_LVDS_IG_BKL_PWM
NC_SMC_BS_ALRT_L
DRAWING NUMBER
051-9058
REVISION
6.0.0
BRANCH
PAGE
7 OF 109
SHEET
6 OF 86
124578
9
9
9
9
D
9
9
9
9
9
9
9
9
C
6
33
6
33
B
6
33
6
33
81
81
6
81
6
81
81
81
81
81
A
SIZE
D
8 7 6 5 4 3
=PPBUS_G3H
63 64
PPVIN_SW_T29BST
35
VOLTAGE=12.8V
=PPVIN_S5_HS_COMPUTING_ISNS
50
D
=PPVIN_S5_HS_OTHER_ISNS
50
=PP18V5_DCIN_CONN
63
=PP3V42_G3H_REG
63
C
=PPVRTC_G3_OUT
24
=PP5V_S5_LDO
66
=PP5V_SUS_FET
72
B
=PP5V_S3_REG
66
=PP5V_S0_FET
72
A
=PP5V_S0_HDD_ISNS
49
"G3Hot" (Always-Present) Rails
PPBUS_G3H
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=12.8V
MAKE_BASE=TRUE
=PPBUS_S0_LCDBKLT
=PPBUS_S5_FWPWRSW
=PPBUS_S0_VSENSE
=PPVIN_SW_T29BST
=PPVIN_S5_HS_COMPUTING_ISNS_R
=PPVIN_S5_HS_OTHER_ISNS_R
PPBUS_S5_HS_COMPUTING_ISNS
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=12.8V
MAKE_BASE=TRUE
=PPVIN_S0_CPUIMVP
=PPVIN_S3_DDRREG
=PPVIN_S0_CPUVCCIOS0
=PPVIN_S0_VCCSAS0
=PPVIN_S0_CPUAXG
PPBUS_S5_HS_OTHER_ISNS
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=12.8V
MAKE_BASE=TRUE
=PPVIN_S5_5VS3
=PPVIN_S5_3V3S5
PPDCIN_G3H
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 MM
VOLTAGE=18.5V
MAKE_BASE=TRUE
=PPDCIN_S5_CHGR
=PPDCIN_S5_VSENSE
PP3V42_G3H
MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.42V
MAKE_BASE=TRUE
=PP3V3_S5_LPCPLUS
=PP3V3_S5_SMC
=PP3V42_G3H_BATT
=PP3V42_G3H_CHGR
=PP3V42_G3H_ONEWIREPROT
=PP3V42_G3H_PWRCTL
=PP3V42_G3H_SMBUS_SMC_BSA
=PP3V42_G3H_SMCUSBMUX
=PP3V42_G3H_TPAD
=PPVIN_S5_SMCVREF
=PPVBAT_G3_SYSCLK
=PP3V42_G3H_AUDIO
PPVRTC_G3H
MIN_LINE_WIDTH=0.2 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3V
MAKE_BASE=TRUE
=PPVRTC_G3_PCH
5V Rails
PP5V_S5
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=5V
MAKE_BASE=TRUE
=PP5V_S5_P1V5DDRFET
=PP5V_S5_TPAD
=PP5V_S5_P5VSUSFET
PP5V_SUS
MIN_LINE_WIDTH=0.50MM
MIN_NECK_WIDTH=0.20MM
VOLTAGE=3.3V
MAKE_BASE=TRUE
=PP5V_SUS_PCH
PP5V_S3
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=5V
MAKE_BASE=TRUE
=PP5V_S3_ALSCAMERA
=PP5V_S3_AUDIO
=PP5V_S3_AUDIO_AMP
=PP5V_S3_DDRREG
=PP5V_S3_IR
=PP5V_S3_MEMRESET
=PP5V_S3_ODD
=PP5V_S3_P5VS0FET
=PP5V_S3_USB
=PP5V_S3_SYSLED
PP5V_S0
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=5V
MAKE_BASE=TRUE
=PP5V_S0_BKL
=PP5V_S0_CPUIMVP
=PP5V_S0_CPUVCCIOS0
=PP5V_S0_FAN_RT
=PP5V_S0_HDD_ISNS_R
=PP5V_S0_KBDLED
=PP5V_S0_LPCPLUS
=PP5V_S0_VCCSAS0
=PP5V_S0_PCH
=PP5V_S0_VMON
=PP5V_S0_ISNS
=PP5V_S0_AUDIO
PP5V_S0_HDD
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.4MM
VOLTAGE=5V
MAKE_BASE=TRUE
=PP5V_S0_HDD
=PP3V3_S5_REG
66
6
77
39
50
8
35
50 39
50
68 69
67
70
65
69
=PP3V3_SUS_FET
72
66
66
64
50
6
=PP3V3_S4_FET
72
47
45 46
63
64
63
73
48
42
53
46
24
58
16 17 20
72
54
72
22
6
32
57
60
67
41 44
26
41
72
42
46
6
77
68 69
70
52
49
54
47
65
22 24
73
49
41
=PP3V3_S3_FET
72
=PP3V3_S0_FET
72
3.3V Rails
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
MIN_LINE_WIDTH=0.50MM
MIN_NECK_WIDTH=0.20MM
MIN_LINE_WIDTH=0.50MM
MIN_NECK_WIDTH=0.20MM
MIN_LINE_WIDTH=0.50MM
MIN_NECK_WIDTH=0.20MM
=PP3V3_S3_USB_HUB
=PP3V3_S0_KBDLED
=PP3V3_S0_VMON
PP3V3_S5
=PP3V3_S5_XDP
=PP3V3_S0_P3V3S0FET
=PP3V3_S3_P3V3S3FET
=PP3V3_S5_CPU_VCCDDR
=PP3V3_S4_P3V3S4FET
=PP3V3_S5_LCD
=PP3V3_S5_PCH
=PP3V3_S5_PCHPWRGD
=PP3V3_S5_SMCBATLOW
=PP3V3_S5_PCH_VCCDSW
=PP3V3_S5_SYSCLK
=PP3V3_S5_VMON
=PP3V3_S5_PWRCTL
=PP3V3_S5_P3V3SUSFET
=PP3V3_S4_TBTAPWRSW
=PP3V3_S5_PCH_GPIO
PP3V3_SUS
=PP3V3_SUS_PCH_VCCSUS_USB
=PP3V3_SUS_PCH_VCCSUS_GPIO
=PP3V3_SUS_PCH_VCCSUS
=PP3V3_SUS_PCH_GPIO
=PP3V3_SUS_PCH
=PP3V3_SUS_PWRCTL
=PP3V3_SUS_P1V05SUSLDO
=PP3V3_SUS_SMC
=PP3V3_SUS_ROM
=PP3V3_SUS_PCH_VCC_SPI
PP3V3_S4
=PP3V3_S4_TPAD
=PP3V3_S4_SMC
=PP3V3_S4_SD_HPD
=PP3V3_S4_BT
PP3V3_S3
=PP3V3_S3_BT
=PP3V3_S3_MEMRESET
=PP3V3_S3_SMBUS_SMC_A_S3
=PP3V3_S3_SMBUS_SMC_MGMT
=PP3V3_S3_SMS
=PP3V3_S3_USB_RESET
=PP3V3_S3_VREFMRGN
=PP3V3_S3_WLAN
=PP3V3_S3_SDBUF
=PP3V3_S3_P3V3ENETFET
=PP3V3_S3_PCH_GPIO
=PP3V3_S3_ISNS
=PP3V3_S3_USBMUX
PP3V3_S0
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.20MM
=PP3V3_S0_HDD
=PP3V3_S0_AUDIO
=PP3V3_S0_BKL_VDDIO
=PP3V3_S0_ISNS
=PP3V3_S0_HS_COMPUTING_ISNS
=PP3V3_S0_CPUTHMSNS
=PP3V3_S0_LCD
=PP3V3_S0_DP_DDC
=PP3V3_S0_ENETPHY
=PP3V3_S0_FAN_RT
=PP3V3_S0_FWPWRCTL
=PP3V3_S0_FWLATEVG
=PP3V3_S0_P3V3T29FET
=PP3V3_S0_SDCARD
=PP3V3_S0_P1V8S0
=PP3V3_S0_ODD
=PP3V3_FW_P3V3FWFET
=PP3V3_S0_PCH
=PP3V3_S0_PCH_GPIO
=PP3V3_S0_PCH_VCC3_3_CLK
=PP3V3_S0_PCH_VCC3_3_GPIO
=PP3V3_S0_PCH_VCC3_3_HVCMOS
=PP3V3_S0_PCH_VCC3_3_PCI
=PP3V3_S0_PCH_VCC3_3_SATA
=PP3V3_S0_PCH_VCCADAC
=PP3V3_S0_PCH_VCCA_LVDS
=PP3V3_S0_PWRCTL
=PP3V3_S0_RSTBUF
=PP3V3_S0_SB_PM
=PP3V3_S0_SMBUS_PCH
=PP3V3_S0_SMBUS_SMC_0_S0
=PP3V3_S0_SMBUS_SMC_B_S0
=PP3V3_S0_SMC
=PPSPD_S0_MEM_A
=PPSPD_S0_MEM_B
=PP3V3_S0_P1V5S0
=PP3V3_S0_T29PWRCTL
=PP3V3_S0_HS_OTHER_ISNS
=PP3V3_S0_DPSDRVA
=PP3V3_S0_P1V05S0LDO
=PP3V3_S0_IMVPISNS
=PP3V3_S0_XDP
=PP3V3_S0_T29I2C
VOLTAGE=3.3V
MAKE_BASE=TRUE
VOLTAGE=3.3V
MAKE_BASE=TRUE
VOLTAGE=3.3V
MAKE_BASE=TRUE
VOLTAGE=3.3V
MAKE_BASE=TRUE
VOLTAGE=3.3V
MAKE_BASE=TRUE
6
85
23
72
72
26
72
74
17
24
46
20 22
24
73
73
72
76
19
20 22
20 22
20
16 17 18 19
22
73
71
46
56
20 22
6
53 54
46
30
32
6
32
26
48
48
55
25
25
31
32
24
73
18 24
49
25
6
85
41
57 61 62
77
49
50
51
74
8
36
52
39
39 40
35
30
71
41
39
16 22
16 17 18 19 30
22
20 22
20 22
20 22
20 22
22
20
73
24
24
48
48
48
41
54
73
27
29
71
35
50
75
71
49
23
48
=PP1V8_S0_REG
71
2A max supply
=PP1V5_S3_DDR_ISNS
49
=PPDDR_S3_REG
67
=PP1V5_S3RS0_FET
72
=PP1V5_S0_REG
71
=PPVTT_S3_DDR_BUF
31 67
=PPVTT_S0_DDR_LDO
67
=PPVCCSA_S0_REG
65
=PP1V05_SUS_LDO
71
=PPCPUVCCIO_S0_REG
70
? mA
=PP3V3_ENET_FET
73
1.8V/1.5V/1.2V/1.05V Rails
PP1V8_S0
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.8V
MAKE_BASE=TRUE
=PP1V8_S0_CPU_VCCPLL
=PP1V8_S0_PCH_VCCTX_LVDS
=PP1V8_S0_PCH_VCC_DFTERM
=PP1V8_S0_P1V05S0LDO
=PP1V8R1V5_S0_PCH_VCCVRM
=PPVDDIO_S0_SBCLK
PP1V5_S3_DDR
MIN_LINE_WIDTH=0.8 MM
MIN_NECK_WIDTH=0.1 MM
VOLTAGE=1.5V
MAKE_BASE=TRUE
=PP1V5_S3_MEMRESET
=PP1V5_S3_MEM_A
=PP1V5_S3_MEM_B
=PPVIN_S0_DDRREG_LDO
=PPDDR_S3_MEMVREF
PP1V5_S3
MIN_LINE_WIDTH=0.8 MM
MIN_NECK_WIDTH=0.1 MM
VOLTAGE=1.5V
MAKE_BASE=TRUE
=PP1V5_S3_P1V5S3RS0_FET
=PP1V5_S3_DDR_ISNS_R
PP1V5_S3RS0
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.5V
MAKE_BASE=TRUE
=PP1V5_S3_CPU_VCCDDR
PP1V5_S0
MIN_LINE_WIDTH=2 mm
MIN_NECK_WIDTH=0.17 mm
VOLTAGE=1.5V
MAKE_BASE=TRUE
=PP1V5_S0_RDRVR
=PP1V8R1V5_S0_AUDIO
=PP3V3R1V5_S0_AUDIO
=PP3V3R1V5_S0_PCH_VCCSUSHDA
=PP1V5_S0_VMON
PPVTTDDR_S3
MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=0.75V
MAKE_BASE=TRUE
PP0V75_S0_DDRVTT
MIN_LINE_WIDTH=2 mm
MIN_NECK_WIDTH=0.17 mm
VOLTAGE=0.75V
MAKE_BASE=TRUE
=PP0V75_S0_MEM_VTT_A
=PP0V75_S0_MEM_VTT_B
=PPVTT_S0_VTTCLAMP
PPVCCSA_S0_CPU
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=0.9V
MAKE_BASE=TRUE
=PPVCCSA_S0_CPU
PP1V05_SUS
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
MAKE_BASE=TRUE
=PP1V05_SUS_PCH_JTAG
PP1V05_S0
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1V
MAKE_BASE=TRUE
=PP1V05_S0_CPU_VCCIO
=PPVCCIO_S0_CPUIMVP
=PPVCCIO_S0_XDP
=PPVCCIO_S0_SMC
=PP1V05_S0_FWPWRCTL
=PP1V05_FW_P1V0FWFET
=PP1V05_S0_VMON
XW0800
SM
XW0801
SM
21
21
ENET Rails
=PP1V05_S0_P1V05T29FET
PP1V05_S0_PCH
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1V
MAKE_BASE=TRUE
=PP1V05_S0_PCH_VCCIO_PLLPCIE
=PP1V05_S0_PCH
=PP1V05_S0_PCH_VCCIO
=PP1V05_S0_PCH_VCCIO_PCIE
=PP1V05_S0_PCH_VCCIO_SATA
=PP1V05_S0_PCH_VCCASW
=PP1V05_S0_PCH_VCCIO_USB
=PP1V05_S0_PCH_VCC_CORE
=PP1V05_S0_PCH_VCCIO_CLK
=PP1V05_S0_PCH_VCCDIFFCLK
=PP1V05_S0_PCH_VCCSSC
=PP1V05_S0_PCH_V_PROC_IO
=PP1V05_S0_PCH_VCCIO_PLLUSB
=PP1V05_S0_PCH_VCC_DMI
=PP1V05_S0_PCH_VCCIO_PLLFDI
=PP1V05_S0_PCH_VCCDMI_FDI
PP3V3_ENET
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V
MAKE_BASE=TRUE
=PP3V3_ENET_PHY
=PP3V3_ENET_SYSCLK
=PPVDDIO_ENET_CLK
6
14
22
19 20 22
71
20
24
26
27
29
67
31
6
72
49
6
85
10 12 15 26
41
57
57
20 22 24
73
27
29
26
6
12 15
23
6
9
10 12 14
68
23
46
39
39
73
35
20
16 22
20 22
17
16 20 22
20 22
20 22
20 22
20 22
16 20 22
20 22
20 22
20
20 22
20
20
6
24 36 71
24
24
=PPBUS_FW_FET
39
=PP3V3_FW_FET
=PP1V0_FW_FET_R
39
=PP15V_T29_REG
8
35
=PP3V3_T29_FET
35
=PP1V05_T29_FET
35
=PP1V05_S0_LDO
71
=PPVCORE_S0_CPU_REG
69
=PPVCORE_S0_AXG_REG
69
=PP1V5_S3_CPU_VCCDQ
12 15
=PP1V05_S0_CPU_VCCPQE
8
12 14
=PP1V8_S0_CPU_VCCPLL_R
12 14
"FW" (FireWire) Rails
PPVP_FW
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=12.8V
MAKE_BASE=TRUE
=PPVP_FW_PORT1
=PPVP_FW_PHY_CPS_FET
PP3V3_FW_FWPHY
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V
MAKE_BASE=TRUE
=PP3V3_FW_FWPHY
=PP3V3_S0_P1V05FWFET
PP1V0_FW_FWPHY
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.0V
MAKE_BASE=TRUE
=PP1V0_FW_FWPHY
T29 Rails (off when no cable)
PP15V_T29
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=17.8V
MAKE_BASE=TRUE
=PPHV_SW_TBTAPWRSW
PP3V3_T29
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V
MAKE_BASE=TRUE
=PPVDDIO_T29_CLK
=PP3V3_T29_RTR
=PP3V3_T29_PCH_GPIO
PP1V05_T29
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
MAKE_BASE=TRUE
=PP1V05_T29_RTR
1V05 S0 LDO
PP1V05_S0_PCH_VCCADPLL
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
MAKE_BASE=TRUE
=PP1V05_S0_PCH_VCCADPLL
Chipset "VCore" Rails
SYNC_MASTER=K90I_MLB
PAGE TITLE
PPVCORE_S0_CPU
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 MM
VOLTAGE=1.25V
MAKE_BASE=TRUE
=PPVCORE_S0_CPU
=PPCPUVCORE_S0_VSENSE
PPVCORE_S0_AXG
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
MAKE_BASE=TRUE
=PPVCORE_S0_CPU_VCCAXG
=PPAXGVCORE_S0_VSENSE
PP1V5_S3_CPU_VCCDQ
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.5V
MAKE_BASE=TRUE
PP1V05_S0_CPU_VCCPQE
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
MAKE_BASE=TRUE
PP1V8_S0_CPU_VCCPLL_R
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.8V
MAKE_BASE=TRUE
Power Aliases
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
6 3
12
40
40
38 39 40
38 39
76
24
33 34 35
16 19
35
34
22
SYNC_DATE=02/15/2011
DRAWING NUMBER
051-9058
REVISION
6.0.0
BRANCH
PAGE
8 OF 109
SHEET
7 OF 86
124578
D
C
6
9
12 14
49
B
6
9
12 15
49
A
SIZE
D
8 7 6 5 4 3
CPU signals
HEATSINK STANDOFFS
STDOFF-4.5OD.98H-1.1-3.48-TH
D
STDOFF-4.5OD.98H-1.1-3.48-TH
Z0902
1
Z0904
1
BELOW CPU
Z0920
STDOFF-4.5OD.98H-1.1-3.48-TH
1
LEFT OF CPU
FAN STANDOFF
STDOFF-4.5OD.98H-1.1-3.48-TH
Z0905
1
MLB MOUNTING (TO C. BRACKET) SCREW HOLES
OMIT
Z0906
3R2P5
1
OMIT
Z0907
3R2P5
1
MEMVTT_EN
26
MAKE_BASE=TRUE
DP_EXTA_ML_C_P<3..0>
75 81
MAKE_BASE=TRUE
DP_EXTA_ML_C_N<3..0>
75 81
MAKE_BASE=TRUE
DP_EXTA_AUXCH_C_P
75 81
MAKE_BASE=TRUE
DP_EXTA_AUXCH_C_N
75 81
MAKE_BASE=TRUE
FW_PLUG_DET_L
MAKE_BASE=TRUE
FW643_WAKE_L
39
MAKE_BASE=TRUE
16
16
16
16
16 81
16 81
16 81
16 81
TP_SMC_EXCARD_PWR_EN
MAKE_BASE=TRUE
PCIE_EXCARD_D2R_N
PCIE_EXCARD_D2R_P
PCIE_EXCARD_R2D_C_N
PCIE_EXCARD_R2D_C_P
PCIE_CLK100M_EXCARD_N
PCIE_CLK100M_EXCARD_P
PCIE_PCH_D2R_N<5..8>
PCIE_PCH_D2R_P<5..8>
PCIE_PCH_R2D_C_N<5..8>
PCIE_PCH_R2D_C_P<5..8>
PEG_CLK100M_P
PEG_CLK100M_N
MLB MOUNTING (TO TOPCASE) SCREW HOLES
OMIT
Z0908
3R2P5
C
1
OMIT
Z0911
3R2P5
1
OMIT
Z0909
3R2P5
1
OMIT
Z0912
3R2P5
1
OMIT
Z0910
3R2P5
1
TP_PCH_CLKOUT_DPN
16
TP_PCH_CLKOUT_DPP
16
=DDRVTT_EN
TP_DP_IG_B_MLP<3..0>
TP_DP_IG_B_MLN<3..0>
DPA_IG_AUX_CH_P
DPA_IG_AUX_CH_N
FW_PME_L
=FW_PME_L
SMC_EXCARD_PWR_EN
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
26 67
17
17
17
17
NC_PCIE_EXCARD_D2RN
NC_PCIE_EXCARD_D2RP
NC_PCIE_EXCARD_R2D_CN
NC_PCIE_EXCARD_R2D_CP
NC_PCIE_CLK100M_EXCARDN
TRUE
MAKE_BASE=TRUE
NC_PCIE_CLK100M_EXCARDP
TRUE
MAKE_BASE=TRUE
NC_PCIE_PCH_D2RN<5..8>
NC_PCIE_PCH_D2RP<5..8>
NC_PCIE_PCH_R2D_CN<5..8>
NC_PCIE_PCH_R2D_CP<5..8>
NC_PEG_CLK100MP
NC_PEG_CLK100MN
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
NC_PCH_CLKOUT_DPN
NC_PCH_CLKOUT_DPP
19 39
38 39
17
17
=PEG_R2D_C_P<12..15>
9
=PEG_R2D_C_N<12..15>
9
=PEG_D2R_P<12..15>
9
=PEG_D2R_N<12..15>
9
TP_DP_IG_C_CTRL_CLK
TP_DP_IG_C_CTRL_DATA
TP_DP_IG_D_CTRL_CLK
TP_DP_IG_D_CTRL_DATA
PPBUS_SW_LCDBKLT_PWR
77
MAKE_BASE=TRUE
NC_CPU_VCCIO_SEL
MAKE_BASE=TRUE
DP_EXTA_DDC_CLK
75
MAKE_BASE=TRUE
DP_EXTA_DDC_DATA
MAKE_BASE=TRUE
DP_EXTA_HPD
75
MAKE_BASE=TRUE
7 8
NO_TEST=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
=PP3V3_S0_DP_DDC
R0920
2.2K
5%
1/16W
MF-LF
402
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
1
R0908
100K
5%
1/16W
MF-LF
402
2
R0910
1/16W
MF-LF
PCIE_T29_R2D_C_P<3..0>
PCIE_T29_R2D_C_N<3..0>
PCIE_T29_D2R_P<3..0>
PCIE_T29_D2R_N<3..0>
1
2
1
R0921
2.2K
5%
1/16W
MF-LF
402
2
DPB_IG_DDC_CLK
DPB_IG_DDC_DATA
DP_IG_D_CTRL_CLK
DP_IG_D_CTRL_DATA
7 8
DPA_IG_DDC_CLK
DPA_IG_DDC_DATA
DPA_IG_HPD
0
21
5%
402
CPU_VCCIO_SEL
1
R0922
2.2K
1/16W
MF-LF
R0923
5%
402
2
=PP3V3_S0_DP_DDC
1
2.2K
1/16W
MF-LF
R0925
5%
402
2
R0924
PPBUS_SW_BKL
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.375 MM
VOLTAGE=12.6V
MAKE_BASE=TRUE
=PPBUS_SW_BKL
2.2K
1/16W
MF-LF
2.2K
1/16W
MF-LF
33 81
33 81
33 81
33 81
1
5%
402
2
17
17
1
5%
402
2
17
17 75
17
77
12 78
DPB_IG_HPD
17
TP_DP_IG_C_MLP<3..0>
17
TP_DP_IG_C_MLN<3..0>
17
DPB_IG_AUX_CH_P
17
DPB_IG_AUX_CH_N
17
TP_DP_IG_D_HPD
17
TP_DP_IG_D_MLP<3..0>
17
TP_DP_IG_D_MLN<3..0>
17
TP_DP_IG_D_AUXP
17
TP_DP_IG_D_AUXN
17
NC_BCM57765_CE_L_MS_INS_L
MAKE_BASE=TRUE
TP_LVDS_IG_B_CLKP
6
MAKE_BASE=TRUE
TP_LVDS_IG_B_CLKN
6
MAKE_BASE=TRUE
NC_LVDS_IG_B_DATAP<0..3>
MAKE_BASE=TRUE
NC_LVDS_IG_B_DATAN<0..3>
MAKE_BASE=TRUE
NC_LVDS_IG_A_DATAP<3>
MAKE_BASE=TRUE
NC_LVDS_IG_A_DATAN<3>
MAKE_BASE=TRUE
LVDS_DDC_CLK
6
74
MAKE_BASE=TRUE
LVDS_DDC_DATA
6
74
MAKE_BASE=TRUE
LCD_BKLT_PWM
77
MAKE_BASE=TRUE
LCD_IG_PWR_EN
74
MAKE_BASE=TRUE
LCD_BKLT_EN
77
MAKE_BASE=TRUE
T29 DP Ports
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
DP_T29SNK0_HPD
DP_T29SNK0_ML_C_P<3..0>
DP_T29SNK0_ML_C_N<3..0>
DP_T29SNK0_AUXCH_C_P
DP_T29SNK0_AUXCH_C_N
DP_T29SNK1_HPD
DP_T29SNK1_ML_C_P<3..0>
DP_T29SNK1_ML_C_N<3..0>
DP_T29SNK1_AUXCH_C_P
DP_T29SNK1_AUXCH_C_N
BCM57765_CE_L_MS_INS_L
LVDS_IG_B_CLK_P
LVDS_IG_B_CLK_N
LVDS_IG_B_DATA_P<0..3>
LVDS_IG_B_DATA_N<0..3>
LVDS_IG_A_DATA_P<3>
LVDS_IG_A_DATA_N<3>
LVDS_IG_DDC_CLK
LVDS_IG_DDC_DATA
LVDS_IG_BKL_PWM
LVDS_IG_PANEL_PWR
LVDS_IG_BKL_ON
12
33
33 83
33 83
33 83
33 83
33
D
33 83
33 83
33 83
33 83
17 80
17 80
17 80
17 80
17 80
17 80
17
17
17
17
17
C
USB Signals
NC_USB3_EXTD_TXN
=PPVIN_SW_T29BST
7
35
T29BST:N
R0960
0
5%
1/8W
MF-LF
805
21
=PP15V_T29_REG
MAKE_BASE=TRUE
NC_USB3_EXTD_TXP
MAKE_BASE=TRUE
NC_USB3_EXTD_RXN
MAKE_BASE=TRUE
NC_USB3_EXTD_RXP
MAKE_BASE=TRUE
7
35
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
=PP1V05_S0_CPU_VCCPQE
7
12 14
Unused eDP CLK
DPLL_REF_CLK_P
6
17 26 45 73
MAKE_BASE=TRUE
10
DPLL_REF_CLK_N
10
PM_SLP_S3_L
33
OUT
19 33
OUT
33
IN
33 83
OUT
33 83
OUT
33 83
IN
33 83
IN
33 33
IN
IN
TP_P1V5S3RS0_RAMP_DONE
MAKE_BASE=TRUE
TP_DDRREG_PGOOD
MAKE_BASE=TRUE
T29_A_BIAS
8
75 76
EMI IO (SHORT) POGO PINS
B
ZS0900
1.4DIA-SHORT-SILVER-K99
SM
1
ZS0901
1.4DIA-SHORT-SILVER-K99
SM
1
ZS0902
1.4DIA-SHORT-SILVER-K99
SM
1
ZS0910
1.4DIA-SHORT-SILVER-K99
SM
1
C0960
0.01UF
X5R-CERM
0201
1
10%
10V
2
DP_A_BIAS0
75
C0962
0.01UF
X5R-CERM
0201
10%
10V
T29_A_BIAS_R2DP1
C0970
0.01UF
X5R-CERM
0201
C0972
0.01UF
X5R-CERM
0201
JTAG_ISP_TCK
IN
MAKE_BASE=TRUE
JTAG_ISP_TDI
IN
MAKE_BASE=TRUE
JTAG_ISP_TDO
OUT
MAKE_BASE=TRUE
21
5%
10%
10V
21
5%
10%
10V
T29_A_BIAS_R2DN0
R0971
T29_A_BIAS_R2DP0
MF
VOLTAGE=3.3V
1
2
R0973
T29_A_BIAS_D2RP1
MF
VOLTAGE=3.3V
1
2
ZS0903
1.4DIA-SHORT-SILVER-K99
SM
1
ZS0909
1.4DIA-SHORT-SILVER-K99
SM
1
T29_A_BIAS
8
75 76
R0970
1/20W
51
201
EMI TALL POGO PINS
ZS0904
POGO-2.0OD-3.5H-K86-K87
SM
1
ZS0905
POGO-2.0OD-3.5H-K86-K87
SM
1
ZS0906
POGO-2.0OD-3.5H-K86-K87
SM
1
ZS0907
POGO-2.0OD-3.5H-K86-K87
SM
1
R0972
1/20W
51
201
TALL POGO PINS close to DIMM conn.
ZS0920
A
POGO-2.0OD-3.5H-K86-K87
SM
1
NO STUFF
ZS0921
POGO-2.0OD-3.5H-K86-K87
SM
1
NO STUFF
ZS0922
POGO-2.0OD-3.5H-K86-K87
SM
1
NO STUFF
ZS0923
POGO-2.0OD-3.5H-K86-K87
SM
1
NO STUFF
ZS0924
POGO-2.0OD-3.5H-K86-K87
SM
1
NO STUFF
19 23
19
19
75
1
2
51
201
1/20W
51
201
1/20W
TBT JTAG
DP_A_BIAS2
C0964
0.01UF
X5R-CERM
75
75
21
5%
MF
C0971
0.01UF
10%
10V
X5R-CERM
0201
21
5%
MF
C0973
0.01UF
10%
10V
X5R-CERM
0201
JTAG_TBT_TCK
JTAG_TBT_TDI
JTAG_TBT_TDO
1
10%
10V
2
0201
T29_A_BIAS_R2DN1
VOLTAGE=3.3V
1
2
T29_A_BIAS_D2RN1
VOLTAGE=3.3V
1
2
USB3_EXTD_TX_N
USB3_EXTD_TX_P
USB3_EXTD_RX_N
USB3_EXTD_RX_P
DPLL_REF_CLKP
MAKE_BASE=TRUE
DPLL_REF_CLKN
MAKE_BASE=TRUE
=TBT_S0_EN
Unused T29 Ports
T29_D2R_P<2..3>
T29_D2R_N<2..3>
T29_R2D_C_P<2..3>
T29_R2D_C_N<2..3>
T29_LSEO<2>
T29_LSEO<3>
Unused PGOOD signal
18
18
18
18
1
R0940
1K
5%
1/16W
MF-LF
402
2
1
R0941
1K
5%
1/16W
MF-LF
402
2
76
NC_T29_D2RP<2..3>
MAKE_BASE=TRUE
NC_T29_D2RN<2..3>
MAKE_BASE=TRUE
NC_T29_R2D_CP<2..3>
MAKE_BASE=TRUE
NC_T29_R2D_CN<2..3>
MAKE_BASE=TRUE
T29_LSOE<2>
MAKE_BASE=TRUE
T29_LSOE<3>
MAKE_BASE=TRUE
P1V5S3RS0_RAMP_DONE
DDRREG_PGOOD
USB_BT_N
32 80
MAKE_BASE=TRUE
USB_BT_P
32 80
MAKE_BASE=TRUE
USB_TPAD_N
53 80
MAKE_BASE=TRUE
USB_TPAD_P
53 80
MAKE_BASE=TRUE
USB_IR_N
44 80
MAKE_BASE=TRUE
USB_IR_P
44 80
MAKE_BASE=TRUE
USB_SMC_N
45 80
USB_SMC_P
45 80
NC_USB_EXTD_EHCIN
MAKE_BASE=TRUE
NC_USB_EXTD_EHCIP
MAKE_BASE=TRUE
NC_USB_EXTCN
MAKE_BASE=TRUE
NC_USB_EXTCP
MAKE_BASE=TRUE
NC_USB3_EXTC_TXN
MAKE_BASE=TRUE
NC_USB3_EXTC_TXP
MAKE_BASE=TRUE
NC_USB3_EXTC_RXN
MAKE_BASE=TRUE
NC_USB3_EXTC_RXP
MAKE_BASE=TRUE
NC_USB_EXTD_XHCIN
MAKE_BASE=TRUE
NC_USB_EXTD_XHCIP
MAKE_BASE=TRUE
TP_CPU_THERMDP
MAKE_BASE=TRUE
TP_CPU_THERMDN
MAKE_BASE=TRUE
TP_CPU_VTT_SELECT
MAKE_BASE=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
IN
IN
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
SYNC_MASTER=K90I_MLB SYNC_DATE=02/15/2011
OUT
PAGE TITLE
33 33
OUT
NOTICE OF PROPRIETARY PROPERTY:
72
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
67
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
6 3
USBHUB_DN1_N
USBHUB_DN1_P
USBHUB_DN3_N
USBHUB_DN3_P
USBHUB_DN2_N
USBHUB_DN2_P
NC_USB_SMCN
MAKE_BASE=TRUE
NC_USB_SMCP
MAKE_BASE=TRUE
USB_EXTD_EHCI_N
NO_TEST=TRUE
NO_TEST=TRUE
USB_EXTD_EHCI_P
USB_EXTC_N
USB_EXTC_P
USB3_EXTC_TX_N
USB3_EXTC_TX_P
USB3_EXTC_RX_N
USB3_EXTC_RX_P
USB_EXTD_XHCI_N
USB_EXTD_XHCI_P
CPU_THERMD_P
CPU_THERMD_N
CPU_VTTSELECT
Digital Ground
GND
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=0V
Signal Aliases
Apple Inc.
R
25
25
25
25
25
25
18
18
18 80
18 80
18
18
18
18
18 80
18 80
9
85
9
85
DRAWING NUMBER
051-9058
REVISION
6.0.0
BRANCH
PAGE
9 OF 109
SHEET
8 OF 86
124578
SIZE
B
A
D
8 7 6 5 4 3
NOTE: Intel provides an internal pull-up OF 5-15k to VCCIO on all CFG signals.
12
DMI_S2N_N<0>
17 78
IN
DMI_S2N_N<1>
17 78
IN
DMI_S2N_N<2>
17 78
IN
DMI_S2N_N<3>
17 78
IN
DMI_S2N_P<0>
17 78
D
C
=PP1V05_S0_CPU_VCCIO
7 9
10 12 14
R1030
24.9
1%
1/16W
MF-LF
402
EDP
R1031
10K
1%
1/16W
MF-LF
402
21
21
B
Intel Doc 467283 ChiefRiver Platform design guild rev0.71 section 2.2.12 recommendation.
NOTE: eDP_COMPIO and eDP_ICOMPO can not be left floating
even if internal Graphics is disabled since they are
shared with other interfaces.
NOTE: The EDP_HPD processor input is a low voltage active low signal.
Therefore, an inverting level shifter is required on the motherboard
to convert the active high signal from Embedded DisplayPort sink device
to low voltage signals for the processor
(refer to latest Processor EDS for DC specifications).
If HPD is disabled while eDP interface is still enabled,
connect it to CPU VCCIo via a 10-kOhm pull-up resistor on the motherboard.
This signal can be left as no-connect if entire eDP interface is disabled.
IN
17 78
IN
17 78
IN
17 78
IN
17 78
OUT
17 78
OUT
17 78
OUT
17 78
OUT
17 78
OUT
17 78
OUT
17 78
OUT
17 78
OUT
17 78
OUT
17 78
OUT
17 78
OUT
17 78
OUT
17 78
OUT
17 78
OUT
17 78
OUT
17 78
OUT
17 78
OUT
17 78
OUT
17 78
OUT
17 78
OUT
17 78
OUT
17 78
OUT
17 78
OUT
17 78
OUT
17 78
IN
17 78
IN
17 78
IN
17 78
IN
17 78
IN
PLACE_NEAR=U1000.AF3:12.7MM
PLACE_NEAR=U1000.AG11:12.7MM
DMI_S2N_P<1>
DMI_S2N_P<2>
DMI_S2N_P<3>
DMI_N2S_N<0>
DMI_N2S_N<1>
DMI_N2S_N<2>
DMI_N2S_N<3>
DMI_N2S_P<0>
DMI_N2S_P<1>
DMI_N2S_P<2>
DMI_N2S_P<3>
FDI_DATA_N<0>
FDI_DATA_N<1>
FDI_DATA_N<2>
FDI_DATA_N<3>
FDI_DATA_N<4>
FDI_DATA_N<5>
FDI_DATA_N<6>
FDI_DATA_N<7>
FDI_DATA_P<0>
FDI_DATA_P<1>
FDI_DATA_P<2>
FDI_DATA_P<3>
FDI_DATA_P<4>
FDI_DATA_P<5>
FDI_DATA_P<6>
FDI_DATA_P<7>
FDI_FSYNC<0>
FDI_FSYNC<1>
FDI_INT
FDI_LSYNC<0>
FDI_LSYNC<1>
EDP_COMP
78
EDP_HPD
TP_EDP_AUX_N
6
TP_EDP_AUX_P
6
TP_EDP_TX_N<0>
6
TP_EDP_TX_N<1>
6
TP_EDP_TX_N<2>
6
TP_EDP_TX_N<3>
6
TP_EDP_TX_P<0>
6
TP_EDP_TX_P<1>
6
TP_EDP_TX_P<2>
6
TP_EDP_TX_P<3>
6
AA11
AC12
AA10
AG11
AE11
AE10
P10
P11
W11
AA6
AC9
W10
AA7
AA3
AC8
U11
AG8
AD2
AF3
AG4
AF4
AC3
AC4
AE7
AC1
AA4
AE6
M2
P6
P1
N3
P7
P3
K1
M8
N4
R2
K3
M7
P4
T3
U7
W1
W6
V4
Y2
U6
W3
W7
T4
DMI_RX_0*
DMI_RX_1*
DMI_RX_2*
DMI_RX_3*
DMI_RX_0
DMI_RX_1
DMI_RX_2
DMI_RX_3
DMI_TX_0*
DMI_TX_1*
DMI_TX_2*
DMI_TX_3*
DMI_TX_0
DMI_TX_1
DMI_TX_2
DMI_TX_3
FDI0_TX_0*
FDI0_TX_1*
FDI0_TX_2*
FDI0_TX_3*
FDI1_TX_0*
FDI1_TX_1*
FDI1_TX_2*
FDI1_TX_3*
FDI0_TX_0
FDI0_TX_1
FDI0_TX_2
FDI0_TX_3
FDI1_TX_0
FDI1_TX_1
FDI1_TX_2
FDI1_TX_3
FDI0_FSYNC
FDI1_FSYNC
FDI_INT
FDI0_LSYNC
FDI1_LSYNC
EDP_ICOMPO
EDP_COMPIO
EDP_HPD
EDP_AUX*
EDP_AUX
EDP_TX_0*
EDP_TX_1*
EDP_TX_2*
EDP_TX_3*
EDP_TX_0
EDP_TX_1
EDP_TX_2
EDP_TX_3
OMIT_TABLE
CRITICAL
U1000
IVY-BRIDGE
2C-35W
BGA
(1 OF 9)
DMI
INTEL FLEXIBLE DISPLAY INTERFACE SIGNALS
PCI EXPRESS BASED INTERFACE SIGNALS
EMBEDDED DISPLAY PORT
PEG_ICOMPI
PEG_ICOMPO
PEG_RCOMPO
PEG_RX_0*
PEG_RX_1*
PEG_RX_2*
PEG_RX_3*
PEG_RX_4*
PEG_RX_5*
PEG_RX_6*
PEG_RX_7*
PEG_RX_8*
PEG_RX_9*
PEG_RX_10*
PEG_RX_11*
PEG_RX_12*
PEG_RX_13*
PEG_RX_14*
PEG_RX_15*
PEG_RX_0
PEG_RX_1
PEG_RX_2
PEG_RX_3
PEG_RX_4
PEG_RX_5
PEG_RX_6
PEG_RX_7
PEG_RX_8
PEG_RX_9
PEG_RX_10
PEG_RX_11
PEG_RX_12
PEG_RX_13
PEG_RX_14
PEG_RX_15
PEG_TX_0*
PEG_TX_1*
PEG_TX_2*
PEG_TX_3*
PEG_TX_4*
PEG_TX_5*
PEG_TX_6*
PEG_TX_7*
PEG_TX_8*
PEG_TX_9*
PEG_TX_10*
PEG_TX_11*
PEG_TX_12*
PEG_TX_13*
PEG_TX_14*
PEG_TX_15*
PEG_TX_0
PEG_TX_1
PEG_TX_2
PEG_TX_3
PEG_TX_4
PEG_TX_5
PEG_TX_6
PEG_TX_7
PEG_TX_8
PEG_TX_9
PEG_TX_10
PEG_TX_11
PEG_TX_12
PEG_TX_13
PEG_TX_14
PEG_TX_15
G3
G1
G4
H22
J21
B22
D21
A19
D17
B14
D13
A11
B10
G8
A8
B6
H8
E5
K7
K22
K19
C21
D19
C19
D16
C13
D12
C11
C9
F8
C8
C5
H6
F6
K6
G22
C23
D23
F21
H19
C17
K15
F17
F14
A15
J14
H13
M10
F10
D9
J4
F22
A23
D24
E21
G19
B18
K17
G17
E14
C15
K13
G13
K10
G10
D8
K4
CPU_PEG_COMP
78
PLACE_NEAR=U1000.G3:12.7MM
=PEG_D2R_N<0>
=PEG_D2R_N<1>
=PEG_D2R_N<2>
=PEG_D2R_N<3>
=PEG_D2R_N<4>
=PEG_D2R_N<5>
=PEG_D2R_N<6>
=PEG_D2R_N<7>
=PEG_D2R_N<8>
=PEG_D2R_N<9>
=PEG_D2R_N<10>
=PEG_D2R_N<11>
=PEG_D2R_N<12>
=PEG_D2R_N<13>
=PEG_D2R_N<14>
=PEG_D2R_N<15>
=PEG_D2R_P<0>
=PEG_D2R_P<1>
=PEG_D2R_P<2>
=PEG_D2R_P<3>
=PEG_D2R_P<4>
=PEG_D2R_P<5>
=PEG_D2R_P<6>
=PEG_D2R_P<7>
=PEG_D2R_P<8>
=PEG_D2R_P<9>
=PEG_D2R_P<10>
=PEG_D2R_P<11>
=PEG_D2R_P<12>
=PEG_D2R_P<13>
=PEG_D2R_P<14>
=PEG_D2R_P<15>
=PEG_R2D_C_N<0>
=PEG_R2D_C_N<1>
=PEG_R2D_C_N<2>
=PEG_R2D_C_N<3>
=PEG_R2D_C_N<4>
=PEG_R2D_C_N<5>
=PEG_R2D_C_N<6>
=PEG_R2D_C_N<7>
=PEG_R2D_C_N<8>
=PEG_R2D_C_N<9>
=PEG_R2D_C_N<10>
=PEG_R2D_C_N<11>
=PEG_R2D_C_N<12>
=PEG_R2D_C_N<13>
=PEG_R2D_C_N<14>
=PEG_R2D_C_N<15>
=PEG_R2D_C_P<0>
=PEG_R2D_C_P<1>
=PEG_R2D_C_P<2>
=PEG_R2D_C_P<3>
=PEG_R2D_C_P<4>
=PEG_R2D_C_P<5>
=PEG_R2D_C_P<6>
=PEG_R2D_C_P<7>
=PEG_R2D_C_P<8>
=PEG_R2D_C_P<9>
=PEG_R2D_C_P<10>
=PEG_R2D_C_P<11>
=PEG_R2D_C_P<12>
=PEG_R2D_C_P<13>
=PEG_R2D_C_P<14>
=PEG_R2D_C_P<15>
R1010
24.9
21
=PP1V05_S0_CPU_VCCIO
1%
1/16W
MF-LF
402
6
IN
6
IN
6
IN
6
IN
6
IN
6
IN
6
IN
6
IN
6
IN
6
IN
6
IN
6
IN
8
IN
8
IN
8
IN
8
IN
6
IN
6
IN
6
IN
6
IN
6
IN
6
IN
6
IN
6
IN
6
IN
6
IN
6
IN
6
IN
8
IN
8
IN
8
IN
8
IN
6
OUT
6
OUT
6
OUT
6
OUT
6
OUT
6
OUT
6
OUT
6
OUT
6
OUT
6
OUT
6
OUT
6
OUT
8
OUT
8
OUT
8
OUT
8
OUT
6
OUT
6
OUT
6
OUT
6
OUT
6
OUT
6
OUT
6
OUT
6
OUT
6
OUT
6
OUT
6
OUT
6
OUT
8
OUT
8
OUT
8
OUT
8
OUT
7 9
10 12 14
PLACE_NEAR=U1000.H43:50.8MM
PLACE_SIDE=BOTTOM
=PPVCORE_S0_CPU
NOSTUFF
R1064
NOSTUFF
R1065
NOTE: Intel validation sense lines per
doc 439028 rev1.0 HR_PPDG sections 6.2.1 and 6.3.1.
=PPVCORE_S0_CPU_VCCAXG
NOSTUFF
1
1
49.9
49.9
R1070
49.9
1%
1/16W
MF-LF
1/16W
MF-LF
1%
1/16W
MF-LF
402
402
2
2
PLACE_NEAR=U1000.H45:50.8MM
PLACE_SIDE=BOTTOM
Note. VOLTAGE=1.25V
Note. VOLTAGE=0V
Note. VOLTAGE=1.05V
Note. VOLTAGE=0V
NOSTUFF
1
1
R1071
49.9
1%
1%
1/16W
MF-LF
402
402
2
2
PLACE_NEAR=U1000.K45:50.8MM
PLACE_SIDE=BOTTOM
PLACE_NEAR=U1000.K43:50.8MM
PLACE_SIDE=BOTTOM
7
12 14
7
12 15
NOTE: Intel does not recommend to use
this alnalog sense due to accuracy concern.
CPU_CFG<0>
9
23 78
IN
CPU_CFG<1>
9
23 78
IN
CPU_CFG<2>
9
23 78
IN
CPU_CFG<3>
9
23 78
IN
CPU_CFG<4>
9
23 78
IN
CPU_CFG<5>
9
23 78
IN
CPU_CFG<6>
9
23 78
IN
CPU_CFG<7>
9
23 78
IN
CPU_CFG<8>
23 78
IN
CPU_CFG<9>
23 78
IN
CPU_CFG<10>
23 78
IN
CPU_CFG<11>
23 78
IN
CPU_CFG<12>
23
IN
78
CPU_CFG<13>
23 78
IN
CPU_CFG<14>
23 78
IN
CPU_CFG<15>
23 78
IN
CPU_CFG<16>
9
23
IN
CPU_CFG<17>
23
IN
CPU_VCC_VALSENSE_P
CPU_VCC_VALSENSE_N
CPU_AXG_VALSENSE_P
CPU_AXG_VALSENSE_N
TP_CPU_VCC_DIE_SENSE
CPU_THERMD_P
8
85
OUT
CPU_THERMD_N
8
85
OUT
B50
C51
B54
D53
A51
C53
C55
H49
A55
H51
K49
K53
F53
G53
L51
F51
D52
L53
H43
K43
H45
K45
F48
H48
K48
BA19
NC
AV19
NC
AT21
NC
BB21
NC
BB19
NC
AY21
NC
BA22
NC
AY22
NC
AU19
NC
AU21
NC
BD21
NC
BD22
NC
BD25
NC
BD26
NC
BG22
NC
BE22
NC
BG26
NC
BE26
NC
BF23
NC
BE24
NC
OMIT_TABLE
CRITICAL
CFG_0
CFG_1
CFG_2
CFG_3
CFG_4
CFG_5
CFG_6
CFG_7
CFG_8
CFG_9
CFG_10
CFG_11
CFG_12
CFG_13
CFG_14
CFG_15
CFG_16
CFG_17
VCC_VAL_SENSE
VSS_VAL_SENSE
VAXG_VAL_SENSE
VSSAXG_VAL_SENSE
U1000
VCC_DIE_SENSE
RSVD_6
RSVD_7
RSVD_8
RSVD_9
RSVD_10
RSVD_11
RSVD_12
RSVD_13
RSVD_14
RSVD_15
RSVD_16
RSVD_17
RSVD_18
RSVD_19
RSVD_20
RSVD_21
RSVD_22
RSVD_23
RSVD_24
RSVD_25
RSVD_26
RSVD_27
SA_DIMM_VREFDQ
SB_DIMM_VREFDQ
BGA
(5 OF 9)
RESERVED
2C-35W
IVY-BRIDGE
RSVD_30
RSVD_31
RSVD_32
RSVD_33
RSVD_34
RSVD_35
RSVD_36
RSVD_37
RSVD_38
RSVD_39
RSVD_40
RSVD_41
RSVD_42
RSVD_43
RSVD_44
RSVD_45
DC_TEST_A4
DC_TEST_C4
DC_TEST_D3
DC_TEST_D1
DC_TEST_A58
DC_TEST_A59
DC_TEST_C59
DC_TEST_A61
DC_TEST_C61
DC_TEST_D61
DC_TEST_BD61
DC_TEST_BE61
DC_TEST_BE59
DC_TEST_BG61
DC_TEST_BG59
DC_TEST_BG58
DC_TEST_BG4
DC_TEST_BG3
DC_TEST_BE3
DC_TEST_BG1
DC_TEST_BE1
DC_TEST_BD1
MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.2 MM
BE7
BG7
N42
L42
L45
L47
M13
M14
U14
W14
P13
AT49
K24
AH2
AG13
AM14
AM15
N50
A4
C4
D3
D1
A58
A59
C59
A61
C61
D61
BD61
BE61
BE59
BG61
BG59
BG58
BG4
BG3
BE3
BG1
BE1
BD1
VOLTAGE=0.75V
PPCPU_MEM_VREFDQ_A
PPCPU_MEM_VREFDQ_B
MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.2 MM
NC
VOLTAGE=0.75V
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
TP_CPU_DC_TEST_A4
CPU_DC_TEST_C4_D3
TP_CPU_DC_TEST_D1
TP_CPU_DC_TEST_A58
CPU_DC_TEST_C59_A59
CPU_DC_TEST_C61_A61
TP_CPU_DC_TEST_D61
TP_CPU_DC_TEST_BD61
CPU_DC_TEST_BE59_BE61
CPU_DC_TEST_BG59_BG61
TP_CPU_DC_TEST_BG58
TP_CPU_DC_TEST_BG4
CPU_DC_TEST_C4_BE3_BG3
CPU_DC_TEST_C4_BE1_BG1
TP_CPU_DC_TEST_BD1
31
OUT
31
OUT
D
C
B
CPU_CFG<16>
9
CPU_CFG<7>
9
23 78
CPU_CFG<6>
9
23 78
CPU_CFG<5>
9
23 78
CPU_CFG<4>
9
23 78
CPU_CFG<2>
9
23 78
EDP
1
R1042
1/20W
A
1
R1044
1K
1K
5%
5%
1/20W
MF
MF
201
201
2
2
NOSTUFF
R1045
NOSTUFF
NOSTUFF
1
1
R1046
1K
5%
1/20W
1/20W
MF
201
201
2
1
R1047
1K
1K
5%
5%
1/20W
MF
MF
201
2
2
FOR IVYBRIDGE PROCESSOR
CFG [7] :PEG DEFER TRAINING 1 = (DEFAULT) IMMEDIATELY AFTER xxRESETB 0 = WAIT FOR BIOS
CFG [6:5] :PCIE BIFURCATION 11 = 1 X16 (DEFAULT) 10 = 2 X8 01 = RSVD 00 = X8, X4, X4
CFG [4] :eDP ENABLE/DISABLE 1 = DISABLED 0 = ENABLED
CFG [3] :PCIE x4 LANE REVERSAL 1 = NORMAL OPERATION 0 = LANES REVERSED
CFG [2] :PCIE x16 LANE REVERSAL 1 = NORMAL OPERATION 0 = LANES REVERSED
23
CPU_CFG<3>
9
23 78
CPU_CFG<1>
9
23 78
CPU_CFG<0>
9
23 78
R1040
NOSTUFF
1
1K
5%
1/20W
MF
201
2
NOSTUFF
These can be Placed close to J2500 and Only for debug access
R1041
NOSTUFF
R1043
1
1K
5%
1/20W
MF
201
2
1
1K
5%
1/20W
MF
201
2
NOSTUFF
1
R1049
1K
5%
1/20W
MF
201
2
6 3
SYNC_MASTER=MASTER
PAGE TITLE
CPU DMI/PEG/FDI/RSVD
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
SYNC_DATE=02/15/2011
DRAWING NUMBER
051-9058
REVISION
6.0.0
BRANCH
PAGE
10 OF 109
SHEET
9 OF 86
124578
SIZE
A
D
8 7 6 5 4 3
12
D
=PP1V05_S0_CPU_VCCIO
7 9
10 12 14
NOSTUFF
1
R1100
1
R1101
62
5%
1/20W
MF
201
2
C
R1103
56
45 46 68 78
=PP1V5_S3_CPU_VCCDDR
7
12 15 26
PM_MEM_PWRGD
17 26 78
IN
=PP1V05_S0_CPU_VCCIO
7 9
10 12 14
CPU_PROCHOT_L
BI
R1120
1/16W
MF-LF
200
1
1%
402
2
2 1
5%
1/20W
MF
201
R1121
2 1
130
1/16W
MF-LF
CPU_PROCHOT_R_L
1%
402
19
OUT
45 78
OUT
19 46 78
BI
19 46 78
OUT
17 78
IN
19 23 78
IN
26
OUT
1K
5%
1/20W
MF
201
2
CPU_PROC_SEL_L
CPU_CATERR_L
CPU_PECI
PM_THRMTRIP_L
PM_SYNC
CPU_PWRGD
PM_MEM_PWRGD_R
PLT_RESET_LS1V1_L
=MEM_RESET_L
78
78
78
NOSTUFF
1
1
R1104
51
5%
1/20W
MF
201
2
2
CPU_SM_RCOMP<0>
CPU_SM_RCOMP<1>
CPU_SM_RCOMP<2>
NOSTUFF
R1102
1K
5%
1/20W
201
MF
C57
PROC_DETECT*
NC
F49
PROC_SELECT*
C49
CATERR*
A48
PECI
C45
PROCHOT*
D45
THERMTRIP*
C48
PM_SYNC
B46
UNCOREPWRGOOD
BE45
SM_DRAMPWROK
D44
RESET*
AT30
SM_DRAMRST*
BF44
SM_RCOMP_0
BE43
SM_RCOMP_1
BG43
SM_RCOMP_2
OMIT_TABLE
CRITICAL
U1000
IVY-BRIDGE
2C-35W
BGA
(2 OF 9)
THERMAL
PWR MGMT
DDR3 MISC
DPLL_REF_CLK
DPLL_REF_CLK*
BCLK_ITP
CLOCKS
BCLK_ITP*
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
JTAG & BPM
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
BCLK
BCLK*
PRDY*
PREQ*
TRST*
DBR*
BPM_0*
BPM_1*
BPM_2*
BPM_3*
BPM_4*
BPM_5*
BPM_6*
BPM_7*
TCK
TMS
TDI
TDO
J3
H2
AG3
AG1
N59
N58
N53
N55
L56
L55
J58
M60
L59
K58
G58
E55
E59
G55
G59
H60
J59
J61
DMI_CLK100M_CPU_P
DMI_CLK100M_CPU_N
DPLL_REF_CLK_P
DPLL_REF_CLK_N
ITPCPU_CLK100M_P
ITPCPU_CLK100M_N
XDP_CPU_PRDY_L
XDP_CPU_PREQ_L
XDP_CPU_TCK
XDP_CPU_TMS
XDP_CPU_TRST_L
XDP_CPU_TDI
XDP_CPU_TDO
XDP_DBRESET_L
XDP_BPM_L<0>
XDP_BPM_L<1>
XDP_BPM_L<2>
XDP_BPM_L<3>
XDP_BPM_L<4>
XDP_BPM_L<5>
XDP_BPM_L<6>
XDP_BPM_L<7>
16 78
IN
16 78
IN
8
IN
8
IN
16 78
IN
16 78
IN
23 78
OUT
23 78
IN
23 78
IN
23 78
IN
23 78
IN
23 78
IN
23 78
OUT
23 24 78
OUT
23 78
BI
23 78
BI
23 78
BI
23 78
BI
23
BI
23
BI
23
BI
23
BI
D
C
1
1
B
CPU_RESET_L
23 24
IN
R1126
1/16W
MF-LF
75
1%
402
2
R1125
43.2
2 1
1%
1/20W
MF
201
R1112
140
1%
1/16W
MF-LF
402
2
R1113
25.5
2
R1114
200
1%
1%
1/16W
1/16W
MF-LF
MF-LF
402
402
2
1
1
A
6 3
1
R1111
10K
5%
1/20W
MF
201
2
SYNC_MASTER=MASTER
PAGE TITLE
CPU CLOCK/MISC/JTAG
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
SYNC_DATE=02/15/2011
DRAWING NUMBER
051-9058
REVISION
6.0.0
BRANCH
PAGE
11 OF 109
SHEET
10 OF 86
124578
SIZE
B
A
D
8 7 6 5 4 3
12
OMIT_TABLE
CRITICAL
MEM_A_DQ<0>
28 79
BI
MEM_A_DQ<1>
28 79
BI
MEM_A_DQ<2>
28 79
BI
MEM_A_DQ<3>
28 79
BI
MEM_A_DQ<4>
28 79
D
C
B
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
27 79
OUT
27 79
OUT
27 79
OUT
27 79
OUT
27 79
OUT
27 79
OUT
MEM_A_DQ<5>
MEM_A_DQ<6>
MEM_A_DQ<7>
MEM_A_DQ<8>
MEM_A_DQ<9>
MEM_A_DQ<10>
MEM_A_DQ<11>
MEM_A_DQ<12>
MEM_A_DQ<13>
MEM_A_DQ<14>
MEM_A_DQ<15>
MEM_A_DQ<16>
MEM_A_DQ<17>
MEM_A_DQ<18>
MEM_A_DQ<19>
MEM_A_DQ<20>
MEM_A_DQ<21>
MEM_A_DQ<22>
MEM_A_DQ<23>
MEM_A_DQ<24>
MEM_A_DQ<25>
MEM_A_DQ<26>
MEM_A_DQ<27>
MEM_A_DQ<28>
MEM_A_DQ<29>
MEM_A_DQ<30>
MEM_A_DQ<31>
MEM_A_DQ<32>
MEM_A_DQ<33>
MEM_A_DQ<34>
MEM_A_DQ<35>
MEM_A_DQ<36>
MEM_A_DQ<37>
MEM_A_DQ<38>
MEM_A_DQ<39>
MEM_A_DQ<40>
MEM_A_DQ<41>
MEM_A_DQ<42>
MEM_A_DQ<43>
MEM_A_DQ<44>
MEM_A_DQ<45>
MEM_A_DQ<46>
MEM_A_DQ<47>
MEM_A_DQ<48>
MEM_A_DQ<49>
MEM_A_DQ<50>
MEM_A_DQ<51>
MEM_A_DQ<52>
MEM_A_DQ<53>
MEM_A_DQ<54>
MEM_A_DQ<55>
MEM_A_DQ<56>
MEM_A_DQ<57>
MEM_A_DQ<58>
MEM_A_DQ<59>
MEM_A_DQ<60>
MEM_A_DQ<61>
MEM_A_DQ<62>
MEM_A_DQ<63>
MEM_A_BA<0>
MEM_A_BA<1>
MEM_A_BA<2>
MEM_A_CAS_L
MEM_A_RAS_L
MEM_A_WE_L
AG6
AJ6
AP11
AL6
AJ10
AJ8
AL8
AL7
AR11
AP6
AU6
AV9
AR6
AP8
AT13
AU13
BC7
BB7
BA13
BB11
BA7
BA9
BB9
AY13
AV14
AR14
AY17
AR19
BA14
AU14
BB14
BB17
BA45
AR43
AW48
BC48
BC45
AR45
AT48
AY48
BA49
AV49
BB51
AY53
BB49
AU49
BA53
BB55
BA55
AV56
AP50
AP53
AV54
AT54
AP56
AP52
AN57
AN53
AG56
AG53
AN55
AN52
AG55
AK56
BD37
BF36
BA28
BE39
BD39
AT41
SA_DQ_0
SA_DQ_1
SA_DQ_2
SA_DQ_3
SA_DQ_4
SA_DQ_5
SA_DQ_6
SA_DQ_7
SA_DQ_8
SA_DQ_9
SA_DQ_10
SA_DQ_11
SA_DQ_12
SA_DQ_13
SA_DQ_14
SA_DQ_15
SA_DQ_16
SA_DQ_17
SA_DQ_18
SA_DQ_19
SA_DQ_20
SA_DQ_21
SA_DQ_22
SA_DQ_23
SA_DQ_24
SA_DQ_25
SA_DQ_26
SA_DQ_27
SA_DQ_28
SA_DQ_29
SA_DQ_30
SA_DQ_31
SA_DQ_32
SA_DQ_33
SA_DQ_34
SA_DQ_35
SA_DQ_36
SA_DQ_37
SA_DQ_38
SA_DQ_39
SA_DQ_40
SA_DQ_41
SA_DQ_42
SA_DQ_43
SA_DQ_44
SA_DQ_45
SA_DQ_46
SA_DQ_47
SA_DQ_48
SA_DQ_49
SA_DQ_50
SA_DQ_51
SA_DQ_52
SA_DQ_53
SA_DQ_54
SA_DQ_55
SA_DQ_56
SA_DQ_57
SA_DQ_58
SA_DQ_59
SA_DQ_60
SA_DQ_61
SA_DQ_62
SA_DQ_63
SA_BS_0
SA_BS_1
SA_BS_2
SA_CAS*
SA_RAS*
SA_WE*
U1000
BGA
(3 OF 9)
2C-35W
IVY-BRIDGE
MEMORY CHANNEL A
SA_CK_0
SA_CK_0*
SA_CKE_0
SA_CK_1
SA_CK_1*
SA_CKE_1
SA_CS_0*
SA_CS_1*
SA_ODT_0
SA_ODT_1
SA_DQS_0*
SA_DQS_1*
SA_DQS_2*
SA_DQS_3*
SA_DQS_4*
SA_DQS_5*
SA_DQS_6*
SA_DQS_7*
SA_DQS_0
SA_DQS_1
SA_DQS_2
SA_DQS_3
SA_DQS_4
SA_DQS_5
SA_DQS_6
SA_DQS_7
SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8
SA_MA_9
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13
SA_MA_14
SA_MA_15
AU36
AV36
AY26
AT40
AU40
BB26
BB40
BC41
AY40
BA41
AL11
AR8
AV11
AT17
AV45
AY51
AT55
AK55
AJ11
AR10
AY11
AU17
AW45
AV51
AT56
AK54
BG35
BB34
BE35
BD35
AT34
AU34
BB32
AT32
AY32
AV32
BE37
BA30
BC30
AW41
AY28
AU26
MEM_A_CLK_P<0>
MEM_A_CLK_N<0>
MEM_A_CKE<0>
MEM_A_CLK_P<1>
MEM_A_CLK_N<1>
MEM_A_CKE<1>
MEM_A_CS_L<0>
MEM_A_CS_L<1>
MEM_A_ODT<0>
MEM_A_ODT<1>
MEM_A_DQS_N<0>
MEM_A_DQS_N<1>
MEM_A_DQS_N<2>
MEM_A_DQS_N<3>
MEM_A_DQS_N<4>
MEM_A_DQS_N<5>
MEM_A_DQS_N<6>
MEM_A_DQS_N<7>
MEM_A_DQS_P<0>
MEM_A_DQS_P<1>
MEM_A_DQS_P<2>
MEM_A_DQS_P<3>
MEM_A_DQS_P<4>
MEM_A_DQS_P<5>
MEM_A_DQS_P<6>
MEM_A_DQS_P<7>
MEM_A_A<0>
MEM_A_A<1>
MEM_A_A<2>
MEM_A_A<3>
MEM_A_A<4>
MEM_A_A<5>
MEM_A_A<6>
MEM_A_A<7>
MEM_A_A<8>
MEM_A_A<9>
MEM_A_A<10>
MEM_A_A<11>
MEM_A_A<12>
MEM_A_A<13>
MEM_A_A<14>
MEM_A_A<15>
MEM_B_DQ<0>
27 79
OUT
27 79
OUT
27 79
OUT
27 79
OUT
27 79
OUT
27 79
OUT
27 79
OUT
27 79
OUT
27 79
OUT
27 79
OUT
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
27 79
OUT
27 79
OUT
27 79
OUT
27 79
OUT
27 79
OUT
27 79
OUT
27 79
OUT
27 79
OUT
27 79
OUT
27 79
OUT
27 79
OUT
27 79
OUT
27 79
OUT
27 79
OUT
27 79
OUT
27 79
OUT
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
29 79
OUT
29 79
OUT
29 79
OUT
29 79
OUT
29 79
OUT
29 79
OUT
MEM_B_DQ<1>
MEM_B_DQ<2>
MEM_B_DQ<3>
MEM_B_DQ<4>
MEM_B_DQ<5>
MEM_B_DQ<6>
MEM_B_DQ<7>
MEM_B_DQ<8>
MEM_B_DQ<9>
MEM_B_DQ<10>
MEM_B_DQ<11>
MEM_B_DQ<12>
MEM_B_DQ<13>
MEM_B_DQ<14>
MEM_B_DQ<15>
MEM_B_DQ<16>
MEM_B_DQ<17>
MEM_B_DQ<18>
MEM_B_DQ<19>
MEM_B_DQ<20>
MEM_B_DQ<21>
MEM_B_DQ<22>
MEM_B_DQ<23>
MEM_B_DQ<24>
MEM_B_DQ<25>
MEM_B_DQ<26>
MEM_B_DQ<27>
MEM_B_DQ<28>
MEM_B_DQ<29>
MEM_B_DQ<30>
MEM_B_DQ<31>
MEM_B_DQ<32>
MEM_B_DQ<33>
MEM_B_DQ<34>
MEM_B_DQ<35>
MEM_B_DQ<36>
MEM_B_DQ<37>
MEM_B_DQ<38>
MEM_B_DQ<39>
MEM_B_DQ<40>
MEM_B_DQ<41>
MEM_B_DQ<42>
MEM_B_DQ<43>
MEM_B_DQ<44>
MEM_B_DQ<45>
MEM_B_DQ<46>
MEM_B_DQ<47>
MEM_B_DQ<48>
MEM_B_DQ<49>
MEM_B_DQ<50>
MEM_B_DQ<51>
MEM_B_DQ<52>
MEM_B_DQ<53>
MEM_B_DQ<54>
MEM_B_DQ<55>
MEM_B_DQ<56>
MEM_B_DQ<57>
MEM_B_DQ<58>
MEM_B_DQ<59>
MEM_B_DQ<60>
MEM_B_DQ<61>
MEM_B_DQ<62>
MEM_B_DQ<63>
MEM_B_BA<0>
MEM_B_BA<1>
MEM_B_BA<2>
MEM_B_CAS_L
MEM_B_RAS_L
MEM_B_WE_L
AL4
AL1
AN3
AR4
AK4
AK3
AN4
AR1
AU4
AT2
AV4
BA4
AU3
AR3
AY2
BA3
BE9
BD9
BD13
BF12
BF8
BD10
BD14
BE13
BF16
BE17
BE18
BE21
BE14
BG14
BG18
BF19
BD50
BF48
BD53
BF52
BD49
BE49
BD54
BE53
BF56
BE57
BC59
AY60
BE54
BG54
BA58
AW59
AW58
AU58
AN61
AN59
AU59
AU61
AN58
AR58
AK58
AL58
AG58
AG59
AM60
AL59
AF61
AH60
BG39
BD42
AT22
AV43
BF40
BD45
SB_DQ_0
SB_DQ_1
SB_DQ_2
SB_DQ_3
SB_DQ_4
SB_DQ_5
SB_DQ_6
SB_DQ_7
SB_DQ_8
SB_DQ_9
SB_DQ_10
SB_DQ_11
SB_DQ_12
SB_DQ_13
SB_DQ_14
SB_DQ_15
SB_DQ_16
SB_DQ_17
SB_DQ_18
SB_DQ_19
SB_DQ_20
SB_DQ_21
SB_DQ_22
SB_DQ_23
SB_DQ_24
SB_DQ_25
SB_DQ_26
SB_DQ_27
SB_DQ_28
SB_DQ_29
SB_DQ_30
SB_DQ_31
SB_DQ_32
SB_DQ_33
SB_DQ_34
SB_DQ_35
SB_DQ_36
SB_DQ_37
SB_DQ_38
SB_DQ_39
SB_DQ_40
SB_DQ_41
SB_DQ_42
SB_DQ_43
SB_DQ_44
SB_DQ_45
SB_DQ_46
SB_DQ_47
SB_DQ_48
SB_DQ_49
SB_DQ_50
SB_DQ_51
SB_DQ_52
SB_DQ_53
SB_DQ_54
SB_DQ_55
SB_DQ_56
SB_DQ_57
SB_DQ_58
SB_DQ_59
SB_DQ_60
SB_DQ_61
SB_DQ_62
SB_DQ_63
SB_BS_0
SB_BS_1
SB_BS_2
SB_CAS*
SB_RAS*
SB_WE*
OMIT_TABLE
CRITICAL
2C-35W
SB_CK_0
SB_CK_0*
SB_CKE_0
SB_CK_1
SB_CK_1*
U1000
BGA
(4 OF 9)
SB_CKE_1
IVY-BRIDGE
SB_CS_0*
SB_CS_1*
SB_ODT_0
SB_ODT_1
SB_DQS_0*
SB_DQS_1*
SB_DQS_2*
SB_DQS_3*
SB_DQS_4*
SB_DQS_5*
SB_DQS_6*
SB_DQS_7*
SB_DQS_0
MEMORY CHANNEL B
SB_DQS_1
SB_DQS_2
SB_DQS_3
SB_DQS_4
SB_DQS_5
SB_DQS_6
SB_DQS_7
SB_MA_0
SB_MA_1
SB_MA_2
SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8
SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13
SB_MA_14
SB_MA_15
BA34
AY34
AR22
BA36
BB36
BF27
BE41
BE47
AT43
BG47
AL3
AV3
BG11
BD17
BG51
BA59
AT60
AK59
AM2
AV1
BE11
BD18
BE51
BA61
AR59
AK61
BF32
BE33
BD33
AU30
BD30
AV30
BG30
BD29
BE30
BE28
BD43
AT28
AV28
BD46
AT26
AU22
MEM_B_CLK_P<0>
MEM_B_CLK_N<0>
MEM_B_CKE<0>
MEM_B_CLK_P<1>
MEM_B_CLK_N<1>
MEM_B_CKE<1>
MEM_B_CS_L<0>
MEM_B_CS_L<1>
MEM_B_ODT<0>
MEM_B_ODT<1>
MEM_B_DQS_N<0>
MEM_B_DQS_N<1>
MEM_B_DQS_N<2>
MEM_B_DQS_N<3>
MEM_B_DQS_N<4>
MEM_B_DQS_N<5>
MEM_B_DQS_N<6>
MEM_B_DQS_N<7>
MEM_B_DQS_P<0>
MEM_B_DQS_P<1>
MEM_B_DQS_P<2>
MEM_B_DQS_P<3>
MEM_B_DQS_P<4>
MEM_B_DQS_P<5>
MEM_B_DQS_P<6>
MEM_B_DQS_P<7>
MEM_B_A<0>
MEM_B_A<1>
MEM_B_A<2>
MEM_B_A<3>
MEM_B_A<4>
MEM_B_A<5>
MEM_B_A<6>
MEM_B_A<7>
MEM_B_A<8>
MEM_B_A<9>
MEM_B_A<10>
MEM_B_A<11>
MEM_B_A<12>
MEM_B_A<13>
MEM_B_A<14>
MEM_B_A<15>
29 79
OUT
29 79
OUT
29 79
OUT
29 79
OUT
29 79
OUT
29 79
OUT
29 79
OUT
29 79
OUT
29 79
OUT
29 79
OUT
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
29 79
OUT
29 79
OUT
29 79
OUT
29 79
OUT
29 79
OUT
29 79
OUT
29 79
OUT
29 79
OUT
29 79
OUT
29 79
OUT
29 79
OUT
29 79
OUT
29 79
OUT
29 79
OUT
29 79
OUT
29 79
OUT
D
C
B
A
6 3
SYNC_MASTER=MASTER
PAGE TITLE
CPU DDR3 INTERFACES
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
SYNC_DATE=02/15/2011
DRAWING NUMBER
051-9058
REVISION
6.0.0
BRANCH
PAGE
12 OF 109
SHEET
11 OF 86
124578
SIZE
A
D
8 7 6 5 4 3
12
=PPVCORE_S0_CPU_VCCAXG
7 9
12 15
=PPVCORE_S0_CPU
7 9
12 14
A26
VCC_1
A29
D
C
B
A31
A34
A35
A38
A39
A42
C26
C27
C32
C34
C37
C39
C42
D27
D32
D34
D37
D39
D42
E26
E28
E32
E34
E37
E38
F25
F26
F28
F32
F34
F37
F38
F42
G42
H25
H26
H28
H29
H32
H34
H35
H37
H38
H40
J25
J26
J28
J29
J32
J34
J35
J37
J38
J40
J42
K26
K27
K29
K32
K34
K35
K37
K39
K42
L25
L28
L33
L36
L40
N26
N30
N34
N38
VCC_2
VCC_3
VCC_4
VCC_5
VCC_6
VCC_7
VCC_8
VCC_9
VCC_10
VCC_11
VCC_12
VCC_13
VCC_14
VCC_15
VCC_16
VCC_17
VCC_18
VCC_19
VCC_20
VCC_21
VCC_22
VCC_23
VCC_24
VCC_25
VCC_26
VCC_27
VCC_28
VCC_29
VCC_30
VCC_31
VCC_32
VCC_33
VCC_34
VCC_35
VCC_36
VCC_37
VCC_38
VCC_39
VCC_40
VCC_41
VCC_42
VCC_43
VCC_44
VCC_45
VCC_46
VCC_47
VCC_48
VCC_49
VCC_50
VCC_51
VCC_52
VCC_53
VCC_54
VCC_55
VCC_56
VCC_57
VCC_58
VCC_59
VCC_60
VCC_61
VCC_62
VCC_63
VCC_64
VCC_66
VCC_67
VCC_68
VCC_69
VCC_70
VCC_71
VCC_72
VCC_73
VCC_74
VCC_75
VCC_76
A
OMIT_TABLE
CRITICAL
U1000
BGA
(6 OF 9)
IVY-BRIDGE
PEG AND DDR
CORE SUPLLY
VSS_SENSE_VCCIO
2C-35W
RAIL
LINES
SENSE SVID QUIET
VCCIO_SENSE
VCCIO_1
VCCIO_3
VCCIO_4
VCCIO_5
VCCIO_6
VCCIO_7
VCCIO_8
VCCIO_9
VCCIO_10
VCCIO_11
VCCIO_12
VCCIO_13
VCCIO_14
VCCIO_15
VCCIO_16
VCCIO_17
VCCIO_18
VCCIO_19
VCCIO_20
VCCIO_21
VCCIO_22
VCCIO_23
VCCIO_24
VCCIO_25
VCCIO_26
VCCIO_27
VCCIO_28
VCCIO_29
VCCIO_30
VCCIO_31
VCCIO_32
VCCIO_33
VCCIO_34
VCCIO_35
VCCIO_36
VCCIO_37
VCCIO_38
VCCIO_39
VCCIO_40
VCCIO_41
VCCIO_42
VCCIO_43
VCCIO_44
VCCIO_45
VCCIO_46
VCCIO_47
VCCIO_48
VCCIO_49
VCCIO_50
VCCIO_51
VCCIO_SEL
VCCPQE_1
VCCPQE_2
VIDALERT*
VIDSCLK
VIDSOUT
VCC_SENSE
VSS_SENSE
=PP1V05_S0_CPU_VCCIO
(NOT controlled by VCCIO_SEL)
Fixed at 1.05V
AF46
AG48
AG50
AG51
AJ17
AJ21
AJ25
AJ43
AJ47
AK50
AK51
AL14
AL15
AL16
AL20
AL22
AL26
AL45
AL48
AM16
AM17
AM21
AM43
AM47
AN20
AN42
AN45
AN48
AA14
AA15
AB17
AB20
AC13
AD16
AD18
AD21
AE14
AE15
AF16
AF18
AF20
AG15
AG16
AG17
AG20
AG21
AJ14
AJ15
W16
W17
IVB supports 1.05V VCCIO.
VCCIO_SEL can be NC.
BC22
CPU_VCCIO_SEL
AM25
=PP1V05_S0_CPU_VCCPQE
AN22
A44
B43
C44
F43
G43
AN16
AN17
CPU_VIDALERT_L_R
CPU_VIDSCLK_R
CPU_VIDSOUT_R
CPU_VCCSENSE_P
CPU_VCCSENSE_N
CPU_VCCIOSENSE_P
CPU_VCCIOSENSE_N
AA46
VAXG_1
AB47
VAXG_2
AB50
VAXG_3
AB51
VAXG_4
AB52
VAXG_5
AB53
VAXG_6
AB55
VAXG_7
AB56
VAXG_8
AB58
VAXG_9
AB59
VAXG_10
AC61
VAXG_11
AD47
VAXG_12
AD48
VAXG_13
AD50
VAXG_14
AD51
VAXG_15
AD52
VAXG_16
AD53
VAXG_17
AD55
VAXG_18
AD56
VAXG_19
AD58
VAXG_20
AD59
VAXG_21
AE46
VAXG_22
N45
VAXG_23
P47
VAXG_24
P48
VAXG_25
P50
VAXG_26
P51
VAXG_27
P52
VAXG_28
P53
VAXG_29
P55
VAXG_30
P56
VAXG_31
P61
VAXG_32
T48
VAXG_33
T58
VAXG_34
T59
VAXG_35
T61
VAXG_36
U46
VAXG_37
V47
VAXG_38
V48
VAXG_39
V50
VAXG_40
V51
VAXG_41
V52
VAXG_42
V53
VAXG_43
V55
VAXG_44
V56
VAXG_45
V58
VAXG_46
V59
VAXG_47
W50
=PP1V05_S0_CPU_VCCIO
1
R1302
130
PLACE_NEAR=U1000.C44:2.54mm
1%
1/16W
MF-LF
402
8
78
2
7 8
14
201
201
201
PLACE_NEAR=U1000.F43:50.8mm
Note. VOLTAGE=1.25V
Note. VOLTAGE=0V
Note. VOLTAGE=1.05V
Note. VOLTAGE=0V
PLACE_NEAR=U1000.G43:50.8mm
R1310
1/20W
R1311
1/20W
0
R1312
1/20W
0
PLACE_SIDE=BOTTOM
PLACE_SIDE=BOTTOM
NOSTUFF
R1360
NOSTUFF
R1361
PLACE_NEAR=R1310.2:2.54mm
1
R1300
75
1%
1/20W
MF
201
2
21
MF435%
MF5%
MF5%
CPU_VIDALERT_L
CPU_VIDSCLK
CPU_VIDSOUT
PLACE_NEAR=U1000.A44:38mm
21
21
=PP1V05_S0_CPU_VCCIO
NOSTUFF
1
1
R1362
100
100
1%
1%
1/16W
1/16W
MF-LF
MF-LF
402
402
2
2
NOSTUFF
1
1
R1363
100
100
1%
1%
1/16W
1/16W
MF-LF
MF-LF
402
402
2
2
=PPVCORE_S0_CPU
PLACE_NEAR=U1000.AN16:50.8mm
PLACE_SIDE=BOTTOM
PLACE_NEAR=U1000.AN17:50.8mm
PLACE_SIDE=BOTTOM
7 9
10 12 14
68 78
IN
68 78
OUT
68 78
BI
7 9
12 14
7 9
10 12 14
PLACEMENT NOTE: Please place all sense line resistors on BOTTOM side.
68 78
OUT
68 78
OUT
70 78
OUT
70 78
OUT
=PPVCORE_S0_CPU_VCCAXG
7 9
12 15
PLACE_NEAR=U1000.F45:50.8mm
PLACE_SIDE=BOTTOM
68 78
CPU_AXG_SENSE_P
OUT
68 78
CPU_AXG_SENSE_N
OUT
14
PLACE_NEAR=U1000.G45:50.8mm
PLACE_SIDE=BOTTOM
NOSTUFF
1
R1370
100
1%
1/16W
MF-LF
402
2
Note. VOLTAGE=1.05V
Note. VOLTAGE=0V
=PP1V8_S0_CPU_VCCPLL_R
7
NOSTUFF
R1371
1/16W
MF-LF
100
1%
402
12 15
1
2
=PPVCCSA_S0_CPU
7
VAXG_48
W51
VAXG_49
W52
VAXG_50
W53
VAXG_51
W55
VAXG_52
W56
VAXG_53
W61
VAXG_54
Y48
VAXG_55
Y61
VAXG_56
F45
VAXG_SENSE
G45
VSSAXG_SENSE
BB3
VCCPLL_1
BC1
VCCPLL_2
BC4
VCCPLL_3
L17
VCCSA_1
L21
VCCSA_2
N16
VCCSA_3
N20
VCCSA_4
N22
VCCSA_5
P17
VCCSA_6
P20
VCCSA_7
R16
VCCSA_8
R18
VCCSA_9
R21
VCCSA_10
U15
VCCSA_11
V16
VCCSA_12
V17
VCCSA_13
V18
VCCSA_14
V21
VCCSA_15
W20
VCCSA_16
PLACEMENT NOTE: Please place all sense line resistors on BOTTOM side.
6 3
OMIT_TABLE
CRITICAL
U1000
BGA
(7 OF 9)
IVY-BRIDGE
GRPHICS
DDR3-1.5V RAILS
(IPU)
QUIET
SENSE
(IPU)
LINE
SENSE
1.8V
RAIL
SA RAIL
VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
2C-35W
VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8
VDDQ_9
VDDQ_10
VDDQ_11
VDDQ_12
VDDQ_13
VDDQ_14
VDDQ_15
VDDQ_16
VDDQ_17
VDDQ_18
VDDQ_19
VDDQ_20
VDDQ_21
VDDQ_22
VDDQ_23
VDDQ_24
VDDQ_25
VDDQ_26
VCCDQ_1
VCCDQ_2
RAIL
VDDQ_SENSE
VSS_SENSE_VDDQ
VCCSA_SENSE
LINE
VCCSA_VID_0
VCCSA_VID_1
SM_VREF
=PP1V5_S3_CPU_VCCDDR
AJ28
AJ33
AJ36
AJ40
AL30
AL34
AL38
AL42
AM33
AM36
AM40
AN30
AN34
AN38
AR26
AR28
AR30
AR32
AR34
AR36
AR40
AV41
AW26
BA40
BB28
BG33
AM28
AN26
BC43
BA43
U10
D48
D49
AY43
R1314
=PP1V5_S3_CPU_VCCDQ
CPU_VDDQ_SENSE_P
CPU_VDDQ_SENSE_N
CPU_VCCSASENSE
CPU_VCCSA_VID<0>
CPU_VCCSA_VID<1>
CPU_SM_VREF
VOLTAGE=0.75V
1
1
R1313
10K
10K
1/20W
MF
5%
201
5%
1/20W
MF
201
2
2
=PP1V5_S3_CPU_VCCDDR
7
10 12 15 26
PLACE_NEAR=U1000.U10:50.8mm
PLACE_NEAR=U1000.BC43:50.8mm
PLACE_SIDE=BOTTOM
Note. VOLTAGE=1.05V
Note. VOLTAGE=0V
PLACE_NEAR=U1000.BA43:50.8mm
PLACE_SIDE=BOTTOM
12 15
65
OUT
12
=PPVCCSA_S0_CPU
7
R1382
1
R1380
100
1%
1/16W
MF-LF
402
2
7
15
65
1
R1381
100
1%
1/16W
MF-LF
402
2
100
1/16W
MF-LF
1
1%
402
2
OUT
PLACEMENT NOTE: Please place all sense line resistors on BOTTOM side.
=PP1V5_S3_CPU_VCCDDR
7
10 12 15 26
1
R1330
PLACE_NEAR=U1000.BJ44:2.54mm
PLACE_NEAR=U1000.BJ44:2.54mm
1/16W
MF-LF
R1331
1/16W
MF-LF
1K
5%
402
2
1
1K
5%
402
2
CPU_SM_VREF
1
C1330
0.1UF
10%
16V
2
X7R-CERM
0402
PLACE_NEAR=U1000.BJ44:2.54mm
SYNC_MASTER=MASTER
PAGE TITLE
CPU POWER
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
SYNC_DATE=02/15/2011
DRAWING NUMBER
051-9058
REVISION
6.0.0
BRANCH
PAGE
13 OF 109
SHEET
12 OF 86
124578
D
C
65
B
12
A
SIZE
D
8 7 6 5 4 3
OMIT_TABLE
OMIT_TABLE
CRITICAL
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
M11
M15
M58
N1
N17
N21
N25
N28
N33
N36
N40
N43
N47
N48
N51
N52
N56
N61
P9
P14
P16
P18
P21
P58
P59
R4
R17
R20
R46
T1
T47
T50
T51
T52
T53
T55
T56
U8
U13
V20
V61
W8
W13
W15
W18
W21
W46
Y4
Y47
Y58
Y59
A5
A57
BC61
BD3
BD59
BE4
BE58
BG5
BG57
C3
C58
D59
E1
E61
BG13
VSS
BG17
VSS
BG21
VSS
BG24
VSS
BG28
VSS
D
C
B
BG37
BG41
BG45
BG49
BG53
C29
C35
C40
D10
D14
D18
D22
D26
D29
D35
D40
D43
D46
D50
D54
D58
E25
E29
E35
E40
F13
F15
F19
F29
F35
F40
F55
G48
G51
G61
H10
H14
H17
H21
H53
H58
J49
J55
K11
K21
K51
L16
L20
L22
L26
L30
L34
L38
L43
L48
L61
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
D4
VSS
D6
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
E3
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
G6
VSS
VSS
VSS
VSS
H4
VSS
VSS
VSS
VSS
VSS
VSS
VSS
J1
VSS
VSS
VSS
K8
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
M4
VSS
M6
VSS
U1000
BGA
(9 OF 9)
VSS
2C-35W
IVY-BRIDGE
A
AA13
AA50
AA51
AA52
AA53
AA55
AA56
AB16
AB18
AB21
AB48
AB61
AC10
AC14
AC46
AD17
AD20
AD61
AE13
AF17
AF21
AF47
AF48
AF50
AF51
AF52
AF53
AF55
AF56
AF58
AF59
AG10
AG14
AG18
AG47
AG52
AG61
AH58
AJ13
AJ16
AJ20
AJ22
AJ26
AJ30
AJ34
AJ38
AJ42
AJ45
AJ48
AK52
AL10
AL13
AL17
AL21
AL25
AL28
AL33
AL36
AL40
AL43
AL47
AL61
AM13
AM20
AM22
AM26
AM30
A13
A17
A21
A25
A28
A33
A37
A40
A45
A49
A53
AA1
AA8
AC6
AD4
AE8
AF1
AG7
AH4
AJ7
AK1
AM4
A9
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
CRITICAL
U1000
BGA
(8 OF 9)
VSS
IVY-BRIDGE
2C-35W
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AM34
AM38
AM42
AM45
AM48
AM58
AN1
AN21
AN25
AN28
AN33
AN36
AN40
AN43
AN47
AN50
AN54
AP7
AP10
AP51
AP55
AR7
AR13
AR17
AR21
AR41
AR48
AR61
AT4
AT14
AT19
AT36
AT45
AT52
AT58
AU1
AU7
AU11
AU28
AU32
AU51
AV17
AV21
AV22
AV34
AV40
AV48
AV55
AW7
AW13
AW43
AW61
AY4
AY9
AY14
AY19
AY30
AY36
AY41
AY45
AY49
AY55
AY58
BA1
BA11
BA17
BA21
BA26
BA32
BA48
BA51
BB53
BC5
BC13
BC57
BD8
BD12
BD16
BD19
BD23
BD27
BD32
BD36
BD40
BD44
BD48
BD52
BD56
BE5
BG9
SYNC_MASTER=MASTER
PAGE TITLE
CPU GROUNDS
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
6 3
12
SYNC_DATE=02/15/2011
DRAWING NUMBER
051-9058
REVISION
6.0.0
BRANCH
PAGE
14 OF 109
SHEET
13 OF 86
124578
SIZE
D
C
B
A
D
8 7 6 5 4 3
All INTEL recommendations from Intel doc #4439028 Huron River Platform Power Design Guide
CPU VCORE DECOUPLING
Intel recommendation (Section 6.2): 35x 2.2uF, 25x 22uF, 4x 470uF
=PPVCORE_S0_CPU
7 9
12
D
CRITICAL
1
C1600
2.2UF
20%
4V
2
X5R
402
CRITICAL
1
C1625
2.2UF
20%
4V
2
X5R
402
CRITICAL
1
2
CRITICAL
1
2
C1604
2.2UF
20%
4V
X5R
402
C1627
2.2UF
20%
4V
X5R
402
CRITICAL
1
C1606
2.2UF
20%
4V
2
X5R
402
CRITICAL
1
C1628
2.2UF
20%
4V
2
X5R
402
CRITICAL
1
C1607
2.2UF
20%
4V
2
X5R
402
CRITICAL
1
C1631
2.2UF
20%
4V
2
X5R
402
CRITICAL
1
C1608
2.2UF
20%
4V
2
X5R
402
CRITICAL
1
C1632
2.2UF
20%
4V
2
X5R
402
CRITICAL
1
C1609
2.2UF
20%
4V
2
X5R
402
CRITICAL
1
C1635
2.2UF
20%
4V
2
X5R
402
CRITICAL
1
C1610
2.2UF
20%
4V
2
X5R
402
CRITICAL
1
C1637
2.2UF
20%
4V
2
X5R
402
CRITICAL
1
C1612
2.2UF
20%
4V
2
X5R
402
CRITICAL
1
C1638
2.2UF
20%
4V
2
X5R
402
CRITICAL
1
C1613
2.2UF
20%
4V
2
X5R
402
CRITICAL
1
C1639
2.2UF
20%
4V
2
X5R
402
CRITICAL
1
C1615
2.2UF
20%
4V
2
X5R
402
CRITICAL
1
C1640
2.2UF
20%
4V
2
X5R
402
CRITICAL
1
C1617
2.2UF
20%
4V
2
X5R
402
CRITICAL
1
C1641
2.2UF
20%
4V
2
X5R
402
CRITICAL
1
C1623
2.2UF
20%
4V
2
X5R
402
CRITICAL
1
C1642
2.2UF
20%
4V
2
X5R
402
CRITICAL
1
C1624
2.2UF
20%
4V
2
X5R
402
CRITICAL
1
C1643
2.2UF
20%
4V
2
X5R
402
CRITICAL
1
C1644
2.2UF
20%
4V
2
X5R
402
CRITICAL
1
C1645
2.2UF
20%
4V
2
X5R
402
CRITICAL
1
C1647
2.2UF
20%
4V
2
X5R
402
CRITICAL
1
C1648
2.2UF
20%
4V
2
X5R
402
12
D
CRITICAL
1
C1650
2.2UF
20%
4V
2
X5R
402
PLACEMENT_NOTE (C1655-C1666):
Place close to U1000 on top side.
CRITICAL
OMIT
1
C1655
22UF
20%
6.3V
2
X5R-CERM-1
603
C
PLACEMENT_NOTE (C1667-C1679):
Place close to U1000 on bottom side.
CRITICAL
OMIT
1
C1667
22UF
20%
6.3V
2
X5R-CERM-1
603
CRITICAL
1
C1651
2.2UF
20%
4V
2
X5R
402
CRITICAL
OMIT
1
C1656
22UF
20%
6.3V
2
X5R-CERM-1
603
CRITICAL
OMIT
1
C1668
22UF
20%
6.3V
2
X5R-CERM-1
603
CRITICAL
1
C1652
2.2UF
20%
4V
2
X5R
402
CRITICAL
OMIT
1
C1657
22UF
20%
6.3V
2
X5R-CERM-1
603
CRITICAL
OMIT
1
C1669
22UF
20%
6.3V
2
X5R-CERM-1
603
CRITICAL
1
C1653
2.2UF
20%
4V
2
X5R
402
CRITICAL
OMIT
1
C1658
22UF
20%
6.3V
2
X5R-CERM-1
603
CRITICAL
OMIT
1
C1670
22UF
20%
6.3V
2
X5R-CERM-1
603
CRITICAL
1
C1654
2.2UF
20%
4V
2
X5R
402
CRITICAL
NOSTUFF
1
C1659
22UF
20%
6.3V
2
X5R-CERM-1
603
CRITICAL
NOSTUFF
1
C1671
22UF
20%
6.3V
2
X5R-CERM-1
603
CRITICAL
OMIT
1
C1660
22UF
20%
6.3V
2
X5R-CERM-1
603
CRITICAL
OMIT
1
C1672
22UF
20%
6.3V
2
X5R-CERM-1
603
CRITICAL
OMIT
1
C1661
22UF
20%
6.3V
2
X5R-CERM-1
603
CRITICAL
NOSTUFF
1
C1673
22UF
20%
6.3V
2
X5R-CERM-1
603
CRITICAL
NOSTUFF
1
C1662
22UF
20%
6.3V
2
X5R-CERM-1
603
CRITICAL
NOSTUFF
1
C1674
22UF
20%
6.3V
2
X5R-CERM-1
603
CRITICAL
NOSTUFF
1
C1663
22UF
20%
6.3V
2
X5R-CERM-1
603
CRITICAL
NOSTUFF
1
C1675
22UF
20%
6.3V
2
X5R-CERM-1
603
CRITICAL
OMIT
1
C1664
22UF
20%
6.3V
2
X5R-CERM-1
603
CRITICAL
NOSTUFF
1
C1676
22UF
20%
6.3V
2
X5R-CERM-1
603
CRITICAL
NOSTUFF
1
C1665
22UF
20%
6.3V
2
X5R-CERM-1
603
CRITICAL
OMIT
1
C1677
22UF
20%
6.3V
2
X5R-CERM-1
603
CRITICAL
OMIT
1
C1666
22UF
20%
6.3V
2
X5R-CERM-1
603
CRITICAL
OMIT
1
C1678
22UF
20%
6.3V
2
X5R-CERM-1
603
CRITICAL
OMIT
1
C1679
22UF
20%
6.3V
2
X5R-CERM-1
603
PART NUMBER
138S0691
QTY
16
DESCRIPTION
CAP,CER,X5R,22uF,20%,6.3V,0603,SAMSUNG
C1655,C1660,C1661,C1664,C1666,C1667,C1670,C1677,C1678,C1679,C1657,C1672,C1658,C1669,C1668,C1656
REFERENCE DES
CRITICAL
CRITICAL
BOM OPTION
C
PLACEMENT_NOTE (C1640-C1645):
Place near inductors on bottom side.
Place near inductors on bottom side.
Place near inductors on bottom side.
Place near inductors on bottom side.
1
3 2
C1680
470UF-4MOHM
20%
2.0V
POLY-TANT
D2T-SM1
1
3 2
C1681
470UF-4MOHM
20%
2.0V
POLY-TANT
D2T-SM1
1
C1682
470UF-4MOHM
3 2
20%
2.0V
POLY-TANT
D2T-SM1
1
3 2
C1683
470UF-4MOHM
20%
2.0V
POLY-TANT
D2T-SM1
CPU VCCIO/VCCPQ DECOUPLING
Intel recommendation (Section 6.5): 26x 1uF, 10x 10uF, 2x 330uF
PLACEMENT_NOTE (C1684-C167F):
Place on bottom side of U1000
Place on bottom side of U100.
Place on bottom side of U1000
=PP1V05_S0_CPU_VCCIO
7 9
10 12
B
Place on bottom side of U1000
1
C1684
1UF
2
1
C1697
1UF
2
10%
10V
X5R
402
10%
10V
X5R
402
1
C1685
1UF
10%
10V
2
X5R
402
1
C1698
1UF
10%
2
X5R
402
10V
1
C1686
2
1
C1699
2
1UF
10%
10V
X5R
402
1UF
10%
10V
X5R
402
1
2
1
C169A
2
C1687
1UF
10%
10V
X5R
402
1UF
10%
10V
X5R
402
1
C1688
2
1
C169B
2
1UF
10%
10V
X5R
402
1UF
10%
10V
X5R
402
1
C1689
1UF
2
1
C169C
1UF
2
1
C1690
10%
10V
X5R
402
10%
10V
X5R
402
2
1
C169D
2
1UF
10%
10V
X5R
402
1UF
10%
10V
X5R
402
1
2
1
2
C1691
1UF
10%
10V
X5R
402
C169E
1UF
10%
10V
X5R
402
1
C1692
1UF
2
1
C169F
1UF
2
1
C1693
10%
10V
X5R
402
10%
10V
X5R
402
2
1
2
1UF
10%
10V
X5R
402
C161A
1UF
10%
10V
X5R
402
1
2
1
2
C1694
1UF
10%
10V
X5R
402
C161B
1UF
10%
10V
X5R
402
1
2
1
C161C
2
C1695
1UF
10%
10V
X5R
402
1UF
10%
10V
X5R
402
1
2
1
2
C1696
1UF
10%
10V
X5R
402
C161D
1UF
10%
10V
X5R
402
=PP1V8_S0_CPU_VCCPLL
7
PLACEMENT_NOTE (C1672-C1681):
Place near U1000 on bottom side
Place near U1000 on bottom side
Place near U1000 on bottom side
Place near U1000 on bottom side
Place near U1000 on bottom side
Place near U1000 on bottom side
Place near U1000 on bottom side
Place near U1000 on bottom side
Place near U1000 on bottom side
Place near U1000 on bottom side
1
C161E
10UF
2
1
C161F
20%
6.3V
X5R
603
2
10UF
20%
6.3V
CERM-X5R
0402-1
1
C162A
2
10UF
20%
6.3V
CERM-X5R
0402-1
1
C162B
2
10UF
20%
6.3V
CERM-X5R
0402-1
1
C162C
10UF
20%
6.3V
2
CERM-X5R
0402-1
1
C162D
2
10UF
20%
6.3V
CERM-X5R
0402-1
1
C162E
10UF
20%
6.3V
2
CERM-X5R
0402-1
1
C167A
10UF
20%
6.3V
2
CERM-X5R
0402-1
1
C167B
10UF
20%
6.3V
2
CERM-X5R
0402-1
1
C167C
10UF
20%
6.3V
2
CERM-X5R
0402-1
CPU VCCPLL DECOUPLING
Intel recommendation (section 6.4): 2x 1uF, 1x 330uF
PLACE_NEAR=U1000.AK63:2.54 mm:NO_VIA
PLACEMENT_NOTE (C1646-C1671):
Place near U1000 on top side
R1600
0
21
5%
1/16W
MF-LF
402
1
C160X
1UF
10%
10V
2
X5R
402
PLACE_NEAR=U1000.AK65:2.54 mm:NO_VIA
1
2
C160Y
1UF
10%
10V
X5R
402
CPU VCCPLL Low pass filter
=PP1V8_S0_CPU_VCCPLL_R
PLACE_NEAR=U1000.BC1:5mm
1
C160Z
330UF-0.006OHM
20%
2V
2
POLY
CASE-D2-SM
7
12
B
1
C167D
330UF
20%
2.5V
2
TANT
A
CASE-B2-SM1
1
C167E
330UF
20%
2.5V
2
TANT
CASE-B2-SM1
Intel recommendation: 1x 10mOhn resistor, 1x 1uF 0402
R1601
0.010
21
=PP1V05_S0_CPU_VCCPQE
1%
1/4W
MF
0603
1
2
C167F
1UF
10%
10V
X5R
402
1
C167G
330UF
20%
2.5V
2
TANT
CASE-B2-SM1
1
C167H
330UF
20%
2.5V
2
TANT
CASE-B2-SM1
7 8
1
C167J
330UF
20%
2.5V
2
TANT
CASE-B2-SM1
12
Note:The smallest 10mOhm available in the library are 0805s
6 3
SYNC_MASTER=JACK_J30
PAGE TITLE
CPU DECOUPLING-I
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
SYNC_DATE=09/27/2011
DRAWING NUMBER
051-9058
REVISION
6.0.0
BRANCH
PAGE
16 OF 109
SHEET
14 OF 86
124578
SIZE
A
D
8 7 6 5 4 3
VAXG DECOUPLING
Intel recommendation (section 6.3): 21x 1uF, 6x 10uF, 6x 22uF, 2x 470uF
12
=PPVCORE_S0_CPU_VCCAXG
7 9
12
D
PLACEMENT_NOTE (C1700-C1710):
Place on bottom side of U1000
Place on bottom side of U100.
Place on bottom side of U1000
Place on bottom side of U1000
CRITICAL
1
C1700
1UF
10%
10V
2
X5R
402
CRITICAL
1
C1701
1UF
10%
10V
2
X5R
402
CRITICAL
1
C1702
1UF
10%
10V
2
X5R
402
CRITICAL
1
C1703
1UF
10%
10V
2
X5R
402
CRITICAL
1
C1704
1UF
10%
10V
2
X5R
402
CRITICAL
1
C1705
1UF
10%
10V
2
X5R
402
CRITICAL
1
C1706
1UF
10%
10V
2
X5R
402
CRITICAL
1
C1707
1UF
10%
10V
2
X5R
402
CRITICAL
1
C1708
1UF
10%
10V
2
X5R
402
CRITICAL
1
C1709
1UF
10%
10V
2
X5R
402
CRITICAL
1
C1710
1UF
10%
10V
2
X5R
402
D
PLACEMENT_NOTE (C1711-C1716):
CRITICAL
1
C1711
10UF
20%
6.3V
2
CERM-X5R
0402-1
CRITICAL
1
C1712
10UF
20%
6.3V
2
CERM-X5R
0402-1
CRITICAL
1
C1713
10UF
20%
6.3V
2
CERM-X5R
0402-1
CRITICAL
1
C1714
10UF
20%
6.3V
2
CERM-X5R
0402-1
CRITICAL
1
C1715
10UF
20%
6.3V
2
CERM-X5R
0402-1
CRITICAL
1
C1716
10UF
20%
6.3V
2
CERM-X5R
0402-1
PLACEMENT_NOTE (C1717-C1722):
CRITICAL
OMIT
1
C1717
22UF
20%
6.3V
2
X5R-CERM-1
603
CRITICAL
OMIT
1
C1718
22UF
20%
6.3V
2
X5R-CERM-1
603
CRITICAL
OMIT
1
C1719
22UF
20%
6.3V
2
X5R-CERM-1
603
CRITICAL
OMIT
1
C1720
22UF
20%
6.3V
2
X5R-CERM-1
603
CRITICAL
OMIT
1
C1721
22UF
20%
6.3V
2
X5R-CERM-1
603
CRITICAL
OMIT
1
C1722
22UF
20%
6.3V
2
X5R-CERM-1
603
PART NUMBER
138S0691 CRITICAL
QTY
6
DESCRIPTION
CAP,CER,X5R,22uF,20%,6.3V,0603,SAMSUNG
REFERENCE DES
C1717,C1718,C1719,C1720,C1721,C1722
CRITICAL
BOM OPTION
PLACEMENT_NOTE (C1723-C1724):
Place near inductors on bottom side.
Place near inductors on bottom side.
1
C1723
470UF-4MOHM
C
3 2
20%
2.0V
POLY-TANT
D2T-SM1
1
3 2
C1724
470UF-4MOHM
20%
2.0V
POLY-TANT
D2T-SM1
C
CPU VDDQ/VCCDQ DECOUPLING
Intel recommendation (Section 6.5): 10x 1uF, 8x 10uF, 1x 330uF
=PP1V5_S3_CPU_VCCDDR
7
10 12 26
B
A
PLACEMENT_NOTE (C1738-C1747):
Place on bottom side of U1000
Place on bottom side of U1000
Place on bottom side of U1000
Place on bottom side of U100.
1
C1738
1UF
10%
10V
2
X5R
402
Place close to U1000 on bottom side
Place close to U1000 on bottom side
Place close to U1000 on bottom side
Place close to U1000 on bottom side
Place close to U1000 on bottom side
Place close to U1000 on bottom side
Place close to U1000 on bottom side
Place close to U1000 on bottom side
1
C1748
10UF
20%
6.3V
2
CERM-X5R
0402-1
1
C1756
330UF-0.006OHM
20%
2V
2
POLY
CASE-D2-SM
1
C1739
2
1
C1749
2
1UF
10%
10V
X5R
402
10UF
20%
6.3V
CERM-X5R
0402-1
1
2
1
C1750
2
C1740
1UF
10%
10V
X5R
402
10UF
20%
6.3V
X5R
603
1
2
1
C1751
2
C1741
1UF
10%
10V
X5R
402
10UF
20%
6.3V
CERM-X5R
0402-1
Intel recommendation: 1x 10mOhn resistor, 1x 1uF 0402
R1702
0.010
21
1/4W
MF
0603
1
2
C1757
1UF
10%
10V
X5R
402
=PP1V5_S3_CPU_VCCDQ
1%
7
12
6 3
1
2
1
2
C1742
1UF
10%
10V
X5R
402
C1752
10UF
20%
6.3V
CERM-X5R
0402-1
1
C1743
1UF
10%
10V
2
X5R
402
1
C1753
10UF
20%
6.3V
2
CERM-X5R
0402-1
1
2
1
2
C1744
1UF
10%
10V
X5R
402
C1754
10UF
20%
6.3V
X5R
603
1
2
1
C1755
10UF
20%
6.3V
2
CERM-X5R
0402-1
C1745
1UF
10%
10V
X5R
402
1
C1746
1UF
10%
10V
2
X5R
402
1
C1747
2
1UF
10%
10V
X5R
402
=PPVCCSA_S0_CPU
7
12
CPU VCCSA DECOUPLING
Intel recommendation (Section 6.6): 6x 1uf, 5x 10uf, 1x 330uf
PLACEMENT_NOTE (C1758-C1762):
Place on bottom side of U1000
Place on bottom side of U100.
Place on bottom side of U1000
Place on bottom side of U1000
1
C1758
1UF
10%
10V
2
X5R
402
1
C1763
10UF
20%
6.3V
2
CERM-X5R
0402-1
1
C1768
330UF-0.006OHM
20%
2V
2
POLY
CASE-D2-SM
1
2
1
2
C1759
1UF
10%
10V
X5R
402
C1764
10UF
20%
6.3V
CERM-X5R
0402-1
1
2
1
2
C1760
1UF
10%
10V
X5R
402
C1765
10UF
20%
6.3V
CERM-X5R
0402-1
1
C1761
1UF
10%
10V
2
X5R
402
1
C1766
10UF
20%
6.3V
2
CERM-X5R
0402-1
SYNC_MASTER=MASTER
PAGE TITLE
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
1
C1762
1UF
10%
10V
2
X5R
402
1
C1767
10UF
20%
6.3V
2
CERM-X5R
0402-1
CPU DECOUPLING-II
Apple Inc.
R
SYNC_DATE=02/15/2011
DRAWING NUMBER
051-9058
REVISION
6.0.0
BRANCH
PAGE
17 OF 109
SHEET
15 OF 86
124578
SIZE
B
A
D
8 7 6 5 4 3
12
SYSCLK_CLK32K_RTC
24 81
IN
RTC_RESET_L
16
PCH_SRTCRST_L
16
PCH_INTRUDER_L
16
PCH_INTVRMEN_L
D
VSel strap not functional (VCCVRM = 1.8V)
C
16
HDA_BIT_CLK_R
16 81
HDA_SYNC_R
16 81
PCH_SPKR
16
HDA_RST_R_L
16 81
HDA_SDIN0
57 81
IN
TP_HDA_SDIN1
6
TP_HDA_SDIN2
6
TP_HDA_SDIN3
6
HDA_SDOUT_R
16 24 81
JTAG_TBT_TMS
16 33
OUT
ENET_MEDIA_SENSE_RDIV
16 24
IN
XDP_PCH_TCK
23
IN
XDP_PCH_TMS
23
IN
XDP_PCH_TDI
23
IN
XDP_PCH_TDO
23
OUT
SPI_CLK_R
47 81
OUT
SPI_CS0_R_L
47 81
OUT
TP_SPI_CS1_L
SPI_MOSI_R
47 81
OUT
SPI_MISO
47 81
IN
=PPVRTC_G3_PCH
1
330K
1/20W
1
R1801
1M
5%
5%
1/20W
MF
MF
201
201
2
2
R1800
B
=PP3V3_SUS_PCH_GPIO
=PP3V3_S0_PCH_GPIO
=PP3V3_T29_PCH_GPIO
R1876
R1877
R1878
R1834
R1833
R1842
R1869
R1844
R1845
R1847
A
R1814
R1815
R1843
R1846
R1848
R1853
R1854
R1855
R1879
A20
OMIT_TABLE
RTCX1
C20
RTCX2
NC
D20
RTCRST*
G22
SRTCRST*
K22
INTRUDER*
C17
INTVRMEN
N34
HDA_BCLK
L34
HDA_SYNC
T10
SPKR
(IPD-PLTRST#)
K34
HDA_RST*
E34
HDA_SDIN0
G34
HDA_SDIN1
C34
HDA_SDIN2
A34
HDA_SDIN3
A36
HDA_SDO
C36
HDA_DOCK_EN*/GPIO33
N32
HDA_DOCK_RST*/GPIO13
J3
JTAG_TCK
H7
JTAG_TMS
K5
JTAG_TDI
H1
JTAG_TDO
T3
SPI_CLK
Y14
SPI_CS0*
T1
SPI_CS1*
V4
SPI_MOSI
U3
SPI_MISO
7
17 20
1
R1802
1/20W
C1802
1UF
10K
4.7K
10K
10K
10K
10K
10K
10K
10K
10K
10K
10K
10K
10K
10K
10K
10K
10K
10K
Connect to ENET_MEDIA_SENSE via alias if HDA = 3.3V.
Connect to ENET_MEDIA_SENSE via 12K R if HDA = 1.5V.
If HDA = S0, must also ensure that signal cannot be high in S3.
1
5%
MF
2
1
2
21
21
21
21
21
21
21
21
21
21
12
21
21
21
21
21
21
21
21
R1803
20K
5%
1/20W
MF
201
2
RTC_RESET_L
PCH_SRTCRST_L
PCH_INTRUDER_L
PCH_INTVRMEN_L
1
C1803
1UF
10%
10V
2
X5R
402
7
17 18 19
7
17 18 19 30
7
19
5%
1/20W
5%
1/20W
1/20W
5%
5%
1/20W
5%
1/20W
5%
1/20W
5%
1/20W
5%
1/20W
5%
1/20W
5%
1/20W
5%
1/20W
5%
1/20W
5%
1/20W
5%
1/20W
5%
1/20W
5%
1/20W
5%
1/20W
5%
1/20W
5%
1/20W
MF
201
MF
201
201
MF
MF
201
MF
201
MF
201
MF
201
MF
201
MF
201
MF
201
MF
201
MF
201
MF
201
MF
201
MF
201
MF
201
MF
201
MF
201
MF
201
16
16
16
16
JTAG_TBT_TMS
PCH_SPKR
PCH_SATALED_L
DP_AUXCH_ISOL
SATARDRVR_EN
FW_CLKREQ_L
AP_CLKREQ_L
EXCARD_CLKREQ_L
JTAG_DPMUXUC_TRST_L
ENET_CLKREQ_L
PEG_CLKREQ_L
TBT_CLKREQ_L
PCIECLKRQ0_L_GPIO73
PEGCLKRQA_L_GPIO47
PEGCLKRQB_L_GPIO56
PCH_GPIO11
USB_EXTB_SEL_XHCI
USB_EXTD_SEL_XHCI
ENET_MEDIA_SENSE_RDIV
20K
201
10%
10V
X5R
402
PANTHERPOINT
(IPD-BOOT)
(IPD)
(IPD)
(IPD)
(IPD)
(IPD-BOOT)
(IPD)
(IPU)
(IPU)
(IPD-BOOT)
(IPU)
U1800
MOBILE
FCBGA
(1 OF 10)
RTC
IHDA
JTAG
SPI
FWH4/LFRAME*
(IPU)
LDRQ1*/GPIO23
(IPU)
LPC
SATA
SATAICOMPO
SATAICOMPI
SATA3RCOMPO
SATA3COMPI
SATA3RBIAS
SATA0GP/GPIO21
SATA1GP/GPIO19
(IPU)
LPC_AD_R<0>
16
LPC_AD_R<1>
16
LPC_AD_R<2>
16
LPC_AD_R<3>
16
LPC_FRAME_R_L
16
HDA_BIT_CLK_R
16 81
HDA_SYNC_R
16 81
HDA_RST_R_L
16 81
HDA_SDOUT_R
16 24 81
16 33
16
16
23 75
23 41
16 39
16 32
16
16
16 36
16
16 35
16
16
16
16
16 25
16
16 24
LDRQ0*
SERIRQ
SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP
SATA1RXN
SATA1RXP
SATA1TXN
SATA1TXP
SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP
SATA3RXN
SATA3RXP
SATA3TXN
SATA3TXP
SATA4RXN
SATA4RXP
SATA4TXN
SATA4TXP
SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP
SATALED*
C38
A38
B37
C37
D36
E36
K36
V5
AM3
AM1
AP7
AP5
AM10
AM8
AP11
AP10
AD7
AD5
AH5
AH4
AB8
AB10
AF3
AF1
Y7
Y5
AD3
AD1
Y3
Y1
AB3
AB1
Y11
Y10
AB12
AB13
AH1
P3
V14
P1
FWH0/LAD0
FWH1/LAD1
FWH2/LAD2
FWH3/LAD3
(IPU)
PLACE_NEAR=U1800.N34:1.27mm
PLACE_NEAR=U1800.L34:1.27mm
PLACE_NEAR=U1800.K34:1.27mm
PLACE_NEAR=U1800.A36:1.27mm
LPC_AD_R<0>
LPC_AD_R<1>
LPC_AD_R<2>
LPC_AD_R<3>
LPC_FRAME_R_L
TP_LPC_DREQ0_L
TBT_PWR_EN_PCH
LPC_SERIRQ
SATA_HDD_D2R_N
SATA_HDD_D2R_P
SATA_HDD_R2D_C_N
SATA_HDD_R2D_C_P
SATA_ODD_D2R_N
SATA_ODD_D2R_P
SATA_ODD_R2D_C_N
SATA_ODD_R2D_C_P
TP_SATA_C_D2RN
TP_SATA_C_D2RP
TP_SATA_C_R2D_CN
TP_SATA_C_R2D_CP
TP_SATA_D_D2RN
TP_SATA_D_D2RP
TP_SATA_D_R2D_CN
TP_SATA_D_R2D_CP
TP_SATA_E_D2RN
TP_SATA_E_D2RP
TP_SATA_E_R2D_CN
TP_SATA_E_R2D_CP
TP_SATA_F_D2RN
TP_SATA_F_D2RP
TP_SATA_F_R2D_CN
TP_SATA_F_R2D_CP
PCH_SATAICOMP
80
PCH_SATA3COMP
PCH_SATA3RBIAS
PCH_SATALED_L
XDP_DC2_PCH_GPIO21_DP_AUXCH_ISOL
XDP_DC3_PCH_GPIO19_SATARDRVR_EN
R1860
R1861
R1862
R1863
R1864
R1810
R1811
R1812
R1813
33
33
33
33
33
33
33
33
33
21
21
21
21
21
21
21
21
21
16
16
16
16
16
24
OUT
41 80
IN
41 80
IN
41 80
OUT
41 80
OUT
41 80
IN
41 80
IN
41 80
OUT
41 80
OUT
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
16
5%
1/20W
5%
1/20W
5%
1/20W
5%
1/20W
5%
1/20W
5%
1/20W
5%
1/20W
1/20W
5%
5%
1/20W
ITPCPU_CLK100M_N
10 78
ITPCPU_CLK100M_P
10 78
=PP3V3_S0_PCH
1
R1820
10K
5%
1/20W
MF
201
2
6
45 47
BI
=PP1V05_S0_PCH_VCCIO_SATA
PLACE_NEAR=U1800.Y11:2.54mm
1
R1830
37.4
1%
1/20W
MF
201
2
=PP1V05_S0_PCH
1
R1831
49.9
1%
1/20W
MF
201
2
PLACE_NEAR=U1800.AB12:2.54mm
PLACE_NEAR=U1800.AH1:2.54mm
1
R1832
750
1%
23
OUT
OUT
MF
201
MF
201
MF
201
MF
201
MF
201
MF
201
MF
201
MF
201
MF
201
23
2
LPC_AD<0>
LPC_AD<1>
LPC_AD<2>
LPC_AD<3>
LPC_FRAME_L
HDA_BIT_CLK
HDA_SYNC
HDA_RST_L
HDA_SDOUT
1/20W
MF
201
NO STUFF
R1841
0
5%
1/20W
MF
201
7
22
7
20 22
7
22
6
45 47 81
BI
6
45 47 81
BI
6
45 47 81
BI
6
45 47 81
BI
6
45 47 81
OUT
57 81
OUT
57 81
OUT
57 81
OUT
57 81
OUT
NO STUFF
R1840
0
21
5%
1/20W
MF
201
21
36 81
IN
36 81
IN
36 81
OUT
36 81
OUT
32 81
IN
32 81
IN
32 81
OUT
32 81
OUT
38 81
IN
38 81
IN
38 81
OUT
38 81
OUT
8
IN
8
IN
8
OUT
8
OUT
36 81
OUT
36 81
OUT
16
38 81
OUT
38 81
OUT
16 39
IN
32 81
OUT
32 81
OUT
16 32
IN
8
81
OUT
8
81
OUT
16
IN
6
6
16
OUT
6
6
16 36
IN
6
6
16
8
81
OUT
8
81
OUT
16
IN
33 81
OUT
33 81
OUT
16 35
IN
23 78
23 78
PCIE_ENET_D2R_N
PCIE_ENET_D2R_P
PCIE_ENET_R2D_C_N
PCIE_ENET_R2D_C_P
PCIE_AP_D2R_N
PCIE_AP_D2R_P
PCIE_AP_R2D_C_N
PCIE_AP_R2D_C_P
PCIE_FW_D2R_N
PCIE_FW_D2R_P
PCIE_FW_R2D_C_N
PCIE_FW_R2D_C_P
PCIE_EXCARD_D2R_N
PCIE_EXCARD_D2R_P
PCIE_EXCARD_R2D_C_N
PCIE_EXCARD_R2D_C_P
NC_PCIE_5_D2RN
NC_PCIE_5_D2RP
NC_PCIE_5_R2D_CN
NC_PCIE_5_R2D_CP
NC_PCIE_6_D2RN
NC_PCIE_6_D2RP
NC_PCIE_6_R2D_CN
NC_PCIE_6_R2D_CP
NC_PCIE_7_D2RN
NC_PCIE_7_D2RP
NC_PCIE_7_R2D_CN
NC_PCIE_7_R2D_CP
NC_PCIE_8_D2RN
NC_PCIE_8_D2RP
NC_PCIE_8_R2D_CN
NC_PCIE_8_R2D_CP
PCIE_CLK100M_ENET_N
PCIE_CLK100M_ENET_P
PCIECLKRQ0_L_GPIO73
PCIE_CLK100M_FW_N
PCIE_CLK100M_FW_P
FW_CLKREQ_L
PCIE_CLK100M_AP_N
PCIE_CLK100M_AP_P
AP_CLKREQ_L
PCIE_CLK100M_EXCARD_N
PCIE_CLK100M_EXCARD_P
EXCARD_CLKREQ_L
TP_PCIE_CLK100M_PE4N
TP_PCIE_CLK100M_PE4P
JTAG_DPMUXUC_TRST_L
TP_PCIE_CLK100M_PE5N
TP_PCIE_CLK100M_PE5P
ENET_CLKREQ_L
TP_PCIE_CLK100M_PEBN
TP_PCIE_CLK100M_PEBP
PEGCLKRQB_L_GPIO56
PEG_CLK100M_N
PEG_CLK100M_P
PEG_CLKREQ_L
PCIE_CLK100M_T29_N
PCIE_CLK100M_T29_P
TBT_CLKREQ_L
ITPXDP_CLK100M_N
ITPXDP_CLK100M_P
24 81
IN
Unused clock terminations for FCIM Mode
PCH_CLK96M_DOT_P
16 80
PCH_CLK96M_DOT_N
16 80
PCH_CLK100M_SATA_P
16 80
PCH_CLK100M_SATA_N
16 80
PCIE_CLK100M_PCH_P
16 80
PCIE_CLK100M_PCH_N
16 80
PCH_CLK14P3M_REFCLK
16 80
PCH_CLKIN_GNDP1
16
PCH_CLKIN_GNDN1
16
R1891
R1892
R1893
R1894
R1895
R1896
R1897
R1870
R1871
10K
10K
10K
10K
10K
10K
10K
10K
10K
6 3
BG34
PERN1
BJ34
PERP1
AV32
PETN1
AU32
PETP1
BE34
PERN2
BF34
PERP2
BB32
PETN2
AY32
PETP2
BG36
PERN3
BJ36
PERP3
AV34
PETN3
AU34
PETP3
BF36
PERN4
BE36
PERP4
AY34
PETN4
BB34
PETP4
BG37
PERN5
BH37
PERP5
AY36
PETN5
BB36
PETP5
BJ38
PERN6
BG38
PERP6
AU36
PETN6
AV36
PETP6
BG40
PERN7
BJ40
PERP7
AY40
PETN7
BB40
PETP7
BE38
PERN8
BC38
PERP8
AW38
PETN8
AY38
PETP8
Y40
CLKOUT_PCIE0N
Y39
CLKOUT_PCIE0P
J2
PCIECLKRQ0*/GPIO73
AB49
CLKOUT_PCIE1N
AB47
CLKOUT_PCIE1P
M1
PCIECLKRQ1*/GPIO18
AA48
CLKOUT_PCIE2N
AA47
CLKOUT_PCIE2P
V10
PCIECLKRQ2*/GPIO20
Y37
CLKOUT_PCIE3N
Y36
CLKOUT_PCIE3P
A8
PCIECLKRQ3*/GPIO25
Y43
CLKOUT_PCIE4N
Y45
CLKOUT_PCIE4P
L12
PCIECLKRQ4*/GPIO26
V45
CLKOUT_PCIE5N
V46
CLKOUT_PCIE5P
L14
PCIECLKRQ5*/GPIO44
(IPU-RSMRST#)
AB42
CLKOUT_PEG_B_N
AB40
CLKOUT_PEG_B_P
E6
PEG_B_CLKRQ*/GPIO56
V40
CLKOUT_PCIE6N
V42
CLKOUT_PCIE6P
T13
PCIECLKRQ6*/GPIO45
V38
CLKOUT_PCIE7N
V37
CLKOUT_PCIE7P
K12
PCIECLKRQ7*/GPIO46
(IPU-RSMRST#)
AK14
CLKOUT_ITPXDP_N
AK13
CLKOUT_ITPXDP_P
SYSCLK_CLK25M_SB
21
5%
1/20W
21
5%
1/20W
21
5%
1/20W
21
5%
1/20W
21
5%
1/20W
21
5%
1/20W
21
5%
1/20W
21
5%
1/20W
21
5%
1/20W
OMIT_TABLE
U1800
PANTHERPOINT
MOBILE
FCBGA
(2 OF 10)
SMBUS
SML1ALERT*/PCHHOT*/GPIO74
PCI-E*
C-LINK
Controlled by PCIECLKRQ5#
CLOCKS
FLEX
CLOCKS
R1872
604
21
1%
1/16W
MF-LF
402
MF
201
MF
201
201
MF
MF
201
MF
201
MF
201
MF
201
MF
201
MF
201
SMBALERT*/GPIO11
SMBCLK
SMBDATA
SML0ALERT*/GPIO60
SML0CLK
SML0DATA
SML1CLK/GPIO58
SML1DATA/GPIO75
(IPU/IPD)
(IPU/IPD)
CL_CLK1
CL_DATA1
CL_RST1*
PEG_A_CLKRQ*/GPIO47
CLKOUT_PEG_A_N
CLKOUT_PEG_A_P
CLKOUT_DMI_N
CLKOUT_DMI_P
CLKOUT_DP_N
CLKOUT_DP_P
CLKIN_DMI_N
CLKIN_DMI_P
CLKIN_GND1_N
CLKIN_GND1_P
CLKIN_DOT_96N
CLKIN_DOT_96P
CLKIN_SATA_N
CLKIN_SATA_P
REFCLK14IN
CLKIN_PCILOOPBACK
XTAL25_IN
XTAL25_OUT
XCLK_RCOMP
CLKOUTFLEX0/GPIO64
(IPD-PWROK)
CLKOUTFLEX1/GPIO65
(IPD-PWROK)
CLKOUTFLEX2/GPIO66
(IPD-PWROK)
CLKOUTFLEX3/GPIO67
(IPD-PWROK)
SYSCLK_CLK25M_SB_R
1.8V -> 1.1V
1
R1873
1K
1%
1/20W
MF
201
2
SYNC_MASTER=J31_MLB
PAGE TITLE
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
E12
H14
C9
A12
C8
G12
C13
E14
M16
M7
T11
P10
M10
AB37
AB38
AV22
AU22
AM12
AM13
BF18
BE18
BJ30
BG30
G24
E24
AK7
AK5
K45
H45
V47
V49
Y47
K43
F47
H47
K49
PCH_GPIO11
SMBUS_PCH_CLK
SMBUS_PCH_DATA
USB_EXTB_SEL_XHCI
SML_PCH_0_CLK
SML_PCH_0_DATA
USB_EXTD_SEL_XHCI
SML_PCH_1_CLK
SML_PCH_1_DATA
TP_CLINK_CLK
TP_CLINK_DATA
TP_CLINK_RESET_L
PEGCLKRQA_L_GPIO47
TP_PCIE_CLK100M_PEGAN
TP_PCIE_CLK100M_PEGAP
DMI_CLK100M_CPU_N
DMI_CLK100M_CPU_P
TP_PCH_CLKOUT_DPN
TP_PCH_CLKOUT_DPP
PCIE_CLK100M_PCH_N
PCIE_CLK100M_PCH_P
PCH_CLKIN_GNDN1
PCH_CLKIN_GNDP1
PCH_CLK96M_DOT_N
PCH_CLK96M_DOT_P
PCH_CLK100M_SATA_N
PCH_CLK100M_SATA_P
PCH_CLK14P3M_REFCLK
PCH_CLK33M_PCIIN
DOES THIS NEED LENGTH MATCH???
SYSCLK_CLK25M_SB_R
NC
=PP1V05_S0_PCH_VCCDIFFCLK
7
20 22
PLACE_NEAR=U1800.Y47:2.54mm
PCH_XCLK_RCOMP
TP_PCH_GPIO64_CLKOUTFLEX0
TP_PCH_GPIO65_CLKOUTFLEX1
TP_PCH_GPIO66_CLKOUTFLEX2
TP_PCH_GPIO67_CLKOUTFLEX3
16 81
SYNC_DATE=06/13/2011
PCH SATA/PCIe/CLK/LPC/SPI
Apple Inc.
R
DRAWING NUMBER
051-9058
REVISION
BRANCH
PAGE
18 OF 109
SHEET
124578
16
48 81
OUT
48 81
BI
16 25
OUT
48 81
OUT
48 81
BI
16
OUT
48 81
OUT
48 81
BI
6
6
6
16
10 78
OUT
10 78
OUT
8
OUT
8
OUT
16 80
IN
16 80
IN
16
16
16 80
IN
16 80
IN
16 80
IN
16 80
IN
16 80
IN
24 80
IN
16 81
1
R1890
90.9
1%
1/20W
MF
201
2
6
6
6
6
6.0.0
16 OF 86
SIZE
D
C
B
A
D
8 7 6 5 4 3
12
=PP3V3_SUS_PCH_GPIO
=PP1V05_S0_PCH_VCCIO_PCIE
PLACE_NEAR=U1800.BJ24:12.7mm
1
1
10K
R1900
49.9
1%
5%
1/20W
MF
MF
201
201
2
2
DMI_N2S_N<0>
9
78
IN
DMI_N2S_N<1>
9
78
IN
DMI_N2S_N<2>
9
78
IN
DMI_N2S_N<3>
9
78
IN
DMI_N2S_P<0>
9
78
IN
DMI_N2S_P<1>
9
78
IN
DMI_N2S_P<2>
9
78
IN
DMI_N2S_P<3>
9
78
IN
DMI_S2N_N<0>
9
78
OUT
DMI_S2N_N<1>
9
78
OUT
DMI_S2N_N<2>
9
78
OUT
DMI_S2N_N<3>
9
78
OUT
DMI_S2N_P<0>
9
78
OUT
DMI_S2N_P<1>
9
78
OUT
DMI_S2N_P<2>
9
78
OUT
DMI_S2N_P<3>
9
78
OUT
R1905
1/20W
D
PCH_DMI_COMP
24 45
IN
23 24 45
IN
24
IN
24
IN
10 26 78
OUT
73
IN
17 23 45
IN
45 46 73
IN
46
IN
PCH_DMI2RBIAS
PCH_SUSACK_L
17
PM_SYSRST_L
PM_PCH_SYS_PWROK
PM_PCH_PWROK
PM_PCH_APWROK
PM_MEM_PWRGD
PM_RSMRST_L
PCH_SUSWARN_L
17
PM_PWRBTN_L
SMC_ADAPTER_EN
PM_BATLOW_L
PLACE_NEAR=U1800.BH21:2.54mm
1
R1920
750
1%
1/20W
MF
201
2
C
PCH_RI_L
=PP3V3_SUS_PCH_GPIO
7
16 17 18 19
PCH_SUSWARN_L
17
B
7
16 17 18 19
7
R1983
1/20W
10K
OMIT_TABLE
BC24
BE20
BG18
BG20
BE24
BC20
BJ18
BJ20
AW24
AW20
BB18
AV18
AY24
AY20
AY18
AU18
BJ24
BG25
BH21
C12
DMI0RXN
DMI1RXN
DMI2RXN
DMI3RXN
DMI0RXP
DMI1RXP
DMI2RXP
DMI3RXP
DMI0TXN
DMI1TXN
DMI2TXN
DMI3TXN
DMI0TXP
DMI1TXP
DMI2TXP
DMI3TXP
DMI_ZCOMP
DMI_IRCOMP
DMI2RBIAS
SUSACK*
PANTHERPOINT
(IPU)
U1800
MOBILE
FCBGA
(3 OF 10)
DMI
FDI
FDI_FSYNC0
FDI_FSYNC1
FDI_LSYNC0
FDI_LSYNC1
SYS_RESET*
P12
SYS_PWROK
L22
PWROK
L10
APWROK
B13
DRAMPWROK
C21
RSMRST*
K16
SUSWARN*/SUSPWRDNACK/GPIO30
E20
PWRBTN*
(IPU)
H20
ACPRESENT/GPIO31
(IPD-DeepS4/S5)
E10
BATLOW*/GPIO72
A10
RI*
1
5%
MF
201
R1986
2
0
2 1
1/20W
201
5%
MF
PCH_SUSACK_L
CLKRUN*/GPIO32
SUS_STAT*/GPIO61
SUSCLK/GPIO62
SLP_S5*/GPIO63
MANAGEMENT
SYSTEM POWER
(IPU)
SLP_LAN*/GPIO29
17
FDI_RXN0
FDI_RXN1
FDI_RXN2
FDI_RXN3
FDI_RXN4
FDI_RXN5
FDI_RXN6
FDI_RXN7
FDI_RXP0
FDI_RXP1
FDI_RXP2
FDI_RXP3
FDI_RXP4
FDI_RXP5
FDI_RXP6
FDI_RXP7
FDI_INT
DSWVRMEN
DPWROK
WAKE*
SLP_S4*
SLP_S3*
SLP_A*
SLP_SUS*
PMSYNCH
BJ14
AY14
BE14
BH13
BC12
BJ12
BG10
BG9
BG14
BB14
BF14
BG13
BE12
BG12
BJ10
BH9
AW16
AV12
BC10
AV14
BB10
A18
E22
B9K3
N3
G8
N14
D10
H4
F4
G10
G16
AP14
K14
FDI_DATA_N<0>
FDI_DATA_N<1>
FDI_DATA_N<2>
FDI_DATA_N<3>
FDI_DATA_N<4>
FDI_DATA_N<5>
FDI_DATA_N<6>
FDI_DATA_N<7>
FDI_DATA_P<0>
FDI_DATA_P<1>
FDI_DATA_P<2>
FDI_DATA_P<3>
FDI_DATA_P<4>
FDI_DATA_P<5>
FDI_DATA_P<6>
FDI_DATA_P<7>
FDI_INT
FDI_FSYNC<0>
FDI_FSYNC<1>
FDI_LSYNC<0>
FDI_LSYNC<1>
PCH_DSWVRMEN
PM_DSW_PWRGD
PCIE_WAKE_L
PM_CLKRUN_L
LPC_PWRDWN_L
PM_CLK32K_SUSCLK_R
PM_SLP_S5_L
PM_SLP_S4_L
PM_SLP_S3_L
TP_PM_SLP_A_L
PM_SLP_SUS_L
PM_SYNC
GPIO29
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
IN
BI
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
9
78
9
78
9
78
9
78
9
78
9
78
9
78
9
78
9
78
9
78
9
78
9
78
9
78
9
78
9
78
9
78
9
78
9
78
9
78
9
78
9
78
6
17 24 32
6
17 45 47
6
45 47
46
17 45 73
6
17 26 32 45 73
6 8
17 26 45 73
17 73
10 78
17
PLACE_NEAR=U1800.AF37:2.54mm
=PPVRTC_G3_PCH
1
R1915
390K
5%
1/20W
MF
201
2
45
IN
1
R1909
100K
5%
1/20W
MF
201
2
7
R1950
16 20
2.37K
1/20W
AF37
AF36
AE48
AE47
AK39
AK40
AN48
AM47
AK47
AJ48
AN47
AM49
AK49
AJ47
AF40
AF39
AH45
AH47
AF49
AF45
AH43
AH49
AF47
AF43
J47
M45
P45
T40
K47
T45
P39
N48
P49
T49
T39
M40
M47
M49
T43
T42
L_BKLTEN
L_VDD_EN
L_BKLTCTL
L_DDC_CLK
L_DDC_DATA
(IPD-PLTRST#)
L_CTRL_CLK
L_CTRL_DATA
LVD_IBG
LVD_VBG
LVD_VREFH
LVD_VREFL
LVDSA_CLK*
LVDSA_CLK
LVDSA_DATA0*
LVDSA_DATA1*
LVDSA_DATA2*
LVDSA_DATA3*
LVDSA_DATA0
LVDSA_DATA1
LVDSA_DATA2
LVDSA_DATA3
LVDSB_CLK*
LVDSB_CLK
LVDSB_DATA0*
LVDSB_DATA1*
LVDSB_DATA2*
LVDSB_DATA3*
LVDSB_DATA0
LVDSB_DATA1
LVDSB_DATA2
LVDSB_DATA3
CRT_BLUE
CRT_GREEN
CRT_RED
CRT_DDC_CLK
CRT_DDC_DATA
CRT_HSYNC
CRT_VSYNC
DAC_IREF
CRT_IRTN
LVDS_IG_BKL_ON
8
17
OUT
LVDS_IG_PANEL_PWR
8
17
OUT
LVDS_IG_BKL_PWM
8
OUT
LVDS_IG_DDC_CLK
8
OUT
LVDS_IG_DDC_DATA
8
OUT
TP_LVDS_IG_CTRL_CLK
6
TP_LVDS_IG_CTRL_DATA
6
PCH_LVDS_IBG
TP_PCH_LVDS_VBG
1
1%
MF
201
2
6
LVDS_IG_A_CLK_N
74 80
OUT
LVDS_IG_A_CLK_P
74 80
OUT
LVDS_IG_A_DATA_N<0>
6
74 80
OUT
LVDS_IG_A_DATA_N<1>
6
74 80
OUT
LVDS_IG_A_DATA_N<2>
6
74 80
OUT
LVDS_IG_A_DATA_N<3>
8
80
OUT
LVDS_IG_A_DATA_P<0>
6
74 80
OUT
LVDS_IG_A_DATA_P<1>
6
74 80
OUT
LVDS_IG_A_DATA_P<2>
6
74 80
OUT
LVDS_IG_A_DATA_P<3>
8
80
OUT
LVDS_IG_B_CLK_N
8
80
OUT
LVDS_IG_B_CLK_P
8
80
OUT
LVDS_IG_B_DATA_N<0>
8
80
OUT
LVDS_IG_B_DATA_N<1>
8
80
OUT
LVDS_IG_B_DATA_N<2>
8
80
OUT
LVDS_IG_B_DATA_N<3>
8
80
OUT
LVDS_IG_B_DATA_P<0>
8
80
OUT
LVDS_IG_B_DATA_P<1>
8
80
OUT
LVDS_IG_B_DATA_P<2>
8
80
OUT
LVDS_IG_B_DATA_P<3>
8
80
OUT
TP_CRT_IG_BLUE
6
TP_CRT_IG_GREEN
6
TP_CRT_IG_RED
6
TP_CRT_IG_DDC_CLK
6
TP_CRT_IG_DDC_DATA
6
TP_CRT_IG_HSYNC
6
TP_CRT_IG_VSYNC
6
PCH_DAC_IREF
PLACE_NEAR=U1800.T43:2.54mm
1
R1951
1K
5%
1/20W
MF
201
2
OMIT_TABLE
MOBILE
FCBGA
SDVO_TVCLKINN
SDVO_TVCLKINP
SDVO_STALLN
SDVO_STALLP
SDVO_INTN
SDVO_INTP
SDVO_CTRLCLK
SDVO_CTRLDATA
(IPD-PLTRST#)
DDPB_AUXN
DDPB_AUXP
DDPB_HPD
U1800
PANTHERPOINT
(4 OF 10)
LVDS
DDPC_CTRLCLK
DDPC_CTRLDATA
(IPD-PLTRST#)
DDPC_AUXN
DDPC_AUXP
DDPC_HPD
DIGITAL DISPLAY INTERFACE
DDPD_CTRLCLK
DDPD_CTRLDATA
(IPD-PLTRST#)
DDPD_AUXN
DDPD_AUXP
DDPD_HPD
CRT
(IPD)
(IPD)
(IPD)
(IPD)
(IPD)
(IPD)
DDPB_0N
DDPB_0P
DDPB_1N
DDPB_1P
DDPB_2N
DDPB_2P
DDPB_3N
DDPB_3P
DDPC_0N
DDPC_0P
DDPC_1N
DDPC_1P
DDPC_2N
DDPC_2P
DDPC_3N
DDPC_3P
DDPD_0N
DDPD_0P
DDPD_1N
DDPD_1P
DDPD_2N
DDPD_2P
DDPD_3N
DDPD_3P
AP43
AP45
AM42
AM40
AP39
AP40
P38
M39
AT49
AT47
AT40
AV42
AV40
AV45
AV46
AU48
AU47
AV47
AV49
P46
P42
AP47
AP49
AT38
AY47
AY49
AY43
AY45
BA47
BA48
BB47
BB49
M43
M36
AT45
AT43
BH41
BB43
BB45
BF44
BE44
BF42
BE42
BJ42
BG42
TP_SDVO_TVCLKINN
TP_SDVO_TVCLKINP
TP_SDVO_STALLN
TP_SDVO_STALLP
TP_SDVO_INTN
TP_SDVO_INTP
DPA_IG_DDC_CLK
DPA_IG_DDC_DATA
DPA_IG_AUX_CH_N
DPA_IG_AUX_CH_P
DPA_IG_HPD
TP_DP_IG_B_MLN<0>
TP_DP_IG_B_MLP<0>
TP_DP_IG_B_MLN<1>
TP_DP_IG_B_MLP<1>
TP_DP_IG_B_MLN<2>
TP_DP_IG_B_MLP<2>
TP_DP_IG_B_MLN<3>
TP_DP_IG_B_MLP<3>
DPB_IG_DDC_CLK
DPB_IG_DDC_DATA
DPB_IG_AUX_CH_N
DPB_IG_AUX_CH_P
DPB_IG_HPD
TP_DP_IG_C_MLN<0>
TP_DP_IG_C_MLP<0>
TP_DP_IG_C_MLN<1>
TP_DP_IG_C_MLP<1>
TP_DP_IG_C_MLN<2>
TP_DP_IG_C_MLP<2>
TP_DP_IG_C_MLN<3>
TP_DP_IG_C_MLP<3>
TP_DP_IG_D_CTRL_CLK
TP_DP_IG_D_CTRL_DATA
TP_DP_IG_D_AUXN
TP_DP_IG_D_AUXP
TP_DP_IG_D_HPD
TP_DP_IG_D_MLN<0>
TP_DP_IG_D_MLP<0>
TP_DP_IG_D_MLN<1>
TP_DP_IG_D_MLP<1>
TP_DP_IG_D_MLN<2>
TP_DP_IG_D_MLP<2>
TP_DP_IG_D_MLN<3>
TP_DP_IG_D_MLP<3>
6
6
6
6
6
6
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
D
C
B
=PP3V3_SUS_PCH_GPIO
=PP3V3_S0_PCH_GPIO
=PP3V3_S5_PCH
R1985
R1991
A
R1982
R1925
R1924
R1921
R1922
R1923
R1981
R1984
8.2K
10K
100K
100K
100K
100K
100K
100K
1K
1K
7
16 17 18 19
7
16 18 19 30
7
21
1/20W
5%
21
1/20W
5%
21
1/20W
5%
21
1/20W
5%
12
1/20W
5%
12
1/20W
5% MF
12
1/20W
5%
12
1/20W
5%
12
1/20W
5%
12
1/20W
5%
MF
MF
MF
MF
MF
MF
MF
MF
MF
PM_PWRBTN_L
201
PM_CLKRUN_L
201
GPIO29
201
PCIE_WAKE_L
201
MAKE_BASE=TRUE
PM_SLP_S3_L
201
PM_SLP_S4_L
201
PM_SLP_S5_L
201
PM_SLP_SUS_L
201
LVDS_IG_BKL_ON
201
LVDS_IG_PANEL_PWR
201
17 23 45
6
17 45 47
17
6
17 24 32
=TBT_WAKE_L
6 8
17 26 45 73
6
17 26 32 45 73
17 45 73
17 73
8
17
8
17
75
IN
6 3
SYNC_MASTER=J31_MLB
PAGE TITLE
PCH DMI/FDI/PM/Graphics
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
SYNC_DATE=06/13/2011
DRAWING NUMBER
051-9058
REVISION
6.0.0
BRANCH
PAGE
19 OF 109
SHEET
17 OF 86
124578
SIZE
A
D
8 7 6 5 4 3
12
BG26
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
D
TP_PCH_TP23
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
USB3_EXTA_RX_N
42 80
IN
USB3_EXTB_RX_N
43 80
IN
USB3_EXTC_RX_N
8
IN
USB3_EXTD_RX_N
8
C
=PP3V3_S0_PCH_GPIO
7
16 17 18 19 30
R2010
R2011
R2012
R2013
B
R2054
=PP3V3_SUS_PCH_GPIO
=PP3V3_S3_PCH_GPIO
=PP3V3_S0_PCH_GPIO
R2016
R2017
R2018
R2030
R2014
R2031
A
R2033
R2069
R2060
R2061
R2062
R2068
R2067
10K
10K
10K
10K
10K
10K
10K
10K
10K
10K
10K
10K
10K
NO STUFF
NO STUFF
7
16 17 19
7
24
7
16 17 18 19 30
21
1/20W
5%
21
1/20W
5% MF
21
1/20W
5%
21
1/20W
5%
21
1/20W
5%
21
1/20W
5%
Redundant to pull-up on audio page
21
1/20W
5%
21
5%
21
5%
21
21
5%
21
5%
12
5%
XDP_DB3_PCH_GPIO14_SDCONN_STATE_CHANGE
1/20W
1/20W
1/20W
1/20W
1/20W
1/20W
JTAG_GMUX_TMS
201
MF
BLC_I2C_MUX_SEL
201
USE_HDD_OOB_L
201
MF
BLC_GPIO
201
MF
AUD_IP_PERIPHERAL_DET
201
MF
TBT_PWR_REQ_L
201
MF
AUD_I2C_INT_L
201
MF
MF
201
XDP_DA0_PCH_GPIO59_USB_EXTA_OC_L
MF
201
XDP_DA1_PCH_GPIO40_USB_EXTB_OC_L
MF5%
201
XDP_DA2_PCH_GPIO41_USB_EXTC_OC_L
201
MF
XDP_DA3_PCH_GPIO42_USB_EXTD_OC_L
MF
201
AP_PWR_EN
201
MF
10K
10K
10K
10K
10K
NO STUFF
21
21
21
21
12
18
18
18
18
18 62
18 75
18 62
23 32 73
1/20W
5%
1/20W
5%
1/20W
5%
1/20W
5%
1/20W
5%
18 23
18 23
18 23
18 23
18 23
IN
42 80
IN
43 80
IN
8
IN
8
IN
42 80
OUT
43 80
OUT
8
OUT
8
OUT
42 80
OUT
43 80
OUT
8
OUT
8
OUT
201
MF
201
MF
201
MF
201
MF
18
OUT
18
OUT
18
OUT
201
MF
18
IN
18 62
IN
18 75
IN
18 62
IN
6
24 26
OUT
24 81
OUT
24
OUT
6
24
OUT
USB3_EXTA_RX_P
USB3_EXTB_RX_P
USB3_EXTC_RX_P
USB3_EXTD_RX_P
USB3_EXTA_TX_N
USB3_EXTB_TX_N
USB3_EXTC_TX_N
USB3_EXTD_TX_N
USB3_EXTA_TX_P
USB3_EXTB_TX_P
USB3_EXTC_TX_P
USB3_EXTD_TX_P
PCI_INTA_L
PCI_INTB_L
PCI_INTC_L
PCI_INTD_L
JTAG_GMUX_TMS
BLC_I2C_MUX_SEL
USE_HDD_OOB_L
TP_PCH_STRP_BBS1
TP_PCH_STRP_ESI_L
PCH_STRP_TOPBLK_SWP_L
BLC_GPIO
AUD_IP_PERIPHERAL_DET
TBT_PWR_REQ_L
AUD_I2C_INT_L
TP_PCI_PME_L
PLT_RESET_L
LPC_CLK33M_SMC_R
LPC_CLK33M_LPCPLUS_R
TP_PCI_CLK33M_OUT2
TP_PCI_CLK33M_OUT3
PCH_CLK33M_PCIOUT
TP1
BJ26
TP2
BH25
TP3
BJ16
TP4
BG16
TP5
AH38
TP6
AH37
TP7
AK43
TP8
AK45
TP9
C18
TP10
N30
TP11
H3
TP12
AH12
TP13
AM4
TP14
AM5
TP15
Y13
TP16
K24
TP17
L24
TP18
AB46
TP19
AB45
TP20
B21
TP21
M20
TP22
AY16
TP23
BG46
TP24
BE28
USB3RN1
BC30
USB3RN2
BE32
USB3RN3
BJ32
USB3RN4
BC28
USB3RP1
BE30
USB3RP2
BF32
USB3RP3
BG32
USB3RP4
AV26
USB3TN1
BB26
USB3TN2
AU28
USB3TN3
AY30
USB3TN4
AU26
USB3TP1
AY26
USB3TP2
AV28
USB3TP3
AW30
USB3TP4
K40
PIRQA*
K38
PIRQB*
H38
PIRQC*
G38
PIRQD*
C46
REQ1*/GPIO50
C44
REQ2*/GPIO52
E40
REQ3*/GPIO54
D47
GNT1*/GPIO51
E42
GNT2*/GPIO53
F46
GNT3*/GPIO55
(IPU-PCIERST#)
G42
PIRQE*/GPIO2
G40
PIRQF*/GPIO3
C42
PIRQG*/GPIO4
D44
PIRQH*/GPIO5
K10
PME*
C6
PLTRST*
H49
CLKOUT_PCI0
H43
CLKOUT_PCI1
J48
CLKOUT_PCI2
K42
CLKOUT_PCI3
H40
CLKOUT_PCI4
(IPU)
(IPD)
U1800
PANTHERPOINT
MOBILE
FCBGA
(5 OF 10)
USB
PCI
USBRBIAS*
OC0*/GPIO59
OC1*/GPIO40
OC2*/GPIO41
OC3*/GPIO42
OC4*/GPIO43
OC5*/GPIO9
OC6*/GPIO10
OC7*/GPIO14
6 3
RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
RSVD6
RSVD7
RSVD8
RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
RSVD15
RSVD16
RSVD17
RSVD18
RSVD19
RSVD20
RSVD21
RSVD22
RSVD23
RSVD24
RSVD25
RSVD26
RSVD27
RSVD28
RSVD29
USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P
USBP10N
USBP10P
USBP11N
USBP11P
USBP12N
USBP12P
USBP13N
USBP13P
(IPD)
USBRBIAS
AY7
NC
AV7
NC
AU3
NC
BG4
NC
AT10
NC
BC8
NC
AU2
NC
AT4
NC
AT3
NC
AT1
NC
AY3
NC
AT5
NC
AV3
NC
AV1
NC
BB1
NC
BA3
NC
BB5
NC
BB3
NC
BB7
NC
BE8
NC
BD4
NC
BF6
NC
AV5
NC
AV10
NC
AT8
NC
AY5
NC
BA2
NC
AT12
NC
BF3
NC
C24
A24
C25
B25
C26
A26
K28
H28
E28
D28
C28
A28
C29
B29
N28
M28
L30
K30
G30
E30
C30
A30
L32
K32
G32
E32
C32
A32
C33
B33
A14
K20
B17
C16
L16
A16
D14
C14
USB_EXTA_N
USB_EXTA_P
USB_EXTB_XHCI_N
USB_EXTB_XHCI_P
USB_EXTC_N
USB_EXTC_P
USB_EXTD_XHCI_N
USB_EXTD_XHCI_P
TP_USB_4N
TP_USB_4P
TP_USB_SDN
TP_USB_SDP
TP_USB_WLANN
TP_USB_WLANP
USB_HUB_UP_N
USB_HUB_UP_P
USB_CAMERA_N
USB_CAMERA_P
USB_EXTB_EHCI_N
USB_EXTB_EHCI_P
USB_EXTD_EHCI_N
USB_EXTD_EHCI_P
TP_USB_BT_HSN
TP_USB_BT_HSP
TP_USB_12N
TP_USB_12P
TP_USB_13N
TP_USB_13P
PCH_USB_RBIAS
80
XDP_DA0_PCH_GPIO59_USB_EXTA_OC_L
XDP_DA1_PCH_GPIO40_USB_EXTB_OC_L
XDP_DA2_PCH_GPIO41_USB_EXTC_OC_L
XDP_DA3_PCH_GPIO42_USB_EXTD_OC_L
XDP_DB0_PCH_GPIO43_USB_EXTB_OC_EHCI_L
XDP_DB1_PCH_GPIO9_USB_EXTD_OC_EHCI_L
XDP_DB2_PCH_GPIO10_AP_PWR_EN
XDP_DB3_PCH_GPIO14_SDCONN_STATE_CHANGE
D
42 80
BI
42 80
BI
25 80
BI
25 80
BI
8
80
BI
8
80
BI
8
80
BI
8
80
BI
Ext A (XHCI/EHCI)
Ext B (XHCI)
Ext C (XHCI/EHCI)
Ext D (XHCI) (Mobiles: Trackpad?)
C
Unused
RSVD: SD
RSVD: WiFi
25 80
BI
25 80
BI
32 80
BI
32 80
BI
25 80
BI
25 80
BI
8
BI
8
BI
USB Hub (All LS/FS Devices)
Camera
Ext B (EHCI)
Ext D (EHCI)
RSVD: BT (HS)
Unused
B
Unused
PLACE_NEAR=U1800.B33:2.54mm
1
R2070
2
22.6
1%
1/20W
MF
201
SYNC_MASTER=J31_MLB
PAGE TITLE
PCH PCI/USB/TP/RSVD
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
SYNC_DATE=06/13/2011
DRAWING NUMBER
051-9058
REVISION
6.0.0
BRANCH
PAGE
20 OF 109
SHEET
18 OF 86
SIZE
A
D
18 23
IN
18 23
IN
18 23
IN
18 23
IN
23
IN
23
IN
23
OUT
18 23
IN
124578
OMIT_TABLE
8 7 6 5 4 3
BOM GROUP
RAMCFG_SLOT
BOM OPTIONS
RAMCFG3:H,RAMCFG2:H,RAMCFG1:H,RAMCFG0:H
12
TABLE_BOMGROUP_HEAD
TABLE_BOMGROUP_ITEM
Systems with no chip-down memory should pull all 4 RAMCFG GPIOs high.
Systems with chip-down memory should add pull-downs on another page and set straps per software.
=PP3V3_S0_PCH_GPIO
7
16 17 18 19 30
RAMCFG3:H
R2172
D
XDP_FC1_PCH_GPIO0
19 23
FW_PME_L
8
19 39
IN
DPMUX_UC_IRQ
19
IN
SMC_RUNTIME_SCI_L
19 45
IN
TP_PCH_GPIO8
WOL_EN
19 73
OUT
XDP_FC0_PCH_GPIO15_MEM_VDD_SEL_1V5_L
23
IN
XDP_DD2_PCH_GPIO16_AUD_IPHS_SWITCH_EN_PCH
23
OUT
LPCPLUS_GPIO
6
19 47
BI
ODD_PWR_EN_L
19 41
OUT
PCH_GPIO24
19
(PU necessary?)
SMC_SCI_L
19 46
XDP_DC0_PCH_GPIO28_ISOLATE_CPU_MEM_L
23
35
OUT
TBT_SW_RESET_L
R2180
0
C
OUT
21
5%
MF
TBT_SW_RESET_R_L
19
1/20W
201
XDP_DC1_PCH_GPIO35_MXM_GOOD
23
OUT
XDP_DD0_PCH_GPIO36_DP_GPU_TBT_SEL
19 23
OUT
XDP_DD1_PCH_GPIO37_JTAG_ISP_TCK
23
OUT
JTAG_ISP_TDO
8
19
IN
JTAG_ISP_TDI
8
OUT
FW_PWR_EN_PCH
19 24
OUT
XDP_DD3_PCH_GPIO49_ENET_LOW_PWR_PCH
23
OUT
SPIROM_USE_MLB
6
19 47 56
BI
T7
BMBUSY*/GPIO0
A42
TACH1/GPIO1
H36
TACH2/GPIO6
E38
TACH3/GPIO7
C10
GPIO8
(IPU-RSMRST#)
C4
LAN_PHY_PWR_CTRL/GPIO12
G2
GPIO15
(IPD)
SATA4GP/GPIO16
TACH0/GPIO17
SCLOCK/GPIO22
GPIO24
GPIO27
(IPU-DeepS4/S5)
GPIO28
(IPU-RSMRST#)
STP_PCI*/GPIO34
GPIO35
SATA2GP/GPIO36
(IPD-PLTRST#)
SATA3GP/GPIO37
(IPD-PLTRST#)
SLOAD/GPIO38
SDATAOUT0/GPIO39
SDATAOUT1/GPIO48
SATA5GP/GPIO49/TEMP_ALERT*
GPIO57
VSS_NCTF_0
VSS_NCTF_1
VSS_NCTF_2
VSS_NCTF_3
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_7
VSS_NCTF_8
VSS_NCTF_9
VSS_NCTF_10
VSS_NCTF_11
VSS_NCTF_12
VSS_NCTF_13
BD49
BE49
BF49
U2
D40
T5
E8
E16
P8
K1
K4
V8
M5
N2
M3
V13
V3
D6
A4
A44
A45
A46
A5
A6
B3
B47
BD1
BE1
BF1
OMIT_TABLE
U1800
PANTHERPOINT
MOBILE
FCBGA
(6 OF 10)
NCTF
TACH4/GPIO68
TACH5/GPIO69
TACH6/GPIO70
TACH7/GPIO71
(IPD-PLTRST#?)
CPU/MISC
GPIO
A20GATE
PECI
(IPD)
RCIN*
PROCPWRGD
THRMTRIP*
INIT3_3V*
(IPU)
DF_TVS
TS_VSS1
TS_VSS2
TS_VSS3
TS_VSS4
NC_1
VSS_NCTF_14
VSS_NCTF_15
VSS_NCTF_16
VSS_NCTF_17
VSS_NCTF_18
VSS_NCTF_19
VSS_NCTF_20
VSS_NCTF_21
VSS_NCTF_22
VSS_NCTF_23
VSS_NCTF_24
VSS_NCTF_25
VSS_NCTF_26
VSS_NCTF_27
VSS_NCTF_28
VSS_NCTF_29
VSS_NCTF_30
VSS_NCTF_31
C40
B41
C41
A40
P4
AU16
P5
AY11
AY10
T14
AY1
AH8
AK11
AH10
AK10
P37
BG2
BG48
BH3
BH47
BJ4
BJ44
BJ45
BJ46
BJ5
BJ6
C2
C48
D1
D49
E1
E49
F1
F49
NC
MLB_RAMCFG3
MLB_RAMCFG2
MLB_RAMCFG1
MLB_RAMCFG0
PCH_A20GATE
PCH_PECI
PCH_RCIN_L
PCH_PROCPWRGD
PM_THRMTRIP_L_R
46
PCH_INIT3V3_L
PCH_DF_TVS
NO STUFF
R2130
1/20W
1/20W
19
19
1
1K
This has internal pull up and should not pulled low.
5%
THIS SIGNAL IS INTENDED FOR FIRMWARE HUB AND WE ARE NOT USING IT.
MF
201
2
10K
5%
MF
201
R2170
R2140
R2156
1
2
RAMCFG2:H
1
R2173
10K
5%
1/20W
MF
201
2
43
0
390
NO STUFF
21
CPU_PECI
5%
MF
21
CPU_PWRGD
5%
MF
21
PM_THRMTRIP_L
5%
MF
RAMCFG1:H
R2174
1/20W
201
1/20W
201
1/20W
201
1/20W
10K
RAMCFG0:H
1
1
R2175
10K
5%
5%
1/20W
MF
MF
201
201
2
2
10 46 78
BI
10 23 78
OUT
10 46 78
ININ
R2178
1K
2 1
1/20W
201
=PP1V8_S0_PCH_VCC_DFTERM
1
R2179
2.2K
5%
1/20W
MF
201
2
CPU_PROC_SEL_L
5%
DF_TVS:DMI & FDI Term Voltage
MF
Set to Vss when Low
Set to Vcc when High
10
7
20 22
D
C
SIZE
B
A
D
B
=PP3V3_S5_PCH_GPIO
=PP3V3_SUS_PCH_GPIO
=PP3V3_S0_PCH_GPIO
=PP3V3_T29_PCH_GPIO
R2186
R2199
R2160
R2185
R2196
R2190
R2197
R2184
R2150
R2155
A
R2194
R2192
R2193
R2191
R2111
R2195
R2112
R2198
R2113
R2116
10K
10K
10K
10K
10K
100K
10K
10K
10K
10K
10K
10K
100K
10K
20K
100K
10K
10K
10K
10K
NO STUFF
7
7
16 17 18
7
16 17 18 19 30
7
16
21
1/20W
5%
21
1/20W
5%
21
1/20W
5%
21
1/20W
5%
21
1/20W
5%
21
1/20W
5%
Must stuff R2197 when R2180 NO STUFFed.
21
1/20W
5%
21
1/20W
5%
21
1/20W
5%
21
1/20W
5%
21
1/20W
5%
21
1/20W
5%
21
1/20W
5%
21
1/20W
5%
12
1/20W
5%
12
1/20W
5%
12
1/20W
5%
12
1/20W
5%
12
1/20W
5%
12
1/20W
5%
JTAG_ISP_TDO
201
MF
JTAG_TBT_TDI
201
MF
XDP_FC1_PCH_GPIO0
201
MF
FW_PME_L
201
MF
SMC_RUNTIME_SCI_L
201
MF
LPCPLUS_GPIO
201
MF
TBT_SW_RESET_R_L
201
MF
FW_PWR_EN_PCH
201
MF
PCH_A20GATE
201
MF
PCH_RCIN_L
201
MF
WOL_EN
201
MF
PCH_GPIO24
201
MF
SPIROM_USE_MLB
201
MF
SMC_SCI_L
201
MF
DPMUX_UC_IRQ
201
MF
AUD_IPHS_SWITCH_EN_PCH
201
MF
ODD_PWR_EN_L
201
MF
XDP_DD0_PCH_GPIO36_DP_GPU_TBT_SEL
201
MF
JTAG_ISP_TCK
201
MF
ENET_LOW_PWR_PCH
201
MF
8
19
8
33
19 23
8
19 39
19 45
6
19 47
19
19 24
19
19
19 73
19
6
19 47 56
19 46
19
23 24
19 41
19 23
8
23
23 24
6 3
SYNC_MASTER=J31_MLB
PAGE TITLE
PCH GPIO/MISC/NCTF
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
SYNC_DATE=06/13/2011
DRAWING NUMBER
051-9058
REVISION
6.0.0
BRANCH
PAGE
21 OF 109
SHEET
19 OF 86
124578
8 7 6 5 4 3
12
D
OMIT_TABLE
V5REF
N26
=PP1V05_S0_PCH_VCCIO_USB
P26
P28
T27
T29
T23
=PP3V3_SUS_PCH_VCCSUS_USB
T24
V23
V24
P24
T26
=PP1V05_S0_PCH_VCCIO_PLLUSB
M26
=PP5V_SUS_PCH_V5REFSUS
AN23
AN24
P34
N20
N22
P20
P22
AA16
W16
T34
AJ2
AF13
AH13
AH14
AF14
AK1
AF11
AC16
AC17
AD17
T21
V21
T19
P32
NC-ed per DG
NC
=PP3V3_SUS_PCH_VCCSUS
=PP5V_S0_PCH_V5REF
=PP3V3_SUS_PCH_VCCSUS_GPIO
=PP3V3_S0_PCH_VCC3_3_GPIO
=PP3V3_S0_PCH_VCC3_3_SATA
=PP1V05_S0_PCH_VCCIO_SATA
VCCAPLLSATA pin left as NC per DG
NC
=PP1V8R1V5_S0_PCH_VCCVRM
=PP1V05_S0_PCH_VCCIO_SATA
=PP1V05_S0_PCH_VCCASW
=PP3V3R1V5_S0_PCH_VCCSUSHDA
10 mA Max, 1mA Idle
7
22
7
22
7
22
7
22
7
22
7
22
7
22
7
16 20 22
7
20
7
16 20 22
7
20 22
7
22 24
VCCAFDIPLL pin left as NC per DG
AD49
VCCACLK pin left as NC per DG
=PP3V3_S5_PCH_VCCDSW
7
22
NC
TP_PPVOUT_PCH_DCPSUSBYP
PP3V3_S0_PCH_VCC3_3_CLK_F
22
VCCAPLLDMI2 pin left as NC per DG
=PP1V05_S0_PCH_VCCIO_CLK
7
20 22
AL24 left as NC per DG
=PP1V05_S0_PCH_VCCASW
7
20 22
NC
NC
C
PLACE_NEAR=U1800.N16:2.54mm
B
PCH output, for decoupling only
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V
1
C2210
0.1UF
20%
10V
2
CERM
402
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V
1
C2222
0.1UF
PLACE_NEAR=U1800.V16:2.54mm
20%
10V
2
CERM
402
PPVOUT_G3_PCH_DCPRTC
=PP1V8R1V5_S0_PCH_VCCVRM
7
20
PP1V05_S0_PCH_VCCADPLLA_F
22
PP1V05_S0_PCH_VCCADPLLB_F
22
=PP1V05_S0_PCH_VCCIO_CLK
7
20 22
=PP1V05_S0_PCH_VCCDIFFCLK
7
16 22
55mA Max, 5mA Idle
=PP1V05_S0_PCH_VCCSSC
7
22
PPVOUT_S0_PCH_DCPSST
=PP1V05_S0_PCH_V_PROC_IO
7
22
=PPVRTC_G3_PCH
7
16 17
C2231
PLACE_NEAR=U1800.A22:2.54mm
NC-ed per DG
1
1UF
10%
6.3V
2
CERM
402
NC
NC
1
C2232
0.1UF
20%
10V
2
CERM
402
PLACE_NEAR=U1800.A22:2.54mm
VCCACLK
T16
VCCDSW3_3
V12
DCPSUSBYP
T38
VCC3_3_5_CLK
BH23
VCCAPLLDMI2
AL29
VCCIO_14_PLLCLK
AL24
DCPSUS_3_CLK
AA19
VCCASW_1_CLK
AA21
VCCASW_2_CLK
AA24
VCCASW_3_CLK
AA26
VCCASW_4_CLK
AA27
VCCASW_5_CLK
AA29
VCCASW_6_CLK
AA31
VCCASW_7_CLK
AC26
VCCASW_8_CLK
AC27
VCCASW_9_CLK
AC29
VCCASW_10_CLK
AC31
VCCASW_11_CLK
AD29
VCCASW_12_CLK
AD31
VCCASW_13_CLK
W21
VCCASW_14_CLK
W23
VCCASW_15_CLK
W24
VCCASW_16_CLK
W26
VCCASW_17_CLK
W29
VCCASW_18_CLK
W31
VCCASW_19_CLK
W33
VCCASW_20_CLK
N16
DCPRTC
Y49
VCCVRM_4_CLK
BD47
VCCADPLLA
BF47
VCCADPLLB
AF17
VCCIO_7_CLK
AF33
VCCDIFFCLKN
AF34
VCCDIFFCLKN
AG34
VCCDIFFCLKN
AG33
VCCSSC
V16
DCPSST
T17
DCPSUS_1_CLK
V19
DCPSUS_2_CLK
BJ8
V_PROC_IO
A22
VCCRTC
1
C2233
0.1UF
20%
10V
2
CERM
402
PLACE_NEAR=U1800.A22:2.54mm
U1800
PANTHERPOINT
MOBILE
FCBGA
(8 OF 10)
CLK/MISC
CPURTC
VCCIO_29_USB
VCCIO_30_USB
VCCIO_31_USB
VCCIO_32_USB
VCCIO_33_USB
VCCSUS3_3_7_USB
VCCSUS3_3_8_USB
VCCSUS3_3_9_USB
VCCSUS3_3_10_USB
VCCSUS3_3_6_USB
VCCIO_34_PLLUSB
V5REF_SUS
USB
DCPSUS_4_USB
VCCSUS3_3_1_USB
VCCSUS3_3_2_GPIO
VCCSUS3_3_3_GPIO
VCCSUS3_3_4_GPIO
VCCSUS3_3_5_GPIO
VCC3_3_1_GPIO
VCC3_3_8_GPIO
LPC
VCC3_3_4_GPIO
PCI/GPIO/
VCC3_3_2_SATA
VCCIO_5_PLLSATA
VCCIO_12_SATA3
VCCIO_13_SATA3
VCCIO_6_PLLSATA3
VCCAPLLSATA
SATAMISC
VCCVRM_1_SATA
VCCIO_2_SATA
VCCIO_3_SATA
VCCIO_4_SATA
VCCASW_22_MISC
VCCASW_23_MISC
VCCASW_21_MISC
VCCSUSHDA
HDA
=PP1V05_S0_PCH_VCC_CORE
7
22
1.44 A Max, 474mA Idle
=PP1V05_S0_PCH_VCCIO_PLLPCIE
7
TP_1V05_S0_PCH_VCCAPLLEXP
=PP1V05_S0_PCH_VCCIO
7
22
=PP3V3_S0_PCH_VCC3_3_PCI
7
22
=PP1V8R1V5_S0_PCH_VCCVRM
7
20
=PP1V05_S0_PCH_VCCIO_PLLFDI
7
=PP1V05_S0_PCH_VCCDMI_FDI
7
AA23
VCCCORE
AC23
VCCCORE
AD21
VCCCORE
AD23
VCCCORE
AF21
VCCCORE
AF23
VCCCORE
AG21
VCCCORE
AG23
VCCCORE
AG24
VCCCORE
AG26
VCCCORE
AG27
VCCCORE
AG29
VCCCORE
AJ23
VCCCORE
AJ26
VCCCORE
AJ27
VCCCORE
AJ29
VCCCORE
AJ31
VCCCORE
AN19
VCCIO_28_PLLPCIE
BJ22
VCCAPLLEXP
AN16
VCCIO_15_FDI
AN17
VCCIO_16_FDI
AN21
VCCIO_17_PCIE
AN26
VCCIO_18_PCIE
AN27
VCCIO_19_PCIE
AP21
VCCIO_20_PCIE
AP23
VCCIO_21_PCIE
AP24
VCCIO_22_PCIE
AP26
VCCIO_23_PCIE
AT24
VCCIO_24_PCIE
AN33
VCCIO_25_DP
AN34
VCCIO_26_DP
BH29
VCC3_3_3_PCIE
AP16
VCCVRM_2_FDI
BG6
NC
VCCAFDIPLL
AP17
VCCIO_27_PLLFDI
AU20
VCCDMI_2_FDI
OMIT_TABLE
U1800
PANTHERPOINT
MOBILE
FCBGA
(7 OF 10)
VCC CORE
LVDS
HVCMOS
VCCIO
DMI CRT
FDI
DFT/SPI
VCCADAC
VSSADAC
VCCALVDS
VSSALVDS
VCCTX_LVDS
VCCTX_LVDS
VCCTX_LVDS
VCCTX_LVDS
VCC3_3_6_HVCMOS
VCC3_3_7_HVCMOS
VCCVRM_3_DMI
VCCDMI_1_DMI
VCCCLKDMI
VCCDFTERM
VCCDFTERM
VCCDFTERM
VCCDFTERM
VCCSPI
U48
PP3V3_S0_PCH_VCCA_DAC_F
U47
AK36
=PP3V3_S0_PCH_VCCA_LVDS
AK37
PP1V8_S0_PCH_VCCTX_LVDS_F
AM37
AM38
AP36
AP37
=PP3V3_S0_PCH_VCC3_3_HVCMOS
V33
V34
AT16
=PP1V8R1V5_S0_PCH_VCCVRM
AT20
=PP1V05_S0_PCH_VCC_DMI
AB36
PP1V05_S0_PCH_VCCCLKDMI_F
=PP1V8_S0_PCH_VCC_DFTERM
AG16
AG17
AJ16
AJ17
V1
=PP3V3_SUS_PCH_VCC_SPI
22
7
22
7
22
7
20
7
22
22
7
19 22
7
22
D
C
B
A
SYNC_MASTER=J31_MLB
PAGE TITLE
PCH POWER
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
6 3
SYNC_DATE=06/13/2011
DRAWING NUMBER
051-9058
REVISION
6.0.0
BRANCH
PAGE
22 OF 109
SHEET
20 OF 86
124578
SIZE
A
D
8 7 6 5 4 3
OMIT_TABLE
H5
AA17
AA2
AA3
AA33
AA34
AB11
AB14
AB39
AB4
D
C
B
AB43
AC19
AC21
AC24
AC33
AC34
AC48
AD10
AD11
AD12
AD13
AD19
AD24
AD26
AD27
AD33
AD34
AD36
AD37
AD38
AD39
AD40
AD42
AD43
AD45
AD46
AF10
AF12
AD14
AD16
AF16
AF19
AF24
AF26
AF27
AF29
AF31
AF38
AF42
AF46
AG19
AG31
AG48
AH11
AH36
AH39
AH40
AH42
AH46
AJ19
AJ21
AJ24
AJ33
AJ34
AK12
AB5
AB7
AC2
AD4
AD8
AE2
AE3
AF4
AF5
AF7
AF8
AG2
AH3
AH7
AK3
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
U1800
PANTHERPOINT
MOBILE
FCBGA
(9 OF 10)
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AK38
AK4
AK42
AK46
AK8
AL16
AL17
AL19
AL2
AL21
AL23
AL26
AL27
AL31
AL33
AL34
AL48
AM11
AM14
AM36
AM39
AM43
AM45
AM46
AM7
AN2
AN29
AN3
AN31
AP12
AP19
AP28
AP30
AP32
AP38
AP4
AP42
AP46
AP8
AR2
AR48
AT11
AT13
AT18
AT22
AT26
AT28
AT30
AT32
AT34
AT39
AT42
AT46
AT7
AU24
AU30
AV11
AV16
AV20
AV24
AV30
AV38
AV4
AV43
AV8
AW14
AW18
AW2
AW22
AW26
AW28
AW32
AW34
AW36
AW40
AW48
AY12
AY22
AY28
A
AY42
AY46
BB12
BB16
BB20
BB22
BB24
BB28
BB30
BB38
BB46
BC14
BC18
BC22
BC26
BC32
BC34
BC36
BC40
BC42
BC48
BD46
BE22
BE26
BE40
BF10
BF12
BF16
BF20
BF22
BF24
BF26
BF28
BF30
BF38
BF40
BG17
BG21
BG33
BG44
BH11
BH15
BH17
BH19
BH27
BH31
BH33
BH35
BH39
BH43
AY4
AY8
B11
B15
B19
B23
B27
B31
B35
B39
B7
F45
BB4
BC2
BD5
BD3
BF8
BG8
H10
BH7
D3
D12
D16
D18
D22
D24
D26
D30
D32
D34
D38
D42
D8
E18
E26
G18
G20
G26
G28
G36
G48
H12
H18
H22
H24
H26
H30
H32
H34
F3
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
OMIT_TABLE
U1800
PANTHERPOINT
MOBILE
FCBGA
(10 OF 10)
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
H46
K18
K26
K39
K46
K7
L18
L2
L20
L26
L28
L36
L48
M12
P16
M18
M22
M24
M30
M32
M34
M38
M4
M42
M46
M8
N18
P30
N47
P11
P18
T33
P40
P43
P47
P7
R2
R48
T12
T31
T37
T4
W34
T46
T47
T8
V11
V17
V26
V27
V29
V31
V36
V39
V43
V7
W17
W19
W2
W27
W48
Y12
Y38
Y4
Y42
Y46
Y8
BG29
N24
AJ3
AD47
B43
BE10
BG41
G14
H16
T36
BG22
BG24
C22
AP13
M14
AP3
AP1
BE16
BC16
BG28
BJ28
SYNC_MASTER=J31_MLB
PAGE TITLE
PCH GROUNDS
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
6 3
12
SYNC_DATE=06/13/2011
DRAWING NUMBER
051-9058
REVISION
6.0.0
BRANCH
PAGE
23 OF 109
SHEET
21 OF 86
124578
SIZE
D
C
B
A
D
8 7 6 5 4 3
12
L2406
=PP1V05_S0_PCH
7
16
10UH-0.12A-0.36OHM
0603
21
PP1V05_S0_PCH_VCCCLKDMI_R
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM
VOLTAGE=1.05V
PLACE_NEAR=U1800.AB36:2.54mm
R2415
0
5%
1/16W
MF-LF
402
PP1V05_S0_PCH_VCCCLKDMI_F
21
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM
VOLTAGE=1.05V
MAKE_BASE=TRUE
1
C2411
10UF
20%
6.3V
2
CERM-X5R
0402-1
20
PLACE_NEAR=U1800.P24:2.54mm
D
L2407
=PP1V8_S0_PCH_VCCTX_LVDS
7
=PP3V3_S0_PCH_VCCADAC
7
C
=PP3V3_S0_PCH
7
16
=PP5V_S0_PCH
7
24
1 mA
PLACE_NEAR=U1800.P34:2.54mm
0.1UH
21
PP1V8_S0_PCH_VCCTX_LVDS_F
0805
R2450
1/16W
MF-LF
402
C2450
PLACE_NEAR=U1800.U48:2.54mm
PLACE_NEAR=U1800.U48:2.54mm
PLACE_NEAR=U1800.U48:2.54mm
R2405
C2439
20
C2400
22UF
20%
6.3V
CERM
805
PLACE_NEAR=U1800.AM37:2.54mm
PLACE_NEAR=U1800.AM37:2.54mm
PLACE_NEAR=U1800.AM37:2.54mm
0
21
5%
1
10UF
20%
6.3V
2
X5R
603
2
100
NC
5%
1/16W
MF-LF
402
1
1
1UF
10%
10V
2
X5R
402
C2406
0.01UF
X7R-CERM
0402
10%
16V
1
2
C2408
1
2
PP3V3_S0_PCH_VCCA_DAC_F
1
C2451
0.1UF
X7R-CERM
5
NC
C2455
0.01UF
10%
16V
2
X7R-CERM
0402
PCH V5REF Filter & Follower
(PCH Reference for 5V Tolerance on PCI)
1
D2400
BAT54DW-X-G
SOT-363
6
PP5V_S0_PCH_V5REF
MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.25MM
VOLTAGE=5V
MAKE_BASE=TRUE
0402
=PP5V_S0_PCH_V5REF
0.01UF
10%
16V
X7R-CERM
0402
1
10%
16V
2
NEED PWR CONSTRAINT
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM
VOLTAGE=1.8V
1
2
MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V
<1 MA
20
20
=PP3V3_S0_PCH_VCC3_3_CLK
7
PCH VCCSUS3_3 BYPASS
(PCH SUSPEND USB 3.3V PWR)
=PP3V3_SUS_PCH_VCCSUS_USB
7
20
1
C2484
0.1UF
10%
16V
2
X7R-CERM
0402
=PP1V05_S0_PCH_V_PROC_IO
7
20
PLACE_NEAR=U1800.BJ8:2.54mm
PLACE_NEAR=U1800.BJ8:2.54mm
PLACE_NEAR=U1800.BJ8:2.54mm
PCH VCCIO BYPASS
=PP1V05_S0_PCH_VCC_DMI
7
20
PCH VCC3_3 BYPASS
(PCH PCI 3.3V PWR)
PLACE_NEAR=U1800.AT20:2.54mm
R2451
1
21
5%
1/16W
MF-LF
402
1
C2413
0.1UF
10%
16V
2
X7R-CERM
0402
PLACE_NEAR=U1800.V24:2.54mm
1
1
C2416
4.7UF
20%
6.3V
X5R
402
1
C2419
1UF
10%
6.3V
2
CERM
402
C2417
0.1UF
10%
16V
2
2
X7R-CERM
0402
10UH-0.12A-0.36OHM
PP3V3_S0_PCH_VCC3_3_CLK_R
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V
1
C2430
0.1UF
10%
16V
2
X7R-CERM
0402
PLACE_NEAR=U1800.T16:2.54mm
L2451
21
20
0603
C2453
10UF
6.3V
CERM-X5R
0402-1
PLACE_NEAR=U1800.T38:2.54mm
PLACE_NEAR=U1800.T38:2.54mm
20
PP3V3_S0_PCH_VCC3_3_CLK_F
20%
=PP1V8_S0_PCH_VCC_DFTERM
7
19 20
PLACE_NEAR=U1800.AJ16:2.54mm
PCH VCCSUSHDA BYPASS
(PCH HD Audio 3.3V/1.5V PWR)
=PP3V3R1V5_S0_PCH_VCCSUSHDA
7
20 24
PLACE_NEAR=U1800.P32:2.54mm
=PP3V3_SUS_PCH_VCC_SPI
7
20
PLACE_NEAR=U1800.V1:2.54mm
=PP3V3_S5_PCH_VCCDSW
7
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
C2454
VOLTAGE=3.3V
1
2
1UF
10%
10V
X5R
402
1
2
C2499
0.1UF
20%
10V
CERM
402
1
2
1
C2441
0.1UF
20%
10V
2
CERM
402
1
C2442
1UF
10%
6.3V
2
CERM
402
1
2
C2440
0.1UF
20%
10V
CERM
402
=PP1V05_S0_PCH_VCCIO_SATA
7
16 20
PLACE_NEAR=U1800.AH13:2.54mm
PLACE_NEAR=U1800.AC17:2.54mm
7
20
PLACE_NEAR=U1800.AG33:2.54mm
7
16 20
PLACE_NEAR=U1800.AF34:2.54mm
=PP1V05_S0_PCH_VCCIO
7
20
1
C2444
1UF
10%
6.3V
2
CERM
402
1
C2452
1UF
10%
6.3V
2
CERM
402
=PP1V05_S0_PCH_VCCSSC
1
2
=PP1V05_S0_PCH_VCCDIFFCLK
=PP1V05_S0_PCH_VCC_CORE
7
20
1
C2481
1UF
10%
6.3V
2
CERM
402
PLACE_NEAR=U1800.AD21:2.54mm
PLACE_NEAR=U1800.AG24:2.54mm
PLACE_NEAR=U1800.AJ27:2.54mm
PLACE_NEAR=U1800.AG26:2.54mm
1
C2429
1UF
10%
6.3V
2
CERM
402
1
2
1
C2414
1UF
10%
6.3V
2
CERM
402
C2475
1UF
10%
6.3V
CERM
402
1
C2434
1UF
2
C2482
1UF
10%
6.3V
CERM
402
PCH VCCIO BYPASS
(PCH USB 1.05V PWR)
=PP1V05_S0_PCH_VCCIO_USB
7
20
PLACE_NEAR=U1800.P28:2.54mm
=PP3V3_SUS_PCH_VCCSUS_GPIO
7
20
PLACE_NEAR=U1800.P22:2.54mm
=PP1V05_S0_PCH_VCCIO_CLK
7
20
10%
6.3V
CERM
402
PLACE_NEAR=U1800.AF17:2.54mm
PCH VCCCORE BYPASS
(PCH 1.05V CORE PWR)
1
C2460
2
1
C2407
1UF
10%
6.3V
2
CERM
402
C2483
1UF
10%
6.3V
CERM
402
1
C2463
1UF
10%
6.3V
2
CERM
402
10UF
20%
6.3V
X5R
603
C2401
10UF
1
2
6.3V
20%
X5R
603
1
C2446
1UF
10%
6.3V
2
CERM
402
D
1
C2476
1UF
10%
6.3V
2
CERM
402
1
C2469
1UF
10%
6.3V
2
CERM
402
C
1
2
=PP3V3_SUS_PCH
B
PLACE_NEAR=U1800.M26:2.54mm
=PP3V3_S0_PCH_VCC3_3_PCI
7
20
PLACE_NEAR=U1800.BH29:2.54mm
A
=PP3V3_S0_PCH_VCC3_3_HVCMOS
7
20
PLACE_NEAR=U1800.V33:2.54mm
7
=PP5V_SUS_PCH
7
1 mA S0-S5
C2438
1
C2421
0.1UF
10%
16V
2
X7R-CERM
0402
R2404
1/16W
MF-LF
402
0.1UF
20%
10V
CERM
402
1
C2424
0.1UF
10%
16V
2
X7R-CERM
0402
PCH V5REF_SUS Filter & Follower
(PCH Reference for 5V Tolerance on USB)
2
10
5%
1
1
2
4
2
D2400
NC
NC
BAT54DW-X-G
SOT-363
3
PP5V_SUS_PCH_V5REFSUS
MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.25MM
VOLTAGE=5V
MAKE_BASE=TRUE
=PP5V_SUS_PCH_V5REFSUS
20
NEED PWR CONSTRAINT
=PP3V3_S0_PCH_VCC3_3_SATA
7
PLACE_NEAR=U1800.AJ2:2.54mm
=PP3V3_S0_PCH_VCC3_3_GPIO
7
20
PLACE_NEAR=U1800.T34:2.54mm
<1 MA S0-S5
20
1
C2486
0.1UF
10%
25V
2
X5R
402
1
C2423
0.1UF
10%
16V
2
X7R-CERM
0402
1
C2485
0.1UF
10%
25V
2
PLACE_NEAR=U1800.AA16:2.54mm
X5R
402
=PP1V05_S0_PCH_VCCADPLL
7
R2460
0
5%
1/16W
MF-LF
402
R2465
0
5%
1/16W
MF-LF
402
PCH VCCADPLLA Filter
1
C2402
0.1UF
20%
10V
2
CERM
402
1
C2465
0.1UF
20%
10V
2
CERM
402
(PCH DPLLA PWR)
PP1V05_S0_PCH_VCCADPLLA_F
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
1
C2461
1UF
10%
6.3V
2
CERM
402
PCH VCCADPLLB Filter
(PCH DPLLB PWR)
PP1V05_S0_PCH_VCCADPLLB_F
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
1
C2466
1UF
10%
6.3V
2
CERM
402
PLACE_NEAR=U1800.BD47:2.54MM
PLACE_NEAR=U1800.BF47:2.54MM
68 mA
69 mA
20
=PP1V05_S0_PCH_VCCASW
7
20
1
C2426
1UF
10%
6.3V
2
CERM
402
20
PLACE_NEAR=U1800.AC27:2.54mm
PLACE_NEAR=U1800.AC27:2.54mm
PLACE_NEAR=U1800.AC27:2.54mm
PLACE_NEAR=U1800.AC27:2.54mm
PLACE_NEAR=U1800.AC27:2.54mm
21
21
6 3
PLACE_NEAR=U1800.AN27:2.54mm
PLACE_NEAR=U1800.AN27:2.54mm
PLACE_NEAR=U1800.AN27:2.54mm
PLACE_NEAR=U1800.AN27:2.54mm
PLACE_NEAR=U1800.AN27:2.54mm
C2456
1UF
10%
6.3V
CERM
402
1
C2496
1UF
10%
6.3V
2
CERM
402
C2428
22UF
20%
6.3V
CERM
805
1
C2420
2
1
2
PAGE TITLE
PCH DECOUPLING
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
22UF
6.3V
CERM
20%
805
1
2
SYNC_DATE=02/15/2011SYNC_MASTER=K90I_MLB
DRAWING NUMBER
051-9058
REVISION
6.0.0
BRANCH
PAGE
24 OF 109
SHEET
22 OF 86
124578
SIZE
B
A
D
8 7 6 5 4 3
12
=PPVCCIO_S0_XDP
7
23
=PP3V3_S0_XDP
7
XDP_CPU_PREQ_L
10 78
BI
XDP_CPU_PRDY_L
10 78
D
(R2560-R2563)
XDP_CPU:BPM
XDP_CPU:BPM
XDP_CPU:BPM
XDP_CPU:BPM
10
IN
10
IN
10
IN
10
IN
9
78
IN
9
78
IN
9
78
IN
9
78
IN
10 19 78
IN
17 23 45
OUT
9
23 78
OUT
17 24 45
OUT
XDP_BPM_L<4>
XDP_BPM_L<5>
XDP_BPM_L<6>
XDP_BPM_L<7>
CPU_CFG<12>
CPU_CFG<13>
CPU_CFG<14>
CPU_CFG<15>
CPU_PWRGD
PM_PWRBTN_L
CPU_CFG<0>
PLACE_NEAR=U1000.C60:2.54mm
PLACE_NEAR=U4900.P17:2.54mm
PLACE_NEAR=U1000.B57:2.54mm
PM_PCH_SYS_PWROK
R2560
R2561
R2562
R2563
R2564
R2565
R2566
R2567
R2500
R2502
R2501
R2504
0
0
0
0
(R2564-R2567)
XDP_CPU:CFG
XDP_CPU:CFG
XDP_CPU:CFG
XDP_CPU:CFG
0
0
0
0
1K
0
1K
330
21
5% 201MF
21
5% 201MF
21
5% 201MF
21
5% 201MF
21
5% 201MF
21
5% 201MF
21
5%
21
5% MF
XDP
21
5%
XDP
21
5% 201
XDP
21
5%
XDP
21
5% 201MF
1/20W
1/20W
1/20W
1/20W
1/20W
1/20W
1/20W
1/20W
1/20W
1/20W
1/20W
1/20W
201MF
201
201MF
MF
201MF
C
XDP SIGNALS
R2584
R2585
R2520
R2521
R2522
R2523
R2524
R2525
R2526
R2527
R2528
R2529
R2530
R2531
R2532
R2533
R2534
R2535
R2536
R2537
XDP_DA0_USB_EXTA_OC_L
23
OUT
XDP_DA1_USB_EXTB_OC_L
23
OUT
XDP_DA2_USB_EXTC_OC_L
23
OUT
XDP_DA3_USB_EXTD_OC_L
23
OUT
XDP_DB0_USB_EXTB_OC_EHCI_L
23
OUT
XDP_DB1_USB_EXTD_OC_EHCI_L
23
OUT
XDP_DB2_AP_PWR_EN
23
IN
XDP_DB3_SDCONN_STATE_CHANGE
23
OUT
XDP_FC0
23
OUT
XDP_FC1
23
OUT
XDP_DC0_ISOLATE_CPU_MEM_L
23
IN
XDP_DC1_MXM_GOOD
23
IN
XDP_DC2_DP_AUXCH_ISOL
23
IN
XDP_DC3_SATARDRVR_EN
23
IN
XDP_DD0_DP_GPU_TBT_SEL
23
IN
XDP_DD1_JTAG_ISP_TCK
23
IN
XDP_DD2_AUD_IPHS_SWITCH_EN
23
IN
XDP_DD3_ENET_LOW_PWR
23
IN
B
PCH/XDP Signal Isolation Notes:
- Following Intel’s Debug Prot Design Guid for HR and CR v1.3
doc id 404081.
Initially, stuffing both 33 and 0 ohms and validate whether
it is functional in that state, else add BOM options.
- For isolated GPIOs:
- ’Output’ non-XDP signals require pulls.
- ’Output’ PCH/XDP signals require pulls.
R252x, R253x, R257x and R259x should be placed where signal path
needs to split between route from PCH to J2550
and path to non-XDP signal destination.
ALL_SYS_PWRGD
24 45 73
17 23 45
OUT
IN
PM_PWRBTN_L
PLACE_NEAR=J2550.39:2.54mm
PLACE_NEAR=U4900.P17:2.54mm
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
1K
0
(R2520-R2537)
XDP
XDP
XDP
XDP
XDP
XDP
XDP
XDP
XDP
XDP
XDP
XDP
XDP
XDP
XDP
XDP
XDP
XDP
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
XDP
21
1/20W
5% 201MF
XDP
21
1/20W
5% 201MF
PCH SIGNALS
1/20W
5% 201MF
5% MF
1/20W
1/20W
5% 201MF
1/20W
5% 201MF
5% 201MF
1/20W
1/20W
5% 201MF
1/20W
5%
1/20W
5% 201MF
1/20W
5% 201MF
1/20W
5% 201MF
1/20W
5% 201MF
1/20W
5% 201MF
1/20W
5% 201MF
1/20W
5% 201MF
1/20W
5% 201MF
1/20W
5%
1/20W
5%
5% 201MF
1/20W
XDP_DB0_PCH_GPIO43_USB_EXTB_OC_EHCI_L
XDP_DB3_PCH_GPIO14_SDCONN_STATE_CHANGE
XDP_DD2_PCH_GPIO16_AUD_IPHS_SWITCH_EN_PCH
A
1/20W
XDP_DA0_PCH_GPIO59_USB_EXTA_OC_L
XDP_DA1_PCH_GPIO40_USB_EXTB_OC_L
201
XDP_DA2_PCH_GPIO41_USB_EXTC_OC_L
XDP_DA3_PCH_GPIO42_USB_EXTD_OC_L
XDP_DB1_PCH_GPIO9_USB_EXTD_OC_EHCI_L
201MF
XDP_FC0_PCH_GPIO15_MEM_VDD_SEL_1V5_L
XDP_DC0_PCH_GPIO28_ISOLATE_CPU_MEM_L
XDP_DC2_PCH_GPIO21_DP_AUXCH_ISOL
XDP_DC3_PCH_GPIO19_SATARDRVR_EN
XDP_DD0_PCH_GPIO36_DP_GPU_TBT_SEL
XDP_DD1_PCH_GPIO37_JTAG_ISP_TCK
201MF
201MF
XDP_DD3_PCH_GPIO49_ENET_LOW_PWR_PCH
23 48
23 48
16 23
IN
XDP_BPM_L<0>
10 78
IN
XDP_BPM_L<1>
10 78
IN
XDP_BPM_L<2>
10 78
IN
XDP_BPM_L<3>
10 78
IN
CPU_CFG<10>
9
78
IN
CPU_CFG<11>
9
78
IN
XDP_OBSDATA_B<0>
XDP_OBSDATA_B<1>
XDP_OBSDATA_B<2>
XDP_OBSDATA_B<3>
XDP_CPU_PWRGD
XDP_CPU_PWRBTN_L
XDP_CPU_CFG<0>
XDP_VR_READY
=SMBUS_XDP_SDA
23 48
BI
=SMBUS_XDP_SCL
23 48
IN
XDP_CPU_TCK
10 23 78
OUT
R2581
21
1/20W
5%
201
MF
1K
XDP_DB2_PCH_GPIO10_AP_PWR_EN
XDP_FC1_PCH_GPIO0
XDP_DC1_PCH_GPIO35_MXM_GOOD
TP_XDP_PCH_OBSFN_A<0>
6
TP_XDP_PCH_OBSFN_A<1>
6
XDP_DA0_USB_EXTA_OC_L
23
XDP_DA1_USB_EXTB_OC_L
23
XDP_DA2_USB_EXTC_OC_L
23
XDP_DA3_USB_EXTD_OC_L
23
TP_XDP_PCH_OBSFN_B<0>
6
TP_XDP_PCH_OBSFN_B<1>
6
XDP_DB0_USB_EXTB_OC_EHCI_L
23
XDP_DB1_USB_EXTD_OC_EHCI_L
23
XDP_DB2_AP_PWR_EN
23
XDP_DB3_SDCONN_STATE_CHANGE
23
XDP_PCH_S5_PWRGD
6
XDP_PCH_PWRBTN_L
6
TP_XDPPCH_HOOK2
6
TP_XDPPCH_HOOK3
6
=SMBUS_XDP_SDA
BI
=SMBUS_XDP_SCL
IN
XDP_PCH_TCK
OUT
R2580
201
NO STUFF
1K
R2540
1/16W
MF-LF
21
5%
MF
402
1K
5%
1
2
OBSDATA_A0
OBSDATA_A1
OBSDATA_A2
OBSDATA_A3
OBSDATA_B0
OBSDATA_B1
OBSDATA_B2
OBSDATA_B3
PWRGD/HOOK0
VCC_OBS_AB
18 23
IN
18 23
IN
18
IN
18
IN
18
IN
18
IN
18 23
OUT
18 23
IN
19 23
IN
19
IN
19 23
OUT
19
OUT
16 23
OUT
16 23
OUT
19
OUT
19 23
OUT
19 23
OUT
19 23
OUT
OBSDATA_A0
OBSDATA_A1
OBSDATA_A2
OBSDATA_A3
OBSDATA_B0
OBSDATA_B1
OBSDATA_B2
OBSDATA_B3
PWRGD/HOOK0
VCC_OBS_AB
OBSFN_A0
OBSFN_A1
OBSFN_B0
OBSFN_B1
HOOK1
HOOK2
HOOK3
TCK1
TCK0
C2500
0.1UF
X7R-CERM
NOTE: This is not the standard XDP pinout.
Use with 921-0133 Adapter Flex to
support chipset debug.
OBSFN_A0
OBSFN_A1
OBSFN_B0
OBSFN_B1
HOOK1
HOOK2
HOOK3
TCK1
TCK0
C2580
0.1UF
X7R-CERM
CPU Micro2-XDP
CRITICAL
XDP_CONN
J2500
DF40RC-60DP-0.4V
M-ST-SM
62
8 7
10
12 11
14 13
16 15
18 17
20219
22 21
24 23
26 25
28 27
30329
32 31
34 33
36 35
38 37
40439
42 41
44 43
46 45
48 47
50549
SDA
SCL
XDP
0402
10%
16V
1
2
52 51
54 53
56 55
NC
58 57
60659
64 63
998-2516
PCH Micro2-XDP
CRITICAL
XDP_CONN
J2550
DF40RC-60DP-0.4V
M-ST-SM
62
8 7
10
12 11
14 13
16 15
18 17
20219
22 21
24 23
26 25
28 27
30329
32 31
34 33
36 35
38 37
40439
42 41
44 43
46 45
48 47
50549
SDA
SCL
XDP
0402
10%
16V
1
2
52 51
54 53
56 55
NC
58 57
60659
64 63
998-2516
NOTE: This is not the standard XDP pinout.
Use with 921-0133 Adapter Flex to
support chipset debug.
61
1
9
OBSFN_C0
OBSFN_C1
OBSDATA_C0
OBSDATA_C1
OBSDATA_C2
OBSDATA_C3
OBSFN_D0
OBSFN_D1
OBSDATA_D0
OBSDATA_D1
OBSDATA_D2
OBSDATA_D3
ITPCLK/HOOK4
ITPCLK#/HOOK5
VCC_OBS_CD
RESET#/HOOK6
DBR#/HOOK7
NOTE: XDP_DBRESET_L pulled-up to 3.3V on PCH Support Page
TDO
TRSTn
TDI
TMS
XDP_PRESENT#
XDP
1
C2501
0.1UF
10%
16V
2
X7R-CERM
0402
=PP3V3_S5_XDP
61
1
9
OBSFN_C0
OBSFN_C1
OBSDATA_C0
OBSDATA_C1
OBSDATA_C2
OBSDATA_C3
OBSFN_D0
OBSFN_D1
OBSDATA_D0
OBSDATA_D1
OBSDATA_D2
OBSDATA_D3
ITPCLK/HOOK4
ITPCLK#/HOOK5
VCC_OBS_CD
RESET#/HOOK6
DBR#/HOOK7
NOTE: XDP_DBRESET_L pulled-up to 3.3V on PCH Support Page
TDO
TRSTn
TDI
TMS
XDP_PRESENT#
XDP
1
C2581
0.1UF
10%
16V
2
X7R-CERM
0402
CPU_CFG<16>
CPU_CFG<17>
CPU_CFG<0>
CPU_CFG<1>
CPU_CFG<2>
CPU_CFG<3>
CPU_CFG<8>
CPU_CFG<9>
CPU_CFG<4>
CPU_CFG<5>
CPU_CFG<6>
CPU_CFG<7>
XDP_CPU_CLK100M_P
78
XDP_CPU_CLK100M_N
78
XDP_CPURST_L
78
XDP_DBRESET_L
XDP_CPU_TDO
XDP_CPU_TRST_L
XDP_CPU_TDI
XDP_CPU_TMS
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
IN
OUT
OUT
OUT
9
9
9
23 78
9
78
9
78
9
78
9
78
9
78
9
78
9
78
9
78
9
78
10 23 24 78
10 23 78
10 23 78
10 23 78
10 23 78
PCH SIGNALS
XDP_DA0_PCH_GPIO59_USB_EXTA_OC_L
18 23
OUT
XDP_DA1_PCH_GPIO40_USB_EXTB_OC_L
18 23
OUT
XDP_DB2_PCH_GPIO10_AP_PWR_EN
18 23
IN
XDP_DB3_PCH_GPIO14_SDCONN_STATE_CHANGE
18 23
OUT
XDP_DC3_PCH_GPIO19_SATARDRVR_EN
16 23
IN
XDP_DC0_PCH_GPIO28_ISOLATE_CPU_MEM_L
19 23
OUT
XDP_DC2_PCH_GPIO21_DP_AUXCH_ISOL
16 23
IN
XDP_FC0_PCH_GPIO15_MEM_VDD_SEL_1V5_L
19 23
IN
7
XDP_DD1_PCH_GPIO37_JTAG_ISP_TCK
XDP_DD2_PCH_GPIO16_AUD_IPHS_SWITCH_EN_PCH
19 23
OUT
XDP_DD3_PCH_GPIO49_ENET_LOW_PWR_PCH
19 23
OUT
XDP_FC0
XDP_FC1
XDP_DC0_ISOLATE_CPU_MEM_L
XDP_DC1_MXM_GOOD
XDP_DC2_DP_AUXCH_ISOL
XDP_DC3_SATARDRVR_EN
TP_XDP_PCH_OBSFN_D<0>
TP_XDP_PCH_OBSFN_D<1>
XDP_DD0_DP_GPU_TBT_SEL
XDP_DD1_JTAG_ISP_TCK
XDP_DD2_AUD_IPHS_SWITCH_EN
XDP_DD3_ENET_LOW_PWR
TP_XDP_PCH_HOOK4
TP_XDP_PCH_HOOK5
XDPPCH_PLTRST_L
XDP_DBRESET_L
XDP_PCH_TDO
TP_XDP_PCH_TRST_L
XDP_PCH_TDI
XDP_PCH_TMS
R2515
R2516
R2505
23
23
23
23
23
23
6
6
23
23
23
23
6
6
24
IN
10 23 24 78
OUT
16 23
IN
16 23
OUT
16 23
OUT
XDP_CPU_TDO
10 23 78
XDP_CPU_TDI
10 23 78
XDP_CPU_TMS
10 23 78
XDP_CPU_TCK
10 23 78
XDP_CPU_TRST_L
10 23 78
XDP
0
0
1K
R2590
R2591
R2596
R2597
R2573
R2570
R2572
R2574
PLACE_NEAR=R1841.1:2.54mm
21
ITPXDP_CLK100M_P
1/20W
5% 201MF
XDP
PLACE_NEAR=R1840.1:2.54mm
21
ITPXDP_CLK100M_N
1/20W
5% 201MF
XDP
PLACE_NEAR=U1000.G3:2.54mm
21
CPU_RESET_L
5% 201MF
1/20W
0
0
0
0
0
0
0
0
R2575
R2576
R2577
0
0
0
XDP_PCH_TDO
16 23
XDP_PCH_TDI
16 23
XDP_PCH_TMS
16 23
XDP_PCH_TCK
16 23
1K series R on PCH Support Page
R2510
R2511
R2512
R2513
R2514
21
21
5% 201MF
21
5% 201MF
21
5% 201MF
21
5% 201MF
21
5% 201MF
21
21
5% 201MF
21
5% 201MF
21
5% 201MF
21
5% 201MF
R2550
R2551
R2552
R2556
SYNC_MASTER=J31_MLB
PAGE TITLE
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
51
51
51
51
51
16 78
IN
16 78
IN
10 24
IN
Non-XDP Signals
MF 2015%
1/20W
1/20W
1/20W
1/20W
1/20W
1/20W
MF 2015%
1/20W
1/20W
1/20W
AUD_IPHS_SWITCH_EN_PCH
1/20W
1/20W
51
51
51
51
CPU & PCH XDP
Apple Inc.
R
6 3
=PPVCCIO_S0_XDP
7
23
XDP
PLACE_NEAR=J2500.52:2.54mm
12
1/20W
5% 201MF
XDP
PLACE_NEAR=U1000.K61:2.54mm
12
1/20W
5% 201MF
XDP
PLACE_NEAR=U1000.H59:2.54mm
12
1/20W
5% 201MF
XDP
PLACE_NEAR=U1000.J58:2.54mm
12
1/20W
5% 201MF
XDP
PLACE_NEAR=U1000.H63:2.54mm
12
1/20W
5% 201MF
USB_EXTA_OC_L
USB_EXTB_OC_L
SDCONN_STATE_CHANGE
AP_PWR_EN
SATARDRVR_EN
ISOLATE_CPU_MEM_L
DP_AUXCH_ISOL
MEM_VDD_SEL_1V5_L
JTAG_ISP_TCK
ENET_LOW_PWR_PCH
=PP1V05_SUS_PCH_JTAG
7
XDP
PLACE_NEAR=J2550.52:2.54mm
12
1/20W
5% 201MF
XDP
PLACE_NEAR=U1800.K5:2.54mm
12
1/20W
5% 201MF
XDP
PLACE_NEAR=U1800.H7:2.54mm
12
1/20W
5% 201MF
XDP
PLACE_NEAR=U1800.J3:2.54mm
12
1/20W
5% 201MF
SYNC_DATE=06/13/2011
IN
IN
OUT
IN
OUT
OUT
OUT
OUT
OUTOUT
OUT
OUT
DRAWING NUMBER
051-9058
REVISION
6.0.0
BRANCH
PAGE
25 OF 109
SHEET
23 OF 86
124578
42
42
18 32 73
24
16 41
26
16 75
67
8
19 19 23
19 24
19 24
SIZE
D
C
B
A
D
8 7 6 5 4 3
12
D
GreenClk 25MHz Power
Ethernet XTAL Power
SB XTAL Power
T29 XTAL Power
C
B
A
System RTC Power Source & 32kHz / 25MHz Clock Generator
=PPVBAT_G3_SYSCLK
7
Coin-Cell: VBAT (300-ohm & 10uF RC)
No Coin-Cell: 3.42V G3Hot (no RC)
=PP3V3_S5_SYSCLK
7
Coin-Cell & G3Hot: 3.42V G3Hot
Coin-Cell & No G3Hot: 3.3V S5
=PP3V3_ENET_SYSCLK
7
=PPVDDIO_ENET_CLK
7
=PPVDDIO_S0_SBCLK
7
=PPVDDIO_T29_CLK
7
1
C2624
0.1UF
X5R-CERM
C2605
12PF
2 1
5%
50V
C0G-CERM
0402
C2606
12PF
21
5%
50V 4
C0G-CERM
0402
SYSCLK_CLK25M_X2
CRITICAL
Y2605
NC
SM-3.2X2.5MM
42
NC
31
25.000MHZ-12PF-20PPM
NOTE: 30 PPM crystal required
0201
10%
16V
2
C2622
0.1UF
X5R-CERM
0201
R2605
0
5%
1/20W
MF
201
No Coin-Cell: 3.3V S5
1
C2620
0.1UF
10%
16V
21
10%
16V
2
X5R-CERM
0201
SYSCLK_CLK25M_X2_R
NO STUFF
1
R2606
1M
5%
1/20W
MF
201
2
SYSCLK_CLK25M_X1
No bypass necessary
5172
1
1
C2602
1UF
10%
10V
2
2
X5R
402-1
11
6
14
3
4
VDD_25M
U2600
SLG3NB148A
CRITICAL
VDDIO_25M_A
VDDIO_25M_B
VDDIO_25M_C
X2
X1
+V3.3A
TQFN
VDD_RTC_OUT
THRM
GND
PAD
16107
13
VBAT and +V3.3A are
internally ORed to
+3.42V
create VDD_RTC_OUT.
+V3.3A should be first
available ~3.3V power
to reduce VBAT draw.
12
32KHZ_A
9
25MHZ_A
8
25MHZ_B
15
25MHZ_C
1
SYSCLK_CLK32K_RTC
SYSCLK_CLK25M_SB
SYSCLK_CLK25M_ENET
SYSCLK_CLK25M_T29
=PPVRTC_G3_OUT
For SB RTC Power
1
C2610
1UF
10%
6.3V
2
CERM
402
GPIO Glitch Prevention
=PP3V3_S3_PCH_GPIO
7
18 24
ENET_MEDIA_SENSE ISOLATION CIRCUIT
ENET_MEDIA_SENSE
36
IN
=PP3V3_S3_PCH_GPIO
7
18 24
R2611
100K
5%
1/20W
MF
201
ENET_MEDIA_SENSE_EN_L
R2612
0
5%
1/16W
MF-LF
402
ENET_MEDIA_SENSE_EN
NO STUFF
R2663
0
21
5%
1/16W
MF-LF
402
7
24
1
C2660
0.1UF
20%
10V
2
CERM
402
R2662
3.0K
SYS_PWROK_R
R2660
0
5%
1/16W
MF-LF
402
21
5%
1/16W
MF-LF
402
21
ENET_LOW_PWR_PCH
19 23
IN
PM_PCH_PWROK
17 24
IN
FW_PWR_EN_PCH
19
IN
TBT_PWR_EN_PCH
16
IN
PM_PCH_PWROK
17 24
IN
AUD_IPHS_SWITCH_EN_PCH
19 23
IN
=PP3V3_S5_PCHPWRGD
7
24
=PP3V3_S0_SB_PM
7
24
23 45 73
IN
68
IN
=PP3V3_S3_PCH_GPIO
7
18 24
PCH S0 PWRGD
ALL_SYS_PWRGD
CPUIMVP_PGOOD
CRITICAL
1
2
5
6
CRITICAL
1
2
5
6
R2650
1/16W
MF-LF
VCC
U2601
SOT833
08
A1
B1
A2
B2
GND
VCC
U2652
SOT833
08
A1
B1
A2
B2
GND
1
1K
5%
402
2
1
8
Y1
Y2
4
74LVC2G08GT
8
Y1
Y2
4
74LVC2G08GT
35 45 46
C2650
2
7
ENET_LOW_PWR
3
FW_PWR_EN
1
C2652
2
7
TBT_PWR_EN
3
AUD_IPHS_SWITCH_EN
5
MC74VHC1G08
1
U2650
2
3
SMC_DELAYED_PWRGD
0.1UF
20%
10V
CERM
402
0.1UF
20%
10V
CERM
402
1
C2600
0.1UF
20%
10V
2
CERM
402
SC70-HF
4
PM_S0_PGOOD
30 36
OUT
39
OUT
=PP3V3R1V5_S0_PCH_VCCSUSHDA
35
OUT
62
OUT
=PP3V3_S5_PCHPWRGD
5
MC74VHC1G08
1
2
U2660
3
SC70-HF
4
6 3
Ethernet WAKE# Isolation
=PP3V3_ENET_PHY
1
Q2630
SSM3K15AMFVAPE
VESM
PCIE_WAKE_L
6
17 32 36
OUT
D
3
1
GS
2
R2630
10K
5%
1/16W
MF-LF
402
2
ENET_WAKE_L
MAKE_BASE=TRUE
7
36 71
=ENET_WAKE_L
18 26
IN
PCH Reset Button
=PP3V3_S0_SB_PM
7
24
1
R2695
10K
5%
1/16W
MF-LF
402
2
21
PM_SYSRST_L
OMIT
1
R2697
0
5%
1/16W
MF-LF
402
2
SILK_PART=SYS RESET
=PP3V3_S0_RSTBUF
7
16
OUT
=PP3V3_S3_SDBUF
1
C2670
0.1UF
20%
10V
2
CERM
402
SDCONN_STATE_CHANGE_SMC
SOT665
4
Y
CRITICAL
5
U2670
A
B
3
2
1
R2610
12K
402
CRITICAL
SSM6N37FEAPE
Q2610
SOT563
1
2
5
SSM6N37FEAPE
Q2610
1
SOT563
2
2
PM_PCH_SYS_PWROK
PLACE_NEAR=U1800.L22:5.54mm
NO STUFF
1
R2661
0
5%
1/16W
MF-LF
402
2
XDP_DBRESET_L
10 23
IN
78
OUT
OUT
OUT
OUT
7
5%
21
ENET_MEDIA_SENSE_RDIV
1/16WMF-LF
3
D
SG
4
6
D
SG
1
PM_PCH_PWROK
MAKE_BASE=TRUE
PM_PCH_APWROK
23
XDP
R2696
0
5%
1/16W
MF-LF
16 81
16 81
36 81
33 81
402
SDCONN_STATE_CHANGE ISOLATION
SDCONN_STATE_CHANGE
TC7SZ08FEAPE
17 23 45
OUT
17 24
OUT
17
OUT
Platform Reset Connections
PLT_RESET_L
MAKE_BASE=TRUE
IN
17 45
BI
2
1
C2680
0.1UF
20%
10V
2
CERM
402
18 81
IN
18
IN
18
IN
PCH uses HDA_SDO as a power-up strap. If low, ME functions normally.
7
If high, ME is disabled. This allows for full re-flashing of SPI ROM.
SMC controls strap enable to allow in-field control of strap setting.
Q2620 & 5V pull-up allows circuit to work regardless of HDA voltage.
30 46
=PP3V3R1V5_S0_PCH_VCCSUSHDA
7
20 22 24
SPI_DESCRIPTOR_OVERRIDE_L
45
IN
Unbuffered
R2681
33
21
5%
1/16W
MF-LF
402
R2671
0
21
5%
1/16W
MF-LF
402
Buffered
5
U2680
74LVC1G07
SC70
NC
3
1
NC
LPC_CLK33M_SMC_R
LPC_CLK33M_LPCPLUS_R
PCH_CLK33M_PCIOUT
PLT_RST_BUF_L
MAKE_BASE=TRUE
1
R2680
100K
5%
1/16W
MF-LF
402
2
PLACE_NEAR=U1800.H49:5.1mm
PLACE_NEAR=U1800.H43:5.1mm
PLACE_NEAR=U1800.H40:2.54MM:5.1mm
R2627
22
5%
1/16W
MF-LF
402
R2629
22
5%
1/16W
MF-LF
402
21
R2626
21
PCH ME Disable Strap
Q2620
SSM6N37FEAPE
SOT563
D
3
Q2620
SSM6N37FEAPE
SOT563
5
SPI_DESCRIPTOR_OVERRIDE_LS5V
S G
SPI_DESCRIPTOR_OVERRIDE
4
6
D
2
SG
1
SYNC_MASTER=K90I_MLB SYNC_DATE=02/15/2011
PAGE TITLE
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
LPC_RESET_L
LPCPLUS_RESET_L
MAKE_BASE=TRUE
R2683
33
21
SMC_LRESET_L
5%
1/16W
MF-LF
402
=ENET_RESET_L
R2688
0
21
AP_RESET_L
5%
1/16W
MF-LF
402
XDP
R2689
1/16W
MF-LF
R2693
1/16W
MF-LF
PCA9557D_RESET_L
1K
21
XDPPCH_PLTRST_L
5%
402
=T29_RESET_L
Series R is R3803
0
21
BKLT_PLT_RST_L
5%
402
=FW_RESET_L
Series R is R4283
CPU_RESET_L
VTT voltage divider on CPU page
LPC_CLK33M_SMC
22
21
LPC_CLK33M_LPCPLUS
5%
1/16W
MF-LF
402
PCH_CLK33M_PCIIN
=PP5V_S0_PCH
7
22
Chipset Support
Apple Inc.
R
1
R2620
100K
5%
1/20W
MF
201
2
1
R2621
1K
5%
1/20W
MF
201
2
HDA_SDOUT_R
IPD = 9-50k
DRAWING NUMBER
051-9058
REVISION
BRANCH
PAGE
SHEET
124578
81
OUT
6
47
OUT
45
OUT
30
OUT
32
OUT
31
OUT
23
OUT
35
OUT
77
OUT
39
OUT
10 23
OUT
45 81
OUT
6
47 81
OUT
16 80
OUT
16 81
OUT
6.0.0
26 OF 109
24 OF 86
SIZE
D
C
B
A
D
8 7 6 5 4 3
12
BOM GROUP
HUB_ALLREM
HUB_1NONREM
USB MUX FOR LS/FS INTERNAL DEVICES
R2701
1
R2706
10K
5%
1/16W
MF-LF
402
2
1
2
C2706
X7R-CERM
100
5%
1/16W
MF-LF
402
C2702
0.1UF
10%
16V
X7R-CERM
0402
0.1UF
BYPASS=U2700.5::2MM
1
2
BYPASS=U2700.23::2MM
1
2
USB_HUB_TEST
USB_HUB_RESET_L
25
USB_HUB_XTAL1
USB_HUB_XTAL2_R
C2708
10%
16V
0402
21
USB_HUB_NONREM0
USB_HUB_NONREM1
USB_HUB_CFG_SEL0
USB_HUB_CFG_SEL1
1
R2707
10K
5%
1/16W
MF-LF
402
2
C2703
0.1UF
10%
16V
X7R-CERM
0402
0.1UF
X7R-CERM
1
10%
16V
2
0402
5
VDD33
SYM VER 1
U2700
USB2513B
11
TEST
26
RESET*
33
XTALIN/CLKIN
32
XTALOUT
28
SUSP_IND/LOCAL_PWR/NON_REM0
22
SDA/SMBDATA/NON_REM1
24
SCL/SMBCLK/CFG_SEL0
25
HS_IND/CFG_SEL1
QFN
OMIT
THRM_PAD
PPUSB_HUB2_VDD1V8
MIN_LINE_WIDTH=0.4MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=1.8V
PPUSB_HUB2_VDD1V8PLL
MIN_LINE_WIDTH=0.4MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=1.8V
3629231510
34
14
CRFILT
PLLFILT
USBDM_DN1/PRT_DIS_M1
USBDP_DN1/PRT_DIS_P1
USBDM_DN2/PRT_DIS_M2
USBDP_DN2/PRT_DIS_P2
USBDM_DN3/PRT_DIS_M3
USBDP_DN3/PRT_DIS_P3
PRTPWR1/BC_EN1*
PRTPWR2/BC_EN2*
PRTPWR3/BC_EN3*
37
IPU
IPU
IPU
IPU
OCS1*
OCS2*
OSC3*
RBIAS
VBUS_DET
USBDM_UP
USBDP_UP
1
C2711
0.1UF
10%
16V
2
X7R-CERM
0402
1
USBHUB_DN1_N
2
USBHUB_DN1_P
3
USBHUB_DN2_N
4
USBHUB_DN2_P
6
USBHUB_DN3_N
7
USBHUB_DN3_P
8
USBHUB_DN4_N
NC
9
USBHUB_DN4_P
NC
12
TP_USB_HUB_PRTPWR1
16
NC_USB_HUB_PRTPWR2
18
NC_USB_HUB_PRTPWR3
20
NC_USB_HUB_PRTPWR4
NC
13
TP_USB_HUB_OCS1
17
NC_USB_HUB_OCS2
19
NC_USB_HUB_OCS3
21
NC_USB_HUB_OCS4
NC
35
USB_HUB_RBIAS
27
USB_HUB_VBUS_DET
30
USB_HUB_UP_N
31
USB_HUB_UP_P
PCH PORT 7 (EHCI1)
1
C2712
2
1UF
10%
16V
X5R
402
8
BI
8
BI
8
BI
8
BI
8
BI
8
BI
25
BI
25
BI
18 80
BI
18 80
BI
=PP3V3_S3_USB_HUB
7
D
C
25
1/16W
MF-LF
1/16W
MF-LF
10K
10K
HUB_NONREM0_1
1
1
R2703
10K
5%
5%
1/16W
MF-LF
402
402
2
2
HUB_NONREM0_0
1
1
R2705
10K
5%
5%
1/16W
MF-LF
402
402
2
2
HUB_NONREM1_1
R2702
HUB_NONREM1_0
R2704
J5 USES 197S0181 FOR Y2700 DUE TO HEIGHT LIMITATION
J3X USE 197S0284 FOR Y2700 TO SAVE COST
BYPASS=U27000.5::5MM
BYPASS=U2700.23::5MM
USB_HUB_XTAL2
CRITICAL
1
C2709
18PF
5%
50V
2
C0G-CERM
0402
=PP3V3_S3_USB_RESET
7
1
C2700
4.7UF
20%
6.3V
2
X5R
603
BYPASS=U2700.15::2MM
1
C2704
4.7UF
20%
6.3V
2
X5R
603
Y2700
24.000M-60PPM-16PF
1
R2710
0
5%
1/16W
MF-LF
402
2
5X3.2X1.4-SM
CRITICAL
R2700
1M
5%
1/16W
MF-LF
402
21
21
1
C2701
0.1UF
10%
16V
2
X7R-CERM
0402
BYPASS=U2700.10::2MM
1
C2705
0.1UF
10%
16V
2
X7R-CERM
0402
BYPASS=U2700.36::2MM
BYPASS=U2650.29::2MM
CRITICAL
1
C2710
18PF
5%
50V
2
C0G-CERM
0402
HUB_2NONREM
HUB_3NONREM
NON_REM 1 : NON_REM 0 STRAP PIN CFG
0 : 0 ALL PORTS ARE REMOVABLE
0 : 1 PORT 1 IS NON REMOVABLE
1 : 0 PORT 1&2 ARE NON REMOVABLE
CANNOT INDICATE ALL 4 PORTS ARE NON REMOVABLE ON USB2514B VIA STARPPING, PROGRAM NON_REMOVABLE DEVICE REGISTER 09H
1
2
C2713
0.1UF
10%
16V
X7R-CERM
0402
1
2
C2714
1UF
10%
16V
X5R
402
BLUETOOTH FOR J5 & J3X
TP/KB FOR J5, IR FOR J3X
25
SMC DEBUG PORT FOR J5, TP/KB FOR J3X
25
NC FOR J5, SMC DEBUG PORT FOR J3X
=PP3V3_S3_USB_HUB
1
R2708
10K
5%
1/16W
MF-LF
402
2
CRITICAL
1
R2709
12K
1%
1/16W
MF
402
2
1 : 1 PORT 1&2&3 ARE NON REMOVABLE
PART#
338S0824
338S0923
338S0983
J5 ENGINEERING: USE USB2513B PRODUCTION: USE USB2512B
J3X ENGINEERING: USE USB2514B PRODUCTION: USE USB2513B
USBHUB_DN3_N
8
25
USBHUB_DN3_P
8
25
USBHUB_DN4_N
25
USBHUB_DN4_P
25
7
25
HUB_NONREM1_0,HUB_NONREM0_0
HUB_NONREM1_0,HUB_NONREM0_1
HUB_NONREM1_1,HUB_NONREM0_0
HUB_NONREM1_1,HUB_NONREM0_1
DESCRIPTION
QTY
USB HUB 2514B
1
1
USB HUB 2513B
1
USB HUB 2512B
BOM OPTIONS
BOM TABLE
NOSTUFF
R2716
10K
5%
1/16W
MF-LF
402
NOSTUFF
1
R2717
10K
5%
1/16W
MF-LF
402
2
1
2
REFERENCE DESIGNATOR(S)
U2700
U2700
U2700
=PP3V3_S3_USB_HUB
NOSTUFF
R2718
10K
5%
1/16W
MF-LF
402
NOSTUFF
1
R2719
10K
5%
1/16W
MF-LF
402
2
1
2
CRITICAL BOM OPTION
CRITICAL
CRITICAL
CRITICAL
USBHUB2514B
USBHUB2513B
USBHUB2512B
7
25
TABLE_BOMGROUP_HEAD
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
D
TABLE_5_HEAD
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
C
SIZE
B
A
D
B
PLACE_NEAR=U2700.26:2.5MM
A
C2715
0.1UF
X7R-CERM
10%
16V
0402
1
R2712
10K
5%
1/16W
MF-LF
402
2
USB_HUB_RESET_L
1
2
25
PCH PORT 9 (EHCI2)
PCH PORT 1 (XHCI)
USB XHCI/EHCI2 PORT MUX FOR EXT B
=PP3V3_S3_USBMUX
7
1
18
80
18 80
18
80
18 80
BI
BI
BI
BI
USB_EXTB_EHCI_P
USB_EXTB_EHCI_N
USB_EXTB_XHCI_P
USB_EXTB_XHCI_N
C2760
0.1UF
CERM
20%
10V
2
402
5
4
7
6
8
M+
M-
U2760
PI3USB102ZLE
D+
D-
9
VCC
TQFN
CRITICAL
GND
3
1
Y+
2
Y-
PULL-UP TO 3.3V SUS ON PCH PAGE, SEL PIN IS LEAKAGE-SAFE
10
SELOE*
USB_EXTB_MUX_P
USB_EXTB_MUX_N
USB_EXTB_SEL_XHCI
SEL=0 CHOOSE USB EHCI2 PORT
SEL=1 CHOOSE USB XHCI PORT
43 80
BI
43 80
BI
16
IN
TO CONNECTOR
PCH GPIO60
6 3
SYNC_MASTER=LINDA_J30
PAGE TITLE
USB HUB & MUX
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
SYNC_DATE=09/19/2011
DRAWING NUMBER
051-9058
REVISION
6.0.0
BRANCH
PAGE
27 OF 109
SHEET
25 OF 86
124578
8 7 6 5 4 3
The circuit below handles CPU and VTT power during S0->S3->S0 transitions, as well
as isolating the CPU’s SM_DRAMRST# output from the SO-DIMMs when necessary.
ISOLATE_CPU_MEM_L GPIO state during S3<->S0 transitions determines behavior of signals.
D
WHEN HIGH: CPU 1.5V remains powered in S3, VTT follows S0 rails, MEM_RESET_L not isolated.
WHEN LOW: CPU 1.5V follows S0 rails, VTT ensures clean CKE transition, MEM_RESET_L isolated.
P1V5CPU_EN = (ISOLATE_CPU_MEM_L + PM_SLP_S3_L) * PM_SLP_S4_L
MEMVTT_EN = (ISOLATE_CPU_MEM_L + PLT_RST_L) * PM_SLP_S3_L
MEM_RESET_L = !ISOLATE_CPU_MEM_L + CPU_MEM_RESET_L
PM_SLP_S4_L
6
17 32 45 73
IN
=PP3V3_S3_MEMRESET
7
C
ISOLATE_CPU_MEM_L
23
IN IN
=PP5V_S3_MEMRESET
7
26
CPUMEM_S0
1
R2815
100K
5%
1/16W
MF-LF
402
2
CPUMEM_S0
Q2815
SSM6N37FEAPE
SOT563
B
NOSTUFF
1
C2817
0.047UF
10%
6.3V
2
X5R
201
=MEM_RESET_L
10
IN
6
MEMRESET_ISOL_LS5V_L
31
2
D
S G
CPU_MEM_RESET_L
MAKE_BASE=TRUE
1
CPUMEM_S0
CPUMEM_S0
Q2800
SSM6N37FEAPE
SOT563
CPUMEM_S0
CPUMEM_S0
Q2800
SSM6N37FEAPE
SOT563
CPUMEM_S0
SSM6N37FEAPE
5
S G
4
R2801
100K
1/16W
MF-LF
5
R2802
100K
1/16W
MF-LF
2
Q2815
5%
402
D
SG
5%
402
D
SG
SOT563
1
2
P1V5CPU_EN_L
3
4
1
2
MEMVTT_EN_L
6
1
D
3
SSM6N37FEAPE
SSM6N37FEAPE
CPUMEM_S0
1
R2816
1K
5%
1/16W
MF-LF
402
2
CPUMEM_S0
Q2805
SOT563
CPUMEM_S0
Q2810
SOT563
2
3
4
2
3
4
D
S G
D
S G
1
C2816
2
CPUMEM_S3
R2817
0
21
5%
1/16W
MF-LF
402
Step ISOLATE_CPU_MEM_L PLT_RESET_L PM_SLP_S3_L PM_SLP_S4_L CPU_MEM_RESET_L MEM_RESET_L MEMVTT_EN P1V5CPU_EN
S0
0 1 1 1 1 1 CPU_MEM_RESET_L 1 1
1 0 1 1 1 1 1 1 1
to
2 0 0 1 1 1 1 0 1
A
3 0 0 0 1 X 1 0 0
S3
4 0 0 1 1 X 1 0 1
5 0 1 1 1 0 (*) 1 1 1
to
6 0 1 1 1 1 1 1 1
7 1 1 1 1 1 CPU_MEM_RESET_L 1 1
S0
(*) CPU_MEM_RESET_L asserts due to loss of PM_MEM_PWRGD, must wait for software to clear before deasserting ISOLATE_CPU_MEM_L GPIO.
NOTE: In the event of a S3->S5 transition ISOLATE_CPU_MEM_L will still be asserted on next S5->S0
transition. Rails will power-up as if from S3, but MEM_RESET_L will not properly assert. Software
must deassert ISOLATE_CPU_MEM_L and then generate a valid reset cycle on CPU_MEM_RESET_L.
6 3
CPUMEM_S0
1
R2805
10K
5%
1/16W
MF-LF
402
2
P1V5CPU_EN
6
D
SG
1
CPUMEM_S0
Q2805
SSM6N37FEAPE
SOT563
5
PM_SLP_S3_L
CPUMEM_S0
1
R2810
10K
5%
1/16W
MF-LF
402
2
MEMVTT_EN
6
D
SG
1
CPUMEM_S0
Q2810
SSM6N37FEAPE
SOT563
5
PLT_RESET_L
=PP1V5_S3_MEMRESET
CPUMEM_S0
0.1UF
10%
16V
X7R-CERM
0402
OUT
OUT
IN
7
MEM_RESET_L
72
6 8
8
18 24
17 45 73
12
D
1V5 S0 "PGOOD" for CPU
=PP3V3_S5_CPU_VCCDDR
7
PM_MEM_PWRGD pull-up to CPU VTT rail is on CPU page
=PP1V5_S3_CPU_VCCDDR
7
10 12 15
R2820
27.4K
1/16W
MF-LF
R2821
33.2K
1/16W
MF-LF
1%
402
1%
402
1
2
P1V5_S0_DIV
1
2
NO STUFF
C2820
0.001UF
1
R2822
10K
5%
1/16W
MF-LF
402
2
PM_MEM_PWRGD_L
3
CRITICAL
Q2820
5
DMB53D0UV
SOT-563
1
20%
50V
2
CERM
402
4
CRITICAL
G
2
PM_MEM_PWRGD
6
D
Q2820
DMB53D0UV
SOT-563
S
1
10 17 78
OUT
C
MEMVTT Clamp
Ensures CKE signals are held low in S3
=PPVTT_S0_VTTCLAMP
7
=PP5V_S3_MEMRESET
7
26
27 29
OUT
=DDRVTT_EN
8
67
IN
CPUMEM_S0
CPUMEM_S0
Q2850
SSM6N37FEAPE
SOT563
R2851
100K
1/16W
MF-LF
5
1
5%
402
2
3
D
SG
4
SSM6N37FEAPE
VTTCLAMP_EN
NO STUFF
CPUMEM_S0
Q2850
C2851
0.001UF
20%
50V
CERM
402
SOT563
2
1
2
6
D
SG
1
CPUMEM_S0
VTTCLAMP_L
1
R2850
10
75mA max load @ 0.75V
5%
60mW max power
1/10W
MF-LF
603
2
SYNC_MASTER=K90I_MLB SYNC_DATE=02/15/2011
PAGE TITLE
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
CPU Memory S3 Support
Apple Inc.
R
DRAWING NUMBER
REVISION
BRANCH
PAGE
SHEET
051-9058
28 OF 109
6.0.0
26 OF 86
SIZE
B
A
D
124578
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